Segmentation fault related to "bind" construct

[YikeZhou]

When I tried to read the SystemVerilog code below, I got a segmentation fault without any error message. Since it contains the non-synthesizable language construct, bind, I guess the situation is similar to #2230.

Removing the bind construct at the end of the code made the segmentation fault disappear.

Version

Latest release (2024-03-13-d844d8d)
with Yosys 0.36+58 (git sha1 ea7818d31, clang 14.0.6 -fPIC -Os)

Reproduction Steps

Please consider this example design.sv. (I reduced it a bit.)

module ADD_SUB(
  input            clk,
  input [7:0]      a0,
  input [7:0]      b0,
  input            doAdd0,
  output reg [8:0] result0
);

  always @ (posedge clk)
    begin
      if (doAdd0)
        result0 <= a0 + b0;
      else
        result0 <= a0 - b0;
    end

endmodule: ADD_SUB

interface add_sub_if(
  input bit clk,
  input [7:0] a,
  input [7:0] b,
  input       doAdd,
  input [8:0] result
);

  clocking cb @(posedge clk);
    output    a;
    output    b;
    output    doAdd;
    input     result;
  endclocking

endinterface: add_sub_if

bind ADD_SUB add_sub_if add_sub_if0(
  .clk(clk),
  .a(a0),
  .b(b0),
  .doAdd(doAdd0),
  .result(result0)
);

Run command:

yosys -p "plugin -i systemverilog; read_systemverilog design.sv"

Got:

 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2020  Claire Xenia Wolf <[email protected]>         |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.36+58 (git sha1 ea7818d31, clang 14.0.6 -fPIC -Os)


-- Running command `plugin -i systemverilog; read_systemverilog design.sv' --

1. Executing Verilog with UHDM frontend.
[INF:CM0023] Creating log file "/tmp/slpp_all/surelog.log".
[INF:CP0300] Compilation...
[INF:CP0303] /tmp/design.sv:1:1: Compile module "work@ADD_SUB".
[INF:CP0304] /tmp/design.sv:19:1: Compile interface "work@add_sub_if".
[INF:CP0302] Compile class "work@mailbox".
[INF:CP0302] Compile class "work@process".
[INF:CP0302] Compile class "work@semaphore".
[INF:EL0526] Design Elaboration...
Segmentation fault (core dumped)

[alaindargelas]

@YikeZhou

1. SV Interfaces are not supported at all by Synlig
2. Surelog cores dump as binding interfaces to modules is not supported, binding modules to modules is. I could fix the core dump, but since point 1) there is no point, Synlig will not do anything with the interface.
   If that is a feature that you would like to see being developed, please fund this project. There are other issues filed by other users about the Interface support in Synlig, it's all about funding the development.