parser refuses bit-selection of concatenation

[matlupi]

Describe the bug

The code below raises an error but is valid according to the LMR

To Reproduce

class test;
  bit [31:0] pattern;
  constraint pattern_c {
    foreach (pattern[i]) if (i!=0) if (i<16) {pattern[15:0],pattern[15:0]}[i+:16] != pattern[15:0];
  }
endclass

Called with

> verible-verilog-lint test.sv

Version (to be tried on a newer version)

> verible-verilog-lint --version
v0.0-3481-gc517d611
Commit    2024-01-05
Built    2024-01-05T17:03:26Z

Actual behavior:

Reject valid syntax by returning an error.
The problem is the selection of the concatenation.

> verible-verilog-lint test.sv
test.sv:4:75: syntax error at token "["
test.sv:5:3: syntax error at token "}"

Expected behavior

As indicated in LRM 11.4.12

One or more bits of a concatenation can be selected as if the concatenation were a packed array with the range [n-1:0]. 

[matlupi]

Same problem observed with latest version available.
If I remove the bit-selection, the code is accepted.

Version

> verible-verilog-lint --version
v0.0-3756-gda9a0f8c
Commit    2024-08-23
Built    2024-08-24T03:49:26Z