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The following code is valid SystemVerilog (confirmed here):
package test_pkg; virtual class Class; pure virtual function automatic void func1(); pure virtual function automatic void func2(); endclass endpackage
The linter erroneously flags the second function declaration as invalid syntax.
It appears that the linter is assuming that every function will have an endfunction, but this is not true for pure virtual functions.
function
endfunction
The text was updated successfully, but these errors were encountered:
Thank you for your report. In language specification, automatic is not allowed in pure virtual function.
automatic
class_method ::= pure virtual { class_item_qualifier } method_prototype ; method_prototype ::= function_prototype function_prototype ::= function data_type_or_void function_identifier [ ( [ tf_port_list ] ) ]
I know some tools allow this invalid syntax, but svls check it strictly for interoperability.
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The following code is valid SystemVerilog (confirmed here):
The linter erroneously flags the second function declaration as invalid syntax.
It appears that the linter is assuming that every
function
will have anendfunction
, but this is not true for pure virtual functions.The text was updated successfully, but these errors were encountered: