From a129cca3e22daf4b07a378e80cdfd26cfe30025f Mon Sep 17 00:00:00 2001
From: Nils Ponsard <nilsponsard@gmail.com>
Date: Mon, 28 Feb 2022 10:54:53 +0100
Subject: [PATCH 01/12] unit tests

---
 src/main.rs | 29 +++++++++++++++++++++++++++++
 1 file changed, 29 insertions(+)

diff --git a/src/main.rs b/src/main.rs
index 41e96c2..c90dc27 100644
--- a/src/main.rs
+++ b/src/main.rs
@@ -100,4 +100,33 @@ mod tests {
         assert_eq!(insn.op0, 1);
         assert_eq!(insn.op1, 3);
     }
+    
+    #[test]
+    fn test_instruction_disassemble_xor_r1_r3() {
+        let insn_bytes: u32 = 0x1843;
+        let insn = Instruction::disassemble(insn_bytes);
+
+        assert_eq!(insn.opcode, OpCode::XOR);
+        assert_eq!(insn.op0, 1);
+        assert_eq!(insn.op1, 3);
+    }
+    #[test]
+    fn test_instruction_disassemble_ldw_r1_r3() {
+        let insn_bytes: u32 = 0x1840;
+        let insn = Instruction::disassemble(insn_bytes);
+
+        assert_eq!(insn.opcode, OpCode::LDW);
+        assert_eq!(insn.op0, 1);
+        assert_eq!(insn.op1, 3);
+    }
+
+    #[test]
+    fn test_instruction_disassemble_stw_r1_r3() {
+        let insn_bytes: u32 = 0x1841;
+        let insn = Instruction::disassemble(insn_bytes);
+
+        assert_eq!(insn.opcode, OpCode::STW);
+        assert_eq!(insn.op0, 1);
+        assert_eq!(insn.op1, 3);
+    }
 }

From 8ebd523653ed5695f18ca3dfafa91d7859f7030d Mon Sep 17 00:00:00 2001
From: Nils Ponsard <nilsponsard@gmail.com>
Date: Mon, 28 Feb 2022 11:06:22 +0100
Subject: [PATCH 02/12] implement shift

---
 src/main.rs | 22 +++++++++++++++++++++-
 1 file changed, 21 insertions(+), 1 deletion(-)

diff --git a/src/main.rs b/src/main.rs
index c90dc27..1981da9 100644
--- a/src/main.rs
+++ b/src/main.rs
@@ -28,6 +28,8 @@ enum OpCode {
     STW = 0x01,
     ADD = 0x02,
     XOR = 0x03,
+    SHR = 0x04,
+    SHL = 0x05,
 }
 
 impl OpCode {
@@ -37,6 +39,8 @@ impl OpCode {
             0x01 => OpCode::STW,
             0x02 => OpCode::ADD,
             0x03 => OpCode::XOR,
+            0x04 => OpCode::SHR,
+            0x05 => OpCode::SHL,
             _ => panic!("Unknown opcode {:?}", opcode),
         }
     }
@@ -48,6 +52,20 @@ fn add(op0: u32, op1: u32) -> u32 {
 fn xor(op0: u32, op1: u32) -> u32 {
     op0 ^ op1
 }
+/**
+ * Shift right operation. op1 is the number of bits to shift on op0.
+ */
+fn shr(op0: u32, op1: u32) -> u32 {
+    op0 >> op1
+}
+
+/**
+ * Shift right operation. op1 is the number of bits to shift on op0.
+ */
+fn shl(op0: u32, op1: u32) -> u32 {
+    op0 << op1
+}
+
 
 fn main() {
     // ADD R1, R3 -> Opcode is 2 (ADD), op0 is 1 (R1) and op1 is 3 (R3)
@@ -78,6 +96,8 @@ fn main() {
     match decoded_instruction.opcode {
         OpCode::ADD => r1 = add(r1, r3),
         OpCode::XOR => r1 = xor(r1, r3),
+        OpCode::SHR => r1 = shr(r1, r3),
+        OpCode::SHL => r1 = shl(r1, r3),
         _ => panic!("Unknown opcode {:?}", decoded_instruction.opcode),
     }
 
@@ -100,7 +120,7 @@ mod tests {
         assert_eq!(insn.op0, 1);
         assert_eq!(insn.op1, 3);
     }
-    
+
     #[test]
     fn test_instruction_disassemble_xor_r1_r3() {
         let insn_bytes: u32 = 0x1843;

From 2231ce4afbfbdcc024a3da11898758f713805678 Mon Sep 17 00:00:00 2001
From: Nils Ponsard <nilsponsard@gmail.com>
Date: Mon, 28 Feb 2022 11:10:15 +0100
Subject: [PATCH 03/12] implement dissasemble tests

---
 src/main.rs | 21 ++++++++++++++++++++-
 1 file changed, 20 insertions(+), 1 deletion(-)

diff --git a/src/main.rs b/src/main.rs
index 1981da9..e33e735 100644
--- a/src/main.rs
+++ b/src/main.rs
@@ -60,7 +60,7 @@ fn shr(op0: u32, op1: u32) -> u32 {
 }
 
 /**
- * Shift right operation. op1 is the number of bits to shift on op0.
+ * Shift left operation. op1 is the number of bits to shift on op0.
  */
 fn shl(op0: u32, op1: u32) -> u32 {
     op0 << op1
@@ -148,5 +148,24 @@ mod tests {
         assert_eq!(insn.opcode, OpCode::STW);
         assert_eq!(insn.op0, 1);
         assert_eq!(insn.op1, 3);
+    }    #[test]
+    
+    fn test_instruction_disassemble_shr_r1_r3() {
+        let insn_bytes: u32 = 0x1844;
+        let insn = Instruction::disassemble(insn_bytes);
+
+        assert_eq!(insn.opcode, OpCode::SHR);
+        assert_eq!(insn.op0, 1);
+        assert_eq!(insn.op1, 3);
+    }
+
+    #[test]
+    fn test_instruction_disassemble_shl_r1_r3() {
+        let insn_bytes: u32 = 0x1845;
+        let insn = Instruction::disassemble(insn_bytes);
+
+        assert_eq!(insn.opcode, OpCode::SHL);
+        assert_eq!(insn.op0, 1);
+        assert_eq!(insn.op1, 3);
     }
 }

From 0af3fa5c4017945828c9b40e8bf39c53bd57df34 Mon Sep 17 00:00:00 2001
From: Nils Ponsard <nilsponsard@gmail.com>
Date: Mon, 28 Feb 2022 11:12:54 +0100
Subject: [PATCH 04/12] implement operation tests for shift

---
 src/main.rs | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/src/main.rs b/src/main.rs
index e33e735..439a582 100644
--- a/src/main.rs
+++ b/src/main.rs
@@ -168,4 +168,21 @@ mod tests {
         assert_eq!(insn.op0, 1);
         assert_eq!(insn.op1, 3);
     }
+
+
+    #[test]
+    fn test_shift_right_operation() {
+        let op0: u32 = 0xFF;
+        let op1: u32 = 1;
+        let result = super::shr(op0, op1);
+        assert_eq!(result, 0x7F);
+    }
+
+    #[test]
+    fn test_shift_left_operation() {
+        let op0: u32 = 0x01;
+        let op1: u32 = 1;
+        let result = super::shl(op0, op1);
+        assert_eq!(result, 0x02);
+    }
 }

From 567d627731a62146007ec7bc9285ad45fbd62c0d Mon Sep 17 00:00:00 2001
From: Nils Ponsard <nilsponsard@gmail.com>
Date: Mon, 28 Feb 2022 11:19:51 +0100
Subject: [PATCH 05/12] doc

---
 src/main.rs | 14 ++++++++++----
 1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/src/main.rs b/src/main.rs
index 439a582..5deec8e 100644
--- a/src/main.rs
+++ b/src/main.rs
@@ -45,13 +45,21 @@ impl OpCode {
         }
     }
 }
+
+/**
+ * Add operation between op0 and op1.
+ */
 fn add(op0: u32, op1: u32) -> u32 {
     op0 + op1
 }
 
+/**
+ * Xor operation between op0 and op1.
+ */
 fn xor(op0: u32, op1: u32) -> u32 {
     op0 ^ op1
 }
+
 /**
  * Shift right operation. op1 is the number of bits to shift on op0.
  */
@@ -66,7 +74,6 @@ fn shl(op0: u32, op1: u32) -> u32 {
     op0 << op1
 }
 
-
 fn main() {
     // ADD R1, R3 -> Opcode is 2 (ADD), op0 is 1 (R1) and op1 is 3 (R3)
     // The first 6 bits of the instruction are the opcode (2): 0b000010
@@ -148,8 +155,8 @@ mod tests {
         assert_eq!(insn.opcode, OpCode::STW);
         assert_eq!(insn.op0, 1);
         assert_eq!(insn.op1, 3);
-    }    #[test]
-    
+    }
+    #[test]
     fn test_instruction_disassemble_shr_r1_r3() {
         let insn_bytes: u32 = 0x1844;
         let insn = Instruction::disassemble(insn_bytes);
@@ -169,7 +176,6 @@ mod tests {
         assert_eq!(insn.op1, 3);
     }
 
-
     #[test]
     fn test_shift_right_operation() {
         let op0: u32 = 0xFF;

From 442713806031fa02faa3811577b18b469a3bef67 Mon Sep 17 00:00:00 2001
From: Nils Ponsard <nilsponsard@gmail.com>
Date: Mon, 28 Feb 2022 11:20:39 +0100
Subject: [PATCH 06/12] add more tests

---
 src/main.rs | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/src/main.rs b/src/main.rs
index 5deec8e..3ca7b73 100644
--- a/src/main.rs
+++ b/src/main.rs
@@ -191,4 +191,20 @@ mod tests {
         let result = super::shl(op0, op1);
         assert_eq!(result, 0x02);
     }
+
+    #[test]
+    fn test_add_operation() {
+        let op0: u32 = 0x01;
+        let op1: u32 = 0x02;
+        let result = super::add(op0, op1);
+        assert_eq!(result, 0x03);
+    }
+
+    #[test]
+    fn test_xor_operation() {
+        let op0: u32 = 0x01;
+        let op1: u32 = 0x02;
+        let result = super::xor(op0, op1);
+        assert_eq!(result, 0x03);
+    }
 }

From c194f395b4268792d88302cf604e2b7a899532d2 Mon Sep 17 00:00:00 2001
From: Nils Ponsard <nilsponsard@gmail.com>
Date: Mon, 28 Feb 2022 11:23:27 +0100
Subject: [PATCH 07/12] add overflow test

---
 src/main.rs | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/src/main.rs b/src/main.rs
index 3ca7b73..851e47f 100644
--- a/src/main.rs
+++ b/src/main.rs
@@ -192,6 +192,14 @@ mod tests {
         assert_eq!(result, 0x02);
     }
 
+    #[test]
+    #[should_panic]
+    fn test_shift_left_overflow_operation() {
+        let op0: u32 = 0xFF;
+        let op1: u32 = 0xFF;
+        super::shl(op0, op1);
+    }
+
     #[test]
     fn test_add_operation() {
         let op0: u32 = 0x01;

From 4f2a211f420c2c3227f623de1435ffe08c6648ad Mon Sep 17 00:00:00 2001
From: Nils Ponsard <nilsponsard@gmail.com>
Date: Mon, 28 Feb 2022 11:29:25 +0100
Subject: [PATCH 08/12] underflow test

---
 src/main.rs | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/src/main.rs b/src/main.rs
index 851e47f..016750d 100644
--- a/src/main.rs
+++ b/src/main.rs
@@ -200,6 +200,14 @@ mod tests {
         super::shl(op0, op1);
     }
 
+    #[test]
+    #[should_panic]
+    fn test_shift_right_underflow_operation() {
+        let op0: u32 = 0x01;
+        let op1: u32 = 0xFF;
+        super::shr(op0, op1);
+    }
+
     #[test]
     fn test_add_operation() {
         let op0: u32 = 0x01;

From 1457cd213f772a20888268ca651a21a171846d57 Mon Sep 17 00:00:00 2001
From: Nils Ponsard <nilsponsard@gmail.com>
Date: Mon, 28 Feb 2022 11:40:59 +0100
Subject: [PATCH 09/12] cli

---
 Cargo.toml  |  1 +
 src/main.rs | 30 +++++++++++++++++++++++++++++-
 2 files changed, 30 insertions(+), 1 deletion(-)

diff --git a/Cargo.toml b/Cargo.toml
index 869fecd..110d72b 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -7,3 +7,4 @@ edition = "2018"
 # See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html
 
 [dependencies]
+clap = { version = "3.1.2", features = ["derive"] }
\ No newline at end of file
diff --git a/src/main.rs b/src/main.rs
index 016750d..1bc322a 100644
--- a/src/main.rs
+++ b/src/main.rs
@@ -1,3 +1,6 @@
+use clap::Parser;
+
+
 #[derive(Debug)]
 struct Instruction {
     opcode: OpCode,
@@ -74,7 +77,28 @@ fn shl(op0: u32, op1: u32) -> u32 {
     op0 << op1
 }
 
+#[derive(Parser, Debug)]
+#[clap(author, version, about, long_about = None)]
+struct Args {
+    /// Name of the person to greet
+    #[clap(short, long)]
+    instruction: String,
+
+}
+
+
+
 fn main() {
+    
+    // parse
+    let args = Args::parse();
+
+
+
+
+
+
+
     // ADD R1, R3 -> Opcode is 2 (ADD), op0 is 1 (R1) and op1 is 3 (R3)
     // The first 6 bits of the instruction are the opcode (2): 0b000010
     // Bits 6 to 10 are for op0 (1): 0b000001
@@ -85,7 +109,11 @@ fn main() {
     // 0001 1000 0100 0010
     //  1     8   4    2
     // 0b0001100001000010 = 0x1842
-    let insn: u32 = 0x1842;
+
+
+    let without_prefix = args.instruction.trim_start_matches("0x");
+
+    let insn: u32 = u32::from_str_radix(without_prefix, 16).unwrap();
     let mut r1: u32 = 20;
     let r3: u32 = 12;
 

From 5dd476897e3f431abe73cf41e2c42d0caba19a74 Mon Sep 17 00:00:00 2001
From: Nils Ponsard <nilsponsard@gmail.com>
Date: Mon, 28 Feb 2022 11:43:08 +0100
Subject: [PATCH 10/12] comments

---
 Cargo.lock  | 233 ++++++++++++++++++++++++++++++++++++++++++++++++++++
 src/main.rs |  19 ++---
 2 files changed, 239 insertions(+), 13 deletions(-)

diff --git a/Cargo.lock b/Cargo.lock
index d8530d9..7c1d572 100644
--- a/Cargo.lock
+++ b/Cargo.lock
@@ -1,5 +1,238 @@
 # This file is automatically @generated by Cargo.
 # It is not intended for manual editing.
+version = 3
+
+[[package]]
+name = "atty"
+version = "0.2.14"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "d9b39be18770d11421cdb1b9947a45dd3f37e93092cbf377614828a319d5fee8"
+dependencies = [
+ "hermit-abi",
+ "libc",
+ "winapi",
+]
+
+[[package]]
+name = "autocfg"
+version = "1.1.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "d468802bab17cbc0cc575e9b053f41e72aa36bfa6b7f55e3529ffa43161b97fa"
+
+[[package]]
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+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "bef38d45163c2f1dde094a7dfd33ccf595c92905c8f8f4fdc18d06fb1037718a"
+
+[[package]]
+name = "clap"
+version = "3.1.2"
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+checksum = "5177fac1ab67102d8989464efd043c6ff44191b1557ec1ddd489b4f7e1447e77"
+dependencies = [
+ "atty",
+ "bitflags",
+ "clap_derive",
+ "indexmap",
+ "lazy_static",
+ "os_str_bytes",
+ "strsim",
+ "termcolor",
+ "textwrap",
+]
+
+[[package]]
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+ "heck",
+ "proc-macro-error",
+ "proc-macro2",
+ "quote",
+ "syn",
+]
+
 [[package]]
 name = "do-core1"
 version = "0.1.0"
+dependencies = [
+ "clap",
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+
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+
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+[[package]]
+name = "winapi-util"
+version = "0.1.5"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "70ec6ce85bb158151cae5e5c87f95a8e97d2c0c4b001223f33a334e3ce5de178"
+dependencies = [
+ "winapi",
+]
+
+[[package]]
+name = "winapi-x86_64-pc-windows-gnu"
+version = "0.4.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "712e227841d057c1ee1cd2fb22fa7e5a5461ae8e48fa2ca79ec42cfc1931183f"
diff --git a/src/main.rs b/src/main.rs
index 1bc322a..02768e2 100644
--- a/src/main.rs
+++ b/src/main.rs
@@ -1,6 +1,5 @@
 use clap::Parser;
 
-
 #[derive(Debug)]
 struct Instruction {
     opcode: OpCode,
@@ -83,22 +82,12 @@ struct Args {
     /// Name of the person to greet
     #[clap(short, long)]
     instruction: String,
-
 }
 
-
-
 fn main() {
-    
-    // parse
+    // parse arguments
     let args = Args::parse();
 
-
-
-
-
-
-
     // ADD R1, R3 -> Opcode is 2 (ADD), op0 is 1 (R1) and op1 is 3 (R3)
     // The first 6 bits of the instruction are the opcode (2): 0b000010
     // Bits 6 to 10 are for op0 (1): 0b000001
@@ -110,10 +99,12 @@ fn main() {
     //  1     8   4    2
     // 0b0001100001000010 = 0x1842
 
+    // parse instruction
 
     let without_prefix = args.instruction.trim_start_matches("0x");
+    let insn: u32 = u32::from_str_radix(without_prefix, 16).unwrap_or(0);
 
-    let insn: u32 = u32::from_str_radix(without_prefix, 16).unwrap();
+    // init registers
     let mut r1: u32 = 20;
     let r3: u32 = 12;
 
@@ -128,6 +119,8 @@ fn main() {
         decoded_instruction
     );
 
+    // we currently don’t manage registers, so we only use r1 and r3
+
     match decoded_instruction.opcode {
         OpCode::ADD => r1 = add(r1, r3),
         OpCode::XOR => r1 = xor(r1, r3),

From b7781caba71935661513a8566e3c962768edf83e Mon Sep 17 00:00:00 2001
From: Nils Ponsard <nilsponsard@gmail.com>
Date: Mon, 28 Feb 2022 11:53:47 +0100
Subject: [PATCH 11/12] example

---
 src/main.rs | 30 ++++++++++++++++++------------
 1 file changed, 18 insertions(+), 12 deletions(-)

diff --git a/src/main.rs b/src/main.rs
index 02768e2..2a4ce06 100644
--- a/src/main.rs
+++ b/src/main.rs
@@ -48,30 +48,36 @@ impl OpCode {
     }
 }
 
-/**
- * Add operation between op0 and op1.
- */
+/// Add operation between op0 and op1.
 fn add(op0: u32, op1: u32) -> u32 {
     op0 + op1
 }
 
-/**
- * Xor operation between op0 and op1.
- */
+/// Xor operation between op0 and op1.
 fn xor(op0: u32, op1: u32) -> u32 {
     op0 ^ op1
 }
 
-/**
- * Shift right operation. op1 is the number of bits to shift on op0.
- */
+
+/// Shift right operation. op1 is the number of bits to shift on op0. 
+/// 
+/// # Example
+/// 
+/// ```
+/// assert_eq!(0x02, shr(0x04, 1));
+/// ```
+/// 
 fn shr(op0: u32, op1: u32) -> u32 {
     op0 >> op1
 }
 
-/**
- * Shift left operation. op1 is the number of bits to shift on op0.
- */
+/// Shift left operation. op1 is the number of bits to shift on op0.
+/// 
+/// # Example
+/// 
+/// ```
+/// assert_eq!(0x08, shr(0x04, 1));
+/// ```
 fn shl(op0: u32, op1: u32) -> u32 {
     op0 << op1
 }

From c98f90b24a497ee21e1cd4a418566f2c3c8ff952 Mon Sep 17 00:00:00 2001
From: Nils Ponsard <nilsponsard@gmail.com>
Date: Mon, 28 Feb 2022 13:24:51 +0100
Subject: [PATCH 12/12] fix comments

---
 src/main.rs | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/src/main.rs b/src/main.rs
index 2a4ce06..bdd9b6a 100644
--- a/src/main.rs
+++ b/src/main.rs
@@ -82,10 +82,13 @@ fn shl(op0: u32, op1: u32) -> u32 {
     op0 << op1
 }
 
+
+
+/// Arguments to pass to the program.
 #[derive(Parser, Debug)]
 #[clap(author, version, about, long_about = None)]
 struct Args {
-    /// Name of the person to greet
+    /// The instruction to disassemble and execute.
     #[clap(short, long)]
     instruction: String,
 }