FPGA.bib

% ===============================================================
%                    FPGA Industry  
% ===============================================================
@misc{FPGA-HME,
    title        = {{Hercules Microelectronics Co.}},
    howpublished = "\url{http://hercules-micro.com}",
}
@misc{FPGA-Xilinx,
    title        = {{Xilinx Inc.}},
    howpublished = "\url{http://www.xilinx.com}",
}
@misc{FPGA-Xilinx-ultraFast,
    title        = {{UltraFast Design Methodology Guide for the Vivado Design Suite}},
    howpublished = "\url{https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_1/ug949-vivado-design-methodology.pdf}",
}
@misc{FPGA-iSmartDNN,
    title        = {{iSmartDNN}},
    howpublished = "\url{https://github.com/onioncc/iSmartDNN}",
}



% ===============================================================
%                      HLS 
% ===============================================================
@article{HLS-TCAD2016-Nane,
    title     = {A survey and evaluation of {FPGA} high-level synthesis tools},
    author    = {Nane, Razvan and Sima, Vlad-Mihai and Pilato, Christian and Choi, Jongsok and Fort, Blair and Canis, Andrew and Chen, Yu Ting and Hsiao, Hsuan and Brown, Stephen and Ferrandi, Fabrizio and others},
    journal   = tcad,
    volume    = {35},
    number    = {10},
    pages     = {1591--1604},
    year      = {2016},
    publisher = {IEEE},
}
@inproceedings{HLS-ISLPED2003-Chen,
    title     = {Low-power high-level synthesis for {FPGA} architectures},
    author    = {Chen, Deming and Cong, Jason and Fan, Yiping},
    booktitle = islped,
    pages     = {134--139},
    year      = {2003},
}
@inproceedings{HLS-DATE2021-Sun,
    title     = {Correlated Multi-objective Multi-fidelity Optimization for HLS Directives Design},
    author    = {Qi Sun and Tinghuan Chen and Siting Liu and Jin Miao and Jianli Chen and Hao Yu and Bei Yu},
    booktitle = date,
    year      = {2021},
}

% ===============================================================
%                      FPGA-DNN
% ===============================================================
@inproceedings{FPGA-ASPDAC2016-Motamedi,
    title     = {Design space exploration of {FPGA}-based deep convolutional neural networks},
    author    = {Motamedi, Mohammad and Gysel, Philipp and Akella, Venkatesh and Ghiasi, Soheil},
    booktitle = aspdac,
    pages     = {575--580},
    year      = {2016},
}
@inproceedings{FPGA-DAC2017-Wei,
    title     = {Automated systolic array architecture synthesis for high throughput {CNN} inference on {FPGAs}},
    author    = {Wei, Xuechao and Yu, Cody Hao and Zhang, Peng and Chen, Youxiang and Wang, Yuxin and Hu, Han and Liang, Yun and Cong, Jason},
    booktitle = dac,
    pages     = {29:1--29:6},
    year      = {2017},
}
@inproceedings{FPGA-FPGA2017-Ma,
    title     = {Optimizing loop operation and dataflow in {FPGA} acceleration of deep convolutional neural networks},
    author    = {Ma, Yufei and Cao, Yu and Vrudhula, Sarma and Seo, Jae-sun},
    booktitle = fpga,
    pages     = {45--54},
    year      = {2017},
}
@article{FPGA-TVLSI2018-Ma,
    title   = {Optimizing the Convolution Operation to Accelerate Deep Neural Networks on {FPGA}},
    author  = {Ma, Yufei and Cao, Yu and Vrudhula, Sarma and Seo, Jae-sun},
    journal = tvlsi,
    year    = {2018},
    volume  = {26},
    number  = {7},
    pages   = {1354--1367},
}
@inproceedings{FPGA-ICCAD2018-DNNBuilder,
    title     = {{DNNBuilder}: an automated tool for building high-performance {DNN} hardware accelerators for {FPGAs}},
    author    = {Zhang, Xiaofan and Wang, Junsong and Zhu, Chao and Lin, Yonghua and Xiong, Jinjun and Hwu, Wen-mei and Chen, Deming},
    booktitle = iccad,
    pages     = {56:1--56:8},
    year      = {2018},
}
@inproceedings{FPGA-FPGA2018-Moss,
    title     = {A customizable matrix multiplication framework for the {Intel HARPv2 Xeon+FPGA} platform: A deep learning case study},
    author    = {Moss, Duncan JM and Krishnan, Srivatsan and Nurvitadhi, Eriko and Ratuszniak, Piotr and Johnson, Chris and Sim, Jaewoong and Mishra, Asit and Marr, Debbie and Subhaschandra, Suchit and Leong, Philip HW},
    booktitle = fpga,
    pages     = {107--116},
    year      = {2018},
}
@inproceedings{FPGA-FPGA2019-Synetgy,
  title     = {Synetgy: Algorithm-hardware co-design for convnet accelerators on embedded {FPGAs}},
  author    = {Yang, Yifan and Huang, Qijing and Wu, Bichen and Zhang, Tianjun and Ma, Liang and Gambardella, Giulio and Blott, Michaela and Lavagno, Luciano and Vissers, Kees and Wawrzynek, John and others},
  booktitle = fpga,
  pages     = {23--32},
  year      = {2019},
}
@inproceedings{FPGA-DAC2019-Wei,
    title     = {Overcoming Data Transfer Bottlenecks in FPGA-based DNN Accelerators via Layer Conscious Memory Management},
    author    = {Wei, Xuechao and Liang, Yun and Cong, Jason},
    booktitle = dac,
    pages     = {1--6},
    year      = {2019}
}
@inproceedings{FPGA-ICCAD2019-Sun,
    title     = {Power-Driven {DNN} Dataflow Optimization on {FPGA}},
    author    = {Sun, Qi and Chen, Tinghuan and Miao, Jin and Yu, Bei},
    booktitle = iccad,
    pages     = {1--7},
    year      = {2019},
}

% ===============================================================
%                 FPGA Place & Route
% ===============================================================
% ==== FPGA P&R
@article{FPGA-TRETS2014-VTR,
    title     ={{VTR 7.0}: Next generation architecture and {CAD} system for {FPGAs}},
    author    ={Luu, Jason and Goeders, Jeffrey and Wainberg, Michael and Somerville, Andrew and Yu, Thien and Nasartschuk, Konstantin and Nasr, Miad and Wang, Sen and Liu, Tim and Ahmed, Nooruddin and others},
    journal   =trets,
    volume    ={7},
    number    ={2},
    pages     ={6},
    year      ={2014},
    publisher ={ACM},
}
@inproceedings{FPGA-ICCAD2017-Chen,
    title     = {FPGA placement and routing},
    author    = {Chen, Shih-Chun and Chang, Yao-Wen},
    booktitle = iccad,
    pages     = {914--921},
    year      = {2017},
}
% ==== FPGA Placement
%{{{
@article{FPGA-TCAD2005-Maidee,
    title     = {Timing-driven partitioning-based placement for island style {FPGAs}},
    author    = {Maidee, Pongstorn and Ababei, Cristinel and Bazargan, Kia},
    journal   = tcad,
    volume    = {24},
    number    = {3},
    pages     = {395--406},
    year      = {2005},
    publisher = {IEEE},
}
@inproceedings{FPGA-FPL2005-Xu,
    title     = {{QPF}: efficient quadratic placement for {FPGAs}},
    author    = {Xu, Yonghong and Khalid, Mohammed A.~S.},
    booktitle = fpl,
    pages     = {555--558},
    year      = {2005},
}
@inproceedings{FPGA-ICCAD2006-Tom,
    title     = {{Un/DoPack}: re-clustering of large system-on-chip designs with interconnect variation for low-cost {FPGAs}},
    author    = {Tom, Marvin and Leong, David and Lemieux, Guy},
    booktitle = iccad,
    pages     = {680--687},
    year      = {2006},
}
@inproceedings{FPGA-FPL2007-Chen,
    title     = {Improving timing-driven {FPGA} packing with physical information},
    author    = {Chen, Doris T and Vorwerk, Kristofer and Kennings, Andrew},
    booktitle = fpl,
    pages     = {117--123},
    year      = {2007},
}
@inproceedings{FPGA-ASICON2009-Xie,
    title     = {A New {FPGA} placement algorithm for heterogeneous resources},
    author    = {Xie, Ding and Xu, Jiawei and Lai, Jinmei},
    booktitle = asicon,
    pages     = {742--746},
    year      = {2009},
}
@inproceedings{FPGA-FPGA2011-Wang,
    title     = {Scalable and Deterministic Timing-driven Parallel Placement for {FPGAs}},
    author    = {Wang, Chris C. and Lemieux, Guy G.~F.},
    booktitle = fpga,
    pages     = {153--162},
    year      = {2011},
} 
@article{FPGA-JVLSI2011-Xu,
    title     = {{StarPlace}: A new analytic method for {FPGA} placement},
    author    = {M.~Xu and Gr{\'e}wal, Gary and Areibi, Shawki},
    journal   = jvlsi,
    volume    = {44},
    number    = {3},
    pages     = {192--204},
    year      = {2011},
    publisher = {Elsevier},
}
@inproceedings{FPGA-FPL2012-Gort,
    title     = {Analytical placement for heterogeneous {FPGAs}},
    author    = {Gort, Marcel and Anderson, Jason H.},
    booktitle = fpl,
    pages     = {143--150},
    year      = {2012},
}
@inproceedings{FPGA-DAC2013-Lin,
    title     = {An efficient and effective analytical placer for {FPGAs}},
    author    = {Lin, Tzu-Hen and Banerjee, Pritha and Chang, Yao-Wen},
    booktitle = dac,
    pages     = {10:1--10:6},
    year      = {2013},
}
@inproceedings{FPGA-FPGA2014-Feng,
    title     = {Rent's rule based {FPGA} packing for routability optimization},
    author    = {Feng, Wenyi and Greene, Jonathan and Vorwerk, Kristofer and Pevzner, Val and Kundu, Arun},
    booktitle = fpga,
    pages     = {31--34},
    year      = {2014},
}
@inproceedings{FPGA-ICCAD2014-Chen,
    title     = {Efficient and effective packing and analytical placement for large-scale heterogeneous {FPGAs}},
    author    = {Chen, Yu-Chen and Chen, Sheng-Yen and Chang, Yao-Wen},
    booktitle = iccad,
    pages     = {647--654},
    year      = {2014},
}
@inproceedings{FPGA-DAC2015-Chen,
    title     = {Routing-architecture-aware analytical placement for heterogeneous {FPGAs}},
    author    = {Chen, Sheng-Yen and Chang, Yao-Wen},
    booktitle = dac,
    pages     = {27:1--27:6},
    year      = {2015},
}
@inproceedings{FPGA-ISPD2016-Yang,
    title     = {Routability-Driven {FPGA} Placement Contest},
    author    = {Yang, Stephen and Gayasen, Aman and Mulpuri, Chandra and Reddy, Sainath and Aggarwal, Rajat},
    booktitle = ispd,
    pages     = {139--143},
    year      = {2016},
}
@inproceedings{FPGA-ICCAD2016-Li,
    title     = {{UTPlaceF}: A Routability-driven {FPGA} Placer with Physical and Congestion aware Packing},
    author    = {Li, Wuxi and Dhar, Shounak and Pan, David Z.},
    booktitle = iccad,
    pages     = {66:1--66:7},
    year      = {2016},
}
@inproceedings{FPGA-ICCAD2016-Pui,
    title     = {{RippleFPGA}: A Routability-driven Placement for Large-scale Heterogeneous {FPGAs}},
    author    = {Pui, Chak-Wa and Chen, Gengjie and Chow, Wing-Kai and Lam, Ka-Chun and Kuang, Jian and Tu, Peishan and Zhang, Hang and Young, Evangeline F.~Y. and Yu, Bei},
    booktitle = iccad,
    pages     = {67:1--67:8},
    year      = {2016},
} 
@inproceedings{FPGA-ICCAD2016-Pattison,
    title     = {{GPlace}: A congestion-aware placement tool for UltraScale {FPGAs}},
    author    = {Pattison, Ryan and Abuowaimer, Ziad and Areibi, Shawki and Gr{\'e}wal, Gary and Vannelli, Anthony},
    booktitle = iccad,
    pages     = {68:1--68:7},
    year      = {2016},
}
@inproceedings{FPGA-ISPD2017-Yang,
    title     = {Clock-Aware {FPGA} Placement Contest},
    author    = {Yang, Stephen and Mulpuri, Chandra and Reddy, Sainath and Kalase, Meghraj and Dasasathyan, Srinivasan and Dehkordi, Mehrdad E and Tom, Marvin and Aggarwal, Rajat},
    booktitle = ispd,
    pages     = {159--164},
    year      = {2017},
}
@inproceedings{FPGA-ICCAD2017-Pui,
    title     = {Clock-aware ultrascale FPGA placement with machine learning routability prediction},
    author    = {Pui, Chak-Wa and Chen, Gengjie and Ma, Yuzhe and Young, Evangeline FY and Yu, Bei},
    booktitle = iccad,
    pages     = {929--936},
    year      = {2017},
}
@article{FPGA-TCAD2018-Chen,
    title     = {{RippleFPGA}: Routability-driven simultaneous packing and placement for modern {FPGA}s},
    author    = {Chen, Gengjie and Pui, Chak-Wa and Chow, Wing-Kai and Lam, Ka-Chun and Kuang, Jian and Young, Evangeline FY and Yu, Bei},
    journal   = tcad,
    volume    = {37},
    number    = {10},
    pages     = {2022--2035},
    year      = {2018},
    publisher = {IEEE}
}
%}}}
% ==== FPGA Routing
@article{FPGA-TCAD1996-Alexander,
    title={New performance-driven {FPGA} routing algorithms},
    author={Alexander, Michael J and Robins, Gabriel},
    journal=tcad,
    volume={15},
    number={12},
    pages={1505--1517},
    year={1996},
    publisher={IEEE}
}



% ===============================================================
%                   FPGA Applications
% ===============================================================
@inproceedings{FPGA-FPGA2017-Ling,
    title     = {The Role of {FPGAs} in Deep Learning},
    author    = {Ling, Andrew and Anderson, Jason},
    booktitle = fpga,
    pages     = {3--3},
    year      = {2017},
}
@inproceedings{FPGA-FPGA2017-Constantinides,
    title     = {{FPGAs} in the Cloud},
    author    = {Constantinides, George A.},
    booktitle = fpga,
    pages     = {167--167},
    year      = {2017},
}
@inproceedings{FPGA-FPGA2017-Eriko,
    title       =   {Can {FPGA}s beat {GPU}s in accelerating next-generation deep neural networks?},
    author      =   {Nurvitadhi, Eriko and Venkatesh, Ganesh and Sim, Jaewoong and Marr, Debbie and Huang, Randy and Ong Gee Hock, Jason and Liew, Yeong Tat and Srivatsan, Krishnan and Moss, Duncan and Subhaschandra, Suchit and others},
    booktitle   =   fpga,
    pages       =   {5--14},
    year        =   {2017},
}
@inproceedings{FPGA-ISLPED2016-Schmit,
    title       =   {Dissecting {X}eon+ {FPGA}: Why the integration of {CPU}s and {FPGA}s makes a power difference for the datacenter},
    author      =   {Schmit, Herman and Huang, Randy},
    booktitle   =   islped,
    pages       =   {152--153},
    year        =   {2016},
}