| Accelerator Application | Example | Development Environment | Description |
|---|---|---|---|
| Custom hardware | cl_hello_world | HDK - RTL (Verilog) | Simple getting started example with minimal hardware |
| Custom hardware | cl_dram_dma | HDK - RTL (Verilog) | Demonstrates CL connectivity to the F1 shell and connectivity to/from all DDRs |
| Custom hardware | IP integration example using a GUI - cl_dram_dma_hlx | HLx - Verilog | Demonstrates CL connectivity to the F1 shell and connectivity to/from DRAM using the Vivado IP Integrator GUI |
| Custom hardware | Virtual Ethernet Application | Streaming Data Engine | The Virtual Ethernet framework facilitates streaming Ethernet frames from a network interface (or any source) into the FPGA for processing and back out to some destination. Possible use cases for this include deep packet inspection, software defined networking, stream encryption or compression, and more. |
| Custom hardware | Pipelined Workload Applications - cl_dram_dma_data_retention | HDK SDAccel | Demonstrates how to preserve data in DRAMs while swapping out accelerators. Applications that use a temporal accelerator pipeline can take advantage of this feature to reduce latency between FPGA image swaps |
| High Level Synthesis | Digital Up-Converter - cl_hls_dds_hlx | HLx - C-to-RTL | Demonstrates an example application written in C that is synthesized to RTL (Verilog) |
| Custom Hardware with Software Defined Acceleration | RTL Kernels | Vitis - RTL (Verilog) + C/C++/OpenCL | These examples demonstrate developing new hardware designs (RTL) in a Software Defined workflow |
| Vitis Compression Libraries | File Compression using GZip | Vitis - C/C++/OpenCL | This example demonstrates how to use Vitis Libraries to speed up GZIP compression on an FPGA |
| Vitis BLAS libraries | Matrix Transposer using BLAS | Vitis - C/C++/OpenCL | This example shows how to use Vitis BLAS Libraries to create a Matrix Transposer on an FPGA |
| Vitis Financial libraries | Monte Carlo European Engine | Vitis - C/C++/OpenCL | This example shows how to use Vitis Financial Libraries to accelerate MCEuropean Engine on an FPGA |
| App Note | Description |
|---|---|
| Using PCIe Peer-2-Peer connectivity | This app note shows how to use PCIe P2P connectivity on F1.16XL instances |
| Using PCIM Port | This app note shows how to use the PCIM AXI port to transfer data between card and host memory |
| Using PCIe User Interrupts | This app note describes the basic kernel calls needed for a developer to write a custom interrupt service routine (ISR) and provides an example that demonstrates those calls |
| Using PCIe Write Combining | This app note describes when to use write combining and how to take advantage of write combining in software for a F1 accelerator |