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[chip-test, chip_aes] chip_sw_aes_masking_off #30

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9 tasks
engdoreis opened this issue Feb 12, 2024 · 0 comments
Open
9 tasks

[chip-test, chip_aes] chip_sw_aes_masking_off #30

engdoreis opened this issue Feb 12, 2024 · 0 comments

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@engdoreis
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Test point name

chip_sw_aes_masking_off

Host side component

Rust?

Opentitantool infraestructure implemented

Yes

Silicon Validation (SiVal)

Yes

Emulation targets

  • None
  • CW310
  • Hyperdebug + CW310

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Checklist

Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.

  • Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
  • Device-side (C) component developed
  • Bazel build rules developed
  • Host-side component developed
  • Test added to dvsim nightly regression (and passing at time of checking)
  • For SiVal test cases, test is running relevant FPGA or silicon regression
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