Inquiry Regarding Malfunction of I2S API (i2s_channel_reconfig_std_gpio) (IDFGH-14721)

[illusionkiller]

Build Environment: IDF release-5.4, Windows + VSCode

Test Environment: M5Stack Core2

Test Code Snippet:

esp_codec_dev_handle_t codec_dev = bsp_audio_codec_speaker_init();
i2s_std_gpio_config_t std_gpio_cfg = {
    .mclk = I2S_GPIO_UNUSED, // some codecs may require mclk signal, this example doesn't need it
    .bclk = I2S_GPIO_UNUSED,
    .ws = I2S_GPIO_UNUSED,
    .dout = I2S_GPIO_UNUSED,
    .din = I2S_GPIO_UNUSED,
};
if (codec_dev)
{
    esp_codec_dev_sample_info_t fs = {
        .sample_rate = 44100,
        .channel = 1,
        .bits_per_sample = 16,
    };
    std_gpio_cfg.bclk = GPIO_NUM_12;
    std_gpio_cfg.ws = GPIO_NUM_0;
    std_gpio_cfg.dout = GPIO_NUM_2;
    i2s_channel_disable(bsp_audio_get_codec_tx_channel());
    // ESP_ERROR_CHECK(i2s_channel_reconfig_std_gpio(bsp_audio_get_codec_tx_channel(), &std_gpio_cfg));
    esp_codec_dev_open(codec_dev, &fs);
    esp_codec_dev_set_out_vol(codec_dev, 100);

    extern const unsigned char music[120264];
    unsigned char *buffer = (unsigned char *)calloc(1, 120264);
    memcpy(buffer, music, 120264);
    size_t was_write_length = esp_codec_dev_write(codec_dev, (void *)buffer, 120264);
    ESP_LOGI(TAG, "Write %d bytes to codec!", was_write_length);
    esp_codec_dev_close(codec_dev);
}

Expected Test Result: The presence or absence of the i2s_channel_reconfig_std_gpio API should not affect the normal audio output.
Actual Test Result: When the i2s_channel_reconfig_std_gpio API is uncommented, the audio output becomes abnormal, indicating a potential issue with the API's functionality，and the API does not report any errors.
Note: I have not found any unit tests related to the I2S API, so I am unable to perform additional comparative verification. However, I can confirm that the API call itself is implemented correctly.
Normal and Abnormal Test Logs:

D (1677) i2s_common: tx channel is registered on I2S1 successfully
D (1677) i2s_common: rx channel is registered on I2S1 successfully
D (1677) i2s_common: DMA malloc info: dma_desc_num = 6, dma_desc_buf_size = dma_frame_num * slot_num * data_bit_width = 480
D (1687) i2s_std: Clock division info: [sclk] 160000000 Hz [mdiv] 14 [mclk] 11289600 Hz [bdiv] 8 [bclk] 1411200 Hz
I (1697) i2s_std: i2s_std_set_gpio success
D (1707) i2s_std: The tx channel on I2S1 has been initialized to STD mode successfully
D (1717) i2s_common: i2s tx channel enabled
D (1717) i2s_common: DMA malloc info: dma_desc_num = 6, dma_desc_buf_size = dma_frame_num * slot_num * data_bit_width = 480
D (1727) i2s_std: Clock division info: [sclk] 160000000 Hz [mdiv] 14 [mclk] 11289600 Hz [bdiv] 8 [bclk] 1411200 Hz
I (1737) i2s_std: i2s_std_set_gpio success
D (1737) i2s_std: The rx channel on I2S1 has been initialized to STD mode successfully
I (1747) M5Stack: I2S initialized successfully
I (1757) M5Stack: I2S config: sample_rate=44100, data_bit_width=16, slot_mode=1
I (1757) M5Stack: Set REG 0x94 to 0xf4
I (1507) ili9341: LCD panel create success, version: 1.2.0
I (1647) gpio: GPIO[39]| InputEn: 1| OutputEn: 0| OpenDrain: 0| Pullup: 0| Pulldown: 0| Intr:2
D (1677) i2s_common: tx channel is registered on I2S1 successfully
D (1677) i2s_common: rx channel is registered on I2S1 successfully
D (1677) i2s_common: DMA malloc info: dma_desc_num = 6, dma_desc_buf_size = dma_frame_num * slot_num * data_bit_width = 480
D (1687) i2s_std: Clock division info: [sclk] 160000000 Hz [mdiv] 14 [mclk] 11289600 Hz [bdiv] 8 [bclk] 1411200 Hz
I (1697) i2s_std: i2s_std_set_gpio success
D (1707) i2s_std: The tx channel on I2S1 has been initialized to STD mode successfully
D (1717) i2s_common: i2s tx channel enabled
D (1717) i2s_common: DMA malloc info: dma_desc_num = 6, dma_desc_buf_size = dma_frame_num * slot_num * data_bit_width = 480
D (1727) i2s_std: Clock division info: [sclk] 160000000 Hz [mdiv] 14 [mclk] 11289600 Hz [bdiv] 8 [bclk] 1411200 Hz
I (1737) i2s_std: i2s_std_set_gpio success
D (1737) i2s_std: The rx channel on I2S1 has been initialized to STD mode successfully
I (1747) M5Stack: I2S initialized successfully
I (1757) M5Stack: I2S config: sample_rate=44100, data_bit_width=16, slot_mode=1
I (1757) M5Stack: Set REG 0x94 to 0xf4
I (1647) gpio: GPIO[39]| InputEn: 1| OutputEn: 0| OpenDrain: 0| Pullup: 0| Pulldown: 0| Intr:2
D (1677) i2s_common: tx channel is registered on I2S1 successfully
D (1677) i2s_common: rx channel is registered on I2S1 successfully
D (1677) i2s_common: DMA malloc info: dma_desc_num = 6, dma_desc_buf_size = dma_frame_num * slot_num * data_bit_width = 480
D (1687) i2s_std: Clock division info: [sclk] 160000000 Hz [mdiv] 14 [mclk] 11289600 Hz [bdiv] 8 [bclk] 1411200 Hz
I (1697) i2s_std: i2s_std_set_gpio success
D (1707) i2s_std: The tx channel on I2S1 has been initialized to STD mode successfully
D (1717) i2s_common: i2s tx channel enabled
D (1717) i2s_common: DMA malloc info: dma_desc_num = 6, dma_desc_buf_size = dma_frame_num * slot_num * data_bit_width = 480
D (1727) i2s_std: Clock division info: [sclk] 160000000 Hz [mdiv] 14 [mclk] 11289600 Hz [bdiv] 8 [bclk] 1411200 Hz
I (1737) i2s_std: i2s_std_set_gpio success
D (1737) i2s_std: The rx channel on I2S1 has been initialized to STD mode successfully
I (1747) M5Stack: I2S initialized successfully
I (1757) M5Stack: I2S config: sample_rate=44100, data_bit_width=16, slot_mode=1
I (1757) M5Stack: Set REG 0x94 to 0xf4
I (1697) i2s_std: i2s_std_set_gpio success
D (1707) i2s_std: The tx channel on I2S1 has been initialized to STD mode successfully
D (1717) i2s_common: i2s tx channel enabled
D (1717) i2s_common: DMA malloc info: dma_desc_num = 6, dma_desc_buf_size = dma_frame_num * slot_num * data_bit_width = 480
D (1727) i2s_std: Clock division info: [sclk] 160000000 Hz [mdiv] 14 [mclk] 11289600 Hz [bdiv] 8 [bclk] 1411200 Hz
I (1737) i2s_std: i2s_std_set_gpio success
D (1737) i2s_std: The rx channel on I2S1 has been initialized to STD mode successfully
I (1747) M5Stack: I2S initialized successfully
I (1757) M5Stack: I2S config: sample_rate=44100, data_bit_width=16, slot_mode=1
I (1757) M5Stack: Set REG 0x94 to 0xf4
D (1727) i2s_std: Clock division info: [sclk] 160000000 Hz [mdiv] 14 [mclk] 11289600 Hz [bdiv] 8 [bclk] 1411200 Hz
I (1737) i2s_std: i2s_std_set_gpio success
D (1737) i2s_std: The rx channel on I2S1 has been initialized to STD mode successfully
I (1747) M5Stack: I2S initialized successfully
I (1757) M5Stack: I2S config: sample_rate=44100, data_bit_width=16, slot_mode=1
I (1757) M5Stack: Set REG 0x94 to 0xf4
I (1757) M5Stack: I2S config: sample_rate=44100, data_bit_width=16, slot_mode=1
I (1757) M5Stack: Set REG 0x94 to 0xf4
D (1767) i2s_common: i2s tx channel disabled
E (1767) i2s_common: i2s_channel_disable(1187): the channel has not been enabled yet
I (1777) I2S_IF: channel mode 0 bits:16/16 channel:2 mask:1
D (1777) i2s_std: Clock division info: [sclk] 160000000 Hz [mdiv] 14 [mclk] 11289600 Hz [bdiv] 8 [bclk] 1411200 Hz
I (1787) I2S_IF: STD Mode 1 bits:16/16 channel:2 sample_rate:44100 mask:1
D (1797) i2s_common: i2s tx channel enabled
I (1797) Adev_Codec: Open codec device OK
I (3227) ui_main: Write 0 bytes to codec!
D (3227) i2s_common: i2s tx channel disabled
I (3227) main_task: Returned from app_main()