diff --git a/.circleci/config2.yml b/.circleci/config2.yml
index e6ae87e77f..c3bf2a2706 100644
--- a/.circleci/config2.yml
+++ b/.circleci/config2.yml
@@ -16,7 +16,7 @@ commands:
"arm-gcc": "https://github.com/xpack-dev-tools/arm-none-eabi-gcc-xpack/releases/download/v13.2.1-1.1/xpack-arm-none-eabi-gcc-13.2.1-1.1-linux-x64.tar.gz",
"msp430-gcc": "http://software-dl.ti.com/msp430/msp430_public_sw/mcu/msp430/MSPGCC/9_2_0_0/export/msp430-gcc-9.2.0.50_linux64.tar.bz2",
"riscv-gcc": "https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack/releases/download/v13.2.0-2/xpack-riscv-none-elf-gcc-13.2.0-2-linux-x64.tar.gz",
- "rx-gcc": "https://llvm-gcc-renesas.com/downloads/get.php?f=rx/8.3.0.202004-gnurx/gcc-8.3.0.202004-GNURX-ELF.run",
+ "rx-gcc": "https://github.com/hathach/rx_device/releases/download/0.0.1/gcc-8.3.0.202411-GNURX-ELF.run",
"arm-iar": "https://updates.iar.com/FileStore/STANDARD/001/003/322/cxarm-9.60.3.deb"
}'
toolchain_url=$(echo $TOOLCHAIN_JSON | jq -r '.["<< parameters.toolchain >>"]')
diff --git a/.github/actions/setup_toolchain/action.yml b/.github/actions/setup_toolchain/action.yml
index 8406a812d7..484001cda4 100644
--- a/.github/actions/setup_toolchain/action.yml
+++ b/.github/actions/setup_toolchain/action.yml
@@ -41,7 +41,7 @@ runs:
"arm-clang": "https://github.com/ARM-software/LLVM-embedded-toolchain-for-Arm/releases/download/release-19.1.1/LLVM-ET-Arm-19.1.1-Linux-x86_64.tar.xz",
"msp430-gcc": "http://software-dl.ti.com/msp430/msp430_public_sw/mcu/msp430/MSPGCC/9_2_0_0/export/msp430-gcc-9.2.0.50_linux64.tar.bz2",
"riscv-gcc": "https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack/releases/download/v13.2.0-2/xpack-riscv-none-elf-gcc-13.2.0-2-linux-x64.tar.gz",
- "rx-gcc": "http://gcc-renesas.com/downloads/get.php?f=rx/8.3.0.202004-gnurx/gcc-8.3.0.202004-GNURX-ELF.run"
+ "rx-gcc": "https://github.com/hathach/rx_device/releases/download/0.0.1/gcc-8.3.0.202411-GNURX-ELF.run"
}'
TOOLCHAIN_URL=$(echo $TOOLCHAIN_JSON | jq -r '.["${{ inputs.toolchain }}"]')
echo "toolchain_url=$TOOLCHAIN_URL"
diff --git a/.github/workflows/pre-commit.yml b/.github/workflows/pre-commit.yml
index 530484079e..ed0efd66e8 100644
--- a/.github/workflows/pre-commit.yml
+++ b/.github/workflows/pre-commit.yml
@@ -33,6 +33,8 @@ jobs:
- name: Build Fuzzer
run: |
+ sudo apt install libc++-dev libc++abi-dev
+ clang --version
export CC=clang
export CXX=clang++
fuzz_harness=$(ls -d test/fuzz/device/*/)
diff --git a/.idea/cmake.xml b/.idea/cmake.xml
index 5af6d77224..e4c189251c 100644
--- a/.idea/cmake.xml
+++ b/.idea/cmake.xml
@@ -118,10 +118,13 @@
+
-
-
+
+
+
+
diff --git a/examples/build_system/cmake/cpu/cortex-m85.cmake b/examples/build_system/cmake/cpu/cortex-m85.cmake
new file mode 100644
index 0000000000..30314acbca
--- /dev/null
+++ b/examples/build_system/cmake/cpu/cortex-m85.cmake
@@ -0,0 +1,25 @@
+if (TOOLCHAIN STREQUAL "gcc")
+ set(TOOLCHAIN_COMMON_FLAGS
+ -mthumb
+ -mcpu=cortex-m85
+ -mfloat-abi=hard
+ -mfpu=fpv5-d16
+ )
+ set(FREERTOS_PORT GCC_ARM_CM85_NTZ_NONSECURE CACHE INTERNAL "")
+
+elseif (TOOLCHAIN STREQUAL "clang")
+ set(TOOLCHAIN_COMMON_FLAGS
+ --target=arm-none-eabi
+ -mcpu=cortex-m85
+ -mfpu=fpv5-d16
+ )
+ set(FREERTOS_PORT GCC_ARM_CM85_NTZ_NONSECURE CACHE INTERNAL "")
+
+elseif (TOOLCHAIN STREQUAL "iar")
+ set(TOOLCHAIN_COMMON_FLAGS
+ --cpu cortex-m85
+ --fpu VFPv5_D16
+ )
+ set(FREERTOS_PORT IAR_ARM_CM85_NTZ_NONSECURE CACHE INTERNAL "")
+
+endif ()
diff --git a/examples/build_system/make/cpu/cortex-m85.mk b/examples/build_system/make/cpu/cortex-m85.mk
new file mode 100644
index 0000000000..75e8f3aaf6
--- /dev/null
+++ b/examples/build_system/make/cpu/cortex-m85.mk
@@ -0,0 +1,27 @@
+ifeq ($(TOOLCHAIN),gcc)
+ CFLAGS += \
+ -mthumb \
+ -mcpu=cortex-m85 \
+ -mfloat-abi=hard \
+ -mfpu=fpv5-d16 \
+
+else ifeq ($(TOOLCHAIN),clang)
+ CFLAGS += \
+ --target=arm-none-eabi \
+ -mcpu=cortex-m85 \
+ -mfpu=fpv5-d16 \
+
+else ifeq ($(TOOLCHAIN),iar)
+ CFLAGS += \
+ --cpu cortex-m85 \
+ --fpu VFPv5_D16 \
+
+ ASFLAGS += \
+ --cpu cortex-m85 \
+ --fpu VFPv5_D16 \
+
+else
+ $(error "TOOLCHAIN is not supported")
+endif
+
+FREERTOS_PORTABLE_SRC ?= $(FREERTOS_PORTABLE_PATH)/ARM_CM85_NTZ/non_secure
diff --git a/hw/bsp/ra/board_cfg.h b/hw/bsp/ra/board_cfg.h
index baed46b5fb..825f8cd329 100644
--- a/hw/bsp/ra/board_cfg.h
+++ b/hw/bsp/ra/board_cfg.h
@@ -1,45 +1,13 @@
-/*
- * The MIT License (MIT)
- *
- * Copyright (c) 2023 Ha Thach (tinyusb.org)
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this software and associated documentation files (the "Software"), to deal
- * in the Software without restriction, including without limitation the rights
- * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
- * copies of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
- * THE SOFTWARE.
- *
- */
-
-#ifndef _BOARD_CFG_H
-#define _BOARD_CFG_H
-
+/* generated configuration header file - do not edit */
+#ifndef BOARD_CFG_H_
+#define BOARD_CFG_H_
#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if defined(BSP_MCU_GROUP_RA6M5) || defined(BSP_MCU_GROUP_RA6M3) || (BSP_CFG_MCU_PART_SERIES == 8)
- #define BOARD_HAS_USB_HIGHSPEED
-#endif
+ extern "C" {
+ #endif
-// for SystemInit()
-void bsp_init(void * p_args);
-
-
-#ifdef __cplusplus
-}
-#endif
+ void bsp_init(void * p_args);
-#endif
+ #ifdef __cplusplus
+ }
+ #endif
+#endif /* BOARD_CFG_H_ */
diff --git a/hw/bsp/ra/boards/portenta_c33/board.cmake b/hw/bsp/ra/boards/portenta_c33/board.cmake
index 1837d8450e..520686daa5 100644
--- a/hw/bsp/ra/boards/portenta_c33/board.cmake
+++ b/hw/bsp/ra/boards/portenta_c33/board.cmake
@@ -4,22 +4,13 @@ set(MCU_VARIANT ra6m5)
set(JLINK_DEVICE R7FA6M5BH)
set(DFU_UTIL_VID_PID 2341:0368)
-set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/${BOARD}.ld)
-
-# Device port default to PORT1 Highspeed
-if (NOT DEFINED PORT)
-set(PORT 1)
+# device default to PORT 1 High Speed
+if (NOT DEFINED RHPORT_DEVICE)
+ set(RHPORT_DEVICE 1)
+endif()
+if (NOT DEFINED RHPORT_HOST)
+ set(RHPORT_HOST 0)
endif()
-
-# Host port will be the other port
-set(HOST_PORT $)
function(update_board TARGET)
- target_compile_definitions(${TARGET} PUBLIC
- BOARD_TUD_RHPORT=${PORT}
- BOARD_TUH_RHPORT=${HOST_PORT}
- # port 0 is fullspeed, port 1 is highspeed
- BOARD_TUD_MAX_SPEED=$
- BOARD_TUH_MAX_SPEED=$
- )
endfunction()
diff --git a/hw/bsp/ra/boards/portenta_c33/board.h b/hw/bsp/ra/boards/portenta_c33/board.h
index 7841ec8b84..ba663d040e 100644
--- a/hw/bsp/ra/boards/portenta_c33/board.h
+++ b/hw/bsp/ra/boards/portenta_c33/board.h
@@ -31,36 +31,9 @@
extern "C" {
#endif
-#define LED1 BSP_IO_PORT_01_PIN_07 // Red LED
#define LED_STATE_ON 1
-
-#define SW1 BSP_IO_PORT_04_PIN_08 // D12
#define BUTTON_STATE_ACTIVE 0
-static const ioport_pin_cfg_t board_pin_cfg[] = {
- { .pin = LED1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_OUTPUT | IOPORT_CFG_PORT_OUTPUT_LOW },
- { .pin = SW1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_INPUT },
-
- // USB FS
- { .pin = BSP_IO_PORT_04_PIN_07, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS | IOPORT_CFG_DRIVE_HIGH },
- { .pin = BSP_IO_PORT_05_PIN_00, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS | IOPORT_CFG_DRIVE_HIGH},
- { .pin = BSP_IO_PORT_05_PIN_01, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS | IOPORT_CFG_DRIVE_HIGH},
-
- // USB HS
- { .pin = BSP_IO_PORT_07_PIN_07, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_HS },
- { .pin = BSP_IO_PORT_11_PIN_00, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_HS | IOPORT_CFG_DRIVE_HIGH},
- { .pin = BSP_IO_PORT_11_PIN_01, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_HS | IOPORT_CFG_DRIVE_HIGH},
-
- // ETM Trace
- #ifdef TRACE_ETM
- { .pin = BSP_IO_PORT_02_PIN_08, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE | IOPORT_CFG_DRIVE_HS_HIGH },
- { .pin = BSP_IO_PORT_02_PIN_09, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE | IOPORT_CFG_DRIVE_HS_HIGH },
- { .pin = BSP_IO_PORT_02_PIN_10, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE | IOPORT_CFG_DRIVE_HS_HIGH },
- { .pin = BSP_IO_PORT_02_PIN_11, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE | IOPORT_CFG_DRIVE_HS_HIGH },
- { .pin = BSP_IO_PORT_02_PIN_14, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE | IOPORT_CFG_DRIVE_HS_HIGH },
- #endif
-};
-
#ifdef __cplusplus
}
#endif
diff --git a/hw/bsp/ra/boards/portenta_c33/board.mk b/hw/bsp/ra/boards/portenta_c33/board.mk
index 6a5c2ffce8..ab814cda6c 100644
--- a/hw/bsp/ra/boards/portenta_c33/board.mk
+++ b/hw/bsp/ra/boards/portenta_c33/board.mk
@@ -1,10 +1,9 @@
CPU_CORE = cortex-m33
MCU_VARIANT = ra6m5
-LD_FILE = ${BOARD_PATH}/${BOARD}.ld
-
# Port 1 is highspeed
-PORT ?= 1
+RHPORT_DEVICE ?= 1
+RHPORT_HOST ?= 0
JLINK_DEVICE = R7FA6M5BH
DFU_UTIL_OPTION = -d 2341:0368 -a 0
diff --git a/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_cfg.h
deleted file mode 100644
index 33d3818501..0000000000
--- a/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_cfg.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/* generated configuration header file - do not edit */
-#ifndef BSP_CFG_H_
-#define BSP_CFG_H_
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "bsp_clock_cfg.h"
-#include "bsp_mcu_family_cfg.h"
-#include "board_cfg.h"
-
-#define RA_NOT_DEFINED 0
-#ifndef BSP_CFG_RTOS
-#if (RA_NOT_DEFINED) != (2)
-#define BSP_CFG_RTOS (2)
-#elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED)
- #define BSP_CFG_RTOS (1)
-#else
- #define BSP_CFG_RTOS (0)
-#endif
-#endif
-#ifndef BSP_CFG_RTC_USED
-#define BSP_CFG_RTC_USED (RA_NOT_DEFINED)
-#endif
-#undef RA_NOT_DEFINED
-#if defined(_RA_BOOT_IMAGE)
- #define BSP_CFG_BOOT_IMAGE (1)
-#endif
-#define BSP_CFG_MCU_VCC_MV (3300)
-#define BSP_CFG_STACK_MAIN_BYTES (0x1000)
-#define BSP_CFG_HEAP_BYTES (0x1000)
-#define BSP_CFG_PARAM_CHECKING_ENABLE (1)
-#define BSP_CFG_ASSERT (0)
-#define BSP_CFG_ERROR_LOG (0)
-
-#define BSP_CFG_PFS_PROTECT ((1))
-
-#define BSP_CFG_C_RUNTIME_INIT ((1))
-#define BSP_CFG_EARLY_INIT ((0))
-
-#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0))
-
-#ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED
-#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1)
-#endif
-
-#ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE
-#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0)
-#endif
-#ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE
-#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0)
-#endif
-#ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED
-#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1)
-#endif
-#ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS
-#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-#endif /* BSP_CFG_H_ */
diff --git a/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
deleted file mode 100644
index 6845183db5..0000000000
--- a/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/* generated configuration header file - do not edit */
-#ifndef BSP_MCU_DEVICE_PN_CFG_H_
-#define BSP_MCU_DEVICE_PN_CFG_H_
-#define BSP_MCU_R7FA6M5BH3CFC
-#define BSP_MCU_FEATURE_SET ('B')
-#define BSP_ROM_SIZE_BYTES (2097152)
-#define BSP_RAM_SIZE_BYTES (524288)
-#define BSP_DATA_FLASH_SIZE_BYTES (8192)
-#define BSP_PACKAGE_LQFP
-#define BSP_PACKAGE_PINS (176)
-#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */
diff --git a/hw/bsp/ra/boards/portenta_c33/portenta_c33.ld b/hw/bsp/ra/boards/portenta_c33/portenta_c33.ld
deleted file mode 100644
index ba15588e61..0000000000
--- a/hw/bsp/ra/boards/portenta_c33/portenta_c33.ld
+++ /dev/null
@@ -1,25 +0,0 @@
-RAM_START = 0x20000000;
-RAM_LENGTH = 0x80000;
-FLASH_START = 0x00000000;
-FLASH_LENGTH = 0x200000;
-DATA_FLASH_START = 0x08000000;
-DATA_FLASH_LENGTH = 0x2000;
-OPTION_SETTING_START = 0x0100A100;
-OPTION_SETTING_LENGTH = 0x100;
-OPTION_SETTING_S_START = 0x0100A200;
-OPTION_SETTING_S_LENGTH = 0x100;
-ID_CODE_START = 0x00000000;
-ID_CODE_LENGTH = 0x0;
-SDRAM_START = 0x80010000;
-SDRAM_LENGTH = 0x0;
-QSPI_FLASH_START = 0x60000000;
-QSPI_FLASH_LENGTH = 0x4000000;
-OSPI_DEVICE_0_START = 0x68000000;
-OSPI_DEVICE_0_LENGTH = 0x8000000;
-OSPI_DEVICE_1_START = 0x70000000;
-OSPI_DEVICE_1_LENGTH = 0x10000000;
-
-/* Board has bootloader */
-FLASH_IMAGE_START = 0x10000;
-
-INCLUDE fsp.ld
diff --git a/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_cfg.h
new file mode 100644
index 0000000000..90afbdef3d
--- /dev/null
+++ b/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_cfg.h
@@ -0,0 +1,62 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_CFG_H_
+#define BSP_CFG_H_
+#ifdef __cplusplus
+ extern "C" {
+ #endif
+
+ #include "bsp_clock_cfg.h"
+ #include "bsp_mcu_family_cfg.h"
+ #include "board_cfg.h"
+ #define RA_NOT_DEFINED 0
+ #ifndef BSP_CFG_RTOS
+ #if (RA_NOT_DEFINED) != (RA_NOT_DEFINED)
+ #define BSP_CFG_RTOS (2)
+ #elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED)
+ #define BSP_CFG_RTOS (1)
+ #else
+ #define BSP_CFG_RTOS (0)
+ #endif
+ #endif
+ #ifndef BSP_CFG_RTC_USED
+ #define BSP_CFG_RTC_USED (RA_NOT_DEFINED)
+ #endif
+ #undef RA_NOT_DEFINED
+ #if defined(_RA_BOOT_IMAGE)
+ #define BSP_CFG_BOOT_IMAGE (1)
+ #endif
+ #define BSP_CFG_MCU_VCC_MV (3300)
+ #define BSP_CFG_STACK_MAIN_BYTES (0x1000)
+ #define BSP_CFG_HEAP_BYTES (0x1000)
+ #define BSP_CFG_PARAM_CHECKING_ENABLE (0)
+ #define BSP_CFG_ASSERT (0)
+ #define BSP_CFG_ERROR_LOG (0)
+
+ #define BSP_CFG_PFS_PROTECT ((1))
+
+ #define BSP_CFG_C_RUNTIME_INIT ((1))
+ #define BSP_CFG_EARLY_INIT ((0))
+
+ #define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0))
+
+ #ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED
+ #define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1)
+ #endif
+
+ #ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE
+ #define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0)
+ #endif
+ #ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE
+ #define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0)
+ #endif
+ #ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED
+ #define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1)
+ #endif
+ #ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS
+ #define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
+ #endif
+
+ #ifdef __cplusplus
+ }
+ #endif
+#endif /* BSP_CFG_H_ */
diff --git a/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_mcu_device_cfg.h b/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h
similarity index 100%
rename from hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_mcu_device_cfg.h
rename to hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h
diff --git a/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
new file mode 100644
index 0000000000..e532478f8f
--- /dev/null
+++ b/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
@@ -0,0 +1,11 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_MCU_DEVICE_PN_CFG_H_
+#define BSP_MCU_DEVICE_PN_CFG_H_
+#define BSP_MCU_R7FA6M5BH3CFC
+ #define BSP_MCU_FEATURE_SET ('B')
+ #define BSP_ROM_SIZE_BYTES (2097152)
+ #define BSP_RAM_SIZE_BYTES (524288)
+ #define BSP_DATA_FLASH_SIZE_BYTES (8192)
+ #define BSP_PACKAGE_LQFP
+ #define BSP_PACKAGE_PINS (176)
+#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */
diff --git a/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h
similarity index 56%
rename from hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_mcu_family_cfg.h
rename to hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h
index d5428540fb..c01219377a 100644
--- a/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_mcu_family_cfg.h
+++ b/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h
@@ -5,80 +5,80 @@
extern "C" {
#endif
-#include "bsp_mcu_device_pn_cfg.h"
-#include "bsp_mcu_device_cfg.h"
-#include "../../../ra/fsp/src/bsp/mcu/ra6m5/bsp_mcu_info.h"
-#include "bsp_clock_cfg.h"
-
-#define BSP_MCU_GROUP_RA6M5 (1)
-#define BSP_LOCO_HZ (32768)
-#define BSP_MOCO_HZ (8000000)
-#define BSP_SUB_CLOCK_HZ (32768)
-#if BSP_CFG_HOCO_FREQUENCY == 0
-#define BSP_HOCO_HZ (16000000)
-#elif BSP_CFG_HOCO_FREQUENCY == 1
- #define BSP_HOCO_HZ (18000000)
-#elif BSP_CFG_HOCO_FREQUENCY == 2
- #define BSP_HOCO_HZ (20000000)
-#else
- #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h"
-#endif
+ #include "bsp_mcu_device_pn_cfg.h"
+ #include "bsp_mcu_device_cfg.h"
+ #include "../../../ra/fsp/src/bsp/mcu/ra6m5/bsp_mcu_info.h"
+ #include "bsp_clock_cfg.h"
+ #define BSP_MCU_GROUP_RA6M5 (1)
+ #define BSP_LOCO_HZ (32768)
+ #define BSP_MOCO_HZ (8000000)
+ #define BSP_SUB_CLOCK_HZ (32768)
+ #if BSP_CFG_HOCO_FREQUENCY == 0
+ #define BSP_HOCO_HZ (16000000)
+ #elif BSP_CFG_HOCO_FREQUENCY == 1
+ #define BSP_HOCO_HZ (18000000)
+ #elif BSP_CFG_HOCO_FREQUENCY == 2
+ #define BSP_HOCO_HZ (20000000)
+ #else
+ #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h"
+ #endif
-#define BSP_CFG_FLL_ENABLE (0)
+ #define BSP_CFG_FLL_ENABLE (0)
-#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U)
-#define BSP_VECTOR_TABLE_MAX_ENTRIES (112U)
+ #define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U)
+ #define BSP_VECTOR_TABLE_MAX_ENTRIES (112U)
+ #define BSP_CFG_INLINE_IRQ_FUNCTIONS (1)
-#if defined(_RA_TZ_SECURE)
+ #if defined(_RA_TZ_SECURE)
#define BSP_TZ_SECURE_BUILD (1)
#define BSP_TZ_NONSECURE_BUILD (0)
#elif defined(_RA_TZ_NONSECURE)
#define BSP_TZ_SECURE_BUILD (0)
#define BSP_TZ_NONSECURE_BUILD (1)
#else
-#define BSP_TZ_SECURE_BUILD (0)
-#define BSP_TZ_NONSECURE_BUILD (0)
-#endif
-
-/* TrustZone Settings */
-#define BSP_TZ_CFG_INIT_SECURE_ONLY (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE))
-#define BSP_TZ_CFG_SKIP_INIT (BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_INIT_SECURE_ONLY)
-#define BSP_TZ_CFG_EXCEPTION_RESPONSE (0)
-
-/* CMSIS TrustZone Settings */
-#define SCB_CSR_AIRCR_INIT (1)
-#define SCB_AIRCR_BFHFNMINS_VAL (0)
-#define SCB_AIRCR_SYSRESETREQS_VAL (1)
-#define SCB_AIRCR_PRIS_VAL (0)
-#define TZ_FPU_NS_USAGE (1)
+ #define BSP_TZ_SECURE_BUILD (0)
+ #define BSP_TZ_NONSECURE_BUILD (0)
+ #endif
+
+ /* TrustZone Settings */
+ #define BSP_TZ_CFG_INIT_SECURE_ONLY (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE))
+ #define BSP_TZ_CFG_SKIP_INIT (BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_INIT_SECURE_ONLY)
+ #define BSP_TZ_CFG_EXCEPTION_RESPONSE (0)
+
+ /* CMSIS TrustZone Settings */
+ #define SCB_CSR_AIRCR_INIT (1)
+ #define SCB_AIRCR_BFHFNMINS_VAL (0)
+ #define SCB_AIRCR_SYSRESETREQS_VAL (1)
+ #define SCB_AIRCR_PRIS_VAL (0)
+ #define TZ_FPU_NS_USAGE (1)
#ifndef SCB_NSACR_CP10_11_VAL
-#define SCB_NSACR_CP10_11_VAL (3U)
+ #define SCB_NSACR_CP10_11_VAL (3U)
#endif
#ifndef FPU_FPCCR_TS_VAL
-#define FPU_FPCCR_TS_VAL (1U)
+ #define FPU_FPCCR_TS_VAL (1U)
#endif
-#define FPU_FPCCR_CLRONRETS_VAL (1)
+ #define FPU_FPCCR_CLRONRETS_VAL (1)
#ifndef FPU_FPCCR_CLRONRET_VAL
-#define FPU_FPCCR_CLRONRET_VAL (1)
+ #define FPU_FPCCR_CLRONRET_VAL (1)
#endif
-/* The C-Cache line size that is configured during startup. */
+ /* The C-Cache line size that is configured during startup. */
#ifndef BSP_CFG_C_CACHE_LINE_SIZE
-#define BSP_CFG_C_CACHE_LINE_SIZE (1U)
+ #define BSP_CFG_C_CACHE_LINE_SIZE (1U)
#endif
-/* Type 1 Peripheral Security Attribution */
+ /* Type 1 Peripheral Security Attribution */
-/* Peripheral Security Attribution Register (PSAR) Settings */
+ /* Peripheral Security Attribution Register (PSAR) Settings */
#ifndef BSP_TZ_CFG_PSARB
#define BSP_TZ_CFG_PSARB (\
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CAN1 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* CAN0 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* IIC1 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9) /* IIC0 */ | \
- (((1 > 0) ? 0U : 1U) << 11) /* USBFS */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* USBFS */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 18) /* SPI1 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 19) /* SPI0 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* SCI9 */ | \
@@ -146,19 +146,19 @@ extern "C" {
0xfffffffc) /* Unused */
#endif
-/* Type 2 Peripheral Security Attribution */
+ /* Type 2 Peripheral Security Attribution */
-/* Security attribution for Cache registers. */
+ /* Security attribution for Cache registers. */
#ifndef BSP_TZ_CFG_CSAR
#define BSP_TZ_CFG_CSAR (0xFFFFFFFFU)
#endif
-/* Security attribution for RSTSRn registers. */
+ /* Security attribution for RSTSRn registers. */
#ifndef BSP_TZ_CFG_RSTSAR
#define BSP_TZ_CFG_RSTSAR (0xFFFFFFFFU)
#endif
-/* Security attribution for registers of LVD channels. */
+ /* Security attribution for registers of LVD channels. */
#ifndef BSP_TZ_CFG_LVDSAR
#define BSP_TZ_CFG_LVDSAR (\
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) | /* LVD Channel 1 */ \
@@ -166,16 +166,16 @@ extern "C" {
0xFFFFFFFCU)
#endif
-/* Security attribution for LPM registers. */
+ /* Security attribution for LPM registers. */
#ifndef BSP_TZ_CFG_LPMSAR
#define BSP_TZ_CFG_LPMSAR ((RA_NOT_DEFINED > 0) ? 0xFFFFFCEAU : 0xFFFFFFFFU)
#endif
-/* Deep Standby Interrupt Factor Security Attribution Register. */
+ /* Deep Standby Interrupt Factor Security Attribution Register. */
#ifndef BSP_TZ_CFG_DPFSAR
#define BSP_TZ_CFG_DPFSAR ((RA_NOT_DEFINED > 0) ? 0xF2E00000U : 0xFFFFFFFFU)
#endif
-/* Security attribution for CGC registers. */
+ /* Security attribution for CGC registers. */
#ifndef BSP_TZ_CFG_CGFSAR
#if BSP_CFG_CLOCKS_SECURE
/* Protect all CGC registers from Non-secure write access. */
@@ -186,12 +186,12 @@ extern "C" {
#endif
#endif
-/* Security attribution for Battery Backup registers. */
+ /* Security attribution for Battery Backup registers. */
#ifndef BSP_TZ_CFG_BBFSAR
#define BSP_TZ_CFG_BBFSAR (0x00FFFFFF)
#endif
-/* Security attribution for registers for IRQ channels. */
+ /* Security attribution for registers for IRQ channels. */
#ifndef BSP_TZ_CFG_ICUSARA
#define BSP_TZ_CFG_ICUSARA (\
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ | \
@@ -213,12 +213,12 @@ extern "C" {
0xFFFF0000U)
#endif
-/* Security attribution for NMI registers. */
+ /* Security attribution for NMI registers. */
#ifndef BSP_TZ_CFG_ICUSARB
#define BSP_TZ_CFG_ICUSARB (0 | 0xFFFFFFFEU) /* Should match AIRCR.BFHFNMINS. */
#endif
-/* Security attribution for registers for DMAC channels */
+ /* Security attribution for registers for DMAC channels */
#ifndef BSP_TZ_CFG_ICUSARC
#define BSP_TZ_CFG_ICUSARC (\
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* DMAC Channel 0 */ | \
@@ -232,29 +232,29 @@ extern "C" {
0xFFFFFF00U)
#endif
-/* Security attribution registers for SELSR0. */
+ /* Security attribution registers for SELSR0. */
#ifndef BSP_TZ_CFG_ICUSARD
#define BSP_TZ_CFG_ICUSARD ((RA_NOT_DEFINED > 0) ? 0xFFFFFFFEU : 0xFFFFFFFFU)
#endif
-/* Security attribution registers for WUPEN0. */
+ /* Security attribution registers for WUPEN0. */
#ifndef BSP_TZ_CFG_ICUSARE
#define BSP_TZ_CFG_ICUSARE ((RA_NOT_DEFINED > 0) ? 0x04F2FFFFU : 0xFFFFFFFFU)
#endif
-/* Security attribution registers for WUPEN1. */
+ /* Security attribution registers for WUPEN1. */
#ifndef BSP_TZ_CFG_ICUSARF
#define BSP_TZ_CFG_ICUSARF ((RA_NOT_DEFINED > 0) ? 0xFFFFFFF8U : 0xFFFFFFFFU)
#endif
-/* Set DTCSTSAR if the Secure program uses the DTC. */
+ /* Set DTCSTSAR if the Secure program uses the DTC. */
#if RA_NOT_DEFINED == RA_NOT_DEFINED
-#define BSP_TZ_CFG_DTC_USED (0U)
+ #define BSP_TZ_CFG_DTC_USED (0U)
#else
#define BSP_TZ_CFG_DTC_USED (1U)
#endif
-/* Security attribution of FLWT and FCKMHZ registers. */
+ /* Security attribution of FLWT and FCKMHZ registers. */
#ifndef BSP_TZ_CFG_FSAR
/* If the CGC registers are only accessible in Secure mode, than there is no
* reason for nonsecure applications to access FLWT and FCKMHZ. */
@@ -267,118 +267,123 @@ extern "C" {
#endif
#endif
-/* Security attribution for SRAM registers. */
+ /* Security attribution for SRAM registers. */
#ifndef BSP_TZ_CFG_SRAMSAR
/* If the CGC registers are only accessible in Secure mode, than there is no reason for Non Secure applications to access
* SRAM0WTEN and therefore there is no reason to access PRCR2. */
-#define BSP_TZ_CFG_SRAMSAR (\
+ #define BSP_TZ_CFG_SRAMSAR (\
1 | \
((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 1U) : 0U) | \
4 | \
0xFFFFFFF8U)
#endif
-/* Security attribution for Standby RAM registers. */
+ /* Security attribution for Standby RAM registers. */
#ifndef BSP_TZ_CFG_STBRAMSAR
-#define BSP_TZ_CFG_STBRAMSAR (0 | 0xFFFFFFF0U)
+ #define BSP_TZ_CFG_STBRAMSAR (0 | 0xFFFFFFF0U)
#endif
-/* Security attribution for the DMAC Bus Master MPU settings. */
+ /* Security attribution for the DMAC Bus Master MPU settings. */
#ifndef BSP_TZ_CFG_MMPUSARA
-/* The DMAC Bus Master MPU settings should align with the DMAC channel settings. */
-#define BSP_TZ_CFG_MMPUSARA (BSP_TZ_CFG_ICUSARC)
+ /* The DMAC Bus Master MPU settings should align with the DMAC channel settings. */
+ #define BSP_TZ_CFG_MMPUSARA (BSP_TZ_CFG_ICUSARC)
#endif
-/* Security Attribution Register A for BUS Control registers. */
+ /* Security Attribution Register A for BUS Control registers. */
#ifndef BSP_TZ_CFG_BUSSARA
-#define BSP_TZ_CFG_BUSSARA (0xFFFFFFFFU)
+ #define BSP_TZ_CFG_BUSSARA (0xFFFFFFFFU)
#endif
-/* Security Attribution Register B for BUS Control registers. */
+ /* Security Attribution Register B for BUS Control registers. */
#ifndef BSP_TZ_CFG_BUSSARB
-#define BSP_TZ_CFG_BUSSARB (0xFFFFFFFFU)
+ #define BSP_TZ_CFG_BUSSARB (0xFFFFFFFFU)
#endif
-/* Enable Uninitialized Non-Secure Application Fallback. */
+ /* Enable Uninitialized Non-Secure Application Fallback. */
#ifndef BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK
-#define BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK (1U)
+ #define BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK (1U)
#endif
-#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2)
-#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10)
-#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17)
-#define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26)
-#define OFS_SEQ5 (1 << 28) | (1 << 30)
-#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
-/* Option Function Select Register 1 Security Attribution */
+ #define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2)
+ #define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10)
+ #define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17)
+ #define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26)
+ #define OFS_SEQ5 (1 << 28) | (1 << 30)
+ #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
+
+ /* Option Function Select Register 1 Security Attribution */
#ifndef BSP_CFG_ROM_REG_OFS1_SEL
#if defined(_RA_TZ_SECURE) || defined(_RA_TZ_NONSECURE)
- #define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0x700U : 0U) | ((RA_NOT_DEFINED > 0) ? 0U : 0x7U))
+ #define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U | ((0U << 0U)) | ((0U << 2U)) | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0x700U : 0U))
#else
-#define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U)
+ #define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U)
#endif
#endif
-#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) | (1 << 8))
+ #define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) | (1 << 8))
-/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */
-#define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector)
+ /* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */
+ #define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector)
-/* Dual Mode Select Register */
+ /* Dual Mode Select Register */
#ifndef BSP_CFG_ROM_REG_DUALSEL
-#define BSP_CFG_ROM_REG_DUALSEL (0xFFFFFFF8U | (0x7U))
+ #define BSP_CFG_ROM_REG_DUALSEL (0xFFFFFFF8U | (0x7U))
#endif
-/* Block Protection Register 0 */
+ /* Block Protection Register 0 */
#ifndef BSP_CFG_ROM_REG_BPS0
-#define BSP_CFG_ROM_REG_BPS0 (~( 0U))
+ #define BSP_CFG_ROM_REG_BPS0 (~( 0U))
#endif
-/* Block Protection Register 1 */
+ /* Block Protection Register 1 */
#ifndef BSP_CFG_ROM_REG_BPS1
-#define BSP_CFG_ROM_REG_BPS1 (~( 0U))
+ #define BSP_CFG_ROM_REG_BPS1 (~( 0U))
#endif
-/* Block Protection Register 2 */
+ /* Block Protection Register 2 */
#ifndef BSP_CFG_ROM_REG_BPS2
-#define BSP_CFG_ROM_REG_BPS2 (~( 0U))
+ #define BSP_CFG_ROM_REG_BPS2 (~( 0U))
#endif
-/* Block Protection Register 3 */
+ /* Block Protection Register 3 */
#ifndef BSP_CFG_ROM_REG_BPS3
-#define BSP_CFG_ROM_REG_BPS3 (0xFFFFFFFFU)
+ #define BSP_CFG_ROM_REG_BPS3 (0xFFFFFFFFU)
#endif
-/* Permanent Block Protection Register 0 */
+ /* Permanent Block Protection Register 0 */
#ifndef BSP_CFG_ROM_REG_PBPS0
-#define BSP_CFG_ROM_REG_PBPS0 (~( 0U))
+ #define BSP_CFG_ROM_REG_PBPS0 (~( 0U))
#endif
-/* Permanent Block Protection Register 1 */
+ /* Permanent Block Protection Register 1 */
#ifndef BSP_CFG_ROM_REG_PBPS1
-#define BSP_CFG_ROM_REG_PBPS1 (~( 0U))
+ #define BSP_CFG_ROM_REG_PBPS1 (~( 0U))
#endif
-/* Permanent Block Protection Register 2 */
+ /* Permanent Block Protection Register 2 */
#ifndef BSP_CFG_ROM_REG_PBPS2
-#define BSP_CFG_ROM_REG_PBPS2 (~( 0U))
+ #define BSP_CFG_ROM_REG_PBPS2 (~( 0U))
#endif
-/* Permanent Block Protection Register 3 */
+ /* Permanent Block Protection Register 3 */
#ifndef BSP_CFG_ROM_REG_PBPS3
-#define BSP_CFG_ROM_REG_PBPS3 (0xFFFFFFFFU)
+ #define BSP_CFG_ROM_REG_PBPS3 (0xFFFFFFFFU)
#endif
-/* Security Attribution for Block Protection Register 0 (If any blocks are marked as protected in the secure application, then mark them as secure) */
+ /* Security Attribution for Block Protection Register 0 (If any blocks are marked as protected in the secure application, then mark them as secure) */
#ifndef BSP_CFG_ROM_REG_BPS_SEL0
-#define BSP_CFG_ROM_REG_BPS_SEL0 (BSP_CFG_ROM_REG_BPS0 & BSP_CFG_ROM_REG_PBPS0)
+ #define BSP_CFG_ROM_REG_BPS_SEL0 (BSP_CFG_ROM_REG_BPS0 & BSP_CFG_ROM_REG_PBPS0)
#endif
-/* Security Attribution for Block Protection Register 1 (If any blocks are marked as protected in the secure application, then mark them as secure) */
+ /* Security Attribution for Block Protection Register 1 (If any blocks are marked as protected in the secure application, then mark them as secure) */
#ifndef BSP_CFG_ROM_REG_BPS_SEL1
-#define BSP_CFG_ROM_REG_BPS_SEL1 (BSP_CFG_ROM_REG_BPS1 & BSP_CFG_ROM_REG_PBPS1)
+ #define BSP_CFG_ROM_REG_BPS_SEL1 (BSP_CFG_ROM_REG_BPS1 & BSP_CFG_ROM_REG_PBPS1)
#endif
-/* Security Attribution for Block Protection Register 2 (If any blocks are marked as protected in the secure application, then mark them as secure) */
+ /* Security Attribution for Block Protection Register 2 (If any blocks are marked as protected in the secure application, then mark them as secure) */
#ifndef BSP_CFG_ROM_REG_BPS_SEL2
-#define BSP_CFG_ROM_REG_BPS_SEL2 (BSP_CFG_ROM_REG_BPS2 & BSP_CFG_ROM_REG_PBPS2)
+ #define BSP_CFG_ROM_REG_BPS_SEL2 (BSP_CFG_ROM_REG_BPS2 & BSP_CFG_ROM_REG_PBPS2)
#endif
-/* Security Attribution for Block Protection Register 3 (If any blocks are marked as protected in the secure application, then mark them as secure) */
+ /* Security Attribution for Block Protection Register 3 (If any blocks are marked as protected in the secure application, then mark them as secure) */
#ifndef BSP_CFG_ROM_REG_BPS_SEL3
-#define BSP_CFG_ROM_REG_BPS_SEL3 (BSP_CFG_ROM_REG_BPS3 & BSP_CFG_ROM_REG_PBPS3)
+ #define BSP_CFG_ROM_REG_BPS_SEL3 (BSP_CFG_ROM_REG_BPS3 & BSP_CFG_ROM_REG_PBPS3)
+#endif
+ /* Security Attribution for Bank Select Register */
+#ifndef BSP_CFG_ROM_REG_BANKSEL_SEL
+ #define BSP_CFG_ROM_REG_BANKSEL_SEL (0xFFFFFFFFU)
#endif
#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT
-#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9)
+ #define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9)
#endif
#ifdef __cplusplus
diff --git a/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h b/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h
new file mode 100644
index 0000000000..c411386c14
--- /dev/null
+++ b/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h
@@ -0,0 +1,17 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_PIN_CFG_H_
+#define BSP_PIN_CFG_H_
+#include "r_ioport.h"
+
+/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+#define LED1 (BSP_IO_PORT_01_PIN_07)
+#define SW1 (BSP_IO_PORT_04_PIN_08)
+extern const ioport_cfg_t g_bsp_pin_cfg; /* R7FA6M5BH3CFC.pincfg */
+
+void BSP_PinConfigSecurityInit();
+
+/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+#endif /* BSP_PIN_CFG_H_ */
diff --git a/hw/bsp/ra/r_ioport_cfg.h b/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/r_ioport_cfg.h
similarity index 75%
rename from hw/bsp/ra/r_ioport_cfg.h
rename to hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/r_ioport_cfg.h
index cb7c079326..d2688bf5ba 100644
--- a/hw/bsp/ra/r_ioport_cfg.h
+++ b/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/r_ioport_cfg.h
@@ -1,7 +1,13 @@
/* generated configuration header file - do not edit */
#ifndef R_IOPORT_CFG_H_
#define R_IOPORT_CFG_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
+#ifdef __cplusplus
+}
+#endif
#endif /* R_IOPORT_CFG_H_ */
diff --git a/hw/bsp/ra/boards/portenta_c33/ra_gen/bsp_clock_cfg.h b/hw/bsp/ra/boards/portenta_c33/ra_gen/bsp_clock_cfg.h
new file mode 100644
index 0000000000..91b9de11e3
--- /dev/null
+++ b/hw/bsp/ra/boards/portenta_c33/ra_gen/bsp_clock_cfg.h
@@ -0,0 +1,35 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_CLOCK_CFG_H_
+#define BSP_CLOCK_CFG_H_
+#define BSP_CFG_CLOCKS_SECURE (0)
+#define BSP_CFG_CLOCKS_OVERRIDE (0)
+#define BSP_CFG_XTAL_HZ (24000000) /* XTAL 24000000Hz */
+#define BSP_CFG_HOCO_FREQUENCY (2) /* HOCO 20MHz */
+#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */
+#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_3) /* PLL Div /3 */
+#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(25U,0U) /* PLL Mul x25.0 */
+#define BSP_CFG_PLL2_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL2 Src: XTAL */
+#define BSP_CFG_PLL2_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL2 Div /2 */
+#define BSP_CFG_PLL2_MUL BSP_CLOCKS_PLL_MUL(20U,0U) /* PLL2 Mul x20.0 */
+#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */
+#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */
+#define BSP_CFG_UCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2) /* UCLK Src: PLL2 */
+#define BSP_CFG_U60CK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2) /* U60CK Src: PLL2 */
+#define BSP_CFG_OCTA_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* OCTASPICLK Disabled */
+#define BSP_CFG_CANFDCLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CANFDCLK Disabled */
+#define BSP_CFG_CECCLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CECCLK Disabled */
+#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* ICLK Div /1 */
+#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKA Div /2 */
+#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKB Div /4 */
+#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKC Div /4 */
+#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKD Div /2 */
+#define BSP_CFG_BCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* BCLK Div /2 */
+#define BSP_CFG_BCLK_OUTPUT (2) /* EBCLK Div /2 */
+#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* FCLK Div /4 */
+#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */
+#define BSP_CFG_UCK_DIV (BSP_CLOCKS_USB_CLOCK_DIV_5) /* UCLK Div /5 */
+#define BSP_CFG_U60CK_DIV (BSP_CLOCKS_USB60_CLOCK_DIV_4) /* U60CK Div /4 */
+#define BSP_CFG_OCTA_DIV (BSP_CLOCKS_OCTA_CLOCK_DIV_1) /* OCTASPICLK Div /1 */
+#define BSP_CFG_CANFDCLK_DIV (BSP_CLOCKS_CANFD_CLOCK_DIV_1) /* CANFDCLK Div /1 */
+#define BSP_CFG_CECCLK_DIV (BSP_CLOCKS_CEC_CLOCK_DIV_1) /* CECCLK Div /1 */
+#endif /* BSP_CLOCK_CFG_H_ */
diff --git a/hw/bsp/ra/boards/portenta_c33/ra_gen/common_data.c b/hw/bsp/ra/boards/portenta_c33/ra_gen/common_data.c
new file mode 100644
index 0000000000..50036c0adc
--- /dev/null
+++ b/hw/bsp/ra/boards/portenta_c33/ra_gen/common_data.c
@@ -0,0 +1,11 @@
+/* generated common source file - do not edit */
+#include "common_data.h"
+ioport_instance_ctrl_t g_ioport_ctrl;
+const ioport_instance_t g_ioport =
+ {
+ .p_api = &g_ioport_on_ioport,
+ .p_ctrl = &g_ioport_ctrl,
+ .p_cfg = &g_bsp_pin_cfg,
+ };
+void g_common_init(void) {
+}
diff --git a/hw/bsp/ra/boards/portenta_c33/ra_gen/common_data.h b/hw/bsp/ra/boards/portenta_c33/ra_gen/common_data.h
new file mode 100644
index 0000000000..6a08cbee09
--- /dev/null
+++ b/hw/bsp/ra/boards/portenta_c33/ra_gen/common_data.h
@@ -0,0 +1,20 @@
+/* generated common header file - do not edit */
+#ifndef COMMON_DATA_H_
+#define COMMON_DATA_H_
+#include
+#include "bsp_api.h"
+#include "r_ioport.h"
+#include "bsp_pin_cfg.h"
+FSP_HEADER
+#define IOPORT_CFG_NAME g_bsp_pin_cfg
+#define IOPORT_CFG_OPEN R_IOPORT_Open
+#define IOPORT_CFG_CTRL g_ioport_ctrl
+
+/* IOPORT Instance */
+extern const ioport_instance_t g_ioport;
+
+/* IOPORT control structure. */
+extern ioport_instance_ctrl_t g_ioport_ctrl;
+void g_common_init(void);
+FSP_FOOTER
+#endif /* COMMON_DATA_H_ */
diff --git a/hw/bsp/ra/boards/portenta_c33/ra_gen/pin_data.c b/hw/bsp/ra/boards/portenta_c33/ra_gen/pin_data.c
new file mode 100644
index 0000000000..fad79741a5
--- /dev/null
+++ b/hw/bsp/ra/boards/portenta_c33/ra_gen/pin_data.c
@@ -0,0 +1,71 @@
+/* generated pin source file - do not edit */
+#include "bsp_api.h"
+#include "r_ioport.h"
+
+
+const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = {
+ {
+ .pin = BSP_IO_PORT_01_PIN_07,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+ },
+ {
+ .pin = BSP_IO_PORT_01_PIN_08,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG)
+ },
+ {
+ .pin = BSP_IO_PORT_03_PIN_00,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG)
+ },
+ {
+ .pin = BSP_IO_PORT_04_PIN_07,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)
+ },
+ {
+ .pin = BSP_IO_PORT_04_PIN_08,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT | (uint32_t) IOPORT_CFG_PULLUP_ENABLE)
+ },
+ {
+ .pin = BSP_IO_PORT_11_PIN_01,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_HS)
+ },
+};
+
+const ioport_cfg_t g_bsp_pin_cfg = {
+ .number_of_pins = sizeof(g_bsp_pin_cfg_data)/sizeof(ioport_pin_cfg_t),
+ .p_pin_cfg_data = &g_bsp_pin_cfg_data[0],
+};
+
+#if BSP_TZ_SECURE_BUILD
+
+void R_BSP_PinCfgSecurityInit(void);
+
+/* Initialize SAR registers for secure pins. */
+void R_BSP_PinCfgSecurityInit(void)
+{
+ #if (2U == BSP_FEATURE_IOPORT_VERSION)
+ uint32_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR];
+ #else
+ uint16_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR];
+ #endif
+ memset(pmsar, 0xFF, BSP_FEATURE_BSP_NUM_PMSAR * sizeof(R_PMISC->PMSAR[0]));
+
+
+ for(uint32_t i = 0; i < g_bsp_pin_cfg.number_of_pins; i++)
+ {
+ uint32_t port_pin = g_bsp_pin_cfg.p_pin_cfg_data[i].pin;
+ uint32_t port = port_pin >> 8U;
+ uint32_t pin = port_pin & 0xFFU;
+ pmsar[port] &= (uint16_t) ~(1U << pin);
+ }
+
+ for(uint32_t i = 0; i < BSP_FEATURE_BSP_NUM_PMSAR; i++)
+ {
+ #if (2U == BSP_FEATURE_IOPORT_VERSION)
+ R_PMISC->PMSAR[i].PMSAR = (uint16_t) pmsar[i];
+ #else
+ R_PMISC->PMSAR[i].PMSAR = pmsar[i];
+ #endif
+ }
+
+}
+#endif
diff --git a/hw/bsp/ra/linker/gcc/fsp.ld b/hw/bsp/ra/boards/portenta_c33/script/fsp.ld
similarity index 78%
rename from hw/bsp/ra/linker/gcc/fsp.ld
rename to hw/bsp/ra/boards/portenta_c33/script/fsp.ld
index 453d46f241..605eef7d2c 100644
--- a/hw/bsp/ra/linker/gcc/fsp.ld
+++ b/hw/bsp/ra/boards/portenta_c33/script/fsp.ld
@@ -1,3 +1,9 @@
+/*
+ Linker File for Renesas FSP
+*/
+
+INCLUDE memory_regions.ld
+
/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/
/*
XIP_SECONDARY_SLOT_IMAGE = 1;
@@ -14,8 +20,6 @@ ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0;
ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0;
DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0;
DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0;
-NS_OFFSET_START = DEFINED(NS_OFFSET_START) ? NS_OFFSET_START : 0;
-NS_IMAGE_OFFSET = DEFINED(PROJECT_NONSECURE) ? NS_OFFSET_START : 0;
RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0;
RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0;
RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH;
@@ -32,20 +36,21 @@ PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)
USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE);
__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
- FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH :
- FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH;
+ FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH :
+ (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH :
+ FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH;
__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH;
__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH;
__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
- FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH;
+ FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH;
__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH;
__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
__bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH;
__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
- __bl_FLASH_NS_START - FLASH_APPLICATION_NSC_LENGTH;
+ __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH;
__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH :
RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH;
@@ -55,7 +60,7 @@ __bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
__bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2;
-__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START;
+__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START);
__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2;
@@ -67,30 +72,34 @@ FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START :
LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH :
DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH :
FLASH_LENGTH;
+OPTION_SETTING_SAS_SIZE = 0x34;
+OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 :
+ OPTION_SETTING_LENGTH == 0 ? 0 :
+ OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE;
/* Define memory regions. */
MEMORY
{
- ITCM (rx) : ORIGIN = ITCM_START + NS_IMAGE_OFFSET, LENGTH = ITCM_LENGTH
- DTCM (rwx) : ORIGIN = DTCM_START + NS_IMAGE_OFFSET, LENGTH = DTCM_LENGTH
- FLASH (rx) : ORIGIN = FLASH_ORIGIN + NS_IMAGE_OFFSET, LENGTH = LIMITED_FLASH_LENGTH
- RAM (rwx) : ORIGIN = RAM_START + NS_IMAGE_OFFSET, LENGTH = RAM_LENGTH
- DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START + NS_IMAGE_OFFSET, LENGTH = DATA_FLASH_LENGTH
- QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH
- OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH
- OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH
- OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH
- OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH
- SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH
- OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START + NS_IMAGE_OFFSET, LENGTH = OPTION_SETTING_LENGTH
- OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START + NS_IMAGE_OFFSET, LENGTH = 0x18
- OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + NS_IMAGE_OFFSET + 0x34, LENGTH = OPTION_SETTING_LENGTH - 0x34
- OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START + NS_IMAGE_OFFSET, LENGTH = OPTION_SETTING_S_LENGTH
- ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH
+ ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH
+ DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH
+ FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH
+ RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH
+ DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH
+ QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH
+ OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH
+ OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH
+ OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH
+ OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH
+ SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH
+ OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH
+ OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18
+ OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH
+ OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH
+ ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH
}
/* Library configurations */
-GROUP(libgcc.a libc.a libm.a libnosys.a)
+GROUP(libgcc.a libc.a libm.a)
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
@@ -144,27 +153,6 @@ ENTRY(Reset_Handler)
SECTIONS
{
- /* Initialized ITCM data. */
- .itcm_data :
- {
- /* Start of ITCM Secure Trustzone region. */
- __tz_ITCM_S = ABSOLUTE(ITCM_START);
-
- /* All ITCM data start */
- __itcm_data_start__ = .;
-
- KEEP(*(.itcm_data*))
-
- /* All ITCM data end */
- __itcm_data_end__ = .;
-
- /*
- * Start of the ITCM Non-Secure Trustzone region.
- * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects.
- */
- __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end__, 8192);
- } > ITCM
-
.text :
{
__tz_FLASH_S = ABSOLUTE(FLASH_START);
@@ -177,6 +165,10 @@ SECTIONS
KEEP(*(.application_vectors*))
__Vectors_End = .;
+ /* Some devices have a gap of code flash between the vector table and ROM Registers.
+ * The flash gap section allows applications to place code and data in this section. */
+ *(.flash_gap*)
+
/* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */
. = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400;
KEEP(*(.rom_registers*))
@@ -187,7 +179,6 @@ SECTIONS
/* Allocate flash write-boundary-aligned
* space for sce9 wrapped public keys for mcuboot if the module is used.
*/
- . = ALIGN(128);
KEEP(*(.mcuboot_sce9_key*))
*(.text*)
@@ -233,16 +224,54 @@ SECTIONS
__Vectors_Size = __Vectors_End - __Vectors;
- .ARM.extab :
+ . = .;
+ __itcm_data_pre_location = .;
+
+ /* Initialized ITCM data. */
+ /* Aligned to FCACHE2 for RA8. */
+ .itcm_data : ALIGN(16)
{
- *(.ARM.extab* .gnu.linkonce.armextab.*)
- } > FLASH
+ /* Start of ITCM Secure Trustzone region. */
+ __tz_ITCM_S = ABSOLUTE(ITCM_START);
+
+ /* All ITCM data start */
+ __itcm_data_start = .;
+
+ KEEP(*(.itcm_data*))
+
+ /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */
+ . = ALIGN(8);
+
+ /* All ITCM data end */
+ __itcm_data_end = .;
+
+ /*
+ * Start of the ITCM Non-Secure Trustzone region.
+ * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects.
+ */
+ __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192);
+ } > ITCM AT > FLASH = 0x00
+
+ /* Addresses exported for ITCM initialization. */
+ __itcm_data_init_start = LOADADDR(.itcm_data);
+ __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data);
+
+ ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.")
+ ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.")
+ ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.")
+ ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.")
+
+ /* Restore location counter. */
+ /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */
+ /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */
+ . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location;
__exidx_start = .;
- .ARM.exidx :
+ /DISCARD/ :
{
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
- } > FLASH
+ }
__exidx_end = .;
/* To copy multiple ROM to RAM sections,
@@ -337,50 +366,76 @@ SECTIONS
} > RAM AT > FLASH
- /* Start address of the initial values for .dtcm_data. */
- __dtcm_data_init_start = __etext + __data_end__ - __data_start__;
+ . = .;
+ __dtcm_data_pre_location = LOADADDR(.data) + SIZEOF(.data);
/* Initialized DTCM data. */
- .dtcm_data :
+ /* Aligned to FCACHE2 for RA8. */
+ .dtcm_data : ALIGN(16)
{
/* Start of DTCM Secure Trustzone region. */
__tz_DTCM_S = ABSOLUTE(DTCM_START);
/* Initialized DTCM data start */
- __dtcm_data_start__ = .;
+ __dtcm_data_start = .;
KEEP(*(.dtcm_data*))
+ /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */
+ . = ALIGN(8);
+
/* Initialized DTCM data end */
- __dtcm_data_end__ = .;
- } > DTCM AT > FLASH
+ __dtcm_data_end = .;
+ } > DTCM AT > FLASH = 0x00
+ . = __dtcm_data_end;
/* Uninitialized DTCM data. */
- .dtcm_noinit (NOLOAD):
+ /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */
+ .dtcm_bss ALIGN(8) (NOLOAD) :
{
/* Uninitialized DTCM data start */
- __dtcm_noinit_start = .;
+ __dtcm_bss_start = .;
- KEEP(*(.dtcm_noinit*))
+ KEEP(*(.dtcm_bss*))
+
+ /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */
+ . = ALIGN(8);
/* Uninitialized DTCM data end */
- __dtcm_noinit_end = .;
+ __dtcm_bss_end = .;
/*
* Start of the DTCM Non-Secure Trustzone region.
- * DTCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects.
+ * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects.
*/
- __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_noinit_end, 8192);
+ __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192);
} > DTCM
- /* TrustZone Secure Gateway Stubs Section. */
+ /* Addresses exported for DTCM initialization. */
+ __dtcm_data_init_start = LOADADDR(.dtcm_data);
+ __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data);
+
+ ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.")
+ ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.")
+ ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).")
+ ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.")
+ ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.")
+ ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.")
+ ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.")
+ ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.")
+
+ /* Restore location counter. */
+ /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */
+ /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */
+ . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location;
- /* Some arithmetic is needed to eliminate unnecessary FILL for secure projects. */
- /* 1. Get the address to the next block after the .data section in FLASH. */
- DATA_END = LOADADDR(.data) + SIZEOF(.data);
- /* 2. Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block after .data */
- SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(DATA_END, 1024);
- /* 3. Manually specify the start location for .gnu.sgstubs */
+ /* TrustZone Secure Gateway Stubs Section */
+
+ /* Store location counter for SPI non-retentive sections. */
+ sgstubs_pre_location = .;
+
+ /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */
+ SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024);
.gnu.sgstubs SGSTUBS_LOC : ALIGN(1024)
{
__tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024);
@@ -407,8 +462,8 @@ SECTIONS
__qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__;
/* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */
- __qspi_flash_code_addr__ = __etext + (__data_end__ - __data_start__);
- .qspi_non_retentive : AT (__qspi_flash_code_addr__)
+ __qspi_flash_code_addr__ = sgstubs_pre_location;
+ .qspi_non_retentive : AT(__qspi_flash_code_addr__)
{
__qspi_non_retentive_start__ = .;
KEEP(*(.qspi_non_retentive*))
@@ -456,8 +511,8 @@ SECTIONS
__ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__;
/* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */
- __ospi_device_0_code_addr__ = __etext + (__data_end__ - __data_start__);
- .ospi_device_0_non_retentive : AT (__ospi_device_0_code_addr__)
+ __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive));
+ .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__)
{
__ospi_device_0_non_retentive_start__ = .;
KEEP(*(.ospi_device_0_non_retentive*))
@@ -486,8 +541,8 @@ SECTIONS
__ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__;
/* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */
- __ospi_device_1_code_addr__ = __etext + (__data_end__ - __data_start__);
- .ospi_device_1_non_retentive : AT (__ospi_device_1_code_addr__)
+ __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive));
+ .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__)
{
__ospi_device_1_non_retentive_start__ = .;
KEEP(*(.ospi_device_1_non_retentive*))
@@ -527,7 +582,6 @@ SECTIONS
{
. = ALIGN(8);
__HeapBase = .;
- PROVIDE(end = .);
/* Place the STD heap here. */
KEEP(*(.heap))
__HeapLimit = .;
@@ -615,7 +669,6 @@ SECTIONS
__ID_Code_End = .;
} > ID_CODE
-
/* Symbol required for RA Configuration tool. */
__tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS);
diff --git a/hw/bsp/ra/boards/portenta_c33/script/memory_regions.ld b/hw/bsp/ra/boards/portenta_c33/script/memory_regions.ld
new file mode 100644
index 0000000000..74c6483297
--- /dev/null
+++ b/hw/bsp/ra/boards/portenta_c33/script/memory_regions.ld
@@ -0,0 +1,25 @@
+
+ /* generated memory regions file - do not edit */
+ RAM_START = 0x20000000;
+ RAM_LENGTH = 0x80000;
+ FLASH_START = 0x00000000;
+ FLASH_LENGTH = 0x200000;
+ DATA_FLASH_START = 0x08000000;
+ DATA_FLASH_LENGTH = 0x2000;
+ OPTION_SETTING_START = 0x0100A100;
+ OPTION_SETTING_LENGTH = 0x100;
+ OPTION_SETTING_S_START = 0x0100A200;
+ OPTION_SETTING_S_LENGTH = 0x100;
+ ID_CODE_START = 0x00000000;
+ ID_CODE_LENGTH = 0x0;
+ SDRAM_START = 0x80010000;
+ SDRAM_LENGTH = 0x0;
+ QSPI_FLASH_START = 0x60000000;
+ QSPI_FLASH_LENGTH = 0x4000000;
+ OSPI_DEVICE_0_START = 0x68000000;
+ OSPI_DEVICE_0_LENGTH = 0x8000000;
+ OSPI_DEVICE_1_START = 0x70000000;
+ OSPI_DEVICE_1_LENGTH = 0x10000000;
+
+/* Board has bootloader */
+FLASH_IMAGE_START = 0x10000;
diff --git a/hw/bsp/ra/boards/portenta_c33/smart_configurator/configuration.xml b/hw/bsp/ra/boards/portenta_c33/smart_configurator/configuration.xml
new file mode 100644
index 0000000000..fcc9d711d7
--- /dev/null
+++ b/hw/bsp/ra/boards/portenta_c33/smart_configurator/configuration.xml
@@ -0,0 +1,240 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Board Support Package Common Files
+ Renesas.RA.5.6.0.pack
+
+
+ I/O Port
+ Renesas.RA.5.6.0.pack
+
+
+ Arm CMSIS Version 6 - Core (M)
+ Arm.CMSIS6.6.1.0+fsp.5.6.0.pack
+
+
+ Custom Board Support Files
+ Renesas.RA_board_custom.5.6.0.pack
+
+
+ Board support package for R7FA6M5BH3CFC
+ Renesas.RA_mcu_ra6m5.5.6.0.pack
+
+
+ Board support package for RA6M5
+ Renesas.RA_mcu_ra6m5.5.6.0.pack
+
+
+ Board support package for RA6M5 - FSP Data
+ Renesas.RA_mcu_ra6m5.5.6.0.pack
+
+
+ Board support package for RA6M5 - Events
+ Renesas.RA_mcu_ra6m5.5.6.0.pack
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/hw/bsp/ra/boards/ra2a1_ek/board.h b/hw/bsp/ra/boards/ra2a1_ek/board.h
index 1c2b666d2d..ba663d040e 100644
--- a/hw/bsp/ra/boards/ra2a1_ek/board.h
+++ b/hw/bsp/ra/boards/ra2a1_ek/board.h
@@ -31,21 +31,9 @@
extern "C" {
#endif
-#define LED1 BSP_IO_PORT_02_PIN_05
-#define LED_STATE_ON 1
-
-#define SW1 BSP_IO_PORT_02_PIN_06
+#define LED_STATE_ON 1
#define BUTTON_STATE_ACTIVE 0
-static const ioport_pin_cfg_t board_pin_cfg[] = {
- {.pin = LED1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_OUTPUT},
- {.pin = SW1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_INPUT},
- // USB FS D+, D-, VBus
- {.pin = BSP_IO_PORT_04_PIN_07, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS},
- {.pin = BSP_IO_PORT_09_PIN_14, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS},
- {.pin = BSP_IO_PORT_09_PIN_15, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS},
-};
-
#ifdef __cplusplus
}
#endif
diff --git a/hw/bsp/ra/boards/ra2a1_ek/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/ra2a1_ek/fsp_cfg/bsp/bsp_cfg.h
deleted file mode 100644
index 30637c17b1..0000000000
--- a/hw/bsp/ra/boards/ra2a1_ek/fsp_cfg/bsp/bsp_cfg.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/* generated configuration header file - do not edit */
-#ifndef BSP_CFG_H_
-#define BSP_CFG_H_
-#ifdef __cplusplus
- extern "C" {
- #endif
-
-#include "bsp_clock_cfg.h"
-#include "bsp_mcu_family_cfg.h"
-#include "board_cfg.h"
-#define RA_NOT_DEFINED 0
-#ifndef BSP_CFG_RTOS
-#if (RA_NOT_DEFINED) != (RA_NOT_DEFINED)
- #define BSP_CFG_RTOS (2)
- #elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED)
- #define BSP_CFG_RTOS (1)
- #else
-#define BSP_CFG_RTOS (0)
-#endif
-#endif
-#ifndef BSP_CFG_RTC_USED
-#define BSP_CFG_RTC_USED (RA_NOT_DEFINED)
-#endif
-#undef RA_NOT_DEFINED
-#if defined(_RA_BOOT_IMAGE)
- #define BSP_CFG_BOOT_IMAGE (1)
- #endif
-#define BSP_CFG_MCU_VCC_MV (3300)
-#define BSP_CFG_STACK_MAIN_BYTES (0x400)
-#define BSP_CFG_HEAP_BYTES (0x400)
-#define BSP_CFG_PARAM_CHECKING_ENABLE (1)
-#define BSP_CFG_ASSERT (0)
-#define BSP_CFG_ERROR_LOG (0)
-
-#define BSP_CFG_PFS_PROTECT ((1))
-
-#define BSP_CFG_C_RUNTIME_INIT ((1))
-#define BSP_CFG_EARLY_INIT ((0))
-
-#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0))
-
-#ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED
-#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1)
-#endif
-
-#ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE
-#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0)
-#endif
-#ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE
-#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0)
-#endif
-#ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED
-#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1)
-#endif
-#ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS
-#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
-#endif
-
-#ifdef __cplusplus
- }
- #endif
-#endif /* BSP_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra2a1_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/hw/bsp/ra/boards/ra2a1_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
deleted file mode 100644
index 710e85b28b..0000000000
--- a/hw/bsp/ra/boards/ra2a1_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/* generated configuration header file - do not edit */
-#ifndef BSP_MCU_DEVICE_PN_CFG_H_
-#define BSP_MCU_DEVICE_PN_CFG_H_
-#define BSP_MCU_R7FA2A1AB3CFM
-#define BSP_MCU_FEATURE_SET ('A')
-#define BSP_ROM_SIZE_BYTES (262144)
-#define BSP_RAM_SIZE_BYTES (32768)
-#define BSP_DATA_FLASH_SIZE_BYTES (8192)
-#define BSP_PACKAGE_LQFP
-#define BSP_PACKAGE_PINS (64)
-#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra2a1_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/ra2a1_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h
deleted file mode 100644
index 6caef62cc6..0000000000
--- a/hw/bsp/ra/boards/ra2a1_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h
+++ /dev/null
@@ -1,84 +0,0 @@
-/* generated configuration header file - do not edit */
-#ifndef BSP_MCU_FAMILY_CFG_H_
-#define BSP_MCU_FAMILY_CFG_H_
-#ifdef __cplusplus
- extern "C" {
- #endif
-
-#include "bsp_mcu_device_pn_cfg.h"
-#include "bsp_mcu_device_cfg.h"
-#include "../../../ra/fsp/src/bsp/mcu/ra2a1/bsp_mcu_info.h"
-#include "bsp_clock_cfg.h"
-#define BSP_MCU_GROUP_RA2A1 (1)
-#define BSP_LOCO_HZ (32768)
-#define BSP_MOCO_HZ (8000000)
-#define BSP_SUB_CLOCK_HZ (32768)
-#if BSP_CFG_HOCO_FREQUENCY == 0
-#define BSP_HOCO_HZ (24000000)
-#elif BSP_CFG_HOCO_FREQUENCY == 2
- #define BSP_HOCO_HZ (32000000)
- #elif BSP_CFG_HOCO_FREQUENCY == 4
- #define BSP_HOCO_HZ (48000000)
- #elif BSP_CFG_HOCO_FREQUENCY == 5
- #define BSP_HOCO_HZ (64000000)
- #else
- #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h"
- #endif
-
-#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U)
-#define BSP_VECTOR_TABLE_MAX_ENTRIES (48U)
-
-#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2)
-#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10)
-#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17)
-#define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26)
-#define OFS_SEQ5 (1 << 28) | (1 << 30)
-#define BSP_CFG_USE_LOW_VOLTAGE_MODE ((0))
-#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
-#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEC3 | (1 << 2) | (3 << 3) | (0 << 8))
-#define BSP_CFG_ROM_REG_MPU_PC0_ENABLE (1)
-#define BSP_CFG_ROM_REG_MPU_PC0_START (0x000FFFFC)
-#define BSP_CFG_ROM_REG_MPU_PC0_END (0x000FFFFF)
-#define BSP_CFG_ROM_REG_MPU_PC1_ENABLE (1)
-#define BSP_CFG_ROM_REG_MPU_PC1_START (0x000FFFFC)
-#define BSP_CFG_ROM_REG_MPU_PC1_END (0x000FFFFF)
-#define BSP_CFG_ROM_REG_MPU_REGION0_ENABLE (1)
-#define BSP_CFG_ROM_REG_MPU_REGION0_START (0x000FFFFC)
-#define BSP_CFG_ROM_REG_MPU_REGION0_END (0x000FFFFF)
-#define BSP_CFG_ROM_REG_MPU_REGION1_ENABLE (1)
-#define BSP_CFG_ROM_REG_MPU_REGION1_START (0x200FFFFC)
-#define BSP_CFG_ROM_REG_MPU_REGION1_END (0x200FFFFF)
-#define BSP_CFG_ROM_REG_MPU_REGION2_ENABLE (1)
-#define BSP_CFG_ROM_REG_MPU_REGION2_START (0x407FFFFC)
-#define BSP_CFG_ROM_REG_MPU_REGION2_END (0x407FFFFF)
-#define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1)
-#define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC)
-#define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF)
-#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT
-#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9)
-#endif
-/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */
-#define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector)
-
-/*
- ID Code
- Note: To permanently lock and disable the debug interface define the BSP_ID_CODE_PERMANENTLY_LOCKED in the compiler settings.
- WARNING: This will disable debug access to the part and cannot be reversed by a debug probe.
- */
-#if defined(BSP_ID_CODE_PERMANENTLY_LOCKED)
- #define BSP_CFG_ID_CODE_LONG_1 (0x00000000)
- #define BSP_CFG_ID_CODE_LONG_2 (0x00000000)
- #define BSP_CFG_ID_CODE_LONG_3 (0x00000000)
- #define BSP_CFG_ID_CODE_LONG_4 (0x00000000)
- #else
-/* ID CODE: FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF */
-#define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF)
-#define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF)
-#define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF)
-#define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF)
-#endif
-
-#ifdef __cplusplus
- }
- #endif
-#endif /* BSP_MCU_FAMILY_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h
new file mode 100644
index 0000000000..bf1fe0cc68
--- /dev/null
+++ b/hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h
@@ -0,0 +1,62 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_CFG_H_
+#define BSP_CFG_H_
+#ifdef __cplusplus
+ extern "C" {
+ #endif
+
+ #include "bsp_clock_cfg.h"
+ #include "bsp_mcu_family_cfg.h"
+ #include "board_cfg.h"
+ #define RA_NOT_DEFINED 0
+ #ifndef BSP_CFG_RTOS
+ #if (RA_NOT_DEFINED) != (RA_NOT_DEFINED)
+ #define BSP_CFG_RTOS (2)
+ #elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED)
+ #define BSP_CFG_RTOS (1)
+ #else
+ #define BSP_CFG_RTOS (0)
+ #endif
+ #endif
+ #ifndef BSP_CFG_RTC_USED
+ #define BSP_CFG_RTC_USED (RA_NOT_DEFINED)
+ #endif
+ #undef RA_NOT_DEFINED
+ #if defined(_RA_BOOT_IMAGE)
+ #define BSP_CFG_BOOT_IMAGE (1)
+ #endif
+ #define BSP_CFG_MCU_VCC_MV (3300)
+ #define BSP_CFG_STACK_MAIN_BYTES (0x400)
+ #define BSP_CFG_HEAP_BYTES (0x400)
+ #define BSP_CFG_PARAM_CHECKING_ENABLE (0)
+ #define BSP_CFG_ASSERT (0)
+ #define BSP_CFG_ERROR_LOG (0)
+
+ #define BSP_CFG_PFS_PROTECT ((1))
+
+ #define BSP_CFG_C_RUNTIME_INIT ((1))
+ #define BSP_CFG_EARLY_INIT ((0))
+
+ #define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0))
+
+ #ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED
+ #define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1)
+ #endif
+
+ #ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE
+ #define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0)
+ #endif
+ #ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE
+ #define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0)
+ #endif
+ #ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED
+ #define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1)
+ #endif
+ #ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS
+ #define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
+ #endif
+
+ #ifdef __cplusplus
+ }
+ #endif
+#endif /* BSP_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra2a1_ek/fsp_cfg/bsp/bsp_mcu_device_cfg.h b/hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h
similarity index 100%
rename from hw/bsp/ra/boards/ra2a1_ek/fsp_cfg/bsp/bsp_mcu_device_cfg.h
rename to hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h
diff --git a/hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
new file mode 100644
index 0000000000..6970e4c339
--- /dev/null
+++ b/hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
@@ -0,0 +1,11 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_MCU_DEVICE_PN_CFG_H_
+#define BSP_MCU_DEVICE_PN_CFG_H_
+#define BSP_MCU_R7FA2A1AB3CFM
+ #define BSP_MCU_FEATURE_SET ('A')
+ #define BSP_ROM_SIZE_BYTES (262144)
+ #define BSP_RAM_SIZE_BYTES (32768)
+ #define BSP_DATA_FLASH_SIZE_BYTES (8192)
+ #define BSP_PACKAGE_LQFP
+ #define BSP_PACKAGE_PINS (64)
+#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h
new file mode 100644
index 0000000000..24e3efaa2f
--- /dev/null
+++ b/hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h
@@ -0,0 +1,89 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_MCU_FAMILY_CFG_H_
+#define BSP_MCU_FAMILY_CFG_H_
+#ifdef __cplusplus
+ extern "C" {
+ #endif
+
+ #include "bsp_mcu_device_pn_cfg.h"
+ #include "bsp_mcu_device_cfg.h"
+ #include "../../../ra/fsp/src/bsp/mcu/ra2a1/bsp_mcu_info.h"
+ #include "bsp_clock_cfg.h"
+ #define BSP_MCU_GROUP_RA2A1 (1)
+ #define BSP_LOCO_HZ (32768)
+ #define BSP_MOCO_HZ (8000000)
+ #define BSP_SUB_CLOCK_HZ (32768)
+ #if BSP_CFG_HOCO_FREQUENCY == 0
+ #define BSP_HOCO_HZ (24000000)
+ #elif BSP_CFG_HOCO_FREQUENCY == 2
+ #define BSP_HOCO_HZ (32000000)
+ #elif BSP_CFG_HOCO_FREQUENCY == 4
+ #define BSP_HOCO_HZ (48000000)
+ #elif BSP_CFG_HOCO_FREQUENCY == 5
+ #define BSP_HOCO_HZ (64000000)
+ #else
+ #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h"
+ #endif
+
+ #define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U)
+ #define BSP_VECTOR_TABLE_MAX_ENTRIES (48U)
+ #define BSP_CFG_INLINE_IRQ_FUNCTIONS (0)
+
+ #define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2)
+ #define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10)
+ #define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17)
+ #define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26)
+ #define OFS_SEQ5 (1 << 28) | (1 << 30)
+ #define BSP_CFG_USE_LOW_VOLTAGE_MODE ((0))
+ #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
+ #define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEC3 | (1 << 2) | (3 << 3) | (0 << 8))
+ #define BSP_CFG_ROM_REG_MPU_PC0_ENABLE (1)
+ #define BSP_CFG_ROM_REG_MPU_PC0_START (0x000FFFFC)
+ #define BSP_CFG_ROM_REG_MPU_PC0_END (0x000FFFFF)
+ #define BSP_CFG_ROM_REG_MPU_PC1_ENABLE (1)
+ #define BSP_CFG_ROM_REG_MPU_PC1_START (0x000FFFFC)
+ #define BSP_CFG_ROM_REG_MPU_PC1_END (0x000FFFFF)
+ #define BSP_CFG_ROM_REG_MPU_REGION0_ENABLE (1)
+ #define BSP_CFG_ROM_REG_MPU_REGION0_START (0x000FFFFC)
+ #define BSP_CFG_ROM_REG_MPU_REGION0_END (0x000FFFFF)
+ #define BSP_CFG_ROM_REG_MPU_REGION1_ENABLE (1)
+ #define BSP_CFG_ROM_REG_MPU_REGION1_START (0x200FFFFC)
+ #define BSP_CFG_ROM_REG_MPU_REGION1_END (0x200FFFFF)
+ #define BSP_CFG_ROM_REG_MPU_REGION2_ENABLE (1)
+ #define BSP_CFG_ROM_REG_MPU_REGION2_START (0x407FFFFC)
+ #define BSP_CFG_ROM_REG_MPU_REGION2_END (0x407FFFFF)
+ #define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1)
+ #define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC)
+ #define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF)
+ #ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT
+ #define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9)
+ #endif
+ /* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */
+ #define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector)
+
+ /*
+ ID Code
+ Note: To lock and disable the debug interface define BSP_ID_CODE_LOCKED in compiler settings.
+ WARNING: This will disable debug access to the part. However, ALeRASE command will be accepted, which will clear (reset) the ID code. After clearing ID code, debug access will be enabled.
+ */
+ #if defined(BSP_ID_CODE_LOCKED)
+ #define BSP_CFG_ID_CODE_LONG_1 (0x00000000)
+ #define BSP_CFG_ID_CODE_LONG_2 (0x00000000)
+ #define BSP_CFG_ID_CODE_LONG_3 (0x00000000)
+ #define BSP_CFG_ID_CODE_LONG_4 (0x00000000)
+ #else
+ /* ID CODE: FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF */
+ #define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF)
+ #define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF)
+ #define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF)
+ #define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF)
+ #endif
+
+ #if (0)
+ #define BSP_SECTION_FLASH_GAP BSP_PLACE_IN_SECTION(".flash_gap")
+ #endif
+
+ #ifdef __cplusplus
+ }
+ #endif
+#endif /* BSP_MCU_FAMILY_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h b/hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h
new file mode 100644
index 0000000000..fc48a5809e
--- /dev/null
+++ b/hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h
@@ -0,0 +1,17 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_PIN_CFG_H_
+#define BSP_PIN_CFG_H_
+#include "r_ioport.h"
+
+/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+#define LED1 (BSP_IO_PORT_02_PIN_05)
+#define SW1 (BSP_IO_PORT_02_PIN_06)
+extern const ioport_cfg_t g_bsp_pin_cfg; /* RA2A1-EK.pincfg */
+
+void BSP_PinConfigSecurityInit();
+
+/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+#endif /* BSP_PIN_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h b/hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h
new file mode 100644
index 0000000000..d2688bf5ba
--- /dev/null
+++ b/hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h
@@ -0,0 +1,13 @@
+/* generated configuration header file - do not edit */
+#ifndef R_IOPORT_CFG_H_
+#define R_IOPORT_CFG_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* R_IOPORT_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra2a1_ek/fsp_cfg/bsp_clock_cfg.h b/hw/bsp/ra/boards/ra2a1_ek/ra_gen/bsp_clock_cfg.h
similarity index 92%
rename from hw/bsp/ra/boards/ra2a1_ek/fsp_cfg/bsp_clock_cfg.h
rename to hw/bsp/ra/boards/ra2a1_ek/ra_gen/bsp_clock_cfg.h
index cd9d135f79..6b41669d3c 100644
--- a/hw/bsp/ra/boards/ra2a1_ek/fsp_cfg/bsp_clock_cfg.h
+++ b/hw/bsp/ra/boards/ra2a1_ek/ra_gen/bsp_clock_cfg.h
@@ -8,7 +8,7 @@
#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_HOCO) /* Clock Src: HOCO */
#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* ICLK Div /1 */
#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKB Div /2 */
-#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKD Div /2 */
+#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKD Div /1 */
#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* FCLK Div /2 */
#define BSP_CFG_SDADC_CLOCK_SOURCE (0) /* SDADCCLK Src: HOCO */
#define BSP_CFG_SDADCCLK_DIV (7) /* SDADCCLK Div /12 */
diff --git a/hw/bsp/ra/boards/ra2a1_ek/ra_gen/common_data.c b/hw/bsp/ra/boards/ra2a1_ek/ra_gen/common_data.c
new file mode 100644
index 0000000000..50036c0adc
--- /dev/null
+++ b/hw/bsp/ra/boards/ra2a1_ek/ra_gen/common_data.c
@@ -0,0 +1,11 @@
+/* generated common source file - do not edit */
+#include "common_data.h"
+ioport_instance_ctrl_t g_ioport_ctrl;
+const ioport_instance_t g_ioport =
+ {
+ .p_api = &g_ioport_on_ioport,
+ .p_ctrl = &g_ioport_ctrl,
+ .p_cfg = &g_bsp_pin_cfg,
+ };
+void g_common_init(void) {
+}
diff --git a/hw/bsp/ra/boards/ra2a1_ek/ra_gen/common_data.h b/hw/bsp/ra/boards/ra2a1_ek/ra_gen/common_data.h
new file mode 100644
index 0000000000..6a08cbee09
--- /dev/null
+++ b/hw/bsp/ra/boards/ra2a1_ek/ra_gen/common_data.h
@@ -0,0 +1,20 @@
+/* generated common header file - do not edit */
+#ifndef COMMON_DATA_H_
+#define COMMON_DATA_H_
+#include
+#include "bsp_api.h"
+#include "r_ioport.h"
+#include "bsp_pin_cfg.h"
+FSP_HEADER
+#define IOPORT_CFG_NAME g_bsp_pin_cfg
+#define IOPORT_CFG_OPEN R_IOPORT_Open
+#define IOPORT_CFG_CTRL g_ioport_ctrl
+
+/* IOPORT Instance */
+extern const ioport_instance_t g_ioport;
+
+/* IOPORT control structure. */
+extern ioport_instance_ctrl_t g_ioport_ctrl;
+void g_common_init(void);
+FSP_FOOTER
+#endif /* COMMON_DATA_H_ */
diff --git a/hw/bsp/ra/boards/ra2a1_ek/ra_gen/pin_data.c b/hw/bsp/ra/boards/ra2a1_ek/ra_gen/pin_data.c
new file mode 100644
index 0000000000..7fed326876
--- /dev/null
+++ b/hw/bsp/ra/boards/ra2a1_ek/ra_gen/pin_data.c
@@ -0,0 +1,115 @@
+/* generated pin source file - do not edit */
+#include "bsp_api.h"
+#include "r_ioport.h"
+
+
+const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = {
+ {
+ .pin = BSP_IO_PORT_00_PIN_01,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_CTSU)
+ },
+ {
+ .pin = BSP_IO_PORT_00_PIN_03,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE)
+ },
+ {
+ .pin = BSP_IO_PORT_01_PIN_08,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG)
+ },
+ {
+ .pin = BSP_IO_PORT_01_PIN_11,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
+ },
+ {
+ .pin = BSP_IO_PORT_01_PIN_12,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
+ },
+ {
+ .pin = BSP_IO_PORT_02_PIN_01,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT)
+ },
+ {
+ .pin = BSP_IO_PORT_02_PIN_04,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI0_2_4_6_8)
+ },
+ {
+ .pin = BSP_IO_PORT_02_PIN_05,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+ },
+ {
+ .pin = BSP_IO_PORT_02_PIN_06,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT | (uint32_t) IOPORT_CFG_PULLUP_ENABLE)
+ },
+ {
+ .pin = BSP_IO_PORT_03_PIN_00,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG)
+ },
+ {
+ .pin = BSP_IO_PORT_03_PIN_03,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
+ },
+ {
+ .pin = BSP_IO_PORT_03_PIN_04,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
+ },
+ {
+ .pin = BSP_IO_PORT_04_PIN_07,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)
+ },
+ {
+ .pin = BSP_IO_PORT_04_PIN_09,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_CTSU)
+ },
+ {
+ .pin = BSP_IO_PORT_04_PIN_11,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI0_2_4_6_8)
+ },
+ {
+ .pin = BSP_IO_PORT_09_PIN_14,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)
+ },
+ {
+ .pin = BSP_IO_PORT_09_PIN_15,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)
+ },
+};
+
+const ioport_cfg_t g_bsp_pin_cfg = {
+ .number_of_pins = sizeof(g_bsp_pin_cfg_data)/sizeof(ioport_pin_cfg_t),
+ .p_pin_cfg_data = &g_bsp_pin_cfg_data[0],
+};
+
+#if BSP_TZ_SECURE_BUILD
+
+void R_BSP_PinCfgSecurityInit(void);
+
+/* Initialize SAR registers for secure pins. */
+void R_BSP_PinCfgSecurityInit(void)
+{
+ #if (2U == BSP_FEATURE_IOPORT_VERSION)
+ uint32_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR];
+ #else
+ uint16_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR];
+ #endif
+ memset(pmsar, 0xFF, BSP_FEATURE_BSP_NUM_PMSAR * sizeof(R_PMISC->PMSAR[0]));
+
+
+ for(uint32_t i = 0; i < g_bsp_pin_cfg.number_of_pins; i++)
+ {
+ uint32_t port_pin = g_bsp_pin_cfg.p_pin_cfg_data[i].pin;
+ uint32_t port = port_pin >> 8U;
+ uint32_t pin = port_pin & 0xFFU;
+ pmsar[port] &= (uint16_t) ~(1U << pin);
+ }
+
+ for(uint32_t i = 0; i < BSP_FEATURE_BSP_NUM_PMSAR; i++)
+ {
+ #if (2U == BSP_FEATURE_IOPORT_VERSION)
+ R_PMISC->PMSAR[i].PMSAR = (uint16_t) pmsar[i];
+ #else
+ R_PMISC->PMSAR[i].PMSAR = pmsar[i];
+ #endif
+ }
+
+}
+#endif
diff --git a/hw/bsp/ra/boards/ra2a1_ek/script/fsp.ld b/hw/bsp/ra/boards/ra2a1_ek/script/fsp.ld
new file mode 100644
index 0000000000..605eef7d2c
--- /dev/null
+++ b/hw/bsp/ra/boards/ra2a1_ek/script/fsp.ld
@@ -0,0 +1,769 @@
+/*
+ Linker File for Renesas FSP
+*/
+
+INCLUDE memory_regions.ld
+
+/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/
+/*
+ XIP_SECONDARY_SLOT_IMAGE = 1;
+*/
+
+QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH);
+OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH);
+OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH);
+
+/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */
+__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0);
+
+ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0;
+ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0;
+DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0;
+DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0;
+RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0;
+RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0;
+RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH;
+RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH;
+
+OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80;
+
+/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings.
+ * Bootloader images do not configure option settings because they are owned by the bootloader.
+ * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */
+__bl_FSP_BOOTABLE_IMAGE = 1;
+__bln_FSP_BOOTABLE_IMAGE = 1;
+PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE);
+USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE);
+
+__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+ FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH :
+ (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH :
+ FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH;
+__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+ FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH;
+__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH;
+__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+ FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH;
+__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH;
+__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+ FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
+ __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH;
+__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+ FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
+ __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH;
+__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+ FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH :
+ RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH;
+__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+ FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH :
+ __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH;
+__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+ FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
+ __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2;
+__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START);
+__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+ FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
+ FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2;
+
+XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0;
+FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START :
+ XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START :
+ FLASH_IMAGE_START;
+LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH :
+ DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH :
+ FLASH_LENGTH;
+OPTION_SETTING_SAS_SIZE = 0x34;
+OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 :
+ OPTION_SETTING_LENGTH == 0 ? 0 :
+ OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE;
+
+/* Define memory regions. */
+MEMORY
+{
+ ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH
+ DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH
+ FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH
+ RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH
+ DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH
+ QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH
+ OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH
+ OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH
+ OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH
+ OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH
+ SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH
+ OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH
+ OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18
+ OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH
+ OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH
+ ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH
+}
+
+/* Library configurations */
+GROUP(libgcc.a libc.a libm.a)
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be DEFINED in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __copy_table_start__
+ * __copy_table_end__
+ * __zero_table_start__
+ * __zero_table_end__
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ * __Vectors_End
+ * __Vectors_Size
+ * __qspi_flash_start__
+ * __qspi_flash_end__
+ * __qspi_flash_code_size__
+ * __qspi_region_max_size__
+ * __qspi_region_start_address__
+ * __qspi_region_end_address__
+ * __ospi_device_0_start__
+ * __ospi_device_0_end__
+ * __ospi_device_0_code_size__
+ * __ospi_device_0_region_max_size__
+ * __ospi_device_0_region_start_address__
+ * __ospi_device_0_region_end_address__
+ * __ospi_device_1_start__
+ * __ospi_device_1_end__
+ * __ospi_device_1_code_size__
+ * __ospi_device_1_region_max_size__
+ * __ospi_device_1_region_start_address__
+ * __ospi_device_1_region_end_address__
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ __tz_FLASH_S = ABSOLUTE(FLASH_START);
+ __ROM_Start = .;
+
+ /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much
+ * space because ROM registers are at address 0x400 and there is very little space
+ * in between. */
+ KEEP(*(.fixed_vectors*))
+ KEEP(*(.application_vectors*))
+ __Vectors_End = .;
+
+ /* Some devices have a gap of code flash between the vector table and ROM Registers.
+ * The flash gap section allows applications to place code and data in this section. */
+ *(.flash_gap*)
+
+ /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */
+ . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400;
+ KEEP(*(.rom_registers*))
+
+ /* Reserving 0x100 bytes of space for ROM registers. */
+ . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x500;
+
+ /* Allocate flash write-boundary-aligned
+ * space for sce9 wrapped public keys for mcuboot if the module is used.
+ */
+ KEEP(*(.mcuboot_sce9_key*))
+
+ *(.text*)
+
+ KEEP(*(.version))
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+ __usb_dev_descriptor_start_fs = .;
+ KEEP(*(.usb_device_desc_fs*))
+ __usb_cfg_descriptor_start_fs = .;
+ KEEP(*(.usb_config_desc_fs*))
+ __usb_interface_descriptor_start_fs = .;
+ KEEP(*(.usb_interface_desc_fs*))
+ __usb_descriptor_end_fs = .;
+ __usb_dev_descriptor_start_hs = .;
+ KEEP(*(.usb_device_desc_hs*))
+ __usb_cfg_descriptor_start_hs = .;
+ KEEP(*(.usb_config_desc_hs*))
+ __usb_interface_descriptor_start_hs = .;
+ KEEP(*(.usb_interface_desc_hs*))
+ __usb_descriptor_end_hs = .;
+
+ KEEP(*(.eh_frame*))
+
+ __ROM_End = .;
+ } > FLASH = 0xFF
+
+ __Vectors_Size = __Vectors_End - __Vectors;
+
+ . = .;
+ __itcm_data_pre_location = .;
+
+ /* Initialized ITCM data. */
+ /* Aligned to FCACHE2 for RA8. */
+ .itcm_data : ALIGN(16)
+ {
+ /* Start of ITCM Secure Trustzone region. */
+ __tz_ITCM_S = ABSOLUTE(ITCM_START);
+
+ /* All ITCM data start */
+ __itcm_data_start = .;
+
+ KEEP(*(.itcm_data*))
+
+ /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */
+ . = ALIGN(8);
+
+ /* All ITCM data end */
+ __itcm_data_end = .;
+
+ /*
+ * Start of the ITCM Non-Secure Trustzone region.
+ * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects.
+ */
+ __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192);
+ } > ITCM AT > FLASH = 0x00
+
+ /* Addresses exported for ITCM initialization. */
+ __itcm_data_init_start = LOADADDR(.itcm_data);
+ __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data);
+
+ ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.")
+ ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.")
+ ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.")
+ ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.")
+
+ /* Restore location counter. */
+ /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */
+ /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */
+ . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location;
+
+ __exidx_start = .;
+ /DISCARD/ :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ }
+ __exidx_end = .;
+
+ /* To copy multiple ROM to RAM sections,
+ * uncomment .copy.table section and,
+ * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+ /*
+ .copy.table :
+ {
+ . = ALIGN(4);
+ __copy_table_start__ = .;
+ LONG (__etext)
+ LONG (__data_start__)
+ LONG (__data_end__ - __data_start__)
+ LONG (__etext2)
+ LONG (__data2_start__)
+ LONG (__data2_end__ - __data2_start__)
+ __copy_table_end__ = .;
+ } > FLASH
+ */
+
+ /* To clear multiple BSS sections,
+ * uncomment .zero.table section and,
+ * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+ /*
+ .zero.table :
+ {
+ . = ALIGN(4);
+ __zero_table_start__ = .;
+ LONG (__bss_start__)
+ LONG (__bss_end__ - __bss_start__)
+ LONG (__bss2_start__)
+ LONG (__bss2_end__ - __bss2_start__)
+ __zero_table_end__ = .;
+ } > FLASH
+ */
+
+ __etext = .;
+
+ __tz_RAM_S = ORIGIN(RAM);
+
+ /* If DTC is used, put the DTC vector table at the start of SRAM.
+ This avoids memory holes due to 1K alignment required by it. */
+ .fsp_dtc_vector_table (NOLOAD) :
+ {
+ . = ORIGIN(RAM);
+ *(.fsp_dtc_vector_table)
+ } > RAM
+
+ /* Initialized data section. */
+ .data :
+ {
+ __data_start__ = .;
+ . = ALIGN(4);
+
+ __Code_In_RAM_Start = .;
+
+ KEEP(*(.code_in_ram*))
+ __Code_In_RAM_End = .;
+
+ *(vtable)
+ /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */
+ *(.data.*)
+ *(.data)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+
+ . = ALIGN(4);
+
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM AT > FLASH
+
+ . = .;
+ __dtcm_data_pre_location = LOADADDR(.data) + SIZEOF(.data);
+
+ /* Initialized DTCM data. */
+ /* Aligned to FCACHE2 for RA8. */
+ .dtcm_data : ALIGN(16)
+ {
+ /* Start of DTCM Secure Trustzone region. */
+ __tz_DTCM_S = ABSOLUTE(DTCM_START);
+
+ /* Initialized DTCM data start */
+ __dtcm_data_start = .;
+
+ KEEP(*(.dtcm_data*))
+
+ /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */
+ . = ALIGN(8);
+
+ /* Initialized DTCM data end */
+ __dtcm_data_end = .;
+ } > DTCM AT > FLASH = 0x00
+
+ . = __dtcm_data_end;
+ /* Uninitialized DTCM data. */
+ /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */
+ .dtcm_bss ALIGN(8) (NOLOAD) :
+ {
+ /* Uninitialized DTCM data start */
+ __dtcm_bss_start = .;
+
+ KEEP(*(.dtcm_bss*))
+
+ /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */
+ . = ALIGN(8);
+
+ /* Uninitialized DTCM data end */
+ __dtcm_bss_end = .;
+
+ /*
+ * Start of the DTCM Non-Secure Trustzone region.
+ * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects.
+ */
+ __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192);
+ } > DTCM
+
+ /* Addresses exported for DTCM initialization. */
+ __dtcm_data_init_start = LOADADDR(.dtcm_data);
+ __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data);
+
+ ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.")
+ ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.")
+ ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).")
+ ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.")
+ ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.")
+ ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.")
+ ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.")
+ ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.")
+
+ /* Restore location counter. */
+ /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */
+ /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */
+ . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location;
+
+ /* TrustZone Secure Gateway Stubs Section */
+
+ /* Store location counter for SPI non-retentive sections. */
+ sgstubs_pre_location = .;
+
+ /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */
+ SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024);
+ .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024)
+ {
+ __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024);
+ _start_sg = .;
+ *(.gnu.sgstubs*)
+ . = ALIGN(32);
+ _end_sg = .;
+ } > FLASH
+
+ __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768);
+ FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N;
+
+ /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */
+ __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH);
+
+ /* QSPI_FLASH section to be downloaded via debugger */
+ .qspi_flash :
+ {
+ __qspi_flash_start__ = .;
+ KEEP(*(.qspi_flash*))
+ KEEP(*(.code_in_qspi*))
+ __qspi_flash_end__ = .;
+ } > QSPI_FLASH
+ __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__;
+
+ /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */
+ __qspi_flash_code_addr__ = sgstubs_pre_location;
+ .qspi_non_retentive : AT(__qspi_flash_code_addr__)
+ {
+ __qspi_non_retentive_start__ = .;
+ KEEP(*(.qspi_non_retentive*))
+ __qspi_non_retentive_end__ = .;
+ } > QSPI_FLASH
+ __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__;
+
+ __qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */
+ __qspi_region_start_address__ = __qspi_flash_start__;
+ __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__;
+
+ /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */
+ __tz_QSPI_FLASH_N = __qspi_non_retentive_end__;
+
+ /* Support for OctaRAM */
+ .OSPI_DEVICE_0_NO_LOAD (NOLOAD):
+ {
+ . = ALIGN(4);
+ __ospi_device_0_start__ = .;
+ *(.ospi_device_0_no_load*)
+ . = ALIGN(4);
+ __ospi_device_0_end__ = .;
+ } > OSPI_DEVICE_0_RAM
+
+ .OSPI_DEVICE_1_NO_LOAD (NOLOAD):
+ {
+ . = ALIGN(4);
+ __ospi_device_1_start__ = .;
+ *(.ospi_device_1_no_load*)
+ . = ALIGN(4);
+ __ospi_device_1_end__ = .;
+ } > OSPI_DEVICE_1_RAM
+
+ /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */
+ __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0);
+
+ /* OSPI_DEVICE_0 section to be downloaded via debugger */
+ .OSPI_DEVICE_0 :
+ {
+ __ospi_device_0_start__ = .;
+ KEEP(*(.ospi_device_0*))
+ KEEP(*(.code_in_ospi_device_0*))
+ __ospi_device_0_end__ = .;
+ } > OSPI_DEVICE_0
+ __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__;
+
+ /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */
+ __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive));
+ .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__)
+ {
+ __ospi_device_0_non_retentive_start__ = .;
+ KEEP(*(.ospi_device_0_non_retentive*))
+ __ospi_device_0_non_retentive_end__ = .;
+ } > OSPI_DEVICE_0
+ __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__;
+
+ __ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */
+ __ospi_device_0_region_start_address__ = __ospi_device_0_start__;
+ __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__;
+
+ /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */
+ __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__;
+
+ /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */
+ __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1);
+
+ /* OSPI_DEVICE_1 section to be downloaded via debugger */
+ .OSPI_DEVICE_1 :
+ {
+ __ospi_device_1_start__ = .;
+ KEEP(*(.ospi_device_1*))
+ KEEP(*(.code_in_ospi_device_1*))
+ __ospi_device_1_end__ = .;
+ } > OSPI_DEVICE_1
+ __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__;
+
+ /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */
+ __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive));
+ .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__)
+ {
+ __ospi_device_1_non_retentive_start__ = .;
+ KEEP(*(.ospi_device_1_non_retentive*))
+ __ospi_device_1_non_retentive_end__ = .;
+ } > OSPI_DEVICE_1
+ __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__;
+
+ __ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */
+ __ospi_device_1_region_start_address__ = __ospi_device_1_start__;
+ __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__;
+
+ /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */
+ __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__;
+
+ .noinit (NOLOAD):
+ {
+ . = ALIGN(4);
+ __noinit_start = .;
+ KEEP(*(.noinit*))
+ . = ALIGN(8);
+ /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */
+ KEEP(*(.heap.*))
+ __noinit_end = .;
+ } > RAM
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } > RAM
+
+ .heap (NOLOAD):
+ {
+ . = ALIGN(8);
+ __HeapBase = .;
+ /* Place the STD heap here. */
+ KEEP(*(.heap))
+ __HeapLimit = .;
+ } > RAM
+
+ /* Stacks are stored in this section. */
+ .stack_dummy (NOLOAD):
+ {
+ . = ALIGN(8);
+ __StackLimit = .;
+ /* Main stack */
+ KEEP(*(.stack))
+ __StackTop = .;
+ /* Thread stacks */
+ KEEP(*(.stack*))
+ __StackTopAll = .;
+ } > RAM
+
+ PROVIDE(__stack = __StackTopAll);
+
+ /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used
+ at run time for things such as ThreadX memory pool allocations. */
+ __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4);
+
+ /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects.
+ * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary.
+ * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */
+ __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024);
+
+ /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects.
+ * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not
+ * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary.
+ * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */
+ __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192);
+
+ /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects.
+ * The EDMAC is a non-secure bus master and can only access non-secure RAM. */
+ .ns_buffer (NOLOAD):
+ {
+ /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */
+ . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .;
+
+ KEEP(*(.ns_buffer*))
+ } > RAM
+
+ /* Data flash. */
+ .data_flash :
+ {
+ . = ORIGIN(DATA_FLASH);
+ __tz_DATA_FLASH_S = .;
+ __Data_Flash_Start = .;
+ KEEP(*(.data_flash*))
+ __Data_Flash_End = .;
+
+ __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024);
+ } > DATA_FLASH
+
+ /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */
+ __tz_SDRAM_S = ORIGIN(SDRAM);
+
+ /* SDRAM */
+ .sdram (NOLOAD):
+ {
+ __SDRAM_Start = .;
+ KEEP(*(.sdram*))
+ KEEP(*(.frame*))
+ __SDRAM_End = .;
+ } > SDRAM
+
+ /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */
+ __tz_SDRAM_N = __SDRAM_End;
+
+ /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */
+ __tz_ID_CODE_S = ORIGIN(ID_CODE);
+
+ /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool.
+ * Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE
+ * memory region between TrustZone projects. */
+ __tz_ID_CODE_N = __tz_ID_CODE_S;
+
+ .id_code :
+ {
+ __ID_Code_Start = .;
+ KEEP(*(.id_code*))
+ __ID_Code_End = .;
+ } > ID_CODE
+
+ /* Symbol required for RA Configuration tool. */
+ __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS);
+
+ .option_setting_ofs :
+ {
+ __OPTION_SETTING_OFS_Start = .;
+ KEEP(*(.option_setting_ofs0))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start;
+ KEEP(*(.option_setting_ofs2))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start;
+ KEEP(*(.option_setting_dualsel))
+ __OPTION_SETTING_OFS_End = .;
+ } > OPTION_SETTING_OFS = 0xFF
+
+ .option_setting_sas :
+ {
+ __OPTION_SETTING_SAS_Start = .;
+ KEEP(*(.option_setting_sas))
+ __OPTION_SETTING_SAS_End = .;
+ } > OPTION_SETTING_SAS = 0xFF
+
+ /* Symbol required for RA Configuration tool. */
+ __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS);
+
+ .option_setting_ns :
+ {
+ __OPTION_SETTING_NS_Start = .;
+ KEEP(*(.option_setting_ofs1))
+ . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start;
+ KEEP(*(.option_setting_ofs3))
+ . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start;
+ KEEP(*(.option_setting_banksel))
+ . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start;
+ KEEP(*(.option_setting_bps0))
+ . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start;
+ KEEP(*(.option_setting_bps1))
+ . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start;
+ KEEP(*(.option_setting_bps2))
+ . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start;
+ KEEP(*(.option_setting_bps3))
+ . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start;
+ KEEP(*(.option_setting_pbps0))
+ . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start;
+ KEEP(*(.option_setting_pbps1))
+ . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start;
+ KEEP(*(.option_setting_pbps2))
+ . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start;
+ KEEP(*(.option_setting_pbps3))
+ __OPTION_SETTING_NS_End = .;
+ } > OPTION_SETTING = 0xFF
+
+ /* Symbol required for RA Configuration tool. */
+ __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S);
+
+ .option_setting_s :
+ {
+ __OPTION_SETTING_S_Start = .;
+ KEEP(*(.option_setting_ofs1_sec))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_ofs3_sec))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_banksel_sec))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_bps_sec0))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_bps_sec1))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_bps_sec2))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_bps_sec3))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_pbps_sec0))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_pbps_sec1))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_pbps_sec2))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_pbps_sec3))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_ofs1_sel))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_ofs3_sel))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_banksel_sel))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_bps_sel0))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_bps_sel1))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_bps_sel2))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_bps_sel3))
+ __OPTION_SETTING_S_End = .;
+ } > OPTION_SETTING_S = 0xFF
+
+ /* Symbol required for RA Configuration tool. */
+ __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End;
+}
diff --git a/hw/bsp/ra/boards/ra2a1_ek/script/memory_regions.ld b/hw/bsp/ra/boards/ra2a1_ek/script/memory_regions.ld
new file mode 100644
index 0000000000..2d6992fedb
--- /dev/null
+++ b/hw/bsp/ra/boards/ra2a1_ek/script/memory_regions.ld
@@ -0,0 +1,22 @@
+
+ /* generated memory regions file - do not edit */
+ RAM_START = 0x20000000;
+ RAM_LENGTH = 0x8000;
+ FLASH_START = 0x00000000;
+ FLASH_LENGTH = 0x40000;
+ DATA_FLASH_START = 0x40100000;
+ DATA_FLASH_LENGTH = 0x2000;
+ OPTION_SETTING_START = 0x00000000;
+ OPTION_SETTING_LENGTH = 0x0;
+ OPTION_SETTING_S_START = 0x80000000;
+ OPTION_SETTING_S_LENGTH = 0x0;
+ ID_CODE_START = 0x01010018;
+ ID_CODE_LENGTH = 0x20;
+ SDRAM_START = 0x80010000;
+ SDRAM_LENGTH = 0x0;
+ QSPI_FLASH_START = 0x60000000;
+ QSPI_FLASH_LENGTH = 0x0;
+ OSPI_DEVICE_0_START = 0x80020000;
+ OSPI_DEVICE_0_LENGTH = 0x0;
+ OSPI_DEVICE_1_START = 0x80030000;
+ OSPI_DEVICE_1_LENGTH = 0x0;
diff --git a/hw/bsp/ra/boards/ra2a1_ek/smart_configurator/configuration.xml b/hw/bsp/ra/boards/ra2a1_ek/smart_configurator/configuration.xml
new file mode 100644
index 0000000000..beeeb67f24
--- /dev/null
+++ b/hw/bsp/ra/boards/ra2a1_ek/smart_configurator/configuration.xml
@@ -0,0 +1,258 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Simple application that blinks an LED. No RTOS included.
+ Renesas.RA_baremetal_blinky.5.6.0.pack
+
+
+ Board Support Package Common Files
+ Renesas.RA.5.6.0.pack
+
+
+ I/O Port
+ Renesas.RA.5.6.0.pack
+
+
+ Arm CMSIS Version 6 - Core (M)
+ Arm.CMSIS6.6.1.0+fsp.5.6.0.pack
+
+
+ RA2A1-EK Board Support Files
+ Renesas.RA_board_ra2a1_ek.5.6.0.pack
+
+
+ Board support package for R7FA2A1AB3CFM
+ Renesas.RA_mcu_ra2a1.5.6.0.pack
+
+
+ Board support package for RA2A1
+ Renesas.RA_mcu_ra2a1.5.6.0.pack
+
+
+ Board support package for RA2A1 - FSP Data
+ Renesas.RA_mcu_ra2a1.5.6.0.pack
+
+
+ Board support package for RA2A1 - Events
+ Renesas.RA_mcu_ra2a1.5.6.0.pack
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/hw/bsp/ra/boards/ra4m1_ek/board.h b/hw/bsp/ra/boards/ra4m1_ek/board.h
index c132387bc3..ba663d040e 100644
--- a/hw/bsp/ra/boards/ra4m1_ek/board.h
+++ b/hw/bsp/ra/boards/ra4m1_ek/board.h
@@ -31,21 +31,9 @@
extern "C" {
#endif
-#define LED1 BSP_IO_PORT_01_PIN_06
-#define LED_STATE_ON 1
-
-#define SW1 BSP_IO_PORT_01_PIN_05
+#define LED_STATE_ON 1
#define BUTTON_STATE_ACTIVE 0
-static const ioport_pin_cfg_t board_pin_cfg[] = {
- {.pin = LED1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_OUTPUT},
- {.pin = SW1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_INPUT},
- // USB FS D+, D-, VBus
- {.pin = BSP_IO_PORT_04_PIN_07, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS},
- {.pin = BSP_IO_PORT_09_PIN_14, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS},
- {.pin = BSP_IO_PORT_09_PIN_15, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS},
-};
-
#ifdef __cplusplus
}
#endif
diff --git a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_cfg.h
deleted file mode 100644
index 11d5795dfe..0000000000
--- a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_cfg.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/* generated configuration header file - do not edit */
-#ifndef BSP_CFG_H_
-#define BSP_CFG_H_
-
-#include "bsp_clock_cfg.h"
-#include "bsp_mcu_family_cfg.h"
-#include "board_cfg.h"
-
-#undef RA_NOT_DEFINED
-#define BSP_CFG_RTOS (0)
-#if defined(_RA_BOOT_IMAGE)
-#define BSP_CFG_BOOT_IMAGE (1)
-#endif
-#define BSP_CFG_MCU_VCC_MV (3300)
-#define BSP_CFG_STACK_MAIN_BYTES (0x800)
-#define BSP_CFG_HEAP_BYTES (0x1000)
-#define BSP_CFG_PARAM_CHECKING_ENABLE (1)
-#define BSP_CFG_ASSERT (0)
-#define BSP_CFG_ERROR_LOG (0)
-
-#define BSP_CFG_PFS_PROTECT ((1))
-
-#define BSP_CFG_C_RUNTIME_INIT ((1))
-#define BSP_CFG_EARLY_INIT ((0))
-
-#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0))
-
-#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1)
-
-#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0)
-#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0)
-#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1)
-#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
-
-#endif /* BSP_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
deleted file mode 100644
index d810dabb2f..0000000000
--- a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/* generated configuration header file - do not edit */
-#ifndef BSP_MCU_DEVICE_PN_CFG_H_
-#define BSP_MCU_DEVICE_PN_CFG_H_
-#define BSP_MCU_R7FA4M1AB3CFP
-#define BSP_MCU_FEATURE_SET ('A')
-#define BSP_ROM_SIZE_BYTES (262144)
-#define BSP_RAM_SIZE_BYTES (32768)
-#define BSP_DATA_FLASH_SIZE_BYTES (8192)
-#define BSP_PACKAGE_LQFP
-#define BSP_PACKAGE_PINS (100)
-#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h
deleted file mode 100644
index 72cdb89e67..0000000000
--- a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/* generated configuration header file through renesas e2 studio */
-#ifndef BSP_MCU_FAMILY_CFG_H_
-#define BSP_MCU_FAMILY_CFG_H_
-
-#include "bsp_mcu_device_pn_cfg.h"
-#include "bsp_mcu_device_cfg.h"
-#include "bsp_mcu_info.h"
-#include "bsp_clock_cfg.h"
-
-#define BSP_MCU_GROUP_RA4M1 (1)
-#define BSP_LOCO_HZ (32768)
-#define BSP_MOCO_HZ (8000000)
-#define BSP_SUB_CLOCK_HZ (32768)
-#if BSP_CFG_HOCO_FREQUENCY == 0
- #define BSP_HOCO_HZ (24000000)
-#elif BSP_CFG_HOCO_FREQUENCY == 2
- #define BSP_HOCO_HZ (32000000)
-#elif BSP_CFG_HOCO_FREQUENCY == 4
- #define BSP_HOCO_HZ (48000000)
-#elif BSP_CFG_HOCO_FREQUENCY == 5
- #define BSP_HOCO_HZ (64000000)
-#else
- #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h"
-#endif
-#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U)
-#define BSP_VECTOR_TABLE_MAX_ENTRIES (48U)
-
-#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2)
-#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10)
-#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17)
-#define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26)
-#define OFS_SEQ5 (1 << 28) | (1 << 30)
-#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
-#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEC3 | (1 << 2) | (3 << 3) | (0 << 8))
-#define BSP_CFG_USE_LOW_VOLTAGE_MODE ((0))
-#define BSP_CFG_ROM_REG_MPU_PC0_ENABLE (1)
-#define BSP_CFG_ROM_REG_MPU_PC0_START (0x00FFFFFC)
-#define BSP_CFG_ROM_REG_MPU_PC0_END (0x00FFFFFF)
-#define BSP_CFG_ROM_REG_MPU_PC1_ENABLE (1)
-#define BSP_CFG_ROM_REG_MPU_PC1_START (0x00FFFFFC)
-#define BSP_CFG_ROM_REG_MPU_PC1_END (0x00FFFFFF)
-#define BSP_CFG_ROM_REG_MPU_REGION0_ENABLE (1)
-#define BSP_CFG_ROM_REG_MPU_REGION0_START (0x00FFFFFC)
-#define BSP_CFG_ROM_REG_MPU_REGION0_END (0x00FFFFFF)
-#define BSP_CFG_ROM_REG_MPU_REGION1_ENABLE (1)
-#define BSP_CFG_ROM_REG_MPU_REGION1_START (0x200FFFFC)
-#define BSP_CFG_ROM_REG_MPU_REGION1_END (0x200FFFFF)
-#define BSP_CFG_ROM_REG_MPU_REGION2_ENABLE (1)
-#define BSP_CFG_ROM_REG_MPU_REGION2_START (0x407FFFFC)
-#define BSP_CFG_ROM_REG_MPU_REGION2_END (0x407FFFFF)
-#define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1)
-#define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC)
-#define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF)
-#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT
-#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9)
-#endif
-/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */
-#define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector)
-
-/*
- ID Code
- Note: To permanently lock and disable the debug interface define the BSP_ID_CODE_PERMANENTLY_LOCKED in the compiler settings.
- WARNING: This will disable debug access to the part and cannot be reversed by a debug probe.
- */
-#if defined(BSP_ID_CODE_PERMANENTLY_LOCKED)
- #define BSP_CFG_ID_CODE_LONG_1 (0x00000000)
- #define BSP_CFG_ID_CODE_LONG_2 (0x00000000)
- #define BSP_CFG_ID_CODE_LONG_3 (0x00000000)
- #define BSP_CFG_ID_CODE_LONG_4 (0x00000000)
- #else
-/* ID CODE: FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF */
-#define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF)
-#define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF)
-#define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF)
-#define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF)
-#endif
-
-#endif /* BSP_MCU_FAMILY_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h
new file mode 100644
index 0000000000..43b0f5b651
--- /dev/null
+++ b/hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h
@@ -0,0 +1,62 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_CFG_H_
+#define BSP_CFG_H_
+#ifdef __cplusplus
+ extern "C" {
+ #endif
+
+ #include "bsp_clock_cfg.h"
+ #include "bsp_mcu_family_cfg.h"
+ #include "board_cfg.h"
+ #define RA_NOT_DEFINED 0
+ #ifndef BSP_CFG_RTOS
+ #if (RA_NOT_DEFINED) != (RA_NOT_DEFINED)
+ #define BSP_CFG_RTOS (2)
+ #elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED)
+ #define BSP_CFG_RTOS (1)
+ #else
+ #define BSP_CFG_RTOS (0)
+ #endif
+ #endif
+ #ifndef BSP_CFG_RTC_USED
+ #define BSP_CFG_RTC_USED (RA_NOT_DEFINED)
+ #endif
+ #undef RA_NOT_DEFINED
+ #if defined(_RA_BOOT_IMAGE)
+ #define BSP_CFG_BOOT_IMAGE (1)
+ #endif
+ #define BSP_CFG_MCU_VCC_MV (3300)
+ #define BSP_CFG_STACK_MAIN_BYTES (0x800)
+ #define BSP_CFG_HEAP_BYTES (0x1000)
+ #define BSP_CFG_PARAM_CHECKING_ENABLE (0)
+ #define BSP_CFG_ASSERT (0)
+ #define BSP_CFG_ERROR_LOG (0)
+
+ #define BSP_CFG_PFS_PROTECT ((1))
+
+ #define BSP_CFG_C_RUNTIME_INIT ((1))
+ #define BSP_CFG_EARLY_INIT ((0))
+
+ #define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0))
+
+ #ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED
+ #define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1)
+ #endif
+
+ #ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE
+ #define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0)
+ #endif
+ #ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE
+ #define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0)
+ #endif
+ #ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED
+ #define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1)
+ #endif
+ #ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS
+ #define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
+ #endif
+
+ #ifdef __cplusplus
+ }
+ #endif
+#endif /* BSP_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_mcu_device_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h
similarity index 100%
rename from hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_mcu_device_cfg.h
rename to hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h
diff --git a/hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
new file mode 100644
index 0000000000..243fad9b63
--- /dev/null
+++ b/hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
@@ -0,0 +1,11 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_MCU_DEVICE_PN_CFG_H_
+#define BSP_MCU_DEVICE_PN_CFG_H_
+#define BSP_MCU_R7FA4M1AB3CFP
+ #define BSP_MCU_FEATURE_SET ('A')
+ #define BSP_ROM_SIZE_BYTES (262144)
+ #define BSP_RAM_SIZE_BYTES (32768)
+ #define BSP_DATA_FLASH_SIZE_BYTES (8192)
+ #define BSP_PACKAGE_LQFP
+ #define BSP_PACKAGE_PINS (100)
+#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h
new file mode 100644
index 0000000000..3d482b2b6e
--- /dev/null
+++ b/hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h
@@ -0,0 +1,84 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_MCU_FAMILY_CFG_H_
+#define BSP_MCU_FAMILY_CFG_H_
+#ifdef __cplusplus
+ extern "C" {
+ #endif
+
+ #include "bsp_mcu_device_pn_cfg.h"
+ #include "bsp_mcu_device_cfg.h"
+ #include "../../../ra/fsp/src/bsp/mcu/ra4m1/bsp_mcu_info.h"
+ #include "bsp_clock_cfg.h"
+ #define BSP_MCU_GROUP_RA4M1 (1)
+ #define BSP_LOCO_HZ (32768)
+ #define BSP_MOCO_HZ (8000000)
+ #define BSP_SUB_CLOCK_HZ (32768)
+ #if BSP_CFG_HOCO_FREQUENCY == 0
+ #define BSP_HOCO_HZ (24000000)
+ #elif BSP_CFG_HOCO_FREQUENCY == 2
+ #define BSP_HOCO_HZ (32000000)
+ #elif BSP_CFG_HOCO_FREQUENCY == 4
+ #define BSP_HOCO_HZ (48000000)
+ #elif BSP_CFG_HOCO_FREQUENCY == 5
+ #define BSP_HOCO_HZ (64000000)
+ #else
+ #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h"
+ #endif
+ #define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U)
+ #define BSP_VECTOR_TABLE_MAX_ENTRIES (48U)
+ #define BSP_CFG_INLINE_IRQ_FUNCTIONS (1)
+
+ #define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2)
+ #define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10)
+ #define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17)
+ #define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26)
+ #define OFS_SEQ5 (1 << 28) | (1 << 30)
+ #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
+ #define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEC3 | (1 << 2) | (3 << 3) | (0 << 8))
+ #define BSP_CFG_USE_LOW_VOLTAGE_MODE ((0))
+ #define BSP_CFG_ROM_REG_MPU_PC0_ENABLE (1)
+ #define BSP_CFG_ROM_REG_MPU_PC0_START (0x00FFFFFC)
+ #define BSP_CFG_ROM_REG_MPU_PC0_END (0x00FFFFFF)
+ #define BSP_CFG_ROM_REG_MPU_PC1_ENABLE (1)
+ #define BSP_CFG_ROM_REG_MPU_PC1_START (0x00FFFFFC)
+ #define BSP_CFG_ROM_REG_MPU_PC1_END (0x00FFFFFF)
+ #define BSP_CFG_ROM_REG_MPU_REGION0_ENABLE (1)
+ #define BSP_CFG_ROM_REG_MPU_REGION0_START (0x00FFFFFC)
+ #define BSP_CFG_ROM_REG_MPU_REGION0_END (0x00FFFFFF)
+ #define BSP_CFG_ROM_REG_MPU_REGION1_ENABLE (1)
+ #define BSP_CFG_ROM_REG_MPU_REGION1_START (0x200FFFFC)
+ #define BSP_CFG_ROM_REG_MPU_REGION1_END (0x200FFFFF)
+ #define BSP_CFG_ROM_REG_MPU_REGION2_ENABLE (1)
+ #define BSP_CFG_ROM_REG_MPU_REGION2_START (0x407FFFFC)
+ #define BSP_CFG_ROM_REG_MPU_REGION2_END (0x407FFFFF)
+ #define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1)
+ #define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC)
+ #define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF)
+ #ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT
+ #define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9)
+ #endif
+ /* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */
+ #define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector)
+
+ /*
+ ID Code
+ Note: To permanently lock and disable the debug interface define the BSP_ID_CODE_PERMANENTLY_LOCKED in the compiler settings.
+ WARNING: This will disable debug access to the part and cannot be reversed by a debug probe.
+ */
+ #if defined(BSP_ID_CODE_PERMANENTLY_LOCKED)
+ #define BSP_CFG_ID_CODE_LONG_1 (0x00000000)
+ #define BSP_CFG_ID_CODE_LONG_2 (0x00000000)
+ #define BSP_CFG_ID_CODE_LONG_3 (0x00000000)
+ #define BSP_CFG_ID_CODE_LONG_4 (0x00000000)
+ #else
+ /* ID CODE: FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF */
+ #define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF)
+ #define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF)
+ #define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF)
+ #define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF)
+ #endif
+
+ #ifdef __cplusplus
+ }
+ #endif
+#endif /* BSP_MCU_FAMILY_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h
new file mode 100644
index 0000000000..f77a5bcec4
--- /dev/null
+++ b/hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h
@@ -0,0 +1,17 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_PIN_CFG_H_
+#define BSP_PIN_CFG_H_
+#include "r_ioport.h"
+
+/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+#define SW1 (BSP_IO_PORT_01_PIN_05)
+#define LED1 (BSP_IO_PORT_01_PIN_06)
+extern const ioport_cfg_t g_bsp_pin_cfg; /* RA4M1-EK.pincfg */
+
+void BSP_PinConfigSecurityInit();
+
+/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+#endif /* BSP_PIN_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h
new file mode 100644
index 0000000000..d2688bf5ba
--- /dev/null
+++ b/hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h
@@ -0,0 +1,13 @@
+/* generated configuration header file - do not edit */
+#ifndef R_IOPORT_CFG_H_
+#define R_IOPORT_CFG_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* R_IOPORT_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_clock_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/ra_gen/bsp_clock_cfg.h
similarity index 94%
rename from hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_clock_cfg.h
rename to hw/bsp/ra/boards/ra4m1_ek/ra_gen/bsp_clock_cfg.h
index 554126523e..81ac5dc11e 100644
--- a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_clock_cfg.h
+++ b/hw/bsp/ra/boards/ra4m1_ek/ra_gen/bsp_clock_cfg.h
@@ -7,7 +7,7 @@
#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */
#define BSP_CFG_HOCO_FREQUENCY (0) /* HOCO 24MHz */
#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL Div /2 */
-#define BSP_CFG_PLL_MUL (BSP_CLOCKS_PLL_MUL(8u,0u)) /* PLL Mul x8 */
+#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(8U,0U) /* PLL Mul x8 */
#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */
#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* ICLK Div /1 */
#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKA Div /1 */
diff --git a/hw/bsp/ra/boards/ra4m1_ek/ra_gen/common_data.c b/hw/bsp/ra/boards/ra4m1_ek/ra_gen/common_data.c
new file mode 100644
index 0000000000..50036c0adc
--- /dev/null
+++ b/hw/bsp/ra/boards/ra4m1_ek/ra_gen/common_data.c
@@ -0,0 +1,11 @@
+/* generated common source file - do not edit */
+#include "common_data.h"
+ioport_instance_ctrl_t g_ioport_ctrl;
+const ioport_instance_t g_ioport =
+ {
+ .p_api = &g_ioport_on_ioport,
+ .p_ctrl = &g_ioport_ctrl,
+ .p_cfg = &g_bsp_pin_cfg,
+ };
+void g_common_init(void) {
+}
diff --git a/hw/bsp/ra/boards/ra4m1_ek/ra_gen/common_data.h b/hw/bsp/ra/boards/ra4m1_ek/ra_gen/common_data.h
new file mode 100644
index 0000000000..6a08cbee09
--- /dev/null
+++ b/hw/bsp/ra/boards/ra4m1_ek/ra_gen/common_data.h
@@ -0,0 +1,20 @@
+/* generated common header file - do not edit */
+#ifndef COMMON_DATA_H_
+#define COMMON_DATA_H_
+#include
+#include "bsp_api.h"
+#include "r_ioport.h"
+#include "bsp_pin_cfg.h"
+FSP_HEADER
+#define IOPORT_CFG_NAME g_bsp_pin_cfg
+#define IOPORT_CFG_OPEN R_IOPORT_Open
+#define IOPORT_CFG_CTRL g_ioport_ctrl
+
+/* IOPORT Instance */
+extern const ioport_instance_t g_ioport;
+
+/* IOPORT control structure. */
+extern ioport_instance_ctrl_t g_ioport_ctrl;
+void g_common_init(void);
+FSP_FOOTER
+#endif /* COMMON_DATA_H_ */
diff --git a/hw/bsp/ra/boards/ra4m1_ek/ra_gen/pin_data.c b/hw/bsp/ra/boards/ra4m1_ek/ra_gen/pin_data.c
new file mode 100644
index 0000000000..baa7134434
--- /dev/null
+++ b/hw/bsp/ra/boards/ra4m1_ek/ra_gen/pin_data.c
@@ -0,0 +1,119 @@
+/* generated pin source file - do not edit */
+#include "bsp_api.h"
+#include "r_ioport.h"
+
+
+const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = {
+ {
+ .pin = BSP_IO_PORT_00_PIN_04,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE)
+ },
+ {
+ .pin = BSP_IO_PORT_01_PIN_00,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
+ },
+ {
+ .pin = BSP_IO_PORT_01_PIN_01,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
+ },
+ {
+ .pin = BSP_IO_PORT_01_PIN_02,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
+ },
+ {
+ .pin = BSP_IO_PORT_01_PIN_03,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
+ },
+ {
+ .pin = BSP_IO_PORT_01_PIN_05,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT | (uint32_t) IOPORT_CFG_PULLUP_ENABLE)
+ },
+ {
+ .pin = BSP_IO_PORT_01_PIN_06,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+ },
+ {
+ .pin = BSP_IO_PORT_01_PIN_08,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG)
+ },
+ {
+ .pin = BSP_IO_PORT_01_PIN_15,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_CTSU)
+ },
+ {
+ .pin = BSP_IO_PORT_02_PIN_05,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_CTSU)
+ },
+ {
+ .pin = BSP_IO_PORT_03_PIN_00,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG)
+ },
+ {
+ .pin = BSP_IO_PORT_04_PIN_00,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+ },
+ {
+ .pin = BSP_IO_PORT_04_PIN_01,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI1_3_5_7_9)
+ },
+ {
+ .pin = BSP_IO_PORT_04_PIN_02,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI1_3_5_7_9)
+ },
+ {
+ .pin = BSP_IO_PORT_04_PIN_03,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+ },
+ {
+ .pin = BSP_IO_PORT_04_PIN_07,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)
+ },
+ {
+ .pin = BSP_IO_PORT_09_PIN_14,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)
+ },
+ {
+ .pin = BSP_IO_PORT_09_PIN_15,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)
+ },
+};
+
+const ioport_cfg_t g_bsp_pin_cfg = {
+ .number_of_pins = sizeof(g_bsp_pin_cfg_data)/sizeof(ioport_pin_cfg_t),
+ .p_pin_cfg_data = &g_bsp_pin_cfg_data[0],
+};
+
+#if BSP_TZ_SECURE_BUILD
+
+void R_BSP_PinCfgSecurityInit(void);
+
+/* Initialize SAR registers for secure pins. */
+void R_BSP_PinCfgSecurityInit(void)
+{
+ #if (2U == BSP_FEATURE_IOPORT_VERSION)
+ uint32_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR];
+ #else
+ uint16_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR];
+ #endif
+ memset(pmsar, 0xFF, BSP_FEATURE_BSP_NUM_PMSAR * sizeof(R_PMISC->PMSAR[0]));
+
+
+ for(uint32_t i = 0; i < g_bsp_pin_cfg.number_of_pins; i++)
+ {
+ uint32_t port_pin = g_bsp_pin_cfg.p_pin_cfg_data[i].pin;
+ uint32_t port = port_pin >> 8U;
+ uint32_t pin = port_pin & 0xFFU;
+ pmsar[port] &= (uint16_t) ~(1U << pin);
+ }
+
+ for(uint32_t i = 0; i < BSP_FEATURE_BSP_NUM_PMSAR; i++)
+ {
+ #if (2U == BSP_FEATURE_IOPORT_VERSION)
+ R_PMISC->PMSAR[i].PMSAR = (uint16_t) pmsar[i];
+ #else
+ R_PMISC->PMSAR[i].PMSAR = pmsar[i];
+ #endif
+ }
+
+}
+#endif
diff --git a/hw/bsp/ra/boards/ra4m1_ek/script/fsp.ld b/hw/bsp/ra/boards/ra4m1_ek/script/fsp.ld
new file mode 100644
index 0000000000..605eef7d2c
--- /dev/null
+++ b/hw/bsp/ra/boards/ra4m1_ek/script/fsp.ld
@@ -0,0 +1,769 @@
+/*
+ Linker File for Renesas FSP
+*/
+
+INCLUDE memory_regions.ld
+
+/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/
+/*
+ XIP_SECONDARY_SLOT_IMAGE = 1;
+*/
+
+QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH);
+OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH);
+OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH);
+
+/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */
+__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0);
+
+ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0;
+ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0;
+DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0;
+DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0;
+RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0;
+RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0;
+RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH;
+RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH;
+
+OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80;
+
+/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings.
+ * Bootloader images do not configure option settings because they are owned by the bootloader.
+ * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */
+__bl_FSP_BOOTABLE_IMAGE = 1;
+__bln_FSP_BOOTABLE_IMAGE = 1;
+PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE);
+USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE);
+
+__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+ FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH :
+ (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH :
+ FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH;
+__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+ FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH;
+__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH;
+__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+ FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH;
+__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH;
+__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+ FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
+ __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH;
+__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+ FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
+ __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH;
+__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+ FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH :
+ RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH;
+__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+ FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH :
+ __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH;
+__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+ FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
+ __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2;
+__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START);
+__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+ FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
+ FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2;
+
+XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0;
+FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START :
+ XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START :
+ FLASH_IMAGE_START;
+LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH :
+ DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH :
+ FLASH_LENGTH;
+OPTION_SETTING_SAS_SIZE = 0x34;
+OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 :
+ OPTION_SETTING_LENGTH == 0 ? 0 :
+ OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE;
+
+/* Define memory regions. */
+MEMORY
+{
+ ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH
+ DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH
+ FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH
+ RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH
+ DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH
+ QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH
+ OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH
+ OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH
+ OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH
+ OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH
+ SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH
+ OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH
+ OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18
+ OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH
+ OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH
+ ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH
+}
+
+/* Library configurations */
+GROUP(libgcc.a libc.a libm.a)
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be DEFINED in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __copy_table_start__
+ * __copy_table_end__
+ * __zero_table_start__
+ * __zero_table_end__
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ * __Vectors_End
+ * __Vectors_Size
+ * __qspi_flash_start__
+ * __qspi_flash_end__
+ * __qspi_flash_code_size__
+ * __qspi_region_max_size__
+ * __qspi_region_start_address__
+ * __qspi_region_end_address__
+ * __ospi_device_0_start__
+ * __ospi_device_0_end__
+ * __ospi_device_0_code_size__
+ * __ospi_device_0_region_max_size__
+ * __ospi_device_0_region_start_address__
+ * __ospi_device_0_region_end_address__
+ * __ospi_device_1_start__
+ * __ospi_device_1_end__
+ * __ospi_device_1_code_size__
+ * __ospi_device_1_region_max_size__
+ * __ospi_device_1_region_start_address__
+ * __ospi_device_1_region_end_address__
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ __tz_FLASH_S = ABSOLUTE(FLASH_START);
+ __ROM_Start = .;
+
+ /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much
+ * space because ROM registers are at address 0x400 and there is very little space
+ * in between. */
+ KEEP(*(.fixed_vectors*))
+ KEEP(*(.application_vectors*))
+ __Vectors_End = .;
+
+ /* Some devices have a gap of code flash between the vector table and ROM Registers.
+ * The flash gap section allows applications to place code and data in this section. */
+ *(.flash_gap*)
+
+ /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */
+ . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400;
+ KEEP(*(.rom_registers*))
+
+ /* Reserving 0x100 bytes of space for ROM registers. */
+ . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x500;
+
+ /* Allocate flash write-boundary-aligned
+ * space for sce9 wrapped public keys for mcuboot if the module is used.
+ */
+ KEEP(*(.mcuboot_sce9_key*))
+
+ *(.text*)
+
+ KEEP(*(.version))
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+ __usb_dev_descriptor_start_fs = .;
+ KEEP(*(.usb_device_desc_fs*))
+ __usb_cfg_descriptor_start_fs = .;
+ KEEP(*(.usb_config_desc_fs*))
+ __usb_interface_descriptor_start_fs = .;
+ KEEP(*(.usb_interface_desc_fs*))
+ __usb_descriptor_end_fs = .;
+ __usb_dev_descriptor_start_hs = .;
+ KEEP(*(.usb_device_desc_hs*))
+ __usb_cfg_descriptor_start_hs = .;
+ KEEP(*(.usb_config_desc_hs*))
+ __usb_interface_descriptor_start_hs = .;
+ KEEP(*(.usb_interface_desc_hs*))
+ __usb_descriptor_end_hs = .;
+
+ KEEP(*(.eh_frame*))
+
+ __ROM_End = .;
+ } > FLASH = 0xFF
+
+ __Vectors_Size = __Vectors_End - __Vectors;
+
+ . = .;
+ __itcm_data_pre_location = .;
+
+ /* Initialized ITCM data. */
+ /* Aligned to FCACHE2 for RA8. */
+ .itcm_data : ALIGN(16)
+ {
+ /* Start of ITCM Secure Trustzone region. */
+ __tz_ITCM_S = ABSOLUTE(ITCM_START);
+
+ /* All ITCM data start */
+ __itcm_data_start = .;
+
+ KEEP(*(.itcm_data*))
+
+ /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */
+ . = ALIGN(8);
+
+ /* All ITCM data end */
+ __itcm_data_end = .;
+
+ /*
+ * Start of the ITCM Non-Secure Trustzone region.
+ * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects.
+ */
+ __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192);
+ } > ITCM AT > FLASH = 0x00
+
+ /* Addresses exported for ITCM initialization. */
+ __itcm_data_init_start = LOADADDR(.itcm_data);
+ __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data);
+
+ ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.")
+ ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.")
+ ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.")
+ ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.")
+
+ /* Restore location counter. */
+ /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */
+ /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */
+ . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location;
+
+ __exidx_start = .;
+ /DISCARD/ :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ }
+ __exidx_end = .;
+
+ /* To copy multiple ROM to RAM sections,
+ * uncomment .copy.table section and,
+ * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+ /*
+ .copy.table :
+ {
+ . = ALIGN(4);
+ __copy_table_start__ = .;
+ LONG (__etext)
+ LONG (__data_start__)
+ LONG (__data_end__ - __data_start__)
+ LONG (__etext2)
+ LONG (__data2_start__)
+ LONG (__data2_end__ - __data2_start__)
+ __copy_table_end__ = .;
+ } > FLASH
+ */
+
+ /* To clear multiple BSS sections,
+ * uncomment .zero.table section and,
+ * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+ /*
+ .zero.table :
+ {
+ . = ALIGN(4);
+ __zero_table_start__ = .;
+ LONG (__bss_start__)
+ LONG (__bss_end__ - __bss_start__)
+ LONG (__bss2_start__)
+ LONG (__bss2_end__ - __bss2_start__)
+ __zero_table_end__ = .;
+ } > FLASH
+ */
+
+ __etext = .;
+
+ __tz_RAM_S = ORIGIN(RAM);
+
+ /* If DTC is used, put the DTC vector table at the start of SRAM.
+ This avoids memory holes due to 1K alignment required by it. */
+ .fsp_dtc_vector_table (NOLOAD) :
+ {
+ . = ORIGIN(RAM);
+ *(.fsp_dtc_vector_table)
+ } > RAM
+
+ /* Initialized data section. */
+ .data :
+ {
+ __data_start__ = .;
+ . = ALIGN(4);
+
+ __Code_In_RAM_Start = .;
+
+ KEEP(*(.code_in_ram*))
+ __Code_In_RAM_End = .;
+
+ *(vtable)
+ /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */
+ *(.data.*)
+ *(.data)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+
+ . = ALIGN(4);
+
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM AT > FLASH
+
+ . = .;
+ __dtcm_data_pre_location = LOADADDR(.data) + SIZEOF(.data);
+
+ /* Initialized DTCM data. */
+ /* Aligned to FCACHE2 for RA8. */
+ .dtcm_data : ALIGN(16)
+ {
+ /* Start of DTCM Secure Trustzone region. */
+ __tz_DTCM_S = ABSOLUTE(DTCM_START);
+
+ /* Initialized DTCM data start */
+ __dtcm_data_start = .;
+
+ KEEP(*(.dtcm_data*))
+
+ /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */
+ . = ALIGN(8);
+
+ /* Initialized DTCM data end */
+ __dtcm_data_end = .;
+ } > DTCM AT > FLASH = 0x00
+
+ . = __dtcm_data_end;
+ /* Uninitialized DTCM data. */
+ /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */
+ .dtcm_bss ALIGN(8) (NOLOAD) :
+ {
+ /* Uninitialized DTCM data start */
+ __dtcm_bss_start = .;
+
+ KEEP(*(.dtcm_bss*))
+
+ /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */
+ . = ALIGN(8);
+
+ /* Uninitialized DTCM data end */
+ __dtcm_bss_end = .;
+
+ /*
+ * Start of the DTCM Non-Secure Trustzone region.
+ * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects.
+ */
+ __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192);
+ } > DTCM
+
+ /* Addresses exported for DTCM initialization. */
+ __dtcm_data_init_start = LOADADDR(.dtcm_data);
+ __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data);
+
+ ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.")
+ ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.")
+ ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).")
+ ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.")
+ ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.")
+ ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.")
+ ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.")
+ ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.")
+
+ /* Restore location counter. */
+ /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */
+ /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */
+ . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location;
+
+ /* TrustZone Secure Gateway Stubs Section */
+
+ /* Store location counter for SPI non-retentive sections. */
+ sgstubs_pre_location = .;
+
+ /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */
+ SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024);
+ .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024)
+ {
+ __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024);
+ _start_sg = .;
+ *(.gnu.sgstubs*)
+ . = ALIGN(32);
+ _end_sg = .;
+ } > FLASH
+
+ __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768);
+ FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N;
+
+ /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */
+ __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH);
+
+ /* QSPI_FLASH section to be downloaded via debugger */
+ .qspi_flash :
+ {
+ __qspi_flash_start__ = .;
+ KEEP(*(.qspi_flash*))
+ KEEP(*(.code_in_qspi*))
+ __qspi_flash_end__ = .;
+ } > QSPI_FLASH
+ __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__;
+
+ /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */
+ __qspi_flash_code_addr__ = sgstubs_pre_location;
+ .qspi_non_retentive : AT(__qspi_flash_code_addr__)
+ {
+ __qspi_non_retentive_start__ = .;
+ KEEP(*(.qspi_non_retentive*))
+ __qspi_non_retentive_end__ = .;
+ } > QSPI_FLASH
+ __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__;
+
+ __qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */
+ __qspi_region_start_address__ = __qspi_flash_start__;
+ __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__;
+
+ /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */
+ __tz_QSPI_FLASH_N = __qspi_non_retentive_end__;
+
+ /* Support for OctaRAM */
+ .OSPI_DEVICE_0_NO_LOAD (NOLOAD):
+ {
+ . = ALIGN(4);
+ __ospi_device_0_start__ = .;
+ *(.ospi_device_0_no_load*)
+ . = ALIGN(4);
+ __ospi_device_0_end__ = .;
+ } > OSPI_DEVICE_0_RAM
+
+ .OSPI_DEVICE_1_NO_LOAD (NOLOAD):
+ {
+ . = ALIGN(4);
+ __ospi_device_1_start__ = .;
+ *(.ospi_device_1_no_load*)
+ . = ALIGN(4);
+ __ospi_device_1_end__ = .;
+ } > OSPI_DEVICE_1_RAM
+
+ /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */
+ __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0);
+
+ /* OSPI_DEVICE_0 section to be downloaded via debugger */
+ .OSPI_DEVICE_0 :
+ {
+ __ospi_device_0_start__ = .;
+ KEEP(*(.ospi_device_0*))
+ KEEP(*(.code_in_ospi_device_0*))
+ __ospi_device_0_end__ = .;
+ } > OSPI_DEVICE_0
+ __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__;
+
+ /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */
+ __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive));
+ .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__)
+ {
+ __ospi_device_0_non_retentive_start__ = .;
+ KEEP(*(.ospi_device_0_non_retentive*))
+ __ospi_device_0_non_retentive_end__ = .;
+ } > OSPI_DEVICE_0
+ __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__;
+
+ __ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */
+ __ospi_device_0_region_start_address__ = __ospi_device_0_start__;
+ __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__;
+
+ /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */
+ __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__;
+
+ /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */
+ __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1);
+
+ /* OSPI_DEVICE_1 section to be downloaded via debugger */
+ .OSPI_DEVICE_1 :
+ {
+ __ospi_device_1_start__ = .;
+ KEEP(*(.ospi_device_1*))
+ KEEP(*(.code_in_ospi_device_1*))
+ __ospi_device_1_end__ = .;
+ } > OSPI_DEVICE_1
+ __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__;
+
+ /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */
+ __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive));
+ .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__)
+ {
+ __ospi_device_1_non_retentive_start__ = .;
+ KEEP(*(.ospi_device_1_non_retentive*))
+ __ospi_device_1_non_retentive_end__ = .;
+ } > OSPI_DEVICE_1
+ __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__;
+
+ __ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */
+ __ospi_device_1_region_start_address__ = __ospi_device_1_start__;
+ __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__;
+
+ /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */
+ __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__;
+
+ .noinit (NOLOAD):
+ {
+ . = ALIGN(4);
+ __noinit_start = .;
+ KEEP(*(.noinit*))
+ . = ALIGN(8);
+ /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */
+ KEEP(*(.heap.*))
+ __noinit_end = .;
+ } > RAM
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } > RAM
+
+ .heap (NOLOAD):
+ {
+ . = ALIGN(8);
+ __HeapBase = .;
+ /* Place the STD heap here. */
+ KEEP(*(.heap))
+ __HeapLimit = .;
+ } > RAM
+
+ /* Stacks are stored in this section. */
+ .stack_dummy (NOLOAD):
+ {
+ . = ALIGN(8);
+ __StackLimit = .;
+ /* Main stack */
+ KEEP(*(.stack))
+ __StackTop = .;
+ /* Thread stacks */
+ KEEP(*(.stack*))
+ __StackTopAll = .;
+ } > RAM
+
+ PROVIDE(__stack = __StackTopAll);
+
+ /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used
+ at run time for things such as ThreadX memory pool allocations. */
+ __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4);
+
+ /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects.
+ * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary.
+ * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */
+ __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024);
+
+ /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects.
+ * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not
+ * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary.
+ * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */
+ __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192);
+
+ /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects.
+ * The EDMAC is a non-secure bus master and can only access non-secure RAM. */
+ .ns_buffer (NOLOAD):
+ {
+ /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */
+ . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .;
+
+ KEEP(*(.ns_buffer*))
+ } > RAM
+
+ /* Data flash. */
+ .data_flash :
+ {
+ . = ORIGIN(DATA_FLASH);
+ __tz_DATA_FLASH_S = .;
+ __Data_Flash_Start = .;
+ KEEP(*(.data_flash*))
+ __Data_Flash_End = .;
+
+ __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024);
+ } > DATA_FLASH
+
+ /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */
+ __tz_SDRAM_S = ORIGIN(SDRAM);
+
+ /* SDRAM */
+ .sdram (NOLOAD):
+ {
+ __SDRAM_Start = .;
+ KEEP(*(.sdram*))
+ KEEP(*(.frame*))
+ __SDRAM_End = .;
+ } > SDRAM
+
+ /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */
+ __tz_SDRAM_N = __SDRAM_End;
+
+ /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */
+ __tz_ID_CODE_S = ORIGIN(ID_CODE);
+
+ /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool.
+ * Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE
+ * memory region between TrustZone projects. */
+ __tz_ID_CODE_N = __tz_ID_CODE_S;
+
+ .id_code :
+ {
+ __ID_Code_Start = .;
+ KEEP(*(.id_code*))
+ __ID_Code_End = .;
+ } > ID_CODE
+
+ /* Symbol required for RA Configuration tool. */
+ __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS);
+
+ .option_setting_ofs :
+ {
+ __OPTION_SETTING_OFS_Start = .;
+ KEEP(*(.option_setting_ofs0))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start;
+ KEEP(*(.option_setting_ofs2))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start;
+ KEEP(*(.option_setting_dualsel))
+ __OPTION_SETTING_OFS_End = .;
+ } > OPTION_SETTING_OFS = 0xFF
+
+ .option_setting_sas :
+ {
+ __OPTION_SETTING_SAS_Start = .;
+ KEEP(*(.option_setting_sas))
+ __OPTION_SETTING_SAS_End = .;
+ } > OPTION_SETTING_SAS = 0xFF
+
+ /* Symbol required for RA Configuration tool. */
+ __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS);
+
+ .option_setting_ns :
+ {
+ __OPTION_SETTING_NS_Start = .;
+ KEEP(*(.option_setting_ofs1))
+ . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start;
+ KEEP(*(.option_setting_ofs3))
+ . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start;
+ KEEP(*(.option_setting_banksel))
+ . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start;
+ KEEP(*(.option_setting_bps0))
+ . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start;
+ KEEP(*(.option_setting_bps1))
+ . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start;
+ KEEP(*(.option_setting_bps2))
+ . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start;
+ KEEP(*(.option_setting_bps3))
+ . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start;
+ KEEP(*(.option_setting_pbps0))
+ . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start;
+ KEEP(*(.option_setting_pbps1))
+ . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start;
+ KEEP(*(.option_setting_pbps2))
+ . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start;
+ KEEP(*(.option_setting_pbps3))
+ __OPTION_SETTING_NS_End = .;
+ } > OPTION_SETTING = 0xFF
+
+ /* Symbol required for RA Configuration tool. */
+ __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S);
+
+ .option_setting_s :
+ {
+ __OPTION_SETTING_S_Start = .;
+ KEEP(*(.option_setting_ofs1_sec))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_ofs3_sec))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_banksel_sec))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_bps_sec0))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_bps_sec1))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_bps_sec2))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_bps_sec3))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_pbps_sec0))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_pbps_sec1))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_pbps_sec2))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_pbps_sec3))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_ofs1_sel))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_ofs3_sel))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_banksel_sel))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_bps_sel0))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_bps_sel1))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_bps_sel2))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_bps_sel3))
+ __OPTION_SETTING_S_End = .;
+ } > OPTION_SETTING_S = 0xFF
+
+ /* Symbol required for RA Configuration tool. */
+ __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End;
+}
diff --git a/hw/bsp/ra/boards/ra4m1_ek/script/memory_regions.ld b/hw/bsp/ra/boards/ra4m1_ek/script/memory_regions.ld
new file mode 100644
index 0000000000..2d6992fedb
--- /dev/null
+++ b/hw/bsp/ra/boards/ra4m1_ek/script/memory_regions.ld
@@ -0,0 +1,22 @@
+
+ /* generated memory regions file - do not edit */
+ RAM_START = 0x20000000;
+ RAM_LENGTH = 0x8000;
+ FLASH_START = 0x00000000;
+ FLASH_LENGTH = 0x40000;
+ DATA_FLASH_START = 0x40100000;
+ DATA_FLASH_LENGTH = 0x2000;
+ OPTION_SETTING_START = 0x00000000;
+ OPTION_SETTING_LENGTH = 0x0;
+ OPTION_SETTING_S_START = 0x80000000;
+ OPTION_SETTING_S_LENGTH = 0x0;
+ ID_CODE_START = 0x01010018;
+ ID_CODE_LENGTH = 0x20;
+ SDRAM_START = 0x80010000;
+ SDRAM_LENGTH = 0x0;
+ QSPI_FLASH_START = 0x60000000;
+ QSPI_FLASH_LENGTH = 0x0;
+ OSPI_DEVICE_0_START = 0x80020000;
+ OSPI_DEVICE_0_LENGTH = 0x0;
+ OSPI_DEVICE_1_START = 0x80030000;
+ OSPI_DEVICE_1_LENGTH = 0x0;
diff --git a/hw/bsp/ra/boards/ra4m1_ek/smart_configurator/configuration.xml b/hw/bsp/ra/boards/ra4m1_ek/smart_configurator/configuration.xml
new file mode 100644
index 0000000000..2ca7fe5953
--- /dev/null
+++ b/hw/bsp/ra/boards/ra4m1_ek/smart_configurator/configuration.xml
@@ -0,0 +1,271 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Simple application that blinks an LED. No RTOS included.
+ Renesas.RA_baremetal_blinky.5.6.0.pack
+
+
+ Board Support Package Common Files
+ Renesas.RA.5.6.0.pack
+
+
+ I/O Port
+ Renesas.RA.5.6.0.pack
+
+
+ Arm CMSIS Version 6 - Core (M)
+ Arm.CMSIS6.6.1.0+fsp.5.6.0.pack
+
+
+ RA4M1-EK Board Support Files
+ Renesas.RA_board_ra4m1_ek.5.6.0.pack
+
+
+ Board support package for R7FA4M1AB3CFP
+ Renesas.RA_mcu_ra4m1.5.6.0.pack
+
+
+ Board support package for RA4M1
+ Renesas.RA_mcu_ra4m1.5.6.0.pack
+
+
+ Board support package for RA4M1 - FSP Data
+ Renesas.RA_mcu_ra4m1.5.6.0.pack
+
+
+ Board support package for RA4M1 - Events
+ Renesas.RA_mcu_ra4m1.5.6.0.pack
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_cfg.h
deleted file mode 100644
index 862ec25b7c..0000000000
--- a/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_cfg.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/* generated configuration header file - do not edit */
-#ifndef BSP_CFG_H_
-#define BSP_CFG_H_
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "bsp_clock_cfg.h"
-#include "bsp_mcu_family_cfg.h"
-#include "board_cfg.h"
-
-#define RA_NOT_DEFINED 0
-#ifndef BSP_CFG_RTOS
-#if (RA_NOT_DEFINED) != (RA_NOT_DEFINED)
-#define BSP_CFG_RTOS (2)
-#elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED)
-#define BSP_CFG_RTOS (1)
-#else
-#define BSP_CFG_RTOS (0)
-#endif
-#endif
-#ifndef BSP_CFG_RTC_USED
-#define BSP_CFG_RTC_USED (RA_NOT_DEFINED)
-#endif
-#undef RA_NOT_DEFINED
-#if defined(_RA_BOOT_IMAGE)
-#define BSP_CFG_BOOT_IMAGE (1)
-#endif
-#define BSP_CFG_MCU_VCC_MV (3300)
-#define BSP_CFG_STACK_MAIN_BYTES (0x800)
-#define BSP_CFG_HEAP_BYTES (0x800)
-#define BSP_CFG_PARAM_CHECKING_ENABLE (1)
-#define BSP_CFG_ASSERT (0)
-#define BSP_CFG_ERROR_LOG (0)
-
-#define BSP_CFG_PFS_PROTECT ((1))
-
-#define BSP_CFG_C_RUNTIME_INIT ((1))
-#define BSP_CFG_EARLY_INIT ((0))
-
-#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0))
-
-#ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED
-#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1)
-#endif
-
-#ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE
-#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0)
-#endif
-#ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE
-#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0)
-#endif
-#ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED
-#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1)
-#endif
-#ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS
-#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-#endif /* BSP_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
deleted file mode 100644
index 1a0bc02e26..0000000000
--- a/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/* generated configuration header file - do not edit */
-#ifndef BSP_MCU_DEVICE_PN_CFG_H_
-#define BSP_MCU_DEVICE_PN_CFG_H_
-#define BSP_MCU_R7FA4M3AF3CFB
-#define BSP_MCU_FEATURE_SET ('A')
-#define BSP_ROM_SIZE_BYTES (1048576)
-#define BSP_RAM_SIZE_BYTES (131072)
-#define BSP_DATA_FLASH_SIZE_BYTES (8192)
-#define BSP_PACKAGE_LQFP
-#define BSP_PACKAGE_PINS (144)
-#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra4m3_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/ra4m3_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h
new file mode 100644
index 0000000000..96087fa0d6
--- /dev/null
+++ b/hw/bsp/ra/boards/ra4m3_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h
@@ -0,0 +1,62 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_CFG_H_
+#define BSP_CFG_H_
+#ifdef __cplusplus
+ extern "C" {
+ #endif
+
+ #include "bsp_clock_cfg.h"
+ #include "bsp_mcu_family_cfg.h"
+ #include "board_cfg.h"
+ #define RA_NOT_DEFINED 0
+ #ifndef BSP_CFG_RTOS
+ #if (RA_NOT_DEFINED) != (RA_NOT_DEFINED)
+ #define BSP_CFG_RTOS (2)
+ #elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED)
+ #define BSP_CFG_RTOS (1)
+ #else
+ #define BSP_CFG_RTOS (0)
+ #endif
+ #endif
+ #ifndef BSP_CFG_RTC_USED
+ #define BSP_CFG_RTC_USED (RA_NOT_DEFINED)
+ #endif
+ #undef RA_NOT_DEFINED
+ #if defined(_RA_BOOT_IMAGE)
+ #define BSP_CFG_BOOT_IMAGE (1)
+ #endif
+ #define BSP_CFG_MCU_VCC_MV (3300)
+ #define BSP_CFG_STACK_MAIN_BYTES (0x800)
+ #define BSP_CFG_HEAP_BYTES (0x800)
+ #define BSP_CFG_PARAM_CHECKING_ENABLE (0)
+ #define BSP_CFG_ASSERT (0)
+ #define BSP_CFG_ERROR_LOG (0)
+
+ #define BSP_CFG_PFS_PROTECT ((1))
+
+ #define BSP_CFG_C_RUNTIME_INIT ((1))
+ #define BSP_CFG_EARLY_INIT ((0))
+
+ #define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0))
+
+ #ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED
+ #define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1)
+ #endif
+
+ #ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE
+ #define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0)
+ #endif
+ #ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE
+ #define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0)
+ #endif
+ #ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED
+ #define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1)
+ #endif
+ #ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS
+ #define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
+ #endif
+
+ #ifdef __cplusplus
+ }
+ #endif
+#endif /* BSP_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_mcu_device_cfg.h b/hw/bsp/ra/boards/ra4m3_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h
similarity index 100%
rename from hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_mcu_device_cfg.h
rename to hw/bsp/ra/boards/ra4m3_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h
diff --git a/hw/bsp/ra/boards/ra4m3_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/hw/bsp/ra/boards/ra4m3_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
new file mode 100644
index 0000000000..1aaa4be0af
--- /dev/null
+++ b/hw/bsp/ra/boards/ra4m3_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
@@ -0,0 +1,11 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_MCU_DEVICE_PN_CFG_H_
+#define BSP_MCU_DEVICE_PN_CFG_H_
+#define BSP_MCU_R7FA4M3AF3CFB
+ #define BSP_MCU_FEATURE_SET ('A')
+ #define BSP_ROM_SIZE_BYTES (1048576)
+ #define BSP_RAM_SIZE_BYTES (131072)
+ #define BSP_DATA_FLASH_SIZE_BYTES (8192)
+ #define BSP_PACKAGE_LQFP
+ #define BSP_PACKAGE_PINS (144)
+#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/ra4m3_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h
similarity index 57%
rename from hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h
rename to hw/bsp/ra/boards/ra4m3_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h
index d5428540fb..cb9429057f 100644
--- a/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h
+++ b/hw/bsp/ra/boards/ra4m3_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h
@@ -5,80 +5,80 @@
extern "C" {
#endif
-#include "bsp_mcu_device_pn_cfg.h"
-#include "bsp_mcu_device_cfg.h"
-#include "../../../ra/fsp/src/bsp/mcu/ra6m5/bsp_mcu_info.h"
-#include "bsp_clock_cfg.h"
-
-#define BSP_MCU_GROUP_RA6M5 (1)
-#define BSP_LOCO_HZ (32768)
-#define BSP_MOCO_HZ (8000000)
-#define BSP_SUB_CLOCK_HZ (32768)
-#if BSP_CFG_HOCO_FREQUENCY == 0
-#define BSP_HOCO_HZ (16000000)
-#elif BSP_CFG_HOCO_FREQUENCY == 1
- #define BSP_HOCO_HZ (18000000)
-#elif BSP_CFG_HOCO_FREQUENCY == 2
- #define BSP_HOCO_HZ (20000000)
-#else
- #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h"
-#endif
+ #include "bsp_mcu_device_pn_cfg.h"
+ #include "bsp_mcu_device_cfg.h"
+ #include "../../../ra/fsp/src/bsp/mcu/ra4m3/bsp_mcu_info.h"
+ #include "bsp_clock_cfg.h"
+ #define BSP_MCU_GROUP_RA4M3 (1)
+ #define BSP_LOCO_HZ (32768)
+ #define BSP_MOCO_HZ (8000000)
+ #define BSP_SUB_CLOCK_HZ (32768)
+ #if BSP_CFG_HOCO_FREQUENCY == 0
+ #define BSP_HOCO_HZ (16000000)
+ #elif BSP_CFG_HOCO_FREQUENCY == 1
+ #define BSP_HOCO_HZ (18000000)
+ #elif BSP_CFG_HOCO_FREQUENCY == 2
+ #define BSP_HOCO_HZ (20000000)
+ #else
+ #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h"
+ #endif
-#define BSP_CFG_FLL_ENABLE (0)
+ #define BSP_CFG_FLL_ENABLE (0)
-#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U)
-#define BSP_VECTOR_TABLE_MAX_ENTRIES (112U)
+ #define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U)
+ #define BSP_VECTOR_TABLE_MAX_ENTRIES (112U)
+ #define BSP_CFG_INLINE_IRQ_FUNCTIONS (1)
-#if defined(_RA_TZ_SECURE)
+ #if defined(_RA_TZ_SECURE)
#define BSP_TZ_SECURE_BUILD (1)
#define BSP_TZ_NONSECURE_BUILD (0)
#elif defined(_RA_TZ_NONSECURE)
#define BSP_TZ_SECURE_BUILD (0)
#define BSP_TZ_NONSECURE_BUILD (1)
#else
-#define BSP_TZ_SECURE_BUILD (0)
-#define BSP_TZ_NONSECURE_BUILD (0)
-#endif
-
-/* TrustZone Settings */
-#define BSP_TZ_CFG_INIT_SECURE_ONLY (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE))
-#define BSP_TZ_CFG_SKIP_INIT (BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_INIT_SECURE_ONLY)
-#define BSP_TZ_CFG_EXCEPTION_RESPONSE (0)
-
-/* CMSIS TrustZone Settings */
-#define SCB_CSR_AIRCR_INIT (1)
-#define SCB_AIRCR_BFHFNMINS_VAL (0)
-#define SCB_AIRCR_SYSRESETREQS_VAL (1)
-#define SCB_AIRCR_PRIS_VAL (0)
-#define TZ_FPU_NS_USAGE (1)
+ #define BSP_TZ_SECURE_BUILD (0)
+ #define BSP_TZ_NONSECURE_BUILD (0)
+ #endif
+
+ /* TrustZone Settings */
+ #define BSP_TZ_CFG_INIT_SECURE_ONLY (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE))
+ #define BSP_TZ_CFG_SKIP_INIT (BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_INIT_SECURE_ONLY)
+ #define BSP_TZ_CFG_EXCEPTION_RESPONSE (0)
+
+ /* CMSIS TrustZone Settings */
+ #define SCB_CSR_AIRCR_INIT (1)
+ #define SCB_AIRCR_BFHFNMINS_VAL (0)
+ #define SCB_AIRCR_SYSRESETREQS_VAL (1)
+ #define SCB_AIRCR_PRIS_VAL (0)
+ #define TZ_FPU_NS_USAGE (1)
#ifndef SCB_NSACR_CP10_11_VAL
-#define SCB_NSACR_CP10_11_VAL (3U)
+ #define SCB_NSACR_CP10_11_VAL (3U)
#endif
#ifndef FPU_FPCCR_TS_VAL
-#define FPU_FPCCR_TS_VAL (1U)
+ #define FPU_FPCCR_TS_VAL (1U)
#endif
-#define FPU_FPCCR_CLRONRETS_VAL (1)
+ #define FPU_FPCCR_CLRONRETS_VAL (1)
#ifndef FPU_FPCCR_CLRONRET_VAL
-#define FPU_FPCCR_CLRONRET_VAL (1)
+ #define FPU_FPCCR_CLRONRET_VAL (1)
#endif
-/* The C-Cache line size that is configured during startup. */
+ /* The C-Cache line size that is configured during startup. */
#ifndef BSP_CFG_C_CACHE_LINE_SIZE
-#define BSP_CFG_C_CACHE_LINE_SIZE (1U)
+ #define BSP_CFG_C_CACHE_LINE_SIZE (1U)
#endif
-/* Type 1 Peripheral Security Attribution */
+ /* Type 1 Peripheral Security Attribution */
-/* Peripheral Security Attribution Register (PSAR) Settings */
+ /* Peripheral Security Attribution Register (PSAR) Settings */
#ifndef BSP_TZ_CFG_PSARB
#define BSP_TZ_CFG_PSARB (\
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CAN1 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* CAN0 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* IIC1 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9) /* IIC0 */ | \
- (((1 > 0) ? 0U : 1U) << 11) /* USBFS */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* USBFS */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 18) /* SPI1 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 19) /* SPI0 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* SCI9 */ | \
@@ -146,19 +146,19 @@ extern "C" {
0xfffffffc) /* Unused */
#endif
-/* Type 2 Peripheral Security Attribution */
+ /* Type 2 Peripheral Security Attribution */
-/* Security attribution for Cache registers. */
+ /* Security attribution for Cache registers. */
#ifndef BSP_TZ_CFG_CSAR
#define BSP_TZ_CFG_CSAR (0xFFFFFFFFU)
#endif
-/* Security attribution for RSTSRn registers. */
+ /* Security attribution for RSTSRn registers. */
#ifndef BSP_TZ_CFG_RSTSAR
#define BSP_TZ_CFG_RSTSAR (0xFFFFFFFFU)
#endif
-/* Security attribution for registers of LVD channels. */
+ /* Security attribution for registers of LVD channels. */
#ifndef BSP_TZ_CFG_LVDSAR
#define BSP_TZ_CFG_LVDSAR (\
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) | /* LVD Channel 1 */ \
@@ -166,16 +166,16 @@ extern "C" {
0xFFFFFFFCU)
#endif
-/* Security attribution for LPM registers. */
+ /* Security attribution for LPM registers. */
#ifndef BSP_TZ_CFG_LPMSAR
#define BSP_TZ_CFG_LPMSAR ((RA_NOT_DEFINED > 0) ? 0xFFFFFCEAU : 0xFFFFFFFFU)
#endif
-/* Deep Standby Interrupt Factor Security Attribution Register. */
+ /* Deep Standby Interrupt Factor Security Attribution Register. */
#ifndef BSP_TZ_CFG_DPFSAR
#define BSP_TZ_CFG_DPFSAR ((RA_NOT_DEFINED > 0) ? 0xF2E00000U : 0xFFFFFFFFU)
#endif
-/* Security attribution for CGC registers. */
+ /* Security attribution for CGC registers. */
#ifndef BSP_TZ_CFG_CGFSAR
#if BSP_CFG_CLOCKS_SECURE
/* Protect all CGC registers from Non-secure write access. */
@@ -186,12 +186,12 @@ extern "C" {
#endif
#endif
-/* Security attribution for Battery Backup registers. */
+ /* Security attribution for Battery Backup registers. */
#ifndef BSP_TZ_CFG_BBFSAR
#define BSP_TZ_CFG_BBFSAR (0x00FFFFFF)
#endif
-/* Security attribution for registers for IRQ channels. */
+ /* Security attribution for registers for IRQ channels. */
#ifndef BSP_TZ_CFG_ICUSARA
#define BSP_TZ_CFG_ICUSARA (\
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ | \
@@ -213,12 +213,12 @@ extern "C" {
0xFFFF0000U)
#endif
-/* Security attribution for NMI registers. */
+ /* Security attribution for NMI registers. */
#ifndef BSP_TZ_CFG_ICUSARB
#define BSP_TZ_CFG_ICUSARB (0 | 0xFFFFFFFEU) /* Should match AIRCR.BFHFNMINS. */
#endif
-/* Security attribution for registers for DMAC channels */
+ /* Security attribution for registers for DMAC channels */
#ifndef BSP_TZ_CFG_ICUSARC
#define BSP_TZ_CFG_ICUSARC (\
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* DMAC Channel 0 */ | \
@@ -232,29 +232,29 @@ extern "C" {
0xFFFFFF00U)
#endif
-/* Security attribution registers for SELSR0. */
+ /* Security attribution registers for SELSR0. */
#ifndef BSP_TZ_CFG_ICUSARD
#define BSP_TZ_CFG_ICUSARD ((RA_NOT_DEFINED > 0) ? 0xFFFFFFFEU : 0xFFFFFFFFU)
#endif
-/* Security attribution registers for WUPEN0. */
+ /* Security attribution registers for WUPEN0. */
#ifndef BSP_TZ_CFG_ICUSARE
#define BSP_TZ_CFG_ICUSARE ((RA_NOT_DEFINED > 0) ? 0x04F2FFFFU : 0xFFFFFFFFU)
#endif
-/* Security attribution registers for WUPEN1. */
+ /* Security attribution registers for WUPEN1. */
#ifndef BSP_TZ_CFG_ICUSARF
#define BSP_TZ_CFG_ICUSARF ((RA_NOT_DEFINED > 0) ? 0xFFFFFFF8U : 0xFFFFFFFFU)
#endif
-/* Set DTCSTSAR if the Secure program uses the DTC. */
+ /* Set DTCSTSAR if the Secure program uses the DTC. */
#if RA_NOT_DEFINED == RA_NOT_DEFINED
-#define BSP_TZ_CFG_DTC_USED (0U)
+ #define BSP_TZ_CFG_DTC_USED (0U)
#else
#define BSP_TZ_CFG_DTC_USED (1U)
#endif
-/* Security attribution of FLWT and FCKMHZ registers. */
+ /* Security attribution of FLWT and FCKMHZ registers. */
#ifndef BSP_TZ_CFG_FSAR
/* If the CGC registers are only accessible in Secure mode, than there is no
* reason for nonsecure applications to access FLWT and FCKMHZ. */
@@ -267,118 +267,119 @@ extern "C" {
#endif
#endif
-/* Security attribution for SRAM registers. */
+ /* Security attribution for SRAM registers. */
#ifndef BSP_TZ_CFG_SRAMSAR
/* If the CGC registers are only accessible in Secure mode, than there is no reason for Non Secure applications to access
* SRAM0WTEN and therefore there is no reason to access PRCR2. */
-#define BSP_TZ_CFG_SRAMSAR (\
+ #define BSP_TZ_CFG_SRAMSAR (\
1 | \
((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 1U) : 0U) | \
4 | \
0xFFFFFFF8U)
#endif
-/* Security attribution for Standby RAM registers. */
+ /* Security attribution for Standby RAM registers. */
#ifndef BSP_TZ_CFG_STBRAMSAR
-#define BSP_TZ_CFG_STBRAMSAR (0 | 0xFFFFFFF0U)
+ #define BSP_TZ_CFG_STBRAMSAR (0 | 0xFFFFFFF0U)
#endif
-/* Security attribution for the DMAC Bus Master MPU settings. */
+ /* Security attribution for the DMAC Bus Master MPU settings. */
#ifndef BSP_TZ_CFG_MMPUSARA
-/* The DMAC Bus Master MPU settings should align with the DMAC channel settings. */
-#define BSP_TZ_CFG_MMPUSARA (BSP_TZ_CFG_ICUSARC)
+ /* The DMAC Bus Master MPU settings should align with the DMAC channel settings. */
+ #define BSP_TZ_CFG_MMPUSARA (BSP_TZ_CFG_ICUSARC)
#endif
-/* Security Attribution Register A for BUS Control registers. */
+ /* Security Attribution Register A for BUS Control registers. */
#ifndef BSP_TZ_CFG_BUSSARA
-#define BSP_TZ_CFG_BUSSARA (0xFFFFFFFFU)
+ #define BSP_TZ_CFG_BUSSARA (0xFFFFFFFFU)
#endif
-/* Security Attribution Register B for BUS Control registers. */
+ /* Security Attribution Register B for BUS Control registers. */
#ifndef BSP_TZ_CFG_BUSSARB
-#define BSP_TZ_CFG_BUSSARB (0xFFFFFFFFU)
+ #define BSP_TZ_CFG_BUSSARB (0xFFFFFFFFU)
#endif
-/* Enable Uninitialized Non-Secure Application Fallback. */
+ /* Enable Uninitialized Non-Secure Application Fallback. */
#ifndef BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK
-#define BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK (1U)
+ #define BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK (1U)
#endif
-#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2)
-#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10)
-#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17)
-#define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26)
-#define OFS_SEQ5 (1 << 28) | (1 << 30)
-#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
-/* Option Function Select Register 1 Security Attribution */
+ #define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2)
+ #define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10)
+ #define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17)
+ #define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26)
+ #define OFS_SEQ5 (1 << 28) | (1 << 30)
+ #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
+
+ /* Option Function Select Register 1 Security Attribution */
#ifndef BSP_CFG_ROM_REG_OFS1_SEL
#if defined(_RA_TZ_SECURE) || defined(_RA_TZ_NONSECURE)
- #define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0x700U : 0U) | ((RA_NOT_DEFINED > 0) ? 0U : 0x7U))
+ #define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U | ((0U << 0U)) | ((0U << 2U)) | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0x700U : 0U))
#else
-#define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U)
+ #define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U)
#endif
#endif
-#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) | (1 << 8))
+ #define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) | (1 << 8))
-/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */
-#define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector)
+ /* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */
+ #define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector)
-/* Dual Mode Select Register */
+ /* Dual Mode Select Register */
#ifndef BSP_CFG_ROM_REG_DUALSEL
-#define BSP_CFG_ROM_REG_DUALSEL (0xFFFFFFF8U | (0x7U))
+ #define BSP_CFG_ROM_REG_DUALSEL (0xFFFFFFFFU)
#endif
-/* Block Protection Register 0 */
+ /* Block Protection Register 0 */
#ifndef BSP_CFG_ROM_REG_BPS0
-#define BSP_CFG_ROM_REG_BPS0 (~( 0U))
+ #define BSP_CFG_ROM_REG_BPS0 (~( 0U))
#endif
-/* Block Protection Register 1 */
+ /* Block Protection Register 1 */
#ifndef BSP_CFG_ROM_REG_BPS1
-#define BSP_CFG_ROM_REG_BPS1 (~( 0U))
+ #define BSP_CFG_ROM_REG_BPS1 (~( 0U))
#endif
-/* Block Protection Register 2 */
+ /* Block Protection Register 2 */
#ifndef BSP_CFG_ROM_REG_BPS2
-#define BSP_CFG_ROM_REG_BPS2 (~( 0U))
+ #define BSP_CFG_ROM_REG_BPS2 (0xFFFFFFFFU)
#endif
-/* Block Protection Register 3 */
+ /* Block Protection Register 3 */
#ifndef BSP_CFG_ROM_REG_BPS3
-#define BSP_CFG_ROM_REG_BPS3 (0xFFFFFFFFU)
+ #define BSP_CFG_ROM_REG_BPS3 (0xFFFFFFFFU)
#endif
-/* Permanent Block Protection Register 0 */
+ /* Permanent Block Protection Register 0 */
#ifndef BSP_CFG_ROM_REG_PBPS0
-#define BSP_CFG_ROM_REG_PBPS0 (~( 0U))
+ #define BSP_CFG_ROM_REG_PBPS0 (~( 0U))
#endif
-/* Permanent Block Protection Register 1 */
+ /* Permanent Block Protection Register 1 */
#ifndef BSP_CFG_ROM_REG_PBPS1
-#define BSP_CFG_ROM_REG_PBPS1 (~( 0U))
+ #define BSP_CFG_ROM_REG_PBPS1 (~( 0U))
#endif
-/* Permanent Block Protection Register 2 */
+ /* Permanent Block Protection Register 2 */
#ifndef BSP_CFG_ROM_REG_PBPS2
-#define BSP_CFG_ROM_REG_PBPS2 (~( 0U))
+ #define BSP_CFG_ROM_REG_PBPS2 (0xFFFFFFFFU)
#endif
-/* Permanent Block Protection Register 3 */
+ /* Permanent Block Protection Register 3 */
#ifndef BSP_CFG_ROM_REG_PBPS3
-#define BSP_CFG_ROM_REG_PBPS3 (0xFFFFFFFFU)
+ #define BSP_CFG_ROM_REG_PBPS3 (0xFFFFFFFFU)
#endif
-/* Security Attribution for Block Protection Register 0 (If any blocks are marked as protected in the secure application, then mark them as secure) */
+ /* Security Attribution for Block Protection Register 0 (If any blocks are marked as protected in the secure application, then mark them as secure) */
#ifndef BSP_CFG_ROM_REG_BPS_SEL0
-#define BSP_CFG_ROM_REG_BPS_SEL0 (BSP_CFG_ROM_REG_BPS0 & BSP_CFG_ROM_REG_PBPS0)
+ #define BSP_CFG_ROM_REG_BPS_SEL0 (BSP_CFG_ROM_REG_BPS0 & BSP_CFG_ROM_REG_PBPS0)
#endif
-/* Security Attribution for Block Protection Register 1 (If any blocks are marked as protected in the secure application, then mark them as secure) */
+ /* Security Attribution for Block Protection Register 1 (If any blocks are marked as protected in the secure application, then mark them as secure) */
#ifndef BSP_CFG_ROM_REG_BPS_SEL1
-#define BSP_CFG_ROM_REG_BPS_SEL1 (BSP_CFG_ROM_REG_BPS1 & BSP_CFG_ROM_REG_PBPS1)
+ #define BSP_CFG_ROM_REG_BPS_SEL1 (BSP_CFG_ROM_REG_BPS1 & BSP_CFG_ROM_REG_PBPS1)
#endif
-/* Security Attribution for Block Protection Register 2 (If any blocks are marked as protected in the secure application, then mark them as secure) */
+ /* Security Attribution for Block Protection Register 2 (If any blocks are marked as protected in the secure application, then mark them as secure) */
#ifndef BSP_CFG_ROM_REG_BPS_SEL2
-#define BSP_CFG_ROM_REG_BPS_SEL2 (BSP_CFG_ROM_REG_BPS2 & BSP_CFG_ROM_REG_PBPS2)
+ #define BSP_CFG_ROM_REG_BPS_SEL2 (0xFFFFFFFFU)
#endif
-/* Security Attribution for Block Protection Register 3 (If any blocks are marked as protected in the secure application, then mark them as secure) */
+ /* Security Attribution for Block Protection Register 3 (If any blocks are marked as protected in the secure application, then mark them as secure) */
#ifndef BSP_CFG_ROM_REG_BPS_SEL3
-#define BSP_CFG_ROM_REG_BPS_SEL3 (BSP_CFG_ROM_REG_BPS3 & BSP_CFG_ROM_REG_PBPS3)
+ #define BSP_CFG_ROM_REG_BPS_SEL3 (0xFFFFFFFFU)
#endif
#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT
-#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9)
+ #define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9)
#endif
#ifdef __cplusplus
diff --git a/hw/bsp/ra/boards/ra4m3_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h b/hw/bsp/ra/boards/ra4m3_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h
new file mode 100644
index 0000000000..8ed58a11be
--- /dev/null
+++ b/hw/bsp/ra/boards/ra4m3_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h
@@ -0,0 +1,67 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_PIN_CFG_H_
+#define BSP_PIN_CFG_H_
+#include "r_ioport.h"
+
+/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+#define ARDUINO_A0_MIKROBUS_AN (BSP_IO_PORT_00_PIN_00)
+#define ARDUINO_A1 (BSP_IO_PORT_00_PIN_01)
+#define ARDUINO_A2 (BSP_IO_PORT_00_PIN_03)
+#define SW1 (BSP_IO_PORT_00_PIN_05)
+#define SW2 (BSP_IO_PORT_00_PIN_06)
+#define ARDUINO_A3 (BSP_IO_PORT_00_PIN_07)
+#define PMOD1_INT (BSP_IO_PORT_00_PIN_08)
+#define ARDUINO_A4 (BSP_IO_PORT_00_PIN_14)
+#define ARDUINO_A5 (BSP_IO_PORT_00_PIN_15)
+#define ARDUINO_RX_MIKROBUS_RX (BSP_IO_PORT_01_PIN_00)
+#define ARDUINO_TX_MIKROBUS_TX (BSP_IO_PORT_01_PIN_01)
+#define ARDUINO_D2 (BSP_IO_PORT_01_PIN_05)
+#define ARDUINO_D3 (BSP_IO_PORT_01_PIN_11)
+#define MIKROBUS_RST (BSP_IO_PORT_01_PIN_15)
+#define ARDUINO_MISO_MIKROBUS_MISO_PMOD1_MISO (BSP_IO_PORT_02_PIN_02)
+#define ARDUINO_MOSI_MIKROBUS_MOSI_PMOD1_MOSI (BSP_IO_PORT_02_PIN_03)
+#define ARDUINO_CLK_MIKROBUS_CLK_PMOD1_CLK (BSP_IO_PORT_02_PIN_04)
+#define ARDUINO_SS_MIKCRBUS_SS (BSP_IO_PORT_02_PIN_05)
+#define PMOD1_SS1 (BSP_IO_PORT_02_PIN_06)
+#define PMOD1_SS2 (BSP_IO_PORT_02_PIN_07)
+#define PMOD1_SS3 (BSP_IO_PORT_03_PIN_02)
+#define ARDUINO_D9 (BSP_IO_PORT_03_PIN_03)
+#define ARDUINO_D7 (BSP_IO_PORT_03_PIN_04)
+#define QSPI_CLK (BSP_IO_PORT_03_PIN_05)
+#define QSPI_SSL (BSP_IO_PORT_03_PIN_06)
+#define QSPI_IO0 (BSP_IO_PORT_03_PIN_07)
+#define QSPI_IO1 (BSP_IO_PORT_03_PIN_08)
+#define QSPI_IO2 (BSP_IO_PORT_03_PIN_09)
+#define QSPI_IO3 (BSP_IO_PORT_03_PIN_10)
+#define PMOD1_RST (BSP_IO_PORT_03_PIN_11)
+#define LED3 (BSP_IO_PORT_04_PIN_00)
+#define LED2 (BSP_IO_PORT_04_PIN_04)
+#define USB_VBUS (BSP_IO_PORT_04_PIN_07)
+#define ARDUINO_D6_MIKROBUS_PWM (BSP_IO_PORT_04_PIN_08)
+#define MIKROBUS_INT (BSP_IO_PORT_04_PIN_09)
+#define PMOD2_INT (BSP_IO_PORT_04_PIN_14)
+#define LED1 (BSP_IO_PORT_04_PIN_15)
+#define USB_VBUS_EN (BSP_IO_PORT_05_PIN_00)
+#define USB_VBUS_OC (BSP_IO_PORT_05_PIN_01)
+#define GROVE2_AN1 (BSP_IO_PORT_05_PIN_05)
+#define GROVE2_AN2 (BSP_IO_PORT_05_PIN_06)
+#define GROVE1_SDA_QWIIC_SDA (BSP_IO_PORT_05_PIN_11)
+#define GROVE1_SCL_QWIIC_SCL (BSP_IO_PORT_05_PIN_12)
+#define ARDUINO_SCL_MIKROBUS_SCL (BSP_IO_PORT_06_PIN_01)
+#define ARDUINO_SDA_MIKROBUS_SDA (BSP_IO_PORT_06_PIN_02)
+#define ARDUINO_D8 (BSP_IO_PORT_06_PIN_11)
+#define ARDUINO_RST (BSP_IO_PORT_06_PIN_12)
+#define PMOD2_RST (BSP_IO_PORT_07_PIN_08)
+#define PMOD2_SS2 (BSP_IO_PORT_07_PIN_09)
+#define PMOD2_SS3 (BSP_IO_PORT_07_PIN_10)
+#define ARDUINO_D5 (BSP_IO_PORT_07_PIN_12)
+#define ARDUINO_D4 (BSP_IO_PORT_07_PIN_13)
+extern const ioport_cfg_t g_bsp_pin_cfg; /* RA4M3 EK */
+
+void BSP_PinConfigSecurityInit();
+
+/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+#endif /* BSP_PIN_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra4m3_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h b/hw/bsp/ra/boards/ra4m3_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h
new file mode 100644
index 0000000000..d2688bf5ba
--- /dev/null
+++ b/hw/bsp/ra/boards/ra4m3_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h
@@ -0,0 +1,13 @@
+/* generated configuration header file - do not edit */
+#ifndef R_IOPORT_CFG_H_
+#define R_IOPORT_CFG_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* R_IOPORT_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp_clock_cfg.h b/hw/bsp/ra/boards/ra4m3_ek/ra_gen/bsp_clock_cfg.h
similarity index 82%
rename from hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp_clock_cfg.h
rename to hw/bsp/ra/boards/ra4m3_ek/ra_gen/bsp_clock_cfg.h
index 80641945d6..3eac2985ee 100644
--- a/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp_clock_cfg.h
+++ b/hw/bsp/ra/boards/ra4m3_ek/ra_gen/bsp_clock_cfg.h
@@ -7,10 +7,10 @@
#define BSP_CFG_HOCO_FREQUENCY (2) /* HOCO 20MHz */
#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */
#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_3) /* PLL Div /3 */
-#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(24U,0U) /* PLL Mul x24.0 */
+#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(25U,0U) /* PLL Mul x25.0 */
#define BSP_CFG_PLL2_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL2 Src: XTAL */
-#define BSP_CFG_PLL2_DIV (BSP_CLOCKS_PLL_DIV_3) /* PLL2 Div /3 */
-#define BSP_CFG_PLL2_MUL BSP_CLOCKS_PLL_MUL(24U,0U) /* PLL2 Mul x24.0 */
+#define BSP_CFG_PLL2_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL2 Div /2 */
+#define BSP_CFG_PLL2_MUL BSP_CLOCKS_PLL_MUL(20U,0U) /* PLL2 Mul x20.0 */
#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */
#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */
#define BSP_CFG_UCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2) /* UCLK Src: PLL2 */
@@ -21,5 +21,5 @@
#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKD Div /2 */
#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* FCLK Div /4 */
#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */
-#define BSP_CFG_UCK_DIV (BSP_CLOCKS_USB_CLOCK_DIV_4) /* UCLK Div /4 */
+#define BSP_CFG_UCK_DIV (BSP_CLOCKS_USB_CLOCK_DIV_5) /* UCLK Div /5 */
#endif /* BSP_CLOCK_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra4m3_ek/ra_gen/common_data.c b/hw/bsp/ra/boards/ra4m3_ek/ra_gen/common_data.c
new file mode 100644
index 0000000000..50036c0adc
--- /dev/null
+++ b/hw/bsp/ra/boards/ra4m3_ek/ra_gen/common_data.c
@@ -0,0 +1,11 @@
+/* generated common source file - do not edit */
+#include "common_data.h"
+ioport_instance_ctrl_t g_ioport_ctrl;
+const ioport_instance_t g_ioport =
+ {
+ .p_api = &g_ioport_on_ioport,
+ .p_ctrl = &g_ioport_ctrl,
+ .p_cfg = &g_bsp_pin_cfg,
+ };
+void g_common_init(void) {
+}
diff --git a/hw/bsp/ra/boards/ra4m3_ek/ra_gen/common_data.h b/hw/bsp/ra/boards/ra4m3_ek/ra_gen/common_data.h
new file mode 100644
index 0000000000..6a08cbee09
--- /dev/null
+++ b/hw/bsp/ra/boards/ra4m3_ek/ra_gen/common_data.h
@@ -0,0 +1,20 @@
+/* generated common header file - do not edit */
+#ifndef COMMON_DATA_H_
+#define COMMON_DATA_H_
+#include
+#include "bsp_api.h"
+#include "r_ioport.h"
+#include "bsp_pin_cfg.h"
+FSP_HEADER
+#define IOPORT_CFG_NAME g_bsp_pin_cfg
+#define IOPORT_CFG_OPEN R_IOPORT_Open
+#define IOPORT_CFG_CTRL g_ioport_ctrl
+
+/* IOPORT Instance */
+extern const ioport_instance_t g_ioport;
+
+/* IOPORT control structure. */
+extern ioport_instance_ctrl_t g_ioport_ctrl;
+void g_common_init(void);
+FSP_FOOTER
+#endif /* COMMON_DATA_H_ */
diff --git a/hw/bsp/ra/boards/ra4m3_ek/ra_gen/pin_data.c b/hw/bsp/ra/boards/ra4m3_ek/ra_gen/pin_data.c
new file mode 100644
index 0000000000..bf30782cf5
--- /dev/null
+++ b/hw/bsp/ra/boards/ra4m3_ek/ra_gen/pin_data.c
@@ -0,0 +1,263 @@
+/* generated pin source file - do not edit */
+#include "bsp_api.h"
+#include "r_ioport.h"
+
+
+const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = {
+ {
+ .pin = BSP_IO_PORT_00_PIN_00,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE)
+ },
+ {
+ .pin = BSP_IO_PORT_00_PIN_01,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE)
+ },
+ {
+ .pin = BSP_IO_PORT_00_PIN_03,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE)
+ },
+ {
+ .pin = BSP_IO_PORT_00_PIN_05,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT)
+ },
+ {
+ .pin = BSP_IO_PORT_00_PIN_06,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_IRQ_ENABLE | (uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT)
+ },
+ {
+ .pin = BSP_IO_PORT_00_PIN_07,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE)
+ },
+ {
+ .pin = BSP_IO_PORT_00_PIN_08,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_IRQ_ENABLE | (uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT | (uint32_t) IOPORT_CFG_PULLUP_ENABLE)
+ },
+ {
+ .pin = BSP_IO_PORT_00_PIN_14,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE)
+ },
+ {
+ .pin = BSP_IO_PORT_00_PIN_15,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE)
+ },
+ {
+ .pin = BSP_IO_PORT_01_PIN_00,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI0_2_4_6_8)
+ },
+ {
+ .pin = BSP_IO_PORT_01_PIN_01,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI0_2_4_6_8)
+ },
+ {
+ .pin = BSP_IO_PORT_01_PIN_05,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+ },
+ {
+ .pin = BSP_IO_PORT_01_PIN_08,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG)
+ },
+ {
+ .pin = BSP_IO_PORT_01_PIN_11,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+ },
+ {
+ .pin = BSP_IO_PORT_01_PIN_15,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+ },
+ {
+ .pin = BSP_IO_PORT_02_PIN_02,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
+ },
+ {
+ .pin = BSP_IO_PORT_02_PIN_03,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
+ },
+ {
+ .pin = BSP_IO_PORT_02_PIN_04,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
+ },
+ {
+ .pin = BSP_IO_PORT_02_PIN_05,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
+ },
+ {
+ .pin = BSP_IO_PORT_02_PIN_06,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
+ },
+ {
+ .pin = BSP_IO_PORT_02_PIN_07,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
+ },
+ {
+ .pin = BSP_IO_PORT_03_PIN_00,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG)
+ },
+ {
+ .pin = BSP_IO_PORT_03_PIN_02,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
+ },
+ {
+ .pin = BSP_IO_PORT_03_PIN_03,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+ },
+ {
+ .pin = BSP_IO_PORT_03_PIN_04,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+ },
+ {
+ .pin = BSP_IO_PORT_03_PIN_05,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_QSPI)
+ },
+ {
+ .pin = BSP_IO_PORT_03_PIN_06,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_QSPI)
+ },
+ {
+ .pin = BSP_IO_PORT_03_PIN_07,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_QSPI)
+ },
+ {
+ .pin = BSP_IO_PORT_03_PIN_08,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_QSPI)
+ },
+ {
+ .pin = BSP_IO_PORT_03_PIN_09,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_QSPI)
+ },
+ {
+ .pin = BSP_IO_PORT_03_PIN_10,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_QSPI)
+ },
+ {
+ .pin = BSP_IO_PORT_03_PIN_11,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+ },
+ {
+ .pin = BSP_IO_PORT_04_PIN_00,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+ },
+ {
+ .pin = BSP_IO_PORT_04_PIN_04,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+ },
+ {
+ .pin = BSP_IO_PORT_04_PIN_07,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)
+ },
+ {
+ .pin = BSP_IO_PORT_04_PIN_08,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_GPT1)
+ },
+ {
+ .pin = BSP_IO_PORT_04_PIN_09,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_IRQ_ENABLE | (uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT | (uint32_t) IOPORT_CFG_PULLUP_ENABLE)
+ },
+ {
+ .pin = BSP_IO_PORT_04_PIN_14,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_IRQ_ENABLE | (uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT | (uint32_t) IOPORT_CFG_PULLUP_ENABLE)
+ },
+ {
+ .pin = BSP_IO_PORT_04_PIN_15,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+ },
+ {
+ .pin = BSP_IO_PORT_05_PIN_00,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)
+ },
+ {
+ .pin = BSP_IO_PORT_05_PIN_01,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)
+ },
+ {
+ .pin = BSP_IO_PORT_05_PIN_05,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE)
+ },
+ {
+ .pin = BSP_IO_PORT_05_PIN_06,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE)
+ },
+ {
+ .pin = BSP_IO_PORT_05_PIN_11,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_IIC)
+ },
+ {
+ .pin = BSP_IO_PORT_05_PIN_12,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_IIC)
+ },
+ {
+ .pin = BSP_IO_PORT_06_PIN_01,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_NMOS_ENABLE | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI1_3_5_7_9)
+ },
+ {
+ .pin = BSP_IO_PORT_06_PIN_02,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_NMOS_ENABLE | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI1_3_5_7_9)
+ },
+ {
+ .pin = BSP_IO_PORT_06_PIN_11,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+ },
+ {
+ .pin = BSP_IO_PORT_06_PIN_12,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+ },
+ {
+ .pin = BSP_IO_PORT_07_PIN_08,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+ },
+ {
+ .pin = BSP_IO_PORT_07_PIN_09,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+ },
+ {
+ .pin = BSP_IO_PORT_07_PIN_10,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+ },
+ {
+ .pin = BSP_IO_PORT_07_PIN_12,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+ },
+ {
+ .pin = BSP_IO_PORT_07_PIN_13,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+ },
+};
+
+const ioport_cfg_t g_bsp_pin_cfg = {
+ .number_of_pins = sizeof(g_bsp_pin_cfg_data)/sizeof(ioport_pin_cfg_t),
+ .p_pin_cfg_data = &g_bsp_pin_cfg_data[0],
+};
+
+#if BSP_TZ_SECURE_BUILD
+
+void R_BSP_PinCfgSecurityInit(void);
+
+/* Initialize SAR registers for secure pins. */
+void R_BSP_PinCfgSecurityInit(void)
+{
+ #if (2U == BSP_FEATURE_IOPORT_VERSION)
+ uint32_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR];
+ #else
+ uint16_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR];
+ #endif
+ memset(pmsar, 0xFF, BSP_FEATURE_BSP_NUM_PMSAR * sizeof(R_PMISC->PMSAR[0]));
+
+
+ for(uint32_t i = 0; i < g_bsp_pin_cfg.number_of_pins; i++)
+ {
+ uint32_t port_pin = g_bsp_pin_cfg.p_pin_cfg_data[i].pin;
+ uint32_t port = port_pin >> 8U;
+ uint32_t pin = port_pin & 0xFFU;
+ pmsar[port] &= (uint16_t) ~(1U << pin);
+ }
+
+ for(uint32_t i = 0; i < BSP_FEATURE_BSP_NUM_PMSAR; i++)
+ {
+ #if (2U == BSP_FEATURE_IOPORT_VERSION)
+ R_PMISC->PMSAR[i].PMSAR = (uint16_t) pmsar[i];
+ #else
+ R_PMISC->PMSAR[i].PMSAR = pmsar[i];
+ #endif
+ }
+
+}
+#endif
diff --git a/hw/bsp/ra/boards/ra4m3_ek/script/fsp.ld b/hw/bsp/ra/boards/ra4m3_ek/script/fsp.ld
new file mode 100644
index 0000000000..605eef7d2c
--- /dev/null
+++ b/hw/bsp/ra/boards/ra4m3_ek/script/fsp.ld
@@ -0,0 +1,769 @@
+/*
+ Linker File for Renesas FSP
+*/
+
+INCLUDE memory_regions.ld
+
+/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/
+/*
+ XIP_SECONDARY_SLOT_IMAGE = 1;
+*/
+
+QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH);
+OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH);
+OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH);
+
+/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */
+__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0);
+
+ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0;
+ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0;
+DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0;
+DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0;
+RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0;
+RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0;
+RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH;
+RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH;
+
+OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80;
+
+/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings.
+ * Bootloader images do not configure option settings because they are owned by the bootloader.
+ * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */
+__bl_FSP_BOOTABLE_IMAGE = 1;
+__bln_FSP_BOOTABLE_IMAGE = 1;
+PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE);
+USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE);
+
+__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+ FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH :
+ (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH :
+ FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH;
+__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+ FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH;
+__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH;
+__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+ FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH;
+__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH;
+__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+ FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
+ __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH;
+__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+ FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
+ __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH;
+__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+ FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH :
+ RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH;
+__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+ FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH :
+ __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH;
+__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+ FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
+ __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2;
+__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START);
+__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+ FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
+ FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2;
+
+XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0;
+FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START :
+ XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START :
+ FLASH_IMAGE_START;
+LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH :
+ DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH :
+ FLASH_LENGTH;
+OPTION_SETTING_SAS_SIZE = 0x34;
+OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 :
+ OPTION_SETTING_LENGTH == 0 ? 0 :
+ OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE;
+
+/* Define memory regions. */
+MEMORY
+{
+ ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH
+ DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH
+ FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH
+ RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH
+ DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH
+ QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH
+ OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH
+ OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH
+ OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH
+ OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH
+ SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH
+ OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH
+ OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18
+ OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH
+ OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH
+ ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH
+}
+
+/* Library configurations */
+GROUP(libgcc.a libc.a libm.a)
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be DEFINED in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __copy_table_start__
+ * __copy_table_end__
+ * __zero_table_start__
+ * __zero_table_end__
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ * __Vectors_End
+ * __Vectors_Size
+ * __qspi_flash_start__
+ * __qspi_flash_end__
+ * __qspi_flash_code_size__
+ * __qspi_region_max_size__
+ * __qspi_region_start_address__
+ * __qspi_region_end_address__
+ * __ospi_device_0_start__
+ * __ospi_device_0_end__
+ * __ospi_device_0_code_size__
+ * __ospi_device_0_region_max_size__
+ * __ospi_device_0_region_start_address__
+ * __ospi_device_0_region_end_address__
+ * __ospi_device_1_start__
+ * __ospi_device_1_end__
+ * __ospi_device_1_code_size__
+ * __ospi_device_1_region_max_size__
+ * __ospi_device_1_region_start_address__
+ * __ospi_device_1_region_end_address__
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ __tz_FLASH_S = ABSOLUTE(FLASH_START);
+ __ROM_Start = .;
+
+ /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much
+ * space because ROM registers are at address 0x400 and there is very little space
+ * in between. */
+ KEEP(*(.fixed_vectors*))
+ KEEP(*(.application_vectors*))
+ __Vectors_End = .;
+
+ /* Some devices have a gap of code flash between the vector table and ROM Registers.
+ * The flash gap section allows applications to place code and data in this section. */
+ *(.flash_gap*)
+
+ /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */
+ . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400;
+ KEEP(*(.rom_registers*))
+
+ /* Reserving 0x100 bytes of space for ROM registers. */
+ . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x500;
+
+ /* Allocate flash write-boundary-aligned
+ * space for sce9 wrapped public keys for mcuboot if the module is used.
+ */
+ KEEP(*(.mcuboot_sce9_key*))
+
+ *(.text*)
+
+ KEEP(*(.version))
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+ __usb_dev_descriptor_start_fs = .;
+ KEEP(*(.usb_device_desc_fs*))
+ __usb_cfg_descriptor_start_fs = .;
+ KEEP(*(.usb_config_desc_fs*))
+ __usb_interface_descriptor_start_fs = .;
+ KEEP(*(.usb_interface_desc_fs*))
+ __usb_descriptor_end_fs = .;
+ __usb_dev_descriptor_start_hs = .;
+ KEEP(*(.usb_device_desc_hs*))
+ __usb_cfg_descriptor_start_hs = .;
+ KEEP(*(.usb_config_desc_hs*))
+ __usb_interface_descriptor_start_hs = .;
+ KEEP(*(.usb_interface_desc_hs*))
+ __usb_descriptor_end_hs = .;
+
+ KEEP(*(.eh_frame*))
+
+ __ROM_End = .;
+ } > FLASH = 0xFF
+
+ __Vectors_Size = __Vectors_End - __Vectors;
+
+ . = .;
+ __itcm_data_pre_location = .;
+
+ /* Initialized ITCM data. */
+ /* Aligned to FCACHE2 for RA8. */
+ .itcm_data : ALIGN(16)
+ {
+ /* Start of ITCM Secure Trustzone region. */
+ __tz_ITCM_S = ABSOLUTE(ITCM_START);
+
+ /* All ITCM data start */
+ __itcm_data_start = .;
+
+ KEEP(*(.itcm_data*))
+
+ /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */
+ . = ALIGN(8);
+
+ /* All ITCM data end */
+ __itcm_data_end = .;
+
+ /*
+ * Start of the ITCM Non-Secure Trustzone region.
+ * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects.
+ */
+ __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192);
+ } > ITCM AT > FLASH = 0x00
+
+ /* Addresses exported for ITCM initialization. */
+ __itcm_data_init_start = LOADADDR(.itcm_data);
+ __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data);
+
+ ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.")
+ ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.")
+ ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.")
+ ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.")
+
+ /* Restore location counter. */
+ /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */
+ /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */
+ . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location;
+
+ __exidx_start = .;
+ /DISCARD/ :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ }
+ __exidx_end = .;
+
+ /* To copy multiple ROM to RAM sections,
+ * uncomment .copy.table section and,
+ * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+ /*
+ .copy.table :
+ {
+ . = ALIGN(4);
+ __copy_table_start__ = .;
+ LONG (__etext)
+ LONG (__data_start__)
+ LONG (__data_end__ - __data_start__)
+ LONG (__etext2)
+ LONG (__data2_start__)
+ LONG (__data2_end__ - __data2_start__)
+ __copy_table_end__ = .;
+ } > FLASH
+ */
+
+ /* To clear multiple BSS sections,
+ * uncomment .zero.table section and,
+ * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+ /*
+ .zero.table :
+ {
+ . = ALIGN(4);
+ __zero_table_start__ = .;
+ LONG (__bss_start__)
+ LONG (__bss_end__ - __bss_start__)
+ LONG (__bss2_start__)
+ LONG (__bss2_end__ - __bss2_start__)
+ __zero_table_end__ = .;
+ } > FLASH
+ */
+
+ __etext = .;
+
+ __tz_RAM_S = ORIGIN(RAM);
+
+ /* If DTC is used, put the DTC vector table at the start of SRAM.
+ This avoids memory holes due to 1K alignment required by it. */
+ .fsp_dtc_vector_table (NOLOAD) :
+ {
+ . = ORIGIN(RAM);
+ *(.fsp_dtc_vector_table)
+ } > RAM
+
+ /* Initialized data section. */
+ .data :
+ {
+ __data_start__ = .;
+ . = ALIGN(4);
+
+ __Code_In_RAM_Start = .;
+
+ KEEP(*(.code_in_ram*))
+ __Code_In_RAM_End = .;
+
+ *(vtable)
+ /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */
+ *(.data.*)
+ *(.data)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+
+ . = ALIGN(4);
+
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM AT > FLASH
+
+ . = .;
+ __dtcm_data_pre_location = LOADADDR(.data) + SIZEOF(.data);
+
+ /* Initialized DTCM data. */
+ /* Aligned to FCACHE2 for RA8. */
+ .dtcm_data : ALIGN(16)
+ {
+ /* Start of DTCM Secure Trustzone region. */
+ __tz_DTCM_S = ABSOLUTE(DTCM_START);
+
+ /* Initialized DTCM data start */
+ __dtcm_data_start = .;
+
+ KEEP(*(.dtcm_data*))
+
+ /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */
+ . = ALIGN(8);
+
+ /* Initialized DTCM data end */
+ __dtcm_data_end = .;
+ } > DTCM AT > FLASH = 0x00
+
+ . = __dtcm_data_end;
+ /* Uninitialized DTCM data. */
+ /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */
+ .dtcm_bss ALIGN(8) (NOLOAD) :
+ {
+ /* Uninitialized DTCM data start */
+ __dtcm_bss_start = .;
+
+ KEEP(*(.dtcm_bss*))
+
+ /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */
+ . = ALIGN(8);
+
+ /* Uninitialized DTCM data end */
+ __dtcm_bss_end = .;
+
+ /*
+ * Start of the DTCM Non-Secure Trustzone region.
+ * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects.
+ */
+ __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192);
+ } > DTCM
+
+ /* Addresses exported for DTCM initialization. */
+ __dtcm_data_init_start = LOADADDR(.dtcm_data);
+ __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data);
+
+ ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.")
+ ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.")
+ ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).")
+ ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.")
+ ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.")
+ ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.")
+ ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.")
+ ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.")
+
+ /* Restore location counter. */
+ /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */
+ /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */
+ . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location;
+
+ /* TrustZone Secure Gateway Stubs Section */
+
+ /* Store location counter for SPI non-retentive sections. */
+ sgstubs_pre_location = .;
+
+ /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */
+ SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024);
+ .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024)
+ {
+ __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024);
+ _start_sg = .;
+ *(.gnu.sgstubs*)
+ . = ALIGN(32);
+ _end_sg = .;
+ } > FLASH
+
+ __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768);
+ FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N;
+
+ /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */
+ __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH);
+
+ /* QSPI_FLASH section to be downloaded via debugger */
+ .qspi_flash :
+ {
+ __qspi_flash_start__ = .;
+ KEEP(*(.qspi_flash*))
+ KEEP(*(.code_in_qspi*))
+ __qspi_flash_end__ = .;
+ } > QSPI_FLASH
+ __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__;
+
+ /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */
+ __qspi_flash_code_addr__ = sgstubs_pre_location;
+ .qspi_non_retentive : AT(__qspi_flash_code_addr__)
+ {
+ __qspi_non_retentive_start__ = .;
+ KEEP(*(.qspi_non_retentive*))
+ __qspi_non_retentive_end__ = .;
+ } > QSPI_FLASH
+ __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__;
+
+ __qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */
+ __qspi_region_start_address__ = __qspi_flash_start__;
+ __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__;
+
+ /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */
+ __tz_QSPI_FLASH_N = __qspi_non_retentive_end__;
+
+ /* Support for OctaRAM */
+ .OSPI_DEVICE_0_NO_LOAD (NOLOAD):
+ {
+ . = ALIGN(4);
+ __ospi_device_0_start__ = .;
+ *(.ospi_device_0_no_load*)
+ . = ALIGN(4);
+ __ospi_device_0_end__ = .;
+ } > OSPI_DEVICE_0_RAM
+
+ .OSPI_DEVICE_1_NO_LOAD (NOLOAD):
+ {
+ . = ALIGN(4);
+ __ospi_device_1_start__ = .;
+ *(.ospi_device_1_no_load*)
+ . = ALIGN(4);
+ __ospi_device_1_end__ = .;
+ } > OSPI_DEVICE_1_RAM
+
+ /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */
+ __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0);
+
+ /* OSPI_DEVICE_0 section to be downloaded via debugger */
+ .OSPI_DEVICE_0 :
+ {
+ __ospi_device_0_start__ = .;
+ KEEP(*(.ospi_device_0*))
+ KEEP(*(.code_in_ospi_device_0*))
+ __ospi_device_0_end__ = .;
+ } > OSPI_DEVICE_0
+ __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__;
+
+ /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */
+ __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive));
+ .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__)
+ {
+ __ospi_device_0_non_retentive_start__ = .;
+ KEEP(*(.ospi_device_0_non_retentive*))
+ __ospi_device_0_non_retentive_end__ = .;
+ } > OSPI_DEVICE_0
+ __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__;
+
+ __ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */
+ __ospi_device_0_region_start_address__ = __ospi_device_0_start__;
+ __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__;
+
+ /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */
+ __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__;
+
+ /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */
+ __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1);
+
+ /* OSPI_DEVICE_1 section to be downloaded via debugger */
+ .OSPI_DEVICE_1 :
+ {
+ __ospi_device_1_start__ = .;
+ KEEP(*(.ospi_device_1*))
+ KEEP(*(.code_in_ospi_device_1*))
+ __ospi_device_1_end__ = .;
+ } > OSPI_DEVICE_1
+ __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__;
+
+ /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */
+ __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive));
+ .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__)
+ {
+ __ospi_device_1_non_retentive_start__ = .;
+ KEEP(*(.ospi_device_1_non_retentive*))
+ __ospi_device_1_non_retentive_end__ = .;
+ } > OSPI_DEVICE_1
+ __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__;
+
+ __ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */
+ __ospi_device_1_region_start_address__ = __ospi_device_1_start__;
+ __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__;
+
+ /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */
+ __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__;
+
+ .noinit (NOLOAD):
+ {
+ . = ALIGN(4);
+ __noinit_start = .;
+ KEEP(*(.noinit*))
+ . = ALIGN(8);
+ /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */
+ KEEP(*(.heap.*))
+ __noinit_end = .;
+ } > RAM
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } > RAM
+
+ .heap (NOLOAD):
+ {
+ . = ALIGN(8);
+ __HeapBase = .;
+ /* Place the STD heap here. */
+ KEEP(*(.heap))
+ __HeapLimit = .;
+ } > RAM
+
+ /* Stacks are stored in this section. */
+ .stack_dummy (NOLOAD):
+ {
+ . = ALIGN(8);
+ __StackLimit = .;
+ /* Main stack */
+ KEEP(*(.stack))
+ __StackTop = .;
+ /* Thread stacks */
+ KEEP(*(.stack*))
+ __StackTopAll = .;
+ } > RAM
+
+ PROVIDE(__stack = __StackTopAll);
+
+ /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used
+ at run time for things such as ThreadX memory pool allocations. */
+ __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4);
+
+ /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects.
+ * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary.
+ * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */
+ __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024);
+
+ /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects.
+ * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not
+ * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary.
+ * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */
+ __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192);
+
+ /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects.
+ * The EDMAC is a non-secure bus master and can only access non-secure RAM. */
+ .ns_buffer (NOLOAD):
+ {
+ /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */
+ . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .;
+
+ KEEP(*(.ns_buffer*))
+ } > RAM
+
+ /* Data flash. */
+ .data_flash :
+ {
+ . = ORIGIN(DATA_FLASH);
+ __tz_DATA_FLASH_S = .;
+ __Data_Flash_Start = .;
+ KEEP(*(.data_flash*))
+ __Data_Flash_End = .;
+
+ __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024);
+ } > DATA_FLASH
+
+ /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */
+ __tz_SDRAM_S = ORIGIN(SDRAM);
+
+ /* SDRAM */
+ .sdram (NOLOAD):
+ {
+ __SDRAM_Start = .;
+ KEEP(*(.sdram*))
+ KEEP(*(.frame*))
+ __SDRAM_End = .;
+ } > SDRAM
+
+ /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */
+ __tz_SDRAM_N = __SDRAM_End;
+
+ /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */
+ __tz_ID_CODE_S = ORIGIN(ID_CODE);
+
+ /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool.
+ * Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE
+ * memory region between TrustZone projects. */
+ __tz_ID_CODE_N = __tz_ID_CODE_S;
+
+ .id_code :
+ {
+ __ID_Code_Start = .;
+ KEEP(*(.id_code*))
+ __ID_Code_End = .;
+ } > ID_CODE
+
+ /* Symbol required for RA Configuration tool. */
+ __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS);
+
+ .option_setting_ofs :
+ {
+ __OPTION_SETTING_OFS_Start = .;
+ KEEP(*(.option_setting_ofs0))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start;
+ KEEP(*(.option_setting_ofs2))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start;
+ KEEP(*(.option_setting_dualsel))
+ __OPTION_SETTING_OFS_End = .;
+ } > OPTION_SETTING_OFS = 0xFF
+
+ .option_setting_sas :
+ {
+ __OPTION_SETTING_SAS_Start = .;
+ KEEP(*(.option_setting_sas))
+ __OPTION_SETTING_SAS_End = .;
+ } > OPTION_SETTING_SAS = 0xFF
+
+ /* Symbol required for RA Configuration tool. */
+ __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS);
+
+ .option_setting_ns :
+ {
+ __OPTION_SETTING_NS_Start = .;
+ KEEP(*(.option_setting_ofs1))
+ . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start;
+ KEEP(*(.option_setting_ofs3))
+ . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start;
+ KEEP(*(.option_setting_banksel))
+ . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start;
+ KEEP(*(.option_setting_bps0))
+ . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start;
+ KEEP(*(.option_setting_bps1))
+ . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start;
+ KEEP(*(.option_setting_bps2))
+ . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start;
+ KEEP(*(.option_setting_bps3))
+ . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start;
+ KEEP(*(.option_setting_pbps0))
+ . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start;
+ KEEP(*(.option_setting_pbps1))
+ . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start;
+ KEEP(*(.option_setting_pbps2))
+ . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start;
+ KEEP(*(.option_setting_pbps3))
+ __OPTION_SETTING_NS_End = .;
+ } > OPTION_SETTING = 0xFF
+
+ /* Symbol required for RA Configuration tool. */
+ __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S);
+
+ .option_setting_s :
+ {
+ __OPTION_SETTING_S_Start = .;
+ KEEP(*(.option_setting_ofs1_sec))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_ofs3_sec))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_banksel_sec))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_bps_sec0))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_bps_sec1))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_bps_sec2))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_bps_sec3))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_pbps_sec0))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_pbps_sec1))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_pbps_sec2))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_pbps_sec3))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_ofs1_sel))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_ofs3_sel))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_banksel_sel))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_bps_sel0))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_bps_sel1))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_bps_sel2))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_bps_sel3))
+ __OPTION_SETTING_S_End = .;
+ } > OPTION_SETTING_S = 0xFF
+
+ /* Symbol required for RA Configuration tool. */
+ __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End;
+}
diff --git a/hw/bsp/ra/boards/ra4m3_ek/script/memory_regions.ld b/hw/bsp/ra/boards/ra4m3_ek/script/memory_regions.ld
new file mode 100644
index 0000000000..04d7de497d
--- /dev/null
+++ b/hw/bsp/ra/boards/ra4m3_ek/script/memory_regions.ld
@@ -0,0 +1,22 @@
+
+ /* generated memory regions file - do not edit */
+ RAM_START = 0x20000000;
+ RAM_LENGTH = 0x20000;
+ FLASH_START = 0x00000000;
+ FLASH_LENGTH = 0x100000;
+ DATA_FLASH_START = 0x08000000;
+ DATA_FLASH_LENGTH = 0x2000;
+ OPTION_SETTING_START = 0x0100A100;
+ OPTION_SETTING_LENGTH = 0x100;
+ OPTION_SETTING_S_START = 0x0100A200;
+ OPTION_SETTING_S_LENGTH = 0x100;
+ ID_CODE_START = 0x00000000;
+ ID_CODE_LENGTH = 0x0;
+ SDRAM_START = 0x80010000;
+ SDRAM_LENGTH = 0x0;
+ QSPI_FLASH_START = 0x60000000;
+ QSPI_FLASH_LENGTH = 0x4000000;
+ OSPI_DEVICE_0_START = 0x80020000;
+ OSPI_DEVICE_0_LENGTH = 0x0;
+ OSPI_DEVICE_1_START = 0x80030000;
+ OSPI_DEVICE_1_LENGTH = 0x0;
diff --git a/hw/bsp/ra/boards/ra4m3_ek/smart_configurator/configuration.xml b/hw/bsp/ra/boards/ra4m3_ek/smart_configurator/configuration.xml
new file mode 100644
index 0000000000..1d75f1b72f
--- /dev/null
+++ b/hw/bsp/ra/boards/ra4m3_ek/smart_configurator/configuration.xml
@@ -0,0 +1,432 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Simple application that blinks an LED. No RTOS included.
+ Renesas.RA_baremetal_blinky.5.6.0.pack
+
+
+ Board Support Package Common Files
+ Renesas.RA.5.6.0.pack
+
+
+ I/O Port
+ Renesas.RA.5.6.0.pack
+
+
+ Arm CMSIS Version 6 - Core (M)
+ Arm.CMSIS6.6.1.0+fsp.5.6.0.pack
+
+
+ Board support package for R7FA4M3AF3CFB
+ Renesas.RA_mcu_ra4m3.5.6.0.pack
+
+
+ Board support package for RA4M3
+ Renesas.RA_mcu_ra4m3.5.6.0.pack
+
+
+ Board support package for RA4M3 - FSP Data
+ Renesas.RA_mcu_ra4m3.5.6.0.pack
+
+
+ Board support package for RA4M3 - Events
+ Renesas.RA_mcu_ra4m3.5.6.0.pack
+
+
+ RA4M3-EK Board Support Files
+ Renesas.RA_board_ra4m3_ek.5.6.0.pack
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/hw/bsp/ra/boards/ra6m1_ek/board.h b/hw/bsp/ra/boards/ra6m1_ek/board.h
index f73a08fc0b..ba663d040e 100644
--- a/hw/bsp/ra/boards/ra6m1_ek/board.h
+++ b/hw/bsp/ra/boards/ra6m1_ek/board.h
@@ -31,19 +31,9 @@
extern "C" {
#endif
-#define LED1 BSP_IO_PORT_01_PIN_12
-#define LED_STATE_ON 1
-
-#define SW1 BSP_IO_PORT_04_PIN_15
+#define LED_STATE_ON 1
#define BUTTON_STATE_ACTIVE 0
-static const ioport_pin_cfg_t board_pin_cfg[] = {
- { .pin = LED1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_OUTPUT },
- { .pin = SW1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_INPUT },
- // USB FS
- { .pin = BSP_IO_PORT_04_PIN_07, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS },
-};
-
#ifdef __cplusplus
}
#endif
diff --git a/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_cfg.h
deleted file mode 100644
index 772e5e5b14..0000000000
--- a/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_cfg.h
+++ /dev/null
@@ -1,68 +0,0 @@
-/* generated configuration header file - do not edit */
-#ifndef BSP_CFG_H_
-#define BSP_CFG_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "bsp_clock_cfg.h"
-#include "bsp_mcu_family_cfg.h"
-#include "board_cfg.h"
-
-#define RA_NOT_DEFINED 0
-#ifndef BSP_CFG_RTOS
-#if (RA_NOT_DEFINED) != (2)
-#define BSP_CFG_RTOS (2)
-#elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED)
- #define BSP_CFG_RTOS (1)
-#else
- #define BSP_CFG_RTOS (0)
-#endif
-#endif
-
-#ifndef BSP_CFG_RTC_USED
-#define BSP_CFG_RTC_USED (RA_NOT_DEFINED)
-#endif
-
-#undef RA_NOT_DEFINED
-#if defined(_RA_BOOT_IMAGE)
- #define BSP_CFG_BOOT_IMAGE (1)
-#endif
-
-#define BSP_CFG_MCU_VCC_MV (3300)
-#define BSP_CFG_STACK_MAIN_BYTES (0x1000)
-#define BSP_CFG_HEAP_BYTES (0x1000)
-#define BSP_CFG_PARAM_CHECKING_ENABLE (1)
-#define BSP_CFG_ASSERT (0)
-#define BSP_CFG_ERROR_LOG (0)
-
-#define BSP_CFG_PFS_PROTECT ((1))
-
-#define BSP_CFG_C_RUNTIME_INIT ((1))
-#define BSP_CFG_EARLY_INIT ((0))
-
-#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0))
-
-#ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED
-#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1)
-#endif
-
-#ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE
-#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0)
-#endif
-#ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE
-#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0)
-#endif
-#ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED
-#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1)
-#endif
-#ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS
-#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* BSP_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
deleted file mode 100644
index 40bb3a3bfc..0000000000
--- a/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/* generated configuration header file - do not edit */
-#ifndef BSP_MCU_DEVICE_PN_CFG_H_
-#define BSP_MCU_DEVICE_PN_CFG_H_
-#define BSP_MCU_R7FA6M1AD3CFP
-#define BSP_MCU_FEATURE_SET ('A')
-#define BSP_ROM_SIZE_BYTES (524288)
-#define BSP_RAM_SIZE_BYTES (262144)
-#define BSP_DATA_FLASH_SIZE_BYTES (8192)
-#define BSP_PACKAGE_LQFP
-#define BSP_PACKAGE_PINS (100)
-#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h
deleted file mode 100644
index 5fedd754f5..0000000000
--- a/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h
+++ /dev/null
@@ -1,84 +0,0 @@
-/* generated configuration header file - do not edit */
-#ifndef BSP_MCU_FAMILY_CFG_H_
-#define BSP_MCU_FAMILY_CFG_H_
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "bsp_mcu_device_pn_cfg.h"
-#include "bsp_mcu_device_cfg.h"
-#include "../../../ra/fsp/src/bsp/mcu/ra6m1/bsp_mcu_info.h"
-#include "bsp_clock_cfg.h"
-
-#define BSP_MCU_GROUP_RA6M1 (1)
-#define BSP_LOCO_HZ (32768)
-#define BSP_MOCO_HZ (8000000)
-#define BSP_SUB_CLOCK_HZ (32768)
-#if BSP_CFG_HOCO_FREQUENCY == 0
-#define BSP_HOCO_HZ (16000000)
-#elif BSP_CFG_HOCO_FREQUENCY == 1
- #define BSP_HOCO_HZ (18000000)
-#elif BSP_CFG_HOCO_FREQUENCY == 2
- #define BSP_HOCO_HZ (20000000)
-#else
- #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h"
-#endif
-
-#define BSP_CFG_FLL_ENABLE (0)
-
-#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U)
-#define BSP_VECTOR_TABLE_MAX_ENTRIES (112U)
-
-#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2)
-#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10)
-#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17)
-#define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26)
-#define OFS_SEQ5 (1 << 28) | (1 << 30)
-#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
-#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) | (1 << 8))
-#define BSP_CFG_ROM_REG_MPU_PC0_ENABLE (1)
-#define BSP_CFG_ROM_REG_MPU_PC0_START (0xFFFFFFFC)
-#define BSP_CFG_ROM_REG_MPU_PC0_END (0xFFFFFFFF)
-#define BSP_CFG_ROM_REG_MPU_PC1_ENABLE (1)
-#define BSP_CFG_ROM_REG_MPU_PC1_START (0xFFFFFFFC)
-#define BSP_CFG_ROM_REG_MPU_PC1_END (0xFFFFFFFF)
-#define BSP_CFG_ROM_REG_MPU_REGION0_ENABLE (1)
-#define BSP_CFG_ROM_REG_MPU_REGION0_START (0x00FFFFFC)
-#define BSP_CFG_ROM_REG_MPU_REGION0_END (0x00FFFFFF)
-#define BSP_CFG_ROM_REG_MPU_REGION1_ENABLE (1)
-#define BSP_CFG_ROM_REG_MPU_REGION1_START (0x200FFFFC)
-#define BSP_CFG_ROM_REG_MPU_REGION1_END (0x200FFFFF)
-#define BSP_CFG_ROM_REG_MPU_REGION2_ENABLE (1)
-#define BSP_CFG_ROM_REG_MPU_REGION2_START (0x407FFFFC)
-#define BSP_CFG_ROM_REG_MPU_REGION2_END (0x407FFFFF)
-#define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1)
-#define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC)
-#define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF)
-#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT
-#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9)
-#endif
-/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */
-#define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector)
-
-/*
- ID Code
- Note: To permanently lock and disable the debug interface define the BSP_ID_CODE_PERMANENTLY_LOCKED in the compiler settings.
- WARNING: This will disable debug access to the part and cannot be reversed by a debug probe.
- */
-#if defined(BSP_ID_CODE_PERMANENTLY_LOCKED)
- #define BSP_CFG_ID_CODE_LONG_1 (0x00000000)
- #define BSP_CFG_ID_CODE_LONG_2 (0x00000000)
- #define BSP_CFG_ID_CODE_LONG_3 (0x00000000)
- #define BSP_CFG_ID_CODE_LONG_4 (0x00000000)
-#else
- /* ID CODE: FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF */
- #define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF)
- #define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF)
- #define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF)
- #define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF)
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-#endif /* BSP_MCU_FAMILY_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h
new file mode 100644
index 0000000000..90afbdef3d
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h
@@ -0,0 +1,62 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_CFG_H_
+#define BSP_CFG_H_
+#ifdef __cplusplus
+ extern "C" {
+ #endif
+
+ #include "bsp_clock_cfg.h"
+ #include "bsp_mcu_family_cfg.h"
+ #include "board_cfg.h"
+ #define RA_NOT_DEFINED 0
+ #ifndef BSP_CFG_RTOS
+ #if (RA_NOT_DEFINED) != (RA_NOT_DEFINED)
+ #define BSP_CFG_RTOS (2)
+ #elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED)
+ #define BSP_CFG_RTOS (1)
+ #else
+ #define BSP_CFG_RTOS (0)
+ #endif
+ #endif
+ #ifndef BSP_CFG_RTC_USED
+ #define BSP_CFG_RTC_USED (RA_NOT_DEFINED)
+ #endif
+ #undef RA_NOT_DEFINED
+ #if defined(_RA_BOOT_IMAGE)
+ #define BSP_CFG_BOOT_IMAGE (1)
+ #endif
+ #define BSP_CFG_MCU_VCC_MV (3300)
+ #define BSP_CFG_STACK_MAIN_BYTES (0x1000)
+ #define BSP_CFG_HEAP_BYTES (0x1000)
+ #define BSP_CFG_PARAM_CHECKING_ENABLE (0)
+ #define BSP_CFG_ASSERT (0)
+ #define BSP_CFG_ERROR_LOG (0)
+
+ #define BSP_CFG_PFS_PROTECT ((1))
+
+ #define BSP_CFG_C_RUNTIME_INIT ((1))
+ #define BSP_CFG_EARLY_INIT ((0))
+
+ #define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0))
+
+ #ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED
+ #define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1)
+ #endif
+
+ #ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE
+ #define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0)
+ #endif
+ #ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE
+ #define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0)
+ #endif
+ #ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED
+ #define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1)
+ #endif
+ #ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS
+ #define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
+ #endif
+
+ #ifdef __cplusplus
+ }
+ #endif
+#endif /* BSP_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_mcu_device_cfg.h b/hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h
similarity index 100%
rename from hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_mcu_device_cfg.h
rename to hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h
diff --git a/hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
new file mode 100644
index 0000000000..5e78414429
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
@@ -0,0 +1,11 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_MCU_DEVICE_PN_CFG_H_
+#define BSP_MCU_DEVICE_PN_CFG_H_
+#define BSP_MCU_R7FA6M1AD3CFP
+ #define BSP_MCU_FEATURE_SET ('A')
+ #define BSP_ROM_SIZE_BYTES (524288)
+ #define BSP_RAM_SIZE_BYTES (262144)
+ #define BSP_DATA_FLASH_SIZE_BYTES (8192)
+ #define BSP_PACKAGE_LQFP
+ #define BSP_PACKAGE_PINS (100)
+#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h
new file mode 100644
index 0000000000..16349b5ff7
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h
@@ -0,0 +1,84 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_MCU_FAMILY_CFG_H_
+#define BSP_MCU_FAMILY_CFG_H_
+#ifdef __cplusplus
+ extern "C" {
+ #endif
+
+ #include "bsp_mcu_device_pn_cfg.h"
+ #include "bsp_mcu_device_cfg.h"
+ #include "../../../ra/fsp/src/bsp/mcu/ra6m1/bsp_mcu_info.h"
+ #include "bsp_clock_cfg.h"
+ #define BSP_MCU_GROUP_RA6M1 (1)
+ #define BSP_LOCO_HZ (32768)
+ #define BSP_MOCO_HZ (8000000)
+ #define BSP_SUB_CLOCK_HZ (32768)
+ #if BSP_CFG_HOCO_FREQUENCY == 0
+ #define BSP_HOCO_HZ (16000000)
+ #elif BSP_CFG_HOCO_FREQUENCY == 1
+ #define BSP_HOCO_HZ (18000000)
+ #elif BSP_CFG_HOCO_FREQUENCY == 2
+ #define BSP_HOCO_HZ (20000000)
+ #else
+ #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h"
+ #endif
+
+ #define BSP_CFG_FLL_ENABLE (0)
+
+ #define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U)
+ #define BSP_VECTOR_TABLE_MAX_ENTRIES (112U)
+ #define BSP_CFG_INLINE_IRQ_FUNCTIONS (1)
+
+ #define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2)
+ #define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10)
+ #define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17)
+ #define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26)
+ #define OFS_SEQ5 (1 << 28) | (1 << 30)
+ #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
+ #define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) | (1 << 8))
+ #define BSP_CFG_ROM_REG_MPU_PC0_ENABLE (1)
+ #define BSP_CFG_ROM_REG_MPU_PC0_START (0xFFFFFFFC)
+ #define BSP_CFG_ROM_REG_MPU_PC0_END (0xFFFFFFFF)
+ #define BSP_CFG_ROM_REG_MPU_PC1_ENABLE (1)
+ #define BSP_CFG_ROM_REG_MPU_PC1_START (0xFFFFFFFC)
+ #define BSP_CFG_ROM_REG_MPU_PC1_END (0xFFFFFFFF)
+ #define BSP_CFG_ROM_REG_MPU_REGION0_ENABLE (1)
+ #define BSP_CFG_ROM_REG_MPU_REGION0_START (0x00FFFFFC)
+ #define BSP_CFG_ROM_REG_MPU_REGION0_END (0x00FFFFFF)
+ #define BSP_CFG_ROM_REG_MPU_REGION1_ENABLE (1)
+ #define BSP_CFG_ROM_REG_MPU_REGION1_START (0x200FFFFC)
+ #define BSP_CFG_ROM_REG_MPU_REGION1_END (0x200FFFFF)
+ #define BSP_CFG_ROM_REG_MPU_REGION2_ENABLE (1)
+ #define BSP_CFG_ROM_REG_MPU_REGION2_START (0x407FFFFC)
+ #define BSP_CFG_ROM_REG_MPU_REGION2_END (0x407FFFFF)
+ #define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1)
+ #define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC)
+ #define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF)
+ #ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT
+ #define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9)
+ #endif
+ /* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */
+ #define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector)
+
+ /*
+ ID Code
+ Note: To lock and disable the debug interface define BSP_ID_CODE_LOCKED in compiler settings.
+ WARNING: This will disable debug access to the part. However, ALeRASE command will be accepted, which will clear (reset) the ID code. After clearing ID code, debug access will be enabled.
+ */
+ #if defined(BSP_ID_CODE_LOCKED)
+ #define BSP_CFG_ID_CODE_LONG_1 (0x00000000)
+ #define BSP_CFG_ID_CODE_LONG_2 (0x00000000)
+ #define BSP_CFG_ID_CODE_LONG_3 (0x00000000)
+ #define BSP_CFG_ID_CODE_LONG_4 (0x00000000)
+ #else
+ /* ID CODE: FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF */
+ #define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF)
+ #define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF)
+ #define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF)
+ #define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF)
+ #endif
+
+ #ifdef __cplusplus
+ }
+ #endif
+#endif /* BSP_MCU_FAMILY_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h b/hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h
new file mode 100644
index 0000000000..8ba9aafba9
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h
@@ -0,0 +1,17 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_PIN_CFG_H_
+#define BSP_PIN_CFG_H_
+#include "r_ioport.h"
+
+/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+#define LED1 (BSP_IO_PORT_01_PIN_12)
+#define SW1 (BSP_IO_PORT_04_PIN_15)
+extern const ioport_cfg_t g_bsp_pin_cfg; /* RA6M1-EK.pincfg */
+
+void BSP_PinConfigSecurityInit();
+
+/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+#endif /* BSP_PIN_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h b/hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h
new file mode 100644
index 0000000000..d2688bf5ba
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h
@@ -0,0 +1,13 @@
+/* generated configuration header file - do not edit */
+#ifndef R_IOPORT_CFG_H_
+#define R_IOPORT_CFG_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* R_IOPORT_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp_clock_cfg.h b/hw/bsp/ra/boards/ra6m1_ek/ra_gen/bsp_clock_cfg.h
similarity index 100%
rename from hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp_clock_cfg.h
rename to hw/bsp/ra/boards/ra6m1_ek/ra_gen/bsp_clock_cfg.h
diff --git a/hw/bsp/ra/boards/ra6m1_ek/ra_gen/common_data.c b/hw/bsp/ra/boards/ra6m1_ek/ra_gen/common_data.c
new file mode 100644
index 0000000000..50036c0adc
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m1_ek/ra_gen/common_data.c
@@ -0,0 +1,11 @@
+/* generated common source file - do not edit */
+#include "common_data.h"
+ioport_instance_ctrl_t g_ioport_ctrl;
+const ioport_instance_t g_ioport =
+ {
+ .p_api = &g_ioport_on_ioport,
+ .p_ctrl = &g_ioport_ctrl,
+ .p_cfg = &g_bsp_pin_cfg,
+ };
+void g_common_init(void) {
+}
diff --git a/hw/bsp/ra/boards/ra6m1_ek/ra_gen/common_data.h b/hw/bsp/ra/boards/ra6m1_ek/ra_gen/common_data.h
new file mode 100644
index 0000000000..6a08cbee09
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m1_ek/ra_gen/common_data.h
@@ -0,0 +1,20 @@
+/* generated common header file - do not edit */
+#ifndef COMMON_DATA_H_
+#define COMMON_DATA_H_
+#include
+#include "bsp_api.h"
+#include "r_ioport.h"
+#include "bsp_pin_cfg.h"
+FSP_HEADER
+#define IOPORT_CFG_NAME g_bsp_pin_cfg
+#define IOPORT_CFG_OPEN R_IOPORT_Open
+#define IOPORT_CFG_CTRL g_ioport_ctrl
+
+/* IOPORT Instance */
+extern const ioport_instance_t g_ioport;
+
+/* IOPORT control structure. */
+extern ioport_instance_ctrl_t g_ioport_ctrl;
+void g_common_init(void);
+FSP_FOOTER
+#endif /* COMMON_DATA_H_ */
diff --git a/hw/bsp/ra/boards/ra6m1_ek/ra_gen/pin_data.c b/hw/bsp/ra/boards/ra6m1_ek/ra_gen/pin_data.c
new file mode 100644
index 0000000000..80774b0a55
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m1_ek/ra_gen/pin_data.c
@@ -0,0 +1,115 @@
+/* generated pin source file - do not edit */
+#include "bsp_api.h"
+#include "r_ioport.h"
+
+
+const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = {
+ {
+ .pin = BSP_IO_PORT_00_PIN_04,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE)
+ },
+ {
+ .pin = BSP_IO_PORT_01_PIN_00,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
+ },
+ {
+ .pin = BSP_IO_PORT_01_PIN_01,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
+ },
+ {
+ .pin = BSP_IO_PORT_01_PIN_02,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
+ },
+ {
+ .pin = BSP_IO_PORT_01_PIN_03,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
+ },
+ {
+ .pin = BSP_IO_PORT_01_PIN_04,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI0_2_4_6_8)
+ },
+ {
+ .pin = BSP_IO_PORT_01_PIN_05,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI0_2_4_6_8)
+ },
+ {
+ .pin = BSP_IO_PORT_01_PIN_06,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+ },
+ {
+ .pin = BSP_IO_PORT_01_PIN_07,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+ },
+ {
+ .pin = BSP_IO_PORT_01_PIN_08,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG)
+ },
+ {
+ .pin = BSP_IO_PORT_01_PIN_12,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+ },
+ {
+ .pin = BSP_IO_PORT_02_PIN_01,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT)
+ },
+ {
+ .pin = BSP_IO_PORT_02_PIN_05,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_CTSU)
+ },
+ {
+ .pin = BSP_IO_PORT_02_PIN_07,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_CTSU)
+ },
+ {
+ .pin = BSP_IO_PORT_03_PIN_00,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG)
+ },
+ {
+ .pin = BSP_IO_PORT_04_PIN_07,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)
+ },
+ {
+ .pin = BSP_IO_PORT_04_PIN_15,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT | (uint32_t) IOPORT_CFG_PULLUP_ENABLE)
+ },
+};
+
+const ioport_cfg_t g_bsp_pin_cfg = {
+ .number_of_pins = sizeof(g_bsp_pin_cfg_data)/sizeof(ioport_pin_cfg_t),
+ .p_pin_cfg_data = &g_bsp_pin_cfg_data[0],
+};
+
+#if BSP_TZ_SECURE_BUILD
+
+void R_BSP_PinCfgSecurityInit(void);
+
+/* Initialize SAR registers for secure pins. */
+void R_BSP_PinCfgSecurityInit(void)
+{
+ #if (2U == BSP_FEATURE_IOPORT_VERSION)
+ uint32_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR];
+ #else
+ uint16_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR];
+ #endif
+ memset(pmsar, 0xFF, BSP_FEATURE_BSP_NUM_PMSAR * sizeof(R_PMISC->PMSAR[0]));
+
+
+ for(uint32_t i = 0; i < g_bsp_pin_cfg.number_of_pins; i++)
+ {
+ uint32_t port_pin = g_bsp_pin_cfg.p_pin_cfg_data[i].pin;
+ uint32_t port = port_pin >> 8U;
+ uint32_t pin = port_pin & 0xFFU;
+ pmsar[port] &= (uint16_t) ~(1U << pin);
+ }
+
+ for(uint32_t i = 0; i < BSP_FEATURE_BSP_NUM_PMSAR; i++)
+ {
+ #if (2U == BSP_FEATURE_IOPORT_VERSION)
+ R_PMISC->PMSAR[i].PMSAR = (uint16_t) pmsar[i];
+ #else
+ R_PMISC->PMSAR[i].PMSAR = pmsar[i];
+ #endif
+ }
+
+}
+#endif
diff --git a/hw/bsp/ra/boards/ra6m1_ek/script/fsp.ld b/hw/bsp/ra/boards/ra6m1_ek/script/fsp.ld
new file mode 100644
index 0000000000..605eef7d2c
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m1_ek/script/fsp.ld
@@ -0,0 +1,769 @@
+/*
+ Linker File for Renesas FSP
+*/
+
+INCLUDE memory_regions.ld
+
+/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/
+/*
+ XIP_SECONDARY_SLOT_IMAGE = 1;
+*/
+
+QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH);
+OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH);
+OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH);
+
+/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */
+__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0);
+
+ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0;
+ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0;
+DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0;
+DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0;
+RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0;
+RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0;
+RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH;
+RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH;
+
+OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80;
+
+/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings.
+ * Bootloader images do not configure option settings because they are owned by the bootloader.
+ * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */
+__bl_FSP_BOOTABLE_IMAGE = 1;
+__bln_FSP_BOOTABLE_IMAGE = 1;
+PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE);
+USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE);
+
+__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+ FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH :
+ (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH :
+ FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH;
+__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+ FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH;
+__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH;
+__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+ FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH;
+__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH;
+__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+ FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
+ __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH;
+__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+ FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
+ __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH;
+__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+ FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH :
+ RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH;
+__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+ FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH :
+ __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH;
+__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+ FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
+ __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2;
+__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START);
+__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+ FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
+ FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2;
+
+XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0;
+FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START :
+ XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START :
+ FLASH_IMAGE_START;
+LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH :
+ DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH :
+ FLASH_LENGTH;
+OPTION_SETTING_SAS_SIZE = 0x34;
+OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 :
+ OPTION_SETTING_LENGTH == 0 ? 0 :
+ OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE;
+
+/* Define memory regions. */
+MEMORY
+{
+ ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH
+ DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH
+ FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH
+ RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH
+ DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH
+ QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH
+ OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH
+ OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH
+ OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH
+ OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH
+ SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH
+ OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH
+ OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18
+ OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH
+ OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH
+ ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH
+}
+
+/* Library configurations */
+GROUP(libgcc.a libc.a libm.a)
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be DEFINED in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __copy_table_start__
+ * __copy_table_end__
+ * __zero_table_start__
+ * __zero_table_end__
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ * __Vectors_End
+ * __Vectors_Size
+ * __qspi_flash_start__
+ * __qspi_flash_end__
+ * __qspi_flash_code_size__
+ * __qspi_region_max_size__
+ * __qspi_region_start_address__
+ * __qspi_region_end_address__
+ * __ospi_device_0_start__
+ * __ospi_device_0_end__
+ * __ospi_device_0_code_size__
+ * __ospi_device_0_region_max_size__
+ * __ospi_device_0_region_start_address__
+ * __ospi_device_0_region_end_address__
+ * __ospi_device_1_start__
+ * __ospi_device_1_end__
+ * __ospi_device_1_code_size__
+ * __ospi_device_1_region_max_size__
+ * __ospi_device_1_region_start_address__
+ * __ospi_device_1_region_end_address__
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ __tz_FLASH_S = ABSOLUTE(FLASH_START);
+ __ROM_Start = .;
+
+ /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much
+ * space because ROM registers are at address 0x400 and there is very little space
+ * in between. */
+ KEEP(*(.fixed_vectors*))
+ KEEP(*(.application_vectors*))
+ __Vectors_End = .;
+
+ /* Some devices have a gap of code flash between the vector table and ROM Registers.
+ * The flash gap section allows applications to place code and data in this section. */
+ *(.flash_gap*)
+
+ /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */
+ . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400;
+ KEEP(*(.rom_registers*))
+
+ /* Reserving 0x100 bytes of space for ROM registers. */
+ . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x500;
+
+ /* Allocate flash write-boundary-aligned
+ * space for sce9 wrapped public keys for mcuboot if the module is used.
+ */
+ KEEP(*(.mcuboot_sce9_key*))
+
+ *(.text*)
+
+ KEEP(*(.version))
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+ __usb_dev_descriptor_start_fs = .;
+ KEEP(*(.usb_device_desc_fs*))
+ __usb_cfg_descriptor_start_fs = .;
+ KEEP(*(.usb_config_desc_fs*))
+ __usb_interface_descriptor_start_fs = .;
+ KEEP(*(.usb_interface_desc_fs*))
+ __usb_descriptor_end_fs = .;
+ __usb_dev_descriptor_start_hs = .;
+ KEEP(*(.usb_device_desc_hs*))
+ __usb_cfg_descriptor_start_hs = .;
+ KEEP(*(.usb_config_desc_hs*))
+ __usb_interface_descriptor_start_hs = .;
+ KEEP(*(.usb_interface_desc_hs*))
+ __usb_descriptor_end_hs = .;
+
+ KEEP(*(.eh_frame*))
+
+ __ROM_End = .;
+ } > FLASH = 0xFF
+
+ __Vectors_Size = __Vectors_End - __Vectors;
+
+ . = .;
+ __itcm_data_pre_location = .;
+
+ /* Initialized ITCM data. */
+ /* Aligned to FCACHE2 for RA8. */
+ .itcm_data : ALIGN(16)
+ {
+ /* Start of ITCM Secure Trustzone region. */
+ __tz_ITCM_S = ABSOLUTE(ITCM_START);
+
+ /* All ITCM data start */
+ __itcm_data_start = .;
+
+ KEEP(*(.itcm_data*))
+
+ /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */
+ . = ALIGN(8);
+
+ /* All ITCM data end */
+ __itcm_data_end = .;
+
+ /*
+ * Start of the ITCM Non-Secure Trustzone region.
+ * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects.
+ */
+ __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192);
+ } > ITCM AT > FLASH = 0x00
+
+ /* Addresses exported for ITCM initialization. */
+ __itcm_data_init_start = LOADADDR(.itcm_data);
+ __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data);
+
+ ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.")
+ ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.")
+ ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.")
+ ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.")
+
+ /* Restore location counter. */
+ /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */
+ /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */
+ . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location;
+
+ __exidx_start = .;
+ /DISCARD/ :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ }
+ __exidx_end = .;
+
+ /* To copy multiple ROM to RAM sections,
+ * uncomment .copy.table section and,
+ * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+ /*
+ .copy.table :
+ {
+ . = ALIGN(4);
+ __copy_table_start__ = .;
+ LONG (__etext)
+ LONG (__data_start__)
+ LONG (__data_end__ - __data_start__)
+ LONG (__etext2)
+ LONG (__data2_start__)
+ LONG (__data2_end__ - __data2_start__)
+ __copy_table_end__ = .;
+ } > FLASH
+ */
+
+ /* To clear multiple BSS sections,
+ * uncomment .zero.table section and,
+ * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+ /*
+ .zero.table :
+ {
+ . = ALIGN(4);
+ __zero_table_start__ = .;
+ LONG (__bss_start__)
+ LONG (__bss_end__ - __bss_start__)
+ LONG (__bss2_start__)
+ LONG (__bss2_end__ - __bss2_start__)
+ __zero_table_end__ = .;
+ } > FLASH
+ */
+
+ __etext = .;
+
+ __tz_RAM_S = ORIGIN(RAM);
+
+ /* If DTC is used, put the DTC vector table at the start of SRAM.
+ This avoids memory holes due to 1K alignment required by it. */
+ .fsp_dtc_vector_table (NOLOAD) :
+ {
+ . = ORIGIN(RAM);
+ *(.fsp_dtc_vector_table)
+ } > RAM
+
+ /* Initialized data section. */
+ .data :
+ {
+ __data_start__ = .;
+ . = ALIGN(4);
+
+ __Code_In_RAM_Start = .;
+
+ KEEP(*(.code_in_ram*))
+ __Code_In_RAM_End = .;
+
+ *(vtable)
+ /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */
+ *(.data.*)
+ *(.data)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+
+ . = ALIGN(4);
+
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM AT > FLASH
+
+ . = .;
+ __dtcm_data_pre_location = LOADADDR(.data) + SIZEOF(.data);
+
+ /* Initialized DTCM data. */
+ /* Aligned to FCACHE2 for RA8. */
+ .dtcm_data : ALIGN(16)
+ {
+ /* Start of DTCM Secure Trustzone region. */
+ __tz_DTCM_S = ABSOLUTE(DTCM_START);
+
+ /* Initialized DTCM data start */
+ __dtcm_data_start = .;
+
+ KEEP(*(.dtcm_data*))
+
+ /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */
+ . = ALIGN(8);
+
+ /* Initialized DTCM data end */
+ __dtcm_data_end = .;
+ } > DTCM AT > FLASH = 0x00
+
+ . = __dtcm_data_end;
+ /* Uninitialized DTCM data. */
+ /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */
+ .dtcm_bss ALIGN(8) (NOLOAD) :
+ {
+ /* Uninitialized DTCM data start */
+ __dtcm_bss_start = .;
+
+ KEEP(*(.dtcm_bss*))
+
+ /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */
+ . = ALIGN(8);
+
+ /* Uninitialized DTCM data end */
+ __dtcm_bss_end = .;
+
+ /*
+ * Start of the DTCM Non-Secure Trustzone region.
+ * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects.
+ */
+ __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192);
+ } > DTCM
+
+ /* Addresses exported for DTCM initialization. */
+ __dtcm_data_init_start = LOADADDR(.dtcm_data);
+ __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data);
+
+ ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.")
+ ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.")
+ ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).")
+ ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.")
+ ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.")
+ ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.")
+ ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.")
+ ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.")
+
+ /* Restore location counter. */
+ /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */
+ /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */
+ . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location;
+
+ /* TrustZone Secure Gateway Stubs Section */
+
+ /* Store location counter for SPI non-retentive sections. */
+ sgstubs_pre_location = .;
+
+ /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */
+ SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024);
+ .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024)
+ {
+ __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024);
+ _start_sg = .;
+ *(.gnu.sgstubs*)
+ . = ALIGN(32);
+ _end_sg = .;
+ } > FLASH
+
+ __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768);
+ FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N;
+
+ /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */
+ __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH);
+
+ /* QSPI_FLASH section to be downloaded via debugger */
+ .qspi_flash :
+ {
+ __qspi_flash_start__ = .;
+ KEEP(*(.qspi_flash*))
+ KEEP(*(.code_in_qspi*))
+ __qspi_flash_end__ = .;
+ } > QSPI_FLASH
+ __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__;
+
+ /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */
+ __qspi_flash_code_addr__ = sgstubs_pre_location;
+ .qspi_non_retentive : AT(__qspi_flash_code_addr__)
+ {
+ __qspi_non_retentive_start__ = .;
+ KEEP(*(.qspi_non_retentive*))
+ __qspi_non_retentive_end__ = .;
+ } > QSPI_FLASH
+ __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__;
+
+ __qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */
+ __qspi_region_start_address__ = __qspi_flash_start__;
+ __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__;
+
+ /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */
+ __tz_QSPI_FLASH_N = __qspi_non_retentive_end__;
+
+ /* Support for OctaRAM */
+ .OSPI_DEVICE_0_NO_LOAD (NOLOAD):
+ {
+ . = ALIGN(4);
+ __ospi_device_0_start__ = .;
+ *(.ospi_device_0_no_load*)
+ . = ALIGN(4);
+ __ospi_device_0_end__ = .;
+ } > OSPI_DEVICE_0_RAM
+
+ .OSPI_DEVICE_1_NO_LOAD (NOLOAD):
+ {
+ . = ALIGN(4);
+ __ospi_device_1_start__ = .;
+ *(.ospi_device_1_no_load*)
+ . = ALIGN(4);
+ __ospi_device_1_end__ = .;
+ } > OSPI_DEVICE_1_RAM
+
+ /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */
+ __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0);
+
+ /* OSPI_DEVICE_0 section to be downloaded via debugger */
+ .OSPI_DEVICE_0 :
+ {
+ __ospi_device_0_start__ = .;
+ KEEP(*(.ospi_device_0*))
+ KEEP(*(.code_in_ospi_device_0*))
+ __ospi_device_0_end__ = .;
+ } > OSPI_DEVICE_0
+ __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__;
+
+ /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */
+ __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive));
+ .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__)
+ {
+ __ospi_device_0_non_retentive_start__ = .;
+ KEEP(*(.ospi_device_0_non_retentive*))
+ __ospi_device_0_non_retentive_end__ = .;
+ } > OSPI_DEVICE_0
+ __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__;
+
+ __ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */
+ __ospi_device_0_region_start_address__ = __ospi_device_0_start__;
+ __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__;
+
+ /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */
+ __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__;
+
+ /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */
+ __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1);
+
+ /* OSPI_DEVICE_1 section to be downloaded via debugger */
+ .OSPI_DEVICE_1 :
+ {
+ __ospi_device_1_start__ = .;
+ KEEP(*(.ospi_device_1*))
+ KEEP(*(.code_in_ospi_device_1*))
+ __ospi_device_1_end__ = .;
+ } > OSPI_DEVICE_1
+ __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__;
+
+ /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */
+ __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive));
+ .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__)
+ {
+ __ospi_device_1_non_retentive_start__ = .;
+ KEEP(*(.ospi_device_1_non_retentive*))
+ __ospi_device_1_non_retentive_end__ = .;
+ } > OSPI_DEVICE_1
+ __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__;
+
+ __ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */
+ __ospi_device_1_region_start_address__ = __ospi_device_1_start__;
+ __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__;
+
+ /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */
+ __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__;
+
+ .noinit (NOLOAD):
+ {
+ . = ALIGN(4);
+ __noinit_start = .;
+ KEEP(*(.noinit*))
+ . = ALIGN(8);
+ /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */
+ KEEP(*(.heap.*))
+ __noinit_end = .;
+ } > RAM
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } > RAM
+
+ .heap (NOLOAD):
+ {
+ . = ALIGN(8);
+ __HeapBase = .;
+ /* Place the STD heap here. */
+ KEEP(*(.heap))
+ __HeapLimit = .;
+ } > RAM
+
+ /* Stacks are stored in this section. */
+ .stack_dummy (NOLOAD):
+ {
+ . = ALIGN(8);
+ __StackLimit = .;
+ /* Main stack */
+ KEEP(*(.stack))
+ __StackTop = .;
+ /* Thread stacks */
+ KEEP(*(.stack*))
+ __StackTopAll = .;
+ } > RAM
+
+ PROVIDE(__stack = __StackTopAll);
+
+ /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used
+ at run time for things such as ThreadX memory pool allocations. */
+ __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4);
+
+ /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects.
+ * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary.
+ * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */
+ __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024);
+
+ /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects.
+ * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not
+ * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary.
+ * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */
+ __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192);
+
+ /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects.
+ * The EDMAC is a non-secure bus master and can only access non-secure RAM. */
+ .ns_buffer (NOLOAD):
+ {
+ /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */
+ . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .;
+
+ KEEP(*(.ns_buffer*))
+ } > RAM
+
+ /* Data flash. */
+ .data_flash :
+ {
+ . = ORIGIN(DATA_FLASH);
+ __tz_DATA_FLASH_S = .;
+ __Data_Flash_Start = .;
+ KEEP(*(.data_flash*))
+ __Data_Flash_End = .;
+
+ __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024);
+ } > DATA_FLASH
+
+ /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */
+ __tz_SDRAM_S = ORIGIN(SDRAM);
+
+ /* SDRAM */
+ .sdram (NOLOAD):
+ {
+ __SDRAM_Start = .;
+ KEEP(*(.sdram*))
+ KEEP(*(.frame*))
+ __SDRAM_End = .;
+ } > SDRAM
+
+ /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */
+ __tz_SDRAM_N = __SDRAM_End;
+
+ /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */
+ __tz_ID_CODE_S = ORIGIN(ID_CODE);
+
+ /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool.
+ * Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE
+ * memory region between TrustZone projects. */
+ __tz_ID_CODE_N = __tz_ID_CODE_S;
+
+ .id_code :
+ {
+ __ID_Code_Start = .;
+ KEEP(*(.id_code*))
+ __ID_Code_End = .;
+ } > ID_CODE
+
+ /* Symbol required for RA Configuration tool. */
+ __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS);
+
+ .option_setting_ofs :
+ {
+ __OPTION_SETTING_OFS_Start = .;
+ KEEP(*(.option_setting_ofs0))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start;
+ KEEP(*(.option_setting_ofs2))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start;
+ KEEP(*(.option_setting_dualsel))
+ __OPTION_SETTING_OFS_End = .;
+ } > OPTION_SETTING_OFS = 0xFF
+
+ .option_setting_sas :
+ {
+ __OPTION_SETTING_SAS_Start = .;
+ KEEP(*(.option_setting_sas))
+ __OPTION_SETTING_SAS_End = .;
+ } > OPTION_SETTING_SAS = 0xFF
+
+ /* Symbol required for RA Configuration tool. */
+ __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS);
+
+ .option_setting_ns :
+ {
+ __OPTION_SETTING_NS_Start = .;
+ KEEP(*(.option_setting_ofs1))
+ . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start;
+ KEEP(*(.option_setting_ofs3))
+ . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start;
+ KEEP(*(.option_setting_banksel))
+ . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start;
+ KEEP(*(.option_setting_bps0))
+ . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start;
+ KEEP(*(.option_setting_bps1))
+ . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start;
+ KEEP(*(.option_setting_bps2))
+ . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start;
+ KEEP(*(.option_setting_bps3))
+ . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start;
+ KEEP(*(.option_setting_pbps0))
+ . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start;
+ KEEP(*(.option_setting_pbps1))
+ . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start;
+ KEEP(*(.option_setting_pbps2))
+ . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start;
+ KEEP(*(.option_setting_pbps3))
+ __OPTION_SETTING_NS_End = .;
+ } > OPTION_SETTING = 0xFF
+
+ /* Symbol required for RA Configuration tool. */
+ __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S);
+
+ .option_setting_s :
+ {
+ __OPTION_SETTING_S_Start = .;
+ KEEP(*(.option_setting_ofs1_sec))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_ofs3_sec))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_banksel_sec))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_bps_sec0))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_bps_sec1))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_bps_sec2))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_bps_sec3))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_pbps_sec0))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_pbps_sec1))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_pbps_sec2))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_pbps_sec3))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_ofs1_sel))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_ofs3_sel))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_banksel_sel))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_bps_sel0))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_bps_sel1))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_bps_sel2))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_bps_sel3))
+ __OPTION_SETTING_S_End = .;
+ } > OPTION_SETTING_S = 0xFF
+
+ /* Symbol required for RA Configuration tool. */
+ __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End;
+}
diff --git a/hw/bsp/ra/boards/ra6m1_ek/script/memory_regions.ld b/hw/bsp/ra/boards/ra6m1_ek/script/memory_regions.ld
new file mode 100644
index 0000000000..9d973c7370
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m1_ek/script/memory_regions.ld
@@ -0,0 +1,22 @@
+
+ /* generated memory regions file - do not edit */
+ RAM_START = 0x1FFE0000;
+ RAM_LENGTH = 0x40000;
+ FLASH_START = 0x00000000;
+ FLASH_LENGTH = 0x80000;
+ DATA_FLASH_START = 0x40100000;
+ DATA_FLASH_LENGTH = 0x2000;
+ OPTION_SETTING_START = 0x00000000;
+ OPTION_SETTING_LENGTH = 0x0;
+ OPTION_SETTING_S_START = 0x80000000;
+ OPTION_SETTING_S_LENGTH = 0x0;
+ ID_CODE_START = 0x0100A150;
+ ID_CODE_LENGTH = 0x10;
+ SDRAM_START = 0x80010000;
+ SDRAM_LENGTH = 0x0;
+ QSPI_FLASH_START = 0x60000000;
+ QSPI_FLASH_LENGTH = 0x4000000;
+ OSPI_DEVICE_0_START = 0x80020000;
+ OSPI_DEVICE_0_LENGTH = 0x0;
+ OSPI_DEVICE_1_START = 0x80030000;
+ OSPI_DEVICE_1_LENGTH = 0x0;
diff --git a/hw/bsp/ra/boards/ra6m1_ek/smart_configurator/configuration.xml b/hw/bsp/ra/boards/ra6m1_ek/smart_configurator/configuration.xml
new file mode 100644
index 0000000000..4c5d77ed0d
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m1_ek/smart_configurator/configuration.xml
@@ -0,0 +1,270 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Simple application that blinks an LED. No RTOS included.
+ Renesas.RA_baremetal_blinky.5.6.0.pack
+
+
+ Board Support Package Common Files
+ Renesas.RA.5.6.0.pack
+
+
+ I/O Port
+ Renesas.RA.5.6.0.pack
+
+
+ Arm CMSIS Version 6 - Core (M)
+ Arm.CMSIS6.6.1.0+fsp.5.6.0.pack
+
+
+ RA6M1-EK Board Support Files
+ Renesas.RA_board_ra6m1_ek.5.6.0.pack
+
+
+ Board support package for R7FA6M1AD3CFP
+ Renesas.RA_mcu_ra6m1.5.6.0.pack
+
+
+ Board support package for RA6M1
+ Renesas.RA_mcu_ra6m1.5.6.0.pack
+
+
+ Board support package for RA6M1 - FSP Data
+ Renesas.RA_mcu_ra6m1.5.6.0.pack
+
+
+ Board support package for RA6M1 - Events
+ Renesas.RA_mcu_ra6m1.5.6.0.pack
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/hw/bsp/ra/boards/ra6m5_ek/board.cmake b/hw/bsp/ra/boards/ra6m5_ek/board.cmake
index c91d48a326..568d5d78f4 100644
--- a/hw/bsp/ra/boards/ra6m5_ek/board.cmake
+++ b/hw/bsp/ra/boards/ra6m5_ek/board.cmake
@@ -2,21 +2,15 @@ set(CMAKE_SYSTEM_PROCESSOR cortex-m33 CACHE INTERNAL "System Processor")
set(MCU_VARIANT ra6m5)
set(JLINK_DEVICE R7FA6M5BH)
+set(JLINK_OPTION "-USB 000831915224")
-# Device port default to PORT1 Highspeed
-if (NOT DEFINED PORT)
-set(PORT 1)
+# device default to PORT 1 High Speed
+if (NOT DEFINED RHPORT_DEVICE)
+ set(RHPORT_DEVICE 1)
+endif()
+if (NOT DEFINED RHPORT_HOST)
+ set(RHPORT_HOST 0)
endif()
-
-# Host port will be the other port
-set(HOST_PORT $)
function(update_board TARGET)
- target_compile_definitions(${TARGET} PUBLIC
- BOARD_TUD_RHPORT=${PORT}
- BOARD_TUH_RHPORT=${HOST_PORT}
- # port 0 is fullspeed, port 1 is highspeed
- BOARD_TUD_MAX_SPEED=$
- BOARD_TUH_MAX_SPEED=$
- )
endfunction()
diff --git a/hw/bsp/ra/boards/ra6m5_ek/board.h b/hw/bsp/ra/boards/ra6m5_ek/board.h
index 779f718101..33dda99b4f 100644
--- a/hw/bsp/ra/boards/ra6m5_ek/board.h
+++ b/hw/bsp/ra/boards/ra6m5_ek/board.h
@@ -31,35 +31,9 @@
extern "C" {
#endif
-#define LED1 BSP_IO_PORT_00_PIN_08
#define LED_STATE_ON 1
-
-#define SW1 BSP_IO_PORT_00_PIN_05
#define BUTTON_STATE_ACTIVE 0
-static const ioport_pin_cfg_t board_pin_cfg[] = {
- { .pin = LED1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_OUTPUT | IOPORT_CFG_PORT_OUTPUT_LOW },
- { .pin = SW1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_INPUT },
-
- // USB FS
- { .pin = BSP_IO_PORT_04_PIN_07, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS | IOPORT_CFG_DRIVE_HIGH },
- { .pin = BSP_IO_PORT_05_PIN_00, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS | IOPORT_CFG_DRIVE_HIGH},
- { .pin = BSP_IO_PORT_05_PIN_01, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS | IOPORT_CFG_DRIVE_HIGH},
-
- // USB HS
- { .pin = BSP_IO_PORT_07_PIN_07, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_HS },
- { .pin = BSP_IO_PORT_11_PIN_00, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_HS | IOPORT_CFG_DRIVE_HIGH},
- { .pin = BSP_IO_PORT_11_PIN_01, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_HS | IOPORT_CFG_DRIVE_HIGH},
-
- // ETM Trace
- #ifdef TRACE_ETM
- { .pin = BSP_IO_PORT_02_PIN_08, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE | IOPORT_CFG_DRIVE_HS_HIGH },
- { .pin = BSP_IO_PORT_02_PIN_09, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE | IOPORT_CFG_DRIVE_HS_HIGH },
- { .pin = BSP_IO_PORT_02_PIN_10, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE | IOPORT_CFG_DRIVE_HS_HIGH },
- { .pin = BSP_IO_PORT_02_PIN_11, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE | IOPORT_CFG_DRIVE_HS_HIGH },
- { .pin = BSP_IO_PORT_02_PIN_14, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE | IOPORT_CFG_DRIVE_HS_HIGH },
- #endif
-};
#ifdef __cplusplus
}
diff --git a/hw/bsp/ra/boards/ra6m5_ek/board.mk b/hw/bsp/ra/boards/ra6m5_ek/board.mk
index a5c9337645..5fcc1d0f12 100644
--- a/hw/bsp/ra/boards/ra6m5_ek/board.mk
+++ b/hw/bsp/ra/boards/ra6m5_ek/board.mk
@@ -5,6 +5,7 @@ MCU_VARIANT = ra6m5
JLINK_DEVICE = R7FA6M5BH
# Port 1 is highspeed
-PORT ?= 1
+RHPORT_DEVICE ?= 1
+RHPORT_HOST ?= 0
flash: flash-jlink
diff --git a/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_cfg.h
deleted file mode 100644
index 33d3818501..0000000000
--- a/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_cfg.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/* generated configuration header file - do not edit */
-#ifndef BSP_CFG_H_
-#define BSP_CFG_H_
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "bsp_clock_cfg.h"
-#include "bsp_mcu_family_cfg.h"
-#include "board_cfg.h"
-
-#define RA_NOT_DEFINED 0
-#ifndef BSP_CFG_RTOS
-#if (RA_NOT_DEFINED) != (2)
-#define BSP_CFG_RTOS (2)
-#elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED)
- #define BSP_CFG_RTOS (1)
-#else
- #define BSP_CFG_RTOS (0)
-#endif
-#endif
-#ifndef BSP_CFG_RTC_USED
-#define BSP_CFG_RTC_USED (RA_NOT_DEFINED)
-#endif
-#undef RA_NOT_DEFINED
-#if defined(_RA_BOOT_IMAGE)
- #define BSP_CFG_BOOT_IMAGE (1)
-#endif
-#define BSP_CFG_MCU_VCC_MV (3300)
-#define BSP_CFG_STACK_MAIN_BYTES (0x1000)
-#define BSP_CFG_HEAP_BYTES (0x1000)
-#define BSP_CFG_PARAM_CHECKING_ENABLE (1)
-#define BSP_CFG_ASSERT (0)
-#define BSP_CFG_ERROR_LOG (0)
-
-#define BSP_CFG_PFS_PROTECT ((1))
-
-#define BSP_CFG_C_RUNTIME_INIT ((1))
-#define BSP_CFG_EARLY_INIT ((0))
-
-#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0))
-
-#ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED
-#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1)
-#endif
-
-#ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE
-#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0)
-#endif
-#ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE
-#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0)
-#endif
-#ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED
-#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1)
-#endif
-#ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS
-#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-#endif /* BSP_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
deleted file mode 100644
index 6845183db5..0000000000
--- a/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/* generated configuration header file - do not edit */
-#ifndef BSP_MCU_DEVICE_PN_CFG_H_
-#define BSP_MCU_DEVICE_PN_CFG_H_
-#define BSP_MCU_R7FA6M5BH3CFC
-#define BSP_MCU_FEATURE_SET ('B')
-#define BSP_ROM_SIZE_BYTES (2097152)
-#define BSP_RAM_SIZE_BYTES (524288)
-#define BSP_DATA_FLASH_SIZE_BYTES (8192)
-#define BSP_PACKAGE_LQFP
-#define BSP_PACKAGE_PINS (176)
-#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp_clock_cfg.h b/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp_clock_cfg.h
deleted file mode 100644
index 0eb5e05167..0000000000
--- a/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp_clock_cfg.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/* generated configuration header file - do not edit */
-#ifndef BSP_CLOCK_CFG_H_
-#define BSP_CLOCK_CFG_H_
-
-#define BSP_CFG_CLOCKS_SECURE (0)
-#define BSP_CFG_CLOCKS_OVERRIDE (0)
-#define BSP_CFG_XTAL_HZ (24000000) /* XTAL 24000000Hz */
-#define BSP_CFG_HOCO_FREQUENCY (2) /* HOCO 20MHz */
-#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */
-#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_3) /* PLL Div /3 */
-#define BSP_CFG_PLL_MUL (BSP_CLOCKS_PLL_MUL(25U,0U)) /* PLL Mul x25.0 */
-#define BSP_CFG_PLL2_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL2 Src: XTAL */
-#define BSP_CFG_PLL2_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL2 Div /2 */
-#define BSP_CFG_PLL2_MUL (BSP_CLOCKS_PLL_MUL(20U,0U)) /* PLL2 Mul x20.0 */
-#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */
-#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */
-#define BSP_CFG_UCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2) /* UCLK Src: PLL2 */
-#define BSP_CFG_U60CK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2) /* U60CK Src: PLL2 */
-#define BSP_CFG_OCTA_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* OCTASPICLK Disabled */
-#define BSP_CFG_CANFDCLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CANFDCLK Disabled */
-#define BSP_CFG_CECCLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CECCLK Disabled */
-#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* ICLK Div /1 */
-#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKA Div /2 */
-#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKB Div /4 */
-#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKC Div /4 */
-#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKD Div /2 */
-#define BSP_CFG_BCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* BCLK Div /2 */
-#define BSP_CFG_BCLK_OUTPUT (2) /* EBCLK Div /2 */
-#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* FCLK Div /4 */
-#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */
-#define BSP_CFG_UCK_DIV (BSP_CLOCKS_USB_CLOCK_DIV_5) /* UCLK Div /5 */
-#define BSP_CFG_U60CK_DIV (BSP_CLOCKS_USB60_CLOCK_DIV_4) /* U60CK Div /4 */
-#define BSP_CFG_OCTA_DIV (BSP_CLOCKS_OCTA_CLOCK_DIV_1) /* OCTASPICLK Div /1 */
-#define BSP_CFG_CANFDCLK_DIV (BSP_CLOCKS_CANFD_CLOCK_DIV_1) /* CANFDCLK Div /1 */
-#define BSP_CFG_CECCLK_DIV (BSP_CLOCKS_CEC_CLOCK_DIV_1) /* CECCLK Div /1 */
-
-#endif /* BSP_CLOCK_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra6m5_ek/ozone/ra6m5.jdebug b/hw/bsp/ra/boards/ra6m5_ek/ozone/ra6m5.jdebug
index 7b8ee9c953..ca18fed7cd 100644
--- a/hw/bsp/ra/boards/ra6m5_ek/ozone/ra6m5.jdebug
+++ b/hw/bsp/ra/boards/ra6m5_ek/ozone/ra6m5.jdebug
@@ -20,9 +20,7 @@ void OnProjectLoad (void) {
Project.SetTraceSource ("Trace Pins");
Project.SetTracePortWidth (4);
- //File.Open ("../../../../../../examples/device/cdc_msc/cmake-build-ra6m5/cdc_msc.elf");
- //File.Open ("../../../../../../examples/dual/cmake-build-ra6m5/host_hid_to_device_cdc/host_hid_to_device_cdc.elf");
- File.Open ("../../../../../../examples/cmake-build-ra6m5/host/cdc_msc_hid/cdc_msc_hid.elf");
+ File.Open ("../../../../../../examples/cmake-build-ra6m5_ek/device/cdc_msc/cdc_msc.elf");
}
/*********************************************************************
*
diff --git a/hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h
new file mode 100644
index 0000000000..90afbdef3d
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h
@@ -0,0 +1,62 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_CFG_H_
+#define BSP_CFG_H_
+#ifdef __cplusplus
+ extern "C" {
+ #endif
+
+ #include "bsp_clock_cfg.h"
+ #include "bsp_mcu_family_cfg.h"
+ #include "board_cfg.h"
+ #define RA_NOT_DEFINED 0
+ #ifndef BSP_CFG_RTOS
+ #if (RA_NOT_DEFINED) != (RA_NOT_DEFINED)
+ #define BSP_CFG_RTOS (2)
+ #elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED)
+ #define BSP_CFG_RTOS (1)
+ #else
+ #define BSP_CFG_RTOS (0)
+ #endif
+ #endif
+ #ifndef BSP_CFG_RTC_USED
+ #define BSP_CFG_RTC_USED (RA_NOT_DEFINED)
+ #endif
+ #undef RA_NOT_DEFINED
+ #if defined(_RA_BOOT_IMAGE)
+ #define BSP_CFG_BOOT_IMAGE (1)
+ #endif
+ #define BSP_CFG_MCU_VCC_MV (3300)
+ #define BSP_CFG_STACK_MAIN_BYTES (0x1000)
+ #define BSP_CFG_HEAP_BYTES (0x1000)
+ #define BSP_CFG_PARAM_CHECKING_ENABLE (0)
+ #define BSP_CFG_ASSERT (0)
+ #define BSP_CFG_ERROR_LOG (0)
+
+ #define BSP_CFG_PFS_PROTECT ((1))
+
+ #define BSP_CFG_C_RUNTIME_INIT ((1))
+ #define BSP_CFG_EARLY_INIT ((0))
+
+ #define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0))
+
+ #ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED
+ #define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1)
+ #endif
+
+ #ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE
+ #define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0)
+ #endif
+ #ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE
+ #define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0)
+ #endif
+ #ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED
+ #define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1)
+ #endif
+ #ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS
+ #define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
+ #endif
+
+ #ifdef __cplusplus
+ }
+ #endif
+#endif /* BSP_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_mcu_device_cfg.h b/hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h
similarity index 100%
rename from hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_mcu_device_cfg.h
rename to hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h
diff --git a/hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
new file mode 100644
index 0000000000..e532478f8f
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
@@ -0,0 +1,11 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_MCU_DEVICE_PN_CFG_H_
+#define BSP_MCU_DEVICE_PN_CFG_H_
+#define BSP_MCU_R7FA6M5BH3CFC
+ #define BSP_MCU_FEATURE_SET ('B')
+ #define BSP_ROM_SIZE_BYTES (2097152)
+ #define BSP_RAM_SIZE_BYTES (524288)
+ #define BSP_DATA_FLASH_SIZE_BYTES (8192)
+ #define BSP_PACKAGE_LQFP
+ #define BSP_PACKAGE_PINS (176)
+#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h
similarity index 55%
rename from hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h
rename to hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h
index 26e184a94a..c01219377a 100644
--- a/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h
+++ b/hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h
@@ -5,17 +5,17 @@
extern "C" {
#endif
-#include "bsp_mcu_device_pn_cfg.h"
-#include "bsp_mcu_device_cfg.h"
-#include "../../../ra/fsp/src/bsp/mcu/ra4m3/bsp_mcu_info.h"
-#include "bsp_clock_cfg.h"
-#define BSP_MCU_GROUP_RA4M3 (1)
-#define BSP_LOCO_HZ (32768)
-#define BSP_MOCO_HZ (8000000)
-#define BSP_SUB_CLOCK_HZ (32768)
-#if BSP_CFG_HOCO_FREQUENCY == 0
-#define BSP_HOCO_HZ (16000000)
-#elif BSP_CFG_HOCO_FREQUENCY == 1
+ #include "bsp_mcu_device_pn_cfg.h"
+ #include "bsp_mcu_device_cfg.h"
+ #include "../../../ra/fsp/src/bsp/mcu/ra6m5/bsp_mcu_info.h"
+ #include "bsp_clock_cfg.h"
+ #define BSP_MCU_GROUP_RA6M5 (1)
+ #define BSP_LOCO_HZ (32768)
+ #define BSP_MOCO_HZ (8000000)
+ #define BSP_SUB_CLOCK_HZ (32768)
+ #if BSP_CFG_HOCO_FREQUENCY == 0
+ #define BSP_HOCO_HZ (16000000)
+ #elif BSP_CFG_HOCO_FREQUENCY == 1
#define BSP_HOCO_HZ (18000000)
#elif BSP_CFG_HOCO_FREQUENCY == 2
#define BSP_HOCO_HZ (20000000)
@@ -23,61 +23,62 @@ extern "C" {
#error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h"
#endif
-#define BSP_CFG_FLL_ENABLE (0)
+ #define BSP_CFG_FLL_ENABLE (0)
-#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U)
-#define BSP_VECTOR_TABLE_MAX_ENTRIES (112U)
+ #define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U)
+ #define BSP_VECTOR_TABLE_MAX_ENTRIES (112U)
+ #define BSP_CFG_INLINE_IRQ_FUNCTIONS (1)
-#if defined(_RA_TZ_SECURE)
+ #if defined(_RA_TZ_SECURE)
#define BSP_TZ_SECURE_BUILD (1)
#define BSP_TZ_NONSECURE_BUILD (0)
#elif defined(_RA_TZ_NONSECURE)
#define BSP_TZ_SECURE_BUILD (0)
#define BSP_TZ_NONSECURE_BUILD (1)
#else
-#define BSP_TZ_SECURE_BUILD (0)
-#define BSP_TZ_NONSECURE_BUILD (0)
-#endif
-
-/* TrustZone Settings */
-#define BSP_TZ_CFG_INIT_SECURE_ONLY (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE))
-#define BSP_TZ_CFG_SKIP_INIT (BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_INIT_SECURE_ONLY)
-#define BSP_TZ_CFG_EXCEPTION_RESPONSE (0)
+ #define BSP_TZ_SECURE_BUILD (0)
+ #define BSP_TZ_NONSECURE_BUILD (0)
+ #endif
-/* CMSIS TrustZone Settings */
-#define SCB_CSR_AIRCR_INIT (1)
-#define SCB_AIRCR_BFHFNMINS_VAL (0)
-#define SCB_AIRCR_SYSRESETREQS_VAL (1)
-#define SCB_AIRCR_PRIS_VAL (0)
-#define TZ_FPU_NS_USAGE (1)
+ /* TrustZone Settings */
+ #define BSP_TZ_CFG_INIT_SECURE_ONLY (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE))
+ #define BSP_TZ_CFG_SKIP_INIT (BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_INIT_SECURE_ONLY)
+ #define BSP_TZ_CFG_EXCEPTION_RESPONSE (0)
+
+ /* CMSIS TrustZone Settings */
+ #define SCB_CSR_AIRCR_INIT (1)
+ #define SCB_AIRCR_BFHFNMINS_VAL (0)
+ #define SCB_AIRCR_SYSRESETREQS_VAL (1)
+ #define SCB_AIRCR_PRIS_VAL (0)
+ #define TZ_FPU_NS_USAGE (1)
#ifndef SCB_NSACR_CP10_11_VAL
-#define SCB_NSACR_CP10_11_VAL (3U)
+ #define SCB_NSACR_CP10_11_VAL (3U)
#endif
#ifndef FPU_FPCCR_TS_VAL
-#define FPU_FPCCR_TS_VAL (1U)
+ #define FPU_FPCCR_TS_VAL (1U)
#endif
-#define FPU_FPCCR_CLRONRETS_VAL (1)
+ #define FPU_FPCCR_CLRONRETS_VAL (1)
#ifndef FPU_FPCCR_CLRONRET_VAL
-#define FPU_FPCCR_CLRONRET_VAL (1)
+ #define FPU_FPCCR_CLRONRET_VAL (1)
#endif
-/* The C-Cache line size that is configured during startup. */
+ /* The C-Cache line size that is configured during startup. */
#ifndef BSP_CFG_C_CACHE_LINE_SIZE
-#define BSP_CFG_C_CACHE_LINE_SIZE (1U)
+ #define BSP_CFG_C_CACHE_LINE_SIZE (1U)
#endif
-/* Type 1 Peripheral Security Attribution */
+ /* Type 1 Peripheral Security Attribution */
-/* Peripheral Security Attribution Register (PSAR) Settings */
+ /* Peripheral Security Attribution Register (PSAR) Settings */
#ifndef BSP_TZ_CFG_PSARB
#define BSP_TZ_CFG_PSARB (\
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CAN1 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* CAN0 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* IIC1 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9) /* IIC0 */ | \
- (((1 > 0) ? 0U : 1U) << 11) /* USBFS */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* USBFS */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 18) /* SPI1 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 19) /* SPI0 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* SCI9 */ | \
@@ -114,7 +115,7 @@ extern "C" {
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* POEG1 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* POEG0 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* ADC1 */ | \
- (((1 > 0) ? 0U : 1U) << 16) /* ADC0 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 16) /* ADC0 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 20) /* DAC */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* TSN */ | \
0xffae07f0) /* Unused */
@@ -129,13 +130,13 @@ extern "C" {
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* GPT9 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* GPT8 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* GPT7 */ | \
- (((1 > 0) ? 0U : 1U) << 25) /* GPT6 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* GPT6 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* GPT5 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* GPT4 */ | \
- (((1 > 0) ? 0U : 1U) << 28) /* GPT3 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* GPT3 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* GPT2 */ | \
- (((1 > 0) ? 0U : 1U) << 30) /* GPT1 */ | \
- (((1 > 0) ? 0U : 1U) << 31) /* GPT0 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* GPT1 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* GPT0 */ | \
0x3f3ff8) /* Unused */
#endif
#ifndef BSP_TZ_CFG_MSSAR
@@ -145,19 +146,19 @@ extern "C" {
0xfffffffc) /* Unused */
#endif
-/* Type 2 Peripheral Security Attribution */
+ /* Type 2 Peripheral Security Attribution */
-/* Security attribution for Cache registers. */
+ /* Security attribution for Cache registers. */
#ifndef BSP_TZ_CFG_CSAR
#define BSP_TZ_CFG_CSAR (0xFFFFFFFFU)
#endif
-/* Security attribution for RSTSRn registers. */
+ /* Security attribution for RSTSRn registers. */
#ifndef BSP_TZ_CFG_RSTSAR
#define BSP_TZ_CFG_RSTSAR (0xFFFFFFFFU)
#endif
-/* Security attribution for registers of LVD channels. */
+ /* Security attribution for registers of LVD channels. */
#ifndef BSP_TZ_CFG_LVDSAR
#define BSP_TZ_CFG_LVDSAR (\
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) | /* LVD Channel 1 */ \
@@ -165,16 +166,16 @@ extern "C" {
0xFFFFFFFCU)
#endif
-/* Security attribution for LPM registers. */
+ /* Security attribution for LPM registers. */
#ifndef BSP_TZ_CFG_LPMSAR
#define BSP_TZ_CFG_LPMSAR ((RA_NOT_DEFINED > 0) ? 0xFFFFFCEAU : 0xFFFFFFFFU)
#endif
-/* Deep Standby Interrupt Factor Security Attribution Register. */
+ /* Deep Standby Interrupt Factor Security Attribution Register. */
#ifndef BSP_TZ_CFG_DPFSAR
#define BSP_TZ_CFG_DPFSAR ((RA_NOT_DEFINED > 0) ? 0xF2E00000U : 0xFFFFFFFFU)
#endif
-/* Security attribution for CGC registers. */
+ /* Security attribution for CGC registers. */
#ifndef BSP_TZ_CFG_CGFSAR
#if BSP_CFG_CLOCKS_SECURE
/* Protect all CGC registers from Non-secure write access. */
@@ -185,12 +186,12 @@ extern "C" {
#endif
#endif
-/* Security attribution for Battery Backup registers. */
+ /* Security attribution for Battery Backup registers. */
#ifndef BSP_TZ_CFG_BBFSAR
#define BSP_TZ_CFG_BBFSAR (0x00FFFFFF)
#endif
-/* Security attribution for registers for IRQ channels. */
+ /* Security attribution for registers for IRQ channels. */
#ifndef BSP_TZ_CFG_ICUSARA
#define BSP_TZ_CFG_ICUSARA (\
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ | \
@@ -203,8 +204,8 @@ extern "C" {
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* External IRQ7 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8U) /* External IRQ8 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9U) /* External IRQ9 */ | \
- (((1 > 0) ? 0U : 1U) << 10U) /* External IRQ10 */ | \
- (((1 > 0) ? 0U : 1U) << 11U) /* External IRQ11 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 10U) /* External IRQ10 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11U) /* External IRQ11 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12U) /* External IRQ12 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13U) /* External IRQ13 */ | \
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14U) /* External IRQ14 */ | \
@@ -212,12 +213,12 @@ extern "C" {
0xFFFF0000U)
#endif
-/* Security attribution for NMI registers. */
+ /* Security attribution for NMI registers. */
#ifndef BSP_TZ_CFG_ICUSARB
#define BSP_TZ_CFG_ICUSARB (0 | 0xFFFFFFFEU) /* Should match AIRCR.BFHFNMINS. */
#endif
-/* Security attribution for registers for DMAC channels */
+ /* Security attribution for registers for DMAC channels */
#ifndef BSP_TZ_CFG_ICUSARC
#define BSP_TZ_CFG_ICUSARC (\
(((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* DMAC Channel 0 */ | \
@@ -231,29 +232,29 @@ extern "C" {
0xFFFFFF00U)
#endif
-/* Security attribution registers for SELSR0. */
+ /* Security attribution registers for SELSR0. */
#ifndef BSP_TZ_CFG_ICUSARD
#define BSP_TZ_CFG_ICUSARD ((RA_NOT_DEFINED > 0) ? 0xFFFFFFFEU : 0xFFFFFFFFU)
#endif
-/* Security attribution registers for WUPEN0. */
+ /* Security attribution registers for WUPEN0. */
#ifndef BSP_TZ_CFG_ICUSARE
#define BSP_TZ_CFG_ICUSARE ((RA_NOT_DEFINED > 0) ? 0x04F2FFFFU : 0xFFFFFFFFU)
#endif
-/* Security attribution registers for WUPEN1. */
+ /* Security attribution registers for WUPEN1. */
#ifndef BSP_TZ_CFG_ICUSARF
#define BSP_TZ_CFG_ICUSARF ((RA_NOT_DEFINED > 0) ? 0xFFFFFFF8U : 0xFFFFFFFFU)
#endif
-/* Set DTCSTSAR if the Secure program uses the DTC. */
+ /* Set DTCSTSAR if the Secure program uses the DTC. */
#if RA_NOT_DEFINED == RA_NOT_DEFINED
-#define BSP_TZ_CFG_DTC_USED (0U)
+ #define BSP_TZ_CFG_DTC_USED (0U)
#else
#define BSP_TZ_CFG_DTC_USED (1U)
#endif
-/* Security attribution of FLWT and FCKMHZ registers. */
+ /* Security attribution of FLWT and FCKMHZ registers. */
#ifndef BSP_TZ_CFG_FSAR
/* If the CGC registers are only accessible in Secure mode, than there is no
* reason for nonsecure applications to access FLWT and FCKMHZ. */
@@ -266,118 +267,123 @@ extern "C" {
#endif
#endif
-/* Security attribution for SRAM registers. */
+ /* Security attribution for SRAM registers. */
#ifndef BSP_TZ_CFG_SRAMSAR
/* If the CGC registers are only accessible in Secure mode, than there is no reason for Non Secure applications to access
* SRAM0WTEN and therefore there is no reason to access PRCR2. */
-#define BSP_TZ_CFG_SRAMSAR (\
+ #define BSP_TZ_CFG_SRAMSAR (\
1 | \
((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 1U) : 0U) | \
4 | \
0xFFFFFFF8U)
#endif
-/* Security attribution for Standby RAM registers. */
+ /* Security attribution for Standby RAM registers. */
#ifndef BSP_TZ_CFG_STBRAMSAR
-#define BSP_TZ_CFG_STBRAMSAR (0 | 0xFFFFFFF0U)
+ #define BSP_TZ_CFG_STBRAMSAR (0 | 0xFFFFFFF0U)
#endif
-/* Security attribution for the DMAC Bus Master MPU settings. */
+ /* Security attribution for the DMAC Bus Master MPU settings. */
#ifndef BSP_TZ_CFG_MMPUSARA
-/* The DMAC Bus Master MPU settings should align with the DMAC channel settings. */
-#define BSP_TZ_CFG_MMPUSARA (BSP_TZ_CFG_ICUSARC)
+ /* The DMAC Bus Master MPU settings should align with the DMAC channel settings. */
+ #define BSP_TZ_CFG_MMPUSARA (BSP_TZ_CFG_ICUSARC)
#endif
-/* Security Attribution Register A for BUS Control registers. */
+ /* Security Attribution Register A for BUS Control registers. */
#ifndef BSP_TZ_CFG_BUSSARA
-#define BSP_TZ_CFG_BUSSARA (0xFFFFFFFFU)
+ #define BSP_TZ_CFG_BUSSARA (0xFFFFFFFFU)
#endif
-/* Security Attribution Register B for BUS Control registers. */
+ /* Security Attribution Register B for BUS Control registers. */
#ifndef BSP_TZ_CFG_BUSSARB
-#define BSP_TZ_CFG_BUSSARB (0xFFFFFFFFU)
+ #define BSP_TZ_CFG_BUSSARB (0xFFFFFFFFU)
#endif
-/* Enable Uninitialized Non-Secure Application Fallback. */
+ /* Enable Uninitialized Non-Secure Application Fallback. */
#ifndef BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK
-#define BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK (1U)
+ #define BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK (1U)
#endif
-#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2)
-#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10)
-#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17)
-#define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26)
-#define OFS_SEQ5 (1 << 28) | (1 << 30)
-#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
-/* Option Function Select Register 1 Security Attribution */
+ #define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2)
+ #define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10)
+ #define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17)
+ #define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26)
+ #define OFS_SEQ5 (1 << 28) | (1 << 30)
+ #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
+
+ /* Option Function Select Register 1 Security Attribution */
#ifndef BSP_CFG_ROM_REG_OFS1_SEL
#if defined(_RA_TZ_SECURE) || defined(_RA_TZ_NONSECURE)
- #define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0x700U : 0U) | ((RA_NOT_DEFINED > 0) ? 0U : 0x7U))
+ #define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U | ((0U << 0U)) | ((0U << 2U)) | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0x700U : 0U))
#else
-#define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U)
+ #define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U)
#endif
#endif
-#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) | (1 << 8))
+ #define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) | (1 << 8))
-/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */
-#define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector)
+ /* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */
+ #define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector)
-/* Dual Mode Select Register */
+ /* Dual Mode Select Register */
#ifndef BSP_CFG_ROM_REG_DUALSEL
-#define BSP_CFG_ROM_REG_DUALSEL (0xFFFFFFFFU)
+ #define BSP_CFG_ROM_REG_DUALSEL (0xFFFFFFF8U | (0x7U))
#endif
-/* Block Protection Register 0 */
+ /* Block Protection Register 0 */
#ifndef BSP_CFG_ROM_REG_BPS0
-#define BSP_CFG_ROM_REG_BPS0 (~( 0U))
+ #define BSP_CFG_ROM_REG_BPS0 (~( 0U))
#endif
-/* Block Protection Register 1 */
+ /* Block Protection Register 1 */
#ifndef BSP_CFG_ROM_REG_BPS1
-#define BSP_CFG_ROM_REG_BPS1 (~( 0U))
+ #define BSP_CFG_ROM_REG_BPS1 (~( 0U))
#endif
-/* Block Protection Register 2 */
+ /* Block Protection Register 2 */
#ifndef BSP_CFG_ROM_REG_BPS2
-#define BSP_CFG_ROM_REG_BPS2 (0xFFFFFFFFU)
+ #define BSP_CFG_ROM_REG_BPS2 (~( 0U))
#endif
-/* Block Protection Register 3 */
+ /* Block Protection Register 3 */
#ifndef BSP_CFG_ROM_REG_BPS3
-#define BSP_CFG_ROM_REG_BPS3 (0xFFFFFFFFU)
+ #define BSP_CFG_ROM_REG_BPS3 (0xFFFFFFFFU)
#endif
-/* Permanent Block Protection Register 0 */
+ /* Permanent Block Protection Register 0 */
#ifndef BSP_CFG_ROM_REG_PBPS0
-#define BSP_CFG_ROM_REG_PBPS0 (~( 0U))
+ #define BSP_CFG_ROM_REG_PBPS0 (~( 0U))
#endif
-/* Permanent Block Protection Register 1 */
+ /* Permanent Block Protection Register 1 */
#ifndef BSP_CFG_ROM_REG_PBPS1
-#define BSP_CFG_ROM_REG_PBPS1 (~( 0U))
+ #define BSP_CFG_ROM_REG_PBPS1 (~( 0U))
#endif
-/* Permanent Block Protection Register 2 */
+ /* Permanent Block Protection Register 2 */
#ifndef BSP_CFG_ROM_REG_PBPS2
-#define BSP_CFG_ROM_REG_PBPS2 (0xFFFFFFFFU)
+ #define BSP_CFG_ROM_REG_PBPS2 (~( 0U))
#endif
-/* Permanent Block Protection Register 3 */
+ /* Permanent Block Protection Register 3 */
#ifndef BSP_CFG_ROM_REG_PBPS3
-#define BSP_CFG_ROM_REG_PBPS3 (0xFFFFFFFFU)
+ #define BSP_CFG_ROM_REG_PBPS3 (0xFFFFFFFFU)
#endif
-/* Security Attribution for Block Protection Register 0 (If any blocks are marked as protected in the secure application, then mark them as secure) */
+ /* Security Attribution for Block Protection Register 0 (If any blocks are marked as protected in the secure application, then mark them as secure) */
#ifndef BSP_CFG_ROM_REG_BPS_SEL0
-#define BSP_CFG_ROM_REG_BPS_SEL0 (BSP_CFG_ROM_REG_BPS0 & BSP_CFG_ROM_REG_PBPS0)
+ #define BSP_CFG_ROM_REG_BPS_SEL0 (BSP_CFG_ROM_REG_BPS0 & BSP_CFG_ROM_REG_PBPS0)
#endif
-/* Security Attribution for Block Protection Register 1 (If any blocks are marked as protected in the secure application, then mark them as secure) */
+ /* Security Attribution for Block Protection Register 1 (If any blocks are marked as protected in the secure application, then mark them as secure) */
#ifndef BSP_CFG_ROM_REG_BPS_SEL1
-#define BSP_CFG_ROM_REG_BPS_SEL1 (BSP_CFG_ROM_REG_BPS1 & BSP_CFG_ROM_REG_PBPS1)
+ #define BSP_CFG_ROM_REG_BPS_SEL1 (BSP_CFG_ROM_REG_BPS1 & BSP_CFG_ROM_REG_PBPS1)
#endif
-/* Security Attribution for Block Protection Register 2 (If any blocks are marked as protected in the secure application, then mark them as secure) */
+ /* Security Attribution for Block Protection Register 2 (If any blocks are marked as protected in the secure application, then mark them as secure) */
#ifndef BSP_CFG_ROM_REG_BPS_SEL2
-#define BSP_CFG_ROM_REG_BPS_SEL2 (0xFFFFFFFFU)
+ #define BSP_CFG_ROM_REG_BPS_SEL2 (BSP_CFG_ROM_REG_BPS2 & BSP_CFG_ROM_REG_PBPS2)
#endif
-/* Security Attribution for Block Protection Register 3 (If any blocks are marked as protected in the secure application, then mark them as secure) */
+ /* Security Attribution for Block Protection Register 3 (If any blocks are marked as protected in the secure application, then mark them as secure) */
#ifndef BSP_CFG_ROM_REG_BPS_SEL3
-#define BSP_CFG_ROM_REG_BPS_SEL3 (0xFFFFFFFFU)
+ #define BSP_CFG_ROM_REG_BPS_SEL3 (BSP_CFG_ROM_REG_BPS3 & BSP_CFG_ROM_REG_PBPS3)
+#endif
+ /* Security Attribution for Bank Select Register */
+#ifndef BSP_CFG_ROM_REG_BANKSEL_SEL
+ #define BSP_CFG_ROM_REG_BANKSEL_SEL (0xFFFFFFFFU)
#endif
#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT
-#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9)
+ #define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9)
#endif
#ifdef __cplusplus
diff --git a/hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h b/hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h
new file mode 100644
index 0000000000..d2eec08aeb
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h
@@ -0,0 +1,99 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_PIN_CFG_H_
+#define BSP_PIN_CFG_H_
+#include "r_ioport.h"
+
+/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+#define MIKROBUS_AN_ARDUINO_A0 (BSP_IO_PORT_00_PIN_00)
+#define ARDUINO_A1 (BSP_IO_PORT_00_PIN_01)
+#define ARDUINO_A2 (BSP_IO_PORT_00_PIN_02)
+#define ARDUINO_A3 (BSP_IO_PORT_00_PIN_03)
+#define SW2 (BSP_IO_PORT_00_PIN_04)
+#define SW1 (BSP_IO_PORT_00_PIN_05)
+#define LED1 (BSP_IO_PORT_00_PIN_06)
+#define LED2 (BSP_IO_PORT_00_PIN_07)
+#define LED3 (BSP_IO_PORT_00_PIN_08)
+#define ARDUINO_A4 (BSP_IO_PORT_00_PIN_14)
+#define ARDUINO_A5 (BSP_IO_PORT_00_PIN_15)
+#define OSPI_CLK (BSP_IO_PORT_01_PIN_00)
+#define OSPI_SIO7 (BSP_IO_PORT_01_PIN_01)
+#define OSPI_SIO1 (BSP_IO_PORT_01_PIN_02)
+#define OSPI_SIO6 (BSP_IO_PORT_01_PIN_03)
+#define OSPI_DQS (BSP_IO_PORT_01_PIN_04)
+#define OSPI_SIO5 (BSP_IO_PORT_01_PIN_05)
+#define OSPI_SIO0 (BSP_IO_PORT_01_PIN_06)
+#define OSPI_SIO3 (BSP_IO_PORT_01_PIN_07)
+#define MIKROBUS_PWM_ARDUINO_D3_PWM (BSP_IO_PORT_01_PIN_11)
+#define ARDUINO_D4 (BSP_IO_PORT_01_PIN_12)
+#define ARDUINO_D5 (BSP_IO_PORT_01_PIN_13)
+#define ARDUINO_D6 (BSP_IO_PORT_01_PIN_14)
+#define ARDUINO_D9 (BSP_IO_PORT_01_PIN_15)
+#define MIKROBUS_MISO_ARDUINO_MISO_PMOD1_MISO (BSP_IO_PORT_02_PIN_02)
+#define MIKROBUS_MOSI_ARDUINO_MOSI_PMOD1_MOSI (BSP_IO_PORT_02_PIN_03)
+#define MIKROBUS_SCK_ARDUINO_SCK_PMOD1_SCK (BSP_IO_PORT_02_PIN_04)
+#define MIKROBUS_SS_ARDUINO_SS (BSP_IO_PORT_02_PIN_05)
+#define PMOD1_SS (BSP_IO_PORT_02_PIN_06)
+#define ARDUINO_D8 (BSP_IO_PORT_02_PIN_07)
+#define PMOD1_SS2 (BSP_IO_PORT_03_PIN_01)
+#define PMOD1_SS3 (BSP_IO_PORT_03_PIN_02)
+#define MIKROBUS_RESET_ARDUINO_RESET (BSP_IO_PORT_03_PIN_03)
+#define QSPI_CLK (BSP_IO_PORT_03_PIN_05)
+#define QSPI_CS (BSP_IO_PORT_03_PIN_06)
+#define QSPI_IO0 (BSP_IO_PORT_03_PIN_07)
+#define QSPI_IO1 (BSP_IO_PORT_03_PIN_08)
+#define QSPI_IO2 (BSP_IO_PORT_03_PIN_09)
+#define QSPI_IO3 (BSP_IO_PORT_03_PIN_10)
+#define PMOD1_RST (BSP_IO_PORT_03_PIN_11)
+#define PMOD2_INT (BSP_IO_PORT_04_PIN_00)
+#define ETH_MDC (BSP_IO_PORT_04_PIN_01)
+#define ETH_MDIO (BSP_IO_PORT_04_PIN_02)
+#define ETH_RST (BSP_IO_PORT_04_PIN_03)
+#define PMOD2_RST (BSP_IO_PORT_04_PIN_04)
+#define ETH_TXEN (BSP_IO_PORT_04_PIN_05)
+#define ETH_TXD1 (BSP_IO_PORT_04_PIN_06)
+#define USBFS_VBUS (BSP_IO_PORT_04_PIN_07)
+#define PMOD2_SS2 (BSP_IO_PORT_04_PIN_08)
+#define MIKROBUS_INT_ARDUINO_INT0 (BSP_IO_PORT_04_PIN_09)
+#define PMOD2_MISO (BSP_IO_PORT_04_PIN_10)
+#define PMOD2_MOSI (BSP_IO_PORT_04_PIN_11)
+#define PMOD2_SCK (BSP_IO_PORT_04_PIN_12)
+#define PMOS2_SS (BSP_IO_PORT_04_PIN_13)
+#define GROVE1_SDA_QWIIC_SDA (BSP_IO_PORT_04_PIN_14)
+#define GROVE1_SCL_QWIIC_SCL (BSP_IO_PORT_04_PIN_15)
+#define USBFS_VBUS_EN (BSP_IO_PORT_05_PIN_00)
+#define USBFS_OVERCURA (BSP_IO_PORT_05_PIN_01)
+#define GROVE2_SCL (BSP_IO_PORT_05_PIN_05)
+#define GROVE2_SDA (BSP_IO_PORT_05_PIN_06)
+#define MIKROBUS_SDA_ARDUINO_SDA (BSP_IO_PORT_05_PIN_11)
+#define MIKROBUS_SCL_ARDUINO_SCL (BSP_IO_PORT_05_PIN_12)
+#define OSPI_SIO4 (BSP_IO_PORT_06_PIN_00)
+#define OSPI_SIO2 (BSP_IO_PORT_06_PIN_01)
+#define OSPI_CS1 (BSP_IO_PORT_06_PIN_02)
+#define ARDUINO_D7 (BSP_IO_PORT_06_PIN_08)
+#define CAN_TXD (BSP_IO_PORT_06_PIN_09)
+#define CAN_RDX (BSP_IO_PORT_06_PIN_10)
+#define CAN_STBY (BSP_IO_PORT_06_PIN_11)
+#define MIKROBUS_TX_ARDUINO_TX (BSP_IO_PORT_06_PIN_13)
+#define MIKROBUS_RX_ARDUINO_RX (BSP_IO_PORT_06_PIN_14)
+#define OSPI_RST (BSP_IO_PORT_06_PIN_15)
+#define ETH_TXD0 (BSP_IO_PORT_07_PIN_00)
+#define ETH_50REF (BSP_IO_PORT_07_PIN_01)
+#define ETH_RXD0 (BSP_IO_PORT_07_PIN_02)
+#define ETH_RXD1 (BSP_IO_PORT_07_PIN_03)
+#define ETH_RXERR (BSP_IO_PORT_07_PIN_04)
+#define ETH_CRSDV (BSP_IO_PORT_07_PIN_05)
+#define ETH_INT (BSP_IO_PORT_07_PIN_06)
+#define USBHS_OVERCURA (BSP_IO_PORT_07_PIN_07)
+#define PMOD2_SS3 (BSP_IO_PORT_07_PIN_08)
+#define PMOD1_INT (BSP_IO_PORT_09_PIN_05)
+#define USBHS_VBUS_EN (BSP_IO_PORT_11_PIN_00)
+#define USBHS_VBUS (BSP_IO_PORT_11_PIN_01)
+extern const ioport_cfg_t g_bsp_pin_cfg; /* RA6M5 EK */
+
+void BSP_PinConfigSecurityInit();
+
+/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+#endif /* BSP_PIN_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h b/hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h
new file mode 100644
index 0000000000..d2688bf5ba
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h
@@ -0,0 +1,13 @@
+/* generated configuration header file - do not edit */
+#ifndef R_IOPORT_CFG_H_
+#define R_IOPORT_CFG_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* R_IOPORT_CFG_H_ */
diff --git a/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp_clock_cfg.h b/hw/bsp/ra/boards/ra6m5_ek/ra_gen/bsp_clock_cfg.h
similarity index 100%
rename from hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp_clock_cfg.h
rename to hw/bsp/ra/boards/ra6m5_ek/ra_gen/bsp_clock_cfg.h
diff --git a/hw/bsp/ra/boards/ra6m5_ek/ra_gen/common_data.c b/hw/bsp/ra/boards/ra6m5_ek/ra_gen/common_data.c
new file mode 100644
index 0000000000..50036c0adc
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m5_ek/ra_gen/common_data.c
@@ -0,0 +1,11 @@
+/* generated common source file - do not edit */
+#include "common_data.h"
+ioport_instance_ctrl_t g_ioport_ctrl;
+const ioport_instance_t g_ioport =
+ {
+ .p_api = &g_ioport_on_ioport,
+ .p_ctrl = &g_ioport_ctrl,
+ .p_cfg = &g_bsp_pin_cfg,
+ };
+void g_common_init(void) {
+}
diff --git a/hw/bsp/ra/boards/ra6m5_ek/ra_gen/common_data.h b/hw/bsp/ra/boards/ra6m5_ek/ra_gen/common_data.h
new file mode 100644
index 0000000000..6a08cbee09
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m5_ek/ra_gen/common_data.h
@@ -0,0 +1,20 @@
+/* generated common header file - do not edit */
+#ifndef COMMON_DATA_H_
+#define COMMON_DATA_H_
+#include
+#include "bsp_api.h"
+#include "r_ioport.h"
+#include "bsp_pin_cfg.h"
+FSP_HEADER
+#define IOPORT_CFG_NAME g_bsp_pin_cfg
+#define IOPORT_CFG_OPEN R_IOPORT_Open
+#define IOPORT_CFG_CTRL g_ioport_ctrl
+
+/* IOPORT Instance */
+extern const ioport_instance_t g_ioport;
+
+/* IOPORT control structure. */
+extern ioport_instance_ctrl_t g_ioport_ctrl;
+void g_common_init(void);
+FSP_FOOTER
+#endif /* COMMON_DATA_H_ */
diff --git a/hw/bsp/ra/boards/ra6m5_ek/ra_gen/pin_data.c b/hw/bsp/ra/boards/ra6m5_ek/ra_gen/pin_data.c
new file mode 100644
index 0000000000..6b814d74ac
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m5_ek/ra_gen/pin_data.c
@@ -0,0 +1,411 @@
+/* generated pin source file - do not edit */
+#include "bsp_api.h"
+#include "r_ioport.h"
+
+
+const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = {
+ {
+ .pin = BSP_IO_PORT_00_PIN_00,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE)
+ },
+ {
+ .pin = BSP_IO_PORT_00_PIN_01,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE)
+ },
+ {
+ .pin = BSP_IO_PORT_00_PIN_02,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE)
+ },
+ {
+ .pin = BSP_IO_PORT_00_PIN_03,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE)
+ },
+ {
+ .pin = BSP_IO_PORT_00_PIN_04,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_IRQ_ENABLE | (uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT)
+ },
+ {
+ .pin = BSP_IO_PORT_00_PIN_05,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_IRQ_ENABLE | (uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT)
+ },
+ {
+ .pin = BSP_IO_PORT_00_PIN_06,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+ },
+ {
+ .pin = BSP_IO_PORT_00_PIN_07,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+ },
+ {
+ .pin = BSP_IO_PORT_00_PIN_08,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+ },
+ {
+ .pin = BSP_IO_PORT_00_PIN_14,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE)
+ },
+ {
+ .pin = BSP_IO_PORT_00_PIN_15,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE)
+ },
+ {
+ .pin = BSP_IO_PORT_01_PIN_00,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI)
+ },
+ {
+ .pin = BSP_IO_PORT_01_PIN_01,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI)
+ },
+ {
+ .pin = BSP_IO_PORT_01_PIN_02,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI)
+ },
+ {
+ .pin = BSP_IO_PORT_01_PIN_03,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI)
+ },
+ {
+ .pin = BSP_IO_PORT_01_PIN_04,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI)
+ },
+ {
+ .pin = BSP_IO_PORT_01_PIN_05,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI)
+ },
+ {
+ .pin = BSP_IO_PORT_01_PIN_06,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI)
+ },
+ {
+ .pin = BSP_IO_PORT_01_PIN_07,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI)
+ },
+ {
+ .pin = BSP_IO_PORT_01_PIN_08,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG)
+ },
+ {
+ .pin = BSP_IO_PORT_01_PIN_11,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_GPT1)
+ },
+ {
+ .pin = BSP_IO_PORT_01_PIN_12,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+ },
+ {
+ .pin = BSP_IO_PORT_01_PIN_13,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+ },
+ {
+ .pin = BSP_IO_PORT_01_PIN_14,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+ },
+ {
+ .pin = BSP_IO_PORT_01_PIN_15,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+ },
+ {
+ .pin = BSP_IO_PORT_02_PIN_02,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
+ },
+ {
+ .pin = BSP_IO_PORT_02_PIN_03,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
+ },
+ {
+ .pin = BSP_IO_PORT_02_PIN_04,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
+ },
+ {
+ .pin = BSP_IO_PORT_02_PIN_05,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
+ },
+ {
+ .pin = BSP_IO_PORT_02_PIN_06,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
+ },
+ {
+ .pin = BSP_IO_PORT_02_PIN_07,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+ },
+ {
+ .pin = BSP_IO_PORT_02_PIN_08,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_TRACE)
+ },
+ {
+ .pin = BSP_IO_PORT_02_PIN_09,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_TRACE)
+ },
+ {
+ .pin = BSP_IO_PORT_02_PIN_10,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_TRACE)
+ },
+ {
+ .pin = BSP_IO_PORT_02_PIN_11,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_TRACE)
+ },
+ {
+ .pin = BSP_IO_PORT_02_PIN_14,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_TRACE)
+ },
+ {
+ .pin = BSP_IO_PORT_03_PIN_00,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG)
+ },
+ {
+ .pin = BSP_IO_PORT_03_PIN_01,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
+ },
+ {
+ .pin = BSP_IO_PORT_03_PIN_02,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
+ },
+ {
+ .pin = BSP_IO_PORT_03_PIN_03,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+ },
+ {
+ .pin = BSP_IO_PORT_03_PIN_05,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_QSPI)
+ },
+ {
+ .pin = BSP_IO_PORT_03_PIN_06,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_QSPI)
+ },
+ {
+ .pin = BSP_IO_PORT_03_PIN_07,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_QSPI)
+ },
+ {
+ .pin = BSP_IO_PORT_03_PIN_08,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_QSPI)
+ },
+ {
+ .pin = BSP_IO_PORT_03_PIN_09,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_QSPI)
+ },
+ {
+ .pin = BSP_IO_PORT_03_PIN_10,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_QSPI)
+ },
+ {
+ .pin = BSP_IO_PORT_03_PIN_11,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+ },
+ {
+ .pin = BSP_IO_PORT_04_PIN_00,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_IRQ_ENABLE | (uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT | (uint32_t) IOPORT_CFG_PULLUP_ENABLE)
+ },
+ {
+ .pin = BSP_IO_PORT_04_PIN_01,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_ETHER_RMII)
+ },
+ {
+ .pin = BSP_IO_PORT_04_PIN_02,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_ETHER_RMII)
+ },
+ {
+ .pin = BSP_IO_PORT_04_PIN_03,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_HIGH)
+ },
+ {
+ .pin = BSP_IO_PORT_04_PIN_04,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+ },
+ {
+ .pin = BSP_IO_PORT_04_PIN_05,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_ETHER_RMII)
+ },
+ {
+ .pin = BSP_IO_PORT_04_PIN_06,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_ETHER_RMII)
+ },
+ {
+ .pin = BSP_IO_PORT_04_PIN_07,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)
+ },
+ {
+ .pin = BSP_IO_PORT_04_PIN_08,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+ },
+ {
+ .pin = BSP_IO_PORT_04_PIN_09,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_IRQ_ENABLE | (uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT | (uint32_t) IOPORT_CFG_PULLUP_ENABLE)
+ },
+ {
+ .pin = BSP_IO_PORT_04_PIN_10,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
+ },
+ {
+ .pin = BSP_IO_PORT_04_PIN_11,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
+ },
+ {
+ .pin = BSP_IO_PORT_04_PIN_12,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
+ },
+ {
+ .pin = BSP_IO_PORT_04_PIN_13,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
+ },
+ {
+ .pin = BSP_IO_PORT_04_PIN_14,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_IIC)
+ },
+ {
+ .pin = BSP_IO_PORT_04_PIN_15,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_IIC)
+ },
+ {
+ .pin = BSP_IO_PORT_05_PIN_00,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)
+ },
+ {
+ .pin = BSP_IO_PORT_05_PIN_01,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)
+ },
+ {
+ .pin = BSP_IO_PORT_05_PIN_05,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_NMOS_ENABLE | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI0_2_4_6_8)
+ },
+ {
+ .pin = BSP_IO_PORT_05_PIN_06,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_NMOS_ENABLE | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI0_2_4_6_8)
+ },
+ {
+ .pin = BSP_IO_PORT_05_PIN_11,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_IIC)
+ },
+ {
+ .pin = BSP_IO_PORT_05_PIN_12,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_IIC)
+ },
+ {
+ .pin = BSP_IO_PORT_06_PIN_00,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI)
+ },
+ {
+ .pin = BSP_IO_PORT_06_PIN_01,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI)
+ },
+ {
+ .pin = BSP_IO_PORT_06_PIN_02,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI)
+ },
+ {
+ .pin = BSP_IO_PORT_06_PIN_08,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+ },
+ {
+ .pin = BSP_IO_PORT_06_PIN_09,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_CAN)
+ },
+ {
+ .pin = BSP_IO_PORT_06_PIN_10,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_CAN)
+ },
+ {
+ .pin = BSP_IO_PORT_06_PIN_11,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+ },
+ {
+ .pin = BSP_IO_PORT_06_PIN_13,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI1_3_5_7_9)
+ },
+ {
+ .pin = BSP_IO_PORT_06_PIN_14,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI1_3_5_7_9)
+ },
+ {
+ .pin = BSP_IO_PORT_06_PIN_15,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_MID | (uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_HIGH)
+ },
+ {
+ .pin = BSP_IO_PORT_07_PIN_00,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_ETHER_RMII)
+ },
+ {
+ .pin = BSP_IO_PORT_07_PIN_01,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_ETHER_RMII)
+ },
+ {
+ .pin = BSP_IO_PORT_07_PIN_02,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_ETHER_RMII)
+ },
+ {
+ .pin = BSP_IO_PORT_07_PIN_03,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_ETHER_RMII)
+ },
+ {
+ .pin = BSP_IO_PORT_07_PIN_04,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_ETHER_RMII)
+ },
+ {
+ .pin = BSP_IO_PORT_07_PIN_05,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_ETHER_RMII)
+ },
+ {
+ .pin = BSP_IO_PORT_07_PIN_06,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_IRQ_ENABLE | (uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT)
+ },
+ {
+ .pin = BSP_IO_PORT_07_PIN_07,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_HS)
+ },
+ {
+ .pin = BSP_IO_PORT_07_PIN_08,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
+ },
+ {
+ .pin = BSP_IO_PORT_09_PIN_05,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_IRQ_ENABLE | (uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT | (uint32_t) IOPORT_CFG_PULLUP_ENABLE)
+ },
+ {
+ .pin = BSP_IO_PORT_11_PIN_00,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_HS)
+ },
+ {
+ .pin = BSP_IO_PORT_11_PIN_01,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_HS)
+ },
+};
+
+const ioport_cfg_t g_bsp_pin_cfg = {
+ .number_of_pins = sizeof(g_bsp_pin_cfg_data)/sizeof(ioport_pin_cfg_t),
+ .p_pin_cfg_data = &g_bsp_pin_cfg_data[0],
+};
+
+#if BSP_TZ_SECURE_BUILD
+
+void R_BSP_PinCfgSecurityInit(void);
+
+/* Initialize SAR registers for secure pins. */
+void R_BSP_PinCfgSecurityInit(void)
+{
+ #if (2U == BSP_FEATURE_IOPORT_VERSION)
+ uint32_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR];
+ #else
+ uint16_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR];
+ #endif
+ memset(pmsar, 0xFF, BSP_FEATURE_BSP_NUM_PMSAR * sizeof(R_PMISC->PMSAR[0]));
+
+
+ for(uint32_t i = 0; i < g_bsp_pin_cfg.number_of_pins; i++)
+ {
+ uint32_t port_pin = g_bsp_pin_cfg.p_pin_cfg_data[i].pin;
+ uint32_t port = port_pin >> 8U;
+ uint32_t pin = port_pin & 0xFFU;
+ pmsar[port] &= (uint16_t) ~(1U << pin);
+ }
+
+ for(uint32_t i = 0; i < BSP_FEATURE_BSP_NUM_PMSAR; i++)
+ {
+ #if (2U == BSP_FEATURE_IOPORT_VERSION)
+ R_PMISC->PMSAR[i].PMSAR = (uint16_t) pmsar[i];
+ #else
+ R_PMISC->PMSAR[i].PMSAR = pmsar[i];
+ #endif
+ }
+
+}
+#endif
diff --git a/hw/bsp/ra/boards/ra6m5_ek/script/fsp.ld b/hw/bsp/ra/boards/ra6m5_ek/script/fsp.ld
new file mode 100644
index 0000000000..605eef7d2c
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m5_ek/script/fsp.ld
@@ -0,0 +1,769 @@
+/*
+ Linker File for Renesas FSP
+*/
+
+INCLUDE memory_regions.ld
+
+/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/
+/*
+ XIP_SECONDARY_SLOT_IMAGE = 1;
+*/
+
+QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH);
+OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH);
+OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH);
+
+/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */
+__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0);
+
+ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0;
+ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0;
+DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0;
+DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0;
+RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0;
+RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0;
+RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH;
+RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH;
+
+OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80;
+
+/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings.
+ * Bootloader images do not configure option settings because they are owned by the bootloader.
+ * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */
+__bl_FSP_BOOTABLE_IMAGE = 1;
+__bln_FSP_BOOTABLE_IMAGE = 1;
+PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE);
+USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE);
+
+__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+ FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH :
+ (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH :
+ FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH;
+__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+ FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH;
+__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH;
+__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+ FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH;
+__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH;
+__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+ FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
+ __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH;
+__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+ FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
+ __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH;
+__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+ FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH :
+ RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH;
+__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+ FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH :
+ __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH;
+__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+ FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
+ __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2;
+__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START);
+__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+ FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
+ FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2;
+
+XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0;
+FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START :
+ XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START :
+ FLASH_IMAGE_START;
+LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH :
+ DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH :
+ FLASH_LENGTH;
+OPTION_SETTING_SAS_SIZE = 0x34;
+OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 :
+ OPTION_SETTING_LENGTH == 0 ? 0 :
+ OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE;
+
+/* Define memory regions. */
+MEMORY
+{
+ ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH
+ DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH
+ FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH
+ RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH
+ DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH
+ QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH
+ OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH
+ OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH
+ OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH
+ OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH
+ SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH
+ OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH
+ OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18
+ OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH
+ OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH
+ ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH
+}
+
+/* Library configurations */
+GROUP(libgcc.a libc.a libm.a)
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be DEFINED in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __copy_table_start__
+ * __copy_table_end__
+ * __zero_table_start__
+ * __zero_table_end__
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ * __Vectors_End
+ * __Vectors_Size
+ * __qspi_flash_start__
+ * __qspi_flash_end__
+ * __qspi_flash_code_size__
+ * __qspi_region_max_size__
+ * __qspi_region_start_address__
+ * __qspi_region_end_address__
+ * __ospi_device_0_start__
+ * __ospi_device_0_end__
+ * __ospi_device_0_code_size__
+ * __ospi_device_0_region_max_size__
+ * __ospi_device_0_region_start_address__
+ * __ospi_device_0_region_end_address__
+ * __ospi_device_1_start__
+ * __ospi_device_1_end__
+ * __ospi_device_1_code_size__
+ * __ospi_device_1_region_max_size__
+ * __ospi_device_1_region_start_address__
+ * __ospi_device_1_region_end_address__
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ __tz_FLASH_S = ABSOLUTE(FLASH_START);
+ __ROM_Start = .;
+
+ /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much
+ * space because ROM registers are at address 0x400 and there is very little space
+ * in between. */
+ KEEP(*(.fixed_vectors*))
+ KEEP(*(.application_vectors*))
+ __Vectors_End = .;
+
+ /* Some devices have a gap of code flash between the vector table and ROM Registers.
+ * The flash gap section allows applications to place code and data in this section. */
+ *(.flash_gap*)
+
+ /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */
+ . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400;
+ KEEP(*(.rom_registers*))
+
+ /* Reserving 0x100 bytes of space for ROM registers. */
+ . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x500;
+
+ /* Allocate flash write-boundary-aligned
+ * space for sce9 wrapped public keys for mcuboot if the module is used.
+ */
+ KEEP(*(.mcuboot_sce9_key*))
+
+ *(.text*)
+
+ KEEP(*(.version))
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+ __usb_dev_descriptor_start_fs = .;
+ KEEP(*(.usb_device_desc_fs*))
+ __usb_cfg_descriptor_start_fs = .;
+ KEEP(*(.usb_config_desc_fs*))
+ __usb_interface_descriptor_start_fs = .;
+ KEEP(*(.usb_interface_desc_fs*))
+ __usb_descriptor_end_fs = .;
+ __usb_dev_descriptor_start_hs = .;
+ KEEP(*(.usb_device_desc_hs*))
+ __usb_cfg_descriptor_start_hs = .;
+ KEEP(*(.usb_config_desc_hs*))
+ __usb_interface_descriptor_start_hs = .;
+ KEEP(*(.usb_interface_desc_hs*))
+ __usb_descriptor_end_hs = .;
+
+ KEEP(*(.eh_frame*))
+
+ __ROM_End = .;
+ } > FLASH = 0xFF
+
+ __Vectors_Size = __Vectors_End - __Vectors;
+
+ . = .;
+ __itcm_data_pre_location = .;
+
+ /* Initialized ITCM data. */
+ /* Aligned to FCACHE2 for RA8. */
+ .itcm_data : ALIGN(16)
+ {
+ /* Start of ITCM Secure Trustzone region. */
+ __tz_ITCM_S = ABSOLUTE(ITCM_START);
+
+ /* All ITCM data start */
+ __itcm_data_start = .;
+
+ KEEP(*(.itcm_data*))
+
+ /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */
+ . = ALIGN(8);
+
+ /* All ITCM data end */
+ __itcm_data_end = .;
+
+ /*
+ * Start of the ITCM Non-Secure Trustzone region.
+ * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects.
+ */
+ __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192);
+ } > ITCM AT > FLASH = 0x00
+
+ /* Addresses exported for ITCM initialization. */
+ __itcm_data_init_start = LOADADDR(.itcm_data);
+ __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data);
+
+ ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.")
+ ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.")
+ ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.")
+ ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.")
+
+ /* Restore location counter. */
+ /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */
+ /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */
+ . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location;
+
+ __exidx_start = .;
+ /DISCARD/ :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ }
+ __exidx_end = .;
+
+ /* To copy multiple ROM to RAM sections,
+ * uncomment .copy.table section and,
+ * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+ /*
+ .copy.table :
+ {
+ . = ALIGN(4);
+ __copy_table_start__ = .;
+ LONG (__etext)
+ LONG (__data_start__)
+ LONG (__data_end__ - __data_start__)
+ LONG (__etext2)
+ LONG (__data2_start__)
+ LONG (__data2_end__ - __data2_start__)
+ __copy_table_end__ = .;
+ } > FLASH
+ */
+
+ /* To clear multiple BSS sections,
+ * uncomment .zero.table section and,
+ * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+ /*
+ .zero.table :
+ {
+ . = ALIGN(4);
+ __zero_table_start__ = .;
+ LONG (__bss_start__)
+ LONG (__bss_end__ - __bss_start__)
+ LONG (__bss2_start__)
+ LONG (__bss2_end__ - __bss2_start__)
+ __zero_table_end__ = .;
+ } > FLASH
+ */
+
+ __etext = .;
+
+ __tz_RAM_S = ORIGIN(RAM);
+
+ /* If DTC is used, put the DTC vector table at the start of SRAM.
+ This avoids memory holes due to 1K alignment required by it. */
+ .fsp_dtc_vector_table (NOLOAD) :
+ {
+ . = ORIGIN(RAM);
+ *(.fsp_dtc_vector_table)
+ } > RAM
+
+ /* Initialized data section. */
+ .data :
+ {
+ __data_start__ = .;
+ . = ALIGN(4);
+
+ __Code_In_RAM_Start = .;
+
+ KEEP(*(.code_in_ram*))
+ __Code_In_RAM_End = .;
+
+ *(vtable)
+ /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */
+ *(.data.*)
+ *(.data)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+
+ . = ALIGN(4);
+
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM AT > FLASH
+
+ . = .;
+ __dtcm_data_pre_location = LOADADDR(.data) + SIZEOF(.data);
+
+ /* Initialized DTCM data. */
+ /* Aligned to FCACHE2 for RA8. */
+ .dtcm_data : ALIGN(16)
+ {
+ /* Start of DTCM Secure Trustzone region. */
+ __tz_DTCM_S = ABSOLUTE(DTCM_START);
+
+ /* Initialized DTCM data start */
+ __dtcm_data_start = .;
+
+ KEEP(*(.dtcm_data*))
+
+ /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */
+ . = ALIGN(8);
+
+ /* Initialized DTCM data end */
+ __dtcm_data_end = .;
+ } > DTCM AT > FLASH = 0x00
+
+ . = __dtcm_data_end;
+ /* Uninitialized DTCM data. */
+ /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */
+ .dtcm_bss ALIGN(8) (NOLOAD) :
+ {
+ /* Uninitialized DTCM data start */
+ __dtcm_bss_start = .;
+
+ KEEP(*(.dtcm_bss*))
+
+ /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */
+ . = ALIGN(8);
+
+ /* Uninitialized DTCM data end */
+ __dtcm_bss_end = .;
+
+ /*
+ * Start of the DTCM Non-Secure Trustzone region.
+ * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects.
+ */
+ __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192);
+ } > DTCM
+
+ /* Addresses exported for DTCM initialization. */
+ __dtcm_data_init_start = LOADADDR(.dtcm_data);
+ __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data);
+
+ ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.")
+ ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.")
+ ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).")
+ ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.")
+ ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.")
+ ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.")
+ ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.")
+ ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.")
+
+ /* Restore location counter. */
+ /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */
+ /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */
+ . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location;
+
+ /* TrustZone Secure Gateway Stubs Section */
+
+ /* Store location counter for SPI non-retentive sections. */
+ sgstubs_pre_location = .;
+
+ /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */
+ SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024);
+ .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024)
+ {
+ __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024);
+ _start_sg = .;
+ *(.gnu.sgstubs*)
+ . = ALIGN(32);
+ _end_sg = .;
+ } > FLASH
+
+ __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768);
+ FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N;
+
+ /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */
+ __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH);
+
+ /* QSPI_FLASH section to be downloaded via debugger */
+ .qspi_flash :
+ {
+ __qspi_flash_start__ = .;
+ KEEP(*(.qspi_flash*))
+ KEEP(*(.code_in_qspi*))
+ __qspi_flash_end__ = .;
+ } > QSPI_FLASH
+ __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__;
+
+ /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */
+ __qspi_flash_code_addr__ = sgstubs_pre_location;
+ .qspi_non_retentive : AT(__qspi_flash_code_addr__)
+ {
+ __qspi_non_retentive_start__ = .;
+ KEEP(*(.qspi_non_retentive*))
+ __qspi_non_retentive_end__ = .;
+ } > QSPI_FLASH
+ __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__;
+
+ __qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */
+ __qspi_region_start_address__ = __qspi_flash_start__;
+ __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__;
+
+ /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */
+ __tz_QSPI_FLASH_N = __qspi_non_retentive_end__;
+
+ /* Support for OctaRAM */
+ .OSPI_DEVICE_0_NO_LOAD (NOLOAD):
+ {
+ . = ALIGN(4);
+ __ospi_device_0_start__ = .;
+ *(.ospi_device_0_no_load*)
+ . = ALIGN(4);
+ __ospi_device_0_end__ = .;
+ } > OSPI_DEVICE_0_RAM
+
+ .OSPI_DEVICE_1_NO_LOAD (NOLOAD):
+ {
+ . = ALIGN(4);
+ __ospi_device_1_start__ = .;
+ *(.ospi_device_1_no_load*)
+ . = ALIGN(4);
+ __ospi_device_1_end__ = .;
+ } > OSPI_DEVICE_1_RAM
+
+ /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */
+ __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0);
+
+ /* OSPI_DEVICE_0 section to be downloaded via debugger */
+ .OSPI_DEVICE_0 :
+ {
+ __ospi_device_0_start__ = .;
+ KEEP(*(.ospi_device_0*))
+ KEEP(*(.code_in_ospi_device_0*))
+ __ospi_device_0_end__ = .;
+ } > OSPI_DEVICE_0
+ __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__;
+
+ /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */
+ __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive));
+ .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__)
+ {
+ __ospi_device_0_non_retentive_start__ = .;
+ KEEP(*(.ospi_device_0_non_retentive*))
+ __ospi_device_0_non_retentive_end__ = .;
+ } > OSPI_DEVICE_0
+ __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__;
+
+ __ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */
+ __ospi_device_0_region_start_address__ = __ospi_device_0_start__;
+ __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__;
+
+ /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */
+ __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__;
+
+ /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */
+ __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1);
+
+ /* OSPI_DEVICE_1 section to be downloaded via debugger */
+ .OSPI_DEVICE_1 :
+ {
+ __ospi_device_1_start__ = .;
+ KEEP(*(.ospi_device_1*))
+ KEEP(*(.code_in_ospi_device_1*))
+ __ospi_device_1_end__ = .;
+ } > OSPI_DEVICE_1
+ __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__;
+
+ /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */
+ __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive));
+ .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__)
+ {
+ __ospi_device_1_non_retentive_start__ = .;
+ KEEP(*(.ospi_device_1_non_retentive*))
+ __ospi_device_1_non_retentive_end__ = .;
+ } > OSPI_DEVICE_1
+ __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__;
+
+ __ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */
+ __ospi_device_1_region_start_address__ = __ospi_device_1_start__;
+ __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__;
+
+ /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */
+ __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__;
+
+ .noinit (NOLOAD):
+ {
+ . = ALIGN(4);
+ __noinit_start = .;
+ KEEP(*(.noinit*))
+ . = ALIGN(8);
+ /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */
+ KEEP(*(.heap.*))
+ __noinit_end = .;
+ } > RAM
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } > RAM
+
+ .heap (NOLOAD):
+ {
+ . = ALIGN(8);
+ __HeapBase = .;
+ /* Place the STD heap here. */
+ KEEP(*(.heap))
+ __HeapLimit = .;
+ } > RAM
+
+ /* Stacks are stored in this section. */
+ .stack_dummy (NOLOAD):
+ {
+ . = ALIGN(8);
+ __StackLimit = .;
+ /* Main stack */
+ KEEP(*(.stack))
+ __StackTop = .;
+ /* Thread stacks */
+ KEEP(*(.stack*))
+ __StackTopAll = .;
+ } > RAM
+
+ PROVIDE(__stack = __StackTopAll);
+
+ /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used
+ at run time for things such as ThreadX memory pool allocations. */
+ __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4);
+
+ /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects.
+ * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary.
+ * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */
+ __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024);
+
+ /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects.
+ * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not
+ * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary.
+ * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */
+ __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192);
+
+ /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects.
+ * The EDMAC is a non-secure bus master and can only access non-secure RAM. */
+ .ns_buffer (NOLOAD):
+ {
+ /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */
+ . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .;
+
+ KEEP(*(.ns_buffer*))
+ } > RAM
+
+ /* Data flash. */
+ .data_flash :
+ {
+ . = ORIGIN(DATA_FLASH);
+ __tz_DATA_FLASH_S = .;
+ __Data_Flash_Start = .;
+ KEEP(*(.data_flash*))
+ __Data_Flash_End = .;
+
+ __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024);
+ } > DATA_FLASH
+
+ /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */
+ __tz_SDRAM_S = ORIGIN(SDRAM);
+
+ /* SDRAM */
+ .sdram (NOLOAD):
+ {
+ __SDRAM_Start = .;
+ KEEP(*(.sdram*))
+ KEEP(*(.frame*))
+ __SDRAM_End = .;
+ } > SDRAM
+
+ /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */
+ __tz_SDRAM_N = __SDRAM_End;
+
+ /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */
+ __tz_ID_CODE_S = ORIGIN(ID_CODE);
+
+ /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool.
+ * Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE
+ * memory region between TrustZone projects. */
+ __tz_ID_CODE_N = __tz_ID_CODE_S;
+
+ .id_code :
+ {
+ __ID_Code_Start = .;
+ KEEP(*(.id_code*))
+ __ID_Code_End = .;
+ } > ID_CODE
+
+ /* Symbol required for RA Configuration tool. */
+ __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS);
+
+ .option_setting_ofs :
+ {
+ __OPTION_SETTING_OFS_Start = .;
+ KEEP(*(.option_setting_ofs0))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start;
+ KEEP(*(.option_setting_ofs2))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start;
+ KEEP(*(.option_setting_dualsel))
+ __OPTION_SETTING_OFS_End = .;
+ } > OPTION_SETTING_OFS = 0xFF
+
+ .option_setting_sas :
+ {
+ __OPTION_SETTING_SAS_Start = .;
+ KEEP(*(.option_setting_sas))
+ __OPTION_SETTING_SAS_End = .;
+ } > OPTION_SETTING_SAS = 0xFF
+
+ /* Symbol required for RA Configuration tool. */
+ __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS);
+
+ .option_setting_ns :
+ {
+ __OPTION_SETTING_NS_Start = .;
+ KEEP(*(.option_setting_ofs1))
+ . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start;
+ KEEP(*(.option_setting_ofs3))
+ . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start;
+ KEEP(*(.option_setting_banksel))
+ . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start;
+ KEEP(*(.option_setting_bps0))
+ . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start;
+ KEEP(*(.option_setting_bps1))
+ . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start;
+ KEEP(*(.option_setting_bps2))
+ . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start;
+ KEEP(*(.option_setting_bps3))
+ . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start;
+ KEEP(*(.option_setting_pbps0))
+ . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start;
+ KEEP(*(.option_setting_pbps1))
+ . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start;
+ KEEP(*(.option_setting_pbps2))
+ . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start;
+ KEEP(*(.option_setting_pbps3))
+ __OPTION_SETTING_NS_End = .;
+ } > OPTION_SETTING = 0xFF
+
+ /* Symbol required for RA Configuration tool. */
+ __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S);
+
+ .option_setting_s :
+ {
+ __OPTION_SETTING_S_Start = .;
+ KEEP(*(.option_setting_ofs1_sec))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_ofs3_sec))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_banksel_sec))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_bps_sec0))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_bps_sec1))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_bps_sec2))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_bps_sec3))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_pbps_sec0))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_pbps_sec1))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_pbps_sec2))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_pbps_sec3))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_ofs1_sel))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_ofs3_sel))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_banksel_sel))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_bps_sel0))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_bps_sel1))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_bps_sel2))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_bps_sel3))
+ __OPTION_SETTING_S_End = .;
+ } > OPTION_SETTING_S = 0xFF
+
+ /* Symbol required for RA Configuration tool. */
+ __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End;
+}
diff --git a/hw/bsp/ra/boards/ra6m5_ek/script/memory_regions.ld b/hw/bsp/ra/boards/ra6m5_ek/script/memory_regions.ld
new file mode 100644
index 0000000000..19864683f4
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m5_ek/script/memory_regions.ld
@@ -0,0 +1,22 @@
+
+ /* generated memory regions file - do not edit */
+ RAM_START = 0x20000000;
+ RAM_LENGTH = 0x80000;
+ FLASH_START = 0x00000000;
+ FLASH_LENGTH = 0x200000;
+ DATA_FLASH_START = 0x08000000;
+ DATA_FLASH_LENGTH = 0x2000;
+ OPTION_SETTING_START = 0x0100A100;
+ OPTION_SETTING_LENGTH = 0x100;
+ OPTION_SETTING_S_START = 0x0100A200;
+ OPTION_SETTING_S_LENGTH = 0x100;
+ ID_CODE_START = 0x00000000;
+ ID_CODE_LENGTH = 0x0;
+ SDRAM_START = 0x80010000;
+ SDRAM_LENGTH = 0x0;
+ QSPI_FLASH_START = 0x60000000;
+ QSPI_FLASH_LENGTH = 0x4000000;
+ OSPI_DEVICE_0_START = 0x68000000;
+ OSPI_DEVICE_0_LENGTH = 0x8000000;
+ OSPI_DEVICE_1_START = 0x70000000;
+ OSPI_DEVICE_1_LENGTH = 0x10000000;
diff --git a/hw/bsp/ra/boards/ra6m5_ek/smart_configurator/configuration.xml b/hw/bsp/ra/boards/ra6m5_ek/smart_configurator/configuration.xml
new file mode 100644
index 0000000000..4544d0f2a7
--- /dev/null
+++ b/hw/bsp/ra/boards/ra6m5_ek/smart_configurator/configuration.xml
@@ -0,0 +1,670 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
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+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Simple application that blinks an LED. No RTOS included.
+ Renesas.RA_baremetal_blinky.5.6.0.pack
+
+
+ Board Support Package Common Files
+ Renesas.RA.5.6.0.pack
+
+
+ I/O Port
+ Renesas.RA.5.6.0.pack
+
+
+ Arm CMSIS Version 6 - Core (M)
+ Arm.CMSIS6.6.1.0+fsp.5.6.0.pack
+
+
+ RA6M5-EK Board Support Files
+ Renesas.RA_board_ra6m5_ek.5.6.0.pack
+
+
+ Board support package for R7FA6M5BH3CFC
+ Renesas.RA_mcu_ra6m5.5.6.0.pack
+
+
+ Board support package for RA6M5
+ Renesas.RA_mcu_ra6m5.5.6.0.pack
+
+
+ Board support package for RA6M5 - FSP Data
+ Renesas.RA_mcu_ra6m5.5.6.0.pack
+
+
+ Board support package for RA6M5 - Events
+ Renesas.RA_mcu_ra6m5.5.6.0.pack
+
+
+
+
+
+
+
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+
diff --git a/hw/bsp/ra/boards/ra8m1_ek/board.cmake b/hw/bsp/ra/boards/ra8m1_ek/board.cmake
new file mode 100644
index 0000000000..9c797c3b7c
--- /dev/null
+++ b/hw/bsp/ra/boards/ra8m1_ek/board.cmake
@@ -0,0 +1,16 @@
+set(CMAKE_SYSTEM_PROCESSOR cortex-m85 CACHE INTERNAL "System Processor")
+set(MCU_VARIANT ra8m1)
+
+set(JLINK_DEVICE R7FA8M1AH)
+#set(JLINK_OPTION "-USB 001083115236")
+
+# device default to PORT 1 High Speed
+if (NOT DEFINED RHPORT_DEVICE)
+ set(RHPORT_DEVICE 1)
+endif()
+if (NOT DEFINED RHPORT_HOST)
+ set(RHPORT_HOST 0)
+endif()
+
+function(update_board TARGET)
+endfunction()
diff --git a/hw/bsp/ra/boards/ra8m1_ek/board.h b/hw/bsp/ra/boards/ra8m1_ek/board.h
new file mode 100644
index 0000000000..33dda99b4f
--- /dev/null
+++ b/hw/bsp/ra/boards/ra8m1_ek/board.h
@@ -0,0 +1,42 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2023 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define LED_STATE_ON 1
+#define BUTTON_STATE_ACTIVE 0
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/hw/bsp/ra/boards/ra8m1_ek/board.mk b/hw/bsp/ra/boards/ra8m1_ek/board.mk
new file mode 100644
index 0000000000..2e56b37812
--- /dev/null
+++ b/hw/bsp/ra/boards/ra8m1_ek/board.mk
@@ -0,0 +1,11 @@
+CPU_CORE = cortex-m85
+MCU_VARIANT = ra8m1
+
+# For flash-jlink target
+JLINK_DEVICE = R7FA8M1AH
+
+# Port 1 is highspeed
+RHPORT_DEVICE ?= 1
+RHPORT_HOST ?= 0
+
+flash: flash-jlink
diff --git a/hw/bsp/ra/boards/ra8m1_ek/ozone/Renesas_RA8_TracePins.pex b/hw/bsp/ra/boards/ra8m1_ek/ozone/Renesas_RA8_TracePins.pex
new file mode 100644
index 0000000000..70dd323ecb
Binary files /dev/null and b/hw/bsp/ra/boards/ra8m1_ek/ozone/Renesas_RA8_TracePins.pex differ
diff --git a/hw/bsp/ra/boards/ra8m1_ek/ozone/ra8m1.jdebug b/hw/bsp/ra/boards/ra8m1_ek/ozone/ra8m1.jdebug
new file mode 100644
index 0000000000..242a15db9a
--- /dev/null
+++ b/hw/bsp/ra/boards/ra8m1_ek/ozone/ra8m1.jdebug
@@ -0,0 +1,231 @@
+
+/*********************************************************************
+*
+* OnProjectLoad
+*
+* Function description
+* Project load routine. Required.
+*
+**********************************************************************
+*/
+void OnProjectLoad (void) {
+ Project.SetTraceSource ("Trace Pins");
+ Project.SetDevice ("R7FA8M1AH");
+ Project.SetHostIF ("USB", "");
+ Project.SetTargetIF ("SWD");
+ Project.SetTIFSpeed ("50 MHz");
+
+ Project.AddSvdFile ("$(InstallDir)/Config/CPU/Cortex-M85F.svd");
+ Project.AddSvdFile ("../../../../../../../cmsis-svd-data/data/Renesas/R7FA6M5BH.svd");
+
+ File.Open ("../../../../../../examples/cmake-build-ra8m1_ek/device/cdc_msc/cdc_msc.elf");
+}
+/*********************************************************************
+*
+* BeforeTargetConnect
+*
+* Function description
+* Event handler routine. Optional.
+*
+**********************************************************************
+*/
+void BeforeTargetConnect (void) {
+ // Trace pin init is done by J-Link script file as J-Link script files are IDE independent
+ //Project.SetJLinkScript("../../../debug.jlinkscript");
+ Project.SetJLinkScript ("$(ProjectDir)/Renesas_RA8_TracePins.pex");
+}
+
+/*********************************************************************
+*
+* AfterTargetConnect
+*
+* Function description
+* Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void AfterTargetConnect (void) {
+//}
+
+/*********************************************************************
+*
+* TargetDownload
+*
+* Function description
+* Replaces the default program download routine. Optional.
+*
+**********************************************************************
+*/
+//void TargetDownload (void) {
+//}
+
+/*********************************************************************
+*
+* BeforeTargetDownload
+*
+* Function description
+* Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void BeforeTargetDownload (void) {
+//}
+
+/*********************************************************************
+*
+* AfterTargetDownload
+*
+* Function description
+* Event handler routine. Optional.
+* The default implementation initializes SP and PC to reset values.
+*
+**********************************************************************
+*/
+void AfterTargetDownload (void) {
+ _SetupTarget();
+}
+
+/*********************************************************************
+*
+* BeforeTargetDisconnect
+*
+* Function description
+* Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void BeforeTargetDisconnect (void) {
+//}
+
+/*********************************************************************
+*
+* AfterTargetDisconnect
+*
+* Function description
+* Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void AfterTargetDisconnect (void) {
+//}
+
+/*********************************************************************
+*
+* AfterTargetHalt
+*
+* Function description
+* Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void AfterTargetHalt (void) {
+//}
+
+/*********************************************************************
+*
+* BeforeTargetResume
+*
+* Function description
+* Event handler routine. Optional.
+*
+**********************************************************************
+*/
+//void BeforeTargetResume (void) {
+//}
+
+/*********************************************************************
+*
+* OnSnapshotLoad
+*
+* Function description
+* Called upon loading a snapshot. Optional.
+*
+* Additional information
+* This function is used to restore the target state in cases
+* where values cannot simply be written to the target.
+* Typical use: GPIO clock needs to be enabled, before
+* GPIO is configured.
+*
+**********************************************************************
+*/
+//void OnSnapshotLoad (void) {
+//}
+
+/*********************************************************************
+*
+* OnSnapshotSave
+*
+* Function description
+* Called upon saving a snapshot. Optional.
+*
+* Additional information
+* This function is usually used to save values of the target
+* state which can either not be trivially read,
+* or need to be restored in a specific way or order.
+* Typically use: Memory Mapped Registers,
+* such as PLL and GPIO configuration.
+*
+**********************************************************************
+*/
+//void OnSnapshotSave (void) {
+//}
+
+/*********************************************************************
+*
+* OnError
+*
+* Function description
+* Called when an error occurred. Optional.
+*
+**********************************************************************
+*/
+//void OnError (void) {
+//}
+
+/*********************************************************************
+*
+* AfterProjectLoad
+*
+* Function description
+* After Project load routine. Optional.
+*
+**********************************************************************
+*/
+//void AfterProjectLoad (void) {
+//}
+
+/*********************************************************************
+*
+* _SetupTarget
+*
+* Function description
+* Setup the target.
+* Called by AfterTargetReset() and AfterTargetDownload().
+*
+* Auto-generated function. May be overridden by Ozone.
+*
+**********************************************************************
+*/
+void _SetupTarget(void) {
+ unsigned int SP;
+ unsigned int PC;
+ unsigned int VectorTableAddr;
+
+ VectorTableAddr = Elf.GetBaseAddr();
+ //
+ // Set up initial stack pointer
+ //
+ SP = Target.ReadU32(VectorTableAddr);
+ if (SP != 0xFFFFFFFF) {
+ Target.SetReg("SP", SP);
+ }
+ //
+ // Set up entry point PC
+ //
+ PC = Elf.GetEntryPointPC();
+ if (PC != 0xFFFFFFFF) {
+ Target.SetReg("PC", PC);
+ } else {
+ Util.Error("Project script error: failed to set up entry point PC", 1);
+ }
+}
diff --git a/hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h
new file mode 100644
index 0000000000..90afbdef3d
--- /dev/null
+++ b/hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h
@@ -0,0 +1,62 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_CFG_H_
+#define BSP_CFG_H_
+#ifdef __cplusplus
+ extern "C" {
+ #endif
+
+ #include "bsp_clock_cfg.h"
+ #include "bsp_mcu_family_cfg.h"
+ #include "board_cfg.h"
+ #define RA_NOT_DEFINED 0
+ #ifndef BSP_CFG_RTOS
+ #if (RA_NOT_DEFINED) != (RA_NOT_DEFINED)
+ #define BSP_CFG_RTOS (2)
+ #elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED)
+ #define BSP_CFG_RTOS (1)
+ #else
+ #define BSP_CFG_RTOS (0)
+ #endif
+ #endif
+ #ifndef BSP_CFG_RTC_USED
+ #define BSP_CFG_RTC_USED (RA_NOT_DEFINED)
+ #endif
+ #undef RA_NOT_DEFINED
+ #if defined(_RA_BOOT_IMAGE)
+ #define BSP_CFG_BOOT_IMAGE (1)
+ #endif
+ #define BSP_CFG_MCU_VCC_MV (3300)
+ #define BSP_CFG_STACK_MAIN_BYTES (0x1000)
+ #define BSP_CFG_HEAP_BYTES (0x1000)
+ #define BSP_CFG_PARAM_CHECKING_ENABLE (0)
+ #define BSP_CFG_ASSERT (0)
+ #define BSP_CFG_ERROR_LOG (0)
+
+ #define BSP_CFG_PFS_PROTECT ((1))
+
+ #define BSP_CFG_C_RUNTIME_INIT ((1))
+ #define BSP_CFG_EARLY_INIT ((0))
+
+ #define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0))
+
+ #ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED
+ #define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1)
+ #endif
+
+ #ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE
+ #define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0)
+ #endif
+ #ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE
+ #define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0)
+ #endif
+ #ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED
+ #define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1)
+ #endif
+ #ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS
+ #define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
+ #endif
+
+ #ifdef __cplusplus
+ }
+ #endif
+#endif /* BSP_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h b/hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h
new file mode 100644
index 0000000000..92e7ddcdb6
--- /dev/null
+++ b/hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h
@@ -0,0 +1,5 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_MCU_DEVICE_CFG_H_
+#define BSP_MCU_DEVICE_CFG_H_
+#define BSP_CFG_MCU_PART_SERIES (8)
+#endif /* BSP_MCU_DEVICE_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
new file mode 100644
index 0000000000..a22da075de
--- /dev/null
+++ b/hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
@@ -0,0 +1,11 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_MCU_DEVICE_PN_CFG_H_
+#define BSP_MCU_DEVICE_PN_CFG_H_
+#define BSP_MCU_R7FA8M1AHECBD
+ #define BSP_MCU_FEATURE_SET ('A')
+ #define BSP_ROM_SIZE_BYTES (2064384)
+ #define BSP_RAM_SIZE_BYTES (917504)
+ #define BSP_DATA_FLASH_SIZE_BYTES (12288)
+ #define BSP_PACKAGE_BGA
+ #define BSP_PACKAGE_PINS (224)
+#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h
new file mode 100644
index 0000000000..94f09c61fb
--- /dev/null
+++ b/hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h
@@ -0,0 +1,526 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_MCU_FAMILY_CFG_H_
+#define BSP_MCU_FAMILY_CFG_H_
+#include "bsp_mcu_device_pn_cfg.h"
+ #include "bsp_mcu_device_cfg.h"
+ #include "../../../ra/fsp/src/bsp/mcu/ra8m1/bsp_override.h"
+ #include "../../../ra/fsp/src/bsp/mcu/ra8m1/bsp_mcu_info.h"
+ #include "bsp_clock_cfg.h"
+ #define BSP_MCU_GROUP_RA8M1 (1)
+ #define BSP_LOCO_HZ (32768)
+ #define BSP_MOCO_HZ (8000000)
+ #define BSP_SUB_CLOCK_HZ (0)
+ #if BSP_CFG_HOCO_FREQUENCY == 0
+ #define BSP_HOCO_HZ (16000000)
+ #elif BSP_CFG_HOCO_FREQUENCY == 1
+ #define BSP_HOCO_HZ (18000000)
+ #elif BSP_CFG_HOCO_FREQUENCY == 2
+ #define BSP_HOCO_HZ (20000000)
+ #elif BSP_CFG_HOCO_FREQUENCY == 4
+ #define BSP_HOCO_HZ (32000000)
+ #elif BSP_CFG_HOCO_FREQUENCY == 7
+ #define BSP_HOCO_HZ (48000000)
+ #else
+ #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h"
+ #endif
+
+ #define BSP_CFG_FLL_ENABLE (0)
+
+ #define BSP_CFG_CLOCK_SETTLING_DELAY_ENABLE (1)
+ #define BSP_CFG_SLEEP_MODE_DELAY_ENABLE (1)
+ #define BSP_CFG_MSTP_CHANGE_DELAY_ENABLE (1)
+ #define BSP_CFG_RTOS_IDLE_SLEEP (0)
+ #define BSP_CFG_CLOCK_SETTLING_DELAY_US (150)
+
+ #if defined(BSP_PACKAGE_LQFP) && (BSP_PACKAGE_PINS == 100)
+ #define BSP_MAX_CLOCK_CHANGE_THRESHOLD (180000000U)
+ #elif defined(BSP_PACKAGE_LQFP)
+ #define BSP_MAX_CLOCK_CHANGE_THRESHOLD (200000000U)
+ #else
+ #define BSP_MAX_CLOCK_CHANGE_THRESHOLD (240000000U)
+ #endif
+
+ #define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U)
+ #define BSP_VECTOR_TABLE_MAX_ENTRIES (112U)
+ #define BSP_CFG_INLINE_IRQ_FUNCTIONS (1)
+
+ #if defined(_RA_TZ_SECURE)
+ #define BSP_TZ_SECURE_BUILD (1)
+ #define BSP_TZ_NONSECURE_BUILD (0)
+ #elif defined(_RA_TZ_NONSECURE)
+ #define BSP_TZ_SECURE_BUILD (0)
+ #define BSP_TZ_NONSECURE_BUILD (1)
+ #else
+ #define BSP_TZ_SECURE_BUILD (0)
+ #define BSP_TZ_NONSECURE_BUILD (0)
+ #endif
+
+ /* TrustZone Settings */
+ #define BSP_TZ_CFG_INIT_SECURE_ONLY (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE))
+ #define BSP_TZ_CFG_SKIP_INIT (BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_INIT_SECURE_ONLY)
+ #define BSP_TZ_CFG_EXCEPTION_RESPONSE (0)
+
+ /* CMSIS TrustZone Settings */
+ #define SCB_CSR_AIRCR_INIT (1)
+ #define SCB_AIRCR_BFHFNMINS_VAL (0)
+ #define SCB_AIRCR_SYSRESETREQS_VAL (1)
+ #define SCB_AIRCR_PRIS_VAL (0)
+ #define TZ_FPU_NS_USAGE (1)
+#ifndef SCB_NSACR_CP10_11_VAL
+ #define SCB_NSACR_CP10_11_VAL (3U)
+#endif
+
+#ifndef FPU_FPCCR_TS_VAL
+ #define FPU_FPCCR_TS_VAL (1U)
+#endif
+ #define FPU_FPCCR_CLRONRETS_VAL (1)
+
+#ifndef FPU_FPCCR_CLRONRET_VAL
+ #define FPU_FPCCR_CLRONRET_VAL (1)
+#endif
+
+ /* Type 1 Peripheral Security Attribution */
+
+ /* Peripheral Security Attribution Register (PSAR) Settings */
+#ifndef BSP_TZ_CFG_PSARB
+#define BSP_TZ_CFG_PSARB (\
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4) /* I3C */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* IIC1 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9) /* IIC0 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* USBFS */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* USBHS */ | \
+ (1 << 15) /* ETHERC/EDMAC */ | \
+ (1 << 16) /* OSPI */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 18) /* SPI1 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 19) /* SPI0 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* SCI9 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* SCI4 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* SCI3 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* SCI2 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* SCI1 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCI0 */)
+#endif
+#ifndef BSP_TZ_CFG_PSARC
+#define BSP_TZ_CFG_PSARC (\
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* CAC */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CRC */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7) /* SSIE1 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* SSIE0 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* SDHI1 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* SDHI0 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* DOC */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 16) /* CEU */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* CANFD1 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* CANFD0 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* RSIP-E51A */)
+#endif
+#ifndef BSP_TZ_CFG_PSARD
+#define BSP_TZ_CFG_PSARD (\
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4) /* AGT1 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5) /* AGT0 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* POEG3 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* POEG2 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* POEG1 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* POEG0 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* ADC121 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 16) /* ADC120 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 20) /* DAC120 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* TSN */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* ACMPHS1 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* ACMPHS0 */)
+#endif
+#ifndef BSP_TZ_CFG_PSARE
+#define BSP_TZ_CFG_PSARE (\
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* WDT */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* IWDT */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* RTC */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* ULPT1 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9) /* ULPT0 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 18) /* GPT13 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 19) /* GPT12 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 20) /* GPT11 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 21) /* GPT10 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* GPT9 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* GPT8 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* GPT7 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* GPT6 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* GPT5 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* GPT4 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* GPT3 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* GPT2 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* GPT1 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* GPT0 */)
+#endif
+#ifndef BSP_TZ_CFG_MSSAR
+#define BSP_TZ_CFG_MSSAR (\
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* DTC_DMAC */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* ELC */)
+#endif
+
+ /* Type 2 Peripheral Security Attribution */
+
+ /* Security attribution for RSTSRn registers. */
+#ifndef BSP_TZ_CFG_RSTSAR
+#define BSP_TZ_CFG_RSTSAR (0x00000007U)
+#endif
+
+ /* Security attribution for registers of LVD channels. */
+#ifndef BSP_TZ_CFG_LVDSAR
+ /* The LVD driver needs to access both channels. This means that the security attribution for both channels must be the same. */
+#if (RA_NOT_DEFINED > 0) || (RA_NOT_DEFINED > 0)
+#define BSP_TZ_CFG_LVDSAR (0U)
+#else
+#define BSP_TZ_CFG_LVDSAR (3U)
+#endif
+#endif
+
+ /* Security attribution for LPM registers.
+ * - OPCCR based on clock security.
+ * - Set remaining registers based on LPM security.
+ */
+#ifndef BSP_TZ_CFG_LPMSAR
+#define BSP_TZ_CFG_LPMSAR ((RA_NOT_DEFINED > 0) ? BSP_CFG_CLOCKS_SECURE == 0 : (\
+ 0x002E0106U | \
+ (BSP_CFG_CLOCKS_SECURE == 0)))
+#endif
+ /* Deep Standby Interrupt Factor Security Attribution Register. */
+#ifndef BSP_TZ_CFG_DPFSAR
+#define BSP_TZ_CFG_DPFSAR ((RA_NOT_DEFINED > 0) ? 0U : 0xAF1FFFFFU)
+#endif
+ /* RAM Standby Control Security Attribution Register. */
+#ifndef BSP_TZ_CFG_RSCSAR
+#define BSP_TZ_CFG_RSCSAR ((RA_NOT_DEFINED > 0) ? 0U : 0x00037FFFU)
+#endif
+
+ /* Security attribution for CGC registers. */
+#ifndef BSP_TZ_CFG_CGFSAR
+#if BSP_CFG_CLOCKS_SECURE
+/* Protect all CGC registers from Non-secure write access. */
+#define BSP_TZ_CFG_CGFSAR (0U)
+#else
+/* Allow Secure and Non-secure write access. */
+#define BSP_TZ_CFG_CGFSAR (0x047F3BFDU)
+#endif
+#endif
+
+ /* Security attribution for Battery Backup registers. */
+#ifndef BSP_TZ_CFG_BBFSAR
+#if 0
+#define BSP_TZ_CFG_BBFSAR (0U)
+#else
+#define BSP_TZ_CFG_BBFSAR (0x1FU)
+#endif
+#endif
+
+ /* Security attribution for Battery Backup registers (VBTBKRn). */
+#ifndef BSP_TZ_CFG_VBRSABAR
+#if 0
+#define BSP_TZ_CFG_VBRSABAR (0xFFE0)
+#else
+#define BSP_TZ_CFG_VBRSABAR (0xED00)
+#endif
+#endif
+
+ /* Security attribution for registers for IRQ channels. */
+#ifndef BSP_TZ_CFG_ICUSARA
+#define BSP_TZ_CFG_ICUSARA (\
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* External IRQ1 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* External IRQ2 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* External IRQ3 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* External IRQ4 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* External IRQ5 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* External IRQ6 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* External IRQ7 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8U) /* External IRQ8 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9U) /* External IRQ9 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 10U) /* External IRQ10 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11U) /* External IRQ11 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12U) /* External IRQ12 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13U) /* External IRQ13 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14U) /* External IRQ14 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15U) /* External IRQ15 */)
+#endif
+
+ /* Security attribution for NMI registers. */
+#ifndef BSP_TZ_CFG_ICUSARB
+#define BSP_TZ_CFG_ICUSARB (0 | 0U) /* Should match AIRCR.BFHFNMINS. */
+#endif
+
+ /* Security attribution for registers for DMAC channels */
+#ifndef BSP_TZ_CFG_DMACCHSAR
+#define BSP_TZ_CFG_DMACCHSAR (\
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* DMAC Channel 0 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* DMAC Channel 1 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* DMAC Channel 2 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* DMAC Channel 3 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* DMAC Channel 4 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* DMAC Channel 5 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* DMAC Channel 6 */ | \
+ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* DMAC Channel 7 */)
+#endif
+
+ /* Security attribution registers for WUPEN0. */
+#ifndef BSP_TZ_CFG_ICUSARE
+#define BSP_TZ_CFG_ICUSARE ((RA_NOT_DEFINED > 0) ? 0U : 0xFF1D0000U)
+#endif
+
+ /* Security attribution registers for WUPEN1. */
+#ifndef BSP_TZ_CFG_ICUSARF
+#define BSP_TZ_CFG_ICUSARF ((RA_NOT_DEFINED > 0) ? 0U : 0x00007F08U)
+#endif
+
+ /* Trusted Event Route Control Register for IELSR, DMAC.DELSR and ELC.ELSR. Note that currently Trusted Event Route Control is not supported. */
+#ifndef BSP_TZ_CFG_TEVTRCR
+#define BSP_TZ_CFG_TEVTRCR (0)
+#endif
+
+ /* Security attribution register for ELCR, ELSEGR0, ELSEGR1 Security Attribution. */
+#ifndef BSP_TZ_CFG_ELCSARA
+ #define BSP_TZ_CFG_ELCSARA (0x00000007U)
+#endif
+
+ /* Set DTCSTSAR if the Secure program uses the DTC. */
+#if RA_NOT_DEFINED == RA_NOT_DEFINED
+ #define BSP_TZ_CFG_DTC_USED (0U)
+#else
+ #define BSP_TZ_CFG_DTC_USED (1U)
+#endif
+
+ /* Security attribution of FLWT and FCKMHZ registers. */
+#ifndef BSP_TZ_CFG_FSAR
+/* If the CGC registers are only accessible in Secure mode, than there is no
+ * reason for nonsecure applications to access FLWT and FCKMHZ. */
+#define BSP_TZ_CFG_FSAR (\
+ ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 0) : 0U) | /* FLWTSA */\
+ ((RA_NOT_DEFINED) > 0 ? 0U: (1U << 1)) | /* FCACHESA */\
+ ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 8) : 0U) | /* FCKMHZSA */ \
+ ((RA_NOT_DEFINED) > 0 ? 0U : (1U << 9U)) | /* FACICMISA */\
+ ((RA_NOT_DEFINED) > 0 ? 0U: (1U << 10U)) /* FACICMRSA */)
+#endif
+
+ /* Security attribution for SRAM registers. */
+#ifndef BSP_TZ_CFG_SRAMSAR
+/* If the CGC registers are only accessible in Secure mode, than there is no reason for Non Secure applications to access
+ * SRAM0WTEN and therefore there is no reason to access PRCR2. */
+ #define BSP_TZ_CFG_SRAMSAR (\
+ ((1U) << 0U) | /* SRAMSA0 */\
+ ((1U) << 1U) | /* SRAMSA1 */\
+ ((1U) << 7U) | /* STBRAMSA */\
+ ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 8U) : 0U) /* SRAMWTSA */)
+#endif
+
+ /* Security attribution for the DMAC Bus Master MPU settings. */
+#ifndef BSP_TZ_CFG_MMPUSARA
+ /* The DMAC Bus Master MPU settings should align with the DMAC channel settings. */
+ #define BSP_TZ_CFG_MMPUSARA (BSP_TZ_CFG_DMACCHSAR)
+#endif
+
+ /* Security Attribution Register A for BUS Control registers. */
+#ifndef BSP_TZ_CFG_BUSSARA
+ #define BSP_TZ_CFG_BUSSARA (1U)
+#endif
+ /* Security Attribution Register B for BUS Control registers. */
+#ifndef BSP_TZ_CFG_BUSSARB
+ #define BSP_TZ_CFG_BUSSARB (1U)
+#endif
+ /* Security Attribution Register C for BUS Control registers. */
+#ifndef BSP_TZ_CFG_BUSSARC
+ #define BSP_TZ_CFG_BUSSARC (1U)
+#endif
+
+ /* Enable Uninitialized Non-Secure Application Fallback. */
+#ifndef BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK
+ #define BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK (1U)
+#endif
+
+
+ #define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2)
+ #define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10)
+ #define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17)
+ #define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26)
+ #define OFS_SEQ5 (1 << 28) | (1 << 30)
+ #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
+
+ #define BSP_CFG_ROM_REG_OFS2 ((1 << 0) | 0xFFFFFFFEU)
+
+ /* Option Function Select Register 1 Security Attribution */
+#ifndef BSP_CFG_ROM_REG_OFS1_SEL
+#if defined(_RA_TZ_SECURE) || defined(_RA_TZ_NONSECURE)
+ #define BSP_CFG_ROM_REG_OFS1_SEL (0x00000000U | ((0U << 0U)) | ((0U << 3U)) | ((0U << 5U)) | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0xF00U : 0U) | ((0U << 24U)) | ((0U << 25U)))
+#else
+ #define BSP_CFG_ROM_REG_OFS1_SEL (0x00000000U)
+#endif
+#endif
+ #define BSP_CFG_ROM_REG_OFS1_INITECCEN (0 << 25)
+ #define BSP_CFG_ROM_REG_OFS1 (0xFCFFFED0 | (1 << 3) | (7) | (1 << 5) | (1 << 8) | (1 << 24) | (BSP_CFG_ROM_REG_OFS1_INITECCEN))
+
+ /* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */
+ #define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector)
+
+ /* Dual Mode Select Register */
+#ifndef BSP_CFG_ROM_REG_DUALSEL
+ #define BSP_CFG_ROM_REG_DUALSEL (0xFFFFFFF8U | (0x7U))
+#endif
+
+ /* Block Protection Register 0 */
+#ifndef BSP_CFG_ROM_REG_BPS0
+ #define BSP_CFG_ROM_REG_BPS0 (~( 0U))
+#endif
+ /* Block Protection Register 1 */
+#ifndef BSP_CFG_ROM_REG_BPS1
+ #define BSP_CFG_ROM_REG_BPS1 (~( 0U))
+#endif
+ /* Block Protection Register 2 */
+#ifndef BSP_CFG_ROM_REG_BPS2
+ #define BSP_CFG_ROM_REG_BPS2 (~( 0U))
+#endif
+ /* Block Protection Register 3 */
+#ifndef BSP_CFG_ROM_REG_BPS3
+ #define BSP_CFG_ROM_REG_BPS3 (~( 0U))
+#endif
+ /* Permanent Block Protection Register 0 */
+#ifndef BSP_CFG_ROM_REG_PBPS0
+ #define BSP_CFG_ROM_REG_PBPS0 (~( 0U))
+#endif
+ /* Permanent Block Protection Register 1 */
+#ifndef BSP_CFG_ROM_REG_PBPS1
+ #define BSP_CFG_ROM_REG_PBPS1 (~( 0U))
+#endif
+ /* Permanent Block Protection Register 2 */
+#ifndef BSP_CFG_ROM_REG_PBPS2
+ #define BSP_CFG_ROM_REG_PBPS2 (~( 0U))
+#endif
+ /* Permanent Block Protection Register 3 */
+#ifndef BSP_CFG_ROM_REG_PBPS3
+ #define BSP_CFG_ROM_REG_PBPS3 (~( 0U))
+#endif
+ /* Security Attribution for Block Protection Register 0 (If any blocks are marked as protected in the secure application, then mark them as secure) */
+#ifndef BSP_CFG_ROM_REG_BPS_SEL0
+ #define BSP_CFG_ROM_REG_BPS_SEL0 (BSP_CFG_ROM_REG_BPS0 & BSP_CFG_ROM_REG_PBPS0)
+#endif
+ /* Security Attribution for Block Protection Register 1 (If any blocks are marked as protected in the secure application, then mark them as secure) */
+#ifndef BSP_CFG_ROM_REG_BPS_SEL1
+ #define BSP_CFG_ROM_REG_BPS_SEL1 (BSP_CFG_ROM_REG_BPS1 & BSP_CFG_ROM_REG_PBPS1)
+#endif
+ /* Security Attribution for Block Protection Register 2 (If any blocks are marked as protected in the secure application, then mark them as secure) */
+#ifndef BSP_CFG_ROM_REG_BPS_SEL2
+ #define BSP_CFG_ROM_REG_BPS_SEL2 (BSP_CFG_ROM_REG_BPS2 & BSP_CFG_ROM_REG_PBPS2)
+#endif
+ /* Security Attribution for Block Protection Register 3 (If any blocks are marked as protected in the secure application, then mark them as secure) */
+#ifndef BSP_CFG_ROM_REG_BPS_SEL3
+ #define BSP_CFG_ROM_REG_BPS_SEL3 (BSP_CFG_ROM_REG_BPS3 & BSP_CFG_ROM_REG_PBPS3)
+#endif
+ /* Security Attribution for Bank Select Register */
+#ifndef BSP_CFG_ROM_REG_BANKSEL_SEL
+ #define BSP_CFG_ROM_REG_BANKSEL_SEL (0xFFFFFFFFU)
+#endif
+#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT
+ #define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9)
+#endif
+
+ /* FSBL Control Register 0 */
+#ifndef BSP_CFG_ROM_REG_FSBLCTRL0
+#define BSP_CFG_ROM_REG_FSBLCTRL0 ( \
+ (7 << R_OFS_DATAFLASH_FSBLCTRL0_FSBLEN_Pos) | \
+ (7 << R_OFS_DATAFLASH_FSBLCTRL0_FSBLSKIPSW_Pos) | \
+ (7 << R_OFS_DATAFLASH_FSBLCTRL0_FSBLSKIPDS_Pos) | \
+ (7 << R_OFS_DATAFLASH_FSBLCTRL0_FSBLCLK_Pos) | \
+ 0xFFFFF000)
+#endif
+
+ /* FSBL Control Register 1 */
+#ifndef BSP_CFG_ROM_REG_FSBLCTRL1
+#define BSP_CFG_ROM_REG_FSBLCTRL1 ( \
+ (3 << R_OFS_DATAFLASH_FSBLCTRL1_FSBLEXMD_Pos) | \
+ 0xFFFFFFFC)
+#endif
+
+ /* FSBL Control Register 2 */
+#ifndef BSP_CFG_ROM_REG_FSBLCTRL2
+#define BSP_CFG_ROM_REG_FSBLCTRL2 ( \
+ (15 << R_OFS_DATAFLASH_FSBLCTRL2_PORTPN_Pos) | \
+ (0x1F << R_OFS_DATAFLASH_FSBLCTRL2_PORTGN_Pos) | \
+ 0xFFFFFE00)
+#endif
+
+ /* Start Address of Code Certificate Register 0 */
+#ifndef BSP_CFG_ROM_REG_SACC0
+#define BSP_CFG_ROM_REG_SACC0 (0xFFFFFFFF)
+#endif
+
+ /* Start Address of Code Certificate Register 1 */
+#ifndef BSP_CFG_ROM_REG_SACC1
+#define BSP_CFG_ROM_REG_SACC1 (0xFFFFFFFF)
+#endif
+
+ /* Start Address of Measurement Report Register */
+#ifndef BSP_CFG_ROM_REG_SAMR
+#define BSP_CFG_ROM_REG_SAMR (0xFFFFFFFF)
+#endif
+
+#ifndef BSP_CFG_DCACHE_ENABLED
+#define BSP_CFG_DCACHE_ENABLED (0)
+#endif
+
+
+#ifndef BSP_CFG_SDRAM_ENABLED
+ #define BSP_CFG_SDRAM_ENABLED (0)
+#endif
+
+#ifndef BSP_CFG_SDRAM_TRAS
+ #define BSP_CFG_SDRAM_TRAS (6)
+#endif
+
+#ifndef BSP_CFG_SDRAM_TRCD
+ #define BSP_CFG_SDRAM_TRCD (3)
+#endif
+
+#ifndef BSP_CFG_SDRAM_TRP
+ #define BSP_CFG_SDRAM_TRP (3)
+#endif
+
+#ifndef BSP_CFG_SDRAM_TWR
+ #define BSP_CFG_SDRAM_TWR (2)
+#endif
+
+#ifndef BSP_CFG_SDRAM_TCL
+ #define BSP_CFG_SDRAM_TCL (3)
+#endif
+
+#ifndef BSP_CFG_SDRAM_TRFC
+ #define BSP_CFG_SDRAM_TRFC (937)
+#endif
+
+#ifndef BSP_CFG_SDRAM_TREFW
+ #define BSP_CFG_SDRAM_TREFW (8)
+#endif
+
+#ifndef BSP_CFG_SDRAM_INIT_ARFI
+ #define BSP_CFG_SDRAM_INIT_ARFI (10)
+#endif
+
+#ifndef BSP_CFG_SDRAM_INIT_ARFC
+ #define BSP_CFG_SDRAM_INIT_ARFC (8)
+#endif
+
+#ifndef BSP_CFG_SDRAM_INIT_PRC
+ #define BSP_CFG_SDRAM_INIT_PRC (3)
+#endif
+
+#ifndef BSP_CFG_SDRAM_MULTIPLEX_ADDR_SHIFT
+ #define BSP_CFG_SDRAM_MULTIPLEX_ADDR_SHIFT (1)
+#endif
+
+#ifndef BSP_CFG_SDRAM_ENDIAN_MODE
+ #define BSP_CFG_SDRAM_ENDIAN_MODE (0)
+#endif
+
+#ifndef BSP_CFG_SDRAM_ACCESS_MODE
+ #define BSP_CFG_SDRAM_ACCESS_MODE (1)
+#endif
+
+#ifndef BSP_CFG_SDRAM_BUS_WIDTH
+ #define BSP_CFG_SDRAM_BUS_WIDTH (0)
+#endif
+#endif /* BSP_MCU_FAMILY_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h b/hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h
new file mode 100644
index 0000000000..8833634378
--- /dev/null
+++ b/hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h
@@ -0,0 +1,127 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_PIN_CFG_H_
+#define BSP_PIN_CFG_H_
+#include "r_ioport.h"
+
+/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+#define ENET_RMII_INT (BSP_IO_PORT_00_PIN_00)
+#define ARDUINO_A3 (BSP_IO_PORT_00_PIN_01)
+#define GROVE2_AN102 (BSP_IO_PORT_00_PIN_02)
+#define ARDUINO_A1 (BSP_IO_PORT_00_PIN_03)
+#define ARDUINO_A0_MIKROBUS_AN000 (BSP_IO_PORT_00_PIN_04)
+#define GROVE2_AN001 (BSP_IO_PORT_00_PIN_05)
+#define PMOD1_IRQ11 (BSP_IO_PORT_00_PIN_06)
+#define ARDUINO_A004 (BSP_IO_PORT_00_PIN_07)
+#define USER_S2 (BSP_IO_PORT_00_PIN_08)
+#define SW1 (BSP_IO_PORT_00_PIN_09)
+#define MIKROBUS_IRQ14 (BSP_IO_PORT_00_PIN_10)
+#define ARDUINO_A4 (BSP_IO_PORT_00_PIN_14)
+#define ARDUINO_A5 (BSP_IO_PORT_00_PIN_15)
+#define OSPI_DQ0 (BSP_IO_PORT_01_PIN_00)
+#define OSPI_DQ3 (BSP_IO_PORT_01_PIN_01)
+#define OSPI_DQ4 (BSP_IO_PORT_01_PIN_02)
+#define OSPI_DQ2 (BSP_IO_PORT_01_PIN_03)
+#define OSPI_CS (BSP_IO_PORT_01_PIN_04)
+#define OSPI_INT (BSP_IO_PORT_01_PIN_05)
+#define OSPI_RESET (BSP_IO_PORT_01_PIN_06)
+#define LED3 (BSP_IO_PORT_01_PIN_07)
+#define ETH_A_RMII_RMII_RXDV (BSP_IO_PORT_01_PIN_12)
+#define ETH_A_LINKSTA (BSP_IO_PORT_01_PIN_14)
+#define MPLX_CTRL (BSP_IO_PORT_01_PIN_15)
+#define NMI (BSP_IO_PORT_02_PIN_00)
+#define MD (BSP_IO_PORT_02_PIN_01)
+#define CAN_STB (BSP_IO_PORT_02_PIN_07)
+#define TDI (BSP_IO_PORT_02_PIN_08)
+#define TDO (BSP_IO_PORT_02_PIN_09)
+#define SWDIO (BSP_IO_PORT_02_PIN_10)
+#define SWCLK (BSP_IO_PORT_02_PIN_11)
+#define EXTAL (BSP_IO_PORT_02_PIN_12)
+#define XTAL (BSP_IO_PORT_02_PIN_13)
+#define ETH_A_RXER (BSP_IO_PORT_03_PIN_00)
+#define ETH_A_RXD1 (BSP_IO_PORT_03_PIN_01)
+#define ETH_A_RXD0 (BSP_IO_PORT_03_PIN_02)
+#define ETH_A_REFCLK (BSP_IO_PORT_03_PIN_03)
+#define ETH_A_TXD0 (BSP_IO_PORT_03_PIN_04)
+#define ETH_A_TXD1 (BSP_IO_PORT_03_PIN_05)
+#define ETH_A_TXEN (BSP_IO_PORT_03_PIN_06)
+#define ETH_A_MDIO (BSP_IO_PORT_03_PIN_07)
+#define ETH_A_MDC (BSP_IO_PORT_03_PIN_08)
+#define ARDUINO_D0_MIKROBUS_RXD3 (BSP_IO_PORT_03_PIN_09)
+#define ARDUINO_D1_MIKROBUS_TXD3 (BSP_IO_PORT_03_PIN_10)
+#define CAN_RXD (BSP_IO_PORT_03_PIN_11)
+#define CAN_TXD (BSP_IO_PORT_03_PIN_12)
+#define I3C_SCL0_ARDUINO_MIKROBUS_PMOD1_3_qwiic (BSP_IO_PORT_04_PIN_00)
+#define I3C_SDA0_ARDUINO_MIKROBUS_PMOD1_4_qwiic (BSP_IO_PORT_04_PIN_01)
+#define ETH_B_MDIO (BSP_IO_PORT_04_PIN_02)
+#define ETH_B_LINKSTA (BSP_IO_PORT_04_PIN_03)
+#define ETH_B_RST_N (BSP_IO_PORT_04_PIN_04)
+#define ETH_B_TXEN (BSP_IO_PORT_04_PIN_05)
+#define ETH_B_TXD1 (BSP_IO_PORT_04_PIN_06)
+#define USBFS_VBUS (BSP_IO_PORT_04_PIN_07)
+#define USBHS_VBUSEN (BSP_IO_PORT_04_PIN_08)
+#define USBHS_OVRCURA (BSP_IO_PORT_04_PIN_09)
+#define MISOB_B_ARDUINO_MIKROBUS (BSP_IO_PORT_04_PIN_10)
+#define MOSIB_B_ARDUINO_MIKROBUS (BSP_IO_PORT_04_PIN_11)
+#define RSPCKB_B_ARDUINO_MIKROBUS (BSP_IO_PORT_04_PIN_12)
+#define SSLB0_B_ARDUINO_D10_MIKROBUS (BSP_IO_PORT_04_PIN_13)
+#define LED2 (BSP_IO_PORT_04_PIN_14)
+#define USBFS_VBUS_EN (BSP_IO_PORT_05_PIN_00)
+#define USBFS_OVERCURA (BSP_IO_PORT_05_PIN_01)
+#define MIKROBUS_RESET (BSP_IO_PORT_05_PIN_02)
+#define PMOD2_7_IRQ1 (BSP_IO_PORT_05_PIN_08)
+#define GROVE2_IIC_SDA1 (BSP_IO_PORT_05_PIN_11)
+#define GROVE2_IIC_SCL1 (BSP_IO_PORT_05_PIN_12)
+#define LED1 (BSP_IO_PORT_06_PIN_00)
+#define ARDUINO_D5 (BSP_IO_PORT_06_PIN_01)
+#define ARDUINO_D6 (BSP_IO_PORT_06_PIN_02)
+#define ARDUINO_D9 (BSP_IO_PORT_06_PIN_03)
+#define PMOD1_3_MISO0_RXD0_SCL0 (BSP_IO_PORT_06_PIN_09)
+#define PMOD1_2_MOSI0_TXD0 (BSP_IO_PORT_06_PIN_10)
+#define PMOD1_4_SCK0 (BSP_IO_PORT_06_PIN_11)
+#define PMOD1_1_SSL0_CTS_RTS (BSP_IO_PORT_06_PIN_12)
+#define PMOD1_1_CTS0 (BSP_IO_PORT_06_PIN_13)
+#define PMOD1_9_GPIO (BSP_IO_PORT_06_PIN_14)
+#define PMOD1_10_GPIO (BSP_IO_PORT_06_PIN_15)
+#define ETH_B_TXD0 (BSP_IO_PORT_07_PIN_00)
+#define ETH_B_REFCLK (BSP_IO_PORT_07_PIN_01)
+#define ETH_B_RXD0 (BSP_IO_PORT_07_PIN_02)
+#define ETH_B_RXD1 (BSP_IO_PORT_07_PIN_03)
+#define ETH_B_RXER (BSP_IO_PORT_07_PIN_04)
+#define ETH_B_RMII_RXDV (BSP_IO_PORT_07_PIN_05)
+#define I3C_SDA0_PULLUP (BSP_IO_PORT_07_PIN_11)
+#define OSPI_DQ5 (BSP_IO_PORT_08_PIN_00)
+#define OSPI_DS (BSP_IO_PORT_08_PIN_01)
+#define OSPI_DQ6 (BSP_IO_PORT_08_PIN_02)
+#define OSPI_DQ1 (BSP_IO_PORT_08_PIN_03)
+#define OSPI_DQ7 (BSP_IO_PORT_08_PIN_04)
+#define OSPI_CK (BSP_IO_PORT_08_PIN_08)
+#define PMOD2_8_RESET (BSP_IO_PORT_08_PIN_09)
+#define PMOD2_9_GPIO (BSP_IO_PORT_08_PIN_10)
+#define PMOD2_10_GPIO (BSP_IO_PORT_08_PIN_11)
+#define ARDUINO_RESET (BSP_IO_PORT_08_PIN_12)
+#define USBFS_P (BSP_IO_PORT_08_PIN_14)
+#define USBFS_N (BSP_IO_PORT_08_PIN_15)
+#define ARDUINO_D4 (BSP_IO_PORT_09_PIN_05)
+#define ARDUINO_D2 (BSP_IO_PORT_09_PIN_06)
+#define ARDUINO_D3_MIKROBUS_GTIOC13A (BSP_IO_PORT_09_PIN_07)
+#define ARDUINO_D7 (BSP_IO_PORT_09_PIN_08)
+#define ARDUINO_D8 (BSP_IO_PORT_09_PIN_09)
+#define PMOD2_3_MISO2_RXD2 (BSP_IO_PORT_10_PIN_02)
+#define PMOD2_2_MOSI2_TXD2 (BSP_IO_PORT_10_PIN_03)
+#define PMOD2_4_SCK2 (BSP_IO_PORT_10_PIN_04)
+#define PMOD2_1_CTS_RTS_SSL2 (BSP_IO_PORT_10_PIN_05)
+#define PMOD2_1_CTS2 (BSP_IO_PORT_10_PIN_06)
+#define PMOD1_8_RESET (BSP_IO_PORT_10_PIN_08)
+#define JLOB_COMS_TX (BSP_IO_PORT_10_PIN_14)
+#define JLOB_COMS_RX (BSP_IO_PORT_10_PIN_15)
+#define I3C_SCL0_PULLUP (BSP_IO_PORT_11_PIN_00)
+#define USBHS_VBUS (BSP_IO_PORT_11_PIN_01)
+extern const ioport_cfg_t g_bsp_pin_cfg; /* RA8M1 EK */
+
+void BSP_PinConfigSecurityInit();
+
+/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+#endif /* BSP_PIN_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h b/hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h
new file mode 100644
index 0000000000..d2688bf5ba
--- /dev/null
+++ b/hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h
@@ -0,0 +1,13 @@
+/* generated configuration header file - do not edit */
+#ifndef R_IOPORT_CFG_H_
+#define R_IOPORT_CFG_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* R_IOPORT_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra8m1_ek/ra_gen/bsp_clock_cfg.h b/hw/bsp/ra/boards/ra8m1_ek/ra_gen/bsp_clock_cfg.h
new file mode 100644
index 0000000000..f2f1ae0c9c
--- /dev/null
+++ b/hw/bsp/ra/boards/ra8m1_ek/ra_gen/bsp_clock_cfg.h
@@ -0,0 +1,56 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_CLOCK_CFG_H_
+#define BSP_CLOCK_CFG_H_
+#define BSP_CFG_CLOCKS_SECURE (0)
+#define BSP_CFG_CLOCKS_OVERRIDE (0)
+#define BSP_CFG_XTAL_HZ (20000000) /* XTAL 20000000Hz */
+#define BSP_CFG_HOCO_FREQUENCY (7) /* HOCO 48MHz */
+#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */
+#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL Div /2 */
+#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(96,0) /* PLL Mul x80-99|Mul x96|PLL Mul x96.00 */
+#define BSP_CFG_PLL_FREQUENCY_HZ (960000000) /* PLL 960000000Hz */
+#define BSP_CFG_PLODIVP (BSP_CLOCKS_PLL_DIV_2) /* PLL1P Div /2 */
+#define BSP_CFG_PLL1P_FREQUENCY_HZ (480000000) /* PLL1P 480000000Hz */
+#define BSP_CFG_PLODIVQ (BSP_CLOCKS_PLL_DIV_4) /* PLL1Q Div /4 */
+#define BSP_CFG_PLL1Q_FREQUENCY_HZ (240000000) /* PLL1Q 240000000Hz */
+#define BSP_CFG_PLODIVR (BSP_CLOCKS_PLL_DIV_2) /* PLL1R Div /2 */
+#define BSP_CFG_PLL1R_FREQUENCY_HZ (480000000) /* PLL1R 480000000Hz */
+#define BSP_CFG_PLL2_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* PLL2 Disabled */
+#define BSP_CFG_PLL2_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL2 Div /2 */
+#define BSP_CFG_PLL2_MUL BSP_CLOCKS_PLL_MUL(96,0) /* PLL2 Mul x80-99|Mul x96|PLL2 Mul x96.00 */
+#define BSP_CFG_PLL2_FREQUENCY_HZ (0) /* PLL2 0Hz */
+#define BSP_CFG_PL2ODIVP (BSP_CLOCKS_PLL_DIV_2) /* PLL2P Div /2 */
+#define BSP_CFG_PLL2P_FREQUENCY_HZ (0) /* PLL2P 0Hz */
+#define BSP_CFG_PL2ODIVQ (BSP_CLOCKS_PLL_DIV_2) /* PLL2Q Div /2 */
+#define BSP_CFG_PLL2Q_FREQUENCY_HZ (0) /* PLL2Q 0Hz */
+#define BSP_CFG_PL2ODIVR (BSP_CLOCKS_PLL_DIV_2) /* PLL2R Div /2 */
+#define BSP_CFG_PLL2R_FREQUENCY_HZ (0) /* PLL2R 0Hz */
+#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL1P) /* Clock Src: PLL1P */
+#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */
+#define BSP_CFG_SCICLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* SCICLK Disabled */
+#define BSP_CFG_SPICLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* SPICLK Disabled */
+#define BSP_CFG_CANFDCLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CANFDCLK Disabled */
+#define BSP_CFG_I3CCLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* I3CCLK Disabled */
+#define BSP_CFG_UCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL1Q) /* UCK Src: PLL1Q */
+#define BSP_CFG_U60CK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL1P) /* U60CK Src: PLL1P */
+#define BSP_CFG_OCTA_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* OCTASPICLK Disabled */
+#define BSP_CFG_CPUCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CPUCLK Div /1 */
+#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* ICLK Div /2 */
+#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKA Div /4 */
+#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_8) /* PCLKB Div /8 */
+#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_8) /* PCLKC Div /8 */
+#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKD Div /4 */
+#define BSP_CFG_PCLKE_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKE Div /2 */
+#define BSP_CFG_SDCLK_OUTPUT (1) /* SDCLK Enabled */
+#define BSP_CFG_BCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* BCLK Div /4 */
+#define BSP_CFG_BCLK_OUTPUT (2) /* EBCLK Div /2 */
+#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_8) /* FCLK Div /8 */
+#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */
+#define BSP_CFG_SCICLK_DIV (BSP_CLOCKS_SCI_CLOCK_DIV_4) /* SCICLK Div /4 */
+#define BSP_CFG_SPICLK_DIV (BSP_CLOCKS_SPI_CLOCK_DIV_4) /* SPICLK Div /4 */
+#define BSP_CFG_CANFDCLK_DIV (BSP_CLOCKS_CANFD_CLOCK_DIV_8) /* CANFDCLK Div /8 */
+#define BSP_CFG_I3CCLK_DIV (BSP_CLOCKS_I3C_CLOCK_DIV_3) /* I3CCLK Div /3 */
+#define BSP_CFG_UCK_DIV (BSP_CLOCKS_USB_CLOCK_DIV_5) /* UCK Div /5 */
+#define BSP_CFG_U60CK_DIV (BSP_CLOCKS_USB_CLOCK_DIV_8) /* U60CK Div /8 */
+#define BSP_CFG_OCTA_DIV (BSP_CLOCKS_OCTA_CLOCK_DIV_4) /* OCTASPICLK Div /4 */
+#endif /* BSP_CLOCK_CFG_H_ */
diff --git a/hw/bsp/ra/boards/ra8m1_ek/ra_gen/common_data.c b/hw/bsp/ra/boards/ra8m1_ek/ra_gen/common_data.c
new file mode 100644
index 0000000000..50036c0adc
--- /dev/null
+++ b/hw/bsp/ra/boards/ra8m1_ek/ra_gen/common_data.c
@@ -0,0 +1,11 @@
+/* generated common source file - do not edit */
+#include "common_data.h"
+ioport_instance_ctrl_t g_ioport_ctrl;
+const ioport_instance_t g_ioport =
+ {
+ .p_api = &g_ioport_on_ioport,
+ .p_ctrl = &g_ioport_ctrl,
+ .p_cfg = &g_bsp_pin_cfg,
+ };
+void g_common_init(void) {
+}
diff --git a/hw/bsp/ra/boards/ra8m1_ek/ra_gen/common_data.h b/hw/bsp/ra/boards/ra8m1_ek/ra_gen/common_data.h
new file mode 100644
index 0000000000..6a08cbee09
--- /dev/null
+++ b/hw/bsp/ra/boards/ra8m1_ek/ra_gen/common_data.h
@@ -0,0 +1,20 @@
+/* generated common header file - do not edit */
+#ifndef COMMON_DATA_H_
+#define COMMON_DATA_H_
+#include
+#include "bsp_api.h"
+#include "r_ioport.h"
+#include "bsp_pin_cfg.h"
+FSP_HEADER
+#define IOPORT_CFG_NAME g_bsp_pin_cfg
+#define IOPORT_CFG_OPEN R_IOPORT_Open
+#define IOPORT_CFG_CTRL g_ioport_ctrl
+
+/* IOPORT Instance */
+extern const ioport_instance_t g_ioport;
+
+/* IOPORT control structure. */
+extern ioport_instance_ctrl_t g_ioport_ctrl;
+void g_common_init(void);
+FSP_FOOTER
+#endif /* COMMON_DATA_H_ */
diff --git a/hw/bsp/ra/boards/ra8m1_ek/ra_gen/pin_data.c b/hw/bsp/ra/boards/ra8m1_ek/ra_gen/pin_data.c
new file mode 100644
index 0000000000..b924217397
--- /dev/null
+++ b/hw/bsp/ra/boards/ra8m1_ek/ra_gen/pin_data.c
@@ -0,0 +1,275 @@
+/* generated pin source file - do not edit */
+#include "bsp_api.h"
+#include "r_ioport.h"
+
+
+const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = {
+ {
+ .pin = BSP_IO_PORT_00_PIN_00,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT)
+ },
+ {
+ .pin = BSP_IO_PORT_00_PIN_02,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE)
+ },
+ {
+ .pin = BSP_IO_PORT_00_PIN_03,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE)
+ },
+ {
+ .pin = BSP_IO_PORT_00_PIN_04,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE)
+ },
+ {
+ .pin = BSP_IO_PORT_00_PIN_05,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE)
+ },
+ {
+ .pin = BSP_IO_PORT_00_PIN_07,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE)
+ },
+ {
+ .pin = BSP_IO_PORT_00_PIN_08,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_IRQ_ENABLE | (uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT)
+ },
+ {
+ .pin = BSP_IO_PORT_00_PIN_09,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_IRQ_ENABLE | (uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT)
+ },
+ {
+ .pin = BSP_IO_PORT_00_PIN_11,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE)
+ },
+ {
+ .pin = BSP_IO_PORT_00_PIN_14,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE)
+ },
+ {
+ .pin = BSP_IO_PORT_00_PIN_15,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE)
+ },
+ {
+ .pin = BSP_IO_PORT_01_PIN_00,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI)
+ },
+ {
+ .pin = BSP_IO_PORT_01_PIN_01,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI)
+ },
+ {
+ .pin = BSP_IO_PORT_01_PIN_02,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI)
+ },
+ {
+ .pin = BSP_IO_PORT_01_PIN_03,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI)
+ },
+ {
+ .pin = BSP_IO_PORT_01_PIN_04,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI)
+ },
+ {
+ .pin = BSP_IO_PORT_01_PIN_05,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI)
+ },
+ {
+ .pin = BSP_IO_PORT_01_PIN_06,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI)
+ },
+ {
+ .pin = BSP_IO_PORT_01_PIN_07,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+ },
+ {
+ .pin = BSP_IO_PORT_02_PIN_09,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_TRACE)
+ },
+ {
+ .pin = BSP_IO_PORT_02_PIN_10,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG)
+ },
+ {
+ .pin = BSP_IO_PORT_02_PIN_11,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG)
+ },
+ {
+ .pin = BSP_IO_PORT_03_PIN_04,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_TRACE)
+ },
+ {
+ .pin = BSP_IO_PORT_03_PIN_05,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_TRACE)
+ },
+ {
+ .pin = BSP_IO_PORT_03_PIN_06,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_TRACE)
+ },
+ {
+ .pin = BSP_IO_PORT_03_PIN_07,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_TRACE)
+ },
+ {
+ .pin = BSP_IO_PORT_03_PIN_08,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_TRACE)
+ },
+ {
+ .pin = BSP_IO_PORT_04_PIN_07,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)
+ },
+ {
+ .pin = BSP_IO_PORT_04_PIN_08,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_HS)
+ },
+ {
+ .pin = BSP_IO_PORT_04_PIN_09,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_HS)
+ },
+ {
+ .pin = BSP_IO_PORT_04_PIN_10,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
+ },
+ {
+ .pin = BSP_IO_PORT_04_PIN_11,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
+ },
+ {
+ .pin = BSP_IO_PORT_04_PIN_12,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
+ },
+ {
+ .pin = BSP_IO_PORT_04_PIN_13,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI)
+ },
+ {
+ .pin = BSP_IO_PORT_04_PIN_14,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+ },
+ {
+ .pin = BSP_IO_PORT_05_PIN_00,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)
+ },
+ {
+ .pin = BSP_IO_PORT_05_PIN_01,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)
+ },
+ {
+ .pin = BSP_IO_PORT_05_PIN_11,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_MID | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_IIC)
+ },
+ {
+ .pin = BSP_IO_PORT_05_PIN_12,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_MID | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_IIC)
+ },
+ {
+ .pin = BSP_IO_PORT_06_PIN_00,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+ },
+ {
+ .pin = BSP_IO_PORT_08_PIN_00,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI)
+ },
+ {
+ .pin = BSP_IO_PORT_08_PIN_01,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI)
+ },
+ {
+ .pin = BSP_IO_PORT_08_PIN_02,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI)
+ },
+ {
+ .pin = BSP_IO_PORT_08_PIN_03,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI)
+ },
+ {
+ .pin = BSP_IO_PORT_08_PIN_04,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI)
+ },
+ {
+ .pin = BSP_IO_PORT_08_PIN_08,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI)
+ },
+ {
+ .pin = BSP_IO_PORT_08_PIN_09,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+ },
+ {
+ .pin = BSP_IO_PORT_08_PIN_14,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)
+ },
+ {
+ .pin = BSP_IO_PORT_08_PIN_15,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)
+ },
+ {
+ .pin = BSP_IO_PORT_10_PIN_02,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI0_2_4_6_8)
+ },
+ {
+ .pin = BSP_IO_PORT_10_PIN_03,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI0_2_4_6_8)
+ },
+ {
+ .pin = BSP_IO_PORT_10_PIN_04,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI0_2_4_6_8)
+ },
+ {
+ .pin = BSP_IO_PORT_10_PIN_05,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI0_2_4_6_8)
+ },
+ {
+ .pin = BSP_IO_PORT_10_PIN_06,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT)
+ },
+ {
+ .pin = BSP_IO_PORT_10_PIN_14,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI1_3_5_7_9)
+ },
+ {
+ .pin = BSP_IO_PORT_10_PIN_15,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI1_3_5_7_9)
+ },
+ {
+ .pin = BSP_IO_PORT_11_PIN_01,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_HS)
+ },
+};
+
+const ioport_cfg_t g_bsp_pin_cfg = {
+ .number_of_pins = sizeof(g_bsp_pin_cfg_data)/sizeof(ioport_pin_cfg_t),
+ .p_pin_cfg_data = &g_bsp_pin_cfg_data[0],
+};
+
+#if BSP_TZ_SECURE_BUILD
+
+void R_BSP_PinCfgSecurityInit(void);
+
+/* Initialize SAR registers for secure pins. */
+void R_BSP_PinCfgSecurityInit(void)
+{
+ #if (2U == BSP_FEATURE_IOPORT_VERSION)
+ uint32_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR];
+ #else
+ uint16_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR];
+ #endif
+ memset(pmsar, 0xFF, BSP_FEATURE_BSP_NUM_PMSAR * sizeof(R_PMISC->PMSAR[0]));
+
+
+ for(uint32_t i = 0; i < g_bsp_pin_cfg.number_of_pins; i++)
+ {
+ uint32_t port_pin = g_bsp_pin_cfg.p_pin_cfg_data[i].pin;
+ uint32_t port = port_pin >> 8U;
+ uint32_t pin = port_pin & 0xFFU;
+ pmsar[port] &= (uint16_t) ~(1U << pin);
+ }
+
+ for(uint32_t i = 0; i < BSP_FEATURE_BSP_NUM_PMSAR; i++)
+ {
+ #if (2U == BSP_FEATURE_IOPORT_VERSION)
+ R_PMISC->PMSAR[i].PMSAR = (uint16_t) pmsar[i];
+ #else
+ R_PMISC->PMSAR[i].PMSAR = pmsar[i];
+ #endif
+ }
+
+}
+#endif
diff --git a/hw/bsp/ra/boards/ra8m1_ek/script/fsp.ld b/hw/bsp/ra/boards/ra8m1_ek/script/fsp.ld
new file mode 100644
index 0000000000..d7f78a9158
--- /dev/null
+++ b/hw/bsp/ra/boards/ra8m1_ek/script/fsp.ld
@@ -0,0 +1,823 @@
+/*
+ Linker File for Renesas FSP
+*/
+
+INCLUDE memory_regions.ld
+
+/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/
+/*
+ XIP_SECONDARY_SLOT_IMAGE = 1;
+*/
+
+QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH);
+OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH);
+OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH);
+
+/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */
+__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0);
+
+ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0;
+ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0;
+DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0;
+DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0;
+RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0;
+RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0;
+RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH;
+RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH;
+
+OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80;
+OPTION_SETTING_DATA_FLASH_S_START = DEFINED(OPTION_SETTING_DATA_FLASH_S_START) ? OPTION_SETTING_DATA_FLASH_S_START : 0;
+OPTION_SETTING_DATA_FLASH_S_LENGTH = DEFINED(OPTION_SETTING_DATA_FLASH_S_LENGTH) ? OPTION_SETTING_DATA_FLASH_S_LENGTH : 0;
+
+/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings.
+ * Bootloader images do not configure option settings because they are owned by the bootloader.
+ * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */
+__bl_FSP_BOOTABLE_IMAGE = 1;
+__bln_FSP_BOOTABLE_IMAGE = 1;
+PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE);
+USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE);
+USE_OPTION_SETTING_DATA_FLASH = PROJECT_SECURE_OR_FLAT && (OPTION_SETTING_DATA_FLASH_S_LENGTH != 0);
+
+__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+ FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH :
+ (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH :
+ FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH;
+__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+ FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH;
+__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH;
+__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+ FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH;
+__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH;
+__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+ FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
+ __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH;
+__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+ FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
+ __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH;
+__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+ FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH :
+ RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH;
+__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+ FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH :
+ __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH;
+__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+ FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
+ __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2;
+__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START);
+__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+ FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
+ FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2;
+
+XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0;
+FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START :
+ XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START :
+ FLASH_IMAGE_START;
+LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH :
+ DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH :
+ FLASH_LENGTH;
+OPTION_SETTING_SAS_SIZE = 0x34;
+OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 :
+ OPTION_SETTING_LENGTH == 0 ? 0 :
+ OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE;
+
+/* Define memory regions. */
+MEMORY
+{
+ ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH
+ DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH
+ FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH
+ RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH
+ DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH
+ QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH
+ OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH
+ OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH
+ OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH
+ OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH
+ SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH
+ OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH
+ OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18
+ OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH
+ OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH
+ OPTION_SETTING_DATA_FLASH_S (r) : ORIGIN = OPTION_SETTING_DATA_FLASH_S_START, LENGTH = OPTION_SETTING_DATA_FLASH_S_LENGTH
+ ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH
+}
+
+/* Library configurations */
+GROUP(libgcc.a libc.a libm.a)
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be DEFINED in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __copy_table_start__
+ * __copy_table_end__
+ * __zero_table_start__
+ * __zero_table_end__
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ * __Vectors_End
+ * __Vectors_Size
+ * __qspi_flash_start__
+ * __qspi_flash_end__
+ * __qspi_flash_code_size__
+ * __qspi_region_max_size__
+ * __qspi_region_start_address__
+ * __qspi_region_end_address__
+ * __ospi_device_0_start__
+ * __ospi_device_0_end__
+ * __ospi_device_0_code_size__
+ * __ospi_device_0_region_max_size__
+ * __ospi_device_0_region_start_address__
+ * __ospi_device_0_region_end_address__
+ * __ospi_device_1_start__
+ * __ospi_device_1_end__
+ * __ospi_device_1_code_size__
+ * __ospi_device_1_region_max_size__
+ * __ospi_device_1_region_start_address__
+ * __ospi_device_1_region_end_address__
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ __tz_FLASH_S = ABSOLUTE(FLASH_START);
+ __ROM_Start = .;
+
+ /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much
+ * space because ROM registers are at address 0x400 and there is very little space
+ * in between. */
+ KEEP(*(.fixed_vectors*))
+ KEEP(*(.application_vectors*))
+ __Vectors_End = .;
+
+ /* Some devices have a gap of code flash between the vector table and ROM Registers.
+ * The flash gap section allows applications to place code and data in this section. */
+ *(.flash_gap*)
+
+ /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */
+ . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400;
+ KEEP(*(.rom_registers*))
+
+ /* Reserving 0x100 bytes of space for ROM registers. */
+ . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x500;
+
+ /* Allocate flash write-boundary-aligned
+ * space for sce9 wrapped public keys for mcuboot if the module is used.
+ */
+ KEEP(*(.mcuboot_sce9_key*))
+
+ *(.text*)
+
+ KEEP(*(.version))
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+ __usb_dev_descriptor_start_fs = .;
+ KEEP(*(.usb_device_desc_fs*))
+ __usb_cfg_descriptor_start_fs = .;
+ KEEP(*(.usb_config_desc_fs*))
+ __usb_interface_descriptor_start_fs = .;
+ KEEP(*(.usb_interface_desc_fs*))
+ __usb_descriptor_end_fs = .;
+ __usb_dev_descriptor_start_hs = .;
+ KEEP(*(.usb_device_desc_hs*))
+ __usb_cfg_descriptor_start_hs = .;
+ KEEP(*(.usb_config_desc_hs*))
+ __usb_interface_descriptor_start_hs = .;
+ KEEP(*(.usb_interface_desc_hs*))
+ __usb_descriptor_end_hs = .;
+
+ KEEP(*(.eh_frame*))
+
+ __ROM_End = .;
+ } > FLASH = 0xFF
+
+ __Vectors_Size = __Vectors_End - __Vectors;
+
+ . = .;
+ __itcm_data_pre_location = .;
+
+ /* Initialized ITCM data. */
+ /* Aligned to FCACHE2 for RA8. */
+ .itcm_data : ALIGN(16)
+ {
+ /* Start of ITCM Secure Trustzone region. */
+ __tz_ITCM_S = ABSOLUTE(ITCM_START);
+
+ /* All ITCM data start */
+ __itcm_data_start = .;
+
+ KEEP(*(.itcm_data*))
+
+ /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */
+ . = ALIGN(8);
+
+ /* All ITCM data end */
+ __itcm_data_end = .;
+
+ /*
+ * Start of the ITCM Non-Secure Trustzone region.
+ * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects.
+ */
+ __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192);
+ } > ITCM AT > FLASH = 0x00
+
+ /* Addresses exported for ITCM initialization. */
+ __itcm_data_init_start = LOADADDR(.itcm_data);
+ __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data);
+
+ ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.")
+ ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.")
+ ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.")
+ ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.")
+
+ /* Restore location counter. */
+ /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */
+ /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */
+ . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location;
+
+ __exidx_start = .;
+ /DISCARD/ :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ }
+ __exidx_end = .;
+
+ /* To copy multiple ROM to RAM sections,
+ * uncomment .copy.table section and,
+ * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+ /*
+ .copy.table :
+ {
+ . = ALIGN(4);
+ __copy_table_start__ = .;
+ LONG (__etext)
+ LONG (__data_start__)
+ LONG (__data_end__ - __data_start__)
+ LONG (__etext2)
+ LONG (__data2_start__)
+ LONG (__data2_end__ - __data2_start__)
+ __copy_table_end__ = .;
+ } > FLASH
+ */
+
+ /* To clear multiple BSS sections,
+ * uncomment .zero.table section and,
+ * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+ /*
+ .zero.table :
+ {
+ . = ALIGN(4);
+ __zero_table_start__ = .;
+ LONG (__bss_start__)
+ LONG (__bss_end__ - __bss_start__)
+ LONG (__bss2_start__)
+ LONG (__bss2_end__ - __bss2_start__)
+ __zero_table_end__ = .;
+ } > FLASH
+ */
+
+ __etext = .;
+
+ __tz_RAM_S = ORIGIN(RAM);
+
+ /* If DTC is used, put the DTC vector table at the start of SRAM.
+ This avoids memory holes due to 1K alignment required by it. */
+ .fsp_dtc_vector_table (NOLOAD) :
+ {
+ . = ORIGIN(RAM);
+ *(.fsp_dtc_vector_table)
+ } > RAM
+
+ /* Initialized data section. */
+ .data :
+ {
+ __data_start__ = .;
+ . = ALIGN(4);
+
+ __Code_In_RAM_Start = .;
+
+ KEEP(*(.code_in_ram*))
+ __Code_In_RAM_End = .;
+
+ *(vtable)
+ /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */
+ *(.data.*)
+ *(.data)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+
+ . = ALIGN(4);
+
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM AT > FLASH
+
+ . = .;
+ __dtcm_data_pre_location = LOADADDR(.data) + SIZEOF(.data);
+
+ /* Initialized DTCM data. */
+ /* Aligned to FCACHE2 for RA8. */
+ .dtcm_data : ALIGN(16)
+ {
+ /* Start of DTCM Secure Trustzone region. */
+ __tz_DTCM_S = ABSOLUTE(DTCM_START);
+
+ /* Initialized DTCM data start */
+ __dtcm_data_start = .;
+
+ KEEP(*(.dtcm_data*))
+
+ /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */
+ . = ALIGN(8);
+
+ /* Initialized DTCM data end */
+ __dtcm_data_end = .;
+ } > DTCM AT > FLASH = 0x00
+
+ . = __dtcm_data_end;
+ /* Uninitialized DTCM data. */
+ /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */
+ .dtcm_bss ALIGN(8) (NOLOAD) :
+ {
+ /* Uninitialized DTCM data start */
+ __dtcm_bss_start = .;
+
+ KEEP(*(.dtcm_bss*))
+
+ /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */
+ . = ALIGN(8);
+
+ /* Uninitialized DTCM data end */
+ __dtcm_bss_end = .;
+
+ /*
+ * Start of the DTCM Non-Secure Trustzone region.
+ * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects.
+ */
+ __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192);
+ } > DTCM
+
+ /* Addresses exported for DTCM initialization. */
+ __dtcm_data_init_start = LOADADDR(.dtcm_data);
+ __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data);
+
+ ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.")
+ ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.")
+ ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).")
+ ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.")
+ ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.")
+ ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.")
+ ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.")
+ ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.")
+
+ /* Restore location counter. */
+ /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */
+ /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */
+ . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location;
+
+ /* TrustZone Secure Gateway Stubs Section */
+
+ /* Store location counter for SPI non-retentive sections. */
+ sgstubs_pre_location = .;
+
+ /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */
+ SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024);
+ .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024)
+ {
+ __FLASH_NSC_START = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024);
+ _start_sg = .;
+ *(.gnu.sgstubs*)
+ . = ALIGN(32);
+ _end_sg = .;
+ } > FLASH
+
+ __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768);
+ FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N;
+
+ /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */
+ __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH);
+
+ /* QSPI_FLASH section to be downloaded via debugger */
+ .qspi_flash :
+ {
+ __qspi_flash_start__ = .;
+ KEEP(*(.qspi_flash*))
+ KEEP(*(.code_in_qspi*))
+ __qspi_flash_end__ = .;
+ } > QSPI_FLASH
+ __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__;
+
+ /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */
+ __qspi_flash_code_addr__ = sgstubs_pre_location;
+ .qspi_non_retentive : AT(__qspi_flash_code_addr__)
+ {
+ __qspi_non_retentive_start__ = .;
+ KEEP(*(.qspi_non_retentive*))
+ __qspi_non_retentive_end__ = .;
+ } > QSPI_FLASH
+ __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__;
+
+ __qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */
+ __qspi_region_start_address__ = __qspi_flash_start__;
+ __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__;
+
+ /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */
+ __tz_QSPI_FLASH_N = __qspi_non_retentive_end__;
+
+ /* Support for OctaRAM */
+ .OSPI_DEVICE_0_NO_LOAD (NOLOAD):
+ {
+ . = ALIGN(4);
+ __ospi_device_0_start__ = .;
+ *(.ospi_device_0_no_load*)
+ . = ALIGN(4);
+ __ospi_device_0_end__ = .;
+ } > OSPI_DEVICE_0_RAM
+
+ .OSPI_DEVICE_1_NO_LOAD (NOLOAD):
+ {
+ . = ALIGN(4);
+ __ospi_device_1_start__ = .;
+ *(.ospi_device_1_no_load*)
+ . = ALIGN(4);
+ __ospi_device_1_end__ = .;
+ } > OSPI_DEVICE_1_RAM
+
+ /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */
+ __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0);
+
+ /* OSPI_DEVICE_0 section to be downloaded via debugger */
+ .OSPI_DEVICE_0 :
+ {
+ __ospi_device_0_start__ = .;
+ KEEP(*(.ospi_device_0*))
+ KEEP(*(.code_in_ospi_device_0*))
+ __ospi_device_0_end__ = .;
+ } > OSPI_DEVICE_0
+ __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__;
+
+ /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */
+ __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive));
+ .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__)
+ {
+ __ospi_device_0_non_retentive_start__ = .;
+ KEEP(*(.ospi_device_0_non_retentive*))
+ __ospi_device_0_non_retentive_end__ = .;
+ } > OSPI_DEVICE_0
+ __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__;
+
+ __ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */
+ __ospi_device_0_region_start_address__ = __ospi_device_0_start__;
+ __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__;
+
+ /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */
+ __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__;
+
+ /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */
+ __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1);
+
+ /* OSPI_DEVICE_1 section to be downloaded via debugger */
+ .OSPI_DEVICE_1 :
+ {
+ __ospi_device_1_start__ = .;
+ KEEP(*(.ospi_device_1*))
+ KEEP(*(.code_in_ospi_device_1*))
+ __ospi_device_1_end__ = .;
+ } > OSPI_DEVICE_1
+ __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__;
+
+ /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */
+ __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive));
+ .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__)
+ {
+ __ospi_device_1_non_retentive_start__ = .;
+ KEEP(*(.ospi_device_1_non_retentive*))
+ __ospi_device_1_non_retentive_end__ = .;
+ } > OSPI_DEVICE_1
+ __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__;
+
+ __ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */
+ __ospi_device_1_region_start_address__ = __ospi_device_1_start__;
+ __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__;
+
+ /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */
+ __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__;
+
+ .noinit (NOLOAD):
+ {
+ . = ALIGN(4);
+ __noinit_start = .;
+ KEEP(*(.noinit*))
+ . = ALIGN(8);
+ /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */
+ KEEP(*(.heap.*))
+ __noinit_end = .;
+ } > RAM
+
+ . = .;
+ __nocache_pre_location = .;
+ .nocache ALIGN(32) (NOLOAD):
+ {
+ __nocache_start = .;
+
+ KEEP(*(.nocache))
+
+ . = ALIGN(32);
+ __nocache_end = .;
+ } > RAM
+ . = (SIZEOF(.nocache) > 0) ? __nocache_end : __nocache_pre_location;
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } > RAM
+
+ .heap (NOLOAD):
+ {
+ . = ALIGN(8);
+ __HeapBase = .;
+ /* Place the STD heap here. */
+ KEEP(*(.heap))
+ __HeapLimit = .;
+ } > RAM
+
+ /* Stacks are stored in this section. */
+ .stack_dummy (NOLOAD):
+ {
+ . = ALIGN(8);
+ __StackLimit = .;
+ /* Main stack */
+ KEEP(*(.stack))
+ __StackTop = .;
+ /* Thread stacks */
+ KEEP(*(.stack*))
+ __StackTopAll = .;
+ } > RAM
+
+ PROVIDE(__stack = __StackTopAll);
+
+ /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used
+ at run time for things such as ThreadX memory pool allocations. */
+ __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4);
+
+ /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects.
+ * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary.
+ * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */
+ __RAM_NSC_START = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024);
+
+ /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects.
+ * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not
+ * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary.
+ * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */
+ __tz_RAM_N = DEFINED(FLASH_BOOTLOADER_LENGTH) ? (RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH) : DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_NSC_START, 8192);
+
+ /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects.
+ * The EDMAC is a non-secure bus master and can only access non-secure RAM. */
+ .ns_buffer (NOLOAD):
+ {
+ /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */
+ . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .;
+
+ KEEP(*(.ns_buffer*))
+ } > RAM
+
+ /* Data flash. */
+ .data_flash :
+ {
+ . = ORIGIN(DATA_FLASH);
+ __tz_DATA_FLASH_S = .;
+ __Data_Flash_Start = .;
+ KEEP(*(.data_flash*))
+ __Data_Flash_End = .;
+
+ __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024);
+ } > DATA_FLASH
+
+ /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */
+ __tz_SDRAM_S = ORIGIN(SDRAM);
+
+ /* SDRAM */
+ .sdram (NOLOAD):
+ {
+ __SDRAM_Start = .;
+ KEEP(*(.sdram*))
+ KEEP(*(.frame*))
+ __SDRAM_End = .;
+ } > SDRAM
+
+ . = .;
+ __nocache_sdram_pre_location = .;
+ .nocache_sdram ALIGN(32) (NOLOAD):
+ {
+ __nocache_sdram_start = .;
+
+ KEEP(*(.nocache_sdram))
+
+ . = ALIGN(32);
+ __nocache_sdram_end = .;
+ } > SDRAM
+ . = (SIZEOF(.nocache_sdram) > 0) ? __nocache_sdram_end : __nocache_sdram_pre_location;
+
+ /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */
+ __tz_SDRAM_N = __SDRAM_End;
+
+ /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */
+ __tz_ID_CODE_S = ORIGIN(ID_CODE);
+
+ /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool.
+ * Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE
+ * memory region between TrustZone projects. */
+ __tz_ID_CODE_N = __tz_ID_CODE_S;
+
+ .id_code :
+ {
+ __ID_Code_Start = .;
+ KEEP(*(.id_code*))
+ __ID_Code_End = .;
+ } > ID_CODE
+
+ /* Symbol required for RA Configuration tool. */
+ __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS);
+
+ .option_setting_ofs :
+ {
+ __OPTION_SETTING_OFS_Start = .;
+ KEEP(*(.option_setting_ofs0))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start;
+ KEEP(*(.option_setting_ofs2))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start;
+ KEEP(*(.option_setting_dualsel))
+ __OPTION_SETTING_OFS_End = .;
+ } > OPTION_SETTING_OFS = 0xFF
+
+ .option_setting_sas :
+ {
+ __OPTION_SETTING_SAS_Start = .;
+ KEEP(*(.option_setting_sas))
+ __OPTION_SETTING_SAS_End = .;
+ } > OPTION_SETTING_SAS = 0xFF
+
+ /* Symbol required for RA Configuration tool. */
+ __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS);
+
+ .option_setting_ns :
+ {
+ __OPTION_SETTING_NS_Start = .;
+ KEEP(*(.option_setting_ofs1))
+ . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start;
+ KEEP(*(.option_setting_ofs3))
+ . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start;
+ KEEP(*(.option_setting_banksel))
+ . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start;
+ KEEP(*(.option_setting_bps0))
+ . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start;
+ KEEP(*(.option_setting_bps1))
+ . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start;
+ KEEP(*(.option_setting_bps2))
+ . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start;
+ KEEP(*(.option_setting_bps3))
+ . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start;
+ KEEP(*(.option_setting_pbps0))
+ . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start;
+ KEEP(*(.option_setting_pbps1))
+ . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start;
+ KEEP(*(.option_setting_pbps2))
+ . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start;
+ KEEP(*(.option_setting_pbps3))
+ __OPTION_SETTING_NS_End = .;
+ } > OPTION_SETTING = 0xFF
+
+ /* Symbol required for RA Configuration tool. */
+ __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S);
+
+ .option_setting_s :
+ {
+ __OPTION_SETTING_S_Start = .;
+ KEEP(*(.option_setting_ofs1_sec))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_ofs3_sec))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_banksel_sec))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_bps_sec0))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_bps_sec1))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_bps_sec2))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_bps_sec3))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_pbps_sec0))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_pbps_sec1))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_pbps_sec2))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_pbps_sec3))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_ofs1_sel))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_ofs3_sel))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_banksel_sel))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_bps_sel0))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_bps_sel1))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_bps_sel2))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_bps_sel3))
+ __OPTION_SETTING_S_End = .;
+ } > OPTION_SETTING_S = 0xFF
+
+ /* Symbol required for RA Configuration tool. */
+ __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End;
+ /* Symbol required for RA Configuration tool. */
+ __tz_OPTION_SETTING_DATA_FLASH_S_S = ORIGIN(OPTION_SETTING_DATA_FLASH_S);
+
+ .option_setting_data_flash_s :
+ {
+ __OPTION_SETTING_DATA_FLASH_S_Start = .;
+ KEEP(*(.option_setting_data_flash_fsblctrl0))
+ . = USE_OPTION_SETTING_DATA_FLASH ? __OPTION_SETTING_DATA_FLASH_S_Start + 0x04 : __OPTION_SETTING_DATA_FLASH_S_Start;
+ KEEP(*(.option_setting_data_flash_fsblctrl1))
+ . = USE_OPTION_SETTING_DATA_FLASH ? __OPTION_SETTING_DATA_FLASH_S_Start + 0x08 : __OPTION_SETTING_DATA_FLASH_S_Start;
+ KEEP(*(.option_setting_data_flash_fsblctrl2))
+ . = USE_OPTION_SETTING_DATA_FLASH ? __OPTION_SETTING_DATA_FLASH_S_Start + 0x0C : __OPTION_SETTING_DATA_FLASH_S_Start;
+ KEEP(*(.option_setting_data_flash_sacc0))
+ . = USE_OPTION_SETTING_DATA_FLASH ? __OPTION_SETTING_DATA_FLASH_S_Start + 0x10 : __OPTION_SETTING_DATA_FLASH_S_Start;
+ KEEP(*(.option_setting_data_flash_sacc1))
+ . = USE_OPTION_SETTING_DATA_FLASH ? __OPTION_SETTING_DATA_FLASH_S_Start + 0x14 : __OPTION_SETTING_DATA_FLASH_S_Start;
+ KEEP(*(.option_setting_data_flash_samr))
+ . = USE_OPTION_SETTING_DATA_FLASH ? __OPTION_SETTING_DATA_FLASH_S_Start + 0x2E0 : __OPTION_SETTING_DATA_FLASH_S_Start;
+ KEEP(*(.option_setting_data_flash_hoemrtpk))
+ __OPTION_SETTING_DATA_FLASH_S_End = .;
+ } > OPTION_SETTING_DATA_FLASH_S = 0xFF
+
+ /* Symbol required for RA Configuration tool. */
+ __tz_OPTION_SETTING_DATA_FLASH_S_N = __OPTION_SETTING_DATA_FLASH_S_End;
+}
diff --git a/hw/bsp/ra/boards/ra8m1_ek/script/memory_regions.ld b/hw/bsp/ra/boards/ra8m1_ek/script/memory_regions.ld
new file mode 100644
index 0000000000..2bc162511f
--- /dev/null
+++ b/hw/bsp/ra/boards/ra8m1_ek/script/memory_regions.ld
@@ -0,0 +1,30 @@
+
+ /* generated memory regions file - do not edit */
+ RAM_START = 0x22000000;
+ RAM_LENGTH = 0xE0000;
+ FLASH_START = 0x02000000;
+ FLASH_LENGTH = 0x1F8000;
+ DATA_FLASH_START = 0x27000000;
+ DATA_FLASH_LENGTH = 0x3000;
+ OPTION_SETTING_START = 0x0300A100;
+ OPTION_SETTING_LENGTH = 0x100;
+ OPTION_SETTING_S_START = 0x0300A200;
+ OPTION_SETTING_S_LENGTH = 0x100;
+ OPTION_SETTING_DATA_FLASH_S_START = 0x27030080;
+ OPTION_SETTING_DATA_FLASH_S_LENGTH = 0x800;
+ ID_CODE_START = 0x00000000;
+ ID_CODE_LENGTH = 0x0;
+ SDRAM_START = 0x68000000;
+ SDRAM_LENGTH = 0x8000000;
+ QSPI_FLASH_START = 0x60000000;
+ QSPI_FLASH_LENGTH = 0x0;
+ OSPI_DEVICE_0_START = 0x80000000;
+ OSPI_DEVICE_0_LENGTH = 0x10000000;
+ OSPI_DEVICE_1_START = 0x90000000;
+ OSPI_DEVICE_1_LENGTH = 0x10000000;
+ ITCM_START = 0x00000000;
+ ITCM_LENGTH = 0x10000;
+ DTCM_START = 0x20000000;
+ DTCM_LENGTH = 0x10000;
+ NS_OFFSET_START = 0x10000000;
+ NS_OFFSET_LENGTH = 0x0;
diff --git a/hw/bsp/ra/boards/ra8m1_ek/smart_configurator/configuration.xml b/hw/bsp/ra/boards/ra8m1_ek/smart_configurator/configuration.xml
new file mode 100644
index 0000000000..0f83b4a11d
--- /dev/null
+++ b/hw/bsp/ra/boards/ra8m1_ek/smart_configurator/configuration.xml
@@ -0,0 +1,680 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Simple application that blinks an LED. No RTOS included.
+ Renesas.RA_baremetal_blinky.5.6.0.pack
+
+
+ Board Support Package Common Files
+ Renesas.RA.5.6.0.pack
+
+
+ I/O Port
+ Renesas.RA.5.6.0.pack
+
+
+ Arm CMSIS Version 6 - Core (M)
+ Arm.CMSIS6.6.1.0+fsp.5.6.0.pack
+
+
+ RA8M1-EK Board Support Files
+ Renesas.RA_board_ra8m1_ek.5.6.0.pack
+
+
+ Board support package for R7FA8M1AHECBD
+ Renesas.RA_mcu_ra8m1.5.6.0.pack
+
+
+ Board support package for RA8M1
+ Renesas.RA_mcu_ra8m1.5.6.0.pack
+
+
+ Board support package for RA8M1 - FSP Data
+ Renesas.RA_mcu_ra8m1.5.6.0.pack
+
+
+ Board support package for RA8M1 - Events
+ Renesas.RA_mcu_ra8m1.5.6.0.pack
+
+
+ USB Basic
+ Renesas.RA.5.6.0.pack
+
+
+ USB Peripheral Communications Device Class
+ Renesas.RA.5.6.0.pack
+
+
+
+
+
+
+
+
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+
+
diff --git a/hw/bsp/ra/boards/uno_r4/board.cmake b/hw/bsp/ra/boards/uno_r4/board.cmake
index 9d59bc4f77..3aa6045be0 100644
--- a/hw/bsp/ra/boards/uno_r4/board.cmake
+++ b/hw/bsp/ra/boards/uno_r4/board.cmake
@@ -1,13 +1,9 @@
set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor")
set(MCU_VARIANT ra4m1)
-
set(JLINK_DEVICE R7FA4M1AB)
-set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/${BOARD}.ld)
function(update_board TARGET)
target_compile_definitions(${TARGET} PUBLIC
CFG_EXAMPLE_VIDEO_READONLY
)
-# target_sources(${TARGET} PRIVATE)
-# target_include_directories(${BOARD_TARGET} PUBLIC)
endfunction()
diff --git a/hw/bsp/ra/boards/uno_r4/board.h b/hw/bsp/ra/boards/uno_r4/board.h
index 72abda27f9..2c262bb9b7 100644
--- a/hw/bsp/ra/boards/uno_r4/board.h
+++ b/hw/bsp/ra/boards/uno_r4/board.h
@@ -31,20 +31,8 @@
extern "C" {
#endif
-#define LED1 BSP_IO_PORT_01_PIN_11 // D13
-#define LED_STATE_ON 1
-
-#define SW1 BSP_IO_PORT_01_PIN_10 // D12
-#define BUTTON_STATE_ACTIVE 0
-
-static const ioport_pin_cfg_t board_pin_cfg[] = {
- {.pin = LED1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_OUTPUT},
- {.pin = SW1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_INPUT},
- // USB FS D+, D-, VBus
- {.pin = BSP_IO_PORT_04_PIN_07, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS},
- {.pin = BSP_IO_PORT_09_PIN_14, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS},
- {.pin = BSP_IO_PORT_09_PIN_15, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS},
-};
+#define LED_STATE_ON 1
+#define BUTTON_STATE_ACTIVE 0
#ifdef __cplusplus
}
diff --git a/hw/bsp/ra/boards/uno_r4/board.mk b/hw/bsp/ra/boards/uno_r4/board.mk
index b7075eec0b..f257c0000f 100644
--- a/hw/bsp/ra/boards/uno_r4/board.mk
+++ b/hw/bsp/ra/boards/uno_r4/board.mk
@@ -1,8 +1,6 @@
CPU_CORE = cortex-m4
MCU_VARIANT = ra4m1
-LD_FILE = ${BOARD_PATH}/${BOARD}.ld
-
# For flash-jlink target
JLINK_DEVICE = R7FA4M1AB
diff --git a/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_cfg.h
deleted file mode 100644
index c1d1022cc1..0000000000
--- a/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_cfg.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/* generated configuration header file - do not edit */
-#ifndef BSP_CFG_H_
-#define BSP_CFG_H_
-
-#include "bsp_clock_cfg.h"
-#include "bsp_mcu_family_cfg.h"
-#include "board_cfg.h"
-
-#undef RA_NOT_DEFINED
-#define BSP_CFG_RTOS (0)
-#if defined(_RA_BOOT_IMAGE)
-#define BSP_CFG_BOOT_IMAGE (1)
-#endif
-#define BSP_CFG_MCU_VCC_MV (3300)
-#define BSP_CFG_STACK_MAIN_BYTES (0x800)
-#define BSP_CFG_HEAP_BYTES (0x1000)
-#define BSP_CFG_PARAM_CHECKING_ENABLE (1)
-#define BSP_CFG_ASSERT (0)
-#define BSP_CFG_ERROR_LOG (0)
-
-#define BSP_CFG_PFS_PROTECT ((1))
-
-#define BSP_CFG_C_RUNTIME_INIT ((1))
-#define BSP_CFG_EARLY_INIT ((0))
-
-#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0))
-
-#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (0)
-
-#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0)
-#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0)
-#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (0)
-#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
-
-#endif /* BSP_CFG_H_ */
diff --git a/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
deleted file mode 100644
index 336918800f..0000000000
--- a/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/* generated configuration header file - do not edit */
-#ifndef BSP_MCU_DEVICE_PN_CFG_H_
-#define BSP_MCU_DEVICE_PN_CFG_H_
-#define BSP_MCU_R7FA4M1AB3CNE
-#define BSP_MCU_FEATURE_SET ('A')
-#define BSP_ROM_SIZE_BYTES (262144)
-#define BSP_RAM_SIZE_BYTES (32768)
-#define BSP_DATA_FLASH_SIZE_BYTES (8192)
-#define BSP_PACKAGE_QFN
-#define BSP_PACKAGE_PINS (48)
-#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */
diff --git a/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_mcu_family_cfg.h
deleted file mode 100644
index fc604eb3b1..0000000000
--- a/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_mcu_family_cfg.h
+++ /dev/null
@@ -1,87 +0,0 @@
-/* generated configuration header file through renesas e2 studio */
-#ifndef BSP_MCU_FAMILY_CFG_H_
-#define BSP_MCU_FAMILY_CFG_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "bsp_mcu_device_pn_cfg.h"
-#include "bsp_mcu_device_cfg.h"
-#include "bsp_mcu_info.h"
-#include "bsp_clock_cfg.h"
-
-#define BSP_MCU_GROUP_RA4M1 (1)
-#define BSP_LOCO_HZ (32768)
-#define BSP_MOCO_HZ (8000000)
-#define BSP_SUB_CLOCK_HZ (32768)
-#if BSP_CFG_HOCO_FREQUENCY == 0
- #define BSP_HOCO_HZ (24000000)
-#elif BSP_CFG_HOCO_FREQUENCY == 2
- #define BSP_HOCO_HZ (32000000)
-#elif BSP_CFG_HOCO_FREQUENCY == 4
- #define BSP_HOCO_HZ (48000000)
-#elif BSP_CFG_HOCO_FREQUENCY == 5
- #define BSP_HOCO_HZ (64000000)
-#else
- #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h"
-#endif
-#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U)
-#define BSP_VECTOR_TABLE_MAX_ENTRIES (48U)
-#define BSP_MCU_VBATT_SUPPORT (1)
-
-#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2)
-#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10)
-#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17)
-#define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26)
-#define OFS_SEQ5 (1 << 28) | (1 << 30)
-#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
-#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEC3 | (1 << 2) | (3 << 3) | (0 << 8))
-#define BSP_CFG_USE_LOW_VOLTAGE_MODE ((0))
-#define BSP_CFG_ROM_REG_MPU_PC0_ENABLE (1)
-#define BSP_CFG_ROM_REG_MPU_PC0_START (0x00FFFFFC)
-#define BSP_CFG_ROM_REG_MPU_PC0_END (0x00FFFFFF)
-#define BSP_CFG_ROM_REG_MPU_PC1_ENABLE (1)
-#define BSP_CFG_ROM_REG_MPU_PC1_START (0x00FFFFFC)
-#define BSP_CFG_ROM_REG_MPU_PC1_END (0x00FFFFFF)
-#define BSP_CFG_ROM_REG_MPU_REGION0_ENABLE (1)
-#define BSP_CFG_ROM_REG_MPU_REGION0_START (0x00FFFFFC)
-#define BSP_CFG_ROM_REG_MPU_REGION0_END (0x00FFFFFF)
-#define BSP_CFG_ROM_REG_MPU_REGION1_ENABLE (1)
-#define BSP_CFG_ROM_REG_MPU_REGION1_START (0x200FFFFC)
-#define BSP_CFG_ROM_REG_MPU_REGION1_END (0x200FFFFF)
-#define BSP_CFG_ROM_REG_MPU_REGION2_ENABLE (1)
-#define BSP_CFG_ROM_REG_MPU_REGION2_START (0x407FFFFC)
-#define BSP_CFG_ROM_REG_MPU_REGION2_END (0x407FFFFF)
-#define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1)
-#define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC)
-#define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF)
-#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT
-#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9)
-#endif
-/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */
-#define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector)
-
-/*
- ID Code
- Note: To permanently lock and disable the debug interface define the BSP_ID_CODE_PERMANENTLY_LOCKED in the compiler settings.
- WARNING: This will disable debug access to the part and cannot be reversed by a debug probe.
- */
-#if defined(BSP_ID_CODE_PERMANENTLY_LOCKED)
- #define BSP_CFG_ID_CODE_LONG_1 (0x00000000)
- #define BSP_CFG_ID_CODE_LONG_2 (0x00000000)
- #define BSP_CFG_ID_CODE_LONG_3 (0x00000000)
- #define BSP_CFG_ID_CODE_LONG_4 (0x00000000)
- #else
-/* ID CODE: FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF */
-#define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF)
-#define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF)
-#define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF)
-#define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF)
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* BSP_MCU_FAMILY_CFG_H_ */
diff --git a/hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/bsp/bsp_cfg.h
new file mode 100644
index 0000000000..4eef62a0e6
--- /dev/null
+++ b/hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/bsp/bsp_cfg.h
@@ -0,0 +1,62 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_CFG_H_
+#define BSP_CFG_H_
+#ifdef __cplusplus
+ extern "C" {
+ #endif
+
+ #include "bsp_clock_cfg.h"
+ #include "bsp_mcu_family_cfg.h"
+ #include "board_cfg.h"
+ #define RA_NOT_DEFINED 0
+ #ifndef BSP_CFG_RTOS
+ #if (RA_NOT_DEFINED) != (RA_NOT_DEFINED)
+ #define BSP_CFG_RTOS (2)
+ #elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED)
+ #define BSP_CFG_RTOS (1)
+ #else
+ #define BSP_CFG_RTOS (0)
+ #endif
+ #endif
+ #ifndef BSP_CFG_RTC_USED
+ #define BSP_CFG_RTC_USED (RA_NOT_DEFINED)
+ #endif
+ #undef RA_NOT_DEFINED
+ #if defined(_RA_BOOT_IMAGE)
+ #define BSP_CFG_BOOT_IMAGE (1)
+ #endif
+ #define BSP_CFG_MCU_VCC_MV (3300)
+ #define BSP_CFG_STACK_MAIN_BYTES (0x800)
+ #define BSP_CFG_HEAP_BYTES (0x1000)
+ #define BSP_CFG_PARAM_CHECKING_ENABLE (0)
+ #define BSP_CFG_ASSERT (0)
+ #define BSP_CFG_ERROR_LOG (0)
+
+ #define BSP_CFG_PFS_PROTECT ((1))
+
+ #define BSP_CFG_C_RUNTIME_INIT ((1))
+ #define BSP_CFG_EARLY_INIT ((0))
+
+ #define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0))
+
+ #ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED
+ #define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (0)
+ #endif
+
+ #ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE
+ #define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0)
+ #endif
+ #ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE
+ #define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0)
+ #endif
+ #ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED
+ #define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (0)
+ #endif
+ #ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS
+ #define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000
+ #endif
+
+ #ifdef __cplusplus
+ }
+ #endif
+#endif /* BSP_CFG_H_ */
diff --git a/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_mcu_device_cfg.h b/hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h
similarity index 100%
rename from hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_mcu_device_cfg.h
rename to hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h
diff --git a/hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
new file mode 100644
index 0000000000..3f1d02b0db
--- /dev/null
+++ b/hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h
@@ -0,0 +1,11 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_MCU_DEVICE_PN_CFG_H_
+#define BSP_MCU_DEVICE_PN_CFG_H_
+#define BSP_MCU_R7FA4M1AB3CNE
+ #define BSP_MCU_FEATURE_SET ('A')
+ #define BSP_ROM_SIZE_BYTES (262144)
+ #define BSP_RAM_SIZE_BYTES (32768)
+ #define BSP_DATA_FLASH_SIZE_BYTES (8192)
+ #define BSP_PACKAGE_QFN
+ #define BSP_PACKAGE_PINS (48)
+#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */
diff --git a/hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h
new file mode 100644
index 0000000000..3d482b2b6e
--- /dev/null
+++ b/hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h
@@ -0,0 +1,84 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_MCU_FAMILY_CFG_H_
+#define BSP_MCU_FAMILY_CFG_H_
+#ifdef __cplusplus
+ extern "C" {
+ #endif
+
+ #include "bsp_mcu_device_pn_cfg.h"
+ #include "bsp_mcu_device_cfg.h"
+ #include "../../../ra/fsp/src/bsp/mcu/ra4m1/bsp_mcu_info.h"
+ #include "bsp_clock_cfg.h"
+ #define BSP_MCU_GROUP_RA4M1 (1)
+ #define BSP_LOCO_HZ (32768)
+ #define BSP_MOCO_HZ (8000000)
+ #define BSP_SUB_CLOCK_HZ (32768)
+ #if BSP_CFG_HOCO_FREQUENCY == 0
+ #define BSP_HOCO_HZ (24000000)
+ #elif BSP_CFG_HOCO_FREQUENCY == 2
+ #define BSP_HOCO_HZ (32000000)
+ #elif BSP_CFG_HOCO_FREQUENCY == 4
+ #define BSP_HOCO_HZ (48000000)
+ #elif BSP_CFG_HOCO_FREQUENCY == 5
+ #define BSP_HOCO_HZ (64000000)
+ #else
+ #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h"
+ #endif
+ #define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U)
+ #define BSP_VECTOR_TABLE_MAX_ENTRIES (48U)
+ #define BSP_CFG_INLINE_IRQ_FUNCTIONS (1)
+
+ #define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2)
+ #define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10)
+ #define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17)
+ #define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26)
+ #define OFS_SEQ5 (1 << 28) | (1 << 30)
+ #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5)
+ #define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEC3 | (1 << 2) | (3 << 3) | (0 << 8))
+ #define BSP_CFG_USE_LOW_VOLTAGE_MODE ((0))
+ #define BSP_CFG_ROM_REG_MPU_PC0_ENABLE (1)
+ #define BSP_CFG_ROM_REG_MPU_PC0_START (0x00FFFFFC)
+ #define BSP_CFG_ROM_REG_MPU_PC0_END (0x00FFFFFF)
+ #define BSP_CFG_ROM_REG_MPU_PC1_ENABLE (1)
+ #define BSP_CFG_ROM_REG_MPU_PC1_START (0x00FFFFFC)
+ #define BSP_CFG_ROM_REG_MPU_PC1_END (0x00FFFFFF)
+ #define BSP_CFG_ROM_REG_MPU_REGION0_ENABLE (1)
+ #define BSP_CFG_ROM_REG_MPU_REGION0_START (0x00FFFFFC)
+ #define BSP_CFG_ROM_REG_MPU_REGION0_END (0x00FFFFFF)
+ #define BSP_CFG_ROM_REG_MPU_REGION1_ENABLE (1)
+ #define BSP_CFG_ROM_REG_MPU_REGION1_START (0x200FFFFC)
+ #define BSP_CFG_ROM_REG_MPU_REGION1_END (0x200FFFFF)
+ #define BSP_CFG_ROM_REG_MPU_REGION2_ENABLE (1)
+ #define BSP_CFG_ROM_REG_MPU_REGION2_START (0x407FFFFC)
+ #define BSP_CFG_ROM_REG_MPU_REGION2_END (0x407FFFFF)
+ #define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1)
+ #define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC)
+ #define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF)
+ #ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT
+ #define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9)
+ #endif
+ /* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */
+ #define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector)
+
+ /*
+ ID Code
+ Note: To permanently lock and disable the debug interface define the BSP_ID_CODE_PERMANENTLY_LOCKED in the compiler settings.
+ WARNING: This will disable debug access to the part and cannot be reversed by a debug probe.
+ */
+ #if defined(BSP_ID_CODE_PERMANENTLY_LOCKED)
+ #define BSP_CFG_ID_CODE_LONG_1 (0x00000000)
+ #define BSP_CFG_ID_CODE_LONG_2 (0x00000000)
+ #define BSP_CFG_ID_CODE_LONG_3 (0x00000000)
+ #define BSP_CFG_ID_CODE_LONG_4 (0x00000000)
+ #else
+ /* ID CODE: FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF */
+ #define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF)
+ #define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF)
+ #define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF)
+ #define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF)
+ #endif
+
+ #ifdef __cplusplus
+ }
+ #endif
+#endif /* BSP_MCU_FAMILY_CFG_H_ */
diff --git a/hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h b/hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h
new file mode 100644
index 0000000000..5440b293b3
--- /dev/null
+++ b/hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h
@@ -0,0 +1,17 @@
+/* generated configuration header file - do not edit */
+#ifndef BSP_PIN_CFG_H_
+#define BSP_PIN_CFG_H_
+#include "r_ioport.h"
+
+/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */
+FSP_HEADER
+
+#define SW1 (BSP_IO_PORT_01_PIN_10) /* active low */
+#define LED1 (BSP_IO_PORT_01_PIN_11) /* active high */
+extern const ioport_cfg_t g_bsp_pin_cfg; /* R7FA4M1AB3CNE.pincfg */
+
+void BSP_PinConfigSecurityInit();
+
+/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */
+FSP_FOOTER
+#endif /* BSP_PIN_CFG_H_ */
diff --git a/hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/r_ioport_cfg.h b/hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/r_ioport_cfg.h
new file mode 100644
index 0000000000..d2688bf5ba
--- /dev/null
+++ b/hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/r_ioport_cfg.h
@@ -0,0 +1,13 @@
+/* generated configuration header file - do not edit */
+#ifndef R_IOPORT_CFG_H_
+#define R_IOPORT_CFG_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE)
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* R_IOPORT_CFG_H_ */
diff --git a/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp_clock_cfg.h b/hw/bsp/ra/boards/uno_r4/ra_gen/bsp_clock_cfg.h
similarity index 92%
rename from hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp_clock_cfg.h
rename to hw/bsp/ra/boards/uno_r4/ra_gen/bsp_clock_cfg.h
index 63618ec4bb..559000a7a7 100644
--- a/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp_clock_cfg.h
+++ b/hw/bsp/ra/boards/uno_r4/ra_gen/bsp_clock_cfg.h
@@ -4,10 +4,10 @@
#define BSP_CFG_CLOCKS_SECURE (0)
#define BSP_CFG_CLOCKS_OVERRIDE (0)
#define BSP_CFG_XTAL_HZ (0) /* XTAL 0Hz */
-#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* PLL Src: XTAL */
+#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* PLL Src: Disabled */
#define BSP_CFG_HOCO_FREQUENCY (4) /* HOCO 48MHz */
#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_4) /* PLL Div /4 */
-#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(12, 0) /* PLL Mul x12 */
+#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(12U,0U) /* PLL Mul x12 */
#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_HOCO) /* Clock Src: HOCO */
#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* ICLK Div /1 */
#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKA Div /1 */
@@ -15,7 +15,7 @@
#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKC Div /1 */
#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKD Div /1 */
#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* FCLK Div /2 */
-#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Src: SUBCLK */
+#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */
#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */
#define BSP_CFG_UCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_HOCO) /* UCLK Src: HOCO */
#endif /* BSP_CLOCK_CFG_H_ */
diff --git a/hw/bsp/ra/boards/uno_r4/ra_gen/common_data.c b/hw/bsp/ra/boards/uno_r4/ra_gen/common_data.c
new file mode 100644
index 0000000000..50036c0adc
--- /dev/null
+++ b/hw/bsp/ra/boards/uno_r4/ra_gen/common_data.c
@@ -0,0 +1,11 @@
+/* generated common source file - do not edit */
+#include "common_data.h"
+ioport_instance_ctrl_t g_ioport_ctrl;
+const ioport_instance_t g_ioport =
+ {
+ .p_api = &g_ioport_on_ioport,
+ .p_ctrl = &g_ioport_ctrl,
+ .p_cfg = &g_bsp_pin_cfg,
+ };
+void g_common_init(void) {
+}
diff --git a/hw/bsp/ra/boards/uno_r4/ra_gen/common_data.h b/hw/bsp/ra/boards/uno_r4/ra_gen/common_data.h
new file mode 100644
index 0000000000..6a08cbee09
--- /dev/null
+++ b/hw/bsp/ra/boards/uno_r4/ra_gen/common_data.h
@@ -0,0 +1,20 @@
+/* generated common header file - do not edit */
+#ifndef COMMON_DATA_H_
+#define COMMON_DATA_H_
+#include
+#include "bsp_api.h"
+#include "r_ioport.h"
+#include "bsp_pin_cfg.h"
+FSP_HEADER
+#define IOPORT_CFG_NAME g_bsp_pin_cfg
+#define IOPORT_CFG_OPEN R_IOPORT_Open
+#define IOPORT_CFG_CTRL g_ioport_ctrl
+
+/* IOPORT Instance */
+extern const ioport_instance_t g_ioport;
+
+/* IOPORT control structure. */
+extern ioport_instance_ctrl_t g_ioport_ctrl;
+void g_common_init(void);
+FSP_FOOTER
+#endif /* COMMON_DATA_H_ */
diff --git a/hw/bsp/ra/boards/uno_r4/ra_gen/pin_data.c b/hw/bsp/ra/boards/uno_r4/ra_gen/pin_data.c
new file mode 100644
index 0000000000..58262de8b5
--- /dev/null
+++ b/hw/bsp/ra/boards/uno_r4/ra_gen/pin_data.c
@@ -0,0 +1,75 @@
+/* generated pin source file - do not edit */
+#include "bsp_api.h"
+#include "r_ioport.h"
+
+
+const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = {
+ {
+ .pin = BSP_IO_PORT_01_PIN_08,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG)
+ },
+ {
+ .pin = BSP_IO_PORT_01_PIN_10,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT | (uint32_t) IOPORT_CFG_PULLUP_ENABLE)
+ },
+ {
+ .pin = BSP_IO_PORT_01_PIN_11,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW)
+ },
+ {
+ .pin = BSP_IO_PORT_03_PIN_00,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG)
+ },
+ {
+ .pin = BSP_IO_PORT_04_PIN_07,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)
+ },
+ {
+ .pin = BSP_IO_PORT_09_PIN_14,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)
+ },
+ {
+ .pin = BSP_IO_PORT_09_PIN_15,
+ .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS)
+ },
+};
+
+const ioport_cfg_t g_bsp_pin_cfg = {
+ .number_of_pins = sizeof(g_bsp_pin_cfg_data)/sizeof(ioport_pin_cfg_t),
+ .p_pin_cfg_data = &g_bsp_pin_cfg_data[0],
+};
+
+#if BSP_TZ_SECURE_BUILD
+
+void R_BSP_PinCfgSecurityInit(void);
+
+/* Initialize SAR registers for secure pins. */
+void R_BSP_PinCfgSecurityInit(void)
+{
+ #if (2U == BSP_FEATURE_IOPORT_VERSION)
+ uint32_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR];
+ #else
+ uint16_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR];
+ #endif
+ memset(pmsar, 0xFF, BSP_FEATURE_BSP_NUM_PMSAR * sizeof(R_PMISC->PMSAR[0]));
+
+
+ for(uint32_t i = 0; i < g_bsp_pin_cfg.number_of_pins; i++)
+ {
+ uint32_t port_pin = g_bsp_pin_cfg.p_pin_cfg_data[i].pin;
+ uint32_t port = port_pin >> 8U;
+ uint32_t pin = port_pin & 0xFFU;
+ pmsar[port] &= (uint16_t) ~(1U << pin);
+ }
+
+ for(uint32_t i = 0; i < BSP_FEATURE_BSP_NUM_PMSAR; i++)
+ {
+ #if (2U == BSP_FEATURE_IOPORT_VERSION)
+ R_PMISC->PMSAR[i].PMSAR = (uint16_t) pmsar[i];
+ #else
+ R_PMISC->PMSAR[i].PMSAR = pmsar[i];
+ #endif
+ }
+
+}
+#endif
diff --git a/hw/bsp/ra/boards/uno_r4/script/fsp.ld b/hw/bsp/ra/boards/uno_r4/script/fsp.ld
new file mode 100644
index 0000000000..605eef7d2c
--- /dev/null
+++ b/hw/bsp/ra/boards/uno_r4/script/fsp.ld
@@ -0,0 +1,769 @@
+/*
+ Linker File for Renesas FSP
+*/
+
+INCLUDE memory_regions.ld
+
+/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/
+/*
+ XIP_SECONDARY_SLOT_IMAGE = 1;
+*/
+
+QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH);
+OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH);
+OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH);
+
+/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */
+__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0);
+
+ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0;
+ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0;
+DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0;
+DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0;
+RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0;
+RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0;
+RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH;
+RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH;
+
+OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80;
+
+/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings.
+ * Bootloader images do not configure option settings because they are owned by the bootloader.
+ * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */
+__bl_FSP_BOOTABLE_IMAGE = 1;
+__bln_FSP_BOOTABLE_IMAGE = 1;
+PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE);
+USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE);
+
+__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+ FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH :
+ (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH :
+ FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH;
+__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+ FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH;
+__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH;
+__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+ FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH;
+__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH;
+__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+ FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
+ __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH;
+__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+ FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
+ __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH;
+__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+ FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH :
+ RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH;
+__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+ FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH :
+ __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH;
+__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+ FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
+ __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2;
+__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START);
+__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 :
+ FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END :
+ FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2;
+
+XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0;
+FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START :
+ XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START :
+ FLASH_IMAGE_START;
+LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH :
+ DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH :
+ FLASH_LENGTH;
+OPTION_SETTING_SAS_SIZE = 0x34;
+OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 :
+ OPTION_SETTING_LENGTH == 0 ? 0 :
+ OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE;
+
+/* Define memory regions. */
+MEMORY
+{
+ ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH
+ DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH
+ FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH
+ RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH
+ DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH
+ QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH
+ OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH
+ OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH
+ OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH
+ OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH
+ SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH
+ OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH
+ OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18
+ OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH
+ OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH
+ ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH
+}
+
+/* Library configurations */
+GROUP(libgcc.a libc.a libm.a)
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be DEFINED in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __copy_table_start__
+ * __copy_table_end__
+ * __zero_table_start__
+ * __zero_table_end__
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ * __Vectors_End
+ * __Vectors_Size
+ * __qspi_flash_start__
+ * __qspi_flash_end__
+ * __qspi_flash_code_size__
+ * __qspi_region_max_size__
+ * __qspi_region_start_address__
+ * __qspi_region_end_address__
+ * __ospi_device_0_start__
+ * __ospi_device_0_end__
+ * __ospi_device_0_code_size__
+ * __ospi_device_0_region_max_size__
+ * __ospi_device_0_region_start_address__
+ * __ospi_device_0_region_end_address__
+ * __ospi_device_1_start__
+ * __ospi_device_1_end__
+ * __ospi_device_1_code_size__
+ * __ospi_device_1_region_max_size__
+ * __ospi_device_1_region_start_address__
+ * __ospi_device_1_region_end_address__
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ __tz_FLASH_S = ABSOLUTE(FLASH_START);
+ __ROM_Start = .;
+
+ /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much
+ * space because ROM registers are at address 0x400 and there is very little space
+ * in between. */
+ KEEP(*(.fixed_vectors*))
+ KEEP(*(.application_vectors*))
+ __Vectors_End = .;
+
+ /* Some devices have a gap of code flash between the vector table and ROM Registers.
+ * The flash gap section allows applications to place code and data in this section. */
+ *(.flash_gap*)
+
+ /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */
+ . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400;
+ KEEP(*(.rom_registers*))
+
+ /* Reserving 0x100 bytes of space for ROM registers. */
+ . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x500;
+
+ /* Allocate flash write-boundary-aligned
+ * space for sce9 wrapped public keys for mcuboot if the module is used.
+ */
+ KEEP(*(.mcuboot_sce9_key*))
+
+ *(.text*)
+
+ KEEP(*(.version))
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+ __usb_dev_descriptor_start_fs = .;
+ KEEP(*(.usb_device_desc_fs*))
+ __usb_cfg_descriptor_start_fs = .;
+ KEEP(*(.usb_config_desc_fs*))
+ __usb_interface_descriptor_start_fs = .;
+ KEEP(*(.usb_interface_desc_fs*))
+ __usb_descriptor_end_fs = .;
+ __usb_dev_descriptor_start_hs = .;
+ KEEP(*(.usb_device_desc_hs*))
+ __usb_cfg_descriptor_start_hs = .;
+ KEEP(*(.usb_config_desc_hs*))
+ __usb_interface_descriptor_start_hs = .;
+ KEEP(*(.usb_interface_desc_hs*))
+ __usb_descriptor_end_hs = .;
+
+ KEEP(*(.eh_frame*))
+
+ __ROM_End = .;
+ } > FLASH = 0xFF
+
+ __Vectors_Size = __Vectors_End - __Vectors;
+
+ . = .;
+ __itcm_data_pre_location = .;
+
+ /* Initialized ITCM data. */
+ /* Aligned to FCACHE2 for RA8. */
+ .itcm_data : ALIGN(16)
+ {
+ /* Start of ITCM Secure Trustzone region. */
+ __tz_ITCM_S = ABSOLUTE(ITCM_START);
+
+ /* All ITCM data start */
+ __itcm_data_start = .;
+
+ KEEP(*(.itcm_data*))
+
+ /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */
+ . = ALIGN(8);
+
+ /* All ITCM data end */
+ __itcm_data_end = .;
+
+ /*
+ * Start of the ITCM Non-Secure Trustzone region.
+ * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects.
+ */
+ __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192);
+ } > ITCM AT > FLASH = 0x00
+
+ /* Addresses exported for ITCM initialization. */
+ __itcm_data_init_start = LOADADDR(.itcm_data);
+ __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data);
+
+ ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.")
+ ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.")
+ ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.")
+ ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.")
+
+ /* Restore location counter. */
+ /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */
+ /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */
+ . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location;
+
+ __exidx_start = .;
+ /DISCARD/ :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ }
+ __exidx_end = .;
+
+ /* To copy multiple ROM to RAM sections,
+ * uncomment .copy.table section and,
+ * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */
+ /*
+ .copy.table :
+ {
+ . = ALIGN(4);
+ __copy_table_start__ = .;
+ LONG (__etext)
+ LONG (__data_start__)
+ LONG (__data_end__ - __data_start__)
+ LONG (__etext2)
+ LONG (__data2_start__)
+ LONG (__data2_end__ - __data2_start__)
+ __copy_table_end__ = .;
+ } > FLASH
+ */
+
+ /* To clear multiple BSS sections,
+ * uncomment .zero.table section and,
+ * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */
+ /*
+ .zero.table :
+ {
+ . = ALIGN(4);
+ __zero_table_start__ = .;
+ LONG (__bss_start__)
+ LONG (__bss_end__ - __bss_start__)
+ LONG (__bss2_start__)
+ LONG (__bss2_end__ - __bss2_start__)
+ __zero_table_end__ = .;
+ } > FLASH
+ */
+
+ __etext = .;
+
+ __tz_RAM_S = ORIGIN(RAM);
+
+ /* If DTC is used, put the DTC vector table at the start of SRAM.
+ This avoids memory holes due to 1K alignment required by it. */
+ .fsp_dtc_vector_table (NOLOAD) :
+ {
+ . = ORIGIN(RAM);
+ *(.fsp_dtc_vector_table)
+ } > RAM
+
+ /* Initialized data section. */
+ .data :
+ {
+ __data_start__ = .;
+ . = ALIGN(4);
+
+ __Code_In_RAM_Start = .;
+
+ KEEP(*(.code_in_ram*))
+ __Code_In_RAM_End = .;
+
+ *(vtable)
+ /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */
+ *(.data.*)
+ *(.data)
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+
+ . = ALIGN(4);
+
+ /* All data end */
+ __data_end__ = .;
+
+ } > RAM AT > FLASH
+
+ . = .;
+ __dtcm_data_pre_location = LOADADDR(.data) + SIZEOF(.data);
+
+ /* Initialized DTCM data. */
+ /* Aligned to FCACHE2 for RA8. */
+ .dtcm_data : ALIGN(16)
+ {
+ /* Start of DTCM Secure Trustzone region. */
+ __tz_DTCM_S = ABSOLUTE(DTCM_START);
+
+ /* Initialized DTCM data start */
+ __dtcm_data_start = .;
+
+ KEEP(*(.dtcm_data*))
+
+ /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */
+ . = ALIGN(8);
+
+ /* Initialized DTCM data end */
+ __dtcm_data_end = .;
+ } > DTCM AT > FLASH = 0x00
+
+ . = __dtcm_data_end;
+ /* Uninitialized DTCM data. */
+ /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */
+ .dtcm_bss ALIGN(8) (NOLOAD) :
+ {
+ /* Uninitialized DTCM data start */
+ __dtcm_bss_start = .;
+
+ KEEP(*(.dtcm_bss*))
+
+ /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */
+ . = ALIGN(8);
+
+ /* Uninitialized DTCM data end */
+ __dtcm_bss_end = .;
+
+ /*
+ * Start of the DTCM Non-Secure Trustzone region.
+ * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects.
+ */
+ __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192);
+ } > DTCM
+
+ /* Addresses exported for DTCM initialization. */
+ __dtcm_data_init_start = LOADADDR(.dtcm_data);
+ __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data);
+
+ ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.")
+ ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.")
+ ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).")
+ ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.")
+ ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.")
+ ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.")
+ ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.")
+ ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.")
+
+ /* Restore location counter. */
+ /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */
+ /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */
+ . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location;
+
+ /* TrustZone Secure Gateway Stubs Section */
+
+ /* Store location counter for SPI non-retentive sections. */
+ sgstubs_pre_location = .;
+
+ /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */
+ SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024);
+ .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024)
+ {
+ __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024);
+ _start_sg = .;
+ *(.gnu.sgstubs*)
+ . = ALIGN(32);
+ _end_sg = .;
+ } > FLASH
+
+ __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768);
+ FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N;
+
+ /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */
+ __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH);
+
+ /* QSPI_FLASH section to be downloaded via debugger */
+ .qspi_flash :
+ {
+ __qspi_flash_start__ = .;
+ KEEP(*(.qspi_flash*))
+ KEEP(*(.code_in_qspi*))
+ __qspi_flash_end__ = .;
+ } > QSPI_FLASH
+ __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__;
+
+ /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */
+ __qspi_flash_code_addr__ = sgstubs_pre_location;
+ .qspi_non_retentive : AT(__qspi_flash_code_addr__)
+ {
+ __qspi_non_retentive_start__ = .;
+ KEEP(*(.qspi_non_retentive*))
+ __qspi_non_retentive_end__ = .;
+ } > QSPI_FLASH
+ __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__;
+
+ __qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */
+ __qspi_region_start_address__ = __qspi_flash_start__;
+ __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__;
+
+ /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */
+ __tz_QSPI_FLASH_N = __qspi_non_retentive_end__;
+
+ /* Support for OctaRAM */
+ .OSPI_DEVICE_0_NO_LOAD (NOLOAD):
+ {
+ . = ALIGN(4);
+ __ospi_device_0_start__ = .;
+ *(.ospi_device_0_no_load*)
+ . = ALIGN(4);
+ __ospi_device_0_end__ = .;
+ } > OSPI_DEVICE_0_RAM
+
+ .OSPI_DEVICE_1_NO_LOAD (NOLOAD):
+ {
+ . = ALIGN(4);
+ __ospi_device_1_start__ = .;
+ *(.ospi_device_1_no_load*)
+ . = ALIGN(4);
+ __ospi_device_1_end__ = .;
+ } > OSPI_DEVICE_1_RAM
+
+ /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */
+ __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0);
+
+ /* OSPI_DEVICE_0 section to be downloaded via debugger */
+ .OSPI_DEVICE_0 :
+ {
+ __ospi_device_0_start__ = .;
+ KEEP(*(.ospi_device_0*))
+ KEEP(*(.code_in_ospi_device_0*))
+ __ospi_device_0_end__ = .;
+ } > OSPI_DEVICE_0
+ __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__;
+
+ /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */
+ __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive));
+ .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__)
+ {
+ __ospi_device_0_non_retentive_start__ = .;
+ KEEP(*(.ospi_device_0_non_retentive*))
+ __ospi_device_0_non_retentive_end__ = .;
+ } > OSPI_DEVICE_0
+ __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__;
+
+ __ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */
+ __ospi_device_0_region_start_address__ = __ospi_device_0_start__;
+ __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__;
+
+ /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */
+ __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__;
+
+ /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */
+ __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1);
+
+ /* OSPI_DEVICE_1 section to be downloaded via debugger */
+ .OSPI_DEVICE_1 :
+ {
+ __ospi_device_1_start__ = .;
+ KEEP(*(.ospi_device_1*))
+ KEEP(*(.code_in_ospi_device_1*))
+ __ospi_device_1_end__ = .;
+ } > OSPI_DEVICE_1
+ __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__;
+
+ /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */
+ __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive));
+ .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__)
+ {
+ __ospi_device_1_non_retentive_start__ = .;
+ KEEP(*(.ospi_device_1_non_retentive*))
+ __ospi_device_1_non_retentive_end__ = .;
+ } > OSPI_DEVICE_1
+ __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__;
+
+ __ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */
+ __ospi_device_1_region_start_address__ = __ospi_device_1_start__;
+ __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__;
+
+ /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */
+ __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__;
+
+ .noinit (NOLOAD):
+ {
+ . = ALIGN(4);
+ __noinit_start = .;
+ KEEP(*(.noinit*))
+ . = ALIGN(8);
+ /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */
+ KEEP(*(.heap.*))
+ __noinit_end = .;
+ } > RAM
+
+ .bss :
+ {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } > RAM
+
+ .heap (NOLOAD):
+ {
+ . = ALIGN(8);
+ __HeapBase = .;
+ /* Place the STD heap here. */
+ KEEP(*(.heap))
+ __HeapLimit = .;
+ } > RAM
+
+ /* Stacks are stored in this section. */
+ .stack_dummy (NOLOAD):
+ {
+ . = ALIGN(8);
+ __StackLimit = .;
+ /* Main stack */
+ KEEP(*(.stack))
+ __StackTop = .;
+ /* Thread stacks */
+ KEEP(*(.stack*))
+ __StackTopAll = .;
+ } > RAM
+
+ PROVIDE(__stack = __StackTopAll);
+
+ /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used
+ at run time for things such as ThreadX memory pool allocations. */
+ __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4);
+
+ /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects.
+ * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary.
+ * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */
+ __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024);
+
+ /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects.
+ * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not
+ * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary.
+ * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */
+ __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192);
+
+ /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects.
+ * The EDMAC is a non-secure bus master and can only access non-secure RAM. */
+ .ns_buffer (NOLOAD):
+ {
+ /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */
+ . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .;
+
+ KEEP(*(.ns_buffer*))
+ } > RAM
+
+ /* Data flash. */
+ .data_flash :
+ {
+ . = ORIGIN(DATA_FLASH);
+ __tz_DATA_FLASH_S = .;
+ __Data_Flash_Start = .;
+ KEEP(*(.data_flash*))
+ __Data_Flash_End = .;
+
+ __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024);
+ } > DATA_FLASH
+
+ /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */
+ __tz_SDRAM_S = ORIGIN(SDRAM);
+
+ /* SDRAM */
+ .sdram (NOLOAD):
+ {
+ __SDRAM_Start = .;
+ KEEP(*(.sdram*))
+ KEEP(*(.frame*))
+ __SDRAM_End = .;
+ } > SDRAM
+
+ /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */
+ __tz_SDRAM_N = __SDRAM_End;
+
+ /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */
+ __tz_ID_CODE_S = ORIGIN(ID_CODE);
+
+ /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool.
+ * Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE
+ * memory region between TrustZone projects. */
+ __tz_ID_CODE_N = __tz_ID_CODE_S;
+
+ .id_code :
+ {
+ __ID_Code_Start = .;
+ KEEP(*(.id_code*))
+ __ID_Code_End = .;
+ } > ID_CODE
+
+ /* Symbol required for RA Configuration tool. */
+ __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS);
+
+ .option_setting_ofs :
+ {
+ __OPTION_SETTING_OFS_Start = .;
+ KEEP(*(.option_setting_ofs0))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start;
+ KEEP(*(.option_setting_ofs2))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start;
+ KEEP(*(.option_setting_dualsel))
+ __OPTION_SETTING_OFS_End = .;
+ } > OPTION_SETTING_OFS = 0xFF
+
+ .option_setting_sas :
+ {
+ __OPTION_SETTING_SAS_Start = .;
+ KEEP(*(.option_setting_sas))
+ __OPTION_SETTING_SAS_End = .;
+ } > OPTION_SETTING_SAS = 0xFF
+
+ /* Symbol required for RA Configuration tool. */
+ __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS);
+
+ .option_setting_ns :
+ {
+ __OPTION_SETTING_NS_Start = .;
+ KEEP(*(.option_setting_ofs1))
+ . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start;
+ KEEP(*(.option_setting_ofs3))
+ . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start;
+ KEEP(*(.option_setting_banksel))
+ . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start;
+ KEEP(*(.option_setting_bps0))
+ . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start;
+ KEEP(*(.option_setting_bps1))
+ . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start;
+ KEEP(*(.option_setting_bps2))
+ . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start;
+ KEEP(*(.option_setting_bps3))
+ . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start;
+ KEEP(*(.option_setting_pbps0))
+ . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start;
+ KEEP(*(.option_setting_pbps1))
+ . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start;
+ KEEP(*(.option_setting_pbps2))
+ . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start;
+ KEEP(*(.option_setting_pbps3))
+ __OPTION_SETTING_NS_End = .;
+ } > OPTION_SETTING = 0xFF
+
+ /* Symbol required for RA Configuration tool. */
+ __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S);
+
+ .option_setting_s :
+ {
+ __OPTION_SETTING_S_Start = .;
+ KEEP(*(.option_setting_ofs1_sec))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_ofs3_sec))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_banksel_sec))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_bps_sec0))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_bps_sec1))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_bps_sec2))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_bps_sec3))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_pbps_sec0))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_pbps_sec1))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_pbps_sec2))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_pbps_sec3))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_ofs1_sel))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_ofs3_sel))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_banksel_sel))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_bps_sel0))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_bps_sel1))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_bps_sel2))
+ . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start;
+ KEEP(*(.option_setting_bps_sel3))
+ __OPTION_SETTING_S_End = .;
+ } > OPTION_SETTING_S = 0xFF
+
+ /* Symbol required for RA Configuration tool. */
+ __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End;
+}
diff --git a/hw/bsp/ra/boards/uno_r4/script/memory_regions.ld b/hw/bsp/ra/boards/uno_r4/script/memory_regions.ld
new file mode 100644
index 0000000000..22775395c8
--- /dev/null
+++ b/hw/bsp/ra/boards/uno_r4/script/memory_regions.ld
@@ -0,0 +1,25 @@
+
+ /* generated memory regions file - do not edit */
+ RAM_START = 0x20000000;
+ RAM_LENGTH = 0x8000;
+ FLASH_START = 0x00000000;
+ FLASH_LENGTH = 0x40000;
+ DATA_FLASH_START = 0x40100000;
+ DATA_FLASH_LENGTH = 0x2000;
+ OPTION_SETTING_START = 0x00000000;
+ OPTION_SETTING_LENGTH = 0x0;
+ OPTION_SETTING_S_START = 0x80000000;
+ OPTION_SETTING_S_LENGTH = 0x0;
+ ID_CODE_START = 0x01010018;
+ ID_CODE_LENGTH = 0x20;
+ SDRAM_START = 0x80010000;
+ SDRAM_LENGTH = 0x0;
+ QSPI_FLASH_START = 0x60000000;
+ QSPI_FLASH_LENGTH = 0x0;
+ OSPI_DEVICE_0_START = 0x80020000;
+ OSPI_DEVICE_0_LENGTH = 0x0;
+ OSPI_DEVICE_1_START = 0x80030000;
+ OSPI_DEVICE_1_LENGTH = 0x0;
+
+/* Uno R4 has bootloader */
+FLASH_IMAGE_START = 0x4000;
diff --git a/hw/bsp/ra/boards/uno_r4/smart_configurator/configuration.xml b/hw/bsp/ra/boards/uno_r4/smart_configurator/configuration.xml
new file mode 100644
index 0000000000..b716c8ec91
--- /dev/null
+++ b/hw/bsp/ra/boards/uno_r4/smart_configurator/configuration.xml
@@ -0,0 +1,218 @@
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Board Support Package Common Files
+ Renesas.RA.5.6.0.pack
+
+
+ I/O Port
+ Renesas.RA.5.6.0.pack
+
+
+ Arm CMSIS Version 6 - Core (M)
+ Arm.CMSIS6.6.1.0+fsp.5.6.0.pack
+
+
+ Custom Board Support Files
+ Renesas.RA_board_custom.5.6.0.pack
+
+
+ Board support package for R7FA4M1AB3CNE
+ Renesas.RA_mcu_ra4m1.5.6.0.pack
+
+
+ Board support package for RA4M1
+ Renesas.RA_mcu_ra4m1.5.6.0.pack
+
+
+ Board support package for RA4M1 - FSP Data
+ Renesas.RA_mcu_ra4m1.5.6.0.pack
+
+
+ Board support package for RA4M1 - Events
+ Renesas.RA_mcu_ra4m1.5.6.0.pack
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/hw/bsp/ra/boards/uno_r4/uno_r4.ld b/hw/bsp/ra/boards/uno_r4/uno_r4.ld
deleted file mode 100644
index 45f11dfb18..0000000000
--- a/hw/bsp/ra/boards/uno_r4/uno_r4.ld
+++ /dev/null
@@ -1,25 +0,0 @@
-RAM_START = 0x20000000;
-RAM_LENGTH = 0x8000;
-FLASH_START = 0x00000000;
-FLASH_LENGTH = 0x40000;
-DATA_FLASH_START = 0x40100000;
-DATA_FLASH_LENGTH = 0x2000;
-OPTION_SETTING_START = 0x00000000;
-OPTION_SETTING_LENGTH = 0x0;
-OPTION_SETTING_S_START = 0x80000000;
-OPTION_SETTING_S_LENGTH = 0x0;
-ID_CODE_START = 0x01010018;
-ID_CODE_LENGTH = 0x20;
-SDRAM_START = 0x80010000;
-SDRAM_LENGTH = 0x0;
-QSPI_FLASH_START = 0x60000000;
-QSPI_FLASH_LENGTH = 0x0;
-OSPI_DEVICE_0_START = 0x80020000;
-OSPI_DEVICE_0_LENGTH = 0x0;
-OSPI_DEVICE_1_START = 0x80030000;
-OSPI_DEVICE_1_LENGTH = 0x0;
-
-/* Uno R4 has bootloader */
-FLASH_IMAGE_START = 0x4000;
-
-INCLUDE fsp.ld
diff --git a/hw/bsp/ra/family.c b/hw/bsp/ra/family.c
index 87f7b4a22a..523b6ff558 100644
--- a/hw/bsp/ra/family.c
+++ b/hw/bsp/ra/family.c
@@ -30,14 +30,9 @@
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wstrict-prototypes"
#pragma GCC diagnostic ignored "-Wundef"
-
-// extra push due to https://github.com/renesas/fsp/pull/278
-#pragma GCC diagnostic push
#endif
-#include "bsp_api.h"
-#include "r_ioport.h"
-#include "r_ioport_api.h"
+#include "common_data.h"
#include "renesas.h"
#ifdef __GNUC__
@@ -50,12 +45,6 @@
/* Key code for writing PRCR register. */
#define BSP_PRV_PRCR_KEY (0xA500U)
-static const ioport_cfg_t family_pin_cfg = {
- .number_of_pins = sizeof(board_pin_cfg) / sizeof(ioport_pin_cfg_t),
- .p_pin_cfg_data = board_pin_cfg,
-};
-static ioport_instance_ctrl_t port_ctrl;
-
//--------------------------------------------------------------------+
// Vector Data
//--------------------------------------------------------------------+
@@ -103,7 +92,7 @@ void board_init(void) {
__enable_irq();
/* Configure pins. */
- R_IOPORT_Open(&port_ctrl, &family_pin_cfg);
+ R_IOPORT_Open(&IOPORT_CFG_CTRL, &IOPORT_CFG_NAME);
#ifdef TRACE_ETM
// TRCKCR is protected by PRCR bit0 register
@@ -138,12 +127,12 @@ void board_init_after_tusb(void) {
}
void board_led_write(bool state) {
- R_IOPORT_PinWrite(&port_ctrl, LED1, state ? LED_STATE_ON : !LED_STATE_ON);
+ R_IOPORT_PinWrite(&IOPORT_CFG_CTRL, LED1, state ? LED_STATE_ON : !LED_STATE_ON);
}
uint32_t board_button_read(void) {
bsp_io_level_t lvl = !BUTTON_STATE_ACTIVE;
- R_IOPORT_PinRead(&port_ctrl, SW1, &lvl);
+ R_IOPORT_PinRead(&IOPORT_CFG_CTRL, SW1, &lvl);
return lvl == BUTTON_STATE_ACTIVE;
}
@@ -211,7 +200,6 @@ void usbfs_d1fifo_handler(void) {
//------------- USB1 HighSpeed -------------//
#ifdef BOARD_HAS_USB_HIGHSPEED
-
void usbhs_interrupt_handler(void) {
IRQn_Type irq = R_FSP_CurrentIrqGet();
R_BSP_IrqStatusClear(irq);
@@ -230,7 +218,6 @@ void usbhs_d1fifo_handler(void) {
R_BSP_IrqStatusClear(irq);
// TODO not used yet
}
-
#endif
//--------------------------------------------------------------------+
diff --git a/hw/bsp/ra/family.cmake b/hw/bsp/ra/family.cmake
index 426e1ca8f6..ceb1e48bd9 100644
--- a/hw/bsp/ra/family.cmake
+++ b/hw/bsp/ra/family.cmake
@@ -4,7 +4,7 @@ if (NOT BOARD)
message(FATAL_ERROR "BOARD not specified")
endif ()
-set(CMSIS_DIR ${TOP}/lib/CMSIS_5)
+set(CMSIS_DIR ${TOP}/lib/CMSIS_6)
set(FSP_RA ${TOP}/hw/mcu/renesas/fsp/ra/fsp)
# include board specific
@@ -15,6 +15,28 @@ set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOL
set(FAMILY_MCUS RAXXX ${MCU_VARIANT} CACHE INTERNAL "")
+# ----------------------
+# Port & Speed Selection
+# ----------------------
+if (NOT DEFINED RHPORT_DEVICE)
+ set(RHPORT_DEVICE 0)
+endif ()
+if (NOT DEFINED RHPORT_HOST)
+ set(RHPORT_HOST 0)
+endif ()
+
+if (NOT DEFINED RHPORT_SPEED)
+ set(RHPORT_SPEED OPT_MODE_FULL_SPEED OPT_MODE_HIGH_SPEED)
+endif ()
+if (NOT DEFINED RHPORT_DEVICE_SPEED)
+ list(GET RHPORT_SPEED ${RHPORT_DEVICE} RHPORT_DEVICE_SPEED)
+endif ()
+if (NOT DEFINED RHPORT_HOST_SPEED)
+ list(GET RHPORT_SPEED ${RHPORT_HOST} RHPORT_HOST_SPEED)
+endif ()
+
+cmake_print_variables(RHPORT_DEVICE RHPORT_DEVICE_SPEED RHPORT_HOST RHPORT_HOST_SPEED)
+
#------------------------------------
# BOARD_TARGET
#------------------------------------
@@ -32,10 +54,11 @@ function(add_board_target BOARD_TARGET)
${FSP_RA}/src/bsp/mcu/all/bsp_io.c
${FSP_RA}/src/bsp/mcu/all/bsp_irq.c
${FSP_RA}/src/bsp/mcu/all/bsp_register_protection.c
- ${FSP_RA}/src/bsp/mcu/all/bsp_rom_registers.c
${FSP_RA}/src/bsp/mcu/all/bsp_sbrk.c
${FSP_RA}/src/bsp/mcu/all/bsp_security.c
${FSP_RA}/src/r_ioport/r_ioport.c
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/ra_gen/common_data.c
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/ra_gen/pin_data.c
)
target_compile_options(${BOARD_TARGET} PUBLIC
@@ -44,8 +67,9 @@ function(add_board_target BOARD_TARGET)
target_include_directories(${BOARD_TARGET} PUBLIC
${CMAKE_CURRENT_FUNCTION_LIST_DIR}
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
- ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/fsp_cfg
- ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/fsp_cfg/bsp
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/ra_cfg/fsp_cfg
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/ra_cfg/fsp_cfg/bsp
+ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/ra_gen
${CMSIS_DIR}/CMSIS/Core/Include
${FSP_RA}/inc
${FSP_RA}/inc/api
@@ -54,22 +78,27 @@ function(add_board_target BOARD_TARGET)
${FSP_RA}/src/bsp/mcu/all
${FSP_RA}/src/bsp/mcu/${MCU_VARIANT}
)
+ target_compile_definitions(${BOARD_TARGET} PUBLIC
+ BOARD_TUD_RHPORT=${RHPORT_DEVICE}
+ BOARD_TUD_MAX_SPEED=${RHPORT_DEVICE_SPEED}
+ BOARD_TUH_RHPORT=${RHPORT_HOST}
+ BOARD_TUH_MAX_SPEED=${RHPORT_HOST_SPEED}
+ )
update_board(${BOARD_TARGET})
if (NOT DEFINED LD_FILE_${CMAKE_C_COMPILER_ID})
- set(LD_FILE_GNU ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/linker/gcc/${MCU_VARIANT}.ld)
+ set(LD_FILE_GNU ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/script/fsp.ld)
endif ()
if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
target_link_options(${BOARD_TARGET} PUBLIC
# linker file
"LINKER:--script=${LD_FILE_GNU}"
- -L${CMAKE_CURRENT_FUNCTION_LIST_DIR}/linker/gcc
+ -L${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/script
+ -Wl,--defsym=end=__bss_end__
-nostartfiles
- # nanolib
- --specs=nano.specs
- --specs=nosys.specs
+ --specs=nano.specs --specs=nosys.specs
)
elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
target_link_options(${BOARD_TARGET} PUBLIC
@@ -95,12 +124,18 @@ function(family_configure_example TARGET RTOS)
# BSP
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+ # Explicitly added bsp_rom_registers here, otherwise MCU can be bricked if g_bsp_rom_registers is dropped by linker
+ ${FSP_RA}/src/bsp/mcu/all/bsp_rom_registers.c
)
target_include_directories(${TARGET} PUBLIC
# family, hw, board
${CMAKE_CURRENT_FUNCTION_LIST_DIR}
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
)
+ target_compile_options(${TARGET} PUBLIC
+ -Wno-error=undef
+ -Wno-error=strict-prototypes
+ )
# # RA has custom freertos port
# if (NOT TARGET freertos_kernel_port)
diff --git a/hw/bsp/ra/family.mk b/hw/bsp/ra/family.mk
index 4447e84995..6ac7c262fd 100644
--- a/hw/bsp/ra/family.mk
+++ b/hw/bsp/ra/family.mk
@@ -1,42 +1,67 @@
-DEPS_SUBMODULES += hw/mcu/renesas/fsp lib/CMSIS_5
-
FSP_RA = hw/mcu/renesas/fsp/ra/fsp
include $(TOP)/$(BOARD_PATH)/board.mk
# Don't include options setting in .bin file since it create unnecessary large file due to padding
OBJCOPY_BIN_OPTION = --only-section .text --only-section .data --only-section .rodata --only-section .bss
-# Default to port 0 fullspeed, board with port 1 highspeed should override this in board.mk
-PORT ?= 0
+# ----------------------
+# Port & Speed Selection
+# ----------------------
+RHPORT_SPEED ?= OPT_MODE_FULL_SPEED OPT_MODE_HIGH_SPEED
+RHPORT_DEVICE ?= 0
+RHPORT_HOST ?= 0
+
+# Determine RHPORT_DEVICE_SPEED if not defined
+ifndef RHPORT_DEVICE_SPEED
+ifeq ($(RHPORT_DEVICE), 0)
+ RHPORT_DEVICE_SPEED = $(firstword $(RHPORT_SPEED))
+else
+ RHPORT_DEVICE_SPEED = $(lastword $(RHPORT_SPEED))
+endif
+endif
+# Determine RHPORT_HOST_SPEED if not defined
+ifndef RHPORT_HOST_SPEED
+ifeq ($(RHPORT_HOST), 0)
+ RHPORT_HOST_SPEED = $(firstword $(RHPORT_SPEED))
+else
+ RHPORT_HOST_SPEED = $(lastword $(RHPORT_SPEED))
+endif
+endif
+
+# --------------
+# Compiler Flags
+# --------------
CFLAGS += \
- -flto \
-DCFG_TUSB_MCU=OPT_MCU_RAXXX \
- -DBOARD_TUD_RHPORT=$(PORT) \
+ -DBOARD_TUD_RHPORT=${RHPORT_DEVICE} \
+ -DBOARD_TUD_MAX_SPEED=${RHPORT_DEVICE_SPEED} \
+ -DBOARD_TUH_RHPORT=${RHPORT_HOST} \
+ -DBOARD_TUH_MAX_SPEED=${RHPORT_HOST_SPEED}
+
+CFLAGS_GCC += \
+ -flto \
-Wno-error=undef \
-Wno-error=strict-prototypes \
-Wno-error=cast-align \
-Wno-error=cast-qual \
-Wno-error=unused-but-set-variable \
-Wno-error=unused-variable \
- -nostdlib \
- -nostartfiles \
-ffreestanding
-ifeq ($(PORT), 1)
- CFLAGS += -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED
- $(info "Using PORT 1 HighSpeed")
-else
- CFLAGS += -DBOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED
- $(info "Using PORT 0 FullSpeed")
-endif
-
-LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs
+LDFLAGS_GCC += \
+ -nostartfiles -nostdlib \
+ -specs=nosys.specs -specs=nano.specs
+# -----------------
+# Sources & Include
+# -----------------
SRC_C += \
src/portable/renesas/rusb2/dcd_rusb2.c \
src/portable/renesas/rusb2/hcd_rusb2.c \
src/portable/renesas/rusb2/rusb2_common.c \
+ ${BOARD_PATH}/ra_gen/common_data.c \
+ ${BOARD_PATH}/ra_gen/pin_data.c \
$(FSP_RA)/src/bsp/cmsis/Device/RENESAS/Source/startup.c \
$(FSP_RA)/src/bsp/cmsis/Device/RENESAS/Source/system.c \
$(FSP_RA)/src/bsp/mcu/all/bsp_clocks.c \
@@ -53,10 +78,11 @@ SRC_C += \
$(FSP_RA)/src/r_ioport/r_ioport.c \
INC += \
- $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
$(TOP)/$(BOARD_PATH) \
- $(TOP)/$(BOARD_PATH)/fsp_cfg \
- $(TOP)/$(BOARD_PATH)/fsp_cfg/bsp \
+ $(TOP)/$(BOARD_PATH)/ra_cfg/fsp_cfg \
+ $(TOP)/$(BOARD_PATH)/ra_cfg/fsp_cfg/bsp \
+ $(TOP)/$(BOARD_PATH)/ra_gen \
+ $(TOP)/lib/CMSIS_6/CMSIS/Core/Include \
$(TOP)/$(FSP_RA)/src/bsp/cmsis/Device/RENESAS/Include \
$(TOP)/$(FSP_RA)/inc \
$(TOP)/$(FSP_RA)/inc/api \
@@ -65,10 +91,11 @@ INC += \
$(TOP)/$(FSP_RA)/src/bsp/mcu/$(MCU_VARIANT) \
ifndef LD_FILE
-LD_FILE = $(FAMILY_PATH)/linker/gcc/$(MCU_VARIANT).ld
+LD_FILE = $(BOARD_PATH)/script/fsp.ld
endif
-LDFLAGS += -L$(TOP)/$(FAMILY_PATH)/linker/gcc
+LDFLAGS += -L$(TOP)/$(BOARD_PATH)/script
+LDFLAGS += -Wl,--defsym=end=__bss_end__
# For freeRTOS port source
# hack to use the port provided by renesas
diff --git a/hw/bsp/ra/linker/gcc/ra2a1.ld b/hw/bsp/ra/linker/gcc/ra2a1.ld
deleted file mode 100644
index 218acbb2a9..0000000000
--- a/hw/bsp/ra/linker/gcc/ra2a1.ld
+++ /dev/null
@@ -1,22 +0,0 @@
-RAM_START = 0x20000000;
-RAM_LENGTH = 0x8000;
-FLASH_START = 0x00000000;
-FLASH_LENGTH = 0x40000;
-DATA_FLASH_START = 0x40100000;
-DATA_FLASH_LENGTH = 0x2000;
-OPTION_SETTING_START = 0x00000000;
-OPTION_SETTING_LENGTH = 0x0;
-OPTION_SETTING_S_START = 0x80000000;
-OPTION_SETTING_S_LENGTH = 0x0;
-ID_CODE_START = 0x01010018;
-ID_CODE_LENGTH = 0x20;
-SDRAM_START = 0x80010000;
-SDRAM_LENGTH = 0x0;
-QSPI_FLASH_START = 0x60000000;
-QSPI_FLASH_LENGTH = 0x0;
-OSPI_DEVICE_0_START = 0x80020000;
-OSPI_DEVICE_0_LENGTH = 0x0;
-OSPI_DEVICE_1_START = 0x80030000;
-OSPI_DEVICE_1_LENGTH = 0x0;
-
-INCLUDE fsp.ld
diff --git a/hw/bsp/ra/linker/gcc/ra4m1.ld b/hw/bsp/ra/linker/gcc/ra4m1.ld
deleted file mode 100644
index 218acbb2a9..0000000000
--- a/hw/bsp/ra/linker/gcc/ra4m1.ld
+++ /dev/null
@@ -1,22 +0,0 @@
-RAM_START = 0x20000000;
-RAM_LENGTH = 0x8000;
-FLASH_START = 0x00000000;
-FLASH_LENGTH = 0x40000;
-DATA_FLASH_START = 0x40100000;
-DATA_FLASH_LENGTH = 0x2000;
-OPTION_SETTING_START = 0x00000000;
-OPTION_SETTING_LENGTH = 0x0;
-OPTION_SETTING_S_START = 0x80000000;
-OPTION_SETTING_S_LENGTH = 0x0;
-ID_CODE_START = 0x01010018;
-ID_CODE_LENGTH = 0x20;
-SDRAM_START = 0x80010000;
-SDRAM_LENGTH = 0x0;
-QSPI_FLASH_START = 0x60000000;
-QSPI_FLASH_LENGTH = 0x0;
-OSPI_DEVICE_0_START = 0x80020000;
-OSPI_DEVICE_0_LENGTH = 0x0;
-OSPI_DEVICE_1_START = 0x80030000;
-OSPI_DEVICE_1_LENGTH = 0x0;
-
-INCLUDE fsp.ld
diff --git a/hw/bsp/ra/linker/gcc/ra4m3.ld b/hw/bsp/ra/linker/gcc/ra4m3.ld
deleted file mode 100644
index 7b3a63fbe7..0000000000
--- a/hw/bsp/ra/linker/gcc/ra4m3.ld
+++ /dev/null
@@ -1,22 +0,0 @@
-RAM_START = 0x20000000;
-RAM_LENGTH = 0x20000;
-FLASH_START = 0x00000000;
-FLASH_LENGTH = 0x100000;
-DATA_FLASH_START = 0x08000000;
-DATA_FLASH_LENGTH = 0x2000;
-OPTION_SETTING_START = 0x0100A100;
-OPTION_SETTING_LENGTH = 0x100;
-OPTION_SETTING_S_START = 0x0100A200;
-OPTION_SETTING_S_LENGTH = 0x100;
-ID_CODE_START = 0x00000000;
-ID_CODE_LENGTH = 0x0;
-SDRAM_START = 0x80010000;
-SDRAM_LENGTH = 0x0;
-QSPI_FLASH_START = 0x60000000;
-QSPI_FLASH_LENGTH = 0x4000000;
-OSPI_DEVICE_0_START = 0x80020000;
-OSPI_DEVICE_0_LENGTH = 0x0;
-OSPI_DEVICE_1_START = 0x80030000;
-OSPI_DEVICE_1_LENGTH = 0x0;
-
-INCLUDE fsp.ld
diff --git a/hw/bsp/ra/linker/gcc/ra6m1.ld b/hw/bsp/ra/linker/gcc/ra6m1.ld
deleted file mode 100644
index 91d27f74cc..0000000000
--- a/hw/bsp/ra/linker/gcc/ra6m1.ld
+++ /dev/null
@@ -1,22 +0,0 @@
-RAM_START = 0x1FFE0000;
-RAM_LENGTH = 0x40000;
-FLASH_START = 0x00000000;
-FLASH_LENGTH = 0x80000;
-DATA_FLASH_START = 0x40100000;
-DATA_FLASH_LENGTH = 0x2000;
-OPTION_SETTING_START = 0x00000000;
-OPTION_SETTING_LENGTH = 0x0;
-OPTION_SETTING_S_START = 0x80000000;
-OPTION_SETTING_S_LENGTH = 0x0;
-ID_CODE_START = 0x0100A150;
-ID_CODE_LENGTH = 0x10;
-SDRAM_START = 0x80010000;
-SDRAM_LENGTH = 0x0;
-QSPI_FLASH_START = 0x60000000;
-QSPI_FLASH_LENGTH = 0x4000000;
-OSPI_DEVICE_0_START = 0x80020000;
-OSPI_DEVICE_0_LENGTH = 0x0;
-OSPI_DEVICE_1_START = 0x80030000;
-OSPI_DEVICE_1_LENGTH = 0x0;
-
-INCLUDE fsp.ld
diff --git a/hw/bsp/ra/linker/gcc/ra6m5.ld b/hw/bsp/ra/linker/gcc/ra6m5.ld
deleted file mode 100644
index af747fd9b8..0000000000
--- a/hw/bsp/ra/linker/gcc/ra6m5.ld
+++ /dev/null
@@ -1,22 +0,0 @@
-RAM_START = 0x20000000;
-RAM_LENGTH = 0x80000;
-FLASH_START = 0x00000000;
-FLASH_LENGTH = 0x200000;
-DATA_FLASH_START = 0x08000000;
-DATA_FLASH_LENGTH = 0x2000;
-OPTION_SETTING_START = 0x0100A100;
-OPTION_SETTING_LENGTH = 0x100;
-OPTION_SETTING_S_START = 0x0100A200;
-OPTION_SETTING_S_LENGTH = 0x100;
-ID_CODE_START = 0x00000000;
-ID_CODE_LENGTH = 0x0;
-SDRAM_START = 0x80010000;
-SDRAM_LENGTH = 0x0;
-QSPI_FLASH_START = 0x60000000;
-QSPI_FLASH_LENGTH = 0x4000000;
-OSPI_DEVICE_0_START = 0x68000000;
-OSPI_DEVICE_0_LENGTH = 0x8000000;
-OSPI_DEVICE_1_START = 0x70000000;
-OSPI_DEVICE_1_LENGTH = 0x10000000;
-
-INCLUDE fsp.ld
diff --git a/hw/bsp/ra/vector_data.h b/hw/bsp/ra/vector_data.h
index 2b3b7d8378..a85d064bdd 100644
--- a/hw/bsp/ra/vector_data.h
+++ b/hw/bsp/ra/vector_data.h
@@ -6,6 +6,10 @@
extern "C" {
#endif
+#if defined(BSP_MCU_GROUP_RA6M5) || defined(BSP_MCU_GROUP_RA6M3) || (BSP_CFG_MCU_PART_SERIES == 8)
+#define BOARD_HAS_USB_HIGHSPEED
+#endif
+
/* ISR prototypes */
void usbfs_interrupt_handler(void);
void usbfs_resume_handler(void);
diff --git a/src/device/usbd_control.c b/src/device/usbd_control.c
index d964a75d0d..c9700fd9db 100644
--- a/src/device/usbd_control.c
+++ b/src/device/usbd_control.c
@@ -44,10 +44,6 @@ TU_ATTR_WEAK void dcd_edpt0_status_complete(uint8_t rhport, const tusb_control_r
// MACRO CONSTANT TYPEDEF
//--------------------------------------------------------------------+
-#if CFG_TUSB_DEBUG >= CFG_TUD_LOG_LEVEL
-extern void usbd_driver_print_control_complete_name(usbd_control_xfer_cb_t callback);
-#endif
-
enum {
EDPT_CTRL_OUT = 0x00,
EDPT_CTRL_IN = 0x80
diff --git a/src/device/usbd_pvt.h b/src/device/usbd_pvt.h
index 90f37db3ed..190d6fd7fc 100644
--- a/src/device/usbd_pvt.h
+++ b/src/device/usbd_pvt.h
@@ -127,6 +127,11 @@ void usbd_sof_enable(uint8_t rhport, sof_consumer_t consumer, bool en);
bool usbd_open_edpt_pair(uint8_t rhport, uint8_t const* p_desc, uint8_t ep_count, uint8_t xfer_type, uint8_t* ep_out, uint8_t* ep_in);
void usbd_defer_func(osal_task_func_t func, void *param, bool in_isr);
+
+#if CFG_TUSB_DEBUG >= CFG_TUD_LOG_LEVEL
+void usbd_driver_print_control_complete_name(usbd_control_xfer_cb_t callback);
+#endif
+
#ifdef __cplusplus
}
#endif
diff --git a/src/tusb_option.h b/src/tusb_option.h
index dca1e4109c..8b1a6af012 100644
--- a/src/tusb_option.h
+++ b/src/tusb_option.h
@@ -152,7 +152,7 @@
#define OPT_MCU_RX63X 1400 ///< Renesas RX63N/631
#define OPT_MCU_RX65X 1401 ///< Renesas RX65N/RX651
#define OPT_MCU_RX72N 1402 ///< Renesas RX72N
-#define OPT_MCU_RAXXX 1403 ///< Renesas RAxxx families
+#define OPT_MCU_RAXXX 1420 ///< Renesas RA generic
// Mind Motion
#define OPT_MCU_MM32F327X 1500 ///< Mind Motion MM32F327
diff --git a/tools/get_deps.py b/tools/get_deps.py
index 58709414c7..c8459c1f13 100755
--- a/tools/get_deps.py
+++ b/tools/get_deps.py
@@ -62,7 +62,7 @@
'fe9133fc513b82cc3dc62c67cb51f2339cf29ef7',
'rp2040'],
'hw/mcu/renesas/fsp': ['https://github.com/renesas/fsp.git',
- 'd52e5a6a59b7c638da860c2bb309b6e78e752ff8',
+ 'edcc97d684b6f716728a60d7a6fea049d9870bd6',
'ra'],
'hw/mcu/renesas/rx': ['https://github.com/kkitayam/rx_device.git',
'706b4e0cf485605c32351e2f90f5698267996023',
@@ -194,13 +194,16 @@
'77c4095087e5ed2c548ec9058e655d0b8757663b',
'ch32f20x'],
'lib/CMSIS_5': ['https://github.com/ARM-software/CMSIS_5.git',
- '20285262657d1b482d132d20d755c8c330d55c1f',
- 'imxrt kinetis_k32l2 kinetis_kl lpc51 lpc54 lpc55 mcx mm32 msp432e4 nrf ra saml2x '
+ '2b7495b8535bdcb306dac29b9ded4cfb679d7e5c',
+ 'imxrt kinetis_k32l2 kinetis_kl lpc51 lpc54 lpc55 mcx mm32 msp432e4 nrf saml2x '
'lpc11 lpc13 lpc15 lpc17 lpc18 lpc40 lpc43 '
'stm32c0 stm32f0 stm32f1 stm32f2 stm32f3 stm32f4 stm32f7 stm32g0 stm32g4 stm32h5 '
'stm32h7 stm32l0 stm32l1 stm32l4 stm32l5 stm32u5 stm32wb '
'sam3x samd11 samd21 samd51 samd5x_e5x same5x same7x saml2x samg '
'tm4c '],
+ 'lib/CMSIS_6': ['https://github.com/ARM-software/CMSIS_6.git',
+ 'b0bbb0423b278ca632cfe1474eb227961d835fd2',
+ 'ra'],
'lib/sct_neopixel': ['https://github.com/gsteiert/sct_neopixel.git',
'e73e04ca63495672d955f9268e003cffe168fcd8',
'lpc55'],