README.md

Sample testbench for a Tiny Tapeout project

This is a sample testbench for a Tiny Tapeout project. It uses cocotb to drive the DUT and check the outputs.

Setting up

1. Edit Makefile and modify PROJECT_SOURCES to point to your Verilog files.
2. Edit tb.v and replace tt_um_example with your module name.

How to run

To run the RTL simulation:

make

To run gatelevel simulation, first harden your project and copy ../runs/wokwi/results/final/verilog/gl/{your_module_name}.v to gate_level_netlist.v.

Then run:

make GATES=yes

How to view the VCD file

gtkwave tb.vcd tb.gtkw