diff --git a/gateware/car.py b/gateware/car.py
index ab88e17..b44e43c 100644
--- a/gateware/car.py
+++ b/gateware/car.py
@@ -13,7 +13,7 @@ def wire_up_reset(self, m, reset):
         m.submodules.reset_sync_dac  = ResetSynchronizer(reset, domain="dac")
         m.submodules.reset_sync_adat = ResetSynchronizer(reset, domain="adat")
 
-class IntelFPGAClockDomainGenerator(Elaboratable, ClockDomainGeneratorBase):
+class IntelCycloneIVClockDomainGenerator(Elaboratable, ClockDomainGeneratorBase):
     ADAT_DIV_48k    = 83
     ADAT_MULT_48k   = 17
 
@@ -157,7 +157,7 @@ def elaborate(self, platform):
         return m
 
 
-class IntelCycloneVFPGAClockDomainGenerator(Elaboratable, ClockDomainGeneratorBase):
+class IntelCycloneVClockDomainGenerator(Elaboratable, ClockDomainGeneratorBase):
 
     def __init__(self, *, clock_frequencies=None, clock_signal_name=None):
         pass
diff --git a/gateware/platforms.py b/gateware/platforms.py
index 71d3df2..fe443bd 100644
--- a/gateware/platforms.py
+++ b/gateware/platforms.py
@@ -9,7 +9,7 @@
 
 from luna.gateware.platform.core import LUNAPlatform
 
-from car                     import IntelFPGAClockDomainGenerator, IntelCycloneVFPGAClockDomainGenerator, Xilinx7SeriesClockDomainGenerator
+from car                     import IntelCycloneIVClockDomainGenerator, IntelCycloneVClockDomainGenerator, Xilinx7SeriesClockDomainGenerator
 from adatface_rev0_baseboard import ADATFaceRev0Baseboard
 
 class IntelFPGAParameters:
@@ -34,7 +34,7 @@ class IntelFPGAParameters:
 
 class ADATFaceCycloneV(QMTech5CEFA2Platform, LUNAPlatform):
     fast_multiplier        = 9
-    clock_domain_generator = IntelCycloneVFPGAClockDomainGenerator
+    clock_domain_generator = IntelCycloneVClockDomainGenerator
     fast_domain_clock_freq = int(48e3 * 256 * fast_multiplier)
 
     @property
@@ -54,7 +54,7 @@ def __init__(self):
 
 class ADATFaceCycloneIV(QMTechEP4CEPlatform, LUNAPlatform):
     fast_multiplier        = 9
-    clock_domain_generator = IntelFPGAClockDomainGenerator
+    clock_domain_generator = IntelCycloneIVClockDomainGenerator
     fast_domain_clock_freq = int(48e3 * 256 * fast_multiplier)
 
     @property
@@ -75,7 +75,7 @@ def __init__(self):
 # This is here just for experimental reasons.
 # right now the design probably would not fit into this device anymore
 class ADATFaceCyclone10(QMTech10CL006Platform, LUNAPlatform):
-    clock_domain_generator = IntelFPGAClockDomainGenerator
+    clock_domain_generator = IntelCycloneIVClockDomainGenerator
     fast_multiplier        = 9
     fast_domain_clock_freq = int(48e3 * 256 * fast_multiplier)