forked from psakhis/Groovy_MiSTer
-
Notifications
You must be signed in to change notification settings - Fork 0
/
Groovy.sv
1823 lines (1630 loc) · 82.9 KB
/
Groovy.sv
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
//============================================================================
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
//
//============================================================================
module emu
(
//Master input clock
input CLK_50M,
//Async reset from top-level module.
//Can be used as initial reset.
input RESET,
//Must be passed to hps_io module
inout [48:0] HPS_BUS,
//Base video clock. Usually equals to CLK_SYS.
output CLK_VIDEO,
//Multiple resolutions are supported using different CE_PIXEL rates.
//Must be based on CLK_VIDEO
output CE_PIXEL,
//Video aspect ratio for HDMI. Most retro systems have ratio 4:3.
//if VIDEO_ARX[12] or VIDEO_ARY[12] is set then [11:0] contains scaled size instead of aspect ratio.
output [12:0] VIDEO_ARX,
output [12:0] VIDEO_ARY,
output [7:0] VGA_R,
output [7:0] VGA_G,
output [7:0] VGA_B,
output VGA_HS,
output VGA_VS,
output VGA_DE, // = ~(VBlank | HBlank)
output VGA_F1,
output [1:0] VGA_SL,
output VGA_SCALER, // Force VGA scaler
output VGA_DISABLE, // analog out is off
input [11:0] HDMI_WIDTH,
input [11:0] HDMI_HEIGHT,
output HDMI_FREEZE,
output HDMI_BLACKOUT,
`ifdef MISTER_FB
// Use framebuffer in DDRAM
// FB_FORMAT:
// [2:0] : 011=8bpp(palette) 100=16bpp 101=24bpp 110=32bpp
// [3] : 0=16bits 565 1=16bits 1555
// [4] : 0=RGB 1=BGR (for 16/24/32 modes)
//
// FB_STRIDE either 0 (rounded to 256 bytes) or multiple of pixel size (in bytes)
output FB_EN,
output [4:0] FB_FORMAT,
output [11:0] FB_WIDTH,
output [11:0] FB_HEIGHT,
output [31:0] FB_BASE,
output [13:0] FB_STRIDE,
input FB_VBL,
input FB_LL,
output FB_FORCE_BLANK,
`ifdef MISTER_FB_PALETTE
// Palette control for 8bit modes.
// Ignored for other video modes.
output FB_PAL_CLK,
output [7:0] FB_PAL_ADDR,
output [23:0] FB_PAL_DOUT,
input [23:0] FB_PAL_DIN,
output FB_PAL_WR,
`endif
`endif
output LED_USER, // 1 - ON, 0 - OFF.
// b[1]: 0 - LED status is system status OR'd with b[0]
// 1 - LED status is controled solely by b[0]
// hint: supply 2'b00 to let the system control the LED.
output [1:0] LED_POWER,
output [1:0] LED_DISK,
// I/O board button press simulation (active high)
// b[1]: user button
// b[0]: osd button
output [1:0] BUTTONS,
input CLK_AUDIO, // 24.576 MHz
output [15:0] AUDIO_L,
output [15:0] AUDIO_R,
output AUDIO_S, // 1 - signed audio samples, 0 - unsigned
output [1:0] AUDIO_MIX, // 0 - no mix, 1 - 25%, 2 - 50%, 3 - 100% (mono)
//ADC
inout [3:0] ADC_BUS,
//SD-SPI
output SD_SCK,
output SD_MOSI,
input SD_MISO,
output SD_CS,
input SD_CD,
//High latency DDR3 RAM interface
//Use for non-critical time purposes
output DDRAM_CLK,
input DDRAM_BUSY,
output [7:0] DDRAM_BURSTCNT,
output [28:0] DDRAM_ADDR,
input [63:0] DDRAM_DOUT,
input DDRAM_DOUT_READY,
output DDRAM_RD,
output [63:0] DDRAM_DIN,
output [7:0] DDRAM_BE,
output DDRAM_WE,
//SDRAM interface with lower latency
output SDRAM_CLK,
output SDRAM_CKE,
output [12:0] SDRAM_A,
output [1:0] SDRAM_BA,
inout [15:0] SDRAM_DQ,
output SDRAM_DQML,
output SDRAM_DQMH,
output SDRAM_nCS,
output SDRAM_nCAS,
output SDRAM_nRAS,
output SDRAM_nWE,
`ifdef MISTER_DUAL_SDRAM
//Secondary SDRAM
//Set all output SDRAM_* signals to Z ASAP if SDRAM2_EN is 0
input SDRAM2_EN,
output SDRAM2_CLK,
output [12:0] SDRAM2_A,
output [1:0] SDRAM2_BA,
inout [15:0] SDRAM2_DQ,
output SDRAM2_nCS,
output SDRAM2_nCAS,
output SDRAM2_nRAS,
output SDRAM2_nWE,
`endif
input UART_CTS,
output UART_RTS,
input UART_RXD,
output UART_TXD,
output UART_DTR,
input UART_DSR,
// Open-drain User port.
// 0 - D+/RX
// 1 - D-/TX
// 2..6 - USR2..USR6
// Set USER_OUT to 1 to read from USER_IN.
input [6:0] USER_IN,
output [6:0] USER_OUT,
input OSD_STATUS,
output PWM_EN //wait to see on framework someday
);
///////// Default values for ports not used in this core /////////
assign ADC_BUS = 'Z;
assign USER_OUT = '1;
assign {UART_RTS, UART_TXD, UART_DTR} = 0;
assign {SD_SCK, SD_MOSI, SD_CS} = 'Z;
assign {SDRAM_DQ, SDRAM_A, SDRAM_BA, SDRAM_CLK, SDRAM_CKE, SDRAM_DQML, SDRAM_DQMH, SDRAM_nWE, SDRAM_nCAS, SDRAM_nRAS, SDRAM_nCS} = 'Z;
//assign {DDRAM_CLK, DDRAM_BURSTCNT, DDRAM_ADDR, DDRAM_DIN, DDRAM_BE, DDRAM_RD, DDRAM_WE} = '0;
assign VGA_SL = PoC_interlaced && !PoC_FB_interlaced ? 1'b0 : scandoubler_fx;
//assign VGA_F1 = 0;
assign VGA_SCALER = 0;
assign VGA_DISABLE = 0;
assign HDMI_FREEZE = 0;
assign HDMI_BLACKOUT = 0;
assign AUDIO_S = hps_audio ? 1'b1 : 1'b0;
assign AUDIO_L = hps_audio ? sound_l_out : 1'b0;
assign AUDIO_R = hps_audio ? sound_r_out : 1'b0;
assign AUDIO_MIX = 0;
assign LED_DISK = 0;
assign LED_POWER = 0;
assign LED_USER = 0;
assign BUTTONS = 0;
assign PWM_EN = hps_pwm;
//////////////////////////////////////////////////////////////////
wire [1:0] ar = status[2:1];
wire [1:0] scandoubler_fx = status[4:3];
wire [1:0] scale = status[6:5];
`include "build_id.v"
localparam CONF_STR = {
"Groovy;;",
"-;",
"FC1,GMC,Load Gmc;",
"-;",
"P1,Video;",
"P1O[4:3],Scandoubler Fx,None,CRT 25%,CRT 50%,CRT 75%;",
"H0P1O[2:1],Aspect ratio,Original,Full Screen,[ARC1],[ARC2];",
"H0P1O[6:5],Scale,Normal,V-Integer,Narrower HV-Integer,Wider HV-Integer;",
"H0P1O[10],Orientation,Horz,Vert;",
"H0P1-;",
"H1P1O[11],240p Crop,Off,On;",
"H2P1O[16:12],Crop Offset,0,+1,+2,+3,+4,+5,+6,+7,+8,-8,-7,-6,-5,-4,-3,-2,-1;",
"P1-;",
"P1O[21:17],CRT H offset,0,-1,-2,-3,-4,-5,-6,-7,-8,-9,-10,-11,-12,-13,-14,-15,+16,+15,+14,+13,+12,+11,+10,+9,+8,+7,+6,+5,+4,+3,+2,+1;",
"P1O[26:22],CRT V offset,0,-1,-2,-3,-4,-5,-6,-7,-8,-9,-10,-11,-12,-13,-14,-15,+16,+15,+14,+13,+12,+11,+10,+9,+8,+7,+6,+5,+4,+3,+2,+1;",
"H8P1O[47],CRT scale enable, Off,On;",
"H3P1O[51:48],CRT scale factor,0,+1,+2,+3,+4,+5,+6,+7,-8,-7,-6,-5,-4,-3,-2,-1;",
"P1-;",
"P1O[37],PWM,Off,On;",
"P1-;",
"D4P1-,Debug options;",
"P1O[32],Volatile framebuffer,Off,On;",
"P1O[46],Vsync overlay,Off,On;",
"P1-;",
"DBP1O[57:56],RGB mode,888,A888,565;",
"DCP1O[58],LZ4 frames,Off,On;",
"-;",
"P2,Audio;",
"P2O[34],Audio,Off,On;",
"P2O[36:35],Desired buffer (ms),0,16,32,64;",
"P2-;",
"D9P2O[53:52],Rate,-,22050,44100,48000;",
"DAP2O[55:54],Channels,-,1,2;",
"-;",
"P3,Server;",
"P3O[33],Screensaver,On,Off;",
"P3O[45:44],ARM clock,Stock,+200Mhz,+400Mhz;",
"P3O[42],Jumbo frames (Max MTU),Off,On;",
"P3-;",
"D5P3-,Send inputs;",
"P3O[39:38],PS2,Off,Keyboard,Keyboard & Mouse;",
"P3O[41:40],Joysticks,Off,Digital,Analog;",
"P3-;",
"D6P3-,Debug options;",
"P3O[28:27],Verbose,Off,1,2,3;",
"P3O[29],Blit at,ASAP,End Line;",
"DDP3O[59],Server type,UDP,XDP;",
"P3-;",
"D7P3-,Save and reload to apply!;",
"-;",
"J1,Button 1,Button 2,Button 3,Button 4,Button 5,Button 6,Button 7,Button 8, Button 9, Button 10;",
"J2,Button 1,Button 2,Button 3,Button 4,Button 5,Button 6,Button 7,Button 8, Button 9, Button 10;",
"V,v",`BUILD_DATE
};
//
// HPS is the module that communicates between the linux and fpga
//
wire [1:0] buttons;
wire forced_scandoubler;
wire [21:0] gamma_bus;
wire direct_video;
wire video_rotated = 0;
wire no_rotate = ~status[10];
wire allow_crop_240p = ~forced_scandoubler && scale == 0 && !direct_video;
wire crop_240p = allow_crop_240p & status[11];
wire [4:0] crop_offset = status[16:12] < 9 ? {status[16:12]} : ( status[16:12] + 5'd15 );
wire hps_frameskip = !status[32];
wire hps_audio = status[34];
wire [1:0] hps_audio_buffer = status[36:35];
wire hps_pwm = status[37];
wire hps_vsync_overlay = status[46];
wire [60:0] status;
wire [31:0] joy0;
wire [31:0] joy1;
hps_io #(.CONF_STR(CONF_STR)) hps_io
(
.clk_sys(clk_sys),
.HPS_BUS(HPS_BUS),
.EXT_BUS(EXT_BUS),
.gamma_bus(gamma_bus),
.direct_video(direct_video),
.forced_scandoubler(forced_scandoubler),
.new_vmode(new_vmode),
.video_rotated(video_rotated),
.buttons(buttons),
.status(status),
.status_menumask(status_menumask),
.joystick_0(joy0),
.joystick_1(joy1)
);
// OSD option visibility
wire [15:0] status_menumask; // a high value hides the menu item
assign status_menumask[15] = 0,
status_menumask[14] = 0,
status_menumask[13] = 1,
status_menumask[12] = 1,
status_menumask[11] = 1,
status_menumask[10] = 1,
status_menumask[9] = 1,
status_menumask[8] = 0, //atm, CRT scale don't support interlaced
status_menumask[7] = 1,
status_menumask[6] = 1,
status_menumask[5] = 1,
status_menumask[4] = 1,
status_menumask[3] = ~hsize_enable,
status_menumask[2] = ~crop_240p,
status_menumask[1] = ~allow_crop_240p,
status_menumask[0] = direct_video;
//////////////////////////// HPS I/O EXT ///////////////////////////////////
wire [35:0] EXT_BUS;
reg reset_switchres = 0, vga_frameskip = 0, vga_frameskip_prev = 0, reset_blit = 0, auto_blit = 0, reset_audio = 0, cmd_fskip = 0, reset_blit_lz4 = 0, auto_blit_lz4 = 0;
wire cmd_init, cmd_switchres, cmd_blit, cmd_logo, cmd_audio, cmd_blit_lz4, cmd_blit_vsync;
wire [15:0] audio_samples;
wire [1:0] sound_rate, sound_chan, rgb_mode, lz4_field, lz4_ABCD;
wire lz4_delta;
wire [31:0] lz4_size, switchres_frame;
hps_ext hps_ext
(
.clk_sys(clk_sys),
.EXT_BUS(EXT_BUS),
.state(state),
.hps_rise(1'b1),
.hps_audio(hps_audio),
.sound_rate(sound_rate),
.sound_chan(sound_chan),
.rgb_mode(rgb_mode),
.vga_frameskip(vga_frameskip | (vga_frameskip_prev & vblank_core)),
.vga_vcount(vga_vcount),
.vga_frame(vga_frame),
.vga_vblank(vblank_core),
.vga_f1(VGA_F1),
.vram_pixels(vram_pixels),
.vram_queue(vram_queue),
.vram_synced(vram_synced),
.vram_end_frame(vram_end_frame),
.vram_ready(vram_req_ready),
.cmd_init(cmd_init),
.reset_switchres(reset_switchres),
.cmd_switchres(cmd_switchres),
.switchres_frame(switchres_frame),
.reset_blit(reset_blit),
.cmd_blit(cmd_blit),
.cmd_logo(cmd_logo),
.cmd_audio(cmd_audio),
.reset_audio(reset_audio),
.audio_samples(audio_samples),
.reset_blit_lz4(reset_blit_lz4),
.cmd_blit_lz4(cmd_blit_lz4),
.lz4_size(lz4_size),
.lz4_ABCD(lz4_ABCD),
.lz4_field(lz4_field),
.lz4_delta(lz4_delta),
.lz4_uncompressed_bytes(lz4_uncompressed_bytes),
.cmd_blit_vsync (cmd_blit_vsync)
/* debug
.PoC_subframe_wr_bytes(PoC_subframe_wr_bytes),
.lz4_run(lz4_run),
.PoC_lz4_resume(PoC_lz4_resume_blit),
.PoC_test1(PoC_test1),
.PoC_test2(PoC_test2),
.cmd_fskip(cmd_fskip),
.lz4_stop(lz4_stop),
.PoC_lz4_ABCD(PoC_lz4_ABCD),
.lz4_compressed_bytes(lz4_compressed_bytes),
.lz4_gravats(lz4_writed_bytes),
.lz4_llegits(lz4_readed_bytes),
.PoC_subframe_lz4_bytes(PoC_subframe_lz4_ddr_bytes),
.PoC_subframe_blit_lz4(PoC_subframe_blit_lz4)
*/
);
/////////////////////// CLOCKS ///////////////////////////////
wire clk_sys, pll_locked;
pll pll
(
.refclk(CLK_50M),
.rst(0),
.outclk_0(clk_sys),
.locked(pll_locked),
.reconfig_to_pll(reconfig_to_pll),
.reconfig_from_pll(reconfig_from_pll)
);
wire [63:0] reconfig_to_pll;
wire [63:0] reconfig_from_pll;
wire cfg_waitrequest;
reg cfg_write;
reg [5:0] cfg_address;
reg [31:0] cfg_data;
pll_cfg pll_cfg
(
.mgmt_clk(CLK_50M),
.mgmt_reset(0),
.mgmt_waitrequest(cfg_waitrequest),
.mgmt_read(0),
.mgmt_readdata(),
.mgmt_write(cfg_write),
.mgmt_address(cfg_address),
.mgmt_writedata(cfg_data),
.reconfig_to_pll(reconfig_to_pll),
.reconfig_from_pll(reconfig_from_pll)
);
localparam PLL_PARAM_F_COUNT = 7;
wire [31:0] PLL_ARM_F[PLL_PARAM_F_COUNT * 2] = '{
'h0, 'h0, // set waitrequest mode
'h4, {16'b00, PoC_pll_F_M0, PoC_pll_F_M1}, // M COUNTER 2'b10 + 8bit (High) + 8bit (Low)
'h3, {16'b01, 16'b00}, // N COUNTER 8bit (High) + 8bit (Low) (always 256/256)
'h5, {16'b00, PoC_pll_F_C0, PoC_pll_F_C1}, // C COUNTER 8bit (High) + 8bit (Low)
'h7, PoC_pll_F_K, // K FRACTIONAL
'h8, 'h6, // BANDWIDTH SETTING (auto)
'h2, 'h0 // start reconfigure
};
//reg reconfig_pause = 0;
reg req_modeline = 0;
reg new_modeline = 0;
reg new_vmode = 0; // notify to OSD
always @(posedge CLK_50M) begin
reg [3:0] param_idx = 0;
reg [7:0] reconfig = 0;
cfg_write <= 0;
if (pll_locked & ~cfg_waitrequest) begin
//pll_init_locked <= 1;
if (&reconfig) begin // do reconfig
cfg_address <= PLL_ARM_F[param_idx * 2 + 0][5:0];
cfg_data <= PLL_ARM_F[param_idx * 2 + 1];
cfg_write <= 1;
param_idx <= param_idx + 4'd1;
if (param_idx == PLL_PARAM_F_COUNT - 1) reconfig <= 8'd0;
end else if (req_modeline != new_modeline) begin // new timing requested
new_modeline <= req_modeline;
reconfig <= 8'd1;
//reconfig_pause <= 1;
param_idx <= 0;
end else if (|reconfig) begin // pausing before reconfigure
reconfig <= reconfig + 8'd1;
end// else begin
// reconfig_pause <= 0; // unpause once pll is locked again
// end
end
end
//reg pll_init_locked = 0;
//wire reset = RESET | buttons[1] | ~pll_init_locked;
//wire reset = RESET | status[0] | buttons[1];
/////////////////////// PIXEL CLOCK/////////////////////////////////////
wire ce_pix, ce_pix2;
reg [7:0] ce_pix_arm;
assign ce_pix_arm = cmd_scandoubler && PoC_pll_S ? (PoC_ce_pix >> 1) - 1'd1 : PoC_ce_pix - 1'd1;
reg [3:0] cencnt = 4'd0;
always @(posedge clk_sys) begin
cencnt <= cencnt==ce_pix_arm ? 4'd0 : (cencnt+4'd1);
end
always @(posedge clk_sys) begin
ce_pix <= cencnt == 4'd0;
ce_pix2 <= cencnt == (ce_pix_arm >> 1) - 1'b1;
end
reg cmd_scandoubler = 1'b0;
always @(posedge clk_sys) begin
cmd_scandoubler <= (forced_scandoubler || scandoubler_fx != 2'b00) && PoC_interlaced && !PoC_FB_interlaced ? 1'b1 : 1'b0;
end
//////////////////////////// MEMORY ///////////////////////////////////
//
//
//////////////////////////// DDRAM ///////////////////////////////////
parameter DDR_SW_HEADER = 28'd8;
parameter DDR_LZ_HEADER = 28'd32;
parameter DDR_FB_OFFSET = 28'hff;
parameter DDR_AB_OFFSET = 28'h32a0ff;
parameter DDR_FD_OFFSET = 28'h1950ff;
parameter DDR_LZ_OFFSET_A = 28'h3320ff;
parameter DDR_LZ_OFFSET_B = 28'h4c70ff;
parameter DDR_LZ_OFFSET_C = 28'h65c0ff;
parameter DDR_LZ_OFFSET_D = 28'h7f10ff;
assign DDRAM_CLK = clk_sys;
wire [63:0] ddr_data;
reg ddr_data_req=1'b0;
reg [27:0] ddr_addr={18'b0,10'b0111111000}; //0x6000000 for read 0x30000000 (chunk 8 bytes, last 3 bits)
wire ddr_data_ready;
wire ddr_busy;
reg ddr_data_write=1'b0;
reg[7:0] ddr_burst = 8'd1;
reg[255:0] ddr_data_tmp = 256'd0;
reg[1:0] ddr_data_idx = 2'd0;
reg [63:0] ddr_data_to_write={8'h00,8'h00,8'h00,8'h00,8'h00,8'h73,8'h65,8'h72};
ddram ddram
(
.*,
.mem_addr(ddr_addr[27:1]),
.mem_dout(ddr_data),
.mem_din(ddr_data_to_write),
.mem_rd(ddr_data_req),
.mem_burst(ddr_burst),
.mem_wr(ddr_data_write),
.mem_busy(ddr_busy),
.mem_dready(ddr_data_ready)
);
///////////////////////////////////////////////////////////////////////////
//
// TASKS
//
///////////////////////////////////////////////////////////////////////////
task decode_pixel;
input drive_lz4;
input[63:0] word64;
input[23:0] total_pixels;
begin
case (rgb_mode)
2'd2: // RGB565
begin
if (total_pixels - PoC_subframe_px_vram > 3) begin
vram_wren1 <= 1'b1;
vram_wren2 <= 1'b1;
vram_wren3 <= 1'b1;
vram_wren4 <= 1'b1;
if (drive_lz4) PoC_subframe_px_lz4 <= PoC_subframe_px_lz4 + 24'd4;
PoC_subframe_px_vram <= PoC_subframe_px_vram + 24'd4;
end else
if (total_pixels - PoC_subframe_px_vram > 2) begin
vram_wren1 <= 1'b1;
vram_wren2 <= 1'b1;
vram_wren3 <= 1'b1;
if (drive_lz4) PoC_subframe_px_lz4 <= PoC_subframe_px_lz4 + 24'd3;
PoC_subframe_px_vram <= PoC_subframe_px_vram + 24'd3;
end else
if (total_pixels - PoC_subframe_px_vram > 1) begin
vram_wren1 <= 1'b1;
vram_wren2 <= 1'b1;
if (drive_lz4) PoC_subframe_px_lz4 <= PoC_subframe_px_lz4 + 24'd2;
PoC_subframe_px_vram <= PoC_subframe_px_vram + 24'd2;
end else
if (total_pixels - PoC_subframe_px_vram > 0) begin
vram_wren1 <= 1'b1;
if (drive_lz4) PoC_subframe_px_lz4 <= PoC_subframe_px_lz4 + 24'd1;
PoC_subframe_px_vram <= PoC_subframe_px_vram + 24'd1;
end
b_vram_in1 <= {word64[00 +: 05], word64[00 +: 03]};
b_vram_in2 <= {word64[16 +: 05], word64[16 +: 03]};
b_vram_in3 <= {word64[32 +: 05], word64[32 +: 03]};
b_vram_in4 <= {word64[48 +: 05], word64[48 +: 03]};
g_vram_in1 <= {word64[05 +: 06], word64[05 +: 02]};
g_vram_in2 <= {word64[21 +: 06], word64[21 +: 02]};
g_vram_in3 <= {word64[37 +: 06], word64[37 +: 02]};
g_vram_in4 <= {word64[53 +: 06], word64[53 +: 02]};
r_vram_in1 <= {word64[11 +: 05], word64[11 +: 03]};
r_vram_in2 <= {word64[27 +: 05], word64[27 +: 03]};
r_vram_in3 <= {word64[43 +: 05], word64[43 +: 03]};
r_vram_in4 <= {word64[59 +: 05], word64[59 +: 03]};
end
2'd1: // RGBA888
begin
if (total_pixels - PoC_subframe_px_vram > 1) begin
vram_wren1 <= 1'b1;
vram_wren2 <= 1'b1;
if (drive_lz4) PoC_subframe_px_lz4 <= PoC_subframe_px_lz4 + 24'd2;
PoC_subframe_px_vram <= PoC_subframe_px_vram + 24'd2;
end else
if (total_pixels - PoC_subframe_px_vram > 0) begin
vram_wren1 <= 1'b1;
if (drive_lz4) PoC_subframe_px_lz4 <= PoC_subframe_px_lz4 + 24'd1;
PoC_subframe_px_vram <= PoC_subframe_px_vram + 24'd1;
end
{r_vram_in1, g_vram_in1, b_vram_in1} <= word64[00 +:24];
{r_vram_in2, g_vram_in2, b_vram_in2} <= word64[32 +:24];
end
default: //RGB888
begin
PoC_frame_rgb_offset <= PoC_frame_rgb_offset == 2 ? 2'd0 : PoC_frame_rgb_offset + 1'b1;
// how many pixels to save
if (total_pixels - PoC_subframe_px_vram > 2 && PoC_frame_rgb_offset != 0) begin
vram_wren1 <= 1'b1;
vram_wren2 <= 1'b1;
vram_wren3 <= 1'b1;
if (drive_lz4) PoC_subframe_px_lz4 <= PoC_subframe_px_lz4 + 24'd3;
PoC_subframe_px_vram <= PoC_subframe_px_vram + 24'd3;
end else
if (total_pixels - PoC_subframe_px_vram > 1) begin
vram_wren1 <= 1'b1;
vram_wren2 <= 1'b1;
if (drive_lz4) PoC_subframe_px_lz4 <= PoC_subframe_px_lz4 + 24'd2;
PoC_subframe_px_vram <= PoC_subframe_px_vram + 24'd2;
end else
if (total_pixels - PoC_subframe_px_vram > 0) begin
vram_wren1 <= 1'b1;
if (drive_lz4) PoC_subframe_px_lz4 <= PoC_subframe_px_lz4 + 24'd1;
PoC_subframe_px_vram <= PoC_subframe_px_vram + 24'd1;
end
// calculate ddr pixels : offsets 64 + 64 + 64 = 48 + 72 + 64
case (PoC_frame_rgb_offset)
2'd0:
begin
{r_vram_in1, g_vram_in1, b_vram_in1} <= word64[00 +:24];
{r_vram_in2, g_vram_in2, b_vram_in2} <= word64[24 +:24];
ddr_data_tmp[00 +: 16] <= word64[48 +:16];
end
2'd1:
begin
{r_vram_in1, g_vram_in1, b_vram_in1} <= {word64[00 +:08], ddr_data_tmp[00 +: 16]};
{r_vram_in2, g_vram_in2, b_vram_in2} <= word64[08 +:24];
{r_vram_in3, g_vram_in3, b_vram_in3} <= word64[32 +:24];
ddr_data_tmp[00 +: 08] <= word64[56 +:08];
end
2'd2:
begin
{r_vram_in1, g_vram_in1, b_vram_in1} <= {word64[00 +:16], ddr_data_tmp[00 +: 08]};
{r_vram_in2, g_vram_in2, b_vram_in2} <= word64[16 +:24];
{r_vram_in3, g_vram_in3, b_vram_in3} <= word64[40 +:24];
end
endcase
end
endcase
end
endtask
///////////////////////////////////////////////////////////////////////////
//
// MAIN FLOW
//
///////////////////////////////////////////////////////////////////////////
// States
parameter S_Idle = 8'd00;
parameter S_Dispatcher = 8'd01;
parameter S_Defaults = 8'd90;
parameter S_Reset = 8'd91;
// Raw Blit
parameter S_Blit_Header_Raw = 8'd20;
parameter S_Blit_Raw = 8'd21;
parameter S_Blit_Prepare_Raw = 8'd22;
parameter S_Blit_Copy_Raw = 8'd23;
parameter S_Blit_End_Raw = 8'd24;
// FrameSkip (non Volatile)
parameter S_Blit_Auto_Skip = 8'd26;
parameter S_Blit_Auto_First = 8'd27;
parameter S_Blit_Auto_Line = 8'd28;
parameter S_Blit_Auto_End = 8'd29;
// Switchres
parameter S_Switchres_Header = 8'd30;
parameter S_Switchres_PLL = 8'd31;
parameter S_Switchres_Mode = 8'd32;
parameter S_Switchres_Scandoubler = 8'd33;
// LZ4 Blit
parameter S_Blit_Header_Lz4 = 8'd50;
parameter S_Blit_Lz4 = 8'd51;
parameter S_Blit_Prepare_Lz4 = 8'd52;
parameter S_Blit_Copy_Lz4 = 8'd53;
parameter S_Blit_Copy_End_Lz4 = 8'd54;
parameter S_Blit_Inflate_Lz4 = 8'd55;
parameter S_Blit_End_Lz4 = 8'd56;
// LZ4 Blit_Delta
parameter S_Delta_Prepare = 8'd60;
parameter S_Delta_Copy = 8'd61;
// Audio
parameter S_Audio_Prepare = 8'd70;
parameter S_Audio_Copy = 8'd71;
parameter S_Audio_End = 8'd72;
/////////////////////////// REGS ////////////////////////////////////////////
reg [7:0] state = S_Idle;
// Header from arm
reg [23:0] PoC_frame_ddr = 24'd0;
reg [15:0] PoC_subframe_bl_ddr = 16'd0;
reg [23:0] PoC_subframe_px_ddr = 24'd0;
// Modeline from arm (default 256x240 sms)
reg [15:0] PoC_H = 16'd256;
reg [7:0] PoC_HFP = 8'd10;
reg [7:0] PoC_HS = 8'd24;
reg [7:0] PoC_HBP = 8'd41;
reg [15:0] PoC_V = 16'd240;
reg [7:0] PoC_VFP = 8'd2;
reg [7:0] PoC_VS = 8'd3;
reg [7:0] PoC_VBP = 8'd16;
// PLL (default 60hz for sms)
reg [7:0] PoC_pll_F_M0 = 8'd4;
reg [7:0] PoC_pll_F_M1 = 8'd4;
reg [7:0] PoC_pll_F_C0 = 8'd3;
reg [7:0] PoC_pll_F_C1 = 8'd2;
reg [31:0] PoC_pll_F_K = 32'd1182682725;
reg [7:0] PoC_ce_pix = 8'd16;
reg PoC_pll_S = 1'b0; //scandoubler 480i
// Interlaced
reg PoC_interlaced = 1'b0;
reg PoC_FB_interlaced = 1'b0;
// Current frame on vram
reg [23:0] PoC_frame_vram = 24'd0;
// Pixels writed on current frame for subframe updates
reg [23:0] PoC_subframe_px_vram = 24'd0;
reg [15:0] PoC_subframe_bl_vram = 16'd0;
reg [23:0] PoC_px_frameskip = 24'd0;
reg [7:0] PoC_state_frameskip = 8'd0;
reg [23:0] PoC_frame_switchres = 24'd0;
reg [1:0] PoC_frame_rgb_offset = 2'd0;
reg [27:0] PoC_subframe_ddr_bytes = 28'd0;
reg [27:0] PoC_subframe_vram_bytes = 28'd0;
// Audio stuff
reg [15:0] PoC_audio_samples = 16'd0;
reg [15:0] PoC_audio_count = 16'd0;
reg [23:0] PoC_audio_ddr_bytes = 24'd0;
reg [23:0] PoC_audio_count_bytes = 24'd0;
// LZ4 stuff
reg [1:0] PoC_lz4_ABCD = 2'd0;
reg [1:0] PoC_lz4_field = 2'd0;
reg [23:0] PoC_frame_lz4 = 24'd0;
reg [15:0] PoC_subframe_blit_lz4 = 16'd0;
reg [23:0] PoC_frame_lz4_ddr = 24'd0;
reg [31:0] PoC_subframe_lz4_ddr_bytes = 32'd0;
reg [15:0] PoC_subframe_blit_lz4_ddr = 16'd0;
reg [27:0] PoC_subframe_wr_bytes = 28'd0;
reg PoC_frame_lz4_FB = 1'b0;
reg PoC_lz4_resume_blit = 1'b0;
reg PoC_lz4_resume_audio = 1'b0;
reg [23:0] PoC_subframe_px_lz4 = 24'd0;
reg PoC_lz4_delta = 1'b0;
reg [6:0] PoC_lz4_delta_index = 7'd0;
reg [63:0] PoC_lz4_delta_FB[128];
reg PoC_lz4_delta_req;
reg [27:0] PoC_lz4_delta_bytes = 28'd0;
// DEBUG
/*
reg PoC_test1 = 1'b0;
reg PoC_test2 = 1'b0;
*/
// Main flow
always @(posedge clk_sys) begin
cmd_fskip <= 1'b0;
if (!cmd_switchres && vga_frameskip && vblank_core && vga_vcount > PoC_interlaced) begin
vga_frameskip <= 1'b0;
vga_frameskip_prev <= 1'b1;
end
// verify if vram has pixels needed for next line to activate non volatile framebuffer (cmd_fskip)
if ((hps_frameskip || cmd_logo) && PoC_frame_vram != 0) begin
if (vga_vcount <= PoC_interlaced && vram_queue == 24'd0) begin // raster at the end of frame and vram is empty
cmd_fskip <= 1'b1;
PoC_state_frameskip <= S_Blit_Auto_First;
end else
if (!vblank_core) begin
if (vga_vcount + 1 + PoC_interlaced >= PoC_V && PoC_H > vram_queue && vram_queue + 20 < vram_pixels && vga_pixels > vram_pixels && vram_pixels > (PoC_H << 2)) begin // last line interlaced
cmd_fskip <= 1'b1;
PoC_state_frameskip <= S_Blit_Auto_End;
end else
if (vga_vcount + 1 + PoC_interlaced < PoC_V && PoC_H > vram_queue && vram_queue + 20 < vram_pixels && ((PoC_H * (vga_vcount + 10'd1 + PoC_interlaced)) >> PoC_FB_interlaced) > vram_pixels) begin // next line
cmd_fskip <= 1'b1;
PoC_state_frameskip <= S_Blit_Auto_Line;
end
end
end
// case -> only evaluates first match (break implicit), if not then default
case (state)
S_Idle: // start?
begin
//error_overlay <= 1'b0;
{r_in, g_in, b_in} <= {8'h00,8'h00,8'h00};
vga_reset <= 1'b0;
vga_frame_reset <= 1'b1;
vga_soft_reset <= 1'b0;
vga_wait_vblank <= 1'b0;
vga_frameskip <= 1'b0;
vga_frameskip_prev <= 1'b0;
vram_reset <= 1'b1;
vram_active <= 1'b0;
vram_wren1 <= 1'b0;
vram_wren2 <= 1'b0;
vram_wren3 <= 1'b0;
vram_wren4 <= 1'b0;
vram_drive_raw <= 1'b0;
vram_drive_lz4 <= 1'b0;
ddr_data_write <= 1'b0;
ddr_data_req <= 1'b0;
ddr_burst <= 8'd1;
ddr_addr <= 28'd0;
sound_reset <= 1'b0;
sound_wren1 <= 1'b0;
sound_wren2 <= 1'b0;
sound_wren3 <= 1'b0;
sound_wren4 <= 1'b0;
PoC_FB_interlaced <= 1'b0;
PoC_interlaced <= 1'b0;
PoC_frame_switchres <= 24'd0;
PoC_subframe_bl_vram <= 16'd0;
PoC_subframe_px_vram <= 24'd0;
PoC_subframe_vram_bytes <= 28'd0;
PoC_frame_vram <= 24'd0;
PoC_frame_ddr <= 24'd0;
PoC_subframe_px_ddr <= 24'd0;
PoC_subframe_ddr_bytes <= 28'd0;
PoC_subframe_bl_ddr <= 16'd0;
PoC_frame_rgb_offset <= 2'd0;
auto_blit <= 1'b0;
lz4_run <= 1'b0;
lz4_reset <= 1'b0;
lz4_compressed_bytes <= 32'd0;
PoC_frame_lz4 <= 24'd0;
PoC_subframe_blit_lz4 <= 16'd0;
PoC_frame_lz4_ddr <= 24'd0;
PoC_subframe_lz4_ddr_bytes <= 32'd0;
PoC_subframe_blit_lz4_ddr <= 16'd0;
PoC_subframe_wr_bytes <= 28'd0;
PoC_frame_lz4_FB <= 1'b0;
PoC_lz4_resume_blit <= 1'b0;
PoC_lz4_resume_audio <= 1'b0;
PoC_subframe_px_lz4 <= 24'd0;
PoC_lz4_ABCD <= 2'd0;
PoC_lz4_field <= 2'd0;
auto_blit_lz4 <= 1'b0;
if (cmd_init) state <= S_Dispatcher;
end
S_Dispatcher: // what to do? dispatcher
begin
{r_in, g_in, b_in} <= {8'h00,8'h00,8'h00};
vga_frame_reset <= 1'b0;
vram_reset <= 1'b0;
vram_wren1 <= 1'b0;
vram_wren2 <= 1'b0;
vram_wren3 <= 1'b0;
vram_wren4 <= 1'b0;
sound_wren1 <= 1'b0;
sound_wren2 <= 1'b0;
sound_wren3 <= 1'b0;
sound_wren4 <= 1'b0;
ddr_data_write <= 1'b0;
ddr_data_req <= 1'b0;
ddr_addr <= 28'd0;
lz4_reset <= 1'b0;
vram_active <= cmd_init ? 1'b1 : 1'b0;
if (!cmd_init) begin // reset to defaults
state <= S_Defaults;
end else if (!ddr_busy) begin
if (cmd_scandoubler != PoC_pll_S && (vblank_core || PoC_subframe_px_vram == 0)) begin // scandoubler request for 480i
state <= S_Switchres_Scandoubler;
end else
if (cmd_switchres && switchres_frame <= vga_frame && (vga_vcount > PoC_V || vga_frame == 0)) begin // request modeline (apply after blit)
reset_switchres <= 1'b1;
ddr_data_req <= 1'b1;
ddr_addr <= DDR_SW_HEADER;
ddr_burst <= 8'd3;
ddr_data_idx <= 2'd0;
state <= S_Switchres_Header;
end else
if (cmd_audio) begin // audio blit samples requested from hps
reset_audio <= 1'b1;
PoC_audio_samples <= audio_samples;
PoC_audio_ddr_bytes <= audio_samples << sound_chan;
PoC_audio_count <= 16'd0;
PoC_audio_count_bytes <= 24'd0;
state <= S_Audio_Prepare;
end else
if (cmd_fskip) begin // use framebuffer avoiding black screeen (auto blit)
state <= S_Blit_Auto_Skip;
end else
if ((cmd_blit || auto_blit) && !vga_frameskip) begin // pixels blit if fskip isn't activated
reset_blit <= cmd_blit && !cmd_switchres ? 1'b1 : 1'b0;
ddr_burst <= 8'd1;
ddr_data_req <= 1'b1;
state <= S_Blit_Header_Raw;
end else
if (cmd_blit_lz4 || auto_blit_lz4) begin // lz4 blit
reset_blit_lz4 <= cmd_blit_lz4 && !cmd_switchres ? 1'b1 : 1'b0;
ddr_burst <= 8'd1;
ddr_data_req <= 1'b1;
ddr_addr <= DDR_LZ_HEADER;
state <= S_Blit_Header_Lz4;
end
end
end
S_Blit_Header_Raw: // header ready
begin
if (ddr_busy) ddr_data_req <= 1'b0;
reset_blit <= 1'b0;
vram_reset <= !vram_synced;
if (ddr_data_ready) begin
ddr_data_req <= 1'b0;
auto_blit <= PoC_frame_vram >= ddr_data[23:0] || (!cmd_switchres && ddr_data[23:0] <= switchres_frame) ? 1'b0 : 1'b1;
state <= cmd_switchres && ddr_data[23:0] > switchres_frame && PoC_subframe_px_vram == 0 ? S_Dispatcher : S_Blit_Raw;
if ((!cmd_switchres && ddr_data[23:0] <= switchres_frame) || ddr_data[23:0] < vga_frame || ddr_data[23:0] < PoC_frame_ddr || ddr_data[23:0] < PoC_frame_vram || ((vblank_core || !vram_pixels || !vram_synced) && ddr_data[23:0] <= vga_frame)) begin //frame arrives later (discard contaminate vram -> latency)
state <= S_Dispatcher;
PoC_subframe_px_vram <= 24'd0;
PoC_subframe_bl_vram <= 16'd0;
PoC_subframe_px_ddr <= 24'd0;
PoC_subframe_bl_ddr <= 16'd0;
PoC_subframe_vram_bytes <= 28'd0;
PoC_subframe_ddr_bytes <= 28'd0;
PoC_frame_rgb_offset <= 2'd0;
if (ddr_data[23:0] > PoC_frame_vram) begin
PoC_frame_vram <= ddr_data[23:0];
PoC_frame_ddr <= ddr_data[23:0];
end
end else begin
if (ddr_data[23:0] > PoC_frame_ddr && PoC_subframe_px_vram != 0 && PoC_frame_vram < PoC_frame_ddr && vram_synced) begin // frame arrives soon, finish blit last asap
PoC_subframe_px_ddr <= vga_pixels;
PoC_subframe_bl_ddr <= PoC_subframe_bl_vram + 1'd1;
end else begin
PoC_frame_ddr <= ddr_data[23:0];
PoC_subframe_px_ddr <= ddr_data[47:24];
PoC_subframe_bl_ddr <= ddr_data[47:24] == vga_pixels ? PoC_subframe_bl_vram + 1'b1 : ddr_data[63:48];
end
end
end
end
S_Blit_Raw: // get pixels to blit from header
begin
state <= S_Dispatcher;
vram_reset <= 1'b0;
if (PoC_frame_ddr > PoC_frame_vram && PoC_subframe_px_ddr > PoC_subframe_px_vram && PoC_subframe_bl_ddr > PoC_subframe_bl_vram) begin
if (PoC_subframe_px_vram == 0) begin
PoC_subframe_vram_bytes <= 24'd0;
vga_frameskip_prev <= 1'b0;
PoC_frame_rgb_offset <= 2'd0;