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il.cpp
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#include <stdarg.h>
#include "il.h"
#include "lowlevelilinstruction.h"
using namespace BinaryNinja;
using namespace armv7;
#define ILREG(op) il.Register(get_register_size((op).reg), (op).reg)
#define ILOFFSETREG(op) il.Register(get_register_size((op).offset), (op).offset)
//Get N set bits at offset O
#define BITMASK(N,O) (((1LL << N) - 1) << O)
static inline ExprId DirectJump(Architecture* arch, LowLevelILFunction& il, uint64_t target, size_t addrSize)
{
BNLowLevelILLabel* label = il.GetLabelForAddress(arch, target);
if (label)
return il.Goto(*label);
else
return il.Jump(il.ConstPointer(addrSize, target));
return 0;
}
static inline ExprId SetRegisterOrBranch(LowLevelILFunction& il, enum Register reg, ExprId expr, uint32_t flags=0)
{
if (reg == REG_PC)
return il.Jump(expr);
else
return il.SetRegister(get_register_size(reg), reg, expr, flags);
}
static inline ExprId ReadRegisterOrPointer(LowLevelILFunction& il, const InstructionOperand& op, size_t addr)
{
if (op.reg == REG_PC)
return il.ConstPointer(4, (addr+8));
return il.Register(get_register_size(op.reg), op.reg);
}
ExprId GetCondition(LowLevelILFunction& il, Condition cond)
{
switch(cond)
{
case COND_EQ: return il.FlagCondition(LLFC_E);
case COND_NE: return il.FlagCondition(LLFC_NE);
case COND_CS: return il.FlagCondition(LLFC_UGE);
case COND_CC: return il.FlagCondition(LLFC_ULT);
case COND_MI: return il.FlagCondition(LLFC_NEG);
case COND_PL: return il.FlagCondition(LLFC_POS);
case COND_VS: return il.FlagCondition(LLFC_O);
case COND_VC: return il.FlagCondition(LLFC_NO);
case COND_HI: return il.FlagCondition(LLFC_UGT);
case COND_LS: return il.FlagCondition(LLFC_ULE);
case COND_GE: return il.FlagCondition(LLFC_SGE);
case COND_LT: return il.FlagCondition(LLFC_SLT);
case COND_GT: return il.FlagCondition(LLFC_SGT);
case COND_LE: return il.FlagCondition(LLFC_SLE);
case COND_NONE:
case COND_NONE2:
return il.Const(0, 1); //Always branch
default:
return il.Const(0, 0); //Never branch
}
}
static void ConditionalJump(Architecture* arch, LowLevelILFunction& il, Condition cond, size_t addrSize, uint64_t t, uint64_t f)
{
BNLowLevelILLabel* trueLabel = il.GetLabelForAddress(arch, t);
BNLowLevelILLabel* falseLabel = il.GetLabelForAddress(arch, f);
if (UNCONDITIONAL(cond))
{
il.AddInstruction(DirectJump(arch, il, t, addrSize));
return;
}
if (trueLabel && falseLabel)
{
il.AddInstruction(il.If(GetCondition(il, cond), *trueLabel, *falseLabel));
return;
}
LowLevelILLabel trueCode, falseCode;
if (trueLabel)
{
il.AddInstruction(il.If(GetCondition(il, cond), *trueLabel, falseCode));
il.MarkLabel(falseCode);
il.AddInstruction(il.Jump(il.ConstPointer(addrSize, f)));
return;
}
if (falseLabel)
{
il.AddInstruction(il.If(GetCondition(il, cond), trueCode, *falseLabel));
il.MarkLabel(trueCode);
il.AddInstruction(il.Jump(il.ConstPointer(addrSize, t)));
return;
}
il.AddInstruction(il.If(GetCondition(il, cond), trueCode, falseCode));
il.MarkLabel(trueCode);
il.AddInstruction(il.Jump(il.ConstPointer(addrSize, t)));
il.MarkLabel(falseCode);
il.AddInstruction(il.Jump(il.ConstPointer(addrSize, f)));
}
static void ConditionExecute(LowLevelILFunction& il, Condition cond, ExprId trueCase)
{
LowLevelILLabel trueCode, falseCode;
if (UNCONDITIONAL(cond))
{
il.AddInstruction(trueCase);
return;
}
il.AddInstruction(il.If(GetCondition(il, cond), trueCode, falseCode));
il.MarkLabel(trueCode);
il.AddInstruction(trueCase);
il.MarkLabel(falseCode);
}
static ExprId GetShifted(LowLevelILFunction& il, Register reg, ExprId ShiftAmount, Shift shift)
{
if (ShiftAmount == 0)
return il.Register(get_register_size(reg), reg);
switch (shift)
{
case SHIFT_NONE:
return il.Register(get_register_size(reg), reg);
case SHIFT_LSR:
return il.LogicalShiftRight(get_register_size(reg),
il.Register(get_register_size(reg), reg),
ShiftAmount);
case SHIFT_LSL:
return il.ShiftLeft(get_register_size(reg),
il.Register(get_register_size(reg), reg),
ShiftAmount);
case SHIFT_ASR:
return il.ArithShiftRight(get_register_size(reg),
il.Register(get_register_size(reg), reg),
ShiftAmount);
case SHIFT_ROR:
return il.RotateRight(get_register_size(reg),
il.Register(get_register_size(reg), reg),
ShiftAmount);
case SHIFT_RRX:
//RRX can only shift 1 at a time
return il.RotateRightCarry(get_register_size(reg),
il.Register(get_register_size(reg), reg),
il.Const(1, 1), il.Flag(IL_FLAG_C));
default:
return 0;
}
}
static ExprId GetShiftedOffset(LowLevelILFunction& il, InstructionOperand& op)
{
return GetShifted(il, op.offset, il.Const(1, op.imm), op.shift);
}
static ExprId GetShiftedRegister(LowLevelILFunction& il, InstructionOperand& op)
{
return GetShifted(il, op.reg, il.Const(1, op.imm), op.shift);
}
static ExprId ReadAddress(LowLevelILFunction& il, InstructionOperand& op, size_t addr)
{
//This should only be called by with cls or MEM_* or label
// <op.imm>
// <op.reg> +/- <op.imm>
// <op.reg> +/- (<op.offset> <shift> <op.imm>)
ExprId expr;
if (op.cls == LABEL)
return il.ConstPointer(4, op.imm);
if (op.shift == SHIFT_NONE)
{
if (op.flags.offsetRegUsed == 1)
{
expr = il.Register(get_register_size(op.offset), op.offset);
}
else
{
expr = il.Const(4, op.imm);
}
}
else
{
if (op.flags.offsetRegUsed == 1)
expr = GetShiftedOffset(il, op);
else
return GetShiftedRegister(il, op);
}
if (op.flags.add == 1)
return il.Add(4, ReadRegisterOrPointer(il, op, addr), expr);
else
return il.Sub(4, ReadRegisterOrPointer(il, op, addr), expr);
}
static ExprId ReadILOperand(LowLevelILFunction& il, InstructionOperand& op, size_t addr, bool isPointer=false)
{
switch (op.cls)
{
case IMM64:
if (isPointer)
return il.ConstPointer(8, op.imm);
return il.Const(8, op.imm);
case IMM:
case LABEL:
if (isPointer)
return il.ConstPointer(4, op.imm);
return il.Const(4, op.imm);
case REG:
if (op.shift == SHIFT_NONE)
return ReadRegisterOrPointer(il, op, addr);
else if (op.flags.offsetRegUsed == 1)
{
return GetShiftedOffset(il, op);
}
else
{
return GetShiftedRegister(il, op);
}
break;
case MEM_IMM:
if (op.shift == SHIFT_NONE)
{
if (op.flags.offsetRegUsed == 1)
{
return op.flags.add?
il.Add(4, ReadRegisterOrPointer(il, op, addr), il.Register(get_register_size(op.reg), op.offset)):
il.Sub(4, ReadRegisterOrPointer(il, op, addr), il.Register(get_register_size(op.reg), op.offset));
}
else
{
if (op.imm == 0)
{
return ReadRegisterOrPointer(il, op, addr);
}
return op.flags.add?
il.Add(4, ReadRegisterOrPointer(il, op, addr), il.Const(4, op.imm)):
il.Sub(4, ReadRegisterOrPointer(il, op, addr), il.Const(4, op.imm));
}
}
else
return op.flags.add?
il.Add(4, ReadRegisterOrPointer(il, op, addr), GetShiftedOffset(il, op)):
il.Sub(4, ReadRegisterOrPointer(il, op, addr), GetShiftedOffset(il, op));
case MEM_PRE_IDX:
case MEM_POST_IDX:
return GetShiftedRegister(il, op);
case FIMM32:
case NONE:
default:
il.AddInstruction(il.Unimplemented());
break;
}
return 0;
}
static void Load(
LowLevelILFunction& il,
bool sx,
size_t size,
InstructionOperand& dst,
InstructionOperand& src,
size_t addr)
{
ExprId value, memValue;
size_t dstSize = get_register_size(dst.reg);
value = ReadAddress(il, src, addr);
switch (src.cls)
{
case MEM_PRE_IDX:
memValue = il.Load(size, ILREG(src));
if (size != dstSize)
{
if (sx)
memValue = il.SignExtend(dstSize, memValue);
else
memValue = il.ZeroExtend(dstSize, memValue);
}
il.AddInstruction(SetRegisterOrBranch(il, src.reg, value));
il.AddInstruction(SetRegisterOrBranch(il, dst.reg, memValue));
break;
case MEM_POST_IDX:
memValue = il.Load(size, ILREG(src));
if (size != dstSize)
{
if (sx)
memValue = il.SignExtend(dstSize, memValue);
else
memValue = il.ZeroExtend(dstSize, memValue);
}
il.AddInstruction(SetRegisterOrBranch(il, dst.reg, memValue));
il.AddInstruction(SetRegisterOrBranch(il, src.reg, value));
break;
case MEM_IMM:
case LABEL:
memValue = il.Load(size, value);
if (size != dstSize)
{
if (sx)
memValue = il.SignExtend(dstSize, memValue);
else
memValue = il.ZeroExtend(dstSize, memValue);
}
il.AddInstruction(SetRegisterOrBranch(il, dst.reg, memValue));
break;
default:
il.AddInstruction(il.Unimplemented());
break;
}
}
static void LoadExclusive(
LowLevelILFunction& il,
bool sx,
size_t size,
InstructionOperand& dst,
InstructionOperand& src,
size_t addr)
{
ExprId address = ReadAddress(il, src, addr);
size_t srcSize = get_register_size(src.reg);
il.AddInstruction(il.Intrinsic({ },
ARMV7_INTRIN_SET_EXCLUSIVE_MONITORS,
{ address, il.Const(1, srcSize) }));
Load(il, sx, size, dst, src, addr);
}
static void LoadPair(
Architecture* arch,
LowLevelILFunction& il,
InstructionOperand& dst1,
InstructionOperand& dst2,
InstructionOperand& src,
size_t addr)
{
ExprId address, value;
size_t dstSize = get_register_size(dst1.reg);
if (src.cls == MEM_PRE_IDX || src.cls == MEM_POST_IDX)
address = ILREG(src);
else
address = ReadAddress(il, src, addr);
value = il.Load(dstSize * 2, address);
if (src.cls == MEM_PRE_IDX)
il.AddInstruction(SetRegisterOrBranch(il, src.reg, ReadAddress(il, src, addr)));
ExprId setReg;
if (arch->GetEndianness() == LittleEndian)
setReg = il.SetRegisterSplit(dstSize, dst2.reg, dst1.reg, value);
else
setReg = il.SetRegisterSplit(dstSize, dst1.reg, dst2.reg, value);
il.AddInstruction(setReg);
if (src.cls == MEM_POST_IDX)
il.AddInstruction(SetRegisterOrBranch(il, src.reg, ReadAddress(il, src, addr)));
}
static void LoadPairExclusive(
Architecture* arch,
LowLevelILFunction& il,
InstructionOperand& dst1,
InstructionOperand& dst2,
InstructionOperand& src,
size_t addr)
{
ExprId address = ReadAddress(il, src, addr);
size_t srcSize = get_register_size(src.reg);
il.AddInstruction(il.Intrinsic({ },
ARMV7_INTRIN_SET_EXCLUSIVE_MONITORS,
{ address, il.Const(1, srcSize) }));
LoadPair(arch, il, dst1, dst2, src, addr);
}
static void Store(
LowLevelILFunction& il,
uint8_t size,
InstructionOperand& src,
InstructionOperand& dst,
size_t addr)
{
ExprId address = ReadAddress(il, dst, addr);
size_t dstSize = get_register_size(dst.reg);
ExprId regSrc = ILREG(src);
size_t srcSize = get_register_size(src.reg);
if (size < srcSize)
regSrc = il.LowPart(size, regSrc);
switch (dst.cls)
{
case MEM_IMM:
il.AddInstruction(il.Store(size, address, regSrc));
break;
case MEM_PRE_IDX:
il.AddInstruction(il.SetRegister(dstSize, dst.reg, address));
il.AddInstruction(il.Store(size, ILREG(dst), regSrc));
break;
case MEM_POST_IDX:
il.AddInstruction(il.Store(size, ILREG(dst), regSrc));
il.AddInstruction(il.SetRegister(dstSize, dst.reg, address));
break;
default:
il.AddInstruction(il.Unimplemented());
break;
}
}
static void StoreExclusive(
LowLevelILFunction& il,
uint8_t size,
InstructionOperand& status,
InstructionOperand& src,
InstructionOperand& dst,
size_t addr)
{
ExprId address = ReadAddress(il, dst, addr);
size_t dstSize = get_register_size(dst.reg);
LowLevelILLabel trueCode, falseCode;
size_t statusSize = get_register_size(status.reg);
il.AddInstruction(il.Intrinsic({ RegisterOrFlag::Register(status.reg) },
ARMV7_INTRIN_EXCLUSIVE_MONITORS_PASS,
{ address, il.Const(1, dstSize) }));
il.AddInstruction(il.If(il.CompareEqual(statusSize, il.Register(statusSize, status.reg), il.Const(statusSize, 1)),
trueCode, falseCode));
il.MarkLabel(trueCode);
Store(il, size, src, dst, addr);
il.MarkLabel(falseCode);
}
static void StorePair(
Architecture* arch,
LowLevelILFunction& il,
InstructionOperand& src1,
InstructionOperand& src2,
InstructionOperand& dst,
size_t addr)
{
ExprId address, value;
size_t srcSize = get_register_size(src1.reg);
LowLevelILLabel trueCode, falseCode;
if (dst.cls == MEM_POST_IDX)
address = ILREG(dst);
else
address = ReadAddress(il, dst, addr);
if (arch->GetEndianness() == LittleEndian)
value = il.RegisterSplit(srcSize, src2.reg, src1.reg);
else
value = il.RegisterSplit(srcSize, src1.reg, src2.reg);
il.AddInstruction(il.Store(srcSize * 2, address, value));
if (dst.cls == MEM_POST_IDX || dst.cls == MEM_PRE_IDX)
il.AddInstruction(SetRegisterOrBranch(il, dst.reg, ReadAddress(il, dst, addr)));
}
static void StorePairExclusive(
Architecture* arch,
LowLevelILFunction& il,
InstructionOperand& status,
InstructionOperand& src1,
InstructionOperand& src2,
InstructionOperand& dst,
size_t addr)
{
ExprId address = ReadAddress(il, dst, addr);
LowLevelILLabel trueCode, falseCode;
size_t statusSize = get_register_size(status.reg);
il.AddInstruction(il.Intrinsic({ RegisterOrFlag::Register(status.reg) },
ARMV7_INTRIN_EXCLUSIVE_MONITORS_PASS,
{ address, il.Const(1, 8) }));
il.AddInstruction(il.If(il.CompareEqual(statusSize, il.Register(statusSize, status.reg), il.Const(statusSize, 1)),
trueCode, falseCode));
il.MarkLabel(trueCode);
StorePair(arch, il, src1, src2, dst, addr);
il.MarkLabel(falseCode);
}
static void Saturate(LowLevelILFunction& il, uint32_t dest, ExprId to_saturate, ExprId saturate_to, bool is_signed)
{
LowLevelILLabel trueCode, falseCode, endCode;
LowLevelILLabel trueCode2, falseCode2, endCode2;
if (is_signed)
{
il.AddInstruction(il.If(il.CompareSignedLessThan(4, to_saturate, il.Neg(4, saturate_to)), trueCode, falseCode));
il.MarkLabel(trueCode);
il.AddInstruction(il.SetRegister(4, dest, il.Neg(4, saturate_to)));
il.AddInstruction(il.Goto(endCode));
il.MarkLabel(falseCode);
il.MarkLabel(endCode);
il.AddInstruction(il.If(il.CompareSignedGreaterThan(4, to_saturate, saturate_to), trueCode2, falseCode2));
il.MarkLabel(trueCode2);
il.AddInstruction(il.SetRegister(4, dest, saturate_to));
il.AddInstruction(il.Goto(endCode2));
il.MarkLabel(falseCode2);
il.AddInstruction(il.SetRegister(4, dest, to_saturate));
il.MarkLabel(endCode2);
}
else
{
il.AddInstruction(il.If(il.CompareSignedLessThan(4, to_saturate, il.Const(4, 0)), trueCode, falseCode));
il.MarkLabel(trueCode);
il.AddInstruction(il.SetRegister(4, dest, il.Const(4, 0)));
il.AddInstruction(il.Goto(endCode));
il.MarkLabel(falseCode);
il.MarkLabel(endCode);
il.AddInstruction(il.If(il.CompareSignedGreaterThan(4, to_saturate, saturate_to), trueCode2, falseCode2));
il.MarkLabel(trueCode2);
il.AddInstruction(il.SetRegister(4, dest, saturate_to));
il.AddInstruction(il.Goto(endCode2));
il.MarkLabel(falseCode2);
il.AddInstruction(il.SetRegister(4, dest, to_saturate));
il.MarkLabel(endCode2);
}
}
uint32_t GetNumberOfRegs(uint16_t regList)
{
uint32_t nregs = 0;
for (uint32_t i = 0; i < 16; i++)
{
if (((regList >> i) & 1) == 1)
nregs++;
}
return nregs;
}
void ConditionExecute(size_t addrSize, Condition cond, Instruction& instr, LowLevelILFunction& il,
std::function<void (size_t addrSize, Instruction& instr, LowLevelILFunction& il)> conditionalCode)
{
if (UNCONDITIONAL(cond))
{
conditionalCode(addrSize, instr, il);
return;
}
LowLevelILLabel trueLabel, falseLabel;
il.AddInstruction(il.If(GetCondition(il, cond), trueLabel, falseLabel));
il.MarkLabel(trueLabel);
conditionalCode(addrSize, instr, il);
il.AddInstruction(il.Goto(falseLabel));
il.MarkLabel(falseLabel);
}
void LoadOrStoreWithAdjustment(InstructionOperand& src,
InstructionOperand& dst,
LowLevelILFunction& il,
bool load,
bool increment,
bool before)
{
if (before)
{
if (increment)
{
il.AddInstruction(il.SetRegister(get_register_size(src.reg), src.reg,
il.Add(get_register_size(src.reg), ILREG(src), il.Const(1, get_register_size(src.reg)))));
}
else
{
il.AddInstruction(il.SetRegister(get_register_size(src.reg), src.reg,
il.Sub(get_register_size(src.reg), ILREG(src), il.Const(1, get_register_size(src.reg)))));
}
}
if (load)
{
il.AddInstruction(il.SetRegister(get_register_size(dst.reg), dst.reg,
il.Load(get_register_size(dst.reg), ILREG(src))));
}
else
{
il.AddInstruction(il.Store(get_register_size(dst.reg), ILREG(dst), ILREG(src)));
}
if (!before)
{
if (increment)
{
il.AddInstruction(il.SetRegister(get_register_size(src.reg), src.reg,
il.Add(get_register_size(src.reg), ILREG(src), il.Const(1, get_register_size(src.reg)))));
}
else
{
il.AddInstruction(il.SetRegister(get_register_size(src.reg), src.reg,
il.Sub(get_register_size(src.reg), ILREG(src), il.Const(1, get_register_size(src.reg)))));
}
}
}
bool GetLowLevelILForArmInstruction(Architecture* arch, uint64_t addr, LowLevelILFunction& il, Instruction& instr, size_t addrSize)
{
(void)arch;
(void)addr;
(void)addrSize;
InstructionOperand& op1 = instr.operands[0];
InstructionOperand& op2 = instr.operands[1];
InstructionOperand& op3 = instr.operands[2];
InstructionOperand& op4 = instr.operands[3];
InstructionOperand& op5 = instr.operands[4];
InstructionOperand& op6 = instr.operands[5];
LowLevelILLabel trueLabel, falseLabel, endLabel, loopBody, loopStart, loopExit;
uint32_t flagOperation[2] = {IL_FLAGWRITE_NONE, IL_FLAGWRITE_ALL};
LowLevelILLabel trueCode, falseCode, endCode;
switch (instr.operation)
{
case ARMV7_ADD:
ConditionExecute(il, instr.cond, SetRegisterOrBranch(il, op1.reg,
il.Add(get_register_size(op1.reg),
ReadRegisterOrPointer(il, op2, addr),
ReadILOperand(il, op3, addr), flagOperation[instr.setsFlags])));
break;
case ARMV7_ADDW:
ConditionExecute(il, instr.cond, SetRegisterOrBranch(il, op1.reg,
il.Add(get_register_size(op1.reg),
ReadRegisterOrPointer(il, op2, addr),
ReadILOperand(il, op3, addr), IL_FLAGWRITE_NONE)));
break;
case ARMV7_ADC:
ConditionExecute(il, instr.cond, SetRegisterOrBranch(il, op1.reg,
il.AddCarry(get_register_size(op1.reg),
ReadRegisterOrPointer(il, op2, addr),
ReadILOperand(il, op3, addr), il.Flag(IL_FLAG_C), flagOperation[instr.setsFlags])));
break;
case ARMV7_ADR:
ConditionExecute(il, instr.cond,
SetRegisterOrBranch(il, op1.reg,
il.ConstPointer(get_register_size(op1.reg), op2.imm)));
break;
case ARMV7_AND:
ConditionExecute(il, instr.cond, SetRegisterOrBranch(il, op1.reg,
il.And(get_register_size(op1.reg),
ReadRegisterOrPointer(il, op2, addr),
ReadILOperand(il, op3, addr), flagOperation[instr.setsFlags])));
break;
case ARMV7_ASR:
ConditionExecute(il, instr.cond,
SetRegisterOrBranch(il, op1.reg,
il.ArithShiftRight(get_register_size(op2.reg),
ReadRegisterOrPointer(il, op2, addr),
ReadILOperand(il, op3, addr), flagOperation[instr.setsFlags])));
break;
case ARMV7_B:
ConditionalJump(arch, il, instr.cond, addrSize, op1.imm, addr + 4);
return false;
case ARMV7_BFC:
ConditionExecute(il, instr.cond, SetRegisterOrBranch(il, op1.reg,
il.And(get_register_size(op1.reg), ReadRegisterOrPointer(il, op1, addr),
il.Const(get_register_size(op1.reg), ~(((1<<op3.imm) - 1) << op2.imm)))));
break;
case ARMV7_BFI:
{
uint32_t lsb = op3.imm;
uint32_t width_mask = (1<<op4.imm) - 1;
uint32_t mask = width_mask << lsb;
//bit field insert: op1 = (op1 & (~(<width_mask> << lsb))) | ((op2 & <width_mask>) << lsb)
//width_mask = (1<<width)-1
ConditionExecute(il, instr.cond, SetRegisterOrBranch(il, op1.reg,
il.Or(get_register_size(op1.reg),
il.And(get_register_size(op1.reg),
ReadRegisterOrPointer(il, op1, addr),
il.Const(4, ~mask)
),
il.ShiftLeft(4,
il.And(get_register_size(op1.reg),
ReadRegisterOrPointer(il, op2, addr),
il.Const(get_register_size(op1.reg), width_mask)
),
il.Const(4, lsb)))));
break;
}
case ARMV7_BKPT:
il.AddInstruction(il.Breakpoint());
break;
case ARMV7_BL:
ConditionExecute(il, instr.cond, il.Call(il.ConstPointer(4, op1.imm)));
break;
case ARMV7_BXJ:
case ARMV7_BX:
ConditionExecute(il, instr.cond, il.Jump(ReadILOperand(il, op1, addr, true)));
break;
case ARMV7_BLX:
if (UNCONDITIONAL(instr.cond) && (op1.cls == REG) && (op1.reg == REG_LR))
il.AddInstruction(il.Jump(ReadILOperand(il, op1, addr, true)));
else
ConditionExecute(il, instr.cond, il.Call(ReadILOperand(il, op1, addr, true)));
break;
case ARMV7_BIC:
ConditionExecute(il, instr.cond, SetRegisterOrBranch(il, op1.reg,
il.And(get_register_size(op2.reg),
ReadRegisterOrPointer(il, op2, addr),
il.Not(get_register_size(op2.reg),
ReadILOperand(il, op3, addr)), flagOperation[instr.setsFlags]
)));
break;
case ARMV7_CLZ:
ConditionExecute(addr, instr.cond, instr, il, [&](size_t, Instruction&, LowLevelILFunction& il){
//Count leading zeros
//
// TEMP0 = 0
// TEMP1 = op2.reg
// while (TEMP1 != 0)
// TEMP1 = TEMP1 >> 1
// TEMP0 = TEMP0 + 1
// op1.reg = 32 - TEMP0
il.AddInstruction(il.SetRegister(4, LLIL_TEMP(0), il.Const(4, 0)));
il.AddInstruction(il.SetRegister(4, LLIL_TEMP(1), ReadRegisterOrPointer(il, op2, addr)));
il.AddInstruction(il.Goto(loopStart));
il.MarkLabel(loopStart);
il.AddInstruction(il.If(il.CompareNotEqual(4, il.Register(4, LLIL_TEMP(1)), il.Const(4, 0)), loopBody, loopExit));
il.MarkLabel(loopBody);
il.AddInstruction(il.SetRegister(4, LLIL_TEMP(1), il.LogicalShiftRight(4, il.Register(4, LLIL_TEMP(1)), il.Const(4,1))));
il.AddInstruction(il.SetRegister(4, LLIL_TEMP(0), il.Add(4, il.Register(4, LLIL_TEMP(0)), il.Const(4,1))));
il.AddInstruction(il.Goto(loopStart));
il.MarkLabel(loopExit);
il.AddInstruction(SetRegisterOrBranch(il, op1.reg, il.Sub(4, il.Const(4, 32), il.Register(4, LLIL_TEMP(0)))));
});
break;
case ARMV7_CMN:
ConditionExecute(il, instr.cond, il.Add(get_register_size(op1.reg),
ReadRegisterOrPointer(il, op1, addr),
ReadILOperand(il, op2, addr), IL_FLAGWRITE_ALL));
break;
case ARMV7_CMP:
ConditionExecute(il, instr.cond, il.Sub(get_register_size(op1.reg),
ReadRegisterOrPointer(il, op1, addr),
ReadILOperand(il, op2, addr), IL_FLAGWRITE_ALL));
break;
case ARMV7_EOR:
ConditionExecute(il, instr.cond, SetRegisterOrBranch(il, op1.reg,
il.Xor(get_register_size(op1.reg),
ReadRegisterOrPointer(il, op2, addr),
ReadILOperand(il, op3, addr), flagOperation[instr.setsFlags])));
break;
case ARMV7_LDM:
case ARMV7_LDMIA:
case ARMV7_LDMIB:
case ARMV7_LDMDA:
case ARMV7_LDMDB:
ConditionExecute(addrSize, instr.cond, instr, il,
[&](size_t addrSize, Instruction& instr, LowLevelILFunction& il)
{
(void) addrSize;
(void) instr;
//Cache src address register in case it's mutated by loads
ExprId base = 0;
switch (instr.operation)
{
case ARMV7_LDM:
case ARMV7_LDMIA:
base = ILREG(op1);
break;
case ARMV7_LDMIB:
base = il.Add(4, ILREG(op1), il.Const(1, 4));
break;
case ARMV7_LDMDB:
base = il.Sub(4, ILREG(op1), il.Const(1, 4 * GetNumberOfRegs(op2.reg)));
break;
case ARMV7_LDMDA:
base = il.Sub(4, ILREG(op1), il.Const(1, 4 * GetNumberOfRegs(op2.reg) - 4));
break;
default:
break;
}
il.AddInstruction(il.SetRegister(4, LLIL_TEMP(0), base));
for (int reg = 0, slot = 0; reg < 16; reg++)
{
if (op2.reg & 1 << reg)
{
il.AddInstruction(
il.SetRegister(4,
// writes to PC are deferred to a final Jump
(reg != REG_PC) ? reg : LLIL_TEMP(1),
il.Load(4,
il.Add(4,
il.Register(4, LLIL_TEMP(0)),
il.Const(1, 4 * slot++)
)
)
)
);
}
}
if (op1.flags.wb)
{
ExprId wb;
switch (instr.operation)
{
case ARMV7_LDM:
case ARMV7_LDMIA:
wb = il.Const(1, 4 * GetNumberOfRegs(op2.reg));
wb = il.Add(4, il.Register(4, LLIL_TEMP(0)), wb);
break;
case ARMV7_LDMIB:
wb = il.Const(1, 4 * GetNumberOfRegs(op2.reg) - 4);
wb = il.Add(4, il.Register(4, LLIL_TEMP(0)), wb);
break;
case ARMV7_LDMDB:
wb = il.Register(4, LLIL_TEMP(0));
break;
case ARMV7_LDMDA:
wb = il.Const(1, 4);
wb = il.Sub(4, il.Register(4, LLIL_TEMP(0)), wb);
break;
default:
break;
}
//if (1 << op1.reg & op2.reg) [[unlikely]] {
if (1 << op1.reg & op2.reg) {
wb = il.Undefined();
}
il.AddInstruction(il.SetRegister(4, op1.reg, wb));
}
if (op2.reg & REG_LIST_PC)
{
il.AddInstruction(il.Jump(il.Register(4, LLIL_TEMP(1))));
}
});
break;
case ARMV7_LDREX:
ConditionExecute(addrSize, instr.cond, instr, il,
[&](size_t addrSize, Instruction& instr, LowLevelILFunction& il)
{
(void) addrSize;
(void) instr;
LoadExclusive(il, false, 4, op1, op2, addr);
});
break;
case ARMV7_LDR:
case ARMV7_LDRT:
ConditionExecute(addrSize, instr.cond, instr, il,
[&](size_t addrSize, Instruction& instr, LowLevelILFunction& il)
{
(void) addrSize;
(void) instr;
Load(il, false, 4, op1, op2, addr);
});
break;
case ARMV7_LDREXH:
ConditionExecute(addrSize, instr.cond, instr, il,
[&](size_t addrSize, Instruction& instr, LowLevelILFunction& il)
{
(void) addrSize;
(void) instr;
LoadExclusive(il, false, 2, op1, op2, addr);
});
break;
case ARMV7_LDRH:
case ARMV7_LDRHT:
ConditionExecute(addrSize, instr.cond, instr, il,
[&](size_t addrSize, Instruction& instr, LowLevelILFunction& il)
{
(void) addrSize;
(void) instr;
Load(il, false, 2, op1, op2, addr);
});
break;
case ARMV7_LDREXB:
ConditionExecute(addrSize, instr.cond, instr, il,
[&](size_t addrSize, Instruction& instr, LowLevelILFunction& il)
{
(void) addrSize;
(void) instr;
LoadExclusive(il, false, 1, op1, op2, addr);
});
break;
case ARMV7_LDRB:
case ARMV7_LDRBT:
ConditionExecute(addrSize, instr.cond, instr, il,
[&](size_t addrSize, Instruction& instr, LowLevelILFunction& il)
{
(void) addrSize;
(void) instr;
Load(il, false, 1, op1, op2, addr);
});
break;
case ARMV7_LDRSH:
case ARMV7_LDRSHT:
ConditionExecute(addrSize, instr.cond, instr, il,
[&](size_t addrSize, Instruction& instr, LowLevelILFunction& il)
{
(void) addrSize;
(void) instr;
Load(il, true, 2, op1, op2, addr);
});
break;
case ARMV7_LDRSB:
case ARMV7_LDRSBT:
ConditionExecute(addrSize, instr.cond, instr, il,
[&](size_t addrSize, Instruction& instr, LowLevelILFunction& il)
{
(void) addrSize;
(void) instr;
Load(il, true, 1, op1, op2, addr);
});
break;
case ARMV7_LDREXD:
ConditionExecute(addrSize, instr.cond, instr, il,
[&](size_t addrSize, Instruction& instr, LowLevelILFunction& il)
{
(void) addrSize;
(void) instr;
LoadPairExclusive(arch, il, op1, op2, op3, addr);
});
break;
case ARMV7_LDRD:
ConditionExecute(addrSize, instr.cond, instr, il,
[&](size_t addrSize, Instruction& instr, LowLevelILFunction& il)
{
(void) addrSize;
(void) instr;
LoadPair(arch, il, op1, op2, op3, addr);
});
break;
case ARMV7_LSL:
ConditionExecute(il, instr.cond, SetRegisterOrBranch(il, op1.reg,
il.ShiftLeft(get_register_size(op2.reg),
ReadRegisterOrPointer(il, op2, addr),
ReadILOperand(il, op3, addr), flagOperation[instr.setsFlags])));
break;
case ARMV7_LSR:
ConditionExecute(il, instr.cond, SetRegisterOrBranch(il, op1.reg,
il.LogicalShiftRight(get_register_size(op2.reg),
ReadRegisterOrPointer(il, op2, addr),
ReadILOperand(il, op3, addr), flagOperation[instr.setsFlags])));
break;
case ARMV7_MCR:
case ARMV7_MCR2:
ConditionExecute(il, instr.cond,
il.Intrinsic({ }, ARMV7_INTRIN_COPROC_SENDONEWORD,
{
il.Register(4, op3.reg),
il.Const(1, op1.reg),
il.Const(1, op2.imm),
il.Const(1, op4.reg),
il.Const(1, op5.reg),
il.Const(1, op6.imm),
}
)
);
break;
case ARMV7_MCRR:
case ARMV7_MCRR2:
ConditionExecute(il, instr.cond,
il.Intrinsic({ }, ARMV7_INTRIN_COPROC_SENDTWOWORDS,
{