Makefrag-verilog

#--------------------------------------------------------------------
# Verilog Generation
#--------------------------------------------------------------------

FIRRTL_JAR := $(base_dir)/firrtl.jar
$(FIRRTL_JAR): $(shell find $(base_dir)/src/main/scala -name '*.scala')
	$(MAKE) -C $(FIRRTL_DIR) SBT="$(SBT)" root_dir=$(base_dir) build-scala
	mkdir -p $(@D)
	cp -p $(FIRRTL_DIR)/utils/bin/firrtl.jar $@
	touch $@

jar: $(FIRRTL_JAR)

# Build .fir
$(FIRRTL_FILE): $(FIRRTL_JAR)
	mkdir -p $(dir $@)
	cd $(base_dir) && \
	$(SBT) "runMain $(GENERATOR) -td $(build_dir) -T $(PROJECT).$(MODEL) -C $(PROJECT).$(CONFIG)"

fir: $(FIRRTL_FILE)

# Build .v
FIRRTL_TRANSFORMS := \
	firrtl.passes.InlineInstances \

FIRRTL := $(JAVA) $(JAVA_ARGS) -cp $(FIRRTL_JAR) firrtl.stage.FirrtlMain
$(VLOG_FILE) $(MEM_CONF): $(FIRRTL_FILE)
	mkdir -p $(dir $@)
	$(FIRRTL) -i $< \
    -o $(VLOG_FILE) \
    -X verilog \
    --infer-rw $(MODEL) \
    --repl-seq-mem -c:$(MODEL):-o:$(MEM_CONF) \
    -td $(build_dir) \
    -fct $(subst $(SPACE),$(COMMA),$(FIRRTL_TRANSFORMS)) \

# Build SRAM
$(SRAM_FILE): $(MEM_CONF) $(VLSI_MEM_GEN)
	cd $(build_dir) && \
	rm -f $@ && \
	$(VLSI_MEM_GEN) $(MEM_CONF) >> $@.tmp && \
	mv $@.tmp $@

# Build ROM
$(BOOTROM_VLOG): $(VLOG_FILE)
	$(MAKE) -C $(BOOTROM_DIR) romvlog

.PHONY: verilog
verilog: $(VLOG_FILE) $(SRAM_FILE) $(BOOTROM_VLOG)