diff --git a/crlcore/src/ccore/verilog/VerilogDriver.cpp b/crlcore/src/ccore/verilog/VerilogDriver.cpp
index a5853db4e..fcef17619 100644
--- a/crlcore/src/ccore/verilog/VerilogDriver.cpp
+++ b/crlcore/src/ccore/verilog/VerilogDriver.cpp
@@ -243,15 +243,10 @@ namespace CRL {
       {
         out << "  inout ";
       }
-      else if (dir == Net::Direction::OUT)
+      else // if direction undefined assume it is output
       {
         out << "  output ";
       }
-      else
-      {
-        std::cerr << "Undetermined direction " << dir << " for the net \"" << name << "\"" << std::endl;
-        assert(false);
-      }
       if (idx_min >= 0)
       {
         out << "[" << idx_max << ":" << idx_min << "] ";