Don't know how to widen the operands for INSERT_SUBVECTOR during RISCV codegen

[steven-johnson]

Stack dump:
0.	Program arguments: /Users/srj/llvm-20-install/bin/llc /tmp/foo.ll
1.	Running pass 'Function Pass Manager' on module '/tmp/foo.ll'.
2.	Running pass 'RISC-V DAG->DAG Pattern Instruction Selection' on function '@output'
 #0 0x000000011030e298 llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/Users/srj/llvm-20-install/bin/llc+0x102636298)
 #1 0x000000011030c178 llvm::sys::RunSignalHandlers() (/Users/srj/llvm-20-install/bin/llc+0x102634178)
 #2 0x000000011030e90e SignalHandler(int) (/Users/srj/llvm-20-install/bin/llc+0x10263690e)
 #3 0x00007ff802ed9fdd (/usr/lib/system/libsystem_platform.dylib+0x7ff80046afdd)
 #4 0x00007fe998700000
 #5 0x00007ff802dd0a79 (/usr/lib/system/libsystem_c.dylib+0x7ff800361a79)
 #6 0x000000011026d733 llvm::report_fatal_error(llvm::Twine const&, bool) (/Users/srj/llvm-20-install/bin/llc+0x102595733)
 #7 0x000000011026d579 llvm::report_fatal_error(char const*, bool) (/Users/srj/llvm-20-install/bin/llc+0x102595579)
 #8 0x000000011009a08d llvm::DAGTypeLegalizer::WidenVecOp_INSERT_SUBVECTOR(llvm::SDNode*) (/Users/srj/llvm-20-install/bin/llc+0x1023c208d)
 #9 0x00000001100987eb llvm::DAGTypeLegalizer::WidenVectorOperand(llvm::SDNode*, unsigned int) (/Users/srj/llvm-20-install/bin/llc+0x1023c07eb)
#10 0x0000000110043787 llvm::DAGTypeLegalizer::run() (/Users/srj/llvm-20-install/bin/llc+0x10236b787)
#11 0x000000011004909e llvm::SelectionDAG::LegalizeTypes() (/Users/srj/llvm-20-install/bin/llc+0x10237109e)
#12 0x0000000110192474 llvm::SelectionDAGISel::CodeGenAndEmitDAG() (/Users/srj/llvm-20-install/bin/llc+0x1024ba474)
#13 0x0000000110191526 llvm::SelectionDAGISel::SelectAllBasicBlocks(llvm::Function const&) (/Users/srj/llvm-20-install/bin/llc+0x1024b9526)
#14 0x000000011018e5a6 llvm::SelectionDAGISel::runOnMachineFunction(llvm::MachineFunction&) (/Users/srj/llvm-20-install/bin/llc+0x1024b65a6)
#15 0x000000011018c826 llvm::SelectionDAGISelLegacy::runOnMachineFunction(llvm::MachineFunction&) (/Users/srj/llvm-20-install/bin/llc+0x1024b4826)
#16 0x000000010f48565e llvm::MachineFunctionPass::runOnFunction(llvm::Function&) (/Users/srj/llvm-20-install/bin/llc+0x1017ad65e)
#17 0x000000010f9a8d30 llvm::FPPassManager::runOnFunction(llvm::Function&) (/Users/srj/llvm-20-install/bin/llc+0x101cd0d30)
#18 0x000000010f9b1034 llvm::FPPassManager::runOnModule(llvm::Module&) (/Users/srj/llvm-20-install/bin/llc+0x101cd9034)
#19 0x000000010f9a9788 llvm::legacy::PassManagerImpl::run(llvm::Module&) (/Users/srj/llvm-20-install/bin/llc+0x101cd1788)
#20 0x000000010dcdce14 main (/Users/srj/llvm-20-install/bin/llc+0x100004e14)
#21 0x00007ff802b1f345
Abort trap: 6

foo.ll.zip

[llvmbot]

@llvm/issue-subscribers-backend-risc-v

Author: Steven Johnson (steven-johnson)

``` Stack dump: 0. Program arguments: /Users/srj/llvm-20-install/bin/llc /tmp/foo.ll 1. Running pass 'Function Pass Manager' on module '/tmp/foo.ll'. 2. Running pass 'RISC-V DAG->DAG Pattern Instruction Selection' on function '@output' #0 0x000000011030e298 llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) (/Users/srj/llvm-20-install/bin/llc+0x102636298) #1 0x000000011030c178 llvm::sys::RunSignalHandlers() (/Users/srj/llvm-20-install/bin/llc+0x102634178) #2 0x000000011030e90e SignalHandler(int) (/Users/srj/llvm-20-install/bin/llc+0x10263690e) #3 0x00007ff802ed9fdd (/usr/lib/system/libsystem_platform.dylib+0x7ff80046afdd) #4 0x00007fe998700000 #5 0x00007ff802dd0a79 (/usr/lib/system/libsystem_c.dylib+0x7ff800361a79) #6 0x000000011026d733 llvm::report_fatal_error(llvm::Twine const&, bool) (/Users/srj/llvm-20-install/bin/llc+0x102595733) #7 0x000000011026d579 llvm::report_fatal_error(char const*, bool) (/Users/srj/llvm-20-install/bin/llc+0x102595579) #8 0x000000011009a08d llvm::DAGTypeLegalizer::WidenVecOp_INSERT_SUBVECTOR(llvm::SDNode*) (/Users/srj/llvm-20-install/bin/llc+0x1023c208d) #9 0x00000001100987eb llvm::DAGTypeLegalizer::WidenVectorOperand(llvm::SDNode*, unsigned int) (/Users/srj/llvm-20-install/bin/llc+0x1023c07eb) #10 0x0000000110043787 llvm::DAGTypeLegalizer::run() (/Users/srj/llvm-20-install/bin/llc+0x10236b787) #11 0x000000011004909e llvm::SelectionDAG::LegalizeTypes() (/Users/srj/llvm-20-install/bin/llc+0x10237109e) #12 0x0000000110192474 llvm::SelectionDAGISel::CodeGenAndEmitDAG() (/Users/srj/llvm-20-install/bin/llc+0x1024ba474) #13 0x0000000110191526 llvm::SelectionDAGISel::SelectAllBasicBlocks(llvm::Function const&) (/Users/srj/llvm-20-install/bin/llc+0x1024b9526) #14 0x000000011018e5a6 llvm::SelectionDAGISel::runOnMachineFunction(llvm::MachineFunction&) (/Users/srj/llvm-20-install/bin/llc+0x1024b65a6) #15 0x000000011018c826 llvm::SelectionDAGISelLegacy::runOnMachineFunction(llvm::MachineFunction&) (/Users/srj/llvm-20-install/bin/llc+0x1024b4826) #16 0x000000010f48565e llvm::MachineFunctionPass::runOnFunction(llvm::Function&) (/Users/srj/llvm-20-install/bin/llc+0x1017ad65e) #17 0x000000010f9a8d30 llvm::FPPassManager::runOnFunction(llvm::Function&) (/Users/srj/llvm-20-install/bin/llc+0x101cd0d30) #18 0x000000010f9b1034 llvm::FPPassManager::runOnModule(llvm::Module&) (/Users/srj/llvm-20-install/bin/llc+0x101cd9034) #19 0x000000010f9a9788 llvm::legacy::PassManagerImpl::run(llvm::Module&) (/Users/srj/llvm-20-install/bin/llc+0x101cd1788) #20 0x000000010dcdce14 main (/Users/srj/llvm-20-install/bin/llc+0x100004e14) #21 0x00007ff802b1f345 Abort trap: 6 ```

foo.ll.zip

[lukel97]

Looks like it's trying to widen some <vscale x 24 x i8> instructions, I'm not sure if we have much testing for these in-between-LMUL types.

[steven-johnson]

Is it legal IR? If so, well, now you have testing for it :-)

[lukel97]

It's legal, I was able to minimize it to this:

define <vscale x 24 x i8> @f(<48 x i8> %23, <48 x i8> %26) {
  %a = shufflevector <48 x i8> %23, <48 x i8> %26, <48 x i32> <i32 0, i32 1, i32 48, i32 3, i32 4, i32 49, i32 6, i32 7, i32 50, i32 9, i32 10, i32 51, i32 12, i32 13, i32 52, i32 15, i32 16, i32 53, i32 18, i32 19, i32 54, i32 21, i32 22, i32 55, i32 24, i32 25, i32 56, i32 27, i32 28, i32 57, i32 30, i32 31, i32 58, i32 33, i32 34, i32 59, i32 36, i32 37, i32 60, i32 39, i32 40, i32 61, i32 42, i32 43, i32 62, i32 45, i32 46, i32 63>
  %b = tail call <vscale x 24 x i8> @llvm.vector.insert.nxv24i8.v48i8(<vscale x 24 x i8> undef, <48 x i8> %a, i64 0)
  ret <vscale x 24 x i8> %b
}

EDIT: This isn't well formed because there's no vscale_range attribute, and we don't know if we can widen a <vscale x 24 x i8> to fit <48 x i8>

[topperc]

There's an attempt at a vscale_range attribute in the IR, but its malformed. It's a string attribute "vscale_range"="2, 2" instead of the correct vscale_range(2, 2)

[steven-johnson]

This is IR that is generated by top-of-tree LLVM, so if it's malformed, we should fix the LLVM codegen.

[topperc]

This is IR that is generated by top-of-tree LLVM, so if it's malformed, we should fix the LLVM codegen.

That attribute was created by Halide https://github.com/halide/Halide/blob/9ba1829297bba557f25fb422518252144ccfa225/src/CodeGen_Internal.cpp#L726

Equivalent code in clang looks like

  // Add vscale_range attribute if appropriate.
  std::optional<std::pair<unsigned, unsigned>> VScaleRange =
      getContext().getTargetInfo().getVScaleRange(getLangOpts());
  if (VScaleRange) {
    CurFn->addFnAttr(llvm::Attribute::getWithVScaleRangeArgs(
        getLLVMContext(), VScaleRange->first, VScaleRange->second));
  }

[steven-johnson]

Whoops! I stand corrected. I'll get that fixed.

EDIT: See halide/Halide#8457

[lukel97]

Posted #115110 to fix this, with the vscale attribute fixed in foo.ll I was able to get the attached test file compiling

[lukel97]

I got myself confused, the test case I included in #115110 was different from what was in foo.ll and we don't actually need it. I think fixing vscale_range should be enough