diff --git a/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp index 6be38f425a..47fc6a13d1 100644 --- a/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp +++ b/openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp @@ -105,6 +105,7 @@ void print_verilog_top_random_testbench_benchmark_instance(std::fstream& fp, const std::string& reference_verilog_top_name, const AtomContext& atom_ctx, const VprNetlistAnnotation& netlist_annotation, + const PinConstraints& pin_constraints, const bool& explicit_port_mapping) { /* Validate the file stream */ valid_file_stream(fp); @@ -125,6 +126,7 @@ void print_verilog_top_random_testbench_benchmark_instance(std::fstream& fp, prefix_to_remove, std::string(BENCHMARK_PORT_POSTFIX), atom_ctx, netlist_annotation, + pin_constraints, explicit_port_mapping); print_verilog_comment(fp, std::string("----- End reference Benchmark Instanication -------")); @@ -155,6 +157,7 @@ void print_verilog_random_testbench_fpga_instance(std::fstream& fp, std::vector(), std::string(FPGA_PORT_POSTFIX), atom_ctx, netlist_annotation, + PinConstraints(), explicit_port_mapping); print_verilog_comment(fp, std::string("----- End FPGA Fabric Instanication -------")); @@ -213,10 +216,6 @@ void print_verilog_random_testbench_reset_stimuli(std::fstream& fp, if (1 == global_ports.global_port_default_value(find_fabric_global_port(global_ports, module_manager, pin_constraints.net_pin(block_name)))) { initial_value = 0; } - /* Pin constraints has the final decision on the default value */ - if (pin_constraints.valid_net_default_value(block_name)) { - initial_value = pin_constraints.net_default_value_to_int(block_name); - } fp << "initial" << std::endl; fp << "\tbegin" << std::endl; @@ -308,6 +307,7 @@ void print_verilog_random_top_testbench(const std::string& circuit_name, if (!options.no_self_checking()) { print_verilog_top_random_testbench_benchmark_instance(fp, circuit_name, atom_ctx, netlist_annotation, + pin_constraints, options.explicit_port_mapping()); } diff --git a/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp b/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp index bd530cc3e7..3542cdcfc8 100644 --- a/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp +++ b/openfpga/src/fpga_verilog/verilog_testbench_utils.cpp @@ -69,6 +69,7 @@ void print_verilog_testbench_benchmark_instance(std::fstream& fp, const std::string& output_port_postfix, const AtomContext& atom_ctx, const VprNetlistAnnotation& netlist_annotation, + const PinConstraints& pin_constraints, const bool& use_explicit_port_map) { /* Validate the file stream */ valid_file_stream(fp); @@ -99,6 +100,15 @@ void print_verilog_testbench_benchmark_instance(std::fstream& fp, if (true == use_explicit_port_map) { fp << "." << block_name << module_input_port_postfix << "("; } + + /* Polarity of some input may have to be inverted, as defined in pin constraints + * For example, the reset signal of the benchmark is active low + * while the reset signal of the FPGA fabric is active high (inside FPGA, the reset signal will be inverted) + * However, to ensure correct stimuli to the benchmark, we have to invert the signal + */ + if (PinConstraints::LOGIC_HIGH == pin_constraints.net_default_value(block_name)) { + fp << "~"; + } fp << block_name; if (true == use_explicit_port_map) { fp << ")"; diff --git a/openfpga/src/fpga_verilog/verilog_testbench_utils.h b/openfpga/src/fpga_verilog/verilog_testbench_utils.h index f45452c6d1..d06f267c90 100644 --- a/openfpga/src/fpga_verilog/verilog_testbench_utils.h +++ b/openfpga/src/fpga_verilog/verilog_testbench_utils.h @@ -38,6 +38,7 @@ void print_verilog_testbench_benchmark_instance(std::fstream& fp, const std::string& output_port_postfix, const AtomContext& atom_ctx, const VprNetlistAnnotation& netlist_annotation, + const PinConstraints& pin_constraints, const bool& use_explicit_port_map); void print_verilog_testbench_connect_fpga_ios(std::fstream& fp, diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp index 1e82b7e818..e4778c2921 100644 --- a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp +++ b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp @@ -912,6 +912,7 @@ void print_verilog_top_testbench_benchmark_instance(std::fstream& fp, const std::string& reference_verilog_top_name, const AtomContext& atom_ctx, const VprNetlistAnnotation& netlist_annotation, + const PinConstraints& pin_constraints, const bool& explicit_port_mapping) { /* Validate the file stream */ valid_file_stream(fp); @@ -932,6 +933,7 @@ void print_verilog_top_testbench_benchmark_instance(std::fstream& fp, prefix_to_remove, std::string(TOP_TESTBENCH_REFERENCE_OUTPUT_POSTFIX), atom_ctx, netlist_annotation, + pin_constraints, explicit_port_mapping); print_verilog_comment(fp, std::string("----- End reference Benchmark Instanication -------")); @@ -1789,11 +1791,7 @@ void print_verilog_top_testbench_reset_stimuli(std::fstream& fp, continue; } - /* Pin constraints has the final decision on the default value */ size_t initial_value = global_ports.global_port_default_value(find_fabric_global_port(global_ports, module_manager, pin_constraints.net_pin(block_name))); - if (pin_constraints.valid_net_default_value(block_name)) { - initial_value = pin_constraints.net_default_value_to_int(block_name); - } /* Connect stimuli to greset with an optional inversion, depending on the default value */ BasicPort reset_port(block_name, 1); @@ -2004,6 +2002,7 @@ int print_verilog_full_testbench(const ModuleManager& module_manager, circuit_name, atom_ctx, netlist_annotation, + pin_constraints, explicit_port_mapping); } diff --git a/openfpga_flow/benchmarks/micro_benchmark/counter4bit_2clock/counter4bit_2clock.act b/openfpga_flow/benchmarks/micro_benchmark/counter4bit_2clock/counter4bit_2clock.act deleted file mode 100644 index e0e56d4492..0000000000 --- a/openfpga_flow/benchmarks/micro_benchmark/counter4bit_2clock/counter4bit_2clock.act +++ /dev/null @@ -1,22 +0,0 @@ -clk0 0.505000 0.204400 -rst0 0.491000 0.206000 -clk1 0.472000 0.204400 -rst1 0.501400 0.204600 -q1[0] 0.278800 0.557400 -q1[1] 0.240600 0.268800 -q1[2] 0.178200 0.120000 -q1[3] 0.098400 0.041600 -q0[0] 0.283400 0.566600 -q0[1] 0.246800 0.272000 -q0[2] 0.181000 0.122200 -q0[3] 0.093200 0.048800 -n34 0.178200 0.068356 -n38 0.098400 0.002698 -$abc$226$new_n22_ 0.880800 0.004943 -n42 0.283400 0.129291 -n46 0.246800 0.084119 -n50 0.181000 0.067113 -n54 0.093200 0.002644 -$abc$226$new_n27_ 0.883200 0.005398 -n26 0.278800 0.038636 -n30 0.240600 0.082416 diff --git a/openfpga_flow/benchmarks/micro_benchmark/counter4bit_2clock/counter4bit_2clock.blif b/openfpga_flow/benchmarks/micro_benchmark/counter4bit_2clock/counter4bit_2clock.blif deleted file mode 100644 index 0ae3c95a7c..0000000000 --- a/openfpga_flow/benchmarks/micro_benchmark/counter4bit_2clock/counter4bit_2clock.blif +++ /dev/null @@ -1,48 +0,0 @@ -# Benchmark "counter4bit_2clock" written by ABC on Wed Jan 13 13:27:00 2021 -.model counter4bit_2clock -.inputs clk0 rst0 clk1 rst1 -.outputs q0[0] q0[1] q0[2] q0[3] q1[0] q1[1] \ -q1[2] q1[3] - -.latch n26 q1[0] re clk1 2 -.latch n30 q1[1] re clk1 2 -.latch n34 q1[2] re clk1 2 -.latch n38 q1[3] re clk1 2 -.latch n42 q0[0] re clk0 2 -.latch n46 q0[1] re clk0 2 -.latch n50 q0[2] re clk0 2 -.latch n54 q0[3] re clk0 2 - -.names q1[0] q1[1] rst1 q1[2] n34 --001 1 -0-01 1 -1100 1 -.names rst1 $abc$226$new_n22_ n38 -00 1 -.names q1[2] q1[0] q1[1] q1[3] $abc$226$new_n22_ ---00 1 --0-0 1 -0--0 1 -1111 1 -.names rst0 q0[0] n42 -00 1 -.names rst0 q0[1] q0[0] n46 -001 1 -010 1 -.names q0[1] q0[0] rst0 q0[2] n50 --001 1 -0-01 1 -1100 1 -.names rst0 $abc$226$new_n27_ n54 -00 1 -.names q0[2] q0[1] q0[0] q0[3] $abc$226$new_n27_ ---00 1 --0-0 1 -0--0 1 -1111 1 -.names q1[0] rst1 n26 -00 1 -.names rst1 q1[0] q1[1] n30 -001 1 -010 1 -.end diff --git a/openfpga_flow/benchmarks/micro_benchmark/counter4bit_2clock/counter4bit_2clock_post_yosys.v b/openfpga_flow/benchmarks/micro_benchmark/counter4bit_2clock/counter4bit_2clock_post_yosys.v deleted file mode 100644 index 2b14fc5400..0000000000 --- a/openfpga_flow/benchmarks/micro_benchmark/counter4bit_2clock/counter4bit_2clock_post_yosys.v +++ /dev/null @@ -1,60 +0,0 @@ -/* Generated by Yosys 0.9+2406 (git sha1 a0606e09, gcc 8.4.0 -fPIC -Os) */ - -module counter4bit_2clock(clk0, rst0, clk1, rst1, \q0[0] , \q0[1] , \q0[2] , \q0[3] , \q1[0] , \q1[1] , \q1[2] , \q1[3] ); - wire _00_; - wire _01_; - input clk0; - input clk1; - wire n26; - wire n30; - wire n34; - wire n38; - wire n42; - wire n46; - wire n50; - wire n54; - output \q0[0] ; - reg \q0[0] ; - output \q0[1] ; - reg \q0[1] ; - output \q0[2] ; - reg \q0[2] ; - output \q0[3] ; - reg \q0[3] ; - output \q1[0] ; - reg \q1[0] ; - output \q1[1] ; - reg \q1[1] ; - output \q1[2] ; - reg \q1[2] ; - output \q1[3] ; - reg \q1[3] ; - input rst0; - input rst1; - always @(posedge clk1) - \q1[0] <= n26; - always @(posedge clk1) - \q1[1] <= n30; - always @(posedge clk1) - \q1[2] <= n34; - always @(posedge clk1) - \q1[3] <= n38; - always @(posedge clk1) - \q0[0] <= n42; - always @(posedge clk1) - \q0[1] <= n46; - always @(posedge clk1) - \q0[2] <= n50; - always @(posedge clk1) - \q0[3] <= n54; - assign n38 = 4'h1 >> { _00_, rst1 }; - assign _00_ = 16'h807f >> { \q1[3] , \q1[1] , \q1[0] , \q1[2] }; - assign n42 = 4'h1 >> { \q0[0] , rst0 }; - assign n46 = 8'h14 >> { \q0[0] , \q0[1] , rst0 }; - assign n50 = 16'h0708 >> { \q0[2] , rst0, \q0[0] , \q0[1] }; - assign n54 = 4'h1 >> { _01_, rst0 }; - assign _01_ = 16'h807f >> { \q0[3] , \q0[0] , \q0[1] , \q0[2] }; - assign n26 = 4'h1 >> { rst1, \q1[0] }; - assign n30 = 8'h14 >> { \q1[1] , \q1[0] , rst1 }; - assign n34 = 16'h0708 >> { \q1[2] , rst1, \q1[1] , \q1[0] }; -endmodule diff --git a/openfpga_flow/benchmarks/micro_benchmark/counter_128bit_async_reset/counter.v b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_128bit_async_reset/counter.v similarity index 100% rename from openfpga_flow/benchmarks/micro_benchmark/counter_128bit_async_reset/counter.v rename to openfpga_flow/benchmarks/micro_benchmark/counters/counter_128bit_async_reset/counter.v diff --git a/openfpga_flow/benchmarks/micro_benchmark/counter_128bit_async_reset/counter_tb.v b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_128bit_async_reset/counter_tb.v similarity index 100% rename from openfpga_flow/benchmarks/micro_benchmark/counter_128bit_async_reset/counter_tb.v rename to openfpga_flow/benchmarks/micro_benchmark/counters/counter_128bit_async_reset/counter_tb.v diff --git a/openfpga_flow/benchmarks/micro_benchmark/counter_128bit_async_resetb/counter.v b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_128bit_async_resetb/counter.v similarity index 100% rename from openfpga_flow/benchmarks/micro_benchmark/counter_128bit_async_resetb/counter.v rename to openfpga_flow/benchmarks/micro_benchmark/counters/counter_128bit_async_resetb/counter.v diff --git a/openfpga_flow/benchmarks/micro_benchmark/counter_128bit_async_resetb/counter_tb.v b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_128bit_async_resetb/counter_tb.v similarity index 100% rename from openfpga_flow/benchmarks/micro_benchmark/counter_128bit_async_resetb/counter_tb.v rename to openfpga_flow/benchmarks/micro_benchmark/counters/counter_128bit_async_resetb/counter_tb.v diff --git a/openfpga_flow/benchmarks/micro_benchmark/counter4bit_2clock/counter4bit_2clock.v b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter_4bit_2clock.v similarity index 85% rename from openfpga_flow/benchmarks/micro_benchmark/counter4bit_2clock/counter4bit_2clock.v rename to openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter_4bit_2clock.v index 93f7dc07bf..c1b5f2ee62 100644 --- a/openfpga_flow/benchmarks/micro_benchmark/counter4bit_2clock/counter4bit_2clock.v +++ b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter_4bit_2clock.v @@ -1,4 +1,4 @@ -module counter4bit_2clock(clk0, rst0, clk1, rst1, q0, q1); +module counter_4bit_2clock(clk0, rst0, clk1, rst1, q0, q1); input clk0; input rst0; diff --git a/openfpga_flow/benchmarks/micro_benchmark/counter4bit_2clock/counter4bit_2clock_tb.v b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter_4bit_2clock_tb.v similarity index 75% rename from openfpga_flow/benchmarks/micro_benchmark/counter4bit_2clock/counter4bit_2clock_tb.v rename to openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter_4bit_2clock_tb.v index 880b990887..9150f55b99 100644 --- a/openfpga_flow/benchmarks/micro_benchmark/counter4bit_2clock/counter4bit_2clock_tb.v +++ b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter_4bit_2clock_tb.v @@ -1,4 +1,4 @@ -module counter4bit_2clock_tb; +module counter_4bit_2clock_tb; reg clk0, rst0; wire [3:0] q0; @@ -6,12 +6,12 @@ module counter4bit_2clock_tb; reg clk1, rst1; wire [3:0] q1; - counter_2clock C_1( + counter_4bit_2clock C_1( clk0, q0, rst0); - counter_2clock C_1( + counter_4bit_2clock C_1( clk1, q1, rst1); diff --git a/openfpga_flow/benchmarks/micro_benchmark/counter_async_reset/counter.v b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_reset/counter.v similarity index 100% rename from openfpga_flow/benchmarks/micro_benchmark/counter_async_reset/counter.v rename to openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_reset/counter.v diff --git a/openfpga_flow/benchmarks/micro_benchmark/counter_async_reset/counter_tb.v b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_reset/counter_tb.v similarity index 100% rename from openfpga_flow/benchmarks/micro_benchmark/counter_async_reset/counter_tb.v rename to openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_reset/counter_tb.v diff --git a/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_resetb/counter.v b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_resetb/counter.v new file mode 100644 index 0000000000..3d929091d5 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_resetb/counter.v @@ -0,0 +1,25 @@ +/////////////////////////////////////////// +// Functionality: Counter with asynchronous reset +// Author: Xifan Tang +//////////////////////////////////////// + +module counter ( + clk, + resetb, + result +); + + input clk; + input resetb; + output [7:0] result; + + reg [7:0] result; + + always @(posedge clk or negedge resetb) + begin + if (!resetb) + result = 0; + else + result = result + 1; + end +endmodule diff --git a/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_resetb/counter_tb.v b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_resetb/counter_tb.v new file mode 100644 index 0000000000..8813aa0c4f --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_resetb/counter_tb.v @@ -0,0 +1,25 @@ +module counter_tb; + + reg clk, resetb; + wire [7:0] result; + + counter DUT( + .clk(clk), + .resetb(resetb), + .result(result) + ); + + initial begin + #0 resetb = 1'b0; clk = 1'b0; + #100 resetb = 1'b1; + end + + always begin + #10 clk = ~clk; + end + + initial begin + #5000 $stop; + end + +endmodule diff --git a/openfpga_flow/benchmarks/micro_benchmark/counter/counter.v b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_sync_reset/counter.v similarity index 100% rename from openfpga_flow/benchmarks/micro_benchmark/counter/counter.v rename to openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_sync_reset/counter.v diff --git a/openfpga_flow/benchmarks/micro_benchmark/counter/counter_tb.v b/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_sync_reset/counter_tb.v similarity index 100% rename from openfpga_flow/benchmarks/micro_benchmark/counter/counter_tb.v rename to openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_sync_reset/counter_tb.v diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_cc_openfpga.xml index 5aca72a879..cd12856c52 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_cc_openfpga.xml @@ -139,15 +139,15 @@ - + - + @@ -220,20 +220,34 @@ - + - + + + + + + + + - + + + + + + + + diff --git a/openfpga_flow/openfpga_cell_library/verilog/dff.v b/openfpga_flow/openfpga_cell_library/verilog/dff.v index c3a5e538e5..2eb5765c93 100644 --- a/openfpga_flow/openfpga_cell_library/verilog/dff.v +++ b/openfpga_flow/openfpga_cell_library/verilog/dff.v @@ -246,9 +246,9 @@ endmodule //End Of Module //----------------------------------------------------- // Function : A multi-functional D-type flip-flop with // - asynchronous reset -// which can be switched between active-low and active hight -// - asynchronous set which can be switched -// which can be switched between active-low and active hight +// which can be switched between active-low and active high +// - asynchronous set +// which can be switched between active-low and active high //----------------------------------------------------- module MULTI_MODE_DFFSRQ ( input SET, // Set input @@ -259,8 +259,8 @@ module MULTI_MODE_DFFSRQ ( input [0:1] mode // mode-selection bits: bit0 for reset polarity; bit1 for set polarity ); -wire post_set = mode ? ~SET : SET; -wire post_reset = mode ? ~RST : RST; +wire post_set = mode[1] ? ~SET : SET; +wire post_reset = mode[0] ? ~RST : RST; DFFSRQ FF_CORE (.SET(post_set), .RST(post_rst), @@ -271,6 +271,29 @@ DFFSRQ FF_CORE (.SET(post_set), endmodule //End Of Module +//----------------------------------------------------- +// Function : A multi-functional D-type flip-flop with +// - asynchronous reset +// which can be switched between active-low and active high +//----------------------------------------------------- +module MULTI_MODE_DFFRQ ( + input RST, // Reset input + input CK, // Clock Input + input D, // Data Input + output Q, // Q output + input mode // mode-selection bits: bit0 for reset polarity; bit1 for set polarity +); + +wire post_reset = mode ? ~RST : RST; + +DFFRQ FF_CORE (.RST(post_rst), + .CK(CK), + .D(D), + .Q(Q) + ); + +endmodule //End Of Module + //----------------------------------------------------- // Function : D-type flip-flop with // - asynchronous active high reset diff --git a/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v b/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v index 707d9c0e65..8c6c149c42 100644 --- a/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v +++ b/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v @@ -17,6 +17,16 @@ module \$_DFF_PP0_ (D, C, R, Q); dffr _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .R(R)); endmodule +// Async active-low reset +module \$_DFF_PN0_ (D, C, R, Q); + input D; + input C; + input R; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + dffrn _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .RN(R)); +endmodule + // Async reset, enable module \$_DFFE_PP0P_ (D, C, E, R, Q); input D; diff --git a/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v b/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v index d4798a9066..12b9e8ec39 100644 --- a/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v +++ b/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v @@ -76,6 +76,37 @@ module dffre( endcase endmodule +//----------------------------- +// D-type flip-flop with active-low asynchronous reset +//----------------------------- +(* abc9_flop, lib_whitebox *) +module dffrn( + output reg Q, + input D, + input RN, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C or negedge RN) + if (RN == 1'b0) + Q <= 1'b0; + else + Q <= D; + 1'b1: + always @(negedge C or negedge RN) + if (RN == 1'b0) + Q <= 1'b0; + else + Q <= D; + endcase +endmodule + (* abc9_flop, lib_whitebox *) module latchre ( output reg Q, diff --git a/openfpga_flow/scripts/run_fpga_task.py b/openfpga_flow/scripts/run_fpga_task.py index 66ac0f838f..7665cfb1b0 100644 --- a/openfpga_flow/scripts/run_fpga_task.py +++ b/openfpga_flow/scripts/run_fpga_task.py @@ -271,9 +271,11 @@ def generate_each_task_actions(taskname): fallback=ys_rewrite_for_task_common) CurrBenchPara["chan_width"] = SynthSection.get(bech_name+"_chan_width", fallback=chan_width_common) + CurrBenchPara["benchVariable"] = [] for eachKey, eachValue in SynthSection.items(): - eachKey = eachKey.replace(bech_name+"_","").upper() - CurrBenchPara[eachKey] = eachValue + if bech_name in eachKey: + eachKey = eachKey.replace(bech_name+"_", "").upper() + CurrBenchPara["benchVariable"] += [f"--{eachKey}", eachValue] if GeneralSection.get("fpga_flow") == "vpr_blif": # Check if activity file exist @@ -335,7 +337,7 @@ def generate_each_task_actions(taskname): "bench": bench, "name": "%02d_%s_%s" % (indx, bench["top_module"], lbl), "run_dir": flow_run_dir, - "commands": command, + "commands": command + bench["benchVariable"], "finished": False, "status": False}) @@ -346,6 +348,8 @@ def generate_each_task_actions(taskname): # Make the directory name unique by including the benchmark index in the list. # This is because benchmarks may share the same top module names + + def get_flow_rundir(arch, top_module, flow_params=None): path = [ os.path.basename(arch).replace(".xml", ""), diff --git a/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/task.conf b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/task.conf index e7cbcb5ab4..feb6dfbaa9 100644 --- a/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/task.conf @@ -20,18 +20,19 @@ openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scrip openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTile4Clk_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_4clock_sim_openfpga.xml openfpga_repack_design_constraints_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/repack_pin_constraints.xml -openfpga_pin_constraints_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/pin_constraints.xml [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTile4Clk_40nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter4bit_2clock/counter4bit_2clock.v +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_4bit_2clock/counter_4bit_2clock.v bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch_2clock/and2_latch_2clock.v [SYNTHESIS_PARAM] -bench0_top = counter4bit_2clock +bench0_top = counter_4bit_2clock +bench0_openfpga_pin_constraints_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/pin_constraints.xml bench1_top = and2_latch_2clock +bench1_openfpga_pin_constraints_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/pin_constraints.xml [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] end_flow_with_test= diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/pin_constraints.xml b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/pin_constraints_reset.xml similarity index 100% rename from openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/pin_constraints.xml rename to openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/pin_constraints_reset.xml diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/pin_constraints_resetb.xml b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/pin_constraints_resetb.xml new file mode 100644 index 0000000000..cdef2ad86a --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/pin_constraints_resetb.xml @@ -0,0 +1,7 @@ + + + + + diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/task.conf b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/task.conf index 07e326a1e9..2408323ed4 100644 --- a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/task.conf @@ -19,7 +19,6 @@ fpga_flow=yosys_vpr openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_without_ace_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml -openfpga_pin_constraints_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/pin_constraints.xml # Yosys script parameters yosys_cell_sim_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v yosys_dff_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v @@ -28,13 +27,18 @@ yosys_dff_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter_async_reset/counter.v +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_reset/counter.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_resetb/counter.v [SYNTHESIS_PARAM] bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys bench0_top = counter +bench0_openfpga_pin_constraints_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/pin_constraints_reset.xml + +bench1_top = counter +bench1_openfpga_pin_constraints_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/pin_constraints_resetb.xml [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] end_flow_with_test= diff --git a/openfpga_flow/tasks/benchmark_sweep/counter/config/task.conf b/openfpga_flow/tasks/benchmark_sweep/counter/config/task.conf index eb00795163..6fefdb16d8 100644 --- a/openfpga_flow/tasks/benchmark_sweep/counter/config/task.conf +++ b/openfpga_flow/tasks/benchmark_sweep/counter/config/task.conf @@ -34,10 +34,10 @@ vpr_route_chan_width=50 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram8K_dsp36_fracff_40nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter/counter.v -bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter_async_reset/counter.v -bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter_128bit_async_reset/counter.v -bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter_128bit_async_resetb/counter.v +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_sync_reset/counter.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_async_reset/counter.v +bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_128bit_async_reset/counter.v +bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_128bit_async_resetb/counter.v [SYNTHESIS_PARAM] bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_dff_flow.ys diff --git a/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/implicit_verilog/config/task.conf b/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/implicit_verilog/config/task.conf index f7f2a8b066..df4d8b8544 100644 --- a/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/implicit_verilog/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/implicit_verilog/config/task.conf @@ -25,7 +25,7 @@ openfpga_verilog_default_net_type=none arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter/counter.v +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_sync_reset/counter.v [SYNTHESIS_PARAM] bench0_top = counter diff --git a/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/implicit_verilog_default_nettype_wire/config/task.conf b/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/implicit_verilog_default_nettype_wire/config/task.conf index 898412cd22..568ded5e46 100644 --- a/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/implicit_verilog_default_nettype_wire/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/verilog_netlist_formats/implicit_verilog_default_nettype_wire/config/task.conf @@ -25,7 +25,7 @@ openfpga_verilog_default_net_type=wire arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counter/counter.v +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_8bit_sync_reset/counter.v [SYNTHESIS_PARAM] bench0_top = counter diff --git a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml index af701b3c9c..5351486bcf 100644 --- a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml +++ b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml @@ -7,11 +7,7 @@ with optionally registered outputs - Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1 - Details on Modelling: - - Based on flagship k4_frac_N4_mem32K_40nm.xml architecture. - - Authors: Jason Luu, Jeff Goeders, Vaughn Betz + Authors: Xifan Tang --> + + + + + + + + + + @@ -54,6 +60,17 @@ + + + + + + + + + + + - - + + - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -417,16 +493,75 @@ 261e-12 - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +