From 46935f9f23dccbfdb16e647aeeaa0cd41c01c043 Mon Sep 17 00:00:00 2001 From: Andrew Pond Date: Thu, 1 Jul 2021 17:12:54 -0600 Subject: [PATCH 01/22] started bram branch --- .../benchmarks/processor/picorv32/picorv32.v | 3044 ++++++ .../processor/vexriscv/vexriscv_large.v | 7460 ++++++++++++++ .../processor/vexriscv/vexriscv_linux.v | 8639 +++++++++++++++++ .../processor/vexriscv/vexriscv_small.v | 3127 ++++++ .../ys_tmpl_yosys_vpr_bram_dsp_dff_flow.ys | 5 + .../misc/ys_tmpl_yosys_vpr_bram_dsp_flow.ys | 5 + .../openfpga_yosys_techlib/dsp18_map.v | 17 + ...chain_dpram1K_dsp18_fracff_40nm_cell_sim.v | 220 + ..._chain_dpram1K_dsp18_fracff_40nm_dff_map.v | 48 + openfpga_flow/tasks/skywater_openfpga_task | 1 + 10 files changed, 22566 insertions(+) create mode 100644 openfpga_flow/benchmarks/processor/picorv32/picorv32.v create mode 100644 openfpga_flow/benchmarks/processor/vexriscv/vexriscv_large.v create mode 100644 openfpga_flow/benchmarks/processor/vexriscv/vexriscv_linux.v create mode 100644 openfpga_flow/benchmarks/processor/vexriscv/vexriscv_small.v create mode 100644 openfpga_flow/openfpga_yosys_techlib/dsp18_map.v create mode 100644 openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_40nm_cell_sim.v create mode 100644 openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_40nm_dff_map.v create mode 120000 openfpga_flow/tasks/skywater_openfpga_task diff --git a/openfpga_flow/benchmarks/processor/picorv32/picorv32.v b/openfpga_flow/benchmarks/processor/picorv32/picorv32.v new file mode 100644 index 0000000000..663352bddc --- /dev/null +++ b/openfpga_flow/benchmarks/processor/picorv32/picorv32.v @@ -0,0 +1,3044 @@ +/* + * PicoRV32 -- A Small RISC-V (RV32I) Processor Core + * + * Copyright (C) 2015 Clifford Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +/* verilator lint_off WIDTH */ +/* verilator lint_off PINMISSING */ +/* verilator lint_off CASEOVERLAP */ +/* verilator lint_off CASEINCOMPLETE */ + +`timescale 1 ns / 1 ps +// `default_nettype none +// `define DEBUGNETS +// `define DEBUGREGS +// `define DEBUGASM +// `define DEBUG + +`ifdef DEBUG + `define debug(debug_command) debug_command +`else + `define debug(debug_command) +`endif + +`ifdef FORMAL + `define FORMAL_KEEP (* keep *) + `define assert(assert_expr) assert(assert_expr) +`else + `ifdef DEBUGNETS + `define FORMAL_KEEP (* keep *) + `else + `define FORMAL_KEEP + `endif + `define assert(assert_expr) empty_statement +`endif + +// uncomment this for register file in extra module +// `define PICORV32_REGS picorv32_regs + +// this macro can be used to check if the verilog files in your +// design are read in the correct order. +`define PICORV32_V + + +/*************************************************************** + * picorv32 + ***************************************************************/ + +module picorv32 #( + parameter [ 0:0] ENABLE_COUNTERS = 1, + parameter [ 0:0] ENABLE_COUNTERS64 = 1, + parameter [ 0:0] ENABLE_REGS_16_31 = 1, + parameter [ 0:0] ENABLE_REGS_DUALPORT = 1, + parameter [ 0:0] LATCHED_MEM_RDATA = 0, + parameter [ 0:0] TWO_STAGE_SHIFT = 1, + parameter [ 0:0] BARREL_SHIFTER = 0, + parameter [ 0:0] TWO_CYCLE_COMPARE = 0, + parameter [ 0:0] TWO_CYCLE_ALU = 0, + parameter [ 0:0] COMPRESSED_ISA = 0, + parameter [ 0:0] CATCH_MISALIGN = 1, + parameter [ 0:0] CATCH_ILLINSN = 1, + parameter [ 0:0] ENABLE_PCPI = 0, + parameter [ 0:0] ENABLE_MUL = 0, + parameter [ 0:0] ENABLE_FAST_MUL = 0, + parameter [ 0:0] ENABLE_DIV = 0, + parameter [ 0:0] ENABLE_IRQ = 0, + parameter [ 0:0] ENABLE_IRQ_QREGS = 1, + parameter [ 0:0] ENABLE_IRQ_TIMER = 1, + parameter [ 0:0] ENABLE_TRACE = 0, + parameter [ 0:0] REGS_INIT_ZERO = 0, + parameter [31:0] MASKED_IRQ = 32'h 0000_0000, + parameter [31:0] LATCHED_IRQ = 32'h ffff_ffff, + parameter [31:0] PROGADDR_RESET = 32'h 0000_0000, + parameter [31:0] PROGADDR_IRQ = 32'h 0000_0010, + parameter [31:0] STACKADDR = 32'h ffff_ffff +) ( + input clk, resetn, + output reg trap, + + output reg mem_valid, + output reg mem_instr, + input mem_ready, + + output reg [31:0] mem_addr, + output reg [31:0] mem_wdata, + output reg [ 3:0] mem_wstrb, + input [31:0] mem_rdata, + + // Look-Ahead Interface + output mem_la_read, + output mem_la_write, + output [31:0] mem_la_addr, + output reg [31:0] mem_la_wdata, + output reg [ 3:0] mem_la_wstrb, + + // Pico Co-Processor Interface (PCPI) + output reg pcpi_valid, + output reg [31:0] pcpi_insn, + output [31:0] pcpi_rs1, + output [31:0] pcpi_rs2, + input pcpi_wr, + input [31:0] pcpi_rd, + input pcpi_wait, + input pcpi_ready, + + // IRQ Interface + input [31:0] irq, + output reg [31:0] eoi, + +`ifdef RISCV_FORMAL + output reg rvfi_valid, + output reg [63:0] rvfi_order, + output reg [31:0] rvfi_insn, + output reg rvfi_trap, + output reg rvfi_halt, + output reg rvfi_intr, + output reg [ 1:0] rvfi_mode, + output reg [ 1:0] rvfi_ixl, + output reg [ 4:0] rvfi_rs1_addr, + output reg [ 4:0] rvfi_rs2_addr, + output reg [31:0] rvfi_rs1_rdata, + output reg [31:0] rvfi_rs2_rdata, + output reg [ 4:0] rvfi_rd_addr, + output reg [31:0] rvfi_rd_wdata, + output reg [31:0] rvfi_pc_rdata, + output reg [31:0] rvfi_pc_wdata, + output reg [31:0] rvfi_mem_addr, + output reg [ 3:0] rvfi_mem_rmask, + output reg [ 3:0] rvfi_mem_wmask, + output reg [31:0] rvfi_mem_rdata, + output reg [31:0] rvfi_mem_wdata, + + output reg [63:0] rvfi_csr_mcycle_rmask, + output reg [63:0] rvfi_csr_mcycle_wmask, + output reg [63:0] rvfi_csr_mcycle_rdata, + output reg [63:0] rvfi_csr_mcycle_wdata, + + output reg [63:0] rvfi_csr_minstret_rmask, + output reg [63:0] rvfi_csr_minstret_wmask, + output reg [63:0] rvfi_csr_minstret_rdata, + output reg [63:0] rvfi_csr_minstret_wdata, +`endif + + // Trace Interface + output reg trace_valid, + output reg [35:0] trace_data +); + localparam integer irq_timer = 0; + localparam integer irq_ebreak = 1; + localparam integer irq_buserror = 2; + + localparam integer irqregs_offset = ENABLE_REGS_16_31 ? 32 : 16; + localparam integer regfile_size = (ENABLE_REGS_16_31 ? 32 : 16) + 4*ENABLE_IRQ*ENABLE_IRQ_QREGS; + localparam integer regindex_bits = (ENABLE_REGS_16_31 ? 5 : 4) + ENABLE_IRQ*ENABLE_IRQ_QREGS; + + localparam WITH_PCPI = ENABLE_PCPI || ENABLE_MUL || ENABLE_FAST_MUL || ENABLE_DIV; + + localparam [35:0] TRACE_BRANCH = {4'b 0001, 32'b 0}; + localparam [35:0] TRACE_ADDR = {4'b 0010, 32'b 0}; + localparam [35:0] TRACE_IRQ = {4'b 1000, 32'b 0}; + + reg [63:0] count_cycle, count_instr; + reg [31:0] reg_pc, reg_next_pc, reg_op1, reg_op2, reg_out; + reg [4:0] reg_sh; + + reg [31:0] next_insn_opcode; + reg [31:0] dbg_insn_opcode; + reg [31:0] dbg_insn_addr; + + wire dbg_mem_valid = mem_valid; + wire dbg_mem_instr = mem_instr; + wire dbg_mem_ready = mem_ready; + wire [31:0] dbg_mem_addr = mem_addr; + wire [31:0] dbg_mem_wdata = mem_wdata; + wire [ 3:0] dbg_mem_wstrb = mem_wstrb; + wire [31:0] dbg_mem_rdata = mem_rdata; + + assign pcpi_rs1 = reg_op1; + assign pcpi_rs2 = reg_op2; + + wire [31:0] next_pc; + + reg irq_delay; + reg irq_active; + reg [31:0] irq_mask; + reg [31:0] irq_pending; + reg [31:0] timer; + +`ifndef PICORV32_REGS + reg [31:0] cpuregs [0:regfile_size-1]; + + integer i; + initial begin + if (REGS_INIT_ZERO) begin + for (i = 0; i < regfile_size; i = i+1) + cpuregs[i] = 0; + end + end +`endif + + task empty_statement; + // This task is used by the `assert directive in non-formal mode to + // avoid empty statement (which are unsupported by plain Verilog syntax). + begin end + endtask + +`ifdef DEBUGREGS + wire [31:0] dbg_reg_x0 = 0; + wire [31:0] dbg_reg_x1 = cpuregs[1]; + wire [31:0] dbg_reg_x2 = cpuregs[2]; + wire [31:0] dbg_reg_x3 = cpuregs[3]; + wire [31:0] dbg_reg_x4 = cpuregs[4]; + wire [31:0] dbg_reg_x5 = cpuregs[5]; + wire [31:0] dbg_reg_x6 = cpuregs[6]; + wire [31:0] dbg_reg_x7 = cpuregs[7]; + wire [31:0] dbg_reg_x8 = cpuregs[8]; + wire [31:0] dbg_reg_x9 = cpuregs[9]; + wire [31:0] dbg_reg_x10 = cpuregs[10]; + wire [31:0] dbg_reg_x11 = cpuregs[11]; + wire [31:0] dbg_reg_x12 = cpuregs[12]; + wire [31:0] dbg_reg_x13 = cpuregs[13]; + wire [31:0] dbg_reg_x14 = cpuregs[14]; + wire [31:0] dbg_reg_x15 = cpuregs[15]; + wire [31:0] dbg_reg_x16 = cpuregs[16]; + wire [31:0] dbg_reg_x17 = cpuregs[17]; + wire [31:0] dbg_reg_x18 = cpuregs[18]; + wire [31:0] dbg_reg_x19 = cpuregs[19]; + wire [31:0] dbg_reg_x20 = cpuregs[20]; + wire [31:0] dbg_reg_x21 = cpuregs[21]; + wire [31:0] dbg_reg_x22 = cpuregs[22]; + wire [31:0] dbg_reg_x23 = cpuregs[23]; + wire [31:0] dbg_reg_x24 = cpuregs[24]; + wire [31:0] dbg_reg_x25 = cpuregs[25]; + wire [31:0] dbg_reg_x26 = cpuregs[26]; + wire [31:0] dbg_reg_x27 = cpuregs[27]; + wire [31:0] dbg_reg_x28 = cpuregs[28]; + wire [31:0] dbg_reg_x29 = cpuregs[29]; + wire [31:0] dbg_reg_x30 = cpuregs[30]; + wire [31:0] dbg_reg_x31 = cpuregs[31]; +`endif + + // Internal PCPI Cores + + wire pcpi_mul_wr; + wire [31:0] pcpi_mul_rd; + wire pcpi_mul_wait; + wire pcpi_mul_ready; + + wire pcpi_div_wr; + wire [31:0] pcpi_div_rd; + wire pcpi_div_wait; + wire pcpi_div_ready; + + reg pcpi_int_wr; + reg [31:0] pcpi_int_rd; + reg pcpi_int_wait; + reg pcpi_int_ready; + + generate if (ENABLE_FAST_MUL) begin + picorv32_pcpi_fast_mul pcpi_mul ( + .clk (clk ), + .resetn (resetn ), + .pcpi_valid(pcpi_valid ), + .pcpi_insn (pcpi_insn ), + .pcpi_rs1 (pcpi_rs1 ), + .pcpi_rs2 (pcpi_rs2 ), + .pcpi_wr (pcpi_mul_wr ), + .pcpi_rd (pcpi_mul_rd ), + .pcpi_wait (pcpi_mul_wait ), + .pcpi_ready(pcpi_mul_ready ) + ); + end else if (ENABLE_MUL) begin + picorv32_pcpi_mul pcpi_mul ( + .clk (clk ), + .resetn (resetn ), + .pcpi_valid(pcpi_valid ), + .pcpi_insn (pcpi_insn ), + .pcpi_rs1 (pcpi_rs1 ), + .pcpi_rs2 (pcpi_rs2 ), + .pcpi_wr (pcpi_mul_wr ), + .pcpi_rd (pcpi_mul_rd ), + .pcpi_wait (pcpi_mul_wait ), + .pcpi_ready(pcpi_mul_ready ) + ); + end else begin + assign pcpi_mul_wr = 0; + assign pcpi_mul_rd = 32'bx; + assign pcpi_mul_wait = 0; + assign pcpi_mul_ready = 0; + end endgenerate + + generate if (ENABLE_DIV) begin + picorv32_pcpi_div pcpi_div ( + .clk (clk ), + .resetn (resetn ), + .pcpi_valid(pcpi_valid ), + .pcpi_insn (pcpi_insn ), + .pcpi_rs1 (pcpi_rs1 ), + .pcpi_rs2 (pcpi_rs2 ), + .pcpi_wr (pcpi_div_wr ), + .pcpi_rd (pcpi_div_rd ), + .pcpi_wait (pcpi_div_wait ), + .pcpi_ready(pcpi_div_ready ) + ); + end else begin + assign pcpi_div_wr = 0; + assign pcpi_div_rd = 32'bx; + assign pcpi_div_wait = 0; + assign pcpi_div_ready = 0; + end endgenerate + + always @* begin + pcpi_int_wr = 0; + pcpi_int_rd = 32'bx; + pcpi_int_wait = |{ENABLE_PCPI && pcpi_wait, (ENABLE_MUL || ENABLE_FAST_MUL) && pcpi_mul_wait, ENABLE_DIV && pcpi_div_wait}; + pcpi_int_ready = |{ENABLE_PCPI && pcpi_ready, (ENABLE_MUL || ENABLE_FAST_MUL) && pcpi_mul_ready, ENABLE_DIV && pcpi_div_ready}; + + (* parallel_case *) + case (1'b1) + ENABLE_PCPI && pcpi_ready: begin + pcpi_int_wr = ENABLE_PCPI ? pcpi_wr : 0; + pcpi_int_rd = ENABLE_PCPI ? pcpi_rd : 0; + end + (ENABLE_MUL || ENABLE_FAST_MUL) && pcpi_mul_ready: begin + pcpi_int_wr = pcpi_mul_wr; + pcpi_int_rd = pcpi_mul_rd; + end + ENABLE_DIV && pcpi_div_ready: begin + pcpi_int_wr = pcpi_div_wr; + pcpi_int_rd = pcpi_div_rd; + end + endcase + end + + + // Memory Interface + + reg [1:0] mem_state; + reg [1:0] mem_wordsize; + reg [31:0] mem_rdata_word; + reg [31:0] mem_rdata_q; + reg mem_do_prefetch; + reg mem_do_rinst; + reg mem_do_rdata; + reg mem_do_wdata; + + wire mem_xfer; + reg mem_la_secondword, mem_la_firstword_reg, last_mem_valid; + wire mem_la_firstword = COMPRESSED_ISA && (mem_do_prefetch || mem_do_rinst) && next_pc[1] && !mem_la_secondword; + wire mem_la_firstword_xfer = COMPRESSED_ISA && mem_xfer && (!last_mem_valid ? mem_la_firstword : mem_la_firstword_reg); + + reg prefetched_high_word; + reg clear_prefetched_high_word; + reg [15:0] mem_16bit_buffer; + + wire [31:0] mem_rdata_latched_noshuffle; + wire [31:0] mem_rdata_latched; + + wire mem_la_use_prefetched_high_word = COMPRESSED_ISA && mem_la_firstword && prefetched_high_word && !clear_prefetched_high_word; + assign mem_xfer = (mem_valid && mem_ready) || (mem_la_use_prefetched_high_word && mem_do_rinst); + + wire mem_busy = |{mem_do_prefetch, mem_do_rinst, mem_do_rdata, mem_do_wdata}; + wire mem_done = resetn && ((mem_xfer && |mem_state && (mem_do_rinst || mem_do_rdata || mem_do_wdata)) || (&mem_state && mem_do_rinst)) && + (!mem_la_firstword || (~&mem_rdata_latched[1:0] && mem_xfer)); + + assign mem_la_write = resetn && !mem_state && mem_do_wdata; + assign mem_la_read = resetn && ((!mem_la_use_prefetched_high_word && !mem_state && (mem_do_rinst || mem_do_prefetch || mem_do_rdata)) || + (COMPRESSED_ISA && mem_xfer && (!last_mem_valid ? mem_la_firstword : mem_la_firstword_reg) && !mem_la_secondword && &mem_rdata_latched[1:0])); + assign mem_la_addr = (mem_do_prefetch || mem_do_rinst) ? {next_pc[31:2] + mem_la_firstword_xfer, 2'b00} : {reg_op1[31:2], 2'b00}; + + assign mem_rdata_latched_noshuffle = (mem_xfer || LATCHED_MEM_RDATA) ? mem_rdata : mem_rdata_q; + + assign mem_rdata_latched = COMPRESSED_ISA && mem_la_use_prefetched_high_word ? {16'bx, mem_16bit_buffer} : + COMPRESSED_ISA && mem_la_secondword ? {mem_rdata_latched_noshuffle[15:0], mem_16bit_buffer} : + COMPRESSED_ISA && mem_la_firstword ? {16'bx, mem_rdata_latched_noshuffle[31:16]} : mem_rdata_latched_noshuffle; + + always @(posedge clk) begin + if (!resetn) begin + mem_la_firstword_reg <= 0; + last_mem_valid <= 0; + end else begin + if (!last_mem_valid) + mem_la_firstword_reg <= mem_la_firstword; + last_mem_valid <= mem_valid && !mem_ready; + end + end + + always @* begin + (* full_case *) + case (mem_wordsize) + 0: begin + mem_la_wdata = reg_op2; + mem_la_wstrb = 4'b1111; + mem_rdata_word = mem_rdata; + end + 1: begin + mem_la_wdata = {2{reg_op2[15:0]}}; + mem_la_wstrb = reg_op1[1] ? 4'b1100 : 4'b0011; + case (reg_op1[1]) + 1'b0: mem_rdata_word = {16'b0, mem_rdata[15: 0]}; + 1'b1: mem_rdata_word = {16'b0, mem_rdata[31:16]}; + endcase + end + 2: begin + mem_la_wdata = {4{reg_op2[7:0]}}; + mem_la_wstrb = 4'b0001 << reg_op1[1:0]; + case (reg_op1[1:0]) + 2'b00: mem_rdata_word = {24'b0, mem_rdata[ 7: 0]}; + 2'b01: mem_rdata_word = {24'b0, mem_rdata[15: 8]}; + 2'b10: mem_rdata_word = {24'b0, mem_rdata[23:16]}; + 2'b11: mem_rdata_word = {24'b0, mem_rdata[31:24]}; + endcase + end + endcase + end + + always @(posedge clk) begin + if (mem_xfer) begin + mem_rdata_q <= COMPRESSED_ISA ? mem_rdata_latched : mem_rdata; + next_insn_opcode <= COMPRESSED_ISA ? mem_rdata_latched : mem_rdata; + end + + if (COMPRESSED_ISA && mem_done && (mem_do_prefetch || mem_do_rinst)) begin + case (mem_rdata_latched[1:0]) + 2'b00: begin // Quadrant 0 + case (mem_rdata_latched[15:13]) + 3'b000: begin // C.ADDI4SPN + mem_rdata_q[14:12] <= 3'b000; + mem_rdata_q[31:20] <= {2'b0, mem_rdata_latched[10:7], mem_rdata_latched[12:11], mem_rdata_latched[5], mem_rdata_latched[6], 2'b00}; + end + 3'b010: begin // C.LW + mem_rdata_q[31:20] <= {5'b0, mem_rdata_latched[5], mem_rdata_latched[12:10], mem_rdata_latched[6], 2'b00}; + mem_rdata_q[14:12] <= 3'b 010; + end + 3'b 110: begin // C.SW + {mem_rdata_q[31:25], mem_rdata_q[11:7]} <= {5'b0, mem_rdata_latched[5], mem_rdata_latched[12:10], mem_rdata_latched[6], 2'b00}; + mem_rdata_q[14:12] <= 3'b 010; + end + endcase + end + 2'b01: begin // Quadrant 1 + case (mem_rdata_latched[15:13]) + 3'b 000: begin // C.ADDI + mem_rdata_q[14:12] <= 3'b000; + mem_rdata_q[31:20] <= $signed({mem_rdata_latched[12], mem_rdata_latched[6:2]}); + end + 3'b 010: begin // C.LI + mem_rdata_q[14:12] <= 3'b000; + mem_rdata_q[31:20] <= $signed({mem_rdata_latched[12], mem_rdata_latched[6:2]}); + end + 3'b 011: begin + if (mem_rdata_latched[11:7] == 2) begin // C.ADDI16SP + mem_rdata_q[14:12] <= 3'b000; + mem_rdata_q[31:20] <= $signed({mem_rdata_latched[12], mem_rdata_latched[4:3], + mem_rdata_latched[5], mem_rdata_latched[2], mem_rdata_latched[6], 4'b 0000}); + end else begin // C.LUI + mem_rdata_q[31:12] <= $signed({mem_rdata_latched[12], mem_rdata_latched[6:2]}); + end + end + 3'b100: begin + if (mem_rdata_latched[11:10] == 2'b00) begin // C.SRLI + mem_rdata_q[31:25] <= 7'b0000000; + mem_rdata_q[14:12] <= 3'b 101; + end + if (mem_rdata_latched[11:10] == 2'b01) begin // C.SRAI + mem_rdata_q[31:25] <= 7'b0100000; + mem_rdata_q[14:12] <= 3'b 101; + end + if (mem_rdata_latched[11:10] == 2'b10) begin // C.ANDI + mem_rdata_q[14:12] <= 3'b111; + mem_rdata_q[31:20] <= $signed({mem_rdata_latched[12], mem_rdata_latched[6:2]}); + end + if (mem_rdata_latched[12:10] == 3'b011) begin // C.SUB, C.XOR, C.OR, C.AND + if (mem_rdata_latched[6:5] == 2'b00) mem_rdata_q[14:12] <= 3'b000; + if (mem_rdata_latched[6:5] == 2'b01) mem_rdata_q[14:12] <= 3'b100; + if (mem_rdata_latched[6:5] == 2'b10) mem_rdata_q[14:12] <= 3'b110; + if (mem_rdata_latched[6:5] == 2'b11) mem_rdata_q[14:12] <= 3'b111; + mem_rdata_q[31:25] <= mem_rdata_latched[6:5] == 2'b00 ? 7'b0100000 : 7'b0000000; + end + end + 3'b 110: begin // C.BEQZ + mem_rdata_q[14:12] <= 3'b000; + { mem_rdata_q[31], mem_rdata_q[7], mem_rdata_q[30:25], mem_rdata_q[11:8] } <= + $signed({mem_rdata_latched[12], mem_rdata_latched[6:5], mem_rdata_latched[2], + mem_rdata_latched[11:10], mem_rdata_latched[4:3]}); + end + 3'b 111: begin // C.BNEZ + mem_rdata_q[14:12] <= 3'b001; + { mem_rdata_q[31], mem_rdata_q[7], mem_rdata_q[30:25], mem_rdata_q[11:8] } <= + $signed({mem_rdata_latched[12], mem_rdata_latched[6:5], mem_rdata_latched[2], + mem_rdata_latched[11:10], mem_rdata_latched[4:3]}); + end + endcase + end + 2'b10: begin // Quadrant 2 + case (mem_rdata_latched[15:13]) + 3'b000: begin // C.SLLI + mem_rdata_q[31:25] <= 7'b0000000; + mem_rdata_q[14:12] <= 3'b 001; + end + 3'b010: begin // C.LWSP + mem_rdata_q[31:20] <= {4'b0, mem_rdata_latched[3:2], mem_rdata_latched[12], mem_rdata_latched[6:4], 2'b00}; + mem_rdata_q[14:12] <= 3'b 010; + end + 3'b100: begin + if (mem_rdata_latched[12] == 0 && mem_rdata_latched[6:2] == 0) begin // C.JR + mem_rdata_q[14:12] <= 3'b000; + mem_rdata_q[31:20] <= 12'b0; + end + if (mem_rdata_latched[12] == 0 && mem_rdata_latched[6:2] != 0) begin // C.MV + mem_rdata_q[14:12] <= 3'b000; + mem_rdata_q[31:25] <= 7'b0000000; + end + if (mem_rdata_latched[12] != 0 && mem_rdata_latched[11:7] != 0 && mem_rdata_latched[6:2] == 0) begin // C.JALR + mem_rdata_q[14:12] <= 3'b000; + mem_rdata_q[31:20] <= 12'b0; + end + if (mem_rdata_latched[12] != 0 && mem_rdata_latched[6:2] != 0) begin // C.ADD + mem_rdata_q[14:12] <= 3'b000; + mem_rdata_q[31:25] <= 7'b0000000; + end + end + 3'b110: begin // C.SWSP + {mem_rdata_q[31:25], mem_rdata_q[11:7]} <= {4'b0, mem_rdata_latched[8:7], mem_rdata_latched[12:9], 2'b00}; + mem_rdata_q[14:12] <= 3'b 010; + end + endcase + end + endcase + end + end + + always @(posedge clk) begin + if (resetn && !trap) begin + if (mem_do_prefetch || mem_do_rinst || mem_do_rdata) + `assert(!mem_do_wdata); + + if (mem_do_prefetch || mem_do_rinst) + `assert(!mem_do_rdata); + + if (mem_do_rdata) + `assert(!mem_do_prefetch && !mem_do_rinst); + + if (mem_do_wdata) + `assert(!(mem_do_prefetch || mem_do_rinst || mem_do_rdata)); + + if (mem_state == 2 || mem_state == 3) + `assert(mem_valid || mem_do_prefetch); + end + end + + always @(posedge clk) begin + if (!resetn || trap) begin + if (!resetn) + mem_state <= 0; + if (!resetn || mem_ready) + mem_valid <= 0; + mem_la_secondword <= 0; + prefetched_high_word <= 0; + end else begin + if (mem_la_read || mem_la_write) begin + mem_addr <= mem_la_addr; + mem_wstrb <= mem_la_wstrb & {4{mem_la_write}}; + end + if (mem_la_write) begin + mem_wdata <= mem_la_wdata; + end + case (mem_state) + 0: begin + if (mem_do_prefetch || mem_do_rinst || mem_do_rdata) begin + mem_valid <= !mem_la_use_prefetched_high_word; + mem_instr <= mem_do_prefetch || mem_do_rinst; + mem_wstrb <= 0; + mem_state <= 1; + end + if (mem_do_wdata) begin + mem_valid <= 1; + mem_instr <= 0; + mem_state <= 2; + end + end + 1: begin + `assert(mem_wstrb == 0); + `assert(mem_do_prefetch || mem_do_rinst || mem_do_rdata); + `assert(mem_valid == !mem_la_use_prefetched_high_word); + `assert(mem_instr == (mem_do_prefetch || mem_do_rinst)); + if (mem_xfer) begin + if (COMPRESSED_ISA && mem_la_read) begin + mem_valid <= 1; + mem_la_secondword <= 1; + if (!mem_la_use_prefetched_high_word) + mem_16bit_buffer <= mem_rdata[31:16]; + end else begin + mem_valid <= 0; + mem_la_secondword <= 0; + if (COMPRESSED_ISA && !mem_do_rdata) begin + if (~&mem_rdata[1:0] || mem_la_secondword) begin + mem_16bit_buffer <= mem_rdata[31:16]; + prefetched_high_word <= 1; + end else begin + prefetched_high_word <= 0; + end + end + mem_state <= mem_do_rinst || mem_do_rdata ? 0 : 3; + end + end + end + 2: begin + `assert(mem_wstrb != 0); + `assert(mem_do_wdata); + if (mem_xfer) begin + mem_valid <= 0; + mem_state <= 0; + end + end + 3: begin + `assert(mem_wstrb == 0); + `assert(mem_do_prefetch); + if (mem_do_rinst) begin + mem_state <= 0; + end + end + endcase + end + + if (clear_prefetched_high_word) + prefetched_high_word <= 0; + end + + + // Instruction Decoder + + reg instr_lui, instr_auipc, instr_jal, instr_jalr; + reg instr_beq, instr_bne, instr_blt, instr_bge, instr_bltu, instr_bgeu; + reg instr_lb, instr_lh, instr_lw, instr_lbu, instr_lhu, instr_sb, instr_sh, instr_sw; + reg instr_addi, instr_slti, instr_sltiu, instr_xori, instr_ori, instr_andi, instr_slli, instr_srli, instr_srai; + reg instr_add, instr_sub, instr_sll, instr_slt, instr_sltu, instr_xor, instr_srl, instr_sra, instr_or, instr_and; + reg instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh, instr_ecall_ebreak; + reg instr_getq, instr_setq, instr_retirq, instr_maskirq, instr_waitirq, instr_timer; + wire instr_trap; + + reg [regindex_bits-1:0] decoded_rd, decoded_rs1, decoded_rs2; + reg [31:0] decoded_imm, decoded_imm_j; + reg decoder_trigger; + reg decoder_trigger_q; + reg decoder_pseudo_trigger; + reg decoder_pseudo_trigger_q; + reg compressed_instr; + + reg is_lui_auipc_jal; + reg is_lb_lh_lw_lbu_lhu; + reg is_slli_srli_srai; + reg is_jalr_addi_slti_sltiu_xori_ori_andi; + reg is_sb_sh_sw; + reg is_sll_srl_sra; + reg is_lui_auipc_jal_jalr_addi_add_sub; + reg is_slti_blt_slt; + reg is_sltiu_bltu_sltu; + reg is_beq_bne_blt_bge_bltu_bgeu; + reg is_lbu_lhu_lw; + reg is_alu_reg_imm; + reg is_alu_reg_reg; + reg is_compare; + + assign instr_trap = (CATCH_ILLINSN || WITH_PCPI) && !{instr_lui, instr_auipc, instr_jal, instr_jalr, + instr_beq, instr_bne, instr_blt, instr_bge, instr_bltu, instr_bgeu, + instr_lb, instr_lh, instr_lw, instr_lbu, instr_lhu, instr_sb, instr_sh, instr_sw, + instr_addi, instr_slti, instr_sltiu, instr_xori, instr_ori, instr_andi, instr_slli, instr_srli, instr_srai, + instr_add, instr_sub, instr_sll, instr_slt, instr_sltu, instr_xor, instr_srl, instr_sra, instr_or, instr_and, + instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh, + instr_getq, instr_setq, instr_retirq, instr_maskirq, instr_waitirq, instr_timer}; + + wire is_rdcycle_rdcycleh_rdinstr_rdinstrh; + assign is_rdcycle_rdcycleh_rdinstr_rdinstrh = |{instr_rdcycle, instr_rdcycleh, instr_rdinstr, instr_rdinstrh}; + + reg [63:0] new_ascii_instr; + `FORMAL_KEEP reg [63:0] dbg_ascii_instr; + `FORMAL_KEEP reg [31:0] dbg_insn_imm; + `FORMAL_KEEP reg [4:0] dbg_insn_rs1; + `FORMAL_KEEP reg [4:0] dbg_insn_rs2; + `FORMAL_KEEP reg [4:0] dbg_insn_rd; + `FORMAL_KEEP reg [31:0] dbg_rs1val; + `FORMAL_KEEP reg [31:0] dbg_rs2val; + `FORMAL_KEEP reg dbg_rs1val_valid; + `FORMAL_KEEP reg dbg_rs2val_valid; + + always @* begin + new_ascii_instr = ""; + + if (instr_lui) new_ascii_instr = "lui"; + if (instr_auipc) new_ascii_instr = "auipc"; + if (instr_jal) new_ascii_instr = "jal"; + if (instr_jalr) new_ascii_instr = "jalr"; + + if (instr_beq) new_ascii_instr = "beq"; + if (instr_bne) new_ascii_instr = "bne"; + if (instr_blt) new_ascii_instr = "blt"; + if (instr_bge) new_ascii_instr = "bge"; + if (instr_bltu) new_ascii_instr = "bltu"; + if (instr_bgeu) new_ascii_instr = "bgeu"; + + if (instr_lb) new_ascii_instr = "lb"; + if (instr_lh) new_ascii_instr = "lh"; + if (instr_lw) new_ascii_instr = "lw"; + if (instr_lbu) new_ascii_instr = "lbu"; + if (instr_lhu) new_ascii_instr = "lhu"; + if (instr_sb) new_ascii_instr = "sb"; + if (instr_sh) new_ascii_instr = "sh"; + if (instr_sw) new_ascii_instr = "sw"; + + if (instr_addi) new_ascii_instr = "addi"; + if (instr_slti) new_ascii_instr = "slti"; + if (instr_sltiu) new_ascii_instr = "sltiu"; + if (instr_xori) new_ascii_instr = "xori"; + if (instr_ori) new_ascii_instr = "ori"; + if (instr_andi) new_ascii_instr = "andi"; + if (instr_slli) new_ascii_instr = "slli"; + if (instr_srli) new_ascii_instr = "srli"; + if (instr_srai) new_ascii_instr = "srai"; + + if (instr_add) new_ascii_instr = "add"; + if (instr_sub) new_ascii_instr = "sub"; + if (instr_sll) new_ascii_instr = "sll"; + if (instr_slt) new_ascii_instr = "slt"; + if (instr_sltu) new_ascii_instr = "sltu"; + if (instr_xor) new_ascii_instr = "xor"; + if (instr_srl) new_ascii_instr = "srl"; + if (instr_sra) new_ascii_instr = "sra"; + if (instr_or) new_ascii_instr = "or"; + if (instr_and) new_ascii_instr = "and"; + + if (instr_rdcycle) new_ascii_instr = "rdcycle"; + if (instr_rdcycleh) new_ascii_instr = "rdcycleh"; + if (instr_rdinstr) new_ascii_instr = "rdinstr"; + if (instr_rdinstrh) new_ascii_instr = "rdinstrh"; + + if (instr_getq) new_ascii_instr = "getq"; + if (instr_setq) new_ascii_instr = "setq"; + if (instr_retirq) new_ascii_instr = "retirq"; + if (instr_maskirq) new_ascii_instr = "maskirq"; + if (instr_waitirq) new_ascii_instr = "waitirq"; + if (instr_timer) new_ascii_instr = "timer"; + end + + reg [63:0] q_ascii_instr; + reg [31:0] q_insn_imm; + reg [31:0] q_insn_opcode; + reg [4:0] q_insn_rs1; + reg [4:0] q_insn_rs2; + reg [4:0] q_insn_rd; + reg dbg_next; + + wire launch_next_insn; + reg dbg_valid_insn; + + reg [63:0] cached_ascii_instr; + reg [31:0] cached_insn_imm; + reg [31:0] cached_insn_opcode; + reg [4:0] cached_insn_rs1; + reg [4:0] cached_insn_rs2; + reg [4:0] cached_insn_rd; + + always @(posedge clk) begin + q_ascii_instr <= dbg_ascii_instr; + q_insn_imm <= dbg_insn_imm; + q_insn_opcode <= dbg_insn_opcode; + q_insn_rs1 <= dbg_insn_rs1; + q_insn_rs2 <= dbg_insn_rs2; + q_insn_rd <= dbg_insn_rd; + dbg_next <= launch_next_insn; + + if (!resetn || trap) + dbg_valid_insn <= 0; + else if (launch_next_insn) + dbg_valid_insn <= 1; + + if (decoder_trigger_q) begin + cached_ascii_instr <= new_ascii_instr; + cached_insn_imm <= decoded_imm; + if (&next_insn_opcode[1:0]) + cached_insn_opcode <= next_insn_opcode; + else + cached_insn_opcode <= {16'b0, next_insn_opcode[15:0]}; + cached_insn_rs1 <= decoded_rs1; + cached_insn_rs2 <= decoded_rs2; + cached_insn_rd <= decoded_rd; + end + + if (launch_next_insn) begin + dbg_insn_addr <= next_pc; + end + end + + always @* begin + dbg_ascii_instr = q_ascii_instr; + dbg_insn_imm = q_insn_imm; + dbg_insn_opcode = q_insn_opcode; + dbg_insn_rs1 = q_insn_rs1; + dbg_insn_rs2 = q_insn_rs2; + dbg_insn_rd = q_insn_rd; + + if (dbg_next) begin + if (decoder_pseudo_trigger_q) begin + dbg_ascii_instr = cached_ascii_instr; + dbg_insn_imm = cached_insn_imm; + dbg_insn_opcode = cached_insn_opcode; + dbg_insn_rs1 = cached_insn_rs1; + dbg_insn_rs2 = cached_insn_rs2; + dbg_insn_rd = cached_insn_rd; + end else begin + dbg_ascii_instr = new_ascii_instr; + if (&next_insn_opcode[1:0]) + dbg_insn_opcode = next_insn_opcode; + else + dbg_insn_opcode = {16'b0, next_insn_opcode[15:0]}; + dbg_insn_imm = decoded_imm; + dbg_insn_rs1 = decoded_rs1; + dbg_insn_rs2 = decoded_rs2; + dbg_insn_rd = decoded_rd; + end + end + end + +`ifdef DEBUGASM + always @(posedge clk) begin + if (dbg_next) begin + $display("debugasm %x %x %s", dbg_insn_addr, dbg_insn_opcode, dbg_ascii_instr ? dbg_ascii_instr : "*"); + end + end +`endif + +`ifdef DEBUG + always @(posedge clk) begin + if (dbg_next) begin + if (&dbg_insn_opcode[1:0]) + $display("DECODE: 0x%08x 0x%08x %-0s", dbg_insn_addr, dbg_insn_opcode, dbg_ascii_instr ? dbg_ascii_instr : "UNKNOWN"); + else + $display("DECODE: 0x%08x 0x%04x %-0s", dbg_insn_addr, dbg_insn_opcode[15:0], dbg_ascii_instr ? dbg_ascii_instr : "UNKNOWN"); + end + end +`endif + + always @(posedge clk) begin + is_lui_auipc_jal <= |{instr_lui, instr_auipc, instr_jal}; + is_lui_auipc_jal_jalr_addi_add_sub <= |{instr_lui, instr_auipc, instr_jal, instr_jalr, instr_addi, instr_add, instr_sub}; + is_slti_blt_slt <= |{instr_slti, instr_blt, instr_slt}; + is_sltiu_bltu_sltu <= |{instr_sltiu, instr_bltu, instr_sltu}; + is_lbu_lhu_lw <= |{instr_lbu, instr_lhu, instr_lw}; + is_compare <= |{is_beq_bne_blt_bge_bltu_bgeu, instr_slti, instr_slt, instr_sltiu, instr_sltu}; + + if (mem_do_rinst && mem_done) begin + instr_lui <= mem_rdata_latched[6:0] == 7'b0110111; + instr_auipc <= mem_rdata_latched[6:0] == 7'b0010111; + instr_jal <= mem_rdata_latched[6:0] == 7'b1101111; + instr_jalr <= mem_rdata_latched[6:0] == 7'b1100111 && mem_rdata_latched[14:12] == 3'b000; + instr_retirq <= mem_rdata_latched[6:0] == 7'b0001011 && mem_rdata_latched[31:25] == 7'b0000010 && ENABLE_IRQ; + instr_waitirq <= mem_rdata_latched[6:0] == 7'b0001011 && mem_rdata_latched[31:25] == 7'b0000100 && ENABLE_IRQ; + + is_beq_bne_blt_bge_bltu_bgeu <= mem_rdata_latched[6:0] == 7'b1100011; + is_lb_lh_lw_lbu_lhu <= mem_rdata_latched[6:0] == 7'b0000011; + is_sb_sh_sw <= mem_rdata_latched[6:0] == 7'b0100011; + is_alu_reg_imm <= mem_rdata_latched[6:0] == 7'b0010011; + is_alu_reg_reg <= mem_rdata_latched[6:0] == 7'b0110011; + + { decoded_imm_j[31:20], decoded_imm_j[10:1], decoded_imm_j[11], decoded_imm_j[19:12], decoded_imm_j[0] } <= $signed({mem_rdata_latched[31:12], 1'b0}); + + decoded_rd <= mem_rdata_latched[11:7]; + decoded_rs1 <= mem_rdata_latched[19:15]; + decoded_rs2 <= mem_rdata_latched[24:20]; + + if (mem_rdata_latched[6:0] == 7'b0001011 && mem_rdata_latched[31:25] == 7'b0000000 && ENABLE_IRQ && ENABLE_IRQ_QREGS) + decoded_rs1[regindex_bits-1] <= 1; // instr_getq + + if (mem_rdata_latched[6:0] == 7'b0001011 && mem_rdata_latched[31:25] == 7'b0000010 && ENABLE_IRQ) + decoded_rs1 <= ENABLE_IRQ_QREGS ? irqregs_offset : 3; // instr_retirq + + compressed_instr <= 0; + if (COMPRESSED_ISA && mem_rdata_latched[1:0] != 2'b11) begin + compressed_instr <= 1; + decoded_rd <= 0; + decoded_rs1 <= 0; + decoded_rs2 <= 0; + + { decoded_imm_j[31:11], decoded_imm_j[4], decoded_imm_j[9:8], decoded_imm_j[10], decoded_imm_j[6], + decoded_imm_j[7], decoded_imm_j[3:1], decoded_imm_j[5], decoded_imm_j[0] } <= $signed({mem_rdata_latched[12:2], 1'b0}); + + case (mem_rdata_latched[1:0]) + 2'b00: begin // Quadrant 0 + case (mem_rdata_latched[15:13]) + 3'b000: begin // C.ADDI4SPN + is_alu_reg_imm <= |mem_rdata_latched[12:5]; + decoded_rs1 <= 2; + decoded_rd <= 8 + mem_rdata_latched[4:2]; + end + 3'b010: begin // C.LW + is_lb_lh_lw_lbu_lhu <= 1; + decoded_rs1 <= 8 + mem_rdata_latched[9:7]; + decoded_rd <= 8 + mem_rdata_latched[4:2]; + end + 3'b110: begin // C.SW + is_sb_sh_sw <= 1; + decoded_rs1 <= 8 + mem_rdata_latched[9:7]; + decoded_rs2 <= 8 + mem_rdata_latched[4:2]; + end + endcase + end + 2'b01: begin // Quadrant 1 + case (mem_rdata_latched[15:13]) + 3'b000: begin // C.NOP / C.ADDI + is_alu_reg_imm <= 1; + decoded_rd <= mem_rdata_latched[11:7]; + decoded_rs1 <= mem_rdata_latched[11:7]; + end + 3'b001: begin // C.JAL + instr_jal <= 1; + decoded_rd <= 1; + end + 3'b 010: begin // C.LI + is_alu_reg_imm <= 1; + decoded_rd <= mem_rdata_latched[11:7]; + decoded_rs1 <= 0; + end + 3'b 011: begin + if (mem_rdata_latched[12] || mem_rdata_latched[6:2]) begin + if (mem_rdata_latched[11:7] == 2) begin // C.ADDI16SP + is_alu_reg_imm <= 1; + decoded_rd <= mem_rdata_latched[11:7]; + decoded_rs1 <= mem_rdata_latched[11:7]; + end else begin // C.LUI + instr_lui <= 1; + decoded_rd <= mem_rdata_latched[11:7]; + decoded_rs1 <= 0; + end + end + end + 3'b100: begin + if (!mem_rdata_latched[11] && !mem_rdata_latched[12]) begin // C.SRLI, C.SRAI + is_alu_reg_imm <= 1; + decoded_rd <= 8 + mem_rdata_latched[9:7]; + decoded_rs1 <= 8 + mem_rdata_latched[9:7]; + decoded_rs2 <= {mem_rdata_latched[12], mem_rdata_latched[6:2]}; + end + if (mem_rdata_latched[11:10] == 2'b10) begin // C.ANDI + is_alu_reg_imm <= 1; + decoded_rd <= 8 + mem_rdata_latched[9:7]; + decoded_rs1 <= 8 + mem_rdata_latched[9:7]; + end + if (mem_rdata_latched[12:10] == 3'b011) begin // C.SUB, C.XOR, C.OR, C.AND + is_alu_reg_reg <= 1; + decoded_rd <= 8 + mem_rdata_latched[9:7]; + decoded_rs1 <= 8 + mem_rdata_latched[9:7]; + decoded_rs2 <= 8 + mem_rdata_latched[4:2]; + end + end + 3'b101: begin // C.J + instr_jal <= 1; + end + 3'b110: begin // C.BEQZ + is_beq_bne_blt_bge_bltu_bgeu <= 1; + decoded_rs1 <= 8 + mem_rdata_latched[9:7]; + decoded_rs2 <= 0; + end + 3'b111: begin // C.BNEZ + is_beq_bne_blt_bge_bltu_bgeu <= 1; + decoded_rs1 <= 8 + mem_rdata_latched[9:7]; + decoded_rs2 <= 0; + end + endcase + end + 2'b10: begin // Quadrant 2 + case (mem_rdata_latched[15:13]) + 3'b000: begin // C.SLLI + if (!mem_rdata_latched[12]) begin + is_alu_reg_imm <= 1; + decoded_rd <= mem_rdata_latched[11:7]; + decoded_rs1 <= mem_rdata_latched[11:7]; + decoded_rs2 <= {mem_rdata_latched[12], mem_rdata_latched[6:2]}; + end + end + 3'b010: begin // C.LWSP + if (mem_rdata_latched[11:7]) begin + is_lb_lh_lw_lbu_lhu <= 1; + decoded_rd <= mem_rdata_latched[11:7]; + decoded_rs1 <= 2; + end + end + 3'b100: begin + if (mem_rdata_latched[12] == 0 && mem_rdata_latched[11:7] != 0 && mem_rdata_latched[6:2] == 0) begin // C.JR + instr_jalr <= 1; + decoded_rd <= 0; + decoded_rs1 <= mem_rdata_latched[11:7]; + end + if (mem_rdata_latched[12] == 0 && mem_rdata_latched[6:2] != 0) begin // C.MV + is_alu_reg_reg <= 1; + decoded_rd <= mem_rdata_latched[11:7]; + decoded_rs1 <= 0; + decoded_rs2 <= mem_rdata_latched[6:2]; + end + if (mem_rdata_latched[12] != 0 && mem_rdata_latched[11:7] != 0 && mem_rdata_latched[6:2] == 0) begin // C.JALR + instr_jalr <= 1; + decoded_rd <= 1; + decoded_rs1 <= mem_rdata_latched[11:7]; + end + if (mem_rdata_latched[12] != 0 && mem_rdata_latched[6:2] != 0) begin // C.ADD + is_alu_reg_reg <= 1; + decoded_rd <= mem_rdata_latched[11:7]; + decoded_rs1 <= mem_rdata_latched[11:7]; + decoded_rs2 <= mem_rdata_latched[6:2]; + end + end + 3'b110: begin // C.SWSP + is_sb_sh_sw <= 1; + decoded_rs1 <= 2; + decoded_rs2 <= mem_rdata_latched[6:2]; + end + endcase + end + endcase + end + end + + if (decoder_trigger && !decoder_pseudo_trigger) begin + pcpi_insn <= WITH_PCPI ? mem_rdata_q : 'bx; + + instr_beq <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b000; + instr_bne <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b001; + instr_blt <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b100; + instr_bge <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b101; + instr_bltu <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b110; + instr_bgeu <= is_beq_bne_blt_bge_bltu_bgeu && mem_rdata_q[14:12] == 3'b111; + + instr_lb <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b000; + instr_lh <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b001; + instr_lw <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b010; + instr_lbu <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b100; + instr_lhu <= is_lb_lh_lw_lbu_lhu && mem_rdata_q[14:12] == 3'b101; + + instr_sb <= is_sb_sh_sw && mem_rdata_q[14:12] == 3'b000; + instr_sh <= is_sb_sh_sw && mem_rdata_q[14:12] == 3'b001; + instr_sw <= is_sb_sh_sw && mem_rdata_q[14:12] == 3'b010; + + instr_addi <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b000; + instr_slti <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b010; + instr_sltiu <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b011; + instr_xori <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b100; + instr_ori <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b110; + instr_andi <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b111; + + instr_slli <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b001 && mem_rdata_q[31:25] == 7'b0000000; + instr_srli <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0000000; + instr_srai <= is_alu_reg_imm && mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0100000; + + instr_add <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b000 && mem_rdata_q[31:25] == 7'b0000000; + instr_sub <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b000 && mem_rdata_q[31:25] == 7'b0100000; + instr_sll <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b001 && mem_rdata_q[31:25] == 7'b0000000; + instr_slt <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b010 && mem_rdata_q[31:25] == 7'b0000000; + instr_sltu <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b011 && mem_rdata_q[31:25] == 7'b0000000; + instr_xor <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b100 && mem_rdata_q[31:25] == 7'b0000000; + instr_srl <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0000000; + instr_sra <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0100000; + instr_or <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b110 && mem_rdata_q[31:25] == 7'b0000000; + instr_and <= is_alu_reg_reg && mem_rdata_q[14:12] == 3'b111 && mem_rdata_q[31:25] == 7'b0000000; + + instr_rdcycle <= ((mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11000000000000000010) || + (mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11000000000100000010)) && ENABLE_COUNTERS; + instr_rdcycleh <= ((mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11001000000000000010) || + (mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11001000000100000010)) && ENABLE_COUNTERS && ENABLE_COUNTERS64; + instr_rdinstr <= (mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11000000001000000010) && ENABLE_COUNTERS; + instr_rdinstrh <= (mem_rdata_q[6:0] == 7'b1110011 && mem_rdata_q[31:12] == 'b11001000001000000010) && ENABLE_COUNTERS && ENABLE_COUNTERS64; + + instr_ecall_ebreak <= ((mem_rdata_q[6:0] == 7'b1110011 && !mem_rdata_q[31:21] && !mem_rdata_q[19:7]) || + (COMPRESSED_ISA && mem_rdata_q[15:0] == 16'h9002)); + + instr_getq <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000000 && ENABLE_IRQ && ENABLE_IRQ_QREGS; + instr_setq <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000001 && ENABLE_IRQ && ENABLE_IRQ_QREGS; + instr_maskirq <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000011 && ENABLE_IRQ; + instr_timer <= mem_rdata_q[6:0] == 7'b0001011 && mem_rdata_q[31:25] == 7'b0000101 && ENABLE_IRQ && ENABLE_IRQ_TIMER; + + is_slli_srli_srai <= is_alu_reg_imm && |{ + mem_rdata_q[14:12] == 3'b001 && mem_rdata_q[31:25] == 7'b0000000, + mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0000000, + mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0100000 + }; + + is_jalr_addi_slti_sltiu_xori_ori_andi <= instr_jalr || is_alu_reg_imm && |{ + mem_rdata_q[14:12] == 3'b000, + mem_rdata_q[14:12] == 3'b010, + mem_rdata_q[14:12] == 3'b011, + mem_rdata_q[14:12] == 3'b100, + mem_rdata_q[14:12] == 3'b110, + mem_rdata_q[14:12] == 3'b111 + }; + + is_sll_srl_sra <= is_alu_reg_reg && |{ + mem_rdata_q[14:12] == 3'b001 && mem_rdata_q[31:25] == 7'b0000000, + mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0000000, + mem_rdata_q[14:12] == 3'b101 && mem_rdata_q[31:25] == 7'b0100000 + }; + + is_lui_auipc_jal_jalr_addi_add_sub <= 0; + is_compare <= 0; + + (* parallel_case *) + case (1'b1) + instr_jal: + decoded_imm <= decoded_imm_j; + |{instr_lui, instr_auipc}: + decoded_imm <= mem_rdata_q[31:12] << 12; + |{instr_jalr, is_lb_lh_lw_lbu_lhu, is_alu_reg_imm}: + decoded_imm <= $signed(mem_rdata_q[31:20]); + is_beq_bne_blt_bge_bltu_bgeu: + decoded_imm <= $signed({mem_rdata_q[31], mem_rdata_q[7], mem_rdata_q[30:25], mem_rdata_q[11:8], 1'b0}); + is_sb_sh_sw: + decoded_imm <= $signed({mem_rdata_q[31:25], mem_rdata_q[11:7]}); + default: + decoded_imm <= 1'bx; + endcase + end + + if (!resetn) begin + is_beq_bne_blt_bge_bltu_bgeu <= 0; + is_compare <= 0; + + instr_beq <= 0; + instr_bne <= 0; + instr_blt <= 0; + instr_bge <= 0; + instr_bltu <= 0; + instr_bgeu <= 0; + + instr_addi <= 0; + instr_slti <= 0; + instr_sltiu <= 0; + instr_xori <= 0; + instr_ori <= 0; + instr_andi <= 0; + + instr_add <= 0; + instr_sub <= 0; + instr_sll <= 0; + instr_slt <= 0; + instr_sltu <= 0; + instr_xor <= 0; + instr_srl <= 0; + instr_sra <= 0; + instr_or <= 0; + instr_and <= 0; + end + end + + + // Main State Machine + + localparam cpu_state_trap = 8'b10000000; + localparam cpu_state_fetch = 8'b01000000; + localparam cpu_state_ld_rs1 = 8'b00100000; + localparam cpu_state_ld_rs2 = 8'b00010000; + localparam cpu_state_exec = 8'b00001000; + localparam cpu_state_shift = 8'b00000100; + localparam cpu_state_stmem = 8'b00000010; + localparam cpu_state_ldmem = 8'b00000001; + + reg [7:0] cpu_state; + reg [1:0] irq_state; + + `FORMAL_KEEP reg [127:0] dbg_ascii_state; + + always @* begin + dbg_ascii_state = ""; + if (cpu_state == cpu_state_trap) dbg_ascii_state = "trap"; + if (cpu_state == cpu_state_fetch) dbg_ascii_state = "fetch"; + if (cpu_state == cpu_state_ld_rs1) dbg_ascii_state = "ld_rs1"; + if (cpu_state == cpu_state_ld_rs2) dbg_ascii_state = "ld_rs2"; + if (cpu_state == cpu_state_exec) dbg_ascii_state = "exec"; + if (cpu_state == cpu_state_shift) dbg_ascii_state = "shift"; + if (cpu_state == cpu_state_stmem) dbg_ascii_state = "stmem"; + if (cpu_state == cpu_state_ldmem) dbg_ascii_state = "ldmem"; + end + + reg set_mem_do_rinst; + reg set_mem_do_rdata; + reg set_mem_do_wdata; + + reg latched_store; + reg latched_stalu; + reg latched_branch; + reg latched_compr; + reg latched_trace; + reg latched_is_lu; + reg latched_is_lh; + reg latched_is_lb; + reg [regindex_bits-1:0] latched_rd; + + reg [31:0] current_pc; + assign next_pc = latched_store && latched_branch ? reg_out & ~1 : reg_next_pc; + + reg [3:0] pcpi_timeout_counter; + reg pcpi_timeout; + + reg [31:0] next_irq_pending; + reg do_waitirq; + + reg [31:0] alu_out, alu_out_q; + reg alu_out_0, alu_out_0_q; + reg alu_wait, alu_wait_2; + + reg [31:0] alu_add_sub; + reg [31:0] alu_shl, alu_shr; + reg alu_eq, alu_ltu, alu_lts; + + generate if (TWO_CYCLE_ALU) begin + always @(posedge clk) begin + alu_add_sub <= instr_sub ? reg_op1 - reg_op2 : reg_op1 + reg_op2; + alu_eq <= reg_op1 == reg_op2; + alu_lts <= $signed(reg_op1) < $signed(reg_op2); + alu_ltu <= reg_op1 < reg_op2; + alu_shl <= reg_op1 << reg_op2[4:0]; + alu_shr <= $signed({instr_sra || instr_srai ? reg_op1[31] : 1'b0, reg_op1}) >>> reg_op2[4:0]; + end + end else begin + always @* begin + alu_add_sub = instr_sub ? reg_op1 - reg_op2 : reg_op1 + reg_op2; + alu_eq = reg_op1 == reg_op2; + alu_lts = $signed(reg_op1) < $signed(reg_op2); + alu_ltu = reg_op1 < reg_op2; + alu_shl = reg_op1 << reg_op2[4:0]; + alu_shr = $signed({instr_sra || instr_srai ? reg_op1[31] : 1'b0, reg_op1}) >>> reg_op2[4:0]; + end + end endgenerate + + always @* begin + alu_out_0 = 'bx; + (* parallel_case, full_case *) + case (1'b1) + instr_beq: + alu_out_0 = alu_eq; + instr_bne: + alu_out_0 = !alu_eq; + instr_bge: + alu_out_0 = !alu_lts; + instr_bgeu: + alu_out_0 = !alu_ltu; + is_slti_blt_slt && (!TWO_CYCLE_COMPARE || !{instr_beq,instr_bne,instr_bge,instr_bgeu}): + alu_out_0 = alu_lts; + is_sltiu_bltu_sltu && (!TWO_CYCLE_COMPARE || !{instr_beq,instr_bne,instr_bge,instr_bgeu}): + alu_out_0 = alu_ltu; + endcase + + alu_out = 'bx; + (* parallel_case, full_case *) + case (1'b1) + is_lui_auipc_jal_jalr_addi_add_sub: + alu_out = alu_add_sub; + is_compare: + alu_out = alu_out_0; + instr_xori || instr_xor: + alu_out = reg_op1 ^ reg_op2; + instr_ori || instr_or: + alu_out = reg_op1 | reg_op2; + instr_andi || instr_and: + alu_out = reg_op1 & reg_op2; + BARREL_SHIFTER && (instr_sll || instr_slli): + alu_out = alu_shl; + BARREL_SHIFTER && (instr_srl || instr_srli || instr_sra || instr_srai): + alu_out = alu_shr; + endcase + +`ifdef RISCV_FORMAL_BLACKBOX_ALU + alu_out_0 = $anyseq; + alu_out = $anyseq; +`endif + end + + reg clear_prefetched_high_word_q; + always @(posedge clk) clear_prefetched_high_word_q <= clear_prefetched_high_word; + + always @* begin + clear_prefetched_high_word = clear_prefetched_high_word_q; + if (!prefetched_high_word) + clear_prefetched_high_word = 0; + if (latched_branch || irq_state || !resetn) + clear_prefetched_high_word = COMPRESSED_ISA; + end + + reg cpuregs_write; + reg [31:0] cpuregs_wrdata; + reg [31:0] cpuregs_rs1; + reg [31:0] cpuregs_rs2; + reg [regindex_bits-1:0] decoded_rs; + + always @* begin + cpuregs_write = 0; + cpuregs_wrdata = 'bx; + + if (cpu_state == cpu_state_fetch) begin + (* parallel_case *) + case (1'b1) + latched_branch: begin + cpuregs_wrdata = reg_pc + (latched_compr ? 2 : 4); + cpuregs_write = 1; + end + latched_store && !latched_branch: begin + cpuregs_wrdata = latched_stalu ? alu_out_q : reg_out; + cpuregs_write = 1; + end + ENABLE_IRQ && irq_state[0]: begin + cpuregs_wrdata = reg_next_pc | latched_compr; + cpuregs_write = 1; + end + ENABLE_IRQ && irq_state[1]: begin + cpuregs_wrdata = irq_pending & ~irq_mask; + cpuregs_write = 1; + end + endcase + end + end + +`ifndef PICORV32_REGS + always @(posedge clk) begin + if (resetn && cpuregs_write && latched_rd) +`ifdef PICORV32_TESTBUG_001 + cpuregs[latched_rd ^ 1] <= cpuregs_wrdata; +`elsif PICORV32_TESTBUG_002 + cpuregs[latched_rd] <= cpuregs_wrdata ^ 1; +`else + cpuregs[latched_rd] <= cpuregs_wrdata; +`endif + end + + always @* begin + decoded_rs = 'bx; + if (ENABLE_REGS_DUALPORT) begin +`ifndef RISCV_FORMAL_BLACKBOX_REGS + cpuregs_rs1 = decoded_rs1 ? cpuregs[decoded_rs1] : 0; + cpuregs_rs2 = decoded_rs2 ? cpuregs[decoded_rs2] : 0; +`else + cpuregs_rs1 = decoded_rs1 ? $anyseq : 0; + cpuregs_rs2 = decoded_rs2 ? $anyseq : 0; +`endif + end else begin + decoded_rs = (cpu_state == cpu_state_ld_rs2) ? decoded_rs2 : decoded_rs1; +`ifndef RISCV_FORMAL_BLACKBOX_REGS + cpuregs_rs1 = decoded_rs ? cpuregs[decoded_rs] : 0; +`else + cpuregs_rs1 = decoded_rs ? $anyseq : 0; +`endif + cpuregs_rs2 = cpuregs_rs1; + end + end +`else + wire[31:0] cpuregs_rdata1; + wire[31:0] cpuregs_rdata2; + + wire [5:0] cpuregs_waddr = latched_rd; + wire [5:0] cpuregs_raddr1 = ENABLE_REGS_DUALPORT ? decoded_rs1 : decoded_rs; + wire [5:0] cpuregs_raddr2 = ENABLE_REGS_DUALPORT ? decoded_rs2 : 0; + + `PICORV32_REGS cpuregs ( + .clk(clk), + .wen(resetn && cpuregs_write && latched_rd), + .waddr(cpuregs_waddr), + .raddr1(cpuregs_raddr1), + .raddr2(cpuregs_raddr2), + .wdata(cpuregs_wrdata), + .rdata1(cpuregs_rdata1), + .rdata2(cpuregs_rdata2) + ); + + always @* begin + decoded_rs = 'bx; + if (ENABLE_REGS_DUALPORT) begin + cpuregs_rs1 = decoded_rs1 ? cpuregs_rdata1 : 0; + cpuregs_rs2 = decoded_rs2 ? cpuregs_rdata2 : 0; + end else begin + decoded_rs = (cpu_state == cpu_state_ld_rs2) ? decoded_rs2 : decoded_rs1; + cpuregs_rs1 = decoded_rs ? cpuregs_rdata1 : 0; + cpuregs_rs2 = cpuregs_rs1; + end + end +`endif + + assign launch_next_insn = cpu_state == cpu_state_fetch && decoder_trigger && (!ENABLE_IRQ || irq_delay || irq_active || !(irq_pending & ~irq_mask)); + + always @(posedge clk) begin + trap <= 0; + reg_sh <= 'bx; + reg_out <= 'bx; + set_mem_do_rinst = 0; + set_mem_do_rdata = 0; + set_mem_do_wdata = 0; + + alu_out_0_q <= alu_out_0; + alu_out_q <= alu_out; + + alu_wait <= 0; + alu_wait_2 <= 0; + + if (launch_next_insn) begin + dbg_rs1val <= 'bx; + dbg_rs2val <= 'bx; + dbg_rs1val_valid <= 0; + dbg_rs2val_valid <= 0; + end + + if (WITH_PCPI && CATCH_ILLINSN) begin + if (resetn && pcpi_valid && !pcpi_int_wait) begin + if (pcpi_timeout_counter) + pcpi_timeout_counter <= pcpi_timeout_counter - 1; + end else + pcpi_timeout_counter <= ~0; + pcpi_timeout <= !pcpi_timeout_counter; + end + + if (ENABLE_COUNTERS) begin + count_cycle <= resetn ? count_cycle + 1 : 0; + if (!ENABLE_COUNTERS64) count_cycle[63:32] <= 0; + end else begin + count_cycle <= 'bx; + count_instr <= 'bx; + end + + next_irq_pending = ENABLE_IRQ ? irq_pending & LATCHED_IRQ : 'bx; + + if (ENABLE_IRQ && ENABLE_IRQ_TIMER && timer) begin + timer <= timer - 1; + end + + decoder_trigger <= mem_do_rinst && mem_done; + decoder_trigger_q <= decoder_trigger; + decoder_pseudo_trigger <= 0; + decoder_pseudo_trigger_q <= decoder_pseudo_trigger; + do_waitirq <= 0; + + trace_valid <= 0; + + if (!ENABLE_TRACE) + trace_data <= 'bx; + + if (!resetn) begin + reg_pc <= PROGADDR_RESET; + reg_next_pc <= PROGADDR_RESET; + if (ENABLE_COUNTERS) + count_instr <= 0; + latched_store <= 0; + latched_stalu <= 0; + latched_branch <= 0; + latched_trace <= 0; + latched_is_lu <= 0; + latched_is_lh <= 0; + latched_is_lb <= 0; + pcpi_valid <= 0; + pcpi_timeout <= 0; + irq_active <= 0; + irq_delay <= 0; + irq_mask <= ~0; + next_irq_pending = 0; + irq_state <= 0; + eoi <= 0; + timer <= 0; + if (~STACKADDR) begin + latched_store <= 1; + latched_rd <= 2; + reg_out <= STACKADDR; + end + cpu_state <= cpu_state_fetch; + end else + (* parallel_case, full_case *) + case (cpu_state) + cpu_state_trap: begin + trap <= 1; + end + + cpu_state_fetch: begin + mem_do_rinst <= !decoder_trigger && !do_waitirq; + mem_wordsize <= 0; + + current_pc = reg_next_pc; + + (* parallel_case *) + case (1'b1) + latched_branch: begin + current_pc = latched_store ? (latched_stalu ? alu_out_q : reg_out) & ~1 : reg_next_pc; + `debug($display("ST_RD: %2d 0x%08x, BRANCH 0x%08x", latched_rd, reg_pc + (latched_compr ? 2 : 4), current_pc);) + end + latched_store && !latched_branch: begin + `debug($display("ST_RD: %2d 0x%08x", latched_rd, latched_stalu ? alu_out_q : reg_out);) + end + ENABLE_IRQ && irq_state[0]: begin + current_pc = PROGADDR_IRQ; + irq_active <= 1; + mem_do_rinst <= 1; + end + ENABLE_IRQ && irq_state[1]: begin + eoi <= irq_pending & ~irq_mask; + next_irq_pending = next_irq_pending & irq_mask; + end + endcase + + if (ENABLE_TRACE && latched_trace) begin + latched_trace <= 0; + trace_valid <= 1; + if (latched_branch) + trace_data <= (irq_active ? TRACE_IRQ : 0) | TRACE_BRANCH | (current_pc & 32'hfffffffe); + else + trace_data <= (irq_active ? TRACE_IRQ : 0) | (latched_stalu ? alu_out_q : reg_out); + end + + reg_pc <= current_pc; + reg_next_pc <= current_pc; + + latched_store <= 0; + latched_stalu <= 0; + latched_branch <= 0; + latched_is_lu <= 0; + latched_is_lh <= 0; + latched_is_lb <= 0; + latched_rd <= decoded_rd; + latched_compr <= compressed_instr; + + if (ENABLE_IRQ && ((decoder_trigger && !irq_active && !irq_delay && |(irq_pending & ~irq_mask)) || irq_state)) begin + irq_state <= + irq_state == 2'b00 ? 2'b01 : + irq_state == 2'b01 ? 2'b10 : 2'b00; + latched_compr <= latched_compr; + if (ENABLE_IRQ_QREGS) + latched_rd <= irqregs_offset | irq_state[0]; + else + latched_rd <= irq_state[0] ? 4 : 3; + end else + if (ENABLE_IRQ && (decoder_trigger || do_waitirq) && instr_waitirq) begin + if (irq_pending) begin + latched_store <= 1; + reg_out <= irq_pending; + reg_next_pc <= current_pc + (compressed_instr ? 2 : 4); + mem_do_rinst <= 1; + end else + do_waitirq <= 1; + end else + if (decoder_trigger) begin + `debug($display("-- %-0t", $time);) + irq_delay <= irq_active; + reg_next_pc <= current_pc + (compressed_instr ? 2 : 4); + if (ENABLE_TRACE) + latched_trace <= 1; + if (ENABLE_COUNTERS) begin + count_instr <= count_instr + 1; + if (!ENABLE_COUNTERS64) count_instr[63:32] <= 0; + end + if (instr_jal) begin + mem_do_rinst <= 1; + reg_next_pc <= current_pc + decoded_imm_j; + latched_branch <= 1; + end else begin + mem_do_rinst <= 0; + mem_do_prefetch <= !instr_jalr && !instr_retirq; + cpu_state <= cpu_state_ld_rs1; + end + end + end + + cpu_state_ld_rs1: begin + reg_op1 <= 'bx; + reg_op2 <= 'bx; + + (* parallel_case *) + case (1'b1) + (CATCH_ILLINSN || WITH_PCPI) && instr_trap: begin + if (WITH_PCPI) begin + `debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);) + reg_op1 <= cpuregs_rs1; + dbg_rs1val <= cpuregs_rs1; + dbg_rs1val_valid <= 1; + if (ENABLE_REGS_DUALPORT) begin + pcpi_valid <= 1; + `debug($display("LD_RS2: %2d 0x%08x", decoded_rs2, cpuregs_rs2);) + reg_sh <= cpuregs_rs2; + reg_op2 <= cpuregs_rs2; + dbg_rs2val <= cpuregs_rs2; + dbg_rs2val_valid <= 1; + if (pcpi_int_ready) begin + mem_do_rinst <= 1; + pcpi_valid <= 0; + reg_out <= pcpi_int_rd; + latched_store <= pcpi_int_wr; + cpu_state <= cpu_state_fetch; + end else + if (CATCH_ILLINSN && (pcpi_timeout || instr_ecall_ebreak)) begin + pcpi_valid <= 0; + `debug($display("EBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);) + if (ENABLE_IRQ && !irq_mask[irq_ebreak] && !irq_active) begin + next_irq_pending[irq_ebreak] = 1; + cpu_state <= cpu_state_fetch; + end else + cpu_state <= cpu_state_trap; + end + end else begin + cpu_state <= cpu_state_ld_rs2; + end + end else begin + `debug($display("EBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);) + if (ENABLE_IRQ && !irq_mask[irq_ebreak] && !irq_active) begin + next_irq_pending[irq_ebreak] = 1; + cpu_state <= cpu_state_fetch; + end else + cpu_state <= cpu_state_trap; + end + end + ENABLE_COUNTERS && is_rdcycle_rdcycleh_rdinstr_rdinstrh: begin + (* parallel_case, full_case *) + case (1'b1) + instr_rdcycle: + reg_out <= count_cycle[31:0]; + instr_rdcycleh && ENABLE_COUNTERS64: + reg_out <= count_cycle[63:32]; + instr_rdinstr: + reg_out <= count_instr[31:0]; + instr_rdinstrh && ENABLE_COUNTERS64: + reg_out <= count_instr[63:32]; + endcase + latched_store <= 1; + cpu_state <= cpu_state_fetch; + end + is_lui_auipc_jal: begin + reg_op1 <= instr_lui ? 0 : reg_pc; + reg_op2 <= decoded_imm; + if (TWO_CYCLE_ALU) + alu_wait <= 1; + else + mem_do_rinst <= mem_do_prefetch; + cpu_state <= cpu_state_exec; + end + ENABLE_IRQ && ENABLE_IRQ_QREGS && instr_getq: begin + `debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);) + reg_out <= cpuregs_rs1; + dbg_rs1val <= cpuregs_rs1; + dbg_rs1val_valid <= 1; + latched_store <= 1; + cpu_state <= cpu_state_fetch; + end + ENABLE_IRQ && ENABLE_IRQ_QREGS && instr_setq: begin + `debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);) + reg_out <= cpuregs_rs1; + dbg_rs1val <= cpuregs_rs1; + dbg_rs1val_valid <= 1; + latched_rd <= latched_rd | irqregs_offset; + latched_store <= 1; + cpu_state <= cpu_state_fetch; + end + ENABLE_IRQ && instr_retirq: begin + eoi <= 0; + irq_active <= 0; + latched_branch <= 1; + latched_store <= 1; + `debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);) + reg_out <= CATCH_MISALIGN ? (cpuregs_rs1 & 32'h fffffffe) : cpuregs_rs1; + dbg_rs1val <= cpuregs_rs1; + dbg_rs1val_valid <= 1; + cpu_state <= cpu_state_fetch; + end + ENABLE_IRQ && instr_maskirq: begin + latched_store <= 1; + reg_out <= irq_mask; + `debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);) + irq_mask <= cpuregs_rs1 | MASKED_IRQ; + dbg_rs1val <= cpuregs_rs1; + dbg_rs1val_valid <= 1; + cpu_state <= cpu_state_fetch; + end + ENABLE_IRQ && ENABLE_IRQ_TIMER && instr_timer: begin + latched_store <= 1; + reg_out <= timer; + `debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);) + timer <= cpuregs_rs1; + dbg_rs1val <= cpuregs_rs1; + dbg_rs1val_valid <= 1; + cpu_state <= cpu_state_fetch; + end + is_lb_lh_lw_lbu_lhu && !instr_trap: begin + `debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);) + reg_op1 <= cpuregs_rs1; + dbg_rs1val <= cpuregs_rs1; + dbg_rs1val_valid <= 1; + cpu_state <= cpu_state_ldmem; + mem_do_rinst <= 1; + end + is_slli_srli_srai && !BARREL_SHIFTER: begin + `debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);) + reg_op1 <= cpuregs_rs1; + dbg_rs1val <= cpuregs_rs1; + dbg_rs1val_valid <= 1; + reg_sh <= decoded_rs2; + cpu_state <= cpu_state_shift; + end + is_jalr_addi_slti_sltiu_xori_ori_andi, is_slli_srli_srai && BARREL_SHIFTER: begin + `debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);) + reg_op1 <= cpuregs_rs1; + dbg_rs1val <= cpuregs_rs1; + dbg_rs1val_valid <= 1; + reg_op2 <= is_slli_srli_srai && BARREL_SHIFTER ? decoded_rs2 : decoded_imm; + if (TWO_CYCLE_ALU) + alu_wait <= 1; + else + mem_do_rinst <= mem_do_prefetch; + cpu_state <= cpu_state_exec; + end + default: begin + `debug($display("LD_RS1: %2d 0x%08x", decoded_rs1, cpuregs_rs1);) + reg_op1 <= cpuregs_rs1; + dbg_rs1val <= cpuregs_rs1; + dbg_rs1val_valid <= 1; + if (ENABLE_REGS_DUALPORT) begin + `debug($display("LD_RS2: %2d 0x%08x", decoded_rs2, cpuregs_rs2);) + reg_sh <= cpuregs_rs2; + reg_op2 <= cpuregs_rs2; + dbg_rs2val <= cpuregs_rs2; + dbg_rs2val_valid <= 1; + (* parallel_case *) + case (1'b1) + is_sb_sh_sw: begin + cpu_state <= cpu_state_stmem; + mem_do_rinst <= 1; + end + is_sll_srl_sra && !BARREL_SHIFTER: begin + cpu_state <= cpu_state_shift; + end + default: begin + if (TWO_CYCLE_ALU || (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu)) begin + alu_wait_2 <= TWO_CYCLE_ALU && (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu); + alu_wait <= 1; + end else + mem_do_rinst <= mem_do_prefetch; + cpu_state <= cpu_state_exec; + end + endcase + end else + cpu_state <= cpu_state_ld_rs2; + end + endcase + end + + cpu_state_ld_rs2: begin + `debug($display("LD_RS2: %2d 0x%08x", decoded_rs2, cpuregs_rs2);) + reg_sh <= cpuregs_rs2; + reg_op2 <= cpuregs_rs2; + dbg_rs2val <= cpuregs_rs2; + dbg_rs2val_valid <= 1; + + (* parallel_case *) + case (1'b1) + WITH_PCPI && instr_trap: begin + pcpi_valid <= 1; + if (pcpi_int_ready) begin + mem_do_rinst <= 1; + pcpi_valid <= 0; + reg_out <= pcpi_int_rd; + latched_store <= pcpi_int_wr; + cpu_state <= cpu_state_fetch; + end else + if (CATCH_ILLINSN && (pcpi_timeout || instr_ecall_ebreak)) begin + pcpi_valid <= 0; + `debug($display("EBREAK OR UNSUPPORTED INSN AT 0x%08x", reg_pc);) + if (ENABLE_IRQ && !irq_mask[irq_ebreak] && !irq_active) begin + next_irq_pending[irq_ebreak] = 1; + cpu_state <= cpu_state_fetch; + end else + cpu_state <= cpu_state_trap; + end + end + is_sb_sh_sw: begin + cpu_state <= cpu_state_stmem; + mem_do_rinst <= 1; + end + is_sll_srl_sra && !BARREL_SHIFTER: begin + cpu_state <= cpu_state_shift; + end + default: begin + if (TWO_CYCLE_ALU || (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu)) begin + alu_wait_2 <= TWO_CYCLE_ALU && (TWO_CYCLE_COMPARE && is_beq_bne_blt_bge_bltu_bgeu); + alu_wait <= 1; + end else + mem_do_rinst <= mem_do_prefetch; + cpu_state <= cpu_state_exec; + end + endcase + end + + cpu_state_exec: begin + reg_out <= reg_pc + decoded_imm; + if ((TWO_CYCLE_ALU || TWO_CYCLE_COMPARE) && (alu_wait || alu_wait_2)) begin + mem_do_rinst <= mem_do_prefetch && !alu_wait_2; + alu_wait <= alu_wait_2; + end else + if (is_beq_bne_blt_bge_bltu_bgeu) begin + latched_rd <= 0; + latched_store <= TWO_CYCLE_COMPARE ? alu_out_0_q : alu_out_0; + latched_branch <= TWO_CYCLE_COMPARE ? alu_out_0_q : alu_out_0; + if (mem_done) + cpu_state <= cpu_state_fetch; + if (TWO_CYCLE_COMPARE ? alu_out_0_q : alu_out_0) begin + decoder_trigger <= 0; + set_mem_do_rinst = 1; + end + end else begin + latched_branch <= instr_jalr; + latched_store <= 1; + latched_stalu <= 1; + cpu_state <= cpu_state_fetch; + end + end + + cpu_state_shift: begin + latched_store <= 1; + if (reg_sh == 0) begin + reg_out <= reg_op1; + mem_do_rinst <= mem_do_prefetch; + cpu_state <= cpu_state_fetch; + end else if (TWO_STAGE_SHIFT && reg_sh >= 4) begin + (* parallel_case, full_case *) + case (1'b1) + instr_slli || instr_sll: reg_op1 <= reg_op1 << 4; + instr_srli || instr_srl: reg_op1 <= reg_op1 >> 4; + instr_srai || instr_sra: reg_op1 <= $signed(reg_op1) >>> 4; + endcase + reg_sh <= reg_sh - 4; + end else begin + (* parallel_case, full_case *) + case (1'b1) + instr_slli || instr_sll: reg_op1 <= reg_op1 << 1; + instr_srli || instr_srl: reg_op1 <= reg_op1 >> 1; + instr_srai || instr_sra: reg_op1 <= $signed(reg_op1) >>> 1; + endcase + reg_sh <= reg_sh - 1; + end + end + + cpu_state_stmem: begin + if (ENABLE_TRACE) + reg_out <= reg_op2; + if (!mem_do_prefetch || mem_done) begin + if (!mem_do_wdata) begin + (* parallel_case, full_case *) + case (1'b1) + instr_sb: mem_wordsize <= 2; + instr_sh: mem_wordsize <= 1; + instr_sw: mem_wordsize <= 0; + endcase + if (ENABLE_TRACE) begin + trace_valid <= 1; + trace_data <= (irq_active ? TRACE_IRQ : 0) | TRACE_ADDR | ((reg_op1 + decoded_imm) & 32'hffffffff); + end + reg_op1 <= reg_op1 + decoded_imm; + set_mem_do_wdata = 1; + end + if (!mem_do_prefetch && mem_done) begin + cpu_state <= cpu_state_fetch; + decoder_trigger <= 1; + decoder_pseudo_trigger <= 1; + end + end + end + + cpu_state_ldmem: begin + latched_store <= 1; + if (!mem_do_prefetch || mem_done) begin + if (!mem_do_rdata) begin + (* parallel_case, full_case *) + case (1'b1) + instr_lb || instr_lbu: mem_wordsize <= 2; + instr_lh || instr_lhu: mem_wordsize <= 1; + instr_lw: mem_wordsize <= 0; + endcase + latched_is_lu <= is_lbu_lhu_lw; + latched_is_lh <= instr_lh; + latched_is_lb <= instr_lb; + if (ENABLE_TRACE) begin + trace_valid <= 1; + trace_data <= (irq_active ? TRACE_IRQ : 0) | TRACE_ADDR | ((reg_op1 + decoded_imm) & 32'hffffffff); + end + reg_op1 <= reg_op1 + decoded_imm; + set_mem_do_rdata = 1; + end + if (!mem_do_prefetch && mem_done) begin + (* parallel_case, full_case *) + case (1'b1) + latched_is_lu: reg_out <= mem_rdata_word; + latched_is_lh: reg_out <= $signed(mem_rdata_word[15:0]); + latched_is_lb: reg_out <= $signed(mem_rdata_word[7:0]); + endcase + decoder_trigger <= 1; + decoder_pseudo_trigger <= 1; + cpu_state <= cpu_state_fetch; + end + end + end + endcase + + if (ENABLE_IRQ) begin + next_irq_pending = next_irq_pending | irq; + if(ENABLE_IRQ_TIMER && timer) + if (timer - 1 == 0) + next_irq_pending[irq_timer] = 1; + end + + if (CATCH_MISALIGN && resetn && (mem_do_rdata || mem_do_wdata)) begin + if (mem_wordsize == 0 && reg_op1[1:0] != 0) begin + `debug($display("MISALIGNED WORD: 0x%08x", reg_op1);) + if (ENABLE_IRQ && !irq_mask[irq_buserror] && !irq_active) begin + next_irq_pending[irq_buserror] = 1; + end else + cpu_state <= cpu_state_trap; + end + if (mem_wordsize == 1 && reg_op1[0] != 0) begin + `debug($display("MISALIGNED HALFWORD: 0x%08x", reg_op1);) + if (ENABLE_IRQ && !irq_mask[irq_buserror] && !irq_active) begin + next_irq_pending[irq_buserror] = 1; + end else + cpu_state <= cpu_state_trap; + end + end + if (CATCH_MISALIGN && resetn && mem_do_rinst && (COMPRESSED_ISA ? reg_pc[0] : |reg_pc[1:0])) begin + `debug($display("MISALIGNED INSTRUCTION: 0x%08x", reg_pc);) + if (ENABLE_IRQ && !irq_mask[irq_buserror] && !irq_active) begin + next_irq_pending[irq_buserror] = 1; + end else + cpu_state <= cpu_state_trap; + end + if (!CATCH_ILLINSN && decoder_trigger_q && !decoder_pseudo_trigger_q && instr_ecall_ebreak) begin + cpu_state <= cpu_state_trap; + end + + if (!resetn || mem_done) begin + mem_do_prefetch <= 0; + mem_do_rinst <= 0; + mem_do_rdata <= 0; + mem_do_wdata <= 0; + end + + if (set_mem_do_rinst) + mem_do_rinst <= 1; + if (set_mem_do_rdata) + mem_do_rdata <= 1; + if (set_mem_do_wdata) + mem_do_wdata <= 1; + + irq_pending <= next_irq_pending & ~MASKED_IRQ; + + if (!CATCH_MISALIGN) begin + if (COMPRESSED_ISA) begin + reg_pc[0] <= 0; + reg_next_pc[0] <= 0; + end else begin + reg_pc[1:0] <= 0; + reg_next_pc[1:0] <= 0; + end + end + current_pc = 'bx; + end + +`ifdef RISCV_FORMAL + reg dbg_irq_call; + reg dbg_irq_enter; + reg [31:0] dbg_irq_ret; + always @(posedge clk) begin + rvfi_valid <= resetn && (launch_next_insn || trap) && dbg_valid_insn; + rvfi_order <= resetn ? rvfi_order + rvfi_valid : 0; + + rvfi_insn <= dbg_insn_opcode; + rvfi_rs1_addr <= dbg_rs1val_valid ? dbg_insn_rs1 : 0; + rvfi_rs2_addr <= dbg_rs2val_valid ? dbg_insn_rs2 : 0; + rvfi_pc_rdata <= dbg_insn_addr; + rvfi_rs1_rdata <= dbg_rs1val_valid ? dbg_rs1val : 0; + rvfi_rs2_rdata <= dbg_rs2val_valid ? dbg_rs2val : 0; + rvfi_trap <= trap; + rvfi_halt <= trap; + rvfi_intr <= dbg_irq_enter; + rvfi_mode <= 3; + rvfi_ixl <= 1; + + if (!resetn) begin + dbg_irq_call <= 0; + dbg_irq_enter <= 0; + end else + if (rvfi_valid) begin + dbg_irq_call <= 0; + dbg_irq_enter <= dbg_irq_call; + end else + if (irq_state == 1) begin + dbg_irq_call <= 1; + dbg_irq_ret <= next_pc; + end + + if (!resetn) begin + rvfi_rd_addr <= 0; + rvfi_rd_wdata <= 0; + end else + if (cpuregs_write && !irq_state) begin +`ifdef PICORV32_TESTBUG_003 + rvfi_rd_addr <= latched_rd ^ 1; +`else + rvfi_rd_addr <= latched_rd; +`endif +`ifdef PICORV32_TESTBUG_004 + rvfi_rd_wdata <= latched_rd ? cpuregs_wrdata ^ 1 : 0; +`else + rvfi_rd_wdata <= latched_rd ? cpuregs_wrdata : 0; +`endif + end else + if (rvfi_valid) begin + rvfi_rd_addr <= 0; + rvfi_rd_wdata <= 0; + end + + casez (dbg_insn_opcode) + 32'b 0000000_?????_000??_???_?????_0001011: begin // getq + rvfi_rs1_addr <= 0; + rvfi_rs1_rdata <= 0; + end + 32'b 0000001_?????_?????_???_000??_0001011: begin // setq + rvfi_rd_addr <= 0; + rvfi_rd_wdata <= 0; + end + 32'b 0000010_?????_00000_???_00000_0001011: begin // retirq + rvfi_rs1_addr <= 0; + rvfi_rs1_rdata <= 0; + end + endcase + + if (!dbg_irq_call) begin + if (dbg_mem_instr) begin + rvfi_mem_addr <= 0; + rvfi_mem_rmask <= 0; + rvfi_mem_wmask <= 0; + rvfi_mem_rdata <= 0; + rvfi_mem_wdata <= 0; + end else + if (dbg_mem_valid && dbg_mem_ready) begin + rvfi_mem_addr <= dbg_mem_addr; + rvfi_mem_rmask <= dbg_mem_wstrb ? 0 : ~0; + rvfi_mem_wmask <= dbg_mem_wstrb; + rvfi_mem_rdata <= dbg_mem_rdata; + rvfi_mem_wdata <= dbg_mem_wdata; + end + end + end + + always @* begin +`ifdef PICORV32_TESTBUG_005 + rvfi_pc_wdata = (dbg_irq_call ? dbg_irq_ret : dbg_insn_addr) ^ 4; +`else + rvfi_pc_wdata = dbg_irq_call ? dbg_irq_ret : dbg_insn_addr; +`endif + + rvfi_csr_mcycle_rmask = 0; + rvfi_csr_mcycle_wmask = 0; + rvfi_csr_mcycle_rdata = 0; + rvfi_csr_mcycle_wdata = 0; + + rvfi_csr_minstret_rmask = 0; + rvfi_csr_minstret_wmask = 0; + rvfi_csr_minstret_rdata = 0; + rvfi_csr_minstret_wdata = 0; + + if (rvfi_valid && rvfi_insn[6:0] == 7'b 1110011 && rvfi_insn[13:12] == 3'b010) begin + if (rvfi_insn[31:20] == 12'h C00) begin + rvfi_csr_mcycle_rmask = 64'h 0000_0000_FFFF_FFFF; + rvfi_csr_mcycle_rdata = {32'h 0000_0000, rvfi_rd_wdata}; + end + if (rvfi_insn[31:20] == 12'h C80) begin + rvfi_csr_mcycle_rmask = 64'h FFFF_FFFF_0000_0000; + rvfi_csr_mcycle_rdata = {rvfi_rd_wdata, 32'h 0000_0000}; + end + if (rvfi_insn[31:20] == 12'h C02) begin + rvfi_csr_minstret_rmask = 64'h 0000_0000_FFFF_FFFF; + rvfi_csr_minstret_rdata = {32'h 0000_0000, rvfi_rd_wdata}; + end + if (rvfi_insn[31:20] == 12'h C82) begin + rvfi_csr_minstret_rmask = 64'h FFFF_FFFF_0000_0000; + rvfi_csr_minstret_rdata = {rvfi_rd_wdata, 32'h 0000_0000}; + end + end + end +`endif + + // Formal Verification +`ifdef FORMAL + reg [3:0] last_mem_nowait; + always @(posedge clk) + last_mem_nowait <= {last_mem_nowait, mem_ready || !mem_valid}; + + // stall the memory interface for max 4 cycles + restrict property (|last_mem_nowait || mem_ready || !mem_valid); + + // resetn low in first cycle, after that resetn high + restrict property (resetn != $initstate); + + // this just makes it much easier to read traces. uncomment as needed. + // assume property (mem_valid || !mem_ready); + + reg ok; + always @* begin + if (resetn) begin + // instruction fetches are read-only + if (mem_valid && mem_instr) + assert (mem_wstrb == 0); + + // cpu_state must be valid + ok = 0; + if (cpu_state == cpu_state_trap) ok = 1; + if (cpu_state == cpu_state_fetch) ok = 1; + if (cpu_state == cpu_state_ld_rs1) ok = 1; + if (cpu_state == cpu_state_ld_rs2) ok = !ENABLE_REGS_DUALPORT; + if (cpu_state == cpu_state_exec) ok = 1; + if (cpu_state == cpu_state_shift) ok = 1; + if (cpu_state == cpu_state_stmem) ok = 1; + if (cpu_state == cpu_state_ldmem) ok = 1; + assert (ok); + end + end + + reg last_mem_la_read = 0; + reg last_mem_la_write = 0; + reg [31:0] last_mem_la_addr; + reg [31:0] last_mem_la_wdata; + reg [3:0] last_mem_la_wstrb = 0; + + always @(posedge clk) begin + last_mem_la_read <= mem_la_read; + last_mem_la_write <= mem_la_write; + last_mem_la_addr <= mem_la_addr; + last_mem_la_wdata <= mem_la_wdata; + last_mem_la_wstrb <= mem_la_wstrb; + + if (last_mem_la_read) begin + assert(mem_valid); + assert(mem_addr == last_mem_la_addr); + assert(mem_wstrb == 0); + end + if (last_mem_la_write) begin + assert(mem_valid); + assert(mem_addr == last_mem_la_addr); + assert(mem_wdata == last_mem_la_wdata); + assert(mem_wstrb == last_mem_la_wstrb); + end + if (mem_la_read || mem_la_write) begin + assert(!mem_valid || mem_ready); + end + end +`endif +endmodule + +// This is a simple example implementation of PICORV32_REGS. +// Use the PICORV32_REGS mechanism if you want to use custom +// memory resources to implement the processor register file. +// Note that your implementation must match the requirements of +// the PicoRV32 configuration. (e.g. QREGS, etc) +module picorv32_regs ( + input clk, wen, + input [5:0] waddr, + input [5:0] raddr1, + input [5:0] raddr2, + input [31:0] wdata, + output [31:0] rdata1, + output [31:0] rdata2 +); + reg [31:0] regs [0:30]; + + always @(posedge clk) + if (wen) regs[~waddr[4:0]] <= wdata; + + assign rdata1 = regs[~raddr1[4:0]]; + assign rdata2 = regs[~raddr2[4:0]]; +endmodule + + +/*************************************************************** + * picorv32_pcpi_mul + ***************************************************************/ + +module picorv32_pcpi_mul #( + parameter STEPS_AT_ONCE = 1, + parameter CARRY_CHAIN = 4 +) ( + input clk, resetn, + + input pcpi_valid, + input [31:0] pcpi_insn, + input [31:0] pcpi_rs1, + input [31:0] pcpi_rs2, + output reg pcpi_wr, + output reg [31:0] pcpi_rd, + output reg pcpi_wait, + output reg pcpi_ready +); + reg instr_mul, instr_mulh, instr_mulhsu, instr_mulhu; + wire instr_any_mul = |{instr_mul, instr_mulh, instr_mulhsu, instr_mulhu}; + wire instr_any_mulh = |{instr_mulh, instr_mulhsu, instr_mulhu}; + wire instr_rs1_signed = |{instr_mulh, instr_mulhsu}; + wire instr_rs2_signed = |{instr_mulh}; + + reg pcpi_wait_q; + wire mul_start = pcpi_wait && !pcpi_wait_q; + + always @(posedge clk) begin + instr_mul <= 0; + instr_mulh <= 0; + instr_mulhsu <= 0; + instr_mulhu <= 0; + + if (resetn && pcpi_valid && pcpi_insn[6:0] == 7'b0110011 && pcpi_insn[31:25] == 7'b0000001) begin + case (pcpi_insn[14:12]) + 3'b000: instr_mul <= 1; + 3'b001: instr_mulh <= 1; + 3'b010: instr_mulhsu <= 1; + 3'b011: instr_mulhu <= 1; + endcase + end + + pcpi_wait <= instr_any_mul; + pcpi_wait_q <= pcpi_wait; + end + + reg [63:0] rs1, rs2, rd, rdx; + reg [63:0] next_rs1, next_rs2, this_rs2; + reg [63:0] next_rd, next_rdx, next_rdt; + reg [6:0] mul_counter; + reg mul_waiting; + reg mul_finish; + integer i, j; + + // carry save accumulator + always @* begin + next_rd = rd; + next_rdx = rdx; + next_rs1 = rs1; + next_rs2 = rs2; + + for (i = 0; i < STEPS_AT_ONCE; i=i+1) begin + this_rs2 = next_rs1[0] ? next_rs2 : 0; + if (CARRY_CHAIN == 0) begin + next_rdt = next_rd ^ next_rdx ^ this_rs2; + next_rdx = ((next_rd & next_rdx) | (next_rd & this_rs2) | (next_rdx & this_rs2)) << 1; + next_rd = next_rdt; + end else begin + next_rdt = 0; + for (j = 0; j < 64; j = j + CARRY_CHAIN) + {next_rdt[j+CARRY_CHAIN-1], next_rd[j +: CARRY_CHAIN]} = + next_rd[j +: CARRY_CHAIN] + next_rdx[j +: CARRY_CHAIN] + this_rs2[j +: CARRY_CHAIN]; + next_rdx = next_rdt << 1; + end + next_rs1 = next_rs1 >> 1; + next_rs2 = next_rs2 << 1; + end + end + + always @(posedge clk) begin + mul_finish <= 0; + if (!resetn) begin + mul_waiting <= 1; + end else + if (mul_waiting) begin + if (instr_rs1_signed) + rs1 <= $signed(pcpi_rs1); + else + rs1 <= $unsigned(pcpi_rs1); + + if (instr_rs2_signed) + rs2 <= $signed(pcpi_rs2); + else + rs2 <= $unsigned(pcpi_rs2); + + rd <= 0; + rdx <= 0; + mul_counter <= (instr_any_mulh ? 63 - STEPS_AT_ONCE : 31 - STEPS_AT_ONCE); + mul_waiting <= !mul_start; + end else begin + rd <= next_rd; + rdx <= next_rdx; + rs1 <= next_rs1; + rs2 <= next_rs2; + + mul_counter <= mul_counter - STEPS_AT_ONCE; + if (mul_counter[6]) begin + mul_finish <= 1; + mul_waiting <= 1; + end + end + end + + always @(posedge clk) begin + pcpi_wr <= 0; + pcpi_ready <= 0; + if (mul_finish && resetn) begin + pcpi_wr <= 1; + pcpi_ready <= 1; + pcpi_rd <= instr_any_mulh ? rd >> 32 : rd; + end + end +endmodule + +module picorv32_pcpi_fast_mul #( + parameter EXTRA_MUL_FFS = 0, + parameter EXTRA_INSN_FFS = 0, + parameter MUL_CLKGATE = 0 +) ( + input clk, resetn, + + input pcpi_valid, + input [31:0] pcpi_insn, + input [31:0] pcpi_rs1, + input [31:0] pcpi_rs2, + output pcpi_wr, + output [31:0] pcpi_rd, + output pcpi_wait, + output pcpi_ready +); + reg instr_mul, instr_mulh, instr_mulhsu, instr_mulhu; + wire instr_any_mul = |{instr_mul, instr_mulh, instr_mulhsu, instr_mulhu}; + wire instr_any_mulh = |{instr_mulh, instr_mulhsu, instr_mulhu}; + wire instr_rs1_signed = |{instr_mulh, instr_mulhsu}; + wire instr_rs2_signed = |{instr_mulh}; + + reg shift_out; + reg [3:0] active; + reg [32:0] rs1, rs2, rs1_q, rs2_q; + reg [63:0] rd, rd_q; + + wire pcpi_insn_valid = pcpi_valid && pcpi_insn[6:0] == 7'b0110011 && pcpi_insn[31:25] == 7'b0000001; + reg pcpi_insn_valid_q; + + always @* begin + instr_mul = 0; + instr_mulh = 0; + instr_mulhsu = 0; + instr_mulhu = 0; + + if (resetn && (EXTRA_INSN_FFS ? pcpi_insn_valid_q : pcpi_insn_valid)) begin + case (pcpi_insn[14:12]) + 3'b000: instr_mul = 1; + 3'b001: instr_mulh = 1; + 3'b010: instr_mulhsu = 1; + 3'b011: instr_mulhu = 1; + endcase + end + end + + always @(posedge clk) begin + pcpi_insn_valid_q <= pcpi_insn_valid; + if (!MUL_CLKGATE || active[0]) begin + rs1_q <= rs1; + rs2_q <= rs2; + end + if (!MUL_CLKGATE || active[1]) begin + rd <= $signed(EXTRA_MUL_FFS ? rs1_q : rs1) * $signed(EXTRA_MUL_FFS ? rs2_q : rs2); + end + if (!MUL_CLKGATE || active[2]) begin + rd_q <= rd; + end + end + + always @(posedge clk) begin + if (instr_any_mul && !(EXTRA_MUL_FFS ? active[3:0] : active[1:0])) begin + if (instr_rs1_signed) + rs1 <= $signed(pcpi_rs1); + else + rs1 <= $unsigned(pcpi_rs1); + + if (instr_rs2_signed) + rs2 <= $signed(pcpi_rs2); + else + rs2 <= $unsigned(pcpi_rs2); + active[0] <= 1; + end else begin + active[0] <= 0; + end + + active[3:1] <= active; + shift_out <= instr_any_mulh; + + if (!resetn) + active <= 0; + end + + assign pcpi_wr = active[EXTRA_MUL_FFS ? 3 : 1]; + assign pcpi_wait = 0; + assign pcpi_ready = active[EXTRA_MUL_FFS ? 3 : 1]; +`ifdef RISCV_FORMAL_ALTOPS + assign pcpi_rd = + instr_mul ? (pcpi_rs1 + pcpi_rs2) ^ 32'h5876063e : + instr_mulh ? (pcpi_rs1 + pcpi_rs2) ^ 32'hf6583fb7 : + instr_mulhsu ? (pcpi_rs1 - pcpi_rs2) ^ 32'hecfbe137 : + instr_mulhu ? (pcpi_rs1 + pcpi_rs2) ^ 32'h949ce5e8 : 1'bx; +`else + assign pcpi_rd = shift_out ? (EXTRA_MUL_FFS ? rd_q : rd) >> 32 : (EXTRA_MUL_FFS ? rd_q : rd); +`endif +endmodule + + +/*************************************************************** + * picorv32_pcpi_div + ***************************************************************/ + +module picorv32_pcpi_div ( + input clk, resetn, + + input pcpi_valid, + input [31:0] pcpi_insn, + input [31:0] pcpi_rs1, + input [31:0] pcpi_rs2, + output reg pcpi_wr, + output reg [31:0] pcpi_rd, + output reg pcpi_wait, + output reg pcpi_ready +); + reg instr_div, instr_divu, instr_rem, instr_remu; + wire instr_any_div_rem = |{instr_div, instr_divu, instr_rem, instr_remu}; + + reg pcpi_wait_q; + wire start = pcpi_wait && !pcpi_wait_q; + + always @(posedge clk) begin + instr_div <= 0; + instr_divu <= 0; + instr_rem <= 0; + instr_remu <= 0; + + if (resetn && pcpi_valid && !pcpi_ready && pcpi_insn[6:0] == 7'b0110011 && pcpi_insn[31:25] == 7'b0000001) begin + case (pcpi_insn[14:12]) + 3'b100: instr_div <= 1; + 3'b101: instr_divu <= 1; + 3'b110: instr_rem <= 1; + 3'b111: instr_remu <= 1; + endcase + end + + pcpi_wait <= instr_any_div_rem && resetn; + pcpi_wait_q <= pcpi_wait && resetn; + end + + reg [31:0] dividend; + reg [62:0] divisor; + reg [31:0] quotient; + reg [31:0] quotient_msk; + reg running; + reg outsign; + + always @(posedge clk) begin + pcpi_ready <= 0; + pcpi_wr <= 0; + pcpi_rd <= 'bx; + + if (!resetn) begin + running <= 0; + end else + if (start) begin + running <= 1; + dividend <= (instr_div || instr_rem) && pcpi_rs1[31] ? -pcpi_rs1 : pcpi_rs1; + divisor <= ((instr_div || instr_rem) && pcpi_rs2[31] ? -pcpi_rs2 : pcpi_rs2) << 31; + outsign <= (instr_div && (pcpi_rs1[31] != pcpi_rs2[31]) && |pcpi_rs2) || (instr_rem && pcpi_rs1[31]); + quotient <= 0; + quotient_msk <= 1 << 31; + end else + if (!quotient_msk && running) begin + running <= 0; + pcpi_ready <= 1; + pcpi_wr <= 1; +`ifdef RISCV_FORMAL_ALTOPS + case (1) + instr_div: pcpi_rd <= (pcpi_rs1 - pcpi_rs2) ^ 32'h7f8529ec; + instr_divu: pcpi_rd <= (pcpi_rs1 - pcpi_rs2) ^ 32'h10e8fd70; + instr_rem: pcpi_rd <= (pcpi_rs1 - pcpi_rs2) ^ 32'h8da68fa5; + instr_remu: pcpi_rd <= (pcpi_rs1 - pcpi_rs2) ^ 32'h3138d0e1; + endcase +`else + if (instr_div || instr_divu) + pcpi_rd <= outsign ? -quotient : quotient; + else + pcpi_rd <= outsign ? -dividend : dividend; +`endif + end else begin + if (divisor <= dividend) begin + dividend <= dividend - divisor; + quotient <= quotient | quotient_msk; + end + divisor <= divisor >> 1; +`ifdef RISCV_FORMAL_ALTOPS + quotient_msk <= quotient_msk >> 5; +`else + quotient_msk <= quotient_msk >> 1; +`endif + end + end +endmodule + + +/*************************************************************** + * picorv32_axi + ***************************************************************/ + +module picorv32_axi #( + parameter [ 0:0] ENABLE_COUNTERS = 1, + parameter [ 0:0] ENABLE_COUNTERS64 = 1, + parameter [ 0:0] ENABLE_REGS_16_31 = 1, + parameter [ 0:0] ENABLE_REGS_DUALPORT = 1, + parameter [ 0:0] TWO_STAGE_SHIFT = 1, + parameter [ 0:0] BARREL_SHIFTER = 0, + parameter [ 0:0] TWO_CYCLE_COMPARE = 0, + parameter [ 0:0] TWO_CYCLE_ALU = 0, + parameter [ 0:0] COMPRESSED_ISA = 0, + parameter [ 0:0] CATCH_MISALIGN = 1, + parameter [ 0:0] CATCH_ILLINSN = 1, + parameter [ 0:0] ENABLE_PCPI = 0, + parameter [ 0:0] ENABLE_MUL = 0, + parameter [ 0:0] ENABLE_FAST_MUL = 0, + parameter [ 0:0] ENABLE_DIV = 0, + parameter [ 0:0] ENABLE_IRQ = 0, + parameter [ 0:0] ENABLE_IRQ_QREGS = 1, + parameter [ 0:0] ENABLE_IRQ_TIMER = 1, + parameter [ 0:0] ENABLE_TRACE = 0, + parameter [ 0:0] REGS_INIT_ZERO = 0, + parameter [31:0] MASKED_IRQ = 32'h 0000_0000, + parameter [31:0] LATCHED_IRQ = 32'h ffff_ffff, + parameter [31:0] PROGADDR_RESET = 32'h 0000_0000, + parameter [31:0] PROGADDR_IRQ = 32'h 0000_0010, + parameter [31:0] STACKADDR = 32'h ffff_ffff +) ( + input clk, resetn, + output trap, + + // AXI4-lite master memory interface + + output mem_axi_awvalid, + input mem_axi_awready, + output [31:0] mem_axi_awaddr, + output [ 2:0] mem_axi_awprot, + + output mem_axi_wvalid, + input mem_axi_wready, + output [31:0] mem_axi_wdata, + output [ 3:0] mem_axi_wstrb, + + input mem_axi_bvalid, + output mem_axi_bready, + + output mem_axi_arvalid, + input mem_axi_arready, + output [31:0] mem_axi_araddr, + output [ 2:0] mem_axi_arprot, + + input mem_axi_rvalid, + output mem_axi_rready, + input [31:0] mem_axi_rdata, + + // Pico Co-Processor Interface (PCPI) + output pcpi_valid, + output [31:0] pcpi_insn, + output [31:0] pcpi_rs1, + output [31:0] pcpi_rs2, + input pcpi_wr, + input [31:0] pcpi_rd, + input pcpi_wait, + input pcpi_ready, + + // IRQ interface + input [31:0] irq, + output [31:0] eoi, + +`ifdef RISCV_FORMAL + output rvfi_valid, + output [63:0] rvfi_order, + output [31:0] rvfi_insn, + output rvfi_trap, + output rvfi_halt, + output rvfi_intr, + output [ 4:0] rvfi_rs1_addr, + output [ 4:0] rvfi_rs2_addr, + output [31:0] rvfi_rs1_rdata, + output [31:0] rvfi_rs2_rdata, + output [ 4:0] rvfi_rd_addr, + output [31:0] rvfi_rd_wdata, + output [31:0] rvfi_pc_rdata, + output [31:0] rvfi_pc_wdata, + output [31:0] rvfi_mem_addr, + output [ 3:0] rvfi_mem_rmask, + output [ 3:0] rvfi_mem_wmask, + output [31:0] rvfi_mem_rdata, + output [31:0] rvfi_mem_wdata, +`endif + + // Trace Interface + output trace_valid, + output [35:0] trace_data +); + wire mem_valid; + wire [31:0] mem_addr; + wire [31:0] mem_wdata; + wire [ 3:0] mem_wstrb; + wire mem_instr; + wire mem_ready; + wire [31:0] mem_rdata; + + picorv32_axi_adapter axi_adapter ( + .clk (clk ), + .resetn (resetn ), + .mem_axi_awvalid(mem_axi_awvalid), + .mem_axi_awready(mem_axi_awready), + .mem_axi_awaddr (mem_axi_awaddr ), + .mem_axi_awprot (mem_axi_awprot ), + .mem_axi_wvalid (mem_axi_wvalid ), + .mem_axi_wready (mem_axi_wready ), + .mem_axi_wdata (mem_axi_wdata ), + .mem_axi_wstrb (mem_axi_wstrb ), + .mem_axi_bvalid (mem_axi_bvalid ), + .mem_axi_bready (mem_axi_bready ), + .mem_axi_arvalid(mem_axi_arvalid), + .mem_axi_arready(mem_axi_arready), + .mem_axi_araddr (mem_axi_araddr ), + .mem_axi_arprot (mem_axi_arprot ), + .mem_axi_rvalid (mem_axi_rvalid ), + .mem_axi_rready (mem_axi_rready ), + .mem_axi_rdata (mem_axi_rdata ), + .mem_valid (mem_valid ), + .mem_instr (mem_instr ), + .mem_ready (mem_ready ), + .mem_addr (mem_addr ), + .mem_wdata (mem_wdata ), + .mem_wstrb (mem_wstrb ), + .mem_rdata (mem_rdata ) + ); + + picorv32 #( + .ENABLE_COUNTERS (ENABLE_COUNTERS ), + .ENABLE_COUNTERS64 (ENABLE_COUNTERS64 ), + .ENABLE_REGS_16_31 (ENABLE_REGS_16_31 ), + .ENABLE_REGS_DUALPORT(ENABLE_REGS_DUALPORT), + .TWO_STAGE_SHIFT (TWO_STAGE_SHIFT ), + .BARREL_SHIFTER (BARREL_SHIFTER ), + .TWO_CYCLE_COMPARE (TWO_CYCLE_COMPARE ), + .TWO_CYCLE_ALU (TWO_CYCLE_ALU ), + .COMPRESSED_ISA (COMPRESSED_ISA ), + .CATCH_MISALIGN (CATCH_MISALIGN ), + .CATCH_ILLINSN (CATCH_ILLINSN ), + .ENABLE_PCPI (ENABLE_PCPI ), + .ENABLE_MUL (ENABLE_MUL ), + .ENABLE_FAST_MUL (ENABLE_FAST_MUL ), + .ENABLE_DIV (ENABLE_DIV ), + .ENABLE_IRQ (ENABLE_IRQ ), + .ENABLE_IRQ_QREGS (ENABLE_IRQ_QREGS ), + .ENABLE_IRQ_TIMER (ENABLE_IRQ_TIMER ), + .ENABLE_TRACE (ENABLE_TRACE ), + .REGS_INIT_ZERO (REGS_INIT_ZERO ), + .MASKED_IRQ (MASKED_IRQ ), + .LATCHED_IRQ (LATCHED_IRQ ), + .PROGADDR_RESET (PROGADDR_RESET ), + .PROGADDR_IRQ (PROGADDR_IRQ ), + .STACKADDR (STACKADDR ) + ) picorv32_core ( + .clk (clk ), + .resetn (resetn), + .trap (trap ), + + .mem_valid(mem_valid), + .mem_addr (mem_addr ), + .mem_wdata(mem_wdata), + .mem_wstrb(mem_wstrb), + .mem_instr(mem_instr), + .mem_ready(mem_ready), + .mem_rdata(mem_rdata), + + .pcpi_valid(pcpi_valid), + .pcpi_insn (pcpi_insn ), + .pcpi_rs1 (pcpi_rs1 ), + .pcpi_rs2 (pcpi_rs2 ), + .pcpi_wr (pcpi_wr ), + .pcpi_rd (pcpi_rd ), + .pcpi_wait (pcpi_wait ), + .pcpi_ready(pcpi_ready), + + .irq(irq), + .eoi(eoi), + +`ifdef RISCV_FORMAL + .rvfi_valid (rvfi_valid ), + .rvfi_order (rvfi_order ), + .rvfi_insn (rvfi_insn ), + .rvfi_trap (rvfi_trap ), + .rvfi_halt (rvfi_halt ), + .rvfi_intr (rvfi_intr ), + .rvfi_rs1_addr (rvfi_rs1_addr ), + .rvfi_rs2_addr (rvfi_rs2_addr ), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_rd_addr (rvfi_rd_addr ), + .rvfi_rd_wdata (rvfi_rd_wdata ), + .rvfi_pc_rdata (rvfi_pc_rdata ), + .rvfi_pc_wdata (rvfi_pc_wdata ), + .rvfi_mem_addr (rvfi_mem_addr ), + .rvfi_mem_rmask(rvfi_mem_rmask), + .rvfi_mem_wmask(rvfi_mem_wmask), + .rvfi_mem_rdata(rvfi_mem_rdata), + .rvfi_mem_wdata(rvfi_mem_wdata), +`endif + + .trace_valid(trace_valid), + .trace_data (trace_data) + ); +endmodule + + +/*************************************************************** + * picorv32_axi_adapter + ***************************************************************/ + +module picorv32_axi_adapter ( + input clk, resetn, + + // AXI4-lite master memory interface + + output mem_axi_awvalid, + input mem_axi_awready, + output [31:0] mem_axi_awaddr, + output [ 2:0] mem_axi_awprot, + + output mem_axi_wvalid, + input mem_axi_wready, + output [31:0] mem_axi_wdata, + output [ 3:0] mem_axi_wstrb, + + input mem_axi_bvalid, + output mem_axi_bready, + + output mem_axi_arvalid, + input mem_axi_arready, + output [31:0] mem_axi_araddr, + output [ 2:0] mem_axi_arprot, + + input mem_axi_rvalid, + output mem_axi_rready, + input [31:0] mem_axi_rdata, + + // Native PicoRV32 memory interface + + input mem_valid, + input mem_instr, + output mem_ready, + input [31:0] mem_addr, + input [31:0] mem_wdata, + input [ 3:0] mem_wstrb, + output [31:0] mem_rdata +); + reg ack_awvalid; + reg ack_arvalid; + reg ack_wvalid; + reg xfer_done; + + assign mem_axi_awvalid = mem_valid && |mem_wstrb && !ack_awvalid; + assign mem_axi_awaddr = mem_addr; + assign mem_axi_awprot = 0; + + assign mem_axi_arvalid = mem_valid && !mem_wstrb && !ack_arvalid; + assign mem_axi_araddr = mem_addr; + assign mem_axi_arprot = mem_instr ? 3'b100 : 3'b000; + + assign mem_axi_wvalid = mem_valid && |mem_wstrb && !ack_wvalid; + assign mem_axi_wdata = mem_wdata; + assign mem_axi_wstrb = mem_wstrb; + + assign mem_ready = mem_axi_bvalid || mem_axi_rvalid; + assign mem_axi_bready = mem_valid && |mem_wstrb; + assign mem_axi_rready = mem_valid && !mem_wstrb; + assign mem_rdata = mem_axi_rdata; + + always @(posedge clk) begin + if (!resetn) begin + ack_awvalid <= 0; + end else begin + xfer_done <= mem_valid && mem_ready; + if (mem_axi_awready && mem_axi_awvalid) + ack_awvalid <= 1; + if (mem_axi_arready && mem_axi_arvalid) + ack_arvalid <= 1; + if (mem_axi_wready && mem_axi_wvalid) + ack_wvalid <= 1; + if (xfer_done || !mem_valid) begin + ack_awvalid <= 0; + ack_arvalid <= 0; + ack_wvalid <= 0; + end + end + end +endmodule + + +/*************************************************************** + * picorv32_wb + ***************************************************************/ + +module picorv32_wb #( + parameter [ 0:0] ENABLE_COUNTERS = 1, + parameter [ 0:0] ENABLE_COUNTERS64 = 1, + parameter [ 0:0] ENABLE_REGS_16_31 = 1, + parameter [ 0:0] ENABLE_REGS_DUALPORT = 1, + parameter [ 0:0] TWO_STAGE_SHIFT = 1, + parameter [ 0:0] BARREL_SHIFTER = 0, + parameter [ 0:0] TWO_CYCLE_COMPARE = 0, + parameter [ 0:0] TWO_CYCLE_ALU = 0, + parameter [ 0:0] COMPRESSED_ISA = 0, + parameter [ 0:0] CATCH_MISALIGN = 1, + parameter [ 0:0] CATCH_ILLINSN = 1, + parameter [ 0:0] ENABLE_PCPI = 0, + parameter [ 0:0] ENABLE_MUL = 0, + parameter [ 0:0] ENABLE_FAST_MUL = 0, + parameter [ 0:0] ENABLE_DIV = 0, + parameter [ 0:0] ENABLE_IRQ = 0, + parameter [ 0:0] ENABLE_IRQ_QREGS = 1, + parameter [ 0:0] ENABLE_IRQ_TIMER = 1, + parameter [ 0:0] ENABLE_TRACE = 0, + parameter [ 0:0] REGS_INIT_ZERO = 0, + parameter [31:0] MASKED_IRQ = 32'h 0000_0000, + parameter [31:0] LATCHED_IRQ = 32'h ffff_ffff, + parameter [31:0] PROGADDR_RESET = 32'h 0000_0000, + parameter [31:0] PROGADDR_IRQ = 32'h 0000_0010, + parameter [31:0] STACKADDR = 32'h ffff_ffff +) ( + output trap, + + // Wishbone interfaces + input wb_rst_i, + input wb_clk_i, + + output reg [31:0] wbm_adr_o, + output reg [31:0] wbm_dat_o, + input [31:0] wbm_dat_i, + output reg wbm_we_o, + output reg [3:0] wbm_sel_o, + output reg wbm_stb_o, + input wbm_ack_i, + output reg wbm_cyc_o, + + // Pico Co-Processor Interface (PCPI) + output pcpi_valid, + output [31:0] pcpi_insn, + output [31:0] pcpi_rs1, + output [31:0] pcpi_rs2, + input pcpi_wr, + input [31:0] pcpi_rd, + input pcpi_wait, + input pcpi_ready, + + // IRQ interface + input [31:0] irq, + output [31:0] eoi, + +`ifdef RISCV_FORMAL + output rvfi_valid, + output [63:0] rvfi_order, + output [31:0] rvfi_insn, + output rvfi_trap, + output rvfi_halt, + output rvfi_intr, + output [ 4:0] rvfi_rs1_addr, + output [ 4:0] rvfi_rs2_addr, + output [31:0] rvfi_rs1_rdata, + output [31:0] rvfi_rs2_rdata, + output [ 4:0] rvfi_rd_addr, + output [31:0] rvfi_rd_wdata, + output [31:0] rvfi_pc_rdata, + output [31:0] rvfi_pc_wdata, + output [31:0] rvfi_mem_addr, + output [ 3:0] rvfi_mem_rmask, + output [ 3:0] rvfi_mem_wmask, + output [31:0] rvfi_mem_rdata, + output [31:0] rvfi_mem_wdata, +`endif + + // Trace Interface + output trace_valid, + output [35:0] trace_data, + + output mem_instr +); + wire mem_valid; + wire [31:0] mem_addr; + wire [31:0] mem_wdata; + wire [ 3:0] mem_wstrb; + reg mem_ready; + reg [31:0] mem_rdata; + + wire clk; + wire resetn; + + assign clk = wb_clk_i; + assign resetn = ~wb_rst_i; + + picorv32 #( + .ENABLE_COUNTERS (ENABLE_COUNTERS ), + .ENABLE_COUNTERS64 (ENABLE_COUNTERS64 ), + .ENABLE_REGS_16_31 (ENABLE_REGS_16_31 ), + .ENABLE_REGS_DUALPORT(ENABLE_REGS_DUALPORT), + .TWO_STAGE_SHIFT (TWO_STAGE_SHIFT ), + .BARREL_SHIFTER (BARREL_SHIFTER ), + .TWO_CYCLE_COMPARE (TWO_CYCLE_COMPARE ), + .TWO_CYCLE_ALU (TWO_CYCLE_ALU ), + .COMPRESSED_ISA (COMPRESSED_ISA ), + .CATCH_MISALIGN (CATCH_MISALIGN ), + .CATCH_ILLINSN (CATCH_ILLINSN ), + .ENABLE_PCPI (ENABLE_PCPI ), + .ENABLE_MUL (ENABLE_MUL ), + .ENABLE_FAST_MUL (ENABLE_FAST_MUL ), + .ENABLE_DIV (ENABLE_DIV ), + .ENABLE_IRQ (ENABLE_IRQ ), + .ENABLE_IRQ_QREGS (ENABLE_IRQ_QREGS ), + .ENABLE_IRQ_TIMER (ENABLE_IRQ_TIMER ), + .ENABLE_TRACE (ENABLE_TRACE ), + .REGS_INIT_ZERO (REGS_INIT_ZERO ), + .MASKED_IRQ (MASKED_IRQ ), + .LATCHED_IRQ (LATCHED_IRQ ), + .PROGADDR_RESET (PROGADDR_RESET ), + .PROGADDR_IRQ (PROGADDR_IRQ ), + .STACKADDR (STACKADDR ) + ) picorv32_core ( + .clk (clk ), + .resetn (resetn), + .trap (trap ), + + .mem_valid(mem_valid), + .mem_addr (mem_addr ), + .mem_wdata(mem_wdata), + .mem_wstrb(mem_wstrb), + .mem_instr(mem_instr), + .mem_ready(mem_ready), + .mem_rdata(mem_rdata), + + .pcpi_valid(pcpi_valid), + .pcpi_insn (pcpi_insn ), + .pcpi_rs1 (pcpi_rs1 ), + .pcpi_rs2 (pcpi_rs2 ), + .pcpi_wr (pcpi_wr ), + .pcpi_rd (pcpi_rd ), + .pcpi_wait (pcpi_wait ), + .pcpi_ready(pcpi_ready), + + .irq(irq), + .eoi(eoi), + +`ifdef RISCV_FORMAL + .rvfi_valid (rvfi_valid ), + .rvfi_order (rvfi_order ), + .rvfi_insn (rvfi_insn ), + .rvfi_trap (rvfi_trap ), + .rvfi_halt (rvfi_halt ), + .rvfi_intr (rvfi_intr ), + .rvfi_rs1_addr (rvfi_rs1_addr ), + .rvfi_rs2_addr (rvfi_rs2_addr ), + .rvfi_rs1_rdata(rvfi_rs1_rdata), + .rvfi_rs2_rdata(rvfi_rs2_rdata), + .rvfi_rd_addr (rvfi_rd_addr ), + .rvfi_rd_wdata (rvfi_rd_wdata ), + .rvfi_pc_rdata (rvfi_pc_rdata ), + .rvfi_pc_wdata (rvfi_pc_wdata ), + .rvfi_mem_addr (rvfi_mem_addr ), + .rvfi_mem_rmask(rvfi_mem_rmask), + .rvfi_mem_wmask(rvfi_mem_wmask), + .rvfi_mem_rdata(rvfi_mem_rdata), + .rvfi_mem_wdata(rvfi_mem_wdata), +`endif + + .trace_valid(trace_valid), + .trace_data (trace_data) + ); + + localparam IDLE = 2'b00; + localparam WBSTART = 2'b01; + localparam WBEND = 2'b10; + + reg [1:0] state; + + wire we; + assign we = (mem_wstrb[0] | mem_wstrb[1] | mem_wstrb[2] | mem_wstrb[3]); + + always @(posedge wb_clk_i) begin + if (wb_rst_i) begin + wbm_adr_o <= 0; + wbm_dat_o <= 0; + wbm_we_o <= 0; + wbm_sel_o <= 0; + wbm_stb_o <= 0; + wbm_cyc_o <= 0; + state <= IDLE; + end else begin + case (state) + IDLE: begin + if (mem_valid) begin + wbm_adr_o <= mem_addr; + wbm_dat_o <= mem_wdata; + wbm_we_o <= we; + wbm_sel_o <= mem_wstrb; + + wbm_stb_o <= 1'b1; + wbm_cyc_o <= 1'b1; + state <= WBSTART; + end else begin + mem_ready <= 1'b0; + + wbm_stb_o <= 1'b0; + wbm_cyc_o <= 1'b0; + wbm_we_o <= 1'b0; + end + end + WBSTART:begin + if (wbm_ack_i) begin + mem_rdata <= wbm_dat_i; + mem_ready <= 1'b1; + + state <= WBEND; + + wbm_stb_o <= 1'b0; + wbm_cyc_o <= 1'b0; + wbm_we_o <= 1'b0; + end + end + WBEND: begin + mem_ready <= 1'b0; + + state <= IDLE; + end + default: + state <= IDLE; + endcase + end + end +endmodule \ No newline at end of file diff --git a/openfpga_flow/benchmarks/processor/vexriscv/vexriscv_large.v b/openfpga_flow/benchmarks/processor/vexriscv/vexriscv_large.v new file mode 100644 index 0000000000..e8ee2b74a1 --- /dev/null +++ b/openfpga_flow/benchmarks/processor/vexriscv/vexriscv_large.v @@ -0,0 +1,7460 @@ +// Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 +// Component : VexRiscv +// Git hash : 36b3cd918896c94c4e8a224d97c559ab6dbf3ec9 + + +`define BranchCtrlEnum_defaultEncoding_type [1:0] +`define BranchCtrlEnum_defaultEncoding_INC 2'b00 +`define BranchCtrlEnum_defaultEncoding_B 2'b01 +`define BranchCtrlEnum_defaultEncoding_JAL 2'b10 +`define BranchCtrlEnum_defaultEncoding_JALR 2'b11 + +`define EnvCtrlEnum_defaultEncoding_type [0:0] +`define EnvCtrlEnum_defaultEncoding_NONE 1'b0 +`define EnvCtrlEnum_defaultEncoding_XRET 1'b1 + +`define ShiftCtrlEnum_defaultEncoding_type [1:0] +`define ShiftCtrlEnum_defaultEncoding_DISABLE_1 2'b00 +`define ShiftCtrlEnum_defaultEncoding_SLL_1 2'b01 +`define ShiftCtrlEnum_defaultEncoding_SRL_1 2'b10 +`define ShiftCtrlEnum_defaultEncoding_SRA_1 2'b11 + +`define AluBitwiseCtrlEnum_defaultEncoding_type [1:0] +`define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 2'b00 +`define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01 +`define AluBitwiseCtrlEnum_defaultEncoding_AND_1 2'b10 + +`define Src2CtrlEnum_defaultEncoding_type [1:0] +`define Src2CtrlEnum_defaultEncoding_RS 2'b00 +`define Src2CtrlEnum_defaultEncoding_IMI 2'b01 +`define Src2CtrlEnum_defaultEncoding_IMS 2'b10 +`define Src2CtrlEnum_defaultEncoding_PC 2'b11 + +`define AluCtrlEnum_defaultEncoding_type [1:0] +`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00 +`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01 +`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10 + +`define Src1CtrlEnum_defaultEncoding_type [1:0] +`define Src1CtrlEnum_defaultEncoding_RS 2'b00 +`define Src1CtrlEnum_defaultEncoding_IMU 2'b01 +`define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10 +`define Src1CtrlEnum_defaultEncoding_URS1 2'b11 + +`define MmuPlugin_shared_State_defaultEncoding_type [2:0] +`define MmuPlugin_shared_State_defaultEncoding_IDLE 3'b000 +`define MmuPlugin_shared_State_defaultEncoding_L1_CMD 3'b001 +`define MmuPlugin_shared_State_defaultEncoding_L1_RSP 3'b010 +`define MmuPlugin_shared_State_defaultEncoding_L0_CMD 3'b011 +`define MmuPlugin_shared_State_defaultEncoding_L0_RSP 3'b100 + + +module VexRiscv ( + output dBus_cmd_valid, + input dBus_cmd_ready, + output dBus_cmd_payload_wr, + output dBus_cmd_payload_uncached, + output [31:0] dBus_cmd_payload_address, + output [31:0] dBus_cmd_payload_data, + output [3:0] dBus_cmd_payload_mask, + output [2:0] dBus_cmd_payload_length, + output dBus_cmd_payload_last, + input dBus_rsp_valid, + input dBus_rsp_payload_last, + input [31:0] dBus_rsp_payload_data, + input dBus_rsp_payload_error, + input timerInterrupt, + input externalInterrupt, + input softwareInterrupt, + input debug_bus_cmd_valid, + output reg debug_bus_cmd_ready, + input debug_bus_cmd_payload_wr, + input [7:0] debug_bus_cmd_payload_address, + input [31:0] debug_bus_cmd_payload_data, + output reg [31:0] debug_bus_rsp_data, + output debug_resetOut, + output iBus_cmd_valid, + input iBus_cmd_ready, + output reg [31:0] iBus_cmd_payload_address, + output [2:0] iBus_cmd_payload_size, + input iBus_rsp_valid, + input [31:0] iBus_rsp_payload_data, + input iBus_rsp_payload_error, + input clk, + input reset, + input debugReset +); + wire _zz_184; + wire _zz_185; + wire _zz_186; + wire _zz_187; + wire _zz_188; + wire _zz_189; + wire _zz_190; + wire _zz_191; + reg _zz_192; + reg _zz_193; + reg [31:0] _zz_194; + reg _zz_195; + reg [31:0] _zz_196; + reg [1:0] _zz_197; + reg _zz_198; + wire [31:0] _zz_199; + reg _zz_200; + reg _zz_201; + wire _zz_202; + wire [31:0] _zz_203; + wire _zz_204; + wire _zz_205; + wire _zz_206; + wire _zz_207; + wire _zz_208; + wire _zz_209; + wire _zz_210; + wire _zz_211; + wire [3:0] _zz_212; + wire _zz_213; + reg [1:0] _zz_214; + reg [31:0] _zz_215; + reg [31:0] _zz_216; + reg [31:0] _zz_217; + reg _zz_218; + reg _zz_219; + reg _zz_220; + reg [9:0] _zz_221; + reg [9:0] _zz_222; + reg [9:0] _zz_223; + reg [9:0] _zz_224; + reg _zz_225; + reg _zz_226; + reg _zz_227; + reg _zz_228; + reg _zz_229; + reg _zz_230; + reg _zz_231; + reg [9:0] _zz_232; + reg [9:0] _zz_233; + reg [9:0] _zz_234; + reg [9:0] _zz_235; + reg _zz_236; + reg _zz_237; + reg _zz_238; + reg _zz_239; + wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; + wire IBusCachedPlugin_cache_io_cpu_decode_error; + wire IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling; + wire IBusCachedPlugin_cache_io_cpu_decode_mmuException; + wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_data; + wire IBusCachedPlugin_cache_io_cpu_decode_cacheMiss; + wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_physicalAddress; + wire IBusCachedPlugin_cache_io_mem_cmd_valid; + wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address; + wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size; + wire dataCache_1_io_cpu_execute_haltIt; + wire dataCache_1_io_cpu_execute_refilling; + wire dataCache_1_io_cpu_memory_isWrite; + wire dataCache_1_io_cpu_writeBack_haltIt; + wire [31:0] dataCache_1_io_cpu_writeBack_data; + wire dataCache_1_io_cpu_writeBack_mmuException; + wire dataCache_1_io_cpu_writeBack_unalignedAccess; + wire dataCache_1_io_cpu_writeBack_accessError; + wire dataCache_1_io_cpu_writeBack_isWrite; + wire dataCache_1_io_cpu_writeBack_keepMemRspData; + wire dataCache_1_io_cpu_flush_ready; + wire dataCache_1_io_cpu_redo; + wire dataCache_1_io_mem_cmd_valid; + wire dataCache_1_io_mem_cmd_payload_wr; + wire dataCache_1_io_mem_cmd_payload_uncached; + wire [31:0] dataCache_1_io_mem_cmd_payload_address; + wire [31:0] dataCache_1_io_mem_cmd_payload_data; + wire [3:0] dataCache_1_io_mem_cmd_payload_mask; + wire [2:0] dataCache_1_io_mem_cmd_payload_length; + wire dataCache_1_io_mem_cmd_payload_last; + wire _zz_240; + wire _zz_241; + wire _zz_242; + wire _zz_243; + wire _zz_244; + wire _zz_245; + wire _zz_246; + wire _zz_247; + wire _zz_248; + wire _zz_249; + wire _zz_250; + wire _zz_251; + wire _zz_252; + wire _zz_253; + wire _zz_254; + wire _zz_255; + wire [1:0] _zz_256; + wire _zz_257; + wire _zz_258; + wire _zz_259; + wire _zz_260; + wire _zz_261; + wire _zz_262; + wire _zz_263; + wire _zz_264; + wire _zz_265; + wire _zz_266; + wire _zz_267; + wire _zz_268; + wire [1:0] _zz_269; + wire _zz_270; + wire _zz_271; + wire _zz_272; + wire [5:0] _zz_273; + wire _zz_274; + wire _zz_275; + wire _zz_276; + wire _zz_277; + wire _zz_278; + wire _zz_279; + wire _zz_280; + wire _zz_281; + wire _zz_282; + wire _zz_283; + wire _zz_284; + wire _zz_285; + wire _zz_286; + wire _zz_287; + wire _zz_288; + wire [1:0] _zz_289; + wire [1:0] _zz_290; + wire _zz_291; + wire [51:0] _zz_292; + wire [51:0] _zz_293; + wire [51:0] _zz_294; + wire [32:0] _zz_295; + wire [51:0] _zz_296; + wire [49:0] _zz_297; + wire [51:0] _zz_298; + wire [49:0] _zz_299; + wire [51:0] _zz_300; + wire [32:0] _zz_301; + wire [31:0] _zz_302; + wire [32:0] _zz_303; + wire [0:0] _zz_304; + wire [0:0] _zz_305; + wire [0:0] _zz_306; + wire [0:0] _zz_307; + wire [0:0] _zz_308; + wire [0:0] _zz_309; + wire [0:0] _zz_310; + wire [0:0] _zz_311; + wire [0:0] _zz_312; + wire [0:0] _zz_313; + wire [0:0] _zz_314; + wire [0:0] _zz_315; + wire [0:0] _zz_316; + wire [0:0] _zz_317; + wire [0:0] _zz_318; + wire [0:0] _zz_319; + wire [0:0] _zz_320; + wire [0:0] _zz_321; + wire [0:0] _zz_322; + wire [3:0] _zz_323; + wire [2:0] _zz_324; + wire [31:0] _zz_325; + wire [1:0] _zz_326; + wire [1:0] _zz_327; + wire [1:0] _zz_328; + wire [1:0] _zz_329; + wire [9:0] _zz_330; + wire [29:0] _zz_331; + wire [9:0] _zz_332; + wire [1:0] _zz_333; + wire [1:0] _zz_334; + wire [1:0] _zz_335; + wire [19:0] _zz_336; + wire [11:0] _zz_337; + wire [31:0] _zz_338; + wire [31:0] _zz_339; + wire [19:0] _zz_340; + wire [11:0] _zz_341; + wire [2:0] _zz_342; + wire [2:0] _zz_343; + wire [0:0] _zz_344; + wire [1:0] _zz_345; + wire [0:0] _zz_346; + wire [2:0] _zz_347; + wire [0:0] _zz_348; + wire [0:0] _zz_349; + wire [0:0] _zz_350; + wire [0:0] _zz_351; + wire [0:0] _zz_352; + wire [0:0] _zz_353; + wire [0:0] _zz_354; + wire [0:0] _zz_355; + wire [1:0] _zz_356; + wire [0:0] _zz_357; + wire [2:0] _zz_358; + wire [4:0] _zz_359; + wire [11:0] _zz_360; + wire [11:0] _zz_361; + wire [31:0] _zz_362; + wire [31:0] _zz_363; + wire [31:0] _zz_364; + wire [31:0] _zz_365; + wire [31:0] _zz_366; + wire [31:0] _zz_367; + wire [31:0] _zz_368; + wire [65:0] _zz_369; + wire [65:0] _zz_370; + wire [31:0] _zz_371; + wire [31:0] _zz_372; + wire [0:0] _zz_373; + wire [5:0] _zz_374; + wire [32:0] _zz_375; + wire [31:0] _zz_376; + wire [31:0] _zz_377; + wire [32:0] _zz_378; + wire [32:0] _zz_379; + wire [32:0] _zz_380; + wire [32:0] _zz_381; + wire [0:0] _zz_382; + wire [32:0] _zz_383; + wire [0:0] _zz_384; + wire [32:0] _zz_385; + wire [0:0] _zz_386; + wire [31:0] _zz_387; + wire [1:0] _zz_388; + wire [1:0] _zz_389; + wire [11:0] _zz_390; + wire [19:0] _zz_391; + wire [11:0] _zz_392; + wire [31:0] _zz_393; + wire [31:0] _zz_394; + wire [31:0] _zz_395; + wire [11:0] _zz_396; + wire [19:0] _zz_397; + wire [11:0] _zz_398; + wire [2:0] _zz_399; + wire [0:0] _zz_400; + wire [0:0] _zz_401; + wire [0:0] _zz_402; + wire [0:0] _zz_403; + wire [0:0] _zz_404; + wire [0:0] _zz_405; + wire [0:0] _zz_406; + wire [0:0] _zz_407; + wire [0:0] _zz_408; + wire [0:0] _zz_409; + wire [0:0] _zz_410; + wire [0:0] _zz_411; + wire [0:0] _zz_412; + wire [1:0] _zz_413; + wire _zz_414; + wire _zz_415; + wire [1:0] _zz_416; + wire [31:0] _zz_417; + wire [31:0] _zz_418; + wire [31:0] _zz_419; + wire _zz_420; + wire [0:0] _zz_421; + wire [13:0] _zz_422; + wire [31:0] _zz_423; + wire [31:0] _zz_424; + wire [31:0] _zz_425; + wire _zz_426; + wire [0:0] _zz_427; + wire [7:0] _zz_428; + wire [31:0] _zz_429; + wire [31:0] _zz_430; + wire [31:0] _zz_431; + wire _zz_432; + wire [0:0] _zz_433; + wire [1:0] _zz_434; + wire _zz_435; + wire _zz_436; + wire _zz_437; + wire [31:0] _zz_438; + wire [31:0] _zz_439; + wire [31:0] _zz_440; + wire [31:0] _zz_441; + wire _zz_442; + wire [0:0] _zz_443; + wire [0:0] _zz_444; + wire _zz_445; + wire [0:0] _zz_446; + wire [26:0] _zz_447; + wire [31:0] _zz_448; + wire [31:0] _zz_449; + wire [31:0] _zz_450; + wire [31:0] _zz_451; + wire [0:0] _zz_452; + wire [0:0] _zz_453; + wire _zz_454; + wire [0:0] _zz_455; + wire [22:0] _zz_456; + wire [31:0] _zz_457; + wire _zz_458; + wire _zz_459; + wire [0:0] _zz_460; + wire [1:0] _zz_461; + wire [0:0] _zz_462; + wire [0:0] _zz_463; + wire _zz_464; + wire [0:0] _zz_465; + wire [18:0] _zz_466; + wire [31:0] _zz_467; + wire [31:0] _zz_468; + wire [31:0] _zz_469; + wire [31:0] _zz_470; + wire [31:0] _zz_471; + wire [31:0] _zz_472; + wire [31:0] _zz_473; + wire [31:0] _zz_474; + wire _zz_475; + wire [1:0] _zz_476; + wire [1:0] _zz_477; + wire _zz_478; + wire [0:0] _zz_479; + wire [15:0] _zz_480; + wire [31:0] _zz_481; + wire [31:0] _zz_482; + wire [31:0] _zz_483; + wire [31:0] _zz_484; + wire [31:0] _zz_485; + wire [31:0] _zz_486; + wire _zz_487; + wire [1:0] _zz_488; + wire [1:0] _zz_489; + wire _zz_490; + wire [0:0] _zz_491; + wire [12:0] _zz_492; + wire [31:0] _zz_493; + wire [31:0] _zz_494; + wire [31:0] _zz_495; + wire [31:0] _zz_496; + wire _zz_497; + wire [0:0] _zz_498; + wire [0:0] _zz_499; + wire _zz_500; + wire [4:0] _zz_501; + wire [4:0] _zz_502; + wire _zz_503; + wire [0:0] _zz_504; + wire [9:0] _zz_505; + wire [31:0] _zz_506; + wire [31:0] _zz_507; + wire [31:0] _zz_508; + wire [31:0] _zz_509; + wire [0:0] _zz_510; + wire [1:0] _zz_511; + wire [0:0] _zz_512; + wire [2:0] _zz_513; + wire [0:0] _zz_514; + wire [4:0] _zz_515; + wire [1:0] _zz_516; + wire [1:0] _zz_517; + wire _zz_518; + wire [0:0] _zz_519; + wire [6:0] _zz_520; + wire [31:0] _zz_521; + wire [31:0] _zz_522; + wire _zz_523; + wire _zz_524; + wire [31:0] _zz_525; + wire [31:0] _zz_526; + wire _zz_527; + wire [0:0] _zz_528; + wire [0:0] _zz_529; + wire _zz_530; + wire [0:0] _zz_531; + wire [2:0] _zz_532; + wire _zz_533; + wire [0:0] _zz_534; + wire [0:0] _zz_535; + wire [0:0] _zz_536; + wire [0:0] _zz_537; + wire _zz_538; + wire [0:0] _zz_539; + wire [4:0] _zz_540; + wire [31:0] _zz_541; + wire [31:0] _zz_542; + wire [31:0] _zz_543; + wire [31:0] _zz_544; + wire [31:0] _zz_545; + wire [31:0] _zz_546; + wire [31:0] _zz_547; + wire [31:0] _zz_548; + wire [31:0] _zz_549; + wire [31:0] _zz_550; + wire _zz_551; + wire [0:0] _zz_552; + wire [0:0] _zz_553; + wire [31:0] _zz_554; + wire [31:0] _zz_555; + wire [31:0] _zz_556; + wire [31:0] _zz_557; + wire [31:0] _zz_558; + wire _zz_559; + wire [3:0] _zz_560; + wire [3:0] _zz_561; + wire _zz_562; + wire [0:0] _zz_563; + wire [2:0] _zz_564; + wire [31:0] _zz_565; + wire [31:0] _zz_566; + wire [31:0] _zz_567; + wire [31:0] _zz_568; + wire [31:0] _zz_569; + wire [31:0] _zz_570; + wire _zz_571; + wire [0:0] _zz_572; + wire [1:0] _zz_573; + wire _zz_574; + wire [2:0] _zz_575; + wire [2:0] _zz_576; + wire _zz_577; + wire [0:0] _zz_578; + wire [0:0] _zz_579; + wire [31:0] _zz_580; + wire [31:0] _zz_581; + wire [31:0] _zz_582; + wire [31:0] _zz_583; + wire [31:0] _zz_584; + wire [31:0] _zz_585; + wire [31:0] _zz_586; + wire _zz_587; + wire _zz_588; + wire _zz_589; + wire [0:0] _zz_590; + wire [0:0] _zz_591; + wire _zz_592; + wire _zz_593; + wire _zz_594; + wire _zz_595; + wire [51:0] memory_MUL_LOW; + wire [31:0] execute_BRANCH_CALC; + wire execute_BRANCH_DO; + wire [33:0] memory_MUL_HH; + wire [33:0] execute_MUL_HH; + wire [33:0] execute_MUL_HL; + wire [33:0] execute_MUL_LH; + wire [31:0] execute_MUL_LL; + wire [31:0] execute_SHIFT_RIGHT; + wire [31:0] execute_REGFILE_WRITE_DATA; + wire execute_IS_DBUS_SHARING; + wire [1:0] memory_MEMORY_ADDRESS_LOW; + wire [1:0] execute_MEMORY_ADDRESS_LOW; + wire decode_PREDICTION_HAD_BRANCHED2; + wire decode_DO_EBREAK; + wire decode_CSR_READ_OPCODE; + wire decode_CSR_WRITE_OPCODE; + wire decode_SRC2_FORCE_ZERO; + wire `BranchCtrlEnum_defaultEncoding_type _zz_1; + wire `BranchCtrlEnum_defaultEncoding_type _zz_2; + wire `BranchCtrlEnum_defaultEncoding_type _zz_3; + wire `BranchCtrlEnum_defaultEncoding_type _zz_4; + wire `EnvCtrlEnum_defaultEncoding_type _zz_5; + wire `EnvCtrlEnum_defaultEncoding_type _zz_6; + wire `EnvCtrlEnum_defaultEncoding_type _zz_7; + wire `EnvCtrlEnum_defaultEncoding_type _zz_8; + wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_9; + wire `EnvCtrlEnum_defaultEncoding_type _zz_10; + wire `EnvCtrlEnum_defaultEncoding_type _zz_11; + wire decode_IS_CSR; + wire decode_IS_RS2_SIGNED; + wire decode_IS_RS1_SIGNED; + wire decode_IS_DIV; + wire memory_IS_MUL; + wire execute_IS_MUL; + wire decode_IS_MUL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_12; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_13; + wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_14; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_15; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_16; + wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_17; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_18; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_19; + wire decode_SRC_LESS_UNSIGNED; + wire memory_IS_SFENCE_VMA; + wire execute_IS_SFENCE_VMA; + wire decode_IS_SFENCE_VMA; + wire decode_MEMORY_MANAGMENT; + wire memory_MEMORY_WR; + wire decode_MEMORY_WR; + wire execute_BYPASSABLE_MEMORY_STAGE; + wire decode_BYPASSABLE_MEMORY_STAGE; + wire decode_BYPASSABLE_EXECUTE_STAGE; + wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; + wire `Src2CtrlEnum_defaultEncoding_type _zz_20; + wire `Src2CtrlEnum_defaultEncoding_type _zz_21; + wire `Src2CtrlEnum_defaultEncoding_type _zz_22; + wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_23; + wire `AluCtrlEnum_defaultEncoding_type _zz_24; + wire `AluCtrlEnum_defaultEncoding_type _zz_25; + wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; + wire `Src1CtrlEnum_defaultEncoding_type _zz_26; + wire `Src1CtrlEnum_defaultEncoding_type _zz_27; + wire `Src1CtrlEnum_defaultEncoding_type _zz_28; + wire decode_MEMORY_FORCE_CONSTISTENCY; + wire execute_PREDICTION_CONTEXT_hazard; + wire [1:0] execute_PREDICTION_CONTEXT_line_history; + wire [31:0] writeBack_FORMAL_PC_NEXT; + wire [31:0] memory_FORMAL_PC_NEXT; + wire [31:0] execute_FORMAL_PC_NEXT; + wire [31:0] decode_FORMAL_PC_NEXT; + wire [31:0] memory_BRANCH_CALC; + wire memory_BRANCH_DO; + wire execute_PREDICTION_HAD_BRANCHED2; + wire execute_BRANCH_COND_RESULT; + wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_29; + wire [31:0] execute_PC; + wire execute_DO_EBREAK; + wire decode_IS_EBREAK; + wire execute_CSR_READ_OPCODE; + wire execute_CSR_WRITE_OPCODE; + wire execute_IS_CSR; + wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_30; + wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_31; + wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_32; + wire execute_IS_RS1_SIGNED; + wire execute_IS_DIV; + wire execute_IS_RS2_SIGNED; + wire memory_IS_DIV; + wire writeBack_IS_MUL; + wire [33:0] writeBack_MUL_HH; + wire [51:0] writeBack_MUL_LOW; + wire [33:0] memory_MUL_HL; + wire [33:0] memory_MUL_LH; + wire [31:0] memory_MUL_LL; + (* keep , syn_keep *) wire [31:0] execute_RS1 /* synthesis syn_keep = 1 */ ; + wire decode_RS2_USE; + wire decode_RS1_USE; + reg [31:0] _zz_33; + wire execute_REGFILE_WRITE_VALID; + wire execute_BYPASSABLE_EXECUTE_STAGE; + wire memory_REGFILE_WRITE_VALID; + wire [31:0] memory_INSTRUCTION; + wire memory_BYPASSABLE_MEMORY_STAGE; + wire writeBack_REGFILE_WRITE_VALID; + reg [31:0] decode_RS2; + reg [31:0] decode_RS1; + wire [31:0] memory_SHIFT_RIGHT; + reg [31:0] _zz_34; + wire `ShiftCtrlEnum_defaultEncoding_type memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_35; + wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_36; + wire execute_SRC_LESS_UNSIGNED; + wire execute_SRC2_FORCE_ZERO; + wire execute_SRC_USE_SUB_LESS; + wire [31:0] _zz_37; + wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL; + wire `Src2CtrlEnum_defaultEncoding_type _zz_38; + wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL; + wire `Src1CtrlEnum_defaultEncoding_type _zz_39; + wire decode_SRC_USE_SUB_LESS; + wire decode_SRC_ADD_ZERO; + wire [31:0] execute_SRC_ADD_SUB; + wire execute_SRC_LESS; + wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_40; + wire [31:0] execute_SRC2; + wire [31:0] execute_SRC1; + wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_41; + wire [31:0] _zz_42; + wire _zz_43; + reg _zz_44; + wire [31:0] decode_INSTRUCTION_ANTICIPATED; + reg decode_REGFILE_WRITE_VALID; + wire decode_LEGAL_INSTRUCTION; + wire `BranchCtrlEnum_defaultEncoding_type _zz_45; + wire `EnvCtrlEnum_defaultEncoding_type _zz_46; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_47; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_48; + wire `Src2CtrlEnum_defaultEncoding_type _zz_49; + wire `AluCtrlEnum_defaultEncoding_type _zz_50; + wire `Src1CtrlEnum_defaultEncoding_type _zz_51; + wire writeBack_IS_SFENCE_VMA; + wire writeBack_IS_DBUS_SHARING; + wire memory_IS_DBUS_SHARING; + reg [31:0] _zz_52; + wire [1:0] writeBack_MEMORY_ADDRESS_LOW; + wire writeBack_MEMORY_WR; + wire [31:0] writeBack_REGFILE_WRITE_DATA; + wire writeBack_MEMORY_ENABLE; + wire [31:0] memory_REGFILE_WRITE_DATA; + wire memory_MEMORY_ENABLE; + wire execute_MEMORY_FORCE_CONSTISTENCY; + wire execute_MEMORY_MANAGMENT; + (* keep , syn_keep *) wire [31:0] execute_RS2 /* synthesis syn_keep = 1 */ ; + wire execute_MEMORY_WR; + wire [31:0] execute_SRC_ADD; + wire execute_MEMORY_ENABLE; + wire [31:0] execute_INSTRUCTION; + wire decode_MEMORY_ENABLE; + wire decode_FLUSH_ALL; + reg IBusCachedPlugin_rsp_issueDetected_4; + reg IBusCachedPlugin_rsp_issueDetected_3; + reg IBusCachedPlugin_rsp_issueDetected_2; + reg IBusCachedPlugin_rsp_issueDetected_1; + wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_53; + wire [31:0] decode_INSTRUCTION; + wire `BranchCtrlEnum_defaultEncoding_type memory_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_54; + wire [31:0] memory_PC; + wire memory_PREDICTION_CONTEXT_hazard; + wire [1:0] memory_PREDICTION_CONTEXT_line_history; + wire decode_PREDICTION_CONTEXT_hazard; + wire [1:0] decode_PREDICTION_CONTEXT_line_history; + reg _zz_55; + reg [31:0] _zz_56; + reg [31:0] _zz_57; + wire [31:0] decode_PC; + wire [31:0] writeBack_PC; + wire [31:0] writeBack_INSTRUCTION; + reg decode_arbitration_haltItself; + reg decode_arbitration_haltByOther; + reg decode_arbitration_removeIt; + wire decode_arbitration_flushIt; + reg decode_arbitration_flushNext; + reg decode_arbitration_isValid; + wire decode_arbitration_isStuck; + wire decode_arbitration_isStuckByOthers; + wire decode_arbitration_isFlushed; + wire decode_arbitration_isMoving; + wire decode_arbitration_isFiring; + reg execute_arbitration_haltItself; + reg execute_arbitration_haltByOther; + reg execute_arbitration_removeIt; + reg execute_arbitration_flushIt; + reg execute_arbitration_flushNext; + reg execute_arbitration_isValid; + wire execute_arbitration_isStuck; + wire execute_arbitration_isStuckByOthers; + wire execute_arbitration_isFlushed; + wire execute_arbitration_isMoving; + wire execute_arbitration_isFiring; + reg memory_arbitration_haltItself; + wire memory_arbitration_haltByOther; + reg memory_arbitration_removeIt; + wire memory_arbitration_flushIt; + reg memory_arbitration_flushNext; + reg memory_arbitration_isValid; + wire memory_arbitration_isStuck; + wire memory_arbitration_isStuckByOthers; + wire memory_arbitration_isFlushed; + wire memory_arbitration_isMoving; + wire memory_arbitration_isFiring; + reg writeBack_arbitration_haltItself; + wire writeBack_arbitration_haltByOther; + reg writeBack_arbitration_removeIt; + reg writeBack_arbitration_flushIt; + reg writeBack_arbitration_flushNext; + reg writeBack_arbitration_isValid; + wire writeBack_arbitration_isStuck; + wire writeBack_arbitration_isStuckByOthers; + wire writeBack_arbitration_isFlushed; + wire writeBack_arbitration_isMoving; + wire writeBack_arbitration_isFiring; + wire [31:0] lastStageInstruction /* verilator public */ ; + wire [31:0] lastStagePc /* verilator public */ ; + wire lastStageIsValid /* verilator public */ ; + wire lastStageIsFiring /* verilator public */ ; + reg IBusCachedPlugin_fetcherHalt; + reg IBusCachedPlugin_incomingInstruction; + wire IBusCachedPlugin_predictionJumpInterface_valid; + (* keep , syn_keep *) wire [31:0] IBusCachedPlugin_predictionJumpInterface_payload /* synthesis syn_keep = 1 */ ; + reg IBusCachedPlugin_decodePrediction_cmd_hadBranch; + wire IBusCachedPlugin_decodePrediction_rsp_wasWrong; + wire IBusCachedPlugin_pcValids_0; + wire IBusCachedPlugin_pcValids_1; + wire IBusCachedPlugin_pcValids_2; + wire IBusCachedPlugin_pcValids_3; + reg IBusCachedPlugin_decodeExceptionPort_valid; + reg [3:0] IBusCachedPlugin_decodeExceptionPort_payload_code; + wire [31:0] IBusCachedPlugin_decodeExceptionPort_payload_badAddr; + wire IBusCachedPlugin_mmuBus_cmd_0_isValid; + wire IBusCachedPlugin_mmuBus_cmd_0_isStuck; + wire [31:0] IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + wire IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation; + reg [31:0] IBusCachedPlugin_mmuBus_rsp_physicalAddress; + wire IBusCachedPlugin_mmuBus_rsp_isIoAccess; + reg IBusCachedPlugin_mmuBus_rsp_isPaging; + reg IBusCachedPlugin_mmuBus_rsp_allowRead; + reg IBusCachedPlugin_mmuBus_rsp_allowWrite; + reg IBusCachedPlugin_mmuBus_rsp_allowExecute; + reg IBusCachedPlugin_mmuBus_rsp_exception; + reg IBusCachedPlugin_mmuBus_rsp_refilling; + wire IBusCachedPlugin_mmuBus_rsp_bypassTranslation; + wire IBusCachedPlugin_mmuBus_rsp_ways_0_sel; + wire [31:0] IBusCachedPlugin_mmuBus_rsp_ways_0_physical; + wire IBusCachedPlugin_mmuBus_rsp_ways_1_sel; + wire [31:0] IBusCachedPlugin_mmuBus_rsp_ways_1_physical; + wire IBusCachedPlugin_mmuBus_rsp_ways_2_sel; + wire [31:0] IBusCachedPlugin_mmuBus_rsp_ways_2_physical; + wire IBusCachedPlugin_mmuBus_rsp_ways_3_sel; + wire [31:0] IBusCachedPlugin_mmuBus_rsp_ways_3_physical; + wire IBusCachedPlugin_mmuBus_end; + wire IBusCachedPlugin_mmuBus_busy; + wire DBusCachedPlugin_mmuBus_cmd_0_isValid; + wire DBusCachedPlugin_mmuBus_cmd_0_isStuck; + wire [31:0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + reg DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation; + reg [31:0] DBusCachedPlugin_mmuBus_rsp_physicalAddress; + wire DBusCachedPlugin_mmuBus_rsp_isIoAccess; + reg DBusCachedPlugin_mmuBus_rsp_isPaging; + reg DBusCachedPlugin_mmuBus_rsp_allowRead; + reg DBusCachedPlugin_mmuBus_rsp_allowWrite; + reg DBusCachedPlugin_mmuBus_rsp_allowExecute; + reg DBusCachedPlugin_mmuBus_rsp_exception; + reg DBusCachedPlugin_mmuBus_rsp_refilling; + wire DBusCachedPlugin_mmuBus_rsp_bypassTranslation; + wire DBusCachedPlugin_mmuBus_rsp_ways_0_sel; + wire [31:0] DBusCachedPlugin_mmuBus_rsp_ways_0_physical; + wire DBusCachedPlugin_mmuBus_rsp_ways_1_sel; + wire [31:0] DBusCachedPlugin_mmuBus_rsp_ways_1_physical; + wire DBusCachedPlugin_mmuBus_rsp_ways_2_sel; + wire [31:0] DBusCachedPlugin_mmuBus_rsp_ways_2_physical; + wire DBusCachedPlugin_mmuBus_rsp_ways_3_sel; + wire [31:0] DBusCachedPlugin_mmuBus_rsp_ways_3_physical; + wire DBusCachedPlugin_mmuBus_rsp_ways_4_sel; + wire [31:0] DBusCachedPlugin_mmuBus_rsp_ways_4_physical; + wire DBusCachedPlugin_mmuBus_rsp_ways_5_sel; + wire [31:0] DBusCachedPlugin_mmuBus_rsp_ways_5_physical; + wire DBusCachedPlugin_mmuBus_end; + wire DBusCachedPlugin_mmuBus_busy; + reg DBusCachedPlugin_redoBranch_valid; + wire [31:0] DBusCachedPlugin_redoBranch_payload; + reg DBusCachedPlugin_exceptionBus_valid; + reg [3:0] DBusCachedPlugin_exceptionBus_payload_code; + wire [31:0] DBusCachedPlugin_exceptionBus_payload_badAddr; + reg _zz_58; + reg MmuPlugin_dBusAccess_cmd_valid; + reg MmuPlugin_dBusAccess_cmd_ready; + reg [31:0] MmuPlugin_dBusAccess_cmd_payload_address; + wire [1:0] MmuPlugin_dBusAccess_cmd_payload_size; + wire MmuPlugin_dBusAccess_cmd_payload_write; + wire [31:0] MmuPlugin_dBusAccess_cmd_payload_data; + wire [3:0] MmuPlugin_dBusAccess_cmd_payload_writeMask; + wire MmuPlugin_dBusAccess_rsp_valid; + wire [31:0] MmuPlugin_dBusAccess_rsp_payload_data; + wire MmuPlugin_dBusAccess_rsp_payload_error; + wire MmuPlugin_dBusAccess_rsp_payload_redo; + wire decodeExceptionPort_valid; + wire [3:0] decodeExceptionPort_payload_code; + wire [31:0] decodeExceptionPort_payload_badAddr; + wire CsrPlugin_inWfi /* verilator public */ ; + reg CsrPlugin_thirdPartyWake; + reg CsrPlugin_jumpInterface_valid; + reg [31:0] CsrPlugin_jumpInterface_payload; + wire CsrPlugin_exceptionPendings_0; + wire CsrPlugin_exceptionPendings_1; + wire CsrPlugin_exceptionPendings_2; + wire CsrPlugin_exceptionPendings_3; + wire contextSwitching; + reg [1:0] CsrPlugin_privilege; + reg CsrPlugin_forceMachineWire; + reg CsrPlugin_allowInterrupts; + reg CsrPlugin_allowException; + reg IBusCachedPlugin_injectionPort_valid; + reg IBusCachedPlugin_injectionPort_ready; + wire [31:0] IBusCachedPlugin_injectionPort_payload; + wire BranchPlugin_jumpInterface_valid; + wire [31:0] BranchPlugin_jumpInterface_payload; + wire BranchPlugin_branchExceptionPort_valid; + wire [3:0] BranchPlugin_branchExceptionPort_payload_code; + wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr; + wire IBusCachedPlugin_externalFlush; + wire IBusCachedPlugin_jump_pcLoad_valid; + wire [31:0] IBusCachedPlugin_jump_pcLoad_payload; + wire [3:0] _zz_59; + wire [3:0] _zz_60; + wire _zz_61; + wire _zz_62; + wire _zz_63; + wire IBusCachedPlugin_fetchPc_output_valid; + wire IBusCachedPlugin_fetchPc_output_ready; + wire [31:0] IBusCachedPlugin_fetchPc_output_payload; + reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ; + reg IBusCachedPlugin_fetchPc_correction; + reg IBusCachedPlugin_fetchPc_correctionReg; + wire IBusCachedPlugin_fetchPc_corrected; + reg IBusCachedPlugin_fetchPc_pcRegPropagate; + reg IBusCachedPlugin_fetchPc_booted; + reg IBusCachedPlugin_fetchPc_inc; + reg [31:0] IBusCachedPlugin_fetchPc_pc; + wire IBusCachedPlugin_fetchPc_redo_valid; + wire [31:0] IBusCachedPlugin_fetchPc_redo_payload; + reg IBusCachedPlugin_fetchPc_flushed; + reg IBusCachedPlugin_iBusRsp_redoFetch; + wire IBusCachedPlugin_iBusRsp_stages_0_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_0_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_0_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_0_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_0_halt; + wire IBusCachedPlugin_iBusRsp_stages_1_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_1_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_1_halt; + wire IBusCachedPlugin_iBusRsp_stages_2_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_2_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_2_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_2_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_2_halt; + wire _zz_64; + wire _zz_65; + wire _zz_66; + wire IBusCachedPlugin_iBusRsp_flush; + wire _zz_67; + wire _zz_68; + reg _zz_69; + wire _zz_70; + reg _zz_71; + reg [31:0] _zz_72; + reg IBusCachedPlugin_iBusRsp_readyForError; + wire IBusCachedPlugin_iBusRsp_output_valid; + wire IBusCachedPlugin_iBusRsp_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_pc; + wire IBusCachedPlugin_iBusRsp_output_payload_rsp_error; + wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; + wire IBusCachedPlugin_iBusRsp_output_payload_isRvc; + reg IBusCachedPlugin_injector_nextPcCalc_valids_0; + reg IBusCachedPlugin_injector_nextPcCalc_valids_1; + reg IBusCachedPlugin_injector_nextPcCalc_valids_2; + reg IBusCachedPlugin_injector_nextPcCalc_valids_3; + reg IBusCachedPlugin_injector_nextPcCalc_valids_4; + wire _zz_74; + wire [9:0] _zz_75; + reg _zz_76; + reg [9:0] _zz_77; + wire [29:0] _zz_78; + wire _zz_79; + reg _zz_80; + reg [1:0] _zz_81; + wire _zz_82; + wire _zz_83; + reg [10:0] _zz_84; + wire _zz_85; + reg [18:0] _zz_86; + reg _zz_87; + wire _zz_88; + reg [10:0] _zz_89; + wire _zz_90; + reg [18:0] _zz_91; + wire [31:0] _zz_92; + reg [31:0] IBusCachedPlugin_rspCounter; + wire IBusCachedPlugin_s0_tightlyCoupledHit; + reg IBusCachedPlugin_s1_tightlyCoupledHit; + reg IBusCachedPlugin_s2_tightlyCoupledHit; + wire IBusCachedPlugin_rsp_iBusRspOutputHalt; + wire IBusCachedPlugin_rsp_issueDetected; + reg IBusCachedPlugin_rsp_redoFetch; + wire [31:0] _zz_93; + reg [31:0] DBusCachedPlugin_rspCounter; + wire [1:0] execute_DBusCachedPlugin_size; + reg [31:0] _zz_94; + reg [31:0] writeBack_DBusCachedPlugin_rspShifted; + wire _zz_95; + reg [31:0] _zz_96; + wire _zz_97; + reg [31:0] _zz_98; + reg [31:0] writeBack_DBusCachedPlugin_rspFormated; + reg DBusCachedPlugin_forceDatapath; + reg MmuPlugin_status_sum; + reg MmuPlugin_status_mxr; + reg MmuPlugin_status_mprv; + reg MmuPlugin_satp_mode; + reg [8:0] MmuPlugin_satp_asid; + reg [19:0] MmuPlugin_satp_ppn; + reg MmuPlugin_ports_0_cache_0_valid; + reg MmuPlugin_ports_0_cache_0_exception; + reg MmuPlugin_ports_0_cache_0_superPage; + reg [9:0] MmuPlugin_ports_0_cache_0_virtualAddress_0; + reg [9:0] MmuPlugin_ports_0_cache_0_virtualAddress_1; + reg [9:0] MmuPlugin_ports_0_cache_0_physicalAddress_0; + reg [9:0] MmuPlugin_ports_0_cache_0_physicalAddress_1; + reg MmuPlugin_ports_0_cache_0_allowRead; + reg MmuPlugin_ports_0_cache_0_allowWrite; + reg MmuPlugin_ports_0_cache_0_allowExecute; + reg MmuPlugin_ports_0_cache_0_allowUser; + reg MmuPlugin_ports_0_cache_1_valid; + reg MmuPlugin_ports_0_cache_1_exception; + reg MmuPlugin_ports_0_cache_1_superPage; + reg [9:0] MmuPlugin_ports_0_cache_1_virtualAddress_0; + reg [9:0] MmuPlugin_ports_0_cache_1_virtualAddress_1; + reg [9:0] MmuPlugin_ports_0_cache_1_physicalAddress_0; + reg [9:0] MmuPlugin_ports_0_cache_1_physicalAddress_1; + reg MmuPlugin_ports_0_cache_1_allowRead; + reg MmuPlugin_ports_0_cache_1_allowWrite; + reg MmuPlugin_ports_0_cache_1_allowExecute; + reg MmuPlugin_ports_0_cache_1_allowUser; + reg MmuPlugin_ports_0_cache_2_valid; + reg MmuPlugin_ports_0_cache_2_exception; + reg MmuPlugin_ports_0_cache_2_superPage; + reg [9:0] MmuPlugin_ports_0_cache_2_virtualAddress_0; + reg [9:0] MmuPlugin_ports_0_cache_2_virtualAddress_1; + reg [9:0] MmuPlugin_ports_0_cache_2_physicalAddress_0; + reg [9:0] MmuPlugin_ports_0_cache_2_physicalAddress_1; + reg MmuPlugin_ports_0_cache_2_allowRead; + reg MmuPlugin_ports_0_cache_2_allowWrite; + reg MmuPlugin_ports_0_cache_2_allowExecute; + reg MmuPlugin_ports_0_cache_2_allowUser; + reg MmuPlugin_ports_0_cache_3_valid; + reg MmuPlugin_ports_0_cache_3_exception; + reg MmuPlugin_ports_0_cache_3_superPage; + reg [9:0] MmuPlugin_ports_0_cache_3_virtualAddress_0; + reg [9:0] MmuPlugin_ports_0_cache_3_virtualAddress_1; + reg [9:0] MmuPlugin_ports_0_cache_3_physicalAddress_0; + reg [9:0] MmuPlugin_ports_0_cache_3_physicalAddress_1; + reg MmuPlugin_ports_0_cache_3_allowRead; + reg MmuPlugin_ports_0_cache_3_allowWrite; + reg MmuPlugin_ports_0_cache_3_allowExecute; + reg MmuPlugin_ports_0_cache_3_allowUser; + wire MmuPlugin_ports_0_dirty; + reg MmuPlugin_ports_0_requireMmuLockupCalc; + reg [3:0] MmuPlugin_ports_0_cacheHitsCalc; + wire MmuPlugin_ports_0_cacheHit; + wire _zz_99; + wire _zz_100; + wire _zz_101; + wire [1:0] _zz_102; + wire MmuPlugin_ports_0_cacheLine_valid; + wire MmuPlugin_ports_0_cacheLine_exception; + wire MmuPlugin_ports_0_cacheLine_superPage; + wire [9:0] MmuPlugin_ports_0_cacheLine_virtualAddress_0; + wire [9:0] MmuPlugin_ports_0_cacheLine_virtualAddress_1; + wire [9:0] MmuPlugin_ports_0_cacheLine_physicalAddress_0; + wire [9:0] MmuPlugin_ports_0_cacheLine_physicalAddress_1; + wire MmuPlugin_ports_0_cacheLine_allowRead; + wire MmuPlugin_ports_0_cacheLine_allowWrite; + wire MmuPlugin_ports_0_cacheLine_allowExecute; + wire MmuPlugin_ports_0_cacheLine_allowUser; + reg MmuPlugin_ports_0_entryToReplace_willIncrement; + wire MmuPlugin_ports_0_entryToReplace_willClear; + reg [1:0] MmuPlugin_ports_0_entryToReplace_valueNext; + reg [1:0] MmuPlugin_ports_0_entryToReplace_value; + wire MmuPlugin_ports_0_entryToReplace_willOverflowIfInc; + wire MmuPlugin_ports_0_entryToReplace_willOverflow; + reg MmuPlugin_ports_1_cache_0_valid; + reg MmuPlugin_ports_1_cache_0_exception; + reg MmuPlugin_ports_1_cache_0_superPage; + reg [9:0] MmuPlugin_ports_1_cache_0_virtualAddress_0; + reg [9:0] MmuPlugin_ports_1_cache_0_virtualAddress_1; + reg [9:0] MmuPlugin_ports_1_cache_0_physicalAddress_0; + reg [9:0] MmuPlugin_ports_1_cache_0_physicalAddress_1; + reg MmuPlugin_ports_1_cache_0_allowRead; + reg MmuPlugin_ports_1_cache_0_allowWrite; + reg MmuPlugin_ports_1_cache_0_allowExecute; + reg MmuPlugin_ports_1_cache_0_allowUser; + reg MmuPlugin_ports_1_cache_1_valid; + reg MmuPlugin_ports_1_cache_1_exception; + reg MmuPlugin_ports_1_cache_1_superPage; + reg [9:0] MmuPlugin_ports_1_cache_1_virtualAddress_0; + reg [9:0] MmuPlugin_ports_1_cache_1_virtualAddress_1; + reg [9:0] MmuPlugin_ports_1_cache_1_physicalAddress_0; + reg [9:0] MmuPlugin_ports_1_cache_1_physicalAddress_1; + reg MmuPlugin_ports_1_cache_1_allowRead; + reg MmuPlugin_ports_1_cache_1_allowWrite; + reg MmuPlugin_ports_1_cache_1_allowExecute; + reg MmuPlugin_ports_1_cache_1_allowUser; + reg MmuPlugin_ports_1_cache_2_valid; + reg MmuPlugin_ports_1_cache_2_exception; + reg MmuPlugin_ports_1_cache_2_superPage; + reg [9:0] MmuPlugin_ports_1_cache_2_virtualAddress_0; + reg [9:0] MmuPlugin_ports_1_cache_2_virtualAddress_1; + reg [9:0] MmuPlugin_ports_1_cache_2_physicalAddress_0; + reg [9:0] MmuPlugin_ports_1_cache_2_physicalAddress_1; + reg MmuPlugin_ports_1_cache_2_allowRead; + reg MmuPlugin_ports_1_cache_2_allowWrite; + reg MmuPlugin_ports_1_cache_2_allowExecute; + reg MmuPlugin_ports_1_cache_2_allowUser; + reg MmuPlugin_ports_1_cache_3_valid; + reg MmuPlugin_ports_1_cache_3_exception; + reg MmuPlugin_ports_1_cache_3_superPage; + reg [9:0] MmuPlugin_ports_1_cache_3_virtualAddress_0; + reg [9:0] MmuPlugin_ports_1_cache_3_virtualAddress_1; + reg [9:0] MmuPlugin_ports_1_cache_3_physicalAddress_0; + reg [9:0] MmuPlugin_ports_1_cache_3_physicalAddress_1; + reg MmuPlugin_ports_1_cache_3_allowRead; + reg MmuPlugin_ports_1_cache_3_allowWrite; + reg MmuPlugin_ports_1_cache_3_allowExecute; + reg MmuPlugin_ports_1_cache_3_allowUser; + reg MmuPlugin_ports_1_cache_4_valid; + reg MmuPlugin_ports_1_cache_4_exception; + reg MmuPlugin_ports_1_cache_4_superPage; + reg [9:0] MmuPlugin_ports_1_cache_4_virtualAddress_0; + reg [9:0] MmuPlugin_ports_1_cache_4_virtualAddress_1; + reg [9:0] MmuPlugin_ports_1_cache_4_physicalAddress_0; + reg [9:0] MmuPlugin_ports_1_cache_4_physicalAddress_1; + reg MmuPlugin_ports_1_cache_4_allowRead; + reg MmuPlugin_ports_1_cache_4_allowWrite; + reg MmuPlugin_ports_1_cache_4_allowExecute; + reg MmuPlugin_ports_1_cache_4_allowUser; + reg MmuPlugin_ports_1_cache_5_valid; + reg MmuPlugin_ports_1_cache_5_exception; + reg MmuPlugin_ports_1_cache_5_superPage; + reg [9:0] MmuPlugin_ports_1_cache_5_virtualAddress_0; + reg [9:0] MmuPlugin_ports_1_cache_5_virtualAddress_1; + reg [9:0] MmuPlugin_ports_1_cache_5_physicalAddress_0; + reg [9:0] MmuPlugin_ports_1_cache_5_physicalAddress_1; + reg MmuPlugin_ports_1_cache_5_allowRead; + reg MmuPlugin_ports_1_cache_5_allowWrite; + reg MmuPlugin_ports_1_cache_5_allowExecute; + reg MmuPlugin_ports_1_cache_5_allowUser; + wire MmuPlugin_ports_1_dirty; + reg MmuPlugin_ports_1_requireMmuLockupCalc; + reg [5:0] MmuPlugin_ports_1_cacheHitsCalc; + wire MmuPlugin_ports_1_cacheHit; + wire _zz_103; + wire _zz_104; + wire _zz_105; + wire _zz_106; + wire _zz_107; + wire [2:0] _zz_108; + wire MmuPlugin_ports_1_cacheLine_valid; + wire MmuPlugin_ports_1_cacheLine_exception; + wire MmuPlugin_ports_1_cacheLine_superPage; + wire [9:0] MmuPlugin_ports_1_cacheLine_virtualAddress_0; + wire [9:0] MmuPlugin_ports_1_cacheLine_virtualAddress_1; + wire [9:0] MmuPlugin_ports_1_cacheLine_physicalAddress_0; + wire [9:0] MmuPlugin_ports_1_cacheLine_physicalAddress_1; + wire MmuPlugin_ports_1_cacheLine_allowRead; + wire MmuPlugin_ports_1_cacheLine_allowWrite; + wire MmuPlugin_ports_1_cacheLine_allowExecute; + wire MmuPlugin_ports_1_cacheLine_allowUser; + reg MmuPlugin_ports_1_entryToReplace_willIncrement; + wire MmuPlugin_ports_1_entryToReplace_willClear; + reg [2:0] MmuPlugin_ports_1_entryToReplace_valueNext; + reg [2:0] MmuPlugin_ports_1_entryToReplace_value; + wire MmuPlugin_ports_1_entryToReplace_willOverflowIfInc; + wire MmuPlugin_ports_1_entryToReplace_willOverflow; + reg `MmuPlugin_shared_State_defaultEncoding_type MmuPlugin_shared_state_1; + reg [9:0] MmuPlugin_shared_vpn_0; + reg [9:0] MmuPlugin_shared_vpn_1; + reg [1:0] MmuPlugin_shared_portSortedOh; + reg MmuPlugin_shared_dBusRspStaged_valid; + reg [31:0] MmuPlugin_shared_dBusRspStaged_payload_data; + reg MmuPlugin_shared_dBusRspStaged_payload_error; + reg MmuPlugin_shared_dBusRspStaged_payload_redo; + wire MmuPlugin_shared_dBusRsp_pte_V; + wire MmuPlugin_shared_dBusRsp_pte_R; + wire MmuPlugin_shared_dBusRsp_pte_W; + wire MmuPlugin_shared_dBusRsp_pte_X; + wire MmuPlugin_shared_dBusRsp_pte_U; + wire MmuPlugin_shared_dBusRsp_pte_G; + wire MmuPlugin_shared_dBusRsp_pte_A; + wire MmuPlugin_shared_dBusRsp_pte_D; + wire [1:0] MmuPlugin_shared_dBusRsp_pte_RSW; + wire [9:0] MmuPlugin_shared_dBusRsp_pte_PPN0; + wire [11:0] MmuPlugin_shared_dBusRsp_pte_PPN1; + wire MmuPlugin_shared_dBusRsp_exception; + wire MmuPlugin_shared_dBusRsp_leaf; + reg MmuPlugin_shared_pteBuffer_V; + reg MmuPlugin_shared_pteBuffer_R; + reg MmuPlugin_shared_pteBuffer_W; + reg MmuPlugin_shared_pteBuffer_X; + reg MmuPlugin_shared_pteBuffer_U; + reg MmuPlugin_shared_pteBuffer_G; + reg MmuPlugin_shared_pteBuffer_A; + reg MmuPlugin_shared_pteBuffer_D; + reg [1:0] MmuPlugin_shared_pteBuffer_RSW; + reg [9:0] MmuPlugin_shared_pteBuffer_PPN0; + reg [11:0] MmuPlugin_shared_pteBuffer_PPN1; + reg [1:0] _zz_109; + wire [1:0] _zz_110; + reg [1:0] _zz_111; + wire [1:0] MmuPlugin_shared_refills; + wire [1:0] _zz_112; + reg [1:0] _zz_113; + wire [31:0] _zz_114; + wire [32:0] _zz_115; + wire _zz_116; + wire _zz_117; + wire _zz_118; + wire _zz_119; + wire `Src1CtrlEnum_defaultEncoding_type _zz_120; + wire `AluCtrlEnum_defaultEncoding_type _zz_121; + wire `Src2CtrlEnum_defaultEncoding_type _zz_122; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_123; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_124; + wire `EnvCtrlEnum_defaultEncoding_type _zz_125; + wire `BranchCtrlEnum_defaultEncoding_type _zz_126; + wire [4:0] decode_RegFilePlugin_regFileReadAddress1; + wire [4:0] decode_RegFilePlugin_regFileReadAddress2; + wire [31:0] decode_RegFilePlugin_rs1Data; + wire [31:0] decode_RegFilePlugin_rs2Data; + reg lastStageRegFileWrite_valid /* verilator public */ ; + reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; + reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; + reg _zz_127; + reg [31:0] execute_IntAluPlugin_bitwise; + reg [31:0] _zz_128; + reg [31:0] _zz_129; + wire _zz_130; + reg [19:0] _zz_131; + wire _zz_132; + reg [19:0] _zz_133; + reg [31:0] _zz_134; + reg [31:0] execute_SrcPlugin_addSub; + wire execute_SrcPlugin_less; + wire [4:0] execute_FullBarrelShifterPlugin_amplitude; + reg [31:0] _zz_135; + wire [31:0] execute_FullBarrelShifterPlugin_reversed; + reg [31:0] _zz_136; + reg _zz_137; + reg _zz_138; + reg _zz_139; + reg [4:0] _zz_140; + reg [31:0] _zz_141; + wire _zz_142; + wire _zz_143; + wire _zz_144; + wire _zz_145; + wire _zz_146; + wire _zz_147; + reg execute_MulPlugin_aSigned; + reg execute_MulPlugin_bSigned; + wire [31:0] execute_MulPlugin_a; + wire [31:0] execute_MulPlugin_b; + wire [15:0] execute_MulPlugin_aULow; + wire [15:0] execute_MulPlugin_bULow; + wire [16:0] execute_MulPlugin_aSLow; + wire [16:0] execute_MulPlugin_bSLow; + wire [16:0] execute_MulPlugin_aHigh; + wire [16:0] execute_MulPlugin_bHigh; + wire [65:0] writeBack_MulPlugin_result; + reg [32:0] memory_DivPlugin_rs1; + reg [31:0] memory_DivPlugin_rs2; + reg [64:0] memory_DivPlugin_accumulator; + wire memory_DivPlugin_frontendOk; + reg memory_DivPlugin_div_needRevert; + reg memory_DivPlugin_div_counter_willIncrement; + reg memory_DivPlugin_div_counter_willClear; + reg [5:0] memory_DivPlugin_div_counter_valueNext; + reg [5:0] memory_DivPlugin_div_counter_value; + wire memory_DivPlugin_div_counter_willOverflowIfInc; + wire memory_DivPlugin_div_counter_willOverflow; + reg memory_DivPlugin_div_done; + reg [31:0] memory_DivPlugin_div_result; + wire [31:0] _zz_148; + wire [32:0] memory_DivPlugin_div_stage_0_remainderShifted; + wire [32:0] memory_DivPlugin_div_stage_0_remainderMinusDenominator; + wire [31:0] memory_DivPlugin_div_stage_0_outRemainder; + wire [31:0] memory_DivPlugin_div_stage_0_outNumerator; + wire [31:0] _zz_149; + wire _zz_150; + wire _zz_151; + reg [32:0] _zz_152; + wire [1:0] CsrPlugin_misa_base; + wire [25:0] CsrPlugin_misa_extensions; + wire [1:0] CsrPlugin_mtvec_mode; + wire [29:0] CsrPlugin_mtvec_base; + reg [31:0] CsrPlugin_mepc; + reg CsrPlugin_mstatus_MIE; + reg CsrPlugin_mstatus_MPIE; + reg [1:0] CsrPlugin_mstatus_MPP; + reg CsrPlugin_mip_MEIP; + reg CsrPlugin_mip_MTIP; + reg CsrPlugin_mip_MSIP; + reg CsrPlugin_mie_MEIE; + reg CsrPlugin_mie_MTIE; + reg CsrPlugin_mie_MSIE; + reg CsrPlugin_mcause_interrupt; + reg [3:0] CsrPlugin_mcause_exceptionCode; + reg [31:0] CsrPlugin_mtval; + reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; + reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; + wire _zz_153; + wire _zz_154; + wire _zz_155; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code; + reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; + wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; + wire [1:0] _zz_156; + wire _zz_157; + reg CsrPlugin_interrupt_valid; + reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; + reg [1:0] CsrPlugin_interrupt_targetPrivilege; + wire CsrPlugin_exception; + wire CsrPlugin_lastStageWasWfi; + reg CsrPlugin_pipelineLiberator_pcValids_0; + reg CsrPlugin_pipelineLiberator_pcValids_1; + reg CsrPlugin_pipelineLiberator_pcValids_2; + wire CsrPlugin_pipelineLiberator_active; + reg CsrPlugin_pipelineLiberator_done; + wire CsrPlugin_interruptJump /* verilator public */ ; + reg CsrPlugin_hadException /* verilator public */ ; + reg [1:0] CsrPlugin_targetPrivilege; + reg [3:0] CsrPlugin_trapCause; + reg [1:0] CsrPlugin_xtvec_mode; + reg [29:0] CsrPlugin_xtvec_base; + reg execute_CsrPlugin_wfiWake; + wire execute_CsrPlugin_blockedBySideEffects; + reg execute_CsrPlugin_illegalAccess; + reg execute_CsrPlugin_illegalInstruction; + wire [31:0] execute_CsrPlugin_readData; + reg execute_CsrPlugin_writeInstruction; + reg execute_CsrPlugin_readInstruction; + wire execute_CsrPlugin_writeEnable; + wire execute_CsrPlugin_readEnable; + wire [31:0] execute_CsrPlugin_readToWriteData; + reg [31:0] execute_CsrPlugin_writeData; + wire [11:0] execute_CsrPlugin_csrAddress; + reg DebugPlugin_firstCycle; + reg DebugPlugin_secondCycle; + reg DebugPlugin_resetIt; + reg DebugPlugin_haltIt; + reg DebugPlugin_stepIt; + reg DebugPlugin_isPipBusy; + reg DebugPlugin_godmode; + reg DebugPlugin_haltedByBreak; + reg [31:0] DebugPlugin_busReadDataReg; + reg _zz_158; + wire DebugPlugin_allowEBreak; + reg DebugPlugin_resetIt_regNext; + wire execute_BranchPlugin_eq; + wire [2:0] _zz_159; + reg _zz_160; + reg _zz_161; + wire _zz_162; + reg [19:0] _zz_163; + wire _zz_164; + reg [10:0] _zz_165; + wire _zz_166; + reg [18:0] _zz_167; + reg _zz_168; + wire execute_BranchPlugin_missAlignedTarget; + reg [31:0] execute_BranchPlugin_branch_src1; + reg [31:0] execute_BranchPlugin_branch_src2; + wire _zz_169; + reg [19:0] _zz_170; + wire _zz_171; + reg [10:0] _zz_172; + wire _zz_173; + reg [18:0] _zz_174; + wire [31:0] execute_BranchPlugin_branchAdder; + reg [31:0] decode_to_execute_PC; + reg [31:0] execute_to_memory_PC; + reg [31:0] memory_to_writeBack_PC; + reg [31:0] decode_to_execute_INSTRUCTION; + reg [31:0] execute_to_memory_INSTRUCTION; + reg [31:0] memory_to_writeBack_INSTRUCTION; + reg [31:0] decode_to_execute_FORMAL_PC_NEXT; + reg [31:0] execute_to_memory_FORMAL_PC_NEXT; + reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; + reg decode_to_execute_PREDICTION_CONTEXT_hazard; + reg [1:0] decode_to_execute_PREDICTION_CONTEXT_line_history; + reg execute_to_memory_PREDICTION_CONTEXT_hazard; + reg [1:0] execute_to_memory_PREDICTION_CONTEXT_line_history; + reg decode_to_execute_MEMORY_FORCE_CONSTISTENCY; + reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL; + reg decode_to_execute_SRC_USE_SUB_LESS; + reg decode_to_execute_MEMORY_ENABLE; + reg execute_to_memory_MEMORY_ENABLE; + reg memory_to_writeBack_MEMORY_ENABLE; + reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; + reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL; + reg decode_to_execute_REGFILE_WRITE_VALID; + reg execute_to_memory_REGFILE_WRITE_VALID; + reg memory_to_writeBack_REGFILE_WRITE_VALID; + reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; + reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; + reg decode_to_execute_MEMORY_WR; + reg execute_to_memory_MEMORY_WR; + reg memory_to_writeBack_MEMORY_WR; + reg decode_to_execute_MEMORY_MANAGMENT; + reg decode_to_execute_IS_SFENCE_VMA; + reg execute_to_memory_IS_SFENCE_VMA; + reg memory_to_writeBack_IS_SFENCE_VMA; + reg decode_to_execute_SRC_LESS_UNSIGNED; + reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; + reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; + reg `ShiftCtrlEnum_defaultEncoding_type execute_to_memory_SHIFT_CTRL; + reg decode_to_execute_IS_MUL; + reg execute_to_memory_IS_MUL; + reg memory_to_writeBack_IS_MUL; + reg decode_to_execute_IS_DIV; + reg execute_to_memory_IS_DIV; + reg decode_to_execute_IS_RS1_SIGNED; + reg decode_to_execute_IS_RS2_SIGNED; + reg decode_to_execute_IS_CSR; + reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; + reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL; + reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL; + reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; + reg `BranchCtrlEnum_defaultEncoding_type execute_to_memory_BRANCH_CTRL; + reg [31:0] decode_to_execute_RS1; + reg [31:0] decode_to_execute_RS2; + reg decode_to_execute_SRC2_FORCE_ZERO; + reg decode_to_execute_CSR_WRITE_OPCODE; + reg decode_to_execute_CSR_READ_OPCODE; + reg decode_to_execute_DO_EBREAK; + reg decode_to_execute_PREDICTION_HAD_BRANCHED2; + reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW; + reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW; + reg execute_to_memory_IS_DBUS_SHARING; + reg memory_to_writeBack_IS_DBUS_SHARING; + reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; + reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; + reg [31:0] execute_to_memory_SHIFT_RIGHT; + reg [31:0] execute_to_memory_MUL_LL; + reg [33:0] execute_to_memory_MUL_LH; + reg [33:0] execute_to_memory_MUL_HL; + reg [33:0] execute_to_memory_MUL_HH; + reg [33:0] memory_to_writeBack_MUL_HH; + reg execute_to_memory_BRANCH_DO; + reg [31:0] execute_to_memory_BRANCH_CALC; + reg [51:0] memory_to_writeBack_MUL_LOW; + reg [2:0] _zz_175; + reg execute_CsrPlugin_csr_768; + reg execute_CsrPlugin_csr_256; + reg execute_CsrPlugin_csr_384; + reg execute_CsrPlugin_csr_836; + reg execute_CsrPlugin_csr_772; + reg execute_CsrPlugin_csr_833; + reg execute_CsrPlugin_csr_834; + reg execute_CsrPlugin_csr_835; + reg [31:0] _zz_176; + reg [31:0] _zz_177; + reg [31:0] _zz_178; + reg [31:0] _zz_179; + reg [31:0] _zz_180; + reg [31:0] _zz_181; + reg [31:0] _zz_182; + reg [31:0] _zz_183; + `ifndef SYNTHESIS + reg [31:0] _zz_1_string; + reg [31:0] _zz_2_string; + reg [31:0] _zz_3_string; + reg [31:0] _zz_4_string; + reg [31:0] _zz_5_string; + reg [31:0] _zz_6_string; + reg [31:0] _zz_7_string; + reg [31:0] _zz_8_string; + reg [31:0] decode_ENV_CTRL_string; + reg [31:0] _zz_9_string; + reg [31:0] _zz_10_string; + reg [31:0] _zz_11_string; + reg [71:0] _zz_12_string; + reg [71:0] _zz_13_string; + reg [71:0] decode_SHIFT_CTRL_string; + reg [71:0] _zz_14_string; + reg [71:0] _zz_15_string; + reg [71:0] _zz_16_string; + reg [39:0] decode_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_17_string; + reg [39:0] _zz_18_string; + reg [39:0] _zz_19_string; + reg [23:0] decode_SRC2_CTRL_string; + reg [23:0] _zz_20_string; + reg [23:0] _zz_21_string; + reg [23:0] _zz_22_string; + reg [63:0] decode_ALU_CTRL_string; + reg [63:0] _zz_23_string; + reg [63:0] _zz_24_string; + reg [63:0] _zz_25_string; + reg [95:0] decode_SRC1_CTRL_string; + reg [95:0] _zz_26_string; + reg [95:0] _zz_27_string; + reg [95:0] _zz_28_string; + reg [31:0] execute_BRANCH_CTRL_string; + reg [31:0] _zz_29_string; + reg [31:0] memory_ENV_CTRL_string; + reg [31:0] _zz_30_string; + reg [31:0] execute_ENV_CTRL_string; + reg [31:0] _zz_31_string; + reg [31:0] writeBack_ENV_CTRL_string; + reg [31:0] _zz_32_string; + reg [71:0] memory_SHIFT_CTRL_string; + reg [71:0] _zz_35_string; + reg [71:0] execute_SHIFT_CTRL_string; + reg [71:0] _zz_36_string; + reg [23:0] execute_SRC2_CTRL_string; + reg [23:0] _zz_38_string; + reg [95:0] execute_SRC1_CTRL_string; + reg [95:0] _zz_39_string; + reg [63:0] execute_ALU_CTRL_string; + reg [63:0] _zz_40_string; + reg [39:0] execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_41_string; + reg [31:0] _zz_45_string; + reg [31:0] _zz_46_string; + reg [71:0] _zz_47_string; + reg [39:0] _zz_48_string; + reg [23:0] _zz_49_string; + reg [63:0] _zz_50_string; + reg [95:0] _zz_51_string; + reg [31:0] decode_BRANCH_CTRL_string; + reg [31:0] _zz_53_string; + reg [31:0] memory_BRANCH_CTRL_string; + reg [31:0] _zz_54_string; + reg [47:0] MmuPlugin_shared_state_1_string; + reg [95:0] _zz_120_string; + reg [63:0] _zz_121_string; + reg [23:0] _zz_122_string; + reg [39:0] _zz_123_string; + reg [71:0] _zz_124_string; + reg [31:0] _zz_125_string; + reg [31:0] _zz_126_string; + reg [95:0] decode_to_execute_SRC1_CTRL_string; + reg [63:0] decode_to_execute_ALU_CTRL_string; + reg [23:0] decode_to_execute_SRC2_CTRL_string; + reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string; + reg [71:0] decode_to_execute_SHIFT_CTRL_string; + reg [71:0] execute_to_memory_SHIFT_CTRL_string; + reg [31:0] decode_to_execute_ENV_CTRL_string; + reg [31:0] execute_to_memory_ENV_CTRL_string; + reg [31:0] memory_to_writeBack_ENV_CTRL_string; + reg [31:0] decode_to_execute_BRANCH_CTRL_string; + reg [31:0] execute_to_memory_BRANCH_CTRL_string; + `endif + + reg [1:0] _zz_73 [0:1023]; + reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; + + assign _zz_240 = (execute_arbitration_isValid && execute_IS_CSR); + assign _zz_241 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_242 = 1'b1; + assign _zz_243 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_244 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_245 = (memory_arbitration_isValid && memory_IS_DIV); + assign _zz_246 = ((_zz_189 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); + assign _zz_247 = ((_zz_189 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); + assign _zz_248 = ((_zz_189 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); + assign _zz_249 = ((_zz_189 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); + assign _zz_250 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); + assign _zz_251 = (execute_arbitration_isValid && execute_DO_EBREAK); + assign _zz_252 = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) == 1'b0); + assign _zz_253 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign _zz_254 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); + assign _zz_255 = (DebugPlugin_stepIt && IBusCachedPlugin_incomingInstruction); + assign _zz_256 = writeBack_INSTRUCTION[29 : 28]; + assign _zz_257 = (! ({(writeBack_arbitration_isValid || CsrPlugin_exceptionPendings_3),{(memory_arbitration_isValid || CsrPlugin_exceptionPendings_2),(execute_arbitration_isValid || CsrPlugin_exceptionPendings_1)}} != 3'b000)); + assign _zz_258 = (! dataCache_1_io_cpu_execute_refilling); + assign _zz_259 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_260 = ((MmuPlugin_shared_dBusRspStaged_valid && (! MmuPlugin_shared_dBusRspStaged_payload_redo)) && (MmuPlugin_shared_dBusRsp_leaf || MmuPlugin_shared_dBusRsp_exception)); + assign _zz_261 = MmuPlugin_shared_portSortedOh[0]; + assign _zz_262 = MmuPlugin_shared_portSortedOh[1]; + assign _zz_263 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_264 = (1'b0 || (! 1'b1)); + assign _zz_265 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_266 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign _zz_267 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_268 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign _zz_269 = execute_INSTRUCTION[13 : 12]; + assign _zz_270 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); + assign _zz_271 = (! memory_arbitration_isStuck); + assign _zz_272 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign _zz_273 = debug_bus_cmd_payload_address[7 : 2]; + assign _zz_274 = (MmuPlugin_shared_refills != 2'b00); + assign _zz_275 = (MmuPlugin_ports_0_entryToReplace_value == 2'b00); + assign _zz_276 = (MmuPlugin_ports_0_entryToReplace_value == 2'b01); + assign _zz_277 = (MmuPlugin_ports_0_entryToReplace_value == 2'b10); + assign _zz_278 = (MmuPlugin_ports_0_entryToReplace_value == 2'b11); + assign _zz_279 = (MmuPlugin_ports_1_entryToReplace_value == 3'b000); + assign _zz_280 = (MmuPlugin_ports_1_entryToReplace_value == 3'b001); + assign _zz_281 = (MmuPlugin_ports_1_entryToReplace_value == 3'b010); + assign _zz_282 = (MmuPlugin_ports_1_entryToReplace_value == 3'b011); + assign _zz_283 = (MmuPlugin_ports_1_entryToReplace_value == 3'b100); + assign _zz_284 = (MmuPlugin_ports_1_entryToReplace_value == 3'b101); + assign _zz_285 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign _zz_286 = ((_zz_153 && 1'b1) && (! 1'b0)); + assign _zz_287 = ((_zz_154 && 1'b1) && (! 1'b0)); + assign _zz_288 = ((_zz_155 && 1'b1) && (! 1'b0)); + assign _zz_289 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_290 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_291 = execute_INSTRUCTION[13]; + assign _zz_292 = ($signed(_zz_293) + $signed(_zz_298)); + assign _zz_293 = ($signed(_zz_294) + $signed(_zz_296)); + assign _zz_294 = 52'h0; + assign _zz_295 = {1'b0,memory_MUL_LL}; + assign _zz_296 = {{19{_zz_295[32]}}, _zz_295}; + assign _zz_297 = ({16'd0,memory_MUL_LH} <<< 16); + assign _zz_298 = {{2{_zz_297[49]}}, _zz_297}; + assign _zz_299 = ({16'd0,memory_MUL_HL} <<< 16); + assign _zz_300 = {{2{_zz_299[49]}}, _zz_299}; + assign _zz_301 = ($signed(_zz_303) >>> execute_FullBarrelShifterPlugin_amplitude); + assign _zz_302 = _zz_301[31 : 0]; + assign _zz_303 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; + assign _zz_304 = _zz_115[28 : 28]; + assign _zz_305 = _zz_115[27 : 27]; + assign _zz_306 = _zz_115[26 : 26]; + assign _zz_307 = _zz_115[25 : 25]; + assign _zz_308 = _zz_115[24 : 24]; + assign _zz_309 = _zz_115[18 : 18]; + assign _zz_310 = _zz_115[17 : 17]; + assign _zz_311 = _zz_115[16 : 16]; + assign _zz_312 = _zz_115[13 : 13]; + assign _zz_313 = _zz_115[12 : 12]; + assign _zz_314 = _zz_115[11 : 11]; + assign _zz_315 = _zz_115[30 : 30]; + assign _zz_316 = _zz_115[15 : 15]; + assign _zz_317 = _zz_115[5 : 5]; + assign _zz_318 = _zz_115[3 : 3]; + assign _zz_319 = _zz_115[21 : 21]; + assign _zz_320 = _zz_115[10 : 10]; + assign _zz_321 = _zz_115[4 : 4]; + assign _zz_322 = _zz_115[0 : 0]; + assign _zz_323 = (_zz_59 - 4'b0001); + assign _zz_324 = {IBusCachedPlugin_fetchPc_inc,2'b00}; + assign _zz_325 = {29'd0, _zz_324}; + assign _zz_326 = ($signed(memory_PREDICTION_CONTEXT_line_history) + $signed(_zz_327)); + assign _zz_327 = (_zz_82 ? _zz_328 : _zz_329); + assign _zz_328 = 2'b11; + assign _zz_329 = 2'b01; + assign _zz_330 = _zz_78[9:0]; + assign _zz_331 = (IBusCachedPlugin_iBusRsp_stages_0_input_payload >>> 2); + assign _zz_332 = _zz_331[9:0]; + assign _zz_333 = (_zz_82 ? _zz_334 : _zz_335); + assign _zz_334 = 2'b10; + assign _zz_335 = 2'b01; + assign _zz_336 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_337 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_338 = {{_zz_84,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_339 = {{_zz_86,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_340 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_341 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_342 = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); + assign _zz_343 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); + assign _zz_344 = MmuPlugin_ports_0_entryToReplace_willIncrement; + assign _zz_345 = {1'd0, _zz_344}; + assign _zz_346 = MmuPlugin_ports_1_entryToReplace_willIncrement; + assign _zz_347 = {2'd0, _zz_346}; + assign _zz_348 = MmuPlugin_shared_dBusRspStaged_payload_data[0 : 0]; + assign _zz_349 = MmuPlugin_shared_dBusRspStaged_payload_data[1 : 1]; + assign _zz_350 = MmuPlugin_shared_dBusRspStaged_payload_data[2 : 2]; + assign _zz_351 = MmuPlugin_shared_dBusRspStaged_payload_data[3 : 3]; + assign _zz_352 = MmuPlugin_shared_dBusRspStaged_payload_data[4 : 4]; + assign _zz_353 = MmuPlugin_shared_dBusRspStaged_payload_data[5 : 5]; + assign _zz_354 = MmuPlugin_shared_dBusRspStaged_payload_data[6 : 6]; + assign _zz_355 = MmuPlugin_shared_dBusRspStaged_payload_data[7 : 7]; + assign _zz_356 = (_zz_111 - 2'b01); + assign _zz_357 = execute_SRC_LESS; + assign _zz_358 = 3'b100; + assign _zz_359 = execute_INSTRUCTION[19 : 15]; + assign _zz_360 = execute_INSTRUCTION[31 : 20]; + assign _zz_361 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_362 = ($signed(_zz_363) + $signed(_zz_366)); + assign _zz_363 = ($signed(_zz_364) + $signed(_zz_365)); + assign _zz_364 = execute_SRC1; + assign _zz_365 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_366 = (execute_SRC_USE_SUB_LESS ? _zz_367 : _zz_368); + assign _zz_367 = 32'h00000001; + assign _zz_368 = 32'h0; + assign _zz_369 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; + assign _zz_370 = ({32'd0,writeBack_MUL_HH} <<< 32); + assign _zz_371 = writeBack_MUL_LOW[31 : 0]; + assign _zz_372 = writeBack_MulPlugin_result[63 : 32]; + assign _zz_373 = memory_DivPlugin_div_counter_willIncrement; + assign _zz_374 = {5'd0, _zz_373}; + assign _zz_375 = {1'd0, memory_DivPlugin_rs2}; + assign _zz_376 = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; + assign _zz_377 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; + assign _zz_378 = {_zz_148,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; + assign _zz_379 = _zz_380; + assign _zz_380 = _zz_381; + assign _zz_381 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_149) : _zz_149)} + _zz_383); + assign _zz_382 = memory_DivPlugin_div_needRevert; + assign _zz_383 = {32'd0, _zz_382}; + assign _zz_384 = _zz_151; + assign _zz_385 = {32'd0, _zz_384}; + assign _zz_386 = _zz_150; + assign _zz_387 = {31'd0, _zz_386}; + assign _zz_388 = (_zz_156 & (~ _zz_389)); + assign _zz_389 = (_zz_156 - 2'b01); + assign _zz_390 = execute_INSTRUCTION[31 : 20]; + assign _zz_391 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_392 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_393 = {_zz_163,execute_INSTRUCTION[31 : 20]}; + assign _zz_394 = {{_zz_165,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_395 = {{_zz_167,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_396 = execute_INSTRUCTION[31 : 20]; + assign _zz_397 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_398 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_399 = 3'b100; + assign _zz_400 = execute_CsrPlugin_writeData[19 : 19]; + assign _zz_401 = execute_CsrPlugin_writeData[18 : 18]; + assign _zz_402 = execute_CsrPlugin_writeData[17 : 17]; + assign _zz_403 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_404 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_405 = execute_CsrPlugin_writeData[19 : 19]; + assign _zz_406 = execute_CsrPlugin_writeData[18 : 18]; + assign _zz_407 = execute_CsrPlugin_writeData[17 : 17]; + assign _zz_408 = execute_CsrPlugin_writeData[31 : 31]; + assign _zz_409 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_410 = execute_CsrPlugin_writeData[11 : 11]; + assign _zz_411 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_412 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_413 = _zz_326; + assign _zz_414 = 1'b1; + assign _zz_415 = 1'b1; + assign _zz_416 = {_zz_63,_zz_62}; + assign _zz_417 = 32'h0000107f; + assign _zz_418 = (decode_INSTRUCTION & 32'h0000207f); + assign _zz_419 = 32'h00002073; + assign _zz_420 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_421 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013); + assign _zz_422 = {((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003),{((decode_INSTRUCTION & _zz_423) == 32'h00000003),{(_zz_424 == _zz_425),{_zz_426,{_zz_427,_zz_428}}}}}}; + assign _zz_423 = 32'h0000505f; + assign _zz_424 = (decode_INSTRUCTION & 32'h0000707b); + assign _zz_425 = 32'h00000063; + assign _zz_426 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_427 = ((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033); + assign _zz_428 = {((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & 32'hbc00707f) == 32'h00005013),{((decode_INSTRUCTION & _zz_429) == 32'h00001013),{(_zz_430 == _zz_431),{_zz_432,{_zz_433,_zz_434}}}}}}; + assign _zz_429 = 32'hfc00307f; + assign _zz_430 = (decode_INSTRUCTION & 32'hbe00707f); + assign _zz_431 = 32'h00005033; + assign _zz_432 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); + assign _zz_433 = ((decode_INSTRUCTION & 32'hfe007fff) == 32'h12000073); + assign _zz_434 = {((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073),((decode_INSTRUCTION & 32'hffffffff) == 32'h00100073)}; + assign _zz_435 = decode_INSTRUCTION[31]; + assign _zz_436 = decode_INSTRUCTION[31]; + assign _zz_437 = decode_INSTRUCTION[7]; + assign _zz_438 = (decode_INSTRUCTION & 32'h0000001c); + assign _zz_439 = 32'h00000004; + assign _zz_440 = (decode_INSTRUCTION & 32'h00000058); + assign _zz_441 = 32'h00000040; + assign _zz_442 = ((decode_INSTRUCTION & 32'h10003050) == 32'h00000050); + assign _zz_443 = ((decode_INSTRUCTION & 32'h02103050) == 32'h00000050); + assign _zz_444 = 1'b0; + assign _zz_445 = ({(_zz_448 == _zz_449),(_zz_450 == _zz_451)} != 2'b00); + assign _zz_446 = (_zz_119 != 1'b0); + assign _zz_447 = {(_zz_119 != 1'b0),{(_zz_452 != _zz_453),{_zz_454,{_zz_455,_zz_456}}}}; + assign _zz_448 = (decode_INSTRUCTION & 32'h00001050); + assign _zz_449 = 32'h00001050; + assign _zz_450 = (decode_INSTRUCTION & 32'h00002050); + assign _zz_451 = 32'h00002050; + assign _zz_452 = ((decode_INSTRUCTION & 32'h02004064) == 32'h02004020); + assign _zz_453 = 1'b0; + assign _zz_454 = (((decode_INSTRUCTION & _zz_457) == 32'h02000030) != 1'b0); + assign _zz_455 = ({_zz_458,_zz_459} != 2'b00); + assign _zz_456 = {({_zz_460,_zz_461} != 3'b000),{(_zz_462 != _zz_463),{_zz_464,{_zz_465,_zz_466}}}}; + assign _zz_457 = 32'h02004074; + assign _zz_458 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00005010); + assign _zz_459 = ((decode_INSTRUCTION & 32'h02007064) == 32'h00005020); + assign _zz_460 = ((decode_INSTRUCTION & _zz_467) == 32'h40001010); + assign _zz_461 = {(_zz_468 == _zz_469),(_zz_470 == _zz_471)}; + assign _zz_462 = ((decode_INSTRUCTION & _zz_472) == 32'h00000024); + assign _zz_463 = 1'b0; + assign _zz_464 = ((_zz_473 == _zz_474) != 1'b0); + assign _zz_465 = (_zz_475 != 1'b0); + assign _zz_466 = {(_zz_476 != _zz_477),{_zz_478,{_zz_479,_zz_480}}}; + assign _zz_467 = 32'h40003054; + assign _zz_468 = (decode_INSTRUCTION & 32'h00007034); + assign _zz_469 = 32'h00001010; + assign _zz_470 = (decode_INSTRUCTION & 32'h02007054); + assign _zz_471 = 32'h00001010; + assign _zz_472 = 32'h00000064; + assign _zz_473 = (decode_INSTRUCTION & 32'h00001000); + assign _zz_474 = 32'h00001000; + assign _zz_475 = ((decode_INSTRUCTION & 32'h00003000) == 32'h00002000); + assign _zz_476 = {(_zz_481 == _zz_482),(_zz_483 == _zz_484)}; + assign _zz_477 = 2'b00; + assign _zz_478 = ((_zz_485 == _zz_486) != 1'b0); + assign _zz_479 = (_zz_487 != 1'b0); + assign _zz_480 = {(_zz_488 != _zz_489),{_zz_490,{_zz_491,_zz_492}}}; + assign _zz_481 = (decode_INSTRUCTION & 32'h00002010); + assign _zz_482 = 32'h00002000; + assign _zz_483 = (decode_INSTRUCTION & 32'h00005000); + assign _zz_484 = 32'h00001000; + assign _zz_485 = (decode_INSTRUCTION & 32'h02003050); + assign _zz_486 = 32'h02000050; + assign _zz_487 = ((decode_INSTRUCTION & 32'h00004048) == 32'h00004008); + assign _zz_488 = {(_zz_493 == _zz_494),(_zz_495 == _zz_496)}; + assign _zz_489 = 2'b00; + assign _zz_490 = ({_zz_497,{_zz_498,_zz_499}} != 3'b000); + assign _zz_491 = (_zz_500 != 1'b0); + assign _zz_492 = {(_zz_501 != _zz_502),{_zz_503,{_zz_504,_zz_505}}}; + assign _zz_493 = (decode_INSTRUCTION & 32'h00000034); + assign _zz_494 = 32'h00000020; + assign _zz_495 = (decode_INSTRUCTION & 32'h00000064); + assign _zz_496 = 32'h00000020; + assign _zz_497 = ((decode_INSTRUCTION & 32'h00000050) == 32'h00000040); + assign _zz_498 = ((decode_INSTRUCTION & _zz_506) == 32'h0); + assign _zz_499 = ((decode_INSTRUCTION & _zz_507) == 32'h00000040); + assign _zz_500 = ((decode_INSTRUCTION & 32'h00000020) == 32'h00000020); + assign _zz_501 = {(_zz_508 == _zz_509),{_zz_117,{_zz_510,_zz_511}}}; + assign _zz_502 = 5'h0; + assign _zz_503 = ({_zz_117,{_zz_512,_zz_513}} != 5'h0); + assign _zz_504 = ({_zz_514,_zz_515} != 6'h0); + assign _zz_505 = {(_zz_516 != _zz_517),{_zz_518,{_zz_519,_zz_520}}}; + assign _zz_506 = 32'h00000038; + assign _zz_507 = 32'h02103040; + assign _zz_508 = (decode_INSTRUCTION & 32'h00000040); + assign _zz_509 = 32'h00000040; + assign _zz_510 = (_zz_521 == _zz_522); + assign _zz_511 = {_zz_523,_zz_524}; + assign _zz_512 = (_zz_525 == _zz_526); + assign _zz_513 = {_zz_527,{_zz_528,_zz_529}}; + assign _zz_514 = _zz_118; + assign _zz_515 = {_zz_530,{_zz_531,_zz_532}}; + assign _zz_516 = {_zz_117,_zz_533}; + assign _zz_517 = 2'b00; + assign _zz_518 = ({_zz_534,_zz_535} != 2'b00); + assign _zz_519 = (_zz_536 != _zz_537); + assign _zz_520 = {_zz_538,{_zz_539,_zz_540}}; + assign _zz_521 = (decode_INSTRUCTION & 32'h00004020); + assign _zz_522 = 32'h00004020; + assign _zz_523 = ((decode_INSTRUCTION & _zz_541) == 32'h00000010); + assign _zz_524 = ((decode_INSTRUCTION & _zz_542) == 32'h00000020); + assign _zz_525 = (decode_INSTRUCTION & 32'h00002030); + assign _zz_526 = 32'h00002010; + assign _zz_527 = ((decode_INSTRUCTION & _zz_543) == 32'h00000010); + assign _zz_528 = (_zz_544 == _zz_545); + assign _zz_529 = (_zz_546 == _zz_547); + assign _zz_530 = ((decode_INSTRUCTION & _zz_548) == 32'h00001010); + assign _zz_531 = (_zz_549 == _zz_550); + assign _zz_532 = {_zz_551,{_zz_552,_zz_553}}; + assign _zz_533 = ((decode_INSTRUCTION & _zz_554) == 32'h00000020); + assign _zz_534 = _zz_117; + assign _zz_535 = (_zz_555 == _zz_556); + assign _zz_536 = (_zz_557 == _zz_558); + assign _zz_537 = 1'b0; + assign _zz_538 = (_zz_559 != 1'b0); + assign _zz_539 = (_zz_560 != _zz_561); + assign _zz_540 = {_zz_562,{_zz_563,_zz_564}}; + assign _zz_541 = 32'h00000030; + assign _zz_542 = 32'h02000020; + assign _zz_543 = 32'h00001030; + assign _zz_544 = (decode_INSTRUCTION & 32'h02002060); + assign _zz_545 = 32'h00002020; + assign _zz_546 = (decode_INSTRUCTION & 32'h02003020); + assign _zz_547 = 32'h00000020; + assign _zz_548 = 32'h00001010; + assign _zz_549 = (decode_INSTRUCTION & 32'h00002010); + assign _zz_550 = 32'h00002010; + assign _zz_551 = ((decode_INSTRUCTION & _zz_565) == 32'h00000010); + assign _zz_552 = (_zz_566 == _zz_567); + assign _zz_553 = (_zz_568 == _zz_569); + assign _zz_554 = 32'h00000070; + assign _zz_555 = (decode_INSTRUCTION & 32'h00000020); + assign _zz_556 = 32'h0; + assign _zz_557 = (decode_INSTRUCTION & 32'h00004014); + assign _zz_558 = 32'h00004010; + assign _zz_559 = ((decode_INSTRUCTION & _zz_570) == 32'h00002010); + assign _zz_560 = {_zz_571,{_zz_572,_zz_573}}; + assign _zz_561 = 4'b0000; + assign _zz_562 = (_zz_574 != 1'b0); + assign _zz_563 = (_zz_575 != _zz_576); + assign _zz_564 = {_zz_577,{_zz_578,_zz_579}}; + assign _zz_565 = 32'h00000050; + assign _zz_566 = (decode_INSTRUCTION & 32'h0000000c); + assign _zz_567 = 32'h00000004; + assign _zz_568 = (decode_INSTRUCTION & 32'h00000028); + assign _zz_569 = 32'h0; + assign _zz_570 = 32'h00006014; + assign _zz_571 = ((decode_INSTRUCTION & 32'h00000044) == 32'h0); + assign _zz_572 = ((decode_INSTRUCTION & _zz_580) == 32'h0); + assign _zz_573 = {(_zz_581 == _zz_582),(_zz_583 == _zz_584)}; + assign _zz_574 = ((decode_INSTRUCTION & 32'h00000058) == 32'h0); + assign _zz_575 = {(_zz_585 == _zz_586),{_zz_587,_zz_588}}; + assign _zz_576 = 3'b000; + assign _zz_577 = ({_zz_589,_zz_116} != 2'b00); + assign _zz_578 = ({_zz_590,_zz_591} != 2'b00); + assign _zz_579 = (_zz_592 != 1'b0); + assign _zz_580 = 32'h00000018; + assign _zz_581 = (decode_INSTRUCTION & 32'h00006004); + assign _zz_582 = 32'h00002000; + assign _zz_583 = (decode_INSTRUCTION & 32'h00005004); + assign _zz_584 = 32'h00001000; + assign _zz_585 = (decode_INSTRUCTION & 32'h00000044); + assign _zz_586 = 32'h00000040; + assign _zz_587 = ((decode_INSTRUCTION & 32'h00002014) == 32'h00002010); + assign _zz_588 = ((decode_INSTRUCTION & 32'h40000034) == 32'h40000030); + assign _zz_589 = ((decode_INSTRUCTION & 32'h00000014) == 32'h00000004); + assign _zz_590 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000004); + assign _zz_591 = _zz_116; + assign _zz_592 = ((decode_INSTRUCTION & 32'h00005048) == 32'h00001008); + assign _zz_593 = execute_INSTRUCTION[31]; + assign _zz_594 = execute_INSTRUCTION[31]; + assign _zz_595 = execute_INSTRUCTION[7]; + always @ (posedge clk) begin + if(_zz_55) begin + _zz_73[_zz_75] <= _zz_413; + end + end + + always @ (posedge clk) begin + if(_zz_79) begin + _zz_214 <= _zz_73[_zz_330]; + end + end + + always @ (posedge clk) begin + if(_zz_414) begin + _zz_215 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + end + end + + always @ (posedge clk) begin + if(_zz_415) begin + _zz_216 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + end + end + + always @ (posedge clk) begin + if(_zz_44) begin + RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; + end + end + + InstructionCache IBusCachedPlugin_cache ( + .io_flush (_zz_184 ), //i + .io_cpu_prefetch_isValid (_zz_185 ), //i + .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o + .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload[31:0] ), //i + .io_cpu_fetch_isValid (_zz_186 ), //i + .io_cpu_fetch_isStuck (_zz_187 ), //i + .io_cpu_fetch_isRemoved (_zz_188 ), //i + .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload[31:0] ), //i + .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data[31:0] ), //o + .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i + .io_cpu_fetch_mmuRsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i + .io_cpu_fetch_mmuRsp_isPaging (IBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_fetch_mmuRsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_fetch_mmuRsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_fetch_mmuRsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_fetch_mmuRsp_exception (IBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_fetch_mmuRsp_ways_0_sel (IBusCachedPlugin_mmuBus_rsp_ways_0_sel ), //i + .io_cpu_fetch_mmuRsp_ways_0_physical (IBusCachedPlugin_mmuBus_rsp_ways_0_physical[31:0] ), //i + .io_cpu_fetch_mmuRsp_ways_1_sel (IBusCachedPlugin_mmuBus_rsp_ways_1_sel ), //i + .io_cpu_fetch_mmuRsp_ways_1_physical (IBusCachedPlugin_mmuBus_rsp_ways_1_physical[31:0] ), //i + .io_cpu_fetch_mmuRsp_ways_2_sel (IBusCachedPlugin_mmuBus_rsp_ways_2_sel ), //i + .io_cpu_fetch_mmuRsp_ways_2_physical (IBusCachedPlugin_mmuBus_rsp_ways_2_physical[31:0] ), //i + .io_cpu_fetch_mmuRsp_ways_3_sel (IBusCachedPlugin_mmuBus_rsp_ways_3_sel ), //i + .io_cpu_fetch_mmuRsp_ways_3_physical (IBusCachedPlugin_mmuBus_rsp_ways_3_physical[31:0] ), //i + .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //o + .io_cpu_decode_isValid (_zz_189 ), //i + .io_cpu_decode_isStuck (_zz_190 ), //i + .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload[31:0] ), //i + .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //o + .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data[31:0] ), //o + .io_cpu_decode_cacheMiss (IBusCachedPlugin_cache_io_cpu_decode_cacheMiss ), //o + .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o + .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o + .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o + .io_cpu_decode_isUser (_zz_191 ), //i + .io_cpu_fill_valid (_zz_192 ), //i + .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //i + .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (iBus_cmd_ready ), //i + .io_mem_cmd_payload_address (IBusCachedPlugin_cache_io_mem_cmd_payload_address[31:0] ), //o + .io_mem_cmd_payload_size (IBusCachedPlugin_cache_io_mem_cmd_payload_size[2:0] ), //o + .io_mem_rsp_valid (iBus_rsp_valid ), //i + .io_mem_rsp_payload_data (iBus_rsp_payload_data[31:0] ), //i + .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i + ._zz_10 (_zz_175[2:0] ), //i + ._zz_11 (IBusCachedPlugin_injectionPort_payload[31:0] ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + DataCache dataCache_1 ( + .io_cpu_execute_isValid (_zz_193 ), //i + .io_cpu_execute_address (_zz_194[31:0] ), //i + .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o + .io_cpu_execute_args_wr (_zz_195 ), //i + .io_cpu_execute_args_data (_zz_196[31:0] ), //i + .io_cpu_execute_args_size (_zz_197[1:0] ), //i + .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i + .io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o + .io_cpu_memory_isValid (_zz_198 ), //i + .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i + .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o + .io_cpu_memory_address (_zz_199[31:0] ), //i + .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i + .io_cpu_memory_mmuRsp_isIoAccess (_zz_200 ), //i + .io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_memory_mmuRsp_allowExecute (DBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_memory_mmuRsp_ways_0_sel (DBusCachedPlugin_mmuBus_rsp_ways_0_sel ), //i + .io_cpu_memory_mmuRsp_ways_0_physical (DBusCachedPlugin_mmuBus_rsp_ways_0_physical[31:0] ), //i + .io_cpu_memory_mmuRsp_ways_1_sel (DBusCachedPlugin_mmuBus_rsp_ways_1_sel ), //i + .io_cpu_memory_mmuRsp_ways_1_physical (DBusCachedPlugin_mmuBus_rsp_ways_1_physical[31:0] ), //i + .io_cpu_memory_mmuRsp_ways_2_sel (DBusCachedPlugin_mmuBus_rsp_ways_2_sel ), //i + .io_cpu_memory_mmuRsp_ways_2_physical (DBusCachedPlugin_mmuBus_rsp_ways_2_physical[31:0] ), //i + .io_cpu_memory_mmuRsp_ways_3_sel (DBusCachedPlugin_mmuBus_rsp_ways_3_sel ), //i + .io_cpu_memory_mmuRsp_ways_3_physical (DBusCachedPlugin_mmuBus_rsp_ways_3_physical[31:0] ), //i + .io_cpu_memory_mmuRsp_ways_4_sel (DBusCachedPlugin_mmuBus_rsp_ways_4_sel ), //i + .io_cpu_memory_mmuRsp_ways_4_physical (DBusCachedPlugin_mmuBus_rsp_ways_4_physical[31:0] ), //i + .io_cpu_memory_mmuRsp_ways_5_sel (DBusCachedPlugin_mmuBus_rsp_ways_5_sel ), //i + .io_cpu_memory_mmuRsp_ways_5_physical (DBusCachedPlugin_mmuBus_rsp_ways_5_physical[31:0] ), //i + .io_cpu_writeBack_isValid (_zz_201 ), //i + .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i + .io_cpu_writeBack_isUser (_zz_202 ), //i + .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o + .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o + .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data[31:0] ), //o + .io_cpu_writeBack_address (_zz_203[31:0] ), //i + .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o + .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o + .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o + .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o + .io_cpu_writeBack_fence_SW (_zz_204 ), //i + .io_cpu_writeBack_fence_SR (_zz_205 ), //i + .io_cpu_writeBack_fence_SO (_zz_206 ), //i + .io_cpu_writeBack_fence_SI (_zz_207 ), //i + .io_cpu_writeBack_fence_PW (_zz_208 ), //i + .io_cpu_writeBack_fence_PR (_zz_209 ), //i + .io_cpu_writeBack_fence_PO (_zz_210 ), //i + .io_cpu_writeBack_fence_PI (_zz_211 ), //i + .io_cpu_writeBack_fence_FM (_zz_212[3:0] ), //i + .io_cpu_redo (dataCache_1_io_cpu_redo ), //o + .io_cpu_flush_valid (_zz_213 ), //i + .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o + .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (dBus_cmd_ready ), //i + .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o + .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o + .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address[31:0] ), //o + .io_mem_cmd_payload_data (dataCache_1_io_mem_cmd_payload_data[31:0] ), //o + .io_mem_cmd_payload_mask (dataCache_1_io_mem_cmd_payload_mask[3:0] ), //o + .io_mem_cmd_payload_length (dataCache_1_io_mem_cmd_payload_length[2:0] ), //o + .io_mem_cmd_payload_last (dataCache_1_io_mem_cmd_payload_last ), //o + .io_mem_rsp_valid (dBus_rsp_valid ), //i + .io_mem_rsp_payload_last (dBus_rsp_payload_last ), //i + .io_mem_rsp_payload_data (dBus_rsp_payload_data[31:0] ), //i + .io_mem_rsp_payload_error (dBus_rsp_payload_error ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + always @(*) begin + case(_zz_416) + 2'b00 : begin + _zz_217 = DBusCachedPlugin_redoBranch_payload; + end + 2'b01 : begin + _zz_217 = CsrPlugin_jumpInterface_payload; + end + 2'b10 : begin + _zz_217 = BranchPlugin_jumpInterface_payload; + end + default : begin + _zz_217 = IBusCachedPlugin_predictionJumpInterface_payload; + end + endcase + end + + always @(*) begin + case(_zz_102) + 2'b00 : begin + _zz_218 = MmuPlugin_ports_0_cache_0_valid; + _zz_219 = MmuPlugin_ports_0_cache_0_exception; + _zz_220 = MmuPlugin_ports_0_cache_0_superPage; + _zz_221 = MmuPlugin_ports_0_cache_0_virtualAddress_0; + _zz_222 = MmuPlugin_ports_0_cache_0_virtualAddress_1; + _zz_223 = MmuPlugin_ports_0_cache_0_physicalAddress_0; + _zz_224 = MmuPlugin_ports_0_cache_0_physicalAddress_1; + _zz_225 = MmuPlugin_ports_0_cache_0_allowRead; + _zz_226 = MmuPlugin_ports_0_cache_0_allowWrite; + _zz_227 = MmuPlugin_ports_0_cache_0_allowExecute; + _zz_228 = MmuPlugin_ports_0_cache_0_allowUser; + end + 2'b01 : begin + _zz_218 = MmuPlugin_ports_0_cache_1_valid; + _zz_219 = MmuPlugin_ports_0_cache_1_exception; + _zz_220 = MmuPlugin_ports_0_cache_1_superPage; + _zz_221 = MmuPlugin_ports_0_cache_1_virtualAddress_0; + _zz_222 = MmuPlugin_ports_0_cache_1_virtualAddress_1; + _zz_223 = MmuPlugin_ports_0_cache_1_physicalAddress_0; + _zz_224 = MmuPlugin_ports_0_cache_1_physicalAddress_1; + _zz_225 = MmuPlugin_ports_0_cache_1_allowRead; + _zz_226 = MmuPlugin_ports_0_cache_1_allowWrite; + _zz_227 = MmuPlugin_ports_0_cache_1_allowExecute; + _zz_228 = MmuPlugin_ports_0_cache_1_allowUser; + end + 2'b10 : begin + _zz_218 = MmuPlugin_ports_0_cache_2_valid; + _zz_219 = MmuPlugin_ports_0_cache_2_exception; + _zz_220 = MmuPlugin_ports_0_cache_2_superPage; + _zz_221 = MmuPlugin_ports_0_cache_2_virtualAddress_0; + _zz_222 = MmuPlugin_ports_0_cache_2_virtualAddress_1; + _zz_223 = MmuPlugin_ports_0_cache_2_physicalAddress_0; + _zz_224 = MmuPlugin_ports_0_cache_2_physicalAddress_1; + _zz_225 = MmuPlugin_ports_0_cache_2_allowRead; + _zz_226 = MmuPlugin_ports_0_cache_2_allowWrite; + _zz_227 = MmuPlugin_ports_0_cache_2_allowExecute; + _zz_228 = MmuPlugin_ports_0_cache_2_allowUser; + end + default : begin + _zz_218 = MmuPlugin_ports_0_cache_3_valid; + _zz_219 = MmuPlugin_ports_0_cache_3_exception; + _zz_220 = MmuPlugin_ports_0_cache_3_superPage; + _zz_221 = MmuPlugin_ports_0_cache_3_virtualAddress_0; + _zz_222 = MmuPlugin_ports_0_cache_3_virtualAddress_1; + _zz_223 = MmuPlugin_ports_0_cache_3_physicalAddress_0; + _zz_224 = MmuPlugin_ports_0_cache_3_physicalAddress_1; + _zz_225 = MmuPlugin_ports_0_cache_3_allowRead; + _zz_226 = MmuPlugin_ports_0_cache_3_allowWrite; + _zz_227 = MmuPlugin_ports_0_cache_3_allowExecute; + _zz_228 = MmuPlugin_ports_0_cache_3_allowUser; + end + endcase + end + + always @(*) begin + case(_zz_108) + 3'b000 : begin + _zz_229 = MmuPlugin_ports_1_cache_0_valid; + _zz_230 = MmuPlugin_ports_1_cache_0_exception; + _zz_231 = MmuPlugin_ports_1_cache_0_superPage; + _zz_232 = MmuPlugin_ports_1_cache_0_virtualAddress_0; + _zz_233 = MmuPlugin_ports_1_cache_0_virtualAddress_1; + _zz_234 = MmuPlugin_ports_1_cache_0_physicalAddress_0; + _zz_235 = MmuPlugin_ports_1_cache_0_physicalAddress_1; + _zz_236 = MmuPlugin_ports_1_cache_0_allowRead; + _zz_237 = MmuPlugin_ports_1_cache_0_allowWrite; + _zz_238 = MmuPlugin_ports_1_cache_0_allowExecute; + _zz_239 = MmuPlugin_ports_1_cache_0_allowUser; + end + 3'b001 : begin + _zz_229 = MmuPlugin_ports_1_cache_1_valid; + _zz_230 = MmuPlugin_ports_1_cache_1_exception; + _zz_231 = MmuPlugin_ports_1_cache_1_superPage; + _zz_232 = MmuPlugin_ports_1_cache_1_virtualAddress_0; + _zz_233 = MmuPlugin_ports_1_cache_1_virtualAddress_1; + _zz_234 = MmuPlugin_ports_1_cache_1_physicalAddress_0; + _zz_235 = MmuPlugin_ports_1_cache_1_physicalAddress_1; + _zz_236 = MmuPlugin_ports_1_cache_1_allowRead; + _zz_237 = MmuPlugin_ports_1_cache_1_allowWrite; + _zz_238 = MmuPlugin_ports_1_cache_1_allowExecute; + _zz_239 = MmuPlugin_ports_1_cache_1_allowUser; + end + 3'b010 : begin + _zz_229 = MmuPlugin_ports_1_cache_2_valid; + _zz_230 = MmuPlugin_ports_1_cache_2_exception; + _zz_231 = MmuPlugin_ports_1_cache_2_superPage; + _zz_232 = MmuPlugin_ports_1_cache_2_virtualAddress_0; + _zz_233 = MmuPlugin_ports_1_cache_2_virtualAddress_1; + _zz_234 = MmuPlugin_ports_1_cache_2_physicalAddress_0; + _zz_235 = MmuPlugin_ports_1_cache_2_physicalAddress_1; + _zz_236 = MmuPlugin_ports_1_cache_2_allowRead; + _zz_237 = MmuPlugin_ports_1_cache_2_allowWrite; + _zz_238 = MmuPlugin_ports_1_cache_2_allowExecute; + _zz_239 = MmuPlugin_ports_1_cache_2_allowUser; + end + 3'b011 : begin + _zz_229 = MmuPlugin_ports_1_cache_3_valid; + _zz_230 = MmuPlugin_ports_1_cache_3_exception; + _zz_231 = MmuPlugin_ports_1_cache_3_superPage; + _zz_232 = MmuPlugin_ports_1_cache_3_virtualAddress_0; + _zz_233 = MmuPlugin_ports_1_cache_3_virtualAddress_1; + _zz_234 = MmuPlugin_ports_1_cache_3_physicalAddress_0; + _zz_235 = MmuPlugin_ports_1_cache_3_physicalAddress_1; + _zz_236 = MmuPlugin_ports_1_cache_3_allowRead; + _zz_237 = MmuPlugin_ports_1_cache_3_allowWrite; + _zz_238 = MmuPlugin_ports_1_cache_3_allowExecute; + _zz_239 = MmuPlugin_ports_1_cache_3_allowUser; + end + 3'b100 : begin + _zz_229 = MmuPlugin_ports_1_cache_4_valid; + _zz_230 = MmuPlugin_ports_1_cache_4_exception; + _zz_231 = MmuPlugin_ports_1_cache_4_superPage; + _zz_232 = MmuPlugin_ports_1_cache_4_virtualAddress_0; + _zz_233 = MmuPlugin_ports_1_cache_4_virtualAddress_1; + _zz_234 = MmuPlugin_ports_1_cache_4_physicalAddress_0; + _zz_235 = MmuPlugin_ports_1_cache_4_physicalAddress_1; + _zz_236 = MmuPlugin_ports_1_cache_4_allowRead; + _zz_237 = MmuPlugin_ports_1_cache_4_allowWrite; + _zz_238 = MmuPlugin_ports_1_cache_4_allowExecute; + _zz_239 = MmuPlugin_ports_1_cache_4_allowUser; + end + default : begin + _zz_229 = MmuPlugin_ports_1_cache_5_valid; + _zz_230 = MmuPlugin_ports_1_cache_5_exception; + _zz_231 = MmuPlugin_ports_1_cache_5_superPage; + _zz_232 = MmuPlugin_ports_1_cache_5_virtualAddress_0; + _zz_233 = MmuPlugin_ports_1_cache_5_virtualAddress_1; + _zz_234 = MmuPlugin_ports_1_cache_5_physicalAddress_0; + _zz_235 = MmuPlugin_ports_1_cache_5_physicalAddress_1; + _zz_236 = MmuPlugin_ports_1_cache_5_allowRead; + _zz_237 = MmuPlugin_ports_1_cache_5_allowWrite; + _zz_238 = MmuPlugin_ports_1_cache_5_allowExecute; + _zz_239 = MmuPlugin_ports_1_cache_5_allowUser; + end + endcase + end + + `ifndef SYNTHESIS + always @(*) begin + case(_zz_1) + `BranchCtrlEnum_defaultEncoding_INC : _zz_1_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_1_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_1_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_1_string = "JALR"; + default : _zz_1_string = "????"; + endcase + end + always @(*) begin + case(_zz_2) + `BranchCtrlEnum_defaultEncoding_INC : _zz_2_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_2_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_2_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_2_string = "JALR"; + default : _zz_2_string = "????"; + endcase + end + always @(*) begin + case(_zz_3) + `BranchCtrlEnum_defaultEncoding_INC : _zz_3_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_3_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_3_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_3_string = "JALR"; + default : _zz_3_string = "????"; + endcase + end + always @(*) begin + case(_zz_4) + `BranchCtrlEnum_defaultEncoding_INC : _zz_4_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_4_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_4_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_4_string = "JALR"; + default : _zz_4_string = "????"; + endcase + end + always @(*) begin + case(_zz_5) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_5_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_5_string = "XRET"; + default : _zz_5_string = "????"; + endcase + end + always @(*) begin + case(_zz_6) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_6_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_6_string = "XRET"; + default : _zz_6_string = "????"; + endcase + end + always @(*) begin + case(_zz_7) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_7_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_7_string = "XRET"; + default : _zz_7_string = "????"; + endcase + end + always @(*) begin + case(_zz_8) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_8_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_8_string = "XRET"; + default : _zz_8_string = "????"; + endcase + end + always @(*) begin + case(decode_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET"; + default : decode_ENV_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_9) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_9_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_9_string = "XRET"; + default : _zz_9_string = "????"; + endcase + end + always @(*) begin + case(_zz_10) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_10_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_10_string = "XRET"; + default : _zz_10_string = "????"; + endcase + end + always @(*) begin + case(_zz_11) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_11_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_11_string = "XRET"; + default : _zz_11_string = "????"; + endcase + end + always @(*) begin + case(_zz_12) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_12_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_12_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_12_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_12_string = "SRA_1 "; + default : _zz_12_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_13) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_13_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_13_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_13_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_13_string = "SRA_1 "; + default : _zz_13_string = "?????????"; + endcase + end + always @(*) begin + case(decode_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; + default : decode_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_14) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_14_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_14_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_14_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_14_string = "SRA_1 "; + default : _zz_14_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_15) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_15_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_15_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_15_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_15_string = "SRA_1 "; + default : _zz_15_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_16) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_16_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_16_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_16_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_16_string = "SRA_1 "; + default : _zz_16_string = "?????????"; + endcase + end + always @(*) begin + case(decode_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_17) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_17_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_17_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_17_string = "AND_1"; + default : _zz_17_string = "?????"; + endcase + end + always @(*) begin + case(_zz_18) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_18_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_18_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_18_string = "AND_1"; + default : _zz_18_string = "?????"; + endcase + end + always @(*) begin + case(_zz_19) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_19_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_19_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_19_string = "AND_1"; + default : _zz_19_string = "?????"; + endcase + end + always @(*) begin + case(decode_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; + default : decode_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(_zz_20) + `Src2CtrlEnum_defaultEncoding_RS : _zz_20_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_20_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_20_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_20_string = "PC "; + default : _zz_20_string = "???"; + endcase + end + always @(*) begin + case(_zz_21) + `Src2CtrlEnum_defaultEncoding_RS : _zz_21_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_21_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_21_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_21_string = "PC "; + default : _zz_21_string = "???"; + endcase + end + always @(*) begin + case(_zz_22) + `Src2CtrlEnum_defaultEncoding_RS : _zz_22_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_22_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_22_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_22_string = "PC "; + default : _zz_22_string = "???"; + endcase + end + always @(*) begin + case(decode_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; + default : decode_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_23) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_23_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_23_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_23_string = "BITWISE "; + default : _zz_23_string = "????????"; + endcase + end + always @(*) begin + case(_zz_24) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_24_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_24_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_24_string = "BITWISE "; + default : _zz_24_string = "????????"; + endcase + end + always @(*) begin + case(_zz_25) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_25_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_25_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_25_string = "BITWISE "; + default : _zz_25_string = "????????"; + endcase + end + always @(*) begin + case(decode_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; + default : decode_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_26) + `Src1CtrlEnum_defaultEncoding_RS : _zz_26_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_26_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_26_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_26_string = "URS1 "; + default : _zz_26_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_27) + `Src1CtrlEnum_defaultEncoding_RS : _zz_27_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_27_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_27_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_27_string = "URS1 "; + default : _zz_27_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_28) + `Src1CtrlEnum_defaultEncoding_RS : _zz_28_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_28_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_28_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_28_string = "URS1 "; + default : _zz_28_string = "????????????"; + endcase + end + always @(*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : execute_BRANCH_CTRL_string = "JALR"; + default : execute_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_29) + `BranchCtrlEnum_defaultEncoding_INC : _zz_29_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_29_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_29_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_29_string = "JALR"; + default : _zz_29_string = "????"; + endcase + end + always @(*) begin + case(memory_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : memory_ENV_CTRL_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : memory_ENV_CTRL_string = "XRET"; + default : memory_ENV_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_30) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_30_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_30_string = "XRET"; + default : _zz_30_string = "????"; + endcase + end + always @(*) begin + case(execute_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : execute_ENV_CTRL_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : execute_ENV_CTRL_string = "XRET"; + default : execute_ENV_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_31) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_31_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_31_string = "XRET"; + default : _zz_31_string = "????"; + endcase + end + always @(*) begin + case(writeBack_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : writeBack_ENV_CTRL_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : writeBack_ENV_CTRL_string = "XRET"; + default : writeBack_ENV_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_32) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_32_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_32_string = "XRET"; + default : _zz_32_string = "????"; + endcase + end + always @(*) begin + case(memory_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 "; + default : memory_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_35) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_35_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_35_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_35_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_35_string = "SRA_1 "; + default : _zz_35_string = "?????????"; + endcase + end + always @(*) begin + case(execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; + default : execute_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_36) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_36_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_36_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_36_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_36_string = "SRA_1 "; + default : _zz_36_string = "?????????"; + endcase + end + always @(*) begin + case(execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : execute_SRC2_CTRL_string = "PC "; + default : execute_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(_zz_38) + `Src2CtrlEnum_defaultEncoding_RS : _zz_38_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_38_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_38_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_38_string = "PC "; + default : _zz_38_string = "???"; + endcase + end + always @(*) begin + case(execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : execute_SRC1_CTRL_string = "URS1 "; + default : execute_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_39) + `Src1CtrlEnum_defaultEncoding_RS : _zz_39_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_39_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_39_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_39_string = "URS1 "; + default : _zz_39_string = "????????????"; + endcase + end + always @(*) begin + case(execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : execute_ALU_CTRL_string = "BITWISE "; + default : execute_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_40) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_40_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_40_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_40_string = "BITWISE "; + default : _zz_40_string = "????????"; + endcase + end + always @(*) begin + case(execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : execute_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_41) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_41_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_41_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_41_string = "AND_1"; + default : _zz_41_string = "?????"; + endcase + end + always @(*) begin + case(_zz_45) + `BranchCtrlEnum_defaultEncoding_INC : _zz_45_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_45_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_45_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_45_string = "JALR"; + default : _zz_45_string = "????"; + endcase + end + always @(*) begin + case(_zz_46) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_46_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_46_string = "XRET"; + default : _zz_46_string = "????"; + endcase + end + always @(*) begin + case(_zz_47) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_47_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_47_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_47_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_47_string = "SRA_1 "; + default : _zz_47_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_48) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_48_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_48_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_48_string = "AND_1"; + default : _zz_48_string = "?????"; + endcase + end + always @(*) begin + case(_zz_49) + `Src2CtrlEnum_defaultEncoding_RS : _zz_49_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_49_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_49_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_49_string = "PC "; + default : _zz_49_string = "???"; + endcase + end + always @(*) begin + case(_zz_50) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_50_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_50_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_50_string = "BITWISE "; + default : _zz_50_string = "????????"; + endcase + end + always @(*) begin + case(_zz_51) + `Src1CtrlEnum_defaultEncoding_RS : _zz_51_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_51_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_51_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_51_string = "URS1 "; + default : _zz_51_string = "????????????"; + endcase + end + always @(*) begin + case(decode_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR"; + default : decode_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_53) + `BranchCtrlEnum_defaultEncoding_INC : _zz_53_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_53_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_53_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_53_string = "JALR"; + default : _zz_53_string = "????"; + endcase + end + always @(*) begin + case(memory_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : memory_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : memory_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : memory_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : memory_BRANCH_CTRL_string = "JALR"; + default : memory_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_54) + `BranchCtrlEnum_defaultEncoding_INC : _zz_54_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_54_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_54_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_54_string = "JALR"; + default : _zz_54_string = "????"; + endcase + end + always @(*) begin + case(MmuPlugin_shared_state_1) + `MmuPlugin_shared_State_defaultEncoding_IDLE : MmuPlugin_shared_state_1_string = "IDLE "; + `MmuPlugin_shared_State_defaultEncoding_L1_CMD : MmuPlugin_shared_state_1_string = "L1_CMD"; + `MmuPlugin_shared_State_defaultEncoding_L1_RSP : MmuPlugin_shared_state_1_string = "L1_RSP"; + `MmuPlugin_shared_State_defaultEncoding_L0_CMD : MmuPlugin_shared_state_1_string = "L0_CMD"; + `MmuPlugin_shared_State_defaultEncoding_L0_RSP : MmuPlugin_shared_state_1_string = "L0_RSP"; + default : MmuPlugin_shared_state_1_string = "??????"; + endcase + end + always @(*) begin + case(_zz_120) + `Src1CtrlEnum_defaultEncoding_RS : _zz_120_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_120_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_120_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_120_string = "URS1 "; + default : _zz_120_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_121) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_121_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_121_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_121_string = "BITWISE "; + default : _zz_121_string = "????????"; + endcase + end + always @(*) begin + case(_zz_122) + `Src2CtrlEnum_defaultEncoding_RS : _zz_122_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_122_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_122_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_122_string = "PC "; + default : _zz_122_string = "???"; + endcase + end + always @(*) begin + case(_zz_123) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_123_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_123_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_123_string = "AND_1"; + default : _zz_123_string = "?????"; + endcase + end + always @(*) begin + case(_zz_124) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_124_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_124_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_124_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_124_string = "SRA_1 "; + default : _zz_124_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_125) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_125_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_125_string = "XRET"; + default : _zz_125_string = "????"; + endcase + end + always @(*) begin + case(_zz_126) + `BranchCtrlEnum_defaultEncoding_INC : _zz_126_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_126_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_126_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_126_string = "JALR"; + default : _zz_126_string = "????"; + endcase + end + always @(*) begin + case(decode_to_execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; + default : decode_to_execute_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(decode_to_execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; + default : decode_to_execute_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(decode_to_execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : decode_to_execute_SRC2_CTRL_string = "PC "; + default : decode_to_execute_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(decode_to_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(decode_to_execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + default : decode_to_execute_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(execute_to_memory_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; + default : execute_to_memory_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(decode_to_execute_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : decode_to_execute_ENV_CTRL_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : decode_to_execute_ENV_CTRL_string = "XRET"; + default : decode_to_execute_ENV_CTRL_string = "????"; + endcase + end + always @(*) begin + case(execute_to_memory_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : execute_to_memory_ENV_CTRL_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : execute_to_memory_ENV_CTRL_string = "XRET"; + default : execute_to_memory_ENV_CTRL_string = "????"; + endcase + end + always @(*) begin + case(memory_to_writeBack_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET"; + default : memory_to_writeBack_ENV_CTRL_string = "????"; + endcase + end + always @(*) begin + case(decode_to_execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; + default : decode_to_execute_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(execute_to_memory_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : execute_to_memory_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : execute_to_memory_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : execute_to_memory_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : execute_to_memory_BRANCH_CTRL_string = "JALR"; + default : execute_to_memory_BRANCH_CTRL_string = "????"; + endcase + end + `endif + + assign memory_MUL_LOW = ($signed(_zz_292) + $signed(_zz_300)); + assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; + assign execute_BRANCH_DO = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget); + assign memory_MUL_HH = execute_to_memory_MUL_HH; + assign execute_MUL_HH = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh)); + assign execute_MUL_HL = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow)); + assign execute_MUL_LH = ($signed(execute_MulPlugin_aSLow) * $signed(execute_MulPlugin_bHigh)); + assign execute_MUL_LL = (execute_MulPlugin_aULow * execute_MulPlugin_bULow); + assign execute_SHIFT_RIGHT = _zz_302; + assign execute_REGFILE_WRITE_DATA = _zz_128; + assign execute_IS_DBUS_SHARING = (MmuPlugin_dBusAccess_cmd_valid && MmuPlugin_dBusAccess_cmd_ready); + assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; + assign execute_MEMORY_ADDRESS_LOW = _zz_194[1 : 0]; + assign decode_PREDICTION_HAD_BRANCHED2 = IBusCachedPlugin_decodePrediction_cmd_hadBranch; + assign decode_DO_EBREAK = (((! DebugPlugin_haltIt) && (decode_IS_EBREAK || 1'b0)) && DebugPlugin_allowEBreak); + assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); + assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); + assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); + assign _zz_1 = _zz_2; + assign _zz_3 = _zz_4; + assign _zz_5 = _zz_6; + assign _zz_7 = _zz_8; + assign decode_ENV_CTRL = _zz_9; + assign _zz_10 = _zz_11; + assign decode_IS_CSR = _zz_304[0]; + assign decode_IS_RS2_SIGNED = _zz_305[0]; + assign decode_IS_RS1_SIGNED = _zz_306[0]; + assign decode_IS_DIV = _zz_307[0]; + assign memory_IS_MUL = execute_to_memory_IS_MUL; + assign execute_IS_MUL = decode_to_execute_IS_MUL; + assign decode_IS_MUL = _zz_308[0]; + assign _zz_12 = _zz_13; + assign decode_SHIFT_CTRL = _zz_14; + assign _zz_15 = _zz_16; + assign decode_ALU_BITWISE_CTRL = _zz_17; + assign _zz_18 = _zz_19; + assign decode_SRC_LESS_UNSIGNED = _zz_309[0]; + assign memory_IS_SFENCE_VMA = execute_to_memory_IS_SFENCE_VMA; + assign execute_IS_SFENCE_VMA = decode_to_execute_IS_SFENCE_VMA; + assign decode_IS_SFENCE_VMA = _zz_310[0]; + assign decode_MEMORY_MANAGMENT = _zz_311[0]; + assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR; + assign decode_MEMORY_WR = _zz_312[0]; + assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_313[0]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_314[0]; + assign decode_SRC2_CTRL = _zz_20; + assign _zz_21 = _zz_22; + assign decode_ALU_CTRL = _zz_23; + assign _zz_24 = _zz_25; + assign decode_SRC1_CTRL = _zz_26; + assign _zz_27 = _zz_28; + assign decode_MEMORY_FORCE_CONSTISTENCY = 1'b0; + assign execute_PREDICTION_CONTEXT_hazard = decode_to_execute_PREDICTION_CONTEXT_hazard; + assign execute_PREDICTION_CONTEXT_line_history = decode_to_execute_PREDICTION_CONTEXT_line_history; + assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; + assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; + assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; + assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004); + assign memory_BRANCH_CALC = execute_to_memory_BRANCH_CALC; + assign memory_BRANCH_DO = execute_to_memory_BRANCH_DO; + assign execute_PREDICTION_HAD_BRANCHED2 = decode_to_execute_PREDICTION_HAD_BRANCHED2; + assign execute_BRANCH_COND_RESULT = _zz_161; + assign execute_BRANCH_CTRL = _zz_29; + assign execute_PC = decode_to_execute_PC; + assign execute_DO_EBREAK = decode_to_execute_DO_EBREAK; + assign decode_IS_EBREAK = _zz_315[0]; + assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; + assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; + assign execute_IS_CSR = decode_to_execute_IS_CSR; + assign memory_ENV_CTRL = _zz_30; + assign execute_ENV_CTRL = _zz_31; + assign writeBack_ENV_CTRL = _zz_32; + assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED; + assign execute_IS_DIV = decode_to_execute_IS_DIV; + assign execute_IS_RS2_SIGNED = decode_to_execute_IS_RS2_SIGNED; + assign memory_IS_DIV = execute_to_memory_IS_DIV; + assign writeBack_IS_MUL = memory_to_writeBack_IS_MUL; + assign writeBack_MUL_HH = memory_to_writeBack_MUL_HH; + assign writeBack_MUL_LOW = memory_to_writeBack_MUL_LOW; + assign memory_MUL_HL = execute_to_memory_MUL_HL; + assign memory_MUL_LH = execute_to_memory_MUL_LH; + assign memory_MUL_LL = execute_to_memory_MUL_LL; + assign execute_RS1 = decode_to_execute_RS1; + assign decode_RS2_USE = _zz_316[0]; + assign decode_RS1_USE = _zz_317[0]; + always @ (*) begin + _zz_33 = execute_REGFILE_WRITE_DATA; + if(_zz_240)begin + _zz_33 = execute_CsrPlugin_readData; + end + if(DBusCachedPlugin_forceDatapath)begin + _zz_33 = MmuPlugin_dBusAccess_cmd_payload_address; + end + end + + assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID; + assign execute_BYPASSABLE_EXECUTE_STAGE = decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + assign memory_REGFILE_WRITE_VALID = execute_to_memory_REGFILE_WRITE_VALID; + assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION; + assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE; + assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; + always @ (*) begin + decode_RS2 = decode_RegFilePlugin_rs2Data; + if(_zz_139)begin + if((_zz_140 == decode_INSTRUCTION[24 : 20]))begin + decode_RS2 = _zz_141; + end + end + if(_zz_241)begin + if(_zz_242)begin + if(_zz_143)begin + decode_RS2 = _zz_52; + end + end + end + if(_zz_243)begin + if(memory_BYPASSABLE_MEMORY_STAGE)begin + if(_zz_145)begin + decode_RS2 = _zz_34; + end + end + end + if(_zz_244)begin + if(execute_BYPASSABLE_EXECUTE_STAGE)begin + if(_zz_147)begin + decode_RS2 = _zz_33; + end + end + end + end + + always @ (*) begin + decode_RS1 = decode_RegFilePlugin_rs1Data; + if(_zz_139)begin + if((_zz_140 == decode_INSTRUCTION[19 : 15]))begin + decode_RS1 = _zz_141; + end + end + if(_zz_241)begin + if(_zz_242)begin + if(_zz_142)begin + decode_RS1 = _zz_52; + end + end + end + if(_zz_243)begin + if(memory_BYPASSABLE_MEMORY_STAGE)begin + if(_zz_144)begin + decode_RS1 = _zz_34; + end + end + end + if(_zz_244)begin + if(execute_BYPASSABLE_EXECUTE_STAGE)begin + if(_zz_146)begin + decode_RS1 = _zz_33; + end + end + end + end + + assign memory_SHIFT_RIGHT = execute_to_memory_SHIFT_RIGHT; + always @ (*) begin + _zz_34 = memory_REGFILE_WRITE_DATA; + if(memory_arbitration_isValid)begin + case(memory_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin + _zz_34 = _zz_136; + end + `ShiftCtrlEnum_defaultEncoding_SRL_1, `ShiftCtrlEnum_defaultEncoding_SRA_1 : begin + _zz_34 = memory_SHIFT_RIGHT; + end + default : begin + end + endcase + end + if(_zz_245)begin + _zz_34 = memory_DivPlugin_div_result; + end + end + + assign memory_SHIFT_CTRL = _zz_35; + assign execute_SHIFT_CTRL = _zz_36; + assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; + assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; + assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; + assign _zz_37 = execute_PC; + assign execute_SRC2_CTRL = _zz_38; + assign execute_SRC1_CTRL = _zz_39; + assign decode_SRC_USE_SUB_LESS = _zz_318[0]; + assign decode_SRC_ADD_ZERO = _zz_319[0]; + assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; + assign execute_SRC_LESS = execute_SrcPlugin_less; + assign execute_ALU_CTRL = _zz_40; + assign execute_SRC2 = _zz_134; + assign execute_SRC1 = _zz_129; + assign execute_ALU_BITWISE_CTRL = _zz_41; + assign _zz_42 = writeBack_INSTRUCTION; + assign _zz_43 = writeBack_REGFILE_WRITE_VALID; + always @ (*) begin + _zz_44 = 1'b0; + if(lastStageRegFileWrite_valid)begin + _zz_44 = 1'b1; + end + end + + assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); + always @ (*) begin + decode_REGFILE_WRITE_VALID = _zz_320[0]; + if((decode_INSTRUCTION[11 : 7] == 5'h0))begin + decode_REGFILE_WRITE_VALID = 1'b0; + end + end + + assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_417) == 32'h00001073),{(_zz_418 == _zz_419),{_zz_420,{_zz_421,_zz_422}}}}}}} != 21'h0); + assign writeBack_IS_SFENCE_VMA = memory_to_writeBack_IS_SFENCE_VMA; + assign writeBack_IS_DBUS_SHARING = memory_to_writeBack_IS_DBUS_SHARING; + assign memory_IS_DBUS_SHARING = execute_to_memory_IS_DBUS_SHARING; + always @ (*) begin + _zz_52 = writeBack_REGFILE_WRITE_DATA; + if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin + _zz_52 = writeBack_DBusCachedPlugin_rspFormated; + end + if((writeBack_arbitration_isValid && writeBack_IS_MUL))begin + case(_zz_290) + 2'b00 : begin + _zz_52 = _zz_371; + end + default : begin + _zz_52 = _zz_372; + end + endcase + end + end + + assign writeBack_MEMORY_ADDRESS_LOW = memory_to_writeBack_MEMORY_ADDRESS_LOW; + assign writeBack_MEMORY_WR = memory_to_writeBack_MEMORY_WR; + assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA; + assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE; + assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA; + assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE; + assign execute_MEMORY_FORCE_CONSTISTENCY = decode_to_execute_MEMORY_FORCE_CONSTISTENCY; + assign execute_MEMORY_MANAGMENT = decode_to_execute_MEMORY_MANAGMENT; + assign execute_RS2 = decode_to_execute_RS2; + assign execute_MEMORY_WR = decode_to_execute_MEMORY_WR; + assign execute_SRC_ADD = execute_SrcPlugin_addSub; + assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; + assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; + assign decode_MEMORY_ENABLE = _zz_321[0]; + assign decode_FLUSH_ALL = _zz_322[0]; + always @ (*) begin + IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3; + if(_zz_246)begin + IBusCachedPlugin_rsp_issueDetected_4 = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2; + if(_zz_247)begin + IBusCachedPlugin_rsp_issueDetected_3 = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1; + if(_zz_248)begin + IBusCachedPlugin_rsp_issueDetected_2 = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected; + if(_zz_249)begin + IBusCachedPlugin_rsp_issueDetected_1 = 1'b1; + end + end + + assign decode_BRANCH_CTRL = _zz_53; + assign decode_INSTRUCTION = IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; + assign memory_BRANCH_CTRL = _zz_54; + assign memory_PC = execute_to_memory_PC; + assign memory_PREDICTION_CONTEXT_hazard = execute_to_memory_PREDICTION_CONTEXT_hazard; + assign memory_PREDICTION_CONTEXT_line_history = execute_to_memory_PREDICTION_CONTEXT_line_history; + assign decode_PREDICTION_CONTEXT_hazard = _zz_80; + assign decode_PREDICTION_CONTEXT_line_history = _zz_81; + always @ (*) begin + _zz_55 = 1'b0; + if(_zz_74)begin + _zz_55 = 1'b1; + end + end + + always @ (*) begin + _zz_56 = memory_FORMAL_PC_NEXT; + if(BranchPlugin_jumpInterface_valid)begin + _zz_56 = BranchPlugin_jumpInterface_payload; + end + end + + always @ (*) begin + _zz_57 = decode_FORMAL_PC_NEXT; + if(IBusCachedPlugin_predictionJumpInterface_valid)begin + _zz_57 = IBusCachedPlugin_predictionJumpInterface_payload; + end + end + + assign decode_PC = IBusCachedPlugin_iBusRsp_output_payload_pc; + assign writeBack_PC = memory_to_writeBack_PC; + assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION; + always @ (*) begin + decode_arbitration_haltItself = 1'b0; + if(((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE))begin + decode_arbitration_haltItself = 1'b1; + end + case(_zz_175) + 3'b010 : begin + decode_arbitration_haltItself = 1'b1; + end + default : begin + end + endcase + end + + always @ (*) begin + decode_arbitration_haltByOther = 1'b0; + if(MmuPlugin_dBusAccess_cmd_valid)begin + decode_arbitration_haltByOther = 1'b1; + end + if((decode_arbitration_isValid && (_zz_137 || _zz_138)))begin + decode_arbitration_haltByOther = 1'b1; + end + if(CsrPlugin_pipelineLiberator_active)begin + decode_arbitration_haltByOther = 1'b1; + end + if(({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET))}} != 3'b000))begin + decode_arbitration_haltByOther = 1'b1; + end + end + + always @ (*) begin + decode_arbitration_removeIt = 1'b0; + if(_zz_250)begin + decode_arbitration_removeIt = 1'b1; + end + if(decode_arbitration_isFlushed)begin + decode_arbitration_removeIt = 1'b1; + end + end + + assign decode_arbitration_flushIt = 1'b0; + always @ (*) begin + decode_arbitration_flushNext = 1'b0; + if(IBusCachedPlugin_predictionJumpInterface_valid)begin + decode_arbitration_flushNext = 1'b1; + end + if(_zz_250)begin + decode_arbitration_flushNext = 1'b1; + end + end + + always @ (*) begin + execute_arbitration_haltItself = 1'b0; + if(((_zz_213 && (! dataCache_1_io_cpu_flush_ready)) || dataCache_1_io_cpu_execute_haltIt))begin + execute_arbitration_haltItself = 1'b1; + end + if(_zz_240)begin + if(execute_CsrPlugin_blockedBySideEffects)begin + execute_arbitration_haltItself = 1'b1; + end + end + end + + always @ (*) begin + execute_arbitration_haltByOther = 1'b0; + if((dataCache_1_io_cpu_execute_refilling && execute_arbitration_isValid))begin + execute_arbitration_haltByOther = 1'b1; + end + if(_zz_251)begin + execute_arbitration_haltByOther = 1'b1; + end + end + + always @ (*) begin + execute_arbitration_removeIt = 1'b0; + if(execute_arbitration_isFlushed)begin + execute_arbitration_removeIt = 1'b1; + end + end + + always @ (*) begin + execute_arbitration_flushIt = 1'b0; + if(_zz_251)begin + if(_zz_252)begin + execute_arbitration_flushIt = 1'b1; + end + end + end + + always @ (*) begin + execute_arbitration_flushNext = 1'b0; + if(_zz_251)begin + if(_zz_252)begin + execute_arbitration_flushNext = 1'b1; + end + end + end + + always @ (*) begin + memory_arbitration_haltItself = 1'b0; + if(_zz_245)begin + if(((! memory_DivPlugin_frontendOk) || (! memory_DivPlugin_div_done)))begin + memory_arbitration_haltItself = 1'b1; + end + end + end + + assign memory_arbitration_haltByOther = 1'b0; + always @ (*) begin + memory_arbitration_removeIt = 1'b0; + if(BranchPlugin_branchExceptionPort_valid)begin + memory_arbitration_removeIt = 1'b1; + end + if(memory_arbitration_isFlushed)begin + memory_arbitration_removeIt = 1'b1; + end + end + + assign memory_arbitration_flushIt = 1'b0; + always @ (*) begin + memory_arbitration_flushNext = 1'b0; + if(BranchPlugin_branchExceptionPort_valid)begin + memory_arbitration_flushNext = 1'b1; + end + if(BranchPlugin_jumpInterface_valid)begin + memory_arbitration_flushNext = 1'b1; + end + end + + always @ (*) begin + writeBack_arbitration_haltItself = 1'b0; + if(dataCache_1_io_cpu_writeBack_haltIt)begin + writeBack_arbitration_haltItself = 1'b1; + end + end + + assign writeBack_arbitration_haltByOther = 1'b0; + always @ (*) begin + writeBack_arbitration_removeIt = 1'b0; + if(DBusCachedPlugin_exceptionBus_valid)begin + writeBack_arbitration_removeIt = 1'b1; + end + if(writeBack_arbitration_isFlushed)begin + writeBack_arbitration_removeIt = 1'b1; + end + end + + always @ (*) begin + writeBack_arbitration_flushIt = 1'b0; + if(DBusCachedPlugin_redoBranch_valid)begin + writeBack_arbitration_flushIt = 1'b1; + end + end + + always @ (*) begin + writeBack_arbitration_flushNext = 1'b0; + if(DBusCachedPlugin_redoBranch_valid)begin + writeBack_arbitration_flushNext = 1'b1; + end + if(DBusCachedPlugin_exceptionBus_valid)begin + writeBack_arbitration_flushNext = 1'b1; + end + if(_zz_253)begin + writeBack_arbitration_flushNext = 1'b1; + end + if(_zz_254)begin + writeBack_arbitration_flushNext = 1'b1; + end + end + + assign lastStageInstruction = writeBack_INSTRUCTION; + assign lastStagePc = writeBack_PC; + assign lastStageIsValid = writeBack_arbitration_isValid; + assign lastStageIsFiring = writeBack_arbitration_isFiring; + always @ (*) begin + IBusCachedPlugin_fetcherHalt = 1'b0; + if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000))begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(_zz_253)begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(_zz_254)begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(_zz_251)begin + if(_zz_252)begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + end + if(DebugPlugin_haltIt)begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(_zz_255)begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_incomingInstruction = 1'b0; + if((IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_stages_2_input_valid))begin + IBusCachedPlugin_incomingInstruction = 1'b1; + end + end + + always @ (*) begin + _zz_58 = 1'b0; + if(DebugPlugin_godmode)begin + _zz_58 = 1'b1; + end + end + + assign CsrPlugin_inWfi = 1'b0; + always @ (*) begin + CsrPlugin_thirdPartyWake = 1'b0; + if(DebugPlugin_haltIt)begin + CsrPlugin_thirdPartyWake = 1'b1; + end + end + + always @ (*) begin + CsrPlugin_jumpInterface_valid = 1'b0; + if(_zz_253)begin + CsrPlugin_jumpInterface_valid = 1'b1; + end + if(_zz_254)begin + CsrPlugin_jumpInterface_valid = 1'b1; + end + end + + always @ (*) begin + CsrPlugin_jumpInterface_payload = 32'h0; + if(_zz_253)begin + CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; + end + if(_zz_254)begin + case(_zz_256) + 2'b11 : begin + CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; + end + default : begin + end + endcase + end + end + + always @ (*) begin + CsrPlugin_forceMachineWire = 1'b0; + if(DebugPlugin_godmode)begin + CsrPlugin_forceMachineWire = 1'b1; + end + end + + always @ (*) begin + CsrPlugin_allowInterrupts = 1'b1; + if((DebugPlugin_haltIt || DebugPlugin_stepIt))begin + CsrPlugin_allowInterrupts = 1'b0; + end + end + + always @ (*) begin + CsrPlugin_allowException = 1'b1; + if(DebugPlugin_godmode)begin + CsrPlugin_allowException = 1'b0; + end + end + + assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); + assign IBusCachedPlugin_jump_pcLoad_valid = ({BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,{DBusCachedPlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}} != 4'b0000); + assign _zz_59 = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}; + assign _zz_60 = (_zz_59 & (~ _zz_323)); + assign _zz_61 = _zz_60[3]; + assign _zz_62 = (_zz_60[1] || _zz_61); + assign _zz_63 = (_zz_60[2] || _zz_61); + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_217; + always @ (*) begin + IBusCachedPlugin_fetchPc_correction = 1'b0; + if(IBusCachedPlugin_fetchPc_redo_valid)begin + IBusCachedPlugin_fetchPc_correction = 1'b1; + end + if(IBusCachedPlugin_jump_pcLoad_valid)begin + IBusCachedPlugin_fetchPc_correction = 1'b1; + end + end + + assign IBusCachedPlugin_fetchPc_corrected = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_correctionReg); + always @ (*) begin + IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b0; + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin + IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_325); + if(IBusCachedPlugin_fetchPc_redo_valid)begin + IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload; + end + if(IBusCachedPlugin_jump_pcLoad_valid)begin + IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_jump_pcLoad_payload; + end + IBusCachedPlugin_fetchPc_pc[0] = 1'b0; + IBusCachedPlugin_fetchPc_pc[1] = 1'b0; + end + + always @ (*) begin + IBusCachedPlugin_fetchPc_flushed = 1'b0; + if(IBusCachedPlugin_fetchPc_redo_valid)begin + IBusCachedPlugin_fetchPc_flushed = 1'b1; + end + if(IBusCachedPlugin_jump_pcLoad_valid)begin + IBusCachedPlugin_fetchPc_flushed = 1'b1; + end + end + + assign IBusCachedPlugin_fetchPc_output_valid = ((! IBusCachedPlugin_fetcherHalt) && IBusCachedPlugin_fetchPc_booted); + assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_pc; + always @ (*) begin + IBusCachedPlugin_iBusRsp_redoFetch = 1'b0; + if(IBusCachedPlugin_rsp_redoFetch)begin + IBusCachedPlugin_iBusRsp_redoFetch = 1'b1; + end + end + + assign IBusCachedPlugin_iBusRsp_stages_0_input_valid = IBusCachedPlugin_fetchPc_output_valid; + assign IBusCachedPlugin_fetchPc_output_ready = IBusCachedPlugin_iBusRsp_stages_0_input_ready; + assign IBusCachedPlugin_iBusRsp_stages_0_input_payload = IBusCachedPlugin_fetchPc_output_payload; + always @ (*) begin + IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b0; + if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt)begin + IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b1; + end + end + + assign _zz_64 = (! IBusCachedPlugin_iBusRsp_stages_0_halt); + assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_64); + assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_64); + assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload; + always @ (*) begin + IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b0; + if(IBusCachedPlugin_mmuBus_busy)begin + IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b1; + end + end + + assign _zz_65 = (! IBusCachedPlugin_iBusRsp_stages_1_halt); + assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_65); + assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_65); + assign IBusCachedPlugin_iBusRsp_stages_1_output_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload; + always @ (*) begin + IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b0; + if((IBusCachedPlugin_rsp_issueDetected_4 || IBusCachedPlugin_rsp_iBusRspOutputHalt))begin + IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b1; + end + end + + assign _zz_66 = (! IBusCachedPlugin_iBusRsp_stages_2_halt); + assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_66); + assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_66); + assign IBusCachedPlugin_iBusRsp_stages_2_output_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; + assign IBusCachedPlugin_fetchPc_redo_valid = IBusCachedPlugin_iBusRsp_redoFetch; + assign IBusCachedPlugin_fetchPc_redo_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; + assign IBusCachedPlugin_iBusRsp_flush = ((decode_arbitration_removeIt || (decode_arbitration_flushNext && (! decode_arbitration_isStuck))) || IBusCachedPlugin_iBusRsp_redoFetch); + assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_67; + assign _zz_67 = ((1'b0 && (! _zz_68)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign _zz_68 = _zz_69; + assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_68; + assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = IBusCachedPlugin_fetchPc_pcReg; + assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! _zz_70)) || IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign _zz_70 = _zz_71; + assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = _zz_70; + assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = _zz_72; + always @ (*) begin + IBusCachedPlugin_iBusRsp_readyForError = 1'b1; + if((! IBusCachedPlugin_pcValids_0))begin + IBusCachedPlugin_iBusRsp_readyForError = 1'b0; + end + end + + assign IBusCachedPlugin_pcValids_0 = IBusCachedPlugin_injector_nextPcCalc_valids_1; + assign IBusCachedPlugin_pcValids_1 = IBusCachedPlugin_injector_nextPcCalc_valids_2; + assign IBusCachedPlugin_pcValids_2 = IBusCachedPlugin_injector_nextPcCalc_valids_3; + assign IBusCachedPlugin_pcValids_3 = IBusCachedPlugin_injector_nextPcCalc_valids_4; + assign IBusCachedPlugin_iBusRsp_output_ready = (! decode_arbitration_isStuck); + always @ (*) begin + decode_arbitration_isValid = IBusCachedPlugin_iBusRsp_output_valid; + case(_zz_175) + 3'b010 : begin + decode_arbitration_isValid = 1'b1; + end + 3'b011 : begin + decode_arbitration_isValid = 1'b1; + end + default : begin + end + endcase + end + + assign _zz_78 = (IBusCachedPlugin_fetchPc_output_payload >>> 2); + assign _zz_79 = (IBusCachedPlugin_iBusRsp_stages_0_output_ready || IBusCachedPlugin_externalFlush); + assign _zz_82 = (IBusCachedPlugin_decodePrediction_rsp_wasWrong ^ memory_PREDICTION_CONTEXT_line_history[1]); + assign _zz_75 = (memory_PC[11 : 2] + 10'h0); + assign _zz_74 = ((((! memory_PREDICTION_CONTEXT_hazard) && memory_arbitration_isFiring) && (memory_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B)) && (! ($signed(memory_PREDICTION_CONTEXT_line_history) == $signed(_zz_333)))); + always @ (*) begin + IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && decode_PREDICTION_CONTEXT_line_history[1])); + if(_zz_87)begin + IBusCachedPlugin_decodePrediction_cmd_hadBranch = 1'b0; + end + end + + assign _zz_83 = _zz_336[19]; + always @ (*) begin + _zz_84[10] = _zz_83; + _zz_84[9] = _zz_83; + _zz_84[8] = _zz_83; + _zz_84[7] = _zz_83; + _zz_84[6] = _zz_83; + _zz_84[5] = _zz_83; + _zz_84[4] = _zz_83; + _zz_84[3] = _zz_83; + _zz_84[2] = _zz_83; + _zz_84[1] = _zz_83; + _zz_84[0] = _zz_83; + end + + assign _zz_85 = _zz_337[11]; + always @ (*) begin + _zz_86[18] = _zz_85; + _zz_86[17] = _zz_85; + _zz_86[16] = _zz_85; + _zz_86[15] = _zz_85; + _zz_86[14] = _zz_85; + _zz_86[13] = _zz_85; + _zz_86[12] = _zz_85; + _zz_86[11] = _zz_85; + _zz_86[10] = _zz_85; + _zz_86[9] = _zz_85; + _zz_86[8] = _zz_85; + _zz_86[7] = _zz_85; + _zz_86[6] = _zz_85; + _zz_86[5] = _zz_85; + _zz_86[4] = _zz_85; + _zz_86[3] = _zz_85; + _zz_86[2] = _zz_85; + _zz_86[1] = _zz_85; + _zz_86[0] = _zz_85; + end + + always @ (*) begin + case(decode_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JAL : begin + _zz_87 = _zz_338[1]; + end + default : begin + _zz_87 = _zz_339[1]; + end + endcase + end + + assign IBusCachedPlugin_predictionJumpInterface_valid = (decode_arbitration_isValid && IBusCachedPlugin_decodePrediction_cmd_hadBranch); + assign _zz_88 = _zz_340[19]; + always @ (*) begin + _zz_89[10] = _zz_88; + _zz_89[9] = _zz_88; + _zz_89[8] = _zz_88; + _zz_89[7] = _zz_88; + _zz_89[6] = _zz_88; + _zz_89[5] = _zz_88; + _zz_89[4] = _zz_88; + _zz_89[3] = _zz_88; + _zz_89[2] = _zz_88; + _zz_89[1] = _zz_88; + _zz_89[0] = _zz_88; + end + + assign _zz_90 = _zz_341[11]; + always @ (*) begin + _zz_91[18] = _zz_90; + _zz_91[17] = _zz_90; + _zz_91[16] = _zz_90; + _zz_91[15] = _zz_90; + _zz_91[14] = _zz_90; + _zz_91[13] = _zz_90; + _zz_91[12] = _zz_90; + _zz_91[11] = _zz_90; + _zz_91[10] = _zz_90; + _zz_91[9] = _zz_90; + _zz_91[8] = _zz_90; + _zz_91[7] = _zz_90; + _zz_91[6] = _zz_90; + _zz_91[5] = _zz_90; + _zz_91[4] = _zz_90; + _zz_91[3] = _zz_90; + _zz_91[2] = _zz_90; + _zz_91[1] = _zz_90; + _zz_91[0] = _zz_90; + end + + assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_89,{{{_zz_435,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_91,{{{_zz_436,_zz_437},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); + assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; + always @ (*) begin + iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; + iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; + end + + assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; + assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; + assign _zz_185 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign _zz_186 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign _zz_187 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_186; + assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload; + assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; + assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush); + assign _zz_189 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); + assign _zz_190 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign _zz_191 = (CsrPlugin_privilege == 2'b00); + assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; + assign IBusCachedPlugin_rsp_issueDetected = 1'b0; + always @ (*) begin + IBusCachedPlugin_rsp_redoFetch = 1'b0; + if(_zz_249)begin + IBusCachedPlugin_rsp_redoFetch = 1'b1; + end + if(_zz_247)begin + IBusCachedPlugin_rsp_redoFetch = 1'b1; + end + end + + always @ (*) begin + _zz_192 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); + if(_zz_247)begin + _zz_192 = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; + if(_zz_248)begin + IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; + end + if(_zz_246)begin + IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; + end + end + + always @ (*) begin + IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx; + if(_zz_248)begin + IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100; + end + if(_zz_246)begin + IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001; + end + end + + assign IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_stages_2_input_payload[31 : 2],2'b00}; + assign IBusCachedPlugin_iBusRsp_output_valid = IBusCachedPlugin_iBusRsp_stages_2_output_valid; + assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready; + assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; + assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload; + assign _zz_184 = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign dBus_cmd_valid = dataCache_1_io_mem_cmd_valid; + assign dBus_cmd_payload_wr = dataCache_1_io_mem_cmd_payload_wr; + assign dBus_cmd_payload_uncached = dataCache_1_io_mem_cmd_payload_uncached; + assign dBus_cmd_payload_address = dataCache_1_io_mem_cmd_payload_address; + assign dBus_cmd_payload_data = dataCache_1_io_mem_cmd_payload_data; + assign dBus_cmd_payload_mask = dataCache_1_io_mem_cmd_payload_mask; + assign dBus_cmd_payload_length = dataCache_1_io_mem_cmd_payload_length; + assign dBus_cmd_payload_last = dataCache_1_io_mem_cmd_payload_last; + assign execute_DBusCachedPlugin_size = execute_INSTRUCTION[13 : 12]; + always @ (*) begin + _zz_193 = (execute_arbitration_isValid && execute_MEMORY_ENABLE); + if(MmuPlugin_dBusAccess_cmd_valid)begin + if(_zz_257)begin + if(_zz_258)begin + _zz_193 = 1'b1; + end + end + end + end + + always @ (*) begin + _zz_194 = execute_SRC_ADD; + if(MmuPlugin_dBusAccess_cmd_valid)begin + if(_zz_257)begin + _zz_194 = MmuPlugin_dBusAccess_cmd_payload_address; + end + end + end + + always @ (*) begin + _zz_195 = execute_MEMORY_WR; + if(MmuPlugin_dBusAccess_cmd_valid)begin + if(_zz_257)begin + _zz_195 = MmuPlugin_dBusAccess_cmd_payload_write; + end + end + end + + always @ (*) begin + case(execute_DBusCachedPlugin_size) + 2'b00 : begin + _zz_94 = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; + end + 2'b01 : begin + _zz_94 = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; + end + default : begin + _zz_94 = execute_RS2[31 : 0]; + end + endcase + end + + always @ (*) begin + _zz_196 = _zz_94; + if(MmuPlugin_dBusAccess_cmd_valid)begin + if(_zz_257)begin + _zz_196 = MmuPlugin_dBusAccess_cmd_payload_data; + end + end + end + + always @ (*) begin + _zz_197 = execute_DBusCachedPlugin_size; + if(MmuPlugin_dBusAccess_cmd_valid)begin + if(_zz_257)begin + _zz_197 = MmuPlugin_dBusAccess_cmd_payload_size; + end + end + end + + assign _zz_213 = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); + always @ (*) begin + _zz_198 = (memory_arbitration_isValid && memory_MEMORY_ENABLE); + if(memory_IS_DBUS_SHARING)begin + _zz_198 = 1'b1; + end + end + + assign _zz_199 = memory_REGFILE_WRITE_DATA; + assign DBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_198; + assign DBusCachedPlugin_mmuBus_cmd_0_isStuck = memory_arbitration_isStuck; + assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = _zz_199; + always @ (*) begin + DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; + if(memory_IS_DBUS_SHARING)begin + DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b1; + end + end + + assign DBusCachedPlugin_mmuBus_end = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); + always @ (*) begin + _zz_200 = DBusCachedPlugin_mmuBus_rsp_isIoAccess; + if((_zz_58 && (! dataCache_1_io_cpu_memory_isWrite)))begin + _zz_200 = 1'b1; + end + end + + always @ (*) begin + _zz_201 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + if(writeBack_IS_DBUS_SHARING)begin + _zz_201 = 1'b1; + end + end + + assign _zz_202 = (CsrPlugin_privilege == 2'b00); + assign _zz_203 = writeBack_REGFILE_WRITE_DATA; + always @ (*) begin + DBusCachedPlugin_redoBranch_valid = 1'b0; + if(_zz_259)begin + if(dataCache_1_io_cpu_redo)begin + DBusCachedPlugin_redoBranch_valid = 1'b1; + end + end + end + + assign DBusCachedPlugin_redoBranch_payload = writeBack_PC; + always @ (*) begin + DBusCachedPlugin_exceptionBus_valid = 1'b0; + if(_zz_259)begin + if(dataCache_1_io_cpu_writeBack_accessError)begin + DBusCachedPlugin_exceptionBus_valid = 1'b1; + end + if(dataCache_1_io_cpu_writeBack_mmuException)begin + DBusCachedPlugin_exceptionBus_valid = 1'b1; + end + if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin + DBusCachedPlugin_exceptionBus_valid = 1'b1; + end + if(dataCache_1_io_cpu_redo)begin + DBusCachedPlugin_exceptionBus_valid = 1'b0; + end + end + end + + assign DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_REGFILE_WRITE_DATA; + always @ (*) begin + DBusCachedPlugin_exceptionBus_payload_code = 4'bxxxx; + if(_zz_259)begin + if(dataCache_1_io_cpu_writeBack_accessError)begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_342}; + end + if(dataCache_1_io_cpu_writeBack_mmuException)begin + DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 4'b1111 : 4'b1101); + end + if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_343}; + end + end + end + + always @ (*) begin + writeBack_DBusCachedPlugin_rspShifted = dataCache_1_io_cpu_writeBack_data; + case(writeBack_MEMORY_ADDRESS_LOW) + 2'b01 : begin + writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1_io_cpu_writeBack_data[15 : 8]; + end + 2'b10 : begin + writeBack_DBusCachedPlugin_rspShifted[15 : 0] = dataCache_1_io_cpu_writeBack_data[31 : 16]; + end + 2'b11 : begin + writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1_io_cpu_writeBack_data[31 : 24]; + end + default : begin + end + endcase + end + + assign _zz_95 = (writeBack_DBusCachedPlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); + always @ (*) begin + _zz_96[31] = _zz_95; + _zz_96[30] = _zz_95; + _zz_96[29] = _zz_95; + _zz_96[28] = _zz_95; + _zz_96[27] = _zz_95; + _zz_96[26] = _zz_95; + _zz_96[25] = _zz_95; + _zz_96[24] = _zz_95; + _zz_96[23] = _zz_95; + _zz_96[22] = _zz_95; + _zz_96[21] = _zz_95; + _zz_96[20] = _zz_95; + _zz_96[19] = _zz_95; + _zz_96[18] = _zz_95; + _zz_96[17] = _zz_95; + _zz_96[16] = _zz_95; + _zz_96[15] = _zz_95; + _zz_96[14] = _zz_95; + _zz_96[13] = _zz_95; + _zz_96[12] = _zz_95; + _zz_96[11] = _zz_95; + _zz_96[10] = _zz_95; + _zz_96[9] = _zz_95; + _zz_96[8] = _zz_95; + _zz_96[7 : 0] = writeBack_DBusCachedPlugin_rspShifted[7 : 0]; + end + + assign _zz_97 = (writeBack_DBusCachedPlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); + always @ (*) begin + _zz_98[31] = _zz_97; + _zz_98[30] = _zz_97; + _zz_98[29] = _zz_97; + _zz_98[28] = _zz_97; + _zz_98[27] = _zz_97; + _zz_98[26] = _zz_97; + _zz_98[25] = _zz_97; + _zz_98[24] = _zz_97; + _zz_98[23] = _zz_97; + _zz_98[22] = _zz_97; + _zz_98[21] = _zz_97; + _zz_98[20] = _zz_97; + _zz_98[19] = _zz_97; + _zz_98[18] = _zz_97; + _zz_98[17] = _zz_97; + _zz_98[16] = _zz_97; + _zz_98[15 : 0] = writeBack_DBusCachedPlugin_rspShifted[15 : 0]; + end + + always @ (*) begin + case(_zz_289) + 2'b00 : begin + writeBack_DBusCachedPlugin_rspFormated = _zz_96; + end + 2'b01 : begin + writeBack_DBusCachedPlugin_rspFormated = _zz_98; + end + default : begin + writeBack_DBusCachedPlugin_rspFormated = writeBack_DBusCachedPlugin_rspShifted; + end + endcase + end + + always @ (*) begin + MmuPlugin_dBusAccess_cmd_ready = 1'b0; + if(MmuPlugin_dBusAccess_cmd_valid)begin + if(_zz_257)begin + if(_zz_258)begin + MmuPlugin_dBusAccess_cmd_ready = (! execute_arbitration_isStuck); + end + end + end + end + + always @ (*) begin + DBusCachedPlugin_forceDatapath = 1'b0; + if(MmuPlugin_dBusAccess_cmd_valid)begin + if(_zz_257)begin + DBusCachedPlugin_forceDatapath = 1'b1; + end + end + end + + assign MmuPlugin_dBusAccess_rsp_valid = ((writeBack_IS_DBUS_SHARING && (! dataCache_1_io_cpu_writeBack_isWrite)) && (dataCache_1_io_cpu_redo || (! dataCache_1_io_cpu_writeBack_haltIt))); + assign MmuPlugin_dBusAccess_rsp_payload_data = dataCache_1_io_cpu_writeBack_data; + assign MmuPlugin_dBusAccess_rsp_payload_error = (dataCache_1_io_cpu_writeBack_unalignedAccess || dataCache_1_io_cpu_writeBack_accessError); + assign MmuPlugin_dBusAccess_rsp_payload_redo = dataCache_1_io_cpu_redo; + assign MmuPlugin_ports_0_dirty = 1'b0; + always @ (*) begin + MmuPlugin_ports_0_requireMmuLockupCalc = (((IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 28] == 4'b1100) && (! IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation)) && MmuPlugin_satp_mode); + if(((! MmuPlugin_status_mprv) && (CsrPlugin_privilege == 2'b11)))begin + MmuPlugin_ports_0_requireMmuLockupCalc = 1'b0; + end + if((CsrPlugin_privilege == 2'b11))begin + MmuPlugin_ports_0_requireMmuLockupCalc = 1'b0; + end + end + + always @ (*) begin + MmuPlugin_ports_0_cacheHitsCalc[0] = ((MmuPlugin_ports_0_cache_0_valid && (MmuPlugin_ports_0_cache_0_virtualAddress_1 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22])) && (MmuPlugin_ports_0_cache_0_superPage || (MmuPlugin_ports_0_cache_0_virtualAddress_0 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]))); + MmuPlugin_ports_0_cacheHitsCalc[1] = ((MmuPlugin_ports_0_cache_1_valid && (MmuPlugin_ports_0_cache_1_virtualAddress_1 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22])) && (MmuPlugin_ports_0_cache_1_superPage || (MmuPlugin_ports_0_cache_1_virtualAddress_0 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]))); + MmuPlugin_ports_0_cacheHitsCalc[2] = ((MmuPlugin_ports_0_cache_2_valid && (MmuPlugin_ports_0_cache_2_virtualAddress_1 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22])) && (MmuPlugin_ports_0_cache_2_superPage || (MmuPlugin_ports_0_cache_2_virtualAddress_0 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]))); + MmuPlugin_ports_0_cacheHitsCalc[3] = ((MmuPlugin_ports_0_cache_3_valid && (MmuPlugin_ports_0_cache_3_virtualAddress_1 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22])) && (MmuPlugin_ports_0_cache_3_superPage || (MmuPlugin_ports_0_cache_3_virtualAddress_0 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]))); + end + + assign MmuPlugin_ports_0_cacheHit = (MmuPlugin_ports_0_cacheHitsCalc != 4'b0000); + assign _zz_99 = MmuPlugin_ports_0_cacheHitsCalc[3]; + assign _zz_100 = (MmuPlugin_ports_0_cacheHitsCalc[1] || _zz_99); + assign _zz_101 = (MmuPlugin_ports_0_cacheHitsCalc[2] || _zz_99); + assign _zz_102 = {_zz_101,_zz_100}; + assign MmuPlugin_ports_0_cacheLine_valid = _zz_218; + assign MmuPlugin_ports_0_cacheLine_exception = _zz_219; + assign MmuPlugin_ports_0_cacheLine_superPage = _zz_220; + assign MmuPlugin_ports_0_cacheLine_virtualAddress_0 = _zz_221; + assign MmuPlugin_ports_0_cacheLine_virtualAddress_1 = _zz_222; + assign MmuPlugin_ports_0_cacheLine_physicalAddress_0 = _zz_223; + assign MmuPlugin_ports_0_cacheLine_physicalAddress_1 = _zz_224; + assign MmuPlugin_ports_0_cacheLine_allowRead = _zz_225; + assign MmuPlugin_ports_0_cacheLine_allowWrite = _zz_226; + assign MmuPlugin_ports_0_cacheLine_allowExecute = _zz_227; + assign MmuPlugin_ports_0_cacheLine_allowUser = _zz_228; + always @ (*) begin + MmuPlugin_ports_0_entryToReplace_willIncrement = 1'b0; + if(_zz_260)begin + if(_zz_261)begin + MmuPlugin_ports_0_entryToReplace_willIncrement = 1'b1; + end + end + end + + assign MmuPlugin_ports_0_entryToReplace_willClear = 1'b0; + assign MmuPlugin_ports_0_entryToReplace_willOverflowIfInc = (MmuPlugin_ports_0_entryToReplace_value == 2'b11); + assign MmuPlugin_ports_0_entryToReplace_willOverflow = (MmuPlugin_ports_0_entryToReplace_willOverflowIfInc && MmuPlugin_ports_0_entryToReplace_willIncrement); + always @ (*) begin + MmuPlugin_ports_0_entryToReplace_valueNext = (MmuPlugin_ports_0_entryToReplace_value + _zz_345); + if(MmuPlugin_ports_0_entryToReplace_willClear)begin + MmuPlugin_ports_0_entryToReplace_valueNext = 2'b00; + end + end + + always @ (*) begin + if(MmuPlugin_ports_0_requireMmuLockupCalc)begin + IBusCachedPlugin_mmuBus_rsp_physicalAddress = {{MmuPlugin_ports_0_cacheLine_physicalAddress_1,(MmuPlugin_ports_0_cacheLine_superPage ? IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_0_cacheLine_physicalAddress_0)},IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; + end else begin + IBusCachedPlugin_mmuBus_rsp_physicalAddress = IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + end + end + + always @ (*) begin + if(MmuPlugin_ports_0_requireMmuLockupCalc)begin + IBusCachedPlugin_mmuBus_rsp_allowRead = (MmuPlugin_ports_0_cacheLine_allowRead || (MmuPlugin_status_mxr && MmuPlugin_ports_0_cacheLine_allowExecute)); + end else begin + IBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; + end + end + + always @ (*) begin + if(MmuPlugin_ports_0_requireMmuLockupCalc)begin + IBusCachedPlugin_mmuBus_rsp_allowWrite = MmuPlugin_ports_0_cacheLine_allowWrite; + end else begin + IBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; + end + end + + always @ (*) begin + if(MmuPlugin_ports_0_requireMmuLockupCalc)begin + IBusCachedPlugin_mmuBus_rsp_allowExecute = MmuPlugin_ports_0_cacheLine_allowExecute; + end else begin + IBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; + end + end + + always @ (*) begin + if(MmuPlugin_ports_0_requireMmuLockupCalc)begin + IBusCachedPlugin_mmuBus_rsp_exception = (((! MmuPlugin_ports_0_dirty) && MmuPlugin_ports_0_cacheHit) && ((MmuPlugin_ports_0_cacheLine_exception || ((MmuPlugin_ports_0_cacheLine_allowUser && (CsrPlugin_privilege == 2'b01)) && (! MmuPlugin_status_sum))) || ((! MmuPlugin_ports_0_cacheLine_allowUser) && (CsrPlugin_privilege == 2'b00)))); + end else begin + IBusCachedPlugin_mmuBus_rsp_exception = 1'b0; + end + end + + always @ (*) begin + if(MmuPlugin_ports_0_requireMmuLockupCalc)begin + IBusCachedPlugin_mmuBus_rsp_refilling = (MmuPlugin_ports_0_dirty || (! MmuPlugin_ports_0_cacheHit)); + end else begin + IBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; + end + end + + always @ (*) begin + if(MmuPlugin_ports_0_requireMmuLockupCalc)begin + IBusCachedPlugin_mmuBus_rsp_isPaging = 1'b1; + end else begin + IBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0; + end + end + + assign IBusCachedPlugin_mmuBus_rsp_isIoAccess = (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31 : 28] == 4'b1111); + assign IBusCachedPlugin_mmuBus_rsp_bypassTranslation = (! MmuPlugin_ports_0_requireMmuLockupCalc); + assign IBusCachedPlugin_mmuBus_rsp_ways_0_sel = MmuPlugin_ports_0_cacheHitsCalc[0]; + assign IBusCachedPlugin_mmuBus_rsp_ways_0_physical = {{MmuPlugin_ports_0_cache_0_physicalAddress_1,(MmuPlugin_ports_0_cache_0_superPage ? IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_0_cache_0_physicalAddress_0)},IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; + assign IBusCachedPlugin_mmuBus_rsp_ways_1_sel = MmuPlugin_ports_0_cacheHitsCalc[1]; + assign IBusCachedPlugin_mmuBus_rsp_ways_1_physical = {{MmuPlugin_ports_0_cache_1_physicalAddress_1,(MmuPlugin_ports_0_cache_1_superPage ? IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_0_cache_1_physicalAddress_0)},IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; + assign IBusCachedPlugin_mmuBus_rsp_ways_2_sel = MmuPlugin_ports_0_cacheHitsCalc[2]; + assign IBusCachedPlugin_mmuBus_rsp_ways_2_physical = {{MmuPlugin_ports_0_cache_2_physicalAddress_1,(MmuPlugin_ports_0_cache_2_superPage ? IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_0_cache_2_physicalAddress_0)},IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; + assign IBusCachedPlugin_mmuBus_rsp_ways_3_sel = MmuPlugin_ports_0_cacheHitsCalc[3]; + assign IBusCachedPlugin_mmuBus_rsp_ways_3_physical = {{MmuPlugin_ports_0_cache_3_physicalAddress_1,(MmuPlugin_ports_0_cache_3_superPage ? IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_0_cache_3_physicalAddress_0)},IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; + assign MmuPlugin_ports_1_dirty = 1'b0; + always @ (*) begin + MmuPlugin_ports_1_requireMmuLockupCalc = (((DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 28] == 4'b1100) && (! DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation)) && MmuPlugin_satp_mode); + if(((! MmuPlugin_status_mprv) && (CsrPlugin_privilege == 2'b11)))begin + MmuPlugin_ports_1_requireMmuLockupCalc = 1'b0; + end + if((CsrPlugin_privilege == 2'b11))begin + if(((! MmuPlugin_status_mprv) || (CsrPlugin_mstatus_MPP == 2'b11)))begin + MmuPlugin_ports_1_requireMmuLockupCalc = 1'b0; + end + end + end + + always @ (*) begin + MmuPlugin_ports_1_cacheHitsCalc[0] = ((MmuPlugin_ports_1_cache_0_valid && (MmuPlugin_ports_1_cache_0_virtualAddress_1 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22])) && (MmuPlugin_ports_1_cache_0_superPage || (MmuPlugin_ports_1_cache_0_virtualAddress_0 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]))); + MmuPlugin_ports_1_cacheHitsCalc[1] = ((MmuPlugin_ports_1_cache_1_valid && (MmuPlugin_ports_1_cache_1_virtualAddress_1 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22])) && (MmuPlugin_ports_1_cache_1_superPage || (MmuPlugin_ports_1_cache_1_virtualAddress_0 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]))); + MmuPlugin_ports_1_cacheHitsCalc[2] = ((MmuPlugin_ports_1_cache_2_valid && (MmuPlugin_ports_1_cache_2_virtualAddress_1 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22])) && (MmuPlugin_ports_1_cache_2_superPage || (MmuPlugin_ports_1_cache_2_virtualAddress_0 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]))); + MmuPlugin_ports_1_cacheHitsCalc[3] = ((MmuPlugin_ports_1_cache_3_valid && (MmuPlugin_ports_1_cache_3_virtualAddress_1 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22])) && (MmuPlugin_ports_1_cache_3_superPage || (MmuPlugin_ports_1_cache_3_virtualAddress_0 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]))); + MmuPlugin_ports_1_cacheHitsCalc[4] = ((MmuPlugin_ports_1_cache_4_valid && (MmuPlugin_ports_1_cache_4_virtualAddress_1 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22])) && (MmuPlugin_ports_1_cache_4_superPage || (MmuPlugin_ports_1_cache_4_virtualAddress_0 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]))); + MmuPlugin_ports_1_cacheHitsCalc[5] = ((MmuPlugin_ports_1_cache_5_valid && (MmuPlugin_ports_1_cache_5_virtualAddress_1 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22])) && (MmuPlugin_ports_1_cache_5_superPage || (MmuPlugin_ports_1_cache_5_virtualAddress_0 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]))); + end + + assign MmuPlugin_ports_1_cacheHit = (MmuPlugin_ports_1_cacheHitsCalc != 6'h0); + assign _zz_103 = MmuPlugin_ports_1_cacheHitsCalc[3]; + assign _zz_104 = MmuPlugin_ports_1_cacheHitsCalc[5]; + assign _zz_105 = ((MmuPlugin_ports_1_cacheHitsCalc[1] || _zz_103) || _zz_104); + assign _zz_106 = (MmuPlugin_ports_1_cacheHitsCalc[2] || _zz_103); + assign _zz_107 = (MmuPlugin_ports_1_cacheHitsCalc[4] || _zz_104); + assign _zz_108 = {_zz_107,{_zz_106,_zz_105}}; + assign MmuPlugin_ports_1_cacheLine_valid = _zz_229; + assign MmuPlugin_ports_1_cacheLine_exception = _zz_230; + assign MmuPlugin_ports_1_cacheLine_superPage = _zz_231; + assign MmuPlugin_ports_1_cacheLine_virtualAddress_0 = _zz_232; + assign MmuPlugin_ports_1_cacheLine_virtualAddress_1 = _zz_233; + assign MmuPlugin_ports_1_cacheLine_physicalAddress_0 = _zz_234; + assign MmuPlugin_ports_1_cacheLine_physicalAddress_1 = _zz_235; + assign MmuPlugin_ports_1_cacheLine_allowRead = _zz_236; + assign MmuPlugin_ports_1_cacheLine_allowWrite = _zz_237; + assign MmuPlugin_ports_1_cacheLine_allowExecute = _zz_238; + assign MmuPlugin_ports_1_cacheLine_allowUser = _zz_239; + always @ (*) begin + MmuPlugin_ports_1_entryToReplace_willIncrement = 1'b0; + if(_zz_260)begin + if(_zz_262)begin + MmuPlugin_ports_1_entryToReplace_willIncrement = 1'b1; + end + end + end + + assign MmuPlugin_ports_1_entryToReplace_willClear = 1'b0; + assign MmuPlugin_ports_1_entryToReplace_willOverflowIfInc = (MmuPlugin_ports_1_entryToReplace_value == 3'b101); + assign MmuPlugin_ports_1_entryToReplace_willOverflow = (MmuPlugin_ports_1_entryToReplace_willOverflowIfInc && MmuPlugin_ports_1_entryToReplace_willIncrement); + always @ (*) begin + if(MmuPlugin_ports_1_entryToReplace_willOverflow)begin + MmuPlugin_ports_1_entryToReplace_valueNext = 3'b000; + end else begin + MmuPlugin_ports_1_entryToReplace_valueNext = (MmuPlugin_ports_1_entryToReplace_value + _zz_347); + end + if(MmuPlugin_ports_1_entryToReplace_willClear)begin + MmuPlugin_ports_1_entryToReplace_valueNext = 3'b000; + end + end + + always @ (*) begin + if(MmuPlugin_ports_1_requireMmuLockupCalc)begin + DBusCachedPlugin_mmuBus_rsp_physicalAddress = {{MmuPlugin_ports_1_cacheLine_physicalAddress_1,(MmuPlugin_ports_1_cacheLine_superPage ? DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_1_cacheLine_physicalAddress_0)},DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; + end else begin + DBusCachedPlugin_mmuBus_rsp_physicalAddress = DBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + end + end + + always @ (*) begin + if(MmuPlugin_ports_1_requireMmuLockupCalc)begin + DBusCachedPlugin_mmuBus_rsp_allowRead = (MmuPlugin_ports_1_cacheLine_allowRead || (MmuPlugin_status_mxr && MmuPlugin_ports_1_cacheLine_allowExecute)); + end else begin + DBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; + end + end + + always @ (*) begin + if(MmuPlugin_ports_1_requireMmuLockupCalc)begin + DBusCachedPlugin_mmuBus_rsp_allowWrite = MmuPlugin_ports_1_cacheLine_allowWrite; + end else begin + DBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; + end + end + + always @ (*) begin + if(MmuPlugin_ports_1_requireMmuLockupCalc)begin + DBusCachedPlugin_mmuBus_rsp_allowExecute = MmuPlugin_ports_1_cacheLine_allowExecute; + end else begin + DBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; + end + end + + always @ (*) begin + if(MmuPlugin_ports_1_requireMmuLockupCalc)begin + DBusCachedPlugin_mmuBus_rsp_exception = (((! MmuPlugin_ports_1_dirty) && MmuPlugin_ports_1_cacheHit) && ((MmuPlugin_ports_1_cacheLine_exception || ((MmuPlugin_ports_1_cacheLine_allowUser && (CsrPlugin_privilege == 2'b01)) && (! MmuPlugin_status_sum))) || ((! MmuPlugin_ports_1_cacheLine_allowUser) && (CsrPlugin_privilege == 2'b00)))); + end else begin + DBusCachedPlugin_mmuBus_rsp_exception = 1'b0; + end + end + + always @ (*) begin + if(MmuPlugin_ports_1_requireMmuLockupCalc)begin + DBusCachedPlugin_mmuBus_rsp_refilling = (MmuPlugin_ports_1_dirty || (! MmuPlugin_ports_1_cacheHit)); + end else begin + DBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; + end + end + + always @ (*) begin + if(MmuPlugin_ports_1_requireMmuLockupCalc)begin + DBusCachedPlugin_mmuBus_rsp_isPaging = 1'b1; + end else begin + DBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0; + end + end + + assign DBusCachedPlugin_mmuBus_rsp_isIoAccess = (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31 : 28] == 4'b1111); + assign DBusCachedPlugin_mmuBus_rsp_bypassTranslation = (! MmuPlugin_ports_1_requireMmuLockupCalc); + assign DBusCachedPlugin_mmuBus_rsp_ways_0_sel = MmuPlugin_ports_1_cacheHitsCalc[0]; + assign DBusCachedPlugin_mmuBus_rsp_ways_0_physical = {{MmuPlugin_ports_1_cache_0_physicalAddress_1,(MmuPlugin_ports_1_cache_0_superPage ? DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_1_cache_0_physicalAddress_0)},DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; + assign DBusCachedPlugin_mmuBus_rsp_ways_1_sel = MmuPlugin_ports_1_cacheHitsCalc[1]; + assign DBusCachedPlugin_mmuBus_rsp_ways_1_physical = {{MmuPlugin_ports_1_cache_1_physicalAddress_1,(MmuPlugin_ports_1_cache_1_superPage ? DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_1_cache_1_physicalAddress_0)},DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; + assign DBusCachedPlugin_mmuBus_rsp_ways_2_sel = MmuPlugin_ports_1_cacheHitsCalc[2]; + assign DBusCachedPlugin_mmuBus_rsp_ways_2_physical = {{MmuPlugin_ports_1_cache_2_physicalAddress_1,(MmuPlugin_ports_1_cache_2_superPage ? DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_1_cache_2_physicalAddress_0)},DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; + assign DBusCachedPlugin_mmuBus_rsp_ways_3_sel = MmuPlugin_ports_1_cacheHitsCalc[3]; + assign DBusCachedPlugin_mmuBus_rsp_ways_3_physical = {{MmuPlugin_ports_1_cache_3_physicalAddress_1,(MmuPlugin_ports_1_cache_3_superPage ? DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_1_cache_3_physicalAddress_0)},DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; + assign DBusCachedPlugin_mmuBus_rsp_ways_4_sel = MmuPlugin_ports_1_cacheHitsCalc[4]; + assign DBusCachedPlugin_mmuBus_rsp_ways_4_physical = {{MmuPlugin_ports_1_cache_4_physicalAddress_1,(MmuPlugin_ports_1_cache_4_superPage ? DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_1_cache_4_physicalAddress_0)},DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; + assign DBusCachedPlugin_mmuBus_rsp_ways_5_sel = MmuPlugin_ports_1_cacheHitsCalc[5]; + assign DBusCachedPlugin_mmuBus_rsp_ways_5_physical = {{MmuPlugin_ports_1_cache_5_physicalAddress_1,(MmuPlugin_ports_1_cache_5_superPage ? DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_1_cache_5_physicalAddress_0)},DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; + assign MmuPlugin_shared_dBusRsp_pte_V = _zz_348[0]; + assign MmuPlugin_shared_dBusRsp_pte_R = _zz_349[0]; + assign MmuPlugin_shared_dBusRsp_pte_W = _zz_350[0]; + assign MmuPlugin_shared_dBusRsp_pte_X = _zz_351[0]; + assign MmuPlugin_shared_dBusRsp_pte_U = _zz_352[0]; + assign MmuPlugin_shared_dBusRsp_pte_G = _zz_353[0]; + assign MmuPlugin_shared_dBusRsp_pte_A = _zz_354[0]; + assign MmuPlugin_shared_dBusRsp_pte_D = _zz_355[0]; + assign MmuPlugin_shared_dBusRsp_pte_RSW = MmuPlugin_shared_dBusRspStaged_payload_data[9 : 8]; + assign MmuPlugin_shared_dBusRsp_pte_PPN0 = MmuPlugin_shared_dBusRspStaged_payload_data[19 : 10]; + assign MmuPlugin_shared_dBusRsp_pte_PPN1 = MmuPlugin_shared_dBusRspStaged_payload_data[31 : 20]; + assign MmuPlugin_shared_dBusRsp_exception = (((! MmuPlugin_shared_dBusRsp_pte_V) || ((! MmuPlugin_shared_dBusRsp_pte_R) && MmuPlugin_shared_dBusRsp_pte_W)) || MmuPlugin_shared_dBusRspStaged_payload_error); + assign MmuPlugin_shared_dBusRsp_leaf = (MmuPlugin_shared_dBusRsp_pte_R || MmuPlugin_shared_dBusRsp_pte_X); + always @ (*) begin + MmuPlugin_dBusAccess_cmd_valid = 1'b0; + case(MmuPlugin_shared_state_1) + `MmuPlugin_shared_State_defaultEncoding_IDLE : begin + end + `MmuPlugin_shared_State_defaultEncoding_L1_CMD : begin + MmuPlugin_dBusAccess_cmd_valid = 1'b1; + end + `MmuPlugin_shared_State_defaultEncoding_L1_RSP : begin + end + `MmuPlugin_shared_State_defaultEncoding_L0_CMD : begin + MmuPlugin_dBusAccess_cmd_valid = 1'b1; + end + default : begin + end + endcase + end + + assign MmuPlugin_dBusAccess_cmd_payload_write = 1'b0; + assign MmuPlugin_dBusAccess_cmd_payload_size = 2'b10; + always @ (*) begin + MmuPlugin_dBusAccess_cmd_payload_address = 32'h0; + case(MmuPlugin_shared_state_1) + `MmuPlugin_shared_State_defaultEncoding_IDLE : begin + end + `MmuPlugin_shared_State_defaultEncoding_L1_CMD : begin + MmuPlugin_dBusAccess_cmd_payload_address = {{MmuPlugin_satp_ppn,MmuPlugin_shared_vpn_1},2'b00}; + end + `MmuPlugin_shared_State_defaultEncoding_L1_RSP : begin + end + `MmuPlugin_shared_State_defaultEncoding_L0_CMD : begin + MmuPlugin_dBusAccess_cmd_payload_address = {{{MmuPlugin_shared_pteBuffer_PPN1[9 : 0],MmuPlugin_shared_pteBuffer_PPN0},MmuPlugin_shared_vpn_0},2'b00}; + end + default : begin + end + endcase + end + + assign MmuPlugin_dBusAccess_cmd_payload_data = 32'h0; + assign MmuPlugin_dBusAccess_cmd_payload_writeMask = 4'bxxxx; + always @ (*) begin + _zz_109[0] = (((IBusCachedPlugin_mmuBus_cmd_0_isValid && MmuPlugin_ports_0_requireMmuLockupCalc) && (! MmuPlugin_ports_0_dirty)) && (! MmuPlugin_ports_0_cacheHit)); + _zz_109[1] = (((DBusCachedPlugin_mmuBus_cmd_0_isValid && MmuPlugin_ports_1_requireMmuLockupCalc) && (! MmuPlugin_ports_1_dirty)) && (! MmuPlugin_ports_1_cacheHit)); + end + + assign _zz_110 = _zz_109; + always @ (*) begin + _zz_111[0] = _zz_110[1]; + _zz_111[1] = _zz_110[0]; + end + + assign _zz_112 = (_zz_111 & (~ _zz_356)); + always @ (*) begin + _zz_113[0] = _zz_112[1]; + _zz_113[1] = _zz_112[0]; + end + + assign MmuPlugin_shared_refills = _zz_113; + assign _zz_114 = (MmuPlugin_shared_refills[0] ? IBusCachedPlugin_mmuBus_cmd_0_virtualAddress : DBusCachedPlugin_mmuBus_cmd_0_virtualAddress); + assign IBusCachedPlugin_mmuBus_busy = ((MmuPlugin_shared_state_1 != `MmuPlugin_shared_State_defaultEncoding_IDLE) && MmuPlugin_shared_portSortedOh[0]); + assign DBusCachedPlugin_mmuBus_busy = ((MmuPlugin_shared_state_1 != `MmuPlugin_shared_State_defaultEncoding_IDLE) && MmuPlugin_shared_portSortedOh[1]); + assign _zz_116 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); + assign _zz_117 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); + assign _zz_118 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); + assign _zz_119 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); + assign _zz_115 = {({_zz_118,(_zz_438 == _zz_439)} != 2'b00),{((_zz_440 == _zz_441) != 1'b0),{(_zz_442 != 1'b0),{(_zz_443 != _zz_444),{_zz_445,{_zz_446,_zz_447}}}}}}; + assign _zz_120 = _zz_115[2 : 1]; + assign _zz_51 = _zz_120; + assign _zz_121 = _zz_115[7 : 6]; + assign _zz_50 = _zz_121; + assign _zz_122 = _zz_115[9 : 8]; + assign _zz_49 = _zz_122; + assign _zz_123 = _zz_115[20 : 19]; + assign _zz_48 = _zz_123; + assign _zz_124 = _zz_115[23 : 22]; + assign _zz_47 = _zz_124; + assign _zz_125 = _zz_115[29 : 29]; + assign _zz_46 = _zz_125; + assign _zz_126 = _zz_115[32 : 31]; + assign _zz_45 = _zz_126; + assign decodeExceptionPort_valid = (decode_arbitration_isValid && (! decode_LEGAL_INSTRUCTION)); + assign decodeExceptionPort_payload_code = 4'b0010; + assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; + assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; + assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; + assign decode_RegFilePlugin_rs1Data = _zz_215; + assign decode_RegFilePlugin_rs2Data = _zz_216; + always @ (*) begin + lastStageRegFileWrite_valid = (_zz_43 && writeBack_arbitration_isFiring); + if(_zz_127)begin + lastStageRegFileWrite_valid = 1'b1; + end + end + + always @ (*) begin + lastStageRegFileWrite_payload_address = _zz_42[11 : 7]; + if(_zz_127)begin + lastStageRegFileWrite_payload_address = 5'h0; + end + end + + always @ (*) begin + lastStageRegFileWrite_payload_data = _zz_52; + if(_zz_127)begin + lastStageRegFileWrite_payload_data = 32'h0; + end + end + + always @ (*) begin + case(execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2); + end + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2); + end + default : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 ^ execute_SRC2); + end + endcase + end + + always @ (*) begin + case(execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_BITWISE : begin + _zz_128 = execute_IntAluPlugin_bitwise; + end + `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin + _zz_128 = {31'd0, _zz_357}; + end + default : begin + _zz_128 = execute_SRC_ADD_SUB; + end + endcase + end + + always @ (*) begin + case(execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : begin + _zz_129 = execute_RS1; + end + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin + _zz_129 = {29'd0, _zz_358}; + end + `Src1CtrlEnum_defaultEncoding_IMU : begin + _zz_129 = {execute_INSTRUCTION[31 : 12],12'h0}; + end + default : begin + _zz_129 = {27'd0, _zz_359}; + end + endcase + end + + assign _zz_130 = _zz_360[11]; + always @ (*) begin + _zz_131[19] = _zz_130; + _zz_131[18] = _zz_130; + _zz_131[17] = _zz_130; + _zz_131[16] = _zz_130; + _zz_131[15] = _zz_130; + _zz_131[14] = _zz_130; + _zz_131[13] = _zz_130; + _zz_131[12] = _zz_130; + _zz_131[11] = _zz_130; + _zz_131[10] = _zz_130; + _zz_131[9] = _zz_130; + _zz_131[8] = _zz_130; + _zz_131[7] = _zz_130; + _zz_131[6] = _zz_130; + _zz_131[5] = _zz_130; + _zz_131[4] = _zz_130; + _zz_131[3] = _zz_130; + _zz_131[2] = _zz_130; + _zz_131[1] = _zz_130; + _zz_131[0] = _zz_130; + end + + assign _zz_132 = _zz_361[11]; + always @ (*) begin + _zz_133[19] = _zz_132; + _zz_133[18] = _zz_132; + _zz_133[17] = _zz_132; + _zz_133[16] = _zz_132; + _zz_133[15] = _zz_132; + _zz_133[14] = _zz_132; + _zz_133[13] = _zz_132; + _zz_133[12] = _zz_132; + _zz_133[11] = _zz_132; + _zz_133[10] = _zz_132; + _zz_133[9] = _zz_132; + _zz_133[8] = _zz_132; + _zz_133[7] = _zz_132; + _zz_133[6] = _zz_132; + _zz_133[5] = _zz_132; + _zz_133[4] = _zz_132; + _zz_133[3] = _zz_132; + _zz_133[2] = _zz_132; + _zz_133[1] = _zz_132; + _zz_133[0] = _zz_132; + end + + always @ (*) begin + case(execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : begin + _zz_134 = execute_RS2; + end + `Src2CtrlEnum_defaultEncoding_IMI : begin + _zz_134 = {_zz_131,execute_INSTRUCTION[31 : 20]}; + end + `Src2CtrlEnum_defaultEncoding_IMS : begin + _zz_134 = {_zz_133,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; + end + default : begin + _zz_134 = _zz_37; + end + endcase + end + + always @ (*) begin + execute_SrcPlugin_addSub = _zz_362; + if(execute_SRC2_FORCE_ZERO)begin + execute_SrcPlugin_addSub = execute_SRC1; + end + end + + assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); + assign execute_FullBarrelShifterPlugin_amplitude = execute_SRC2[4 : 0]; + always @ (*) begin + _zz_135[0] = execute_SRC1[31]; + _zz_135[1] = execute_SRC1[30]; + _zz_135[2] = execute_SRC1[29]; + _zz_135[3] = execute_SRC1[28]; + _zz_135[4] = execute_SRC1[27]; + _zz_135[5] = execute_SRC1[26]; + _zz_135[6] = execute_SRC1[25]; + _zz_135[7] = execute_SRC1[24]; + _zz_135[8] = execute_SRC1[23]; + _zz_135[9] = execute_SRC1[22]; + _zz_135[10] = execute_SRC1[21]; + _zz_135[11] = execute_SRC1[20]; + _zz_135[12] = execute_SRC1[19]; + _zz_135[13] = execute_SRC1[18]; + _zz_135[14] = execute_SRC1[17]; + _zz_135[15] = execute_SRC1[16]; + _zz_135[16] = execute_SRC1[15]; + _zz_135[17] = execute_SRC1[14]; + _zz_135[18] = execute_SRC1[13]; + _zz_135[19] = execute_SRC1[12]; + _zz_135[20] = execute_SRC1[11]; + _zz_135[21] = execute_SRC1[10]; + _zz_135[22] = execute_SRC1[9]; + _zz_135[23] = execute_SRC1[8]; + _zz_135[24] = execute_SRC1[7]; + _zz_135[25] = execute_SRC1[6]; + _zz_135[26] = execute_SRC1[5]; + _zz_135[27] = execute_SRC1[4]; + _zz_135[28] = execute_SRC1[3]; + _zz_135[29] = execute_SRC1[2]; + _zz_135[30] = execute_SRC1[1]; + _zz_135[31] = execute_SRC1[0]; + end + + assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SLL_1) ? _zz_135 : execute_SRC1); + always @ (*) begin + _zz_136[0] = memory_SHIFT_RIGHT[31]; + _zz_136[1] = memory_SHIFT_RIGHT[30]; + _zz_136[2] = memory_SHIFT_RIGHT[29]; + _zz_136[3] = memory_SHIFT_RIGHT[28]; + _zz_136[4] = memory_SHIFT_RIGHT[27]; + _zz_136[5] = memory_SHIFT_RIGHT[26]; + _zz_136[6] = memory_SHIFT_RIGHT[25]; + _zz_136[7] = memory_SHIFT_RIGHT[24]; + _zz_136[8] = memory_SHIFT_RIGHT[23]; + _zz_136[9] = memory_SHIFT_RIGHT[22]; + _zz_136[10] = memory_SHIFT_RIGHT[21]; + _zz_136[11] = memory_SHIFT_RIGHT[20]; + _zz_136[12] = memory_SHIFT_RIGHT[19]; + _zz_136[13] = memory_SHIFT_RIGHT[18]; + _zz_136[14] = memory_SHIFT_RIGHT[17]; + _zz_136[15] = memory_SHIFT_RIGHT[16]; + _zz_136[16] = memory_SHIFT_RIGHT[15]; + _zz_136[17] = memory_SHIFT_RIGHT[14]; + _zz_136[18] = memory_SHIFT_RIGHT[13]; + _zz_136[19] = memory_SHIFT_RIGHT[12]; + _zz_136[20] = memory_SHIFT_RIGHT[11]; + _zz_136[21] = memory_SHIFT_RIGHT[10]; + _zz_136[22] = memory_SHIFT_RIGHT[9]; + _zz_136[23] = memory_SHIFT_RIGHT[8]; + _zz_136[24] = memory_SHIFT_RIGHT[7]; + _zz_136[25] = memory_SHIFT_RIGHT[6]; + _zz_136[26] = memory_SHIFT_RIGHT[5]; + _zz_136[27] = memory_SHIFT_RIGHT[4]; + _zz_136[28] = memory_SHIFT_RIGHT[3]; + _zz_136[29] = memory_SHIFT_RIGHT[2]; + _zz_136[30] = memory_SHIFT_RIGHT[1]; + _zz_136[31] = memory_SHIFT_RIGHT[0]; + end + + always @ (*) begin + _zz_137 = 1'b0; + if(_zz_263)begin + if(_zz_264)begin + if(_zz_142)begin + _zz_137 = 1'b1; + end + end + end + if(_zz_265)begin + if(_zz_266)begin + if(_zz_144)begin + _zz_137 = 1'b1; + end + end + end + if(_zz_267)begin + if(_zz_268)begin + if(_zz_146)begin + _zz_137 = 1'b1; + end + end + end + if((! decode_RS1_USE))begin + _zz_137 = 1'b0; + end + end + + always @ (*) begin + _zz_138 = 1'b0; + if(_zz_263)begin + if(_zz_264)begin + if(_zz_143)begin + _zz_138 = 1'b1; + end + end + end + if(_zz_265)begin + if(_zz_266)begin + if(_zz_145)begin + _zz_138 = 1'b1; + end + end + end + if(_zz_267)begin + if(_zz_268)begin + if(_zz_147)begin + _zz_138 = 1'b1; + end + end + end + if((! decode_RS2_USE))begin + _zz_138 = 1'b0; + end + end + + assign _zz_142 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_143 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_144 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_145 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_146 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_147 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign execute_MulPlugin_a = execute_RS1; + assign execute_MulPlugin_b = execute_RS2; + always @ (*) begin + case(_zz_269) + 2'b01 : begin + execute_MulPlugin_aSigned = 1'b1; + end + 2'b10 : begin + execute_MulPlugin_aSigned = 1'b1; + end + default : begin + execute_MulPlugin_aSigned = 1'b0; + end + endcase + end + + always @ (*) begin + case(_zz_269) + 2'b01 : begin + execute_MulPlugin_bSigned = 1'b1; + end + 2'b10 : begin + execute_MulPlugin_bSigned = 1'b0; + end + default : begin + execute_MulPlugin_bSigned = 1'b0; + end + endcase + end + + assign execute_MulPlugin_aULow = execute_MulPlugin_a[15 : 0]; + assign execute_MulPlugin_bULow = execute_MulPlugin_b[15 : 0]; + assign execute_MulPlugin_aSLow = {1'b0,execute_MulPlugin_a[15 : 0]}; + assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]}; + assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]}; + assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]}; + assign writeBack_MulPlugin_result = ($signed(_zz_369) + $signed(_zz_370)); + assign memory_DivPlugin_frontendOk = 1'b1; + always @ (*) begin + memory_DivPlugin_div_counter_willIncrement = 1'b0; + if(_zz_245)begin + if(_zz_270)begin + memory_DivPlugin_div_counter_willIncrement = 1'b1; + end + end + end + + always @ (*) begin + memory_DivPlugin_div_counter_willClear = 1'b0; + if(_zz_271)begin + memory_DivPlugin_div_counter_willClear = 1'b1; + end + end + + assign memory_DivPlugin_div_counter_willOverflowIfInc = (memory_DivPlugin_div_counter_value == 6'h21); + assign memory_DivPlugin_div_counter_willOverflow = (memory_DivPlugin_div_counter_willOverflowIfInc && memory_DivPlugin_div_counter_willIncrement); + always @ (*) begin + if(memory_DivPlugin_div_counter_willOverflow)begin + memory_DivPlugin_div_counter_valueNext = 6'h0; + end else begin + memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_374); + end + if(memory_DivPlugin_div_counter_willClear)begin + memory_DivPlugin_div_counter_valueNext = 6'h0; + end + end + + assign _zz_148 = memory_DivPlugin_rs1[31 : 0]; + assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_148[31]}; + assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_375); + assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_376 : _zz_377); + assign memory_DivPlugin_div_stage_0_outNumerator = _zz_378[31:0]; + assign _zz_149 = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); + assign _zz_150 = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_151 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); + always @ (*) begin + _zz_152[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_152[31 : 0] = execute_RS1; + end + + always @ (*) begin + CsrPlugin_privilege = 2'b11; + if(CsrPlugin_forceMachineWire)begin + CsrPlugin_privilege = 2'b11; + end + end + + assign CsrPlugin_misa_base = 2'b01; + assign CsrPlugin_misa_extensions = 26'h0000042; + assign CsrPlugin_mtvec_mode = 2'b00; + assign CsrPlugin_mtvec_base = 30'h20000008; + assign _zz_153 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_154 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_155 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; + assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); + assign _zz_156 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; + assign _zz_157 = _zz_388[0]; + always @ (*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + if(_zz_250)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; + end + if(decode_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b0; + end + end + + always @ (*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + if(execute_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b0; + end + end + + always @ (*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + if(BranchPlugin_branchExceptionPort_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1; + end + if(memory_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b0; + end + end + + always @ (*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + if(DBusCachedPlugin_exceptionBus_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b1; + end + if(writeBack_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b0; + end + end + + assign CsrPlugin_exceptionPendings_0 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + assign CsrPlugin_exceptionPendings_1 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + assign CsrPlugin_exceptionPendings_2 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + assign CsrPlugin_exceptionPendings_3 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && CsrPlugin_allowException); + assign CsrPlugin_lastStageWasWfi = 1'b0; + assign CsrPlugin_pipelineLiberator_active = ((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts) && decode_arbitration_isValid); + always @ (*) begin + CsrPlugin_pipelineLiberator_done = CsrPlugin_pipelineLiberator_pcValids_2; + if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000))begin + CsrPlugin_pipelineLiberator_done = 1'b0; + end + if(CsrPlugin_hadException)begin + CsrPlugin_pipelineLiberator_done = 1'b0; + end + end + + assign CsrPlugin_interruptJump = ((CsrPlugin_interrupt_valid && CsrPlugin_pipelineLiberator_done) && CsrPlugin_allowInterrupts); + always @ (*) begin + CsrPlugin_targetPrivilege = CsrPlugin_interrupt_targetPrivilege; + if(CsrPlugin_hadException)begin + CsrPlugin_targetPrivilege = CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; + end + end + + always @ (*) begin + CsrPlugin_trapCause = CsrPlugin_interrupt_code; + if(CsrPlugin_hadException)begin + CsrPlugin_trapCause = CsrPlugin_exceptionPortCtrl_exceptionContext_code; + end + end + + always @ (*) begin + CsrPlugin_xtvec_mode = 2'bxx; + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_xtvec_mode = CsrPlugin_mtvec_mode; + end + default : begin + end + endcase + end + + always @ (*) begin + CsrPlugin_xtvec_base = 30'h0; + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_xtvec_base = CsrPlugin_mtvec_base; + end + default : begin + end + endcase + end + + assign contextSwitching = CsrPlugin_jumpInterface_valid; + assign execute_CsrPlugin_blockedBySideEffects = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) || 1'b0); + always @ (*) begin + execute_CsrPlugin_illegalAccess = 1'b1; + if(execute_CsrPlugin_csr_768)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_256)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_384)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_836)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_772)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_833)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_834)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_835)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(_zz_272)begin + execute_CsrPlugin_illegalAccess = 1'b1; + end + if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + + always @ (*) begin + execute_CsrPlugin_illegalInstruction = 1'b0; + if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)))begin + if((CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]))begin + execute_CsrPlugin_illegalInstruction = 1'b1; + end + end + end + + always @ (*) begin + execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); + if(_zz_272)begin + execute_CsrPlugin_writeInstruction = 1'b0; + end + end + + always @ (*) begin + execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); + if(_zz_272)begin + execute_CsrPlugin_readInstruction = 1'b0; + end + end + + assign execute_CsrPlugin_writeEnable = (execute_CsrPlugin_writeInstruction && (! execute_arbitration_isStuck)); + assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); + assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; + always @ (*) begin + case(_zz_291) + 1'b0 : begin + execute_CsrPlugin_writeData = execute_SRC1; + end + default : begin + execute_CsrPlugin_writeData = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); + end + endcase + end + + assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; + always @ (*) begin + debug_bus_cmd_ready = 1'b1; + if(debug_bus_cmd_valid)begin + case(_zz_273) + 6'h01 : begin + if(debug_bus_cmd_payload_wr)begin + debug_bus_cmd_ready = IBusCachedPlugin_injectionPort_ready; + end + end + default : begin + end + endcase + end + end + + always @ (*) begin + debug_bus_rsp_data = DebugPlugin_busReadDataReg; + if((! _zz_158))begin + debug_bus_rsp_data[0] = DebugPlugin_resetIt; + debug_bus_rsp_data[1] = DebugPlugin_haltIt; + debug_bus_rsp_data[2] = DebugPlugin_isPipBusy; + debug_bus_rsp_data[3] = DebugPlugin_haltedByBreak; + debug_bus_rsp_data[4] = DebugPlugin_stepIt; + end + end + + always @ (*) begin + IBusCachedPlugin_injectionPort_valid = 1'b0; + if(debug_bus_cmd_valid)begin + case(_zz_273) + 6'h01 : begin + if(debug_bus_cmd_payload_wr)begin + IBusCachedPlugin_injectionPort_valid = 1'b1; + end + end + default : begin + end + endcase + end + end + + assign IBusCachedPlugin_injectionPort_payload = debug_bus_cmd_payload_data; + assign DebugPlugin_allowEBreak = (CsrPlugin_privilege == 2'b11); + assign debug_resetOut = DebugPlugin_resetIt_regNext; + assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); + assign _zz_159 = execute_INSTRUCTION[14 : 12]; + always @ (*) begin + if((_zz_159 == 3'b000)) begin + _zz_160 = execute_BranchPlugin_eq; + end else if((_zz_159 == 3'b001)) begin + _zz_160 = (! execute_BranchPlugin_eq); + end else if((((_zz_159 & 3'b101) == 3'b101))) begin + _zz_160 = (! execute_SRC_LESS); + end else begin + _zz_160 = execute_SRC_LESS; + end + end + + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : begin + _zz_161 = 1'b0; + end + `BranchCtrlEnum_defaultEncoding_JAL : begin + _zz_161 = 1'b1; + end + `BranchCtrlEnum_defaultEncoding_JALR : begin + _zz_161 = 1'b1; + end + default : begin + _zz_161 = _zz_160; + end + endcase + end + + assign _zz_162 = _zz_390[11]; + always @ (*) begin + _zz_163[19] = _zz_162; + _zz_163[18] = _zz_162; + _zz_163[17] = _zz_162; + _zz_163[16] = _zz_162; + _zz_163[15] = _zz_162; + _zz_163[14] = _zz_162; + _zz_163[13] = _zz_162; + _zz_163[12] = _zz_162; + _zz_163[11] = _zz_162; + _zz_163[10] = _zz_162; + _zz_163[9] = _zz_162; + _zz_163[8] = _zz_162; + _zz_163[7] = _zz_162; + _zz_163[6] = _zz_162; + _zz_163[5] = _zz_162; + _zz_163[4] = _zz_162; + _zz_163[3] = _zz_162; + _zz_163[2] = _zz_162; + _zz_163[1] = _zz_162; + _zz_163[0] = _zz_162; + end + + assign _zz_164 = _zz_391[19]; + always @ (*) begin + _zz_165[10] = _zz_164; + _zz_165[9] = _zz_164; + _zz_165[8] = _zz_164; + _zz_165[7] = _zz_164; + _zz_165[6] = _zz_164; + _zz_165[5] = _zz_164; + _zz_165[4] = _zz_164; + _zz_165[3] = _zz_164; + _zz_165[2] = _zz_164; + _zz_165[1] = _zz_164; + _zz_165[0] = _zz_164; + end + + assign _zz_166 = _zz_392[11]; + always @ (*) begin + _zz_167[18] = _zz_166; + _zz_167[17] = _zz_166; + _zz_167[16] = _zz_166; + _zz_167[15] = _zz_166; + _zz_167[14] = _zz_166; + _zz_167[13] = _zz_166; + _zz_167[12] = _zz_166; + _zz_167[11] = _zz_166; + _zz_167[10] = _zz_166; + _zz_167[9] = _zz_166; + _zz_167[8] = _zz_166; + _zz_167[7] = _zz_166; + _zz_167[6] = _zz_166; + _zz_167[5] = _zz_166; + _zz_167[4] = _zz_166; + _zz_167[3] = _zz_166; + _zz_167[2] = _zz_166; + _zz_167[1] = _zz_166; + _zz_167[0] = _zz_166; + end + + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JALR : begin + _zz_168 = (_zz_393[1] ^ execute_RS1[1]); + end + `BranchCtrlEnum_defaultEncoding_JAL : begin + _zz_168 = _zz_394[1]; + end + default : begin + _zz_168 = _zz_395[1]; + end + endcase + end + + assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_168); + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JALR : begin + execute_BranchPlugin_branch_src1 = execute_RS1; + end + default : begin + execute_BranchPlugin_branch_src1 = execute_PC; + end + endcase + end + + assign _zz_169 = _zz_396[11]; + always @ (*) begin + _zz_170[19] = _zz_169; + _zz_170[18] = _zz_169; + _zz_170[17] = _zz_169; + _zz_170[16] = _zz_169; + _zz_170[15] = _zz_169; + _zz_170[14] = _zz_169; + _zz_170[13] = _zz_169; + _zz_170[12] = _zz_169; + _zz_170[11] = _zz_169; + _zz_170[10] = _zz_169; + _zz_170[9] = _zz_169; + _zz_170[8] = _zz_169; + _zz_170[7] = _zz_169; + _zz_170[6] = _zz_169; + _zz_170[5] = _zz_169; + _zz_170[4] = _zz_169; + _zz_170[3] = _zz_169; + _zz_170[2] = _zz_169; + _zz_170[1] = _zz_169; + _zz_170[0] = _zz_169; + end + + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JALR : begin + execute_BranchPlugin_branch_src2 = {_zz_170,execute_INSTRUCTION[31 : 20]}; + end + default : begin + execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_172,{{{_zz_593,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_174,{{{_zz_594,_zz_595},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); + if(execute_PREDICTION_HAD_BRANCHED2)begin + execute_BranchPlugin_branch_src2 = {29'd0, _zz_399}; + end + end + endcase + end + + assign _zz_171 = _zz_397[19]; + always @ (*) begin + _zz_172[10] = _zz_171; + _zz_172[9] = _zz_171; + _zz_172[8] = _zz_171; + _zz_172[7] = _zz_171; + _zz_172[6] = _zz_171; + _zz_172[5] = _zz_171; + _zz_172[4] = _zz_171; + _zz_172[3] = _zz_171; + _zz_172[2] = _zz_171; + _zz_172[1] = _zz_171; + _zz_172[0] = _zz_171; + end + + assign _zz_173 = _zz_398[11]; + always @ (*) begin + _zz_174[18] = _zz_173; + _zz_174[17] = _zz_173; + _zz_174[16] = _zz_173; + _zz_174[15] = _zz_173; + _zz_174[14] = _zz_173; + _zz_174[13] = _zz_173; + _zz_174[12] = _zz_173; + _zz_174[11] = _zz_173; + _zz_174[10] = _zz_173; + _zz_174[9] = _zz_173; + _zz_174[8] = _zz_173; + _zz_174[7] = _zz_173; + _zz_174[6] = _zz_173; + _zz_174[5] = _zz_173; + _zz_174[4] = _zz_173; + _zz_174[3] = _zz_173; + _zz_174[2] = _zz_173; + _zz_174[1] = _zz_173; + _zz_174[0] = _zz_173; + end + + assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); + assign BranchPlugin_jumpInterface_valid = ((memory_arbitration_isValid && memory_BRANCH_DO) && (! 1'b0)); + assign BranchPlugin_jumpInterface_payload = memory_BRANCH_CALC; + assign BranchPlugin_branchExceptionPort_valid = (memory_arbitration_isValid && (memory_BRANCH_DO && memory_BRANCH_CALC[1])); + assign BranchPlugin_branchExceptionPort_payload_code = 4'b0000; + assign BranchPlugin_branchExceptionPort_payload_badAddr = memory_BRANCH_CALC; + assign IBusCachedPlugin_decodePrediction_rsp_wasWrong = BranchPlugin_jumpInterface_valid; + assign _zz_28 = decode_SRC1_CTRL; + assign _zz_26 = _zz_51; + assign _zz_39 = decode_to_execute_SRC1_CTRL; + assign _zz_25 = decode_ALU_CTRL; + assign _zz_23 = _zz_50; + assign _zz_40 = decode_to_execute_ALU_CTRL; + assign _zz_22 = decode_SRC2_CTRL; + assign _zz_20 = _zz_49; + assign _zz_38 = decode_to_execute_SRC2_CTRL; + assign _zz_19 = decode_ALU_BITWISE_CTRL; + assign _zz_17 = _zz_48; + assign _zz_41 = decode_to_execute_ALU_BITWISE_CTRL; + assign _zz_16 = decode_SHIFT_CTRL; + assign _zz_13 = execute_SHIFT_CTRL; + assign _zz_14 = _zz_47; + assign _zz_36 = decode_to_execute_SHIFT_CTRL; + assign _zz_35 = execute_to_memory_SHIFT_CTRL; + assign _zz_11 = decode_ENV_CTRL; + assign _zz_8 = execute_ENV_CTRL; + assign _zz_6 = memory_ENV_CTRL; + assign _zz_9 = _zz_46; + assign _zz_31 = decode_to_execute_ENV_CTRL; + assign _zz_30 = execute_to_memory_ENV_CTRL; + assign _zz_32 = memory_to_writeBack_ENV_CTRL; + assign _zz_4 = decode_BRANCH_CTRL; + assign _zz_2 = execute_BRANCH_CTRL; + assign _zz_53 = _zz_45; + assign _zz_29 = decode_to_execute_BRANCH_CTRL; + assign _zz_54 = execute_to_memory_BRANCH_CTRL; + assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != 3'b000) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != 4'b0000)); + assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != 2'b00) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != 3'b000)); + assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != 1'b0) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != 2'b00)); + assign writeBack_arbitration_isFlushed = (1'b0 || (writeBack_arbitration_flushIt != 1'b0)); + assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (((1'b0 || execute_arbitration_isStuck) || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); + assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers); + assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); + assign decode_arbitration_isFiring = ((decode_arbitration_isValid && (! decode_arbitration_isStuck)) && (! decode_arbitration_removeIt)); + assign execute_arbitration_isStuckByOthers = (execute_arbitration_haltByOther || ((1'b0 || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); + assign execute_arbitration_isStuck = (execute_arbitration_haltItself || execute_arbitration_isStuckByOthers); + assign execute_arbitration_isMoving = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); + assign execute_arbitration_isFiring = ((execute_arbitration_isValid && (! execute_arbitration_isStuck)) && (! execute_arbitration_removeIt)); + assign memory_arbitration_isStuckByOthers = (memory_arbitration_haltByOther || (1'b0 || writeBack_arbitration_isStuck)); + assign memory_arbitration_isStuck = (memory_arbitration_haltItself || memory_arbitration_isStuckByOthers); + assign memory_arbitration_isMoving = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)); + assign memory_arbitration_isFiring = ((memory_arbitration_isValid && (! memory_arbitration_isStuck)) && (! memory_arbitration_removeIt)); + assign writeBack_arbitration_isStuckByOthers = (writeBack_arbitration_haltByOther || 1'b0); + assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers); + assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); + assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); + always @ (*) begin + IBusCachedPlugin_injectionPort_ready = 1'b0; + case(_zz_175) + 3'b100 : begin + IBusCachedPlugin_injectionPort_ready = 1'b1; + end + default : begin + end + endcase + end + + always @ (*) begin + _zz_176 = 32'h0; + if(execute_CsrPlugin_csr_768)begin + _zz_176[19 : 19] = MmuPlugin_status_mxr; + _zz_176[18 : 18] = MmuPlugin_status_sum; + _zz_176[17 : 17] = MmuPlugin_status_mprv; + _zz_176[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_176[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_176[3 : 3] = CsrPlugin_mstatus_MIE; + end + end + + always @ (*) begin + _zz_177 = 32'h0; + if(execute_CsrPlugin_csr_256)begin + _zz_177[19 : 19] = MmuPlugin_status_mxr; + _zz_177[18 : 18] = MmuPlugin_status_sum; + _zz_177[17 : 17] = MmuPlugin_status_mprv; + end + end + + always @ (*) begin + _zz_178 = 32'h0; + if(execute_CsrPlugin_csr_384)begin + _zz_178[31 : 31] = MmuPlugin_satp_mode; + _zz_178[30 : 22] = MmuPlugin_satp_asid; + _zz_178[19 : 0] = MmuPlugin_satp_ppn; + end + end + + always @ (*) begin + _zz_179 = 32'h0; + if(execute_CsrPlugin_csr_836)begin + _zz_179[11 : 11] = CsrPlugin_mip_MEIP; + _zz_179[7 : 7] = CsrPlugin_mip_MTIP; + _zz_179[3 : 3] = CsrPlugin_mip_MSIP; + end + end + + always @ (*) begin + _zz_180 = 32'h0; + if(execute_CsrPlugin_csr_772)begin + _zz_180[11 : 11] = CsrPlugin_mie_MEIE; + _zz_180[7 : 7] = CsrPlugin_mie_MTIE; + _zz_180[3 : 3] = CsrPlugin_mie_MSIE; + end + end + + always @ (*) begin + _zz_181 = 32'h0; + if(execute_CsrPlugin_csr_833)begin + _zz_181[31 : 0] = CsrPlugin_mepc; + end + end + + always @ (*) begin + _zz_182 = 32'h0; + if(execute_CsrPlugin_csr_834)begin + _zz_182[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_182[3 : 0] = CsrPlugin_mcause_exceptionCode; + end + end + + always @ (*) begin + _zz_183 = 32'h0; + if(execute_CsrPlugin_csr_835)begin + _zz_183[31 : 0] = CsrPlugin_mtval; + end + end + + assign execute_CsrPlugin_readData = (((_zz_176 | _zz_177) | (_zz_178 | _zz_179)) | ((_zz_180 | _zz_181) | (_zz_182 | _zz_183))); + always @ (posedge clk or posedge reset) begin + if (reset) begin + IBusCachedPlugin_fetchPc_pcReg <= 32'h80000000; + IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; + IBusCachedPlugin_fetchPc_booted <= 1'b0; + IBusCachedPlugin_fetchPc_inc <= 1'b0; + _zz_69 <= 1'b0; + _zz_71 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; + IBusCachedPlugin_rspCounter <= _zz_92; + IBusCachedPlugin_rspCounter <= 32'h0; + DBusCachedPlugin_rspCounter <= _zz_93; + DBusCachedPlugin_rspCounter <= 32'h0; + MmuPlugin_status_sum <= 1'b0; + MmuPlugin_status_mxr <= 1'b0; + MmuPlugin_status_mprv <= 1'b0; + MmuPlugin_satp_mode <= 1'b0; + MmuPlugin_ports_0_cache_0_valid <= 1'b0; + MmuPlugin_ports_0_cache_1_valid <= 1'b0; + MmuPlugin_ports_0_cache_2_valid <= 1'b0; + MmuPlugin_ports_0_cache_3_valid <= 1'b0; + MmuPlugin_ports_0_entryToReplace_value <= 2'b00; + MmuPlugin_ports_1_cache_0_valid <= 1'b0; + MmuPlugin_ports_1_cache_1_valid <= 1'b0; + MmuPlugin_ports_1_cache_2_valid <= 1'b0; + MmuPlugin_ports_1_cache_3_valid <= 1'b0; + MmuPlugin_ports_1_cache_4_valid <= 1'b0; + MmuPlugin_ports_1_cache_5_valid <= 1'b0; + MmuPlugin_ports_1_entryToReplace_value <= 3'b000; + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_IDLE; + MmuPlugin_shared_dBusRspStaged_valid <= 1'b0; + _zz_127 <= 1'b1; + _zz_139 <= 1'b0; + memory_DivPlugin_div_counter_value <= 6'h0; + CsrPlugin_mstatus_MIE <= 1'b0; + CsrPlugin_mstatus_MPIE <= 1'b0; + CsrPlugin_mstatus_MPP <= 2'b11; + CsrPlugin_mie_MEIE <= 1'b0; + CsrPlugin_mie_MTIE <= 1'b0; + CsrPlugin_mie_MSIE <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; + CsrPlugin_interrupt_valid <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; + CsrPlugin_hadException <= 1'b0; + execute_CsrPlugin_wfiWake <= 1'b0; + execute_arbitration_isValid <= 1'b0; + memory_arbitration_isValid <= 1'b0; + writeBack_arbitration_isValid <= 1'b0; + _zz_175 <= 3'b000; + execute_to_memory_IS_DBUS_SHARING <= 1'b0; + memory_to_writeBack_IS_DBUS_SHARING <= 1'b0; + end else begin + if(IBusCachedPlugin_fetchPc_correction)begin + IBusCachedPlugin_fetchPc_correctionReg <= 1'b1; + end + if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin + IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; + end + IBusCachedPlugin_fetchPc_booted <= 1'b1; + if((IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_pcRegPropagate))begin + IBusCachedPlugin_fetchPc_inc <= 1'b0; + end + if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin + IBusCachedPlugin_fetchPc_inc <= 1'b1; + end + if(((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready))begin + IBusCachedPlugin_fetchPc_inc <= 1'b0; + end + if((IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetchPc_correction) || IBusCachedPlugin_fetchPc_pcRegPropagate)))begin + IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc; + end + if(IBusCachedPlugin_iBusRsp_flush)begin + _zz_69 <= 1'b0; + end + if(_zz_67)begin + _zz_69 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); + end + if(IBusCachedPlugin_iBusRsp_flush)begin + _zz_71 <= 1'b0; + end + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin + _zz_71 <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; + end + if((! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready)))begin + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b1; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + end + if((! (! IBusCachedPlugin_iBusRsp_stages_2_input_ready)))begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= IBusCachedPlugin_injector_nextPcCalc_valids_0; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; + end + if((! execute_arbitration_isStuck))begin + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= IBusCachedPlugin_injector_nextPcCalc_valids_1; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; + end + if((! memory_arbitration_isStuck))begin + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= IBusCachedPlugin_injector_nextPcCalc_valids_2; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; + end + if((! writeBack_arbitration_isStuck))begin + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= IBusCachedPlugin_injector_nextPcCalc_valids_3; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; + end + if(iBus_rsp_valid)begin + IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + 32'h00000001); + end + if(dBus_rsp_valid)begin + DBusCachedPlugin_rspCounter <= (DBusCachedPlugin_rspCounter + 32'h00000001); + end + MmuPlugin_ports_0_entryToReplace_value <= MmuPlugin_ports_0_entryToReplace_valueNext; + if(contextSwitching)begin + if(MmuPlugin_ports_0_cache_0_exception)begin + MmuPlugin_ports_0_cache_0_valid <= 1'b0; + end + if(MmuPlugin_ports_0_cache_1_exception)begin + MmuPlugin_ports_0_cache_1_valid <= 1'b0; + end + if(MmuPlugin_ports_0_cache_2_exception)begin + MmuPlugin_ports_0_cache_2_valid <= 1'b0; + end + if(MmuPlugin_ports_0_cache_3_exception)begin + MmuPlugin_ports_0_cache_3_valid <= 1'b0; + end + end + MmuPlugin_ports_1_entryToReplace_value <= MmuPlugin_ports_1_entryToReplace_valueNext; + if(contextSwitching)begin + if(MmuPlugin_ports_1_cache_0_exception)begin + MmuPlugin_ports_1_cache_0_valid <= 1'b0; + end + if(MmuPlugin_ports_1_cache_1_exception)begin + MmuPlugin_ports_1_cache_1_valid <= 1'b0; + end + if(MmuPlugin_ports_1_cache_2_exception)begin + MmuPlugin_ports_1_cache_2_valid <= 1'b0; + end + if(MmuPlugin_ports_1_cache_3_exception)begin + MmuPlugin_ports_1_cache_3_valid <= 1'b0; + end + if(MmuPlugin_ports_1_cache_4_exception)begin + MmuPlugin_ports_1_cache_4_valid <= 1'b0; + end + if(MmuPlugin_ports_1_cache_5_exception)begin + MmuPlugin_ports_1_cache_5_valid <= 1'b0; + end + end + MmuPlugin_shared_dBusRspStaged_valid <= MmuPlugin_dBusAccess_rsp_valid; + case(MmuPlugin_shared_state_1) + `MmuPlugin_shared_State_defaultEncoding_IDLE : begin + if(_zz_274)begin + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_L1_CMD; + end + end + `MmuPlugin_shared_State_defaultEncoding_L1_CMD : begin + if(MmuPlugin_dBusAccess_cmd_ready)begin + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_L1_RSP; + end + end + `MmuPlugin_shared_State_defaultEncoding_L1_RSP : begin + if(MmuPlugin_shared_dBusRspStaged_valid)begin + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_L0_CMD; + if((MmuPlugin_shared_dBusRsp_leaf || MmuPlugin_shared_dBusRsp_exception))begin + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_IDLE; + end + if(MmuPlugin_shared_dBusRspStaged_payload_redo)begin + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_L1_CMD; + end + end + end + `MmuPlugin_shared_State_defaultEncoding_L0_CMD : begin + if(MmuPlugin_dBusAccess_cmd_ready)begin + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_L0_RSP; + end + end + default : begin + if(MmuPlugin_shared_dBusRspStaged_valid)begin + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_IDLE; + if(MmuPlugin_shared_dBusRspStaged_payload_redo)begin + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_L0_CMD; + end + end + end + endcase + if(_zz_260)begin + if(_zz_261)begin + if(_zz_275)begin + MmuPlugin_ports_0_cache_0_valid <= 1'b1; + end + if(_zz_276)begin + MmuPlugin_ports_0_cache_1_valid <= 1'b1; + end + if(_zz_277)begin + MmuPlugin_ports_0_cache_2_valid <= 1'b1; + end + if(_zz_278)begin + MmuPlugin_ports_0_cache_3_valid <= 1'b1; + end + end + if(_zz_262)begin + if(_zz_279)begin + MmuPlugin_ports_1_cache_0_valid <= 1'b1; + end + if(_zz_280)begin + MmuPlugin_ports_1_cache_1_valid <= 1'b1; + end + if(_zz_281)begin + MmuPlugin_ports_1_cache_2_valid <= 1'b1; + end + if(_zz_282)begin + MmuPlugin_ports_1_cache_3_valid <= 1'b1; + end + if(_zz_283)begin + MmuPlugin_ports_1_cache_4_valid <= 1'b1; + end + if(_zz_284)begin + MmuPlugin_ports_1_cache_5_valid <= 1'b1; + end + end + end + if((writeBack_arbitration_isValid && writeBack_IS_SFENCE_VMA))begin + MmuPlugin_ports_0_cache_0_valid <= 1'b0; + MmuPlugin_ports_0_cache_1_valid <= 1'b0; + MmuPlugin_ports_0_cache_2_valid <= 1'b0; + MmuPlugin_ports_0_cache_3_valid <= 1'b0; + MmuPlugin_ports_1_cache_0_valid <= 1'b0; + MmuPlugin_ports_1_cache_1_valid <= 1'b0; + MmuPlugin_ports_1_cache_2_valid <= 1'b0; + MmuPlugin_ports_1_cache_3_valid <= 1'b0; + MmuPlugin_ports_1_cache_4_valid <= 1'b0; + MmuPlugin_ports_1_cache_5_valid <= 1'b0; + end + _zz_127 <= 1'b0; + _zz_139 <= (_zz_43 && writeBack_arbitration_isFiring); + memory_DivPlugin_div_counter_value <= memory_DivPlugin_div_counter_valueNext; + if((! decode_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= CsrPlugin_exceptionPortCtrl_exceptionValids_decode; + end + if((! execute_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= (CsrPlugin_exceptionPortCtrl_exceptionValids_decode && (! decode_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= CsrPlugin_exceptionPortCtrl_exceptionValids_execute; + end + if((! memory_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && (! execute_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= CsrPlugin_exceptionPortCtrl_exceptionValids_memory; + end + if((! writeBack_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= (CsrPlugin_exceptionPortCtrl_exceptionValids_memory && (! memory_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; + end + CsrPlugin_interrupt_valid <= 1'b0; + if(_zz_285)begin + if(_zz_286)begin + CsrPlugin_interrupt_valid <= 1'b1; + end + if(_zz_287)begin + CsrPlugin_interrupt_valid <= 1'b1; + end + if(_zz_288)begin + CsrPlugin_interrupt_valid <= 1'b1; + end + end + if(CsrPlugin_pipelineLiberator_active)begin + if((! execute_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b1; + end + if((! memory_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_1 <= CsrPlugin_pipelineLiberator_pcValids_0; + end + if((! writeBack_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_2 <= CsrPlugin_pipelineLiberator_pcValids_1; + end + end + if(((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt))begin + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; + end + if(CsrPlugin_interruptJump)begin + CsrPlugin_interrupt_valid <= 1'b0; + end + CsrPlugin_hadException <= CsrPlugin_exception; + if(_zz_253)begin + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_mstatus_MIE <= 1'b0; + CsrPlugin_mstatus_MPIE <= CsrPlugin_mstatus_MIE; + CsrPlugin_mstatus_MPP <= CsrPlugin_privilege; + end + default : begin + end + endcase + end + if(_zz_254)begin + case(_zz_256) + 2'b11 : begin + CsrPlugin_mstatus_MPP <= 2'b00; + CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; + CsrPlugin_mstatus_MPIE <= 1'b1; + end + default : begin + end + endcase + end + execute_CsrPlugin_wfiWake <= (({_zz_155,{_zz_154,_zz_153}} != 3'b000) || CsrPlugin_thirdPartyWake); + if((! memory_arbitration_isStuck))begin + execute_to_memory_IS_DBUS_SHARING <= execute_IS_DBUS_SHARING; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_IS_DBUS_SHARING <= memory_IS_DBUS_SHARING; + end + if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin + execute_arbitration_isValid <= 1'b0; + end + if(((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)))begin + execute_arbitration_isValid <= decode_arbitration_isValid; + end + if(((! memory_arbitration_isStuck) || memory_arbitration_removeIt))begin + memory_arbitration_isValid <= 1'b0; + end + if(((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)))begin + memory_arbitration_isValid <= execute_arbitration_isValid; + end + if(((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt))begin + writeBack_arbitration_isValid <= 1'b0; + end + if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin + writeBack_arbitration_isValid <= memory_arbitration_isValid; + end + case(_zz_175) + 3'b000 : begin + if(IBusCachedPlugin_injectionPort_valid)begin + _zz_175 <= 3'b001; + end + end + 3'b001 : begin + _zz_175 <= 3'b010; + end + 3'b010 : begin + _zz_175 <= 3'b011; + end + 3'b011 : begin + if((! decode_arbitration_isStuck))begin + _zz_175 <= 3'b100; + end + end + 3'b100 : begin + _zz_175 <= 3'b000; + end + default : begin + end + endcase + if(MmuPlugin_dBusAccess_rsp_valid)begin + memory_to_writeBack_IS_DBUS_SHARING <= 1'b0; + end + if(execute_CsrPlugin_csr_768)begin + if(execute_CsrPlugin_writeEnable)begin + MmuPlugin_status_mxr <= _zz_400[0]; + MmuPlugin_status_sum <= _zz_401[0]; + MmuPlugin_status_mprv <= _zz_402[0]; + CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; + CsrPlugin_mstatus_MPIE <= _zz_403[0]; + CsrPlugin_mstatus_MIE <= _zz_404[0]; + end + end + if(execute_CsrPlugin_csr_256)begin + if(execute_CsrPlugin_writeEnable)begin + MmuPlugin_status_mxr <= _zz_405[0]; + MmuPlugin_status_sum <= _zz_406[0]; + MmuPlugin_status_mprv <= _zz_407[0]; + end + end + if(execute_CsrPlugin_csr_384)begin + if(execute_CsrPlugin_writeInstruction)begin + MmuPlugin_ports_0_cache_0_valid <= 1'b0; + MmuPlugin_ports_0_cache_1_valid <= 1'b0; + MmuPlugin_ports_0_cache_2_valid <= 1'b0; + MmuPlugin_ports_0_cache_3_valid <= 1'b0; + MmuPlugin_ports_1_cache_0_valid <= 1'b0; + MmuPlugin_ports_1_cache_1_valid <= 1'b0; + MmuPlugin_ports_1_cache_2_valid <= 1'b0; + MmuPlugin_ports_1_cache_3_valid <= 1'b0; + MmuPlugin_ports_1_cache_4_valid <= 1'b0; + MmuPlugin_ports_1_cache_5_valid <= 1'b0; + end + if(execute_CsrPlugin_writeEnable)begin + MmuPlugin_satp_mode <= _zz_408[0]; + end + end + if(execute_CsrPlugin_csr_772)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mie_MEIE <= _zz_410[0]; + CsrPlugin_mie_MTIE <= _zz_411[0]; + CsrPlugin_mie_MSIE <= _zz_412[0]; + end + end + end + end + + always @ (posedge clk) begin + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin + _zz_72 <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; + end + if(IBusCachedPlugin_iBusRsp_stages_0_output_ready)begin + _zz_76 <= _zz_74; + _zz_77 <= _zz_75; + end + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin + _zz_80 <= (_zz_76 && (_zz_77 == _zz_332)); + _zz_81 <= _zz_214[1 : 0]; + end + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin + IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit; + end + if(IBusCachedPlugin_iBusRsp_stages_2_input_ready)begin + IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; + end + MmuPlugin_shared_dBusRspStaged_payload_data <= MmuPlugin_dBusAccess_rsp_payload_data; + MmuPlugin_shared_dBusRspStaged_payload_error <= MmuPlugin_dBusAccess_rsp_payload_error; + MmuPlugin_shared_dBusRspStaged_payload_redo <= MmuPlugin_dBusAccess_rsp_payload_redo; + if((MmuPlugin_shared_dBusRspStaged_valid && (! MmuPlugin_shared_dBusRspStaged_payload_redo)))begin + MmuPlugin_shared_pteBuffer_V <= MmuPlugin_shared_dBusRsp_pte_V; + MmuPlugin_shared_pteBuffer_R <= MmuPlugin_shared_dBusRsp_pte_R; + MmuPlugin_shared_pteBuffer_W <= MmuPlugin_shared_dBusRsp_pte_W; + MmuPlugin_shared_pteBuffer_X <= MmuPlugin_shared_dBusRsp_pte_X; + MmuPlugin_shared_pteBuffer_U <= MmuPlugin_shared_dBusRsp_pte_U; + MmuPlugin_shared_pteBuffer_G <= MmuPlugin_shared_dBusRsp_pte_G; + MmuPlugin_shared_pteBuffer_A <= MmuPlugin_shared_dBusRsp_pte_A; + MmuPlugin_shared_pteBuffer_D <= MmuPlugin_shared_dBusRsp_pte_D; + MmuPlugin_shared_pteBuffer_RSW <= MmuPlugin_shared_dBusRsp_pte_RSW; + MmuPlugin_shared_pteBuffer_PPN0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; + MmuPlugin_shared_pteBuffer_PPN1 <= MmuPlugin_shared_dBusRsp_pte_PPN1; + end + case(MmuPlugin_shared_state_1) + `MmuPlugin_shared_State_defaultEncoding_IDLE : begin + if(_zz_274)begin + MmuPlugin_shared_portSortedOh <= MmuPlugin_shared_refills; + MmuPlugin_shared_vpn_1 <= _zz_114[31 : 22]; + MmuPlugin_shared_vpn_0 <= _zz_114[21 : 12]; + end + end + `MmuPlugin_shared_State_defaultEncoding_L1_CMD : begin + end + `MmuPlugin_shared_State_defaultEncoding_L1_RSP : begin + end + `MmuPlugin_shared_State_defaultEncoding_L0_CMD : begin + end + default : begin + end + endcase + if(_zz_260)begin + if(_zz_261)begin + if(_zz_275)begin + MmuPlugin_ports_0_cache_0_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); + MmuPlugin_ports_0_cache_0_virtualAddress_0 <= MmuPlugin_shared_vpn_0; + MmuPlugin_ports_0_cache_0_virtualAddress_1 <= MmuPlugin_shared_vpn_1; + MmuPlugin_ports_0_cache_0_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; + MmuPlugin_ports_0_cache_0_physicalAddress_1 <= MmuPlugin_shared_dBusRsp_pte_PPN1[9 : 0]; + MmuPlugin_ports_0_cache_0_allowRead <= MmuPlugin_shared_dBusRsp_pte_R; + MmuPlugin_ports_0_cache_0_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; + MmuPlugin_ports_0_cache_0_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; + MmuPlugin_ports_0_cache_0_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; + MmuPlugin_ports_0_cache_0_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); + end + if(_zz_276)begin + MmuPlugin_ports_0_cache_1_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); + MmuPlugin_ports_0_cache_1_virtualAddress_0 <= MmuPlugin_shared_vpn_0; + MmuPlugin_ports_0_cache_1_virtualAddress_1 <= MmuPlugin_shared_vpn_1; + MmuPlugin_ports_0_cache_1_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; + MmuPlugin_ports_0_cache_1_physicalAddress_1 <= MmuPlugin_shared_dBusRsp_pte_PPN1[9 : 0]; + MmuPlugin_ports_0_cache_1_allowRead <= MmuPlugin_shared_dBusRsp_pte_R; + MmuPlugin_ports_0_cache_1_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; + MmuPlugin_ports_0_cache_1_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; + MmuPlugin_ports_0_cache_1_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; + MmuPlugin_ports_0_cache_1_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); + end + if(_zz_277)begin + MmuPlugin_ports_0_cache_2_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); + MmuPlugin_ports_0_cache_2_virtualAddress_0 <= MmuPlugin_shared_vpn_0; + MmuPlugin_ports_0_cache_2_virtualAddress_1 <= MmuPlugin_shared_vpn_1; + MmuPlugin_ports_0_cache_2_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; + MmuPlugin_ports_0_cache_2_physicalAddress_1 <= MmuPlugin_shared_dBusRsp_pte_PPN1[9 : 0]; + MmuPlugin_ports_0_cache_2_allowRead <= MmuPlugin_shared_dBusRsp_pte_R; + MmuPlugin_ports_0_cache_2_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; + MmuPlugin_ports_0_cache_2_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; + MmuPlugin_ports_0_cache_2_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; + MmuPlugin_ports_0_cache_2_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); + end + if(_zz_278)begin + MmuPlugin_ports_0_cache_3_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); + MmuPlugin_ports_0_cache_3_virtualAddress_0 <= MmuPlugin_shared_vpn_0; + MmuPlugin_ports_0_cache_3_virtualAddress_1 <= MmuPlugin_shared_vpn_1; + MmuPlugin_ports_0_cache_3_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; + MmuPlugin_ports_0_cache_3_physicalAddress_1 <= MmuPlugin_shared_dBusRsp_pte_PPN1[9 : 0]; + MmuPlugin_ports_0_cache_3_allowRead <= MmuPlugin_shared_dBusRsp_pte_R; + MmuPlugin_ports_0_cache_3_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; + MmuPlugin_ports_0_cache_3_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; + MmuPlugin_ports_0_cache_3_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; + MmuPlugin_ports_0_cache_3_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); + end + end + if(_zz_262)begin + if(_zz_279)begin + MmuPlugin_ports_1_cache_0_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); + MmuPlugin_ports_1_cache_0_virtualAddress_0 <= MmuPlugin_shared_vpn_0; + MmuPlugin_ports_1_cache_0_virtualAddress_1 <= MmuPlugin_shared_vpn_1; + MmuPlugin_ports_1_cache_0_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; + MmuPlugin_ports_1_cache_0_physicalAddress_1 <= MmuPlugin_shared_dBusRsp_pte_PPN1[9 : 0]; + MmuPlugin_ports_1_cache_0_allowRead <= MmuPlugin_shared_dBusRsp_pte_R; + MmuPlugin_ports_1_cache_0_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; + MmuPlugin_ports_1_cache_0_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; + MmuPlugin_ports_1_cache_0_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; + MmuPlugin_ports_1_cache_0_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); + end + if(_zz_280)begin + MmuPlugin_ports_1_cache_1_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); + MmuPlugin_ports_1_cache_1_virtualAddress_0 <= MmuPlugin_shared_vpn_0; + MmuPlugin_ports_1_cache_1_virtualAddress_1 <= MmuPlugin_shared_vpn_1; + MmuPlugin_ports_1_cache_1_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; + MmuPlugin_ports_1_cache_1_physicalAddress_1 <= MmuPlugin_shared_dBusRsp_pte_PPN1[9 : 0]; + MmuPlugin_ports_1_cache_1_allowRead <= MmuPlugin_shared_dBusRsp_pte_R; + MmuPlugin_ports_1_cache_1_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; + MmuPlugin_ports_1_cache_1_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; + MmuPlugin_ports_1_cache_1_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; + MmuPlugin_ports_1_cache_1_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); + end + if(_zz_281)begin + MmuPlugin_ports_1_cache_2_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); + MmuPlugin_ports_1_cache_2_virtualAddress_0 <= MmuPlugin_shared_vpn_0; + MmuPlugin_ports_1_cache_2_virtualAddress_1 <= MmuPlugin_shared_vpn_1; + MmuPlugin_ports_1_cache_2_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; + MmuPlugin_ports_1_cache_2_physicalAddress_1 <= MmuPlugin_shared_dBusRsp_pte_PPN1[9 : 0]; + MmuPlugin_ports_1_cache_2_allowRead <= MmuPlugin_shared_dBusRsp_pte_R; + MmuPlugin_ports_1_cache_2_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; + MmuPlugin_ports_1_cache_2_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; + MmuPlugin_ports_1_cache_2_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; + MmuPlugin_ports_1_cache_2_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); + end + if(_zz_282)begin + MmuPlugin_ports_1_cache_3_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); + MmuPlugin_ports_1_cache_3_virtualAddress_0 <= MmuPlugin_shared_vpn_0; + MmuPlugin_ports_1_cache_3_virtualAddress_1 <= MmuPlugin_shared_vpn_1; + MmuPlugin_ports_1_cache_3_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; + MmuPlugin_ports_1_cache_3_physicalAddress_1 <= MmuPlugin_shared_dBusRsp_pte_PPN1[9 : 0]; + MmuPlugin_ports_1_cache_3_allowRead <= MmuPlugin_shared_dBusRsp_pte_R; + MmuPlugin_ports_1_cache_3_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; + MmuPlugin_ports_1_cache_3_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; + MmuPlugin_ports_1_cache_3_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; + MmuPlugin_ports_1_cache_3_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); + end + if(_zz_283)begin + MmuPlugin_ports_1_cache_4_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); + MmuPlugin_ports_1_cache_4_virtualAddress_0 <= MmuPlugin_shared_vpn_0; + MmuPlugin_ports_1_cache_4_virtualAddress_1 <= MmuPlugin_shared_vpn_1; + MmuPlugin_ports_1_cache_4_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; + MmuPlugin_ports_1_cache_4_physicalAddress_1 <= MmuPlugin_shared_dBusRsp_pte_PPN1[9 : 0]; + MmuPlugin_ports_1_cache_4_allowRead <= MmuPlugin_shared_dBusRsp_pte_R; + MmuPlugin_ports_1_cache_4_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; + MmuPlugin_ports_1_cache_4_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; + MmuPlugin_ports_1_cache_4_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; + MmuPlugin_ports_1_cache_4_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); + end + if(_zz_284)begin + MmuPlugin_ports_1_cache_5_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); + MmuPlugin_ports_1_cache_5_virtualAddress_0 <= MmuPlugin_shared_vpn_0; + MmuPlugin_ports_1_cache_5_virtualAddress_1 <= MmuPlugin_shared_vpn_1; + MmuPlugin_ports_1_cache_5_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; + MmuPlugin_ports_1_cache_5_physicalAddress_1 <= MmuPlugin_shared_dBusRsp_pte_PPN1[9 : 0]; + MmuPlugin_ports_1_cache_5_allowRead <= MmuPlugin_shared_dBusRsp_pte_R; + MmuPlugin_ports_1_cache_5_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; + MmuPlugin_ports_1_cache_5_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; + MmuPlugin_ports_1_cache_5_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; + MmuPlugin_ports_1_cache_5_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); + end + end + end + _zz_140 <= _zz_42[11 : 7]; + _zz_141 <= _zz_52; + if((memory_DivPlugin_div_counter_value == 6'h20))begin + memory_DivPlugin_div_done <= 1'b1; + end + if((! memory_arbitration_isStuck))begin + memory_DivPlugin_div_done <= 1'b0; + end + if(_zz_245)begin + if(_zz_270)begin + memory_DivPlugin_rs1[31 : 0] <= memory_DivPlugin_div_stage_0_outNumerator; + memory_DivPlugin_accumulator[31 : 0] <= memory_DivPlugin_div_stage_0_outRemainder; + if((memory_DivPlugin_div_counter_value == 6'h20))begin + memory_DivPlugin_div_result <= _zz_379[31:0]; + end + end + end + if(_zz_271)begin + memory_DivPlugin_accumulator <= 65'h0; + memory_DivPlugin_rs1 <= ((_zz_151 ? (~ _zz_152) : _zz_152) + _zz_385); + memory_DivPlugin_rs2 <= ((_zz_150 ? (~ execute_RS2) : execute_RS2) + _zz_387); + memory_DivPlugin_div_needRevert <= ((_zz_151 ^ (_zz_150 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + end + CsrPlugin_mip_MEIP <= externalInterrupt; + CsrPlugin_mip_MTIP <= timerInterrupt; + CsrPlugin_mip_MSIP <= softwareInterrupt; + CsrPlugin_mcycle <= (CsrPlugin_mcycle + 64'h0000000000000001); + if(writeBack_arbitration_isFiring)begin + CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); + end + if(_zz_250)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_157 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_157 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); + end + if(BranchPlugin_branchExceptionPort_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= BranchPlugin_branchExceptionPort_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= BranchPlugin_branchExceptionPort_payload_badAddr; + end + if(DBusCachedPlugin_exceptionBus_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr; + end + if(_zz_285)begin + if(_zz_286)begin + CsrPlugin_interrupt_code <= 4'b0111; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + if(_zz_287)begin + CsrPlugin_interrupt_code <= 4'b0011; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + if(_zz_288)begin + CsrPlugin_interrupt_code <= 4'b1011; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + end + if(_zz_253)begin + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); + CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause; + CsrPlugin_mepc <= writeBack_PC; + if(CsrPlugin_hadException)begin + CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + end + end + default : begin + end + endcase + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_PC <= decode_PC; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_PC <= _zz_37; + end + if(((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)))begin + memory_to_writeBack_PC <= memory_PC; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_FORMAL_PC_NEXT <= _zz_57; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_FORMAL_PC_NEXT <= execute_FORMAL_PC_NEXT; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_FORMAL_PC_NEXT <= _zz_56; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_PREDICTION_CONTEXT_hazard <= decode_PREDICTION_CONTEXT_hazard; + decode_to_execute_PREDICTION_CONTEXT_line_history <= decode_PREDICTION_CONTEXT_line_history; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_PREDICTION_CONTEXT_hazard <= execute_PREDICTION_CONTEXT_hazard; + execute_to_memory_PREDICTION_CONTEXT_line_history <= execute_PREDICTION_CONTEXT_line_history; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_FORCE_CONSTISTENCY <= decode_MEMORY_FORCE_CONSTISTENCY; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC1_CTRL <= _zz_27; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ALU_CTRL <= _zz_24; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC2_CTRL <= _zz_21; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_WR <= decode_MEMORY_WR; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_WR <= execute_MEMORY_WR; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_WR <= memory_MEMORY_WR; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_MANAGMENT <= decode_MEMORY_MANAGMENT; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_SFENCE_VMA <= decode_IS_SFENCE_VMA; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_IS_SFENCE_VMA <= execute_IS_SFENCE_VMA; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_IS_SFENCE_VMA <= memory_IS_SFENCE_VMA; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ALU_BITWISE_CTRL <= _zz_18; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SHIFT_CTRL <= _zz_15; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_SHIFT_CTRL <= _zz_12; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_MUL <= decode_IS_MUL; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_IS_MUL <= execute_IS_MUL; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_IS_MUL <= memory_IS_MUL; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_DIV <= decode_IS_DIV; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_IS_DIV <= execute_IS_DIV; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_CSR <= decode_IS_CSR; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ENV_CTRL <= _zz_10; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_ENV_CTRL <= _zz_7; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_ENV_CTRL <= _zz_5; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BRANCH_CTRL <= _zz_3; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BRANCH_CTRL <= _zz_1; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_RS1 <= decode_RS1; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_RS2 <= decode_RS2; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DO_EBREAK <= decode_DO_EBREAK; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_PREDICTION_HAD_BRANCHED2 <= decode_PREDICTION_HAD_BRANCHED2; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_REGFILE_WRITE_DATA <= _zz_33; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_34; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_SHIFT_RIGHT <= execute_SHIFT_RIGHT; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_LL <= execute_MUL_LL; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_LH <= execute_MUL_LH; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_HL <= execute_MUL_HL; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_HH <= execute_MUL_HH; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MUL_HH <= memory_MUL_HH; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BRANCH_DO <= execute_BRANCH_DO; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MUL_LOW <= memory_MUL_LOW; + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_768 <= (decode_INSTRUCTION[31 : 20] == 12'h300); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_256 <= (decode_INSTRUCTION[31 : 20] == 12'h100); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_384 <= (decode_INSTRUCTION[31 : 20] == 12'h180); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_836 <= (decode_INSTRUCTION[31 : 20] == 12'h344); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_772 <= (decode_INSTRUCTION[31 : 20] == 12'h304); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_833 <= (decode_INSTRUCTION[31 : 20] == 12'h341); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_834 <= (decode_INSTRUCTION[31 : 20] == 12'h342); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_835 <= (decode_INSTRUCTION[31 : 20] == 12'h343); + end + if(execute_CsrPlugin_csr_384)begin + if(execute_CsrPlugin_writeEnable)begin + MmuPlugin_satp_asid <= execute_CsrPlugin_writeData[30 : 22]; + MmuPlugin_satp_ppn <= execute_CsrPlugin_writeData[19 : 0]; + end + end + if(execute_CsrPlugin_csr_836)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mip_MSIP <= _zz_409[0]; + end + end + if(execute_CsrPlugin_csr_833)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0]; + end + end + end + + always @ (posedge clk) begin + DebugPlugin_firstCycle <= 1'b0; + if(debug_bus_cmd_ready)begin + DebugPlugin_firstCycle <= 1'b1; + end + DebugPlugin_secondCycle <= DebugPlugin_firstCycle; + DebugPlugin_isPipBusy <= (({writeBack_arbitration_isValid,{memory_arbitration_isValid,{execute_arbitration_isValid,decode_arbitration_isValid}}} != 4'b0000) || IBusCachedPlugin_incomingInstruction); + if(writeBack_arbitration_isValid)begin + DebugPlugin_busReadDataReg <= _zz_52; + end + _zz_158 <= debug_bus_cmd_payload_address[2]; + if(_zz_251)begin + DebugPlugin_busReadDataReg <= execute_PC; + end + DebugPlugin_resetIt_regNext <= DebugPlugin_resetIt; + end + + always @ (posedge clk or posedge debugReset) begin + if (debugReset) begin + DebugPlugin_resetIt <= 1'b0; + DebugPlugin_haltIt <= 1'b0; + DebugPlugin_stepIt <= 1'b0; + DebugPlugin_godmode <= 1'b0; + DebugPlugin_haltedByBreak <= 1'b0; + end else begin + if((DebugPlugin_haltIt && (! DebugPlugin_isPipBusy)))begin + DebugPlugin_godmode <= 1'b1; + end + if(debug_bus_cmd_valid)begin + case(_zz_273) + 6'h0 : begin + if(debug_bus_cmd_payload_wr)begin + DebugPlugin_stepIt <= debug_bus_cmd_payload_data[4]; + if(debug_bus_cmd_payload_data[16])begin + DebugPlugin_resetIt <= 1'b1; + end + if(debug_bus_cmd_payload_data[24])begin + DebugPlugin_resetIt <= 1'b0; + end + if(debug_bus_cmd_payload_data[17])begin + DebugPlugin_haltIt <= 1'b1; + end + if(debug_bus_cmd_payload_data[25])begin + DebugPlugin_haltIt <= 1'b0; + end + if(debug_bus_cmd_payload_data[25])begin + DebugPlugin_haltedByBreak <= 1'b0; + end + if(debug_bus_cmd_payload_data[25])begin + DebugPlugin_godmode <= 1'b0; + end + end + end + default : begin + end + endcase + end + if(_zz_251)begin + if(_zz_252)begin + DebugPlugin_haltIt <= 1'b1; + DebugPlugin_haltedByBreak <= 1'b1; + end + end + if(_zz_255)begin + if(decode_arbitration_isValid)begin + DebugPlugin_haltIt <= 1'b1; + end + end + end + end + + +endmodule + +module DataCache ( + input io_cpu_execute_isValid, + input [31:0] io_cpu_execute_address, + output io_cpu_execute_haltIt, + input io_cpu_execute_args_wr, + input [31:0] io_cpu_execute_args_data, + input [1:0] io_cpu_execute_args_size, + input io_cpu_execute_args_totalyConsistent, + output io_cpu_execute_refilling, + input io_cpu_memory_isValid, + input io_cpu_memory_isStuck, + output io_cpu_memory_isWrite, + input [31:0] io_cpu_memory_address, + input [31:0] io_cpu_memory_mmuRsp_physicalAddress, + input io_cpu_memory_mmuRsp_isIoAccess, + input io_cpu_memory_mmuRsp_isPaging, + input io_cpu_memory_mmuRsp_allowRead, + input io_cpu_memory_mmuRsp_allowWrite, + input io_cpu_memory_mmuRsp_allowExecute, + input io_cpu_memory_mmuRsp_exception, + input io_cpu_memory_mmuRsp_refilling, + input io_cpu_memory_mmuRsp_bypassTranslation, + input io_cpu_memory_mmuRsp_ways_0_sel, + input [31:0] io_cpu_memory_mmuRsp_ways_0_physical, + input io_cpu_memory_mmuRsp_ways_1_sel, + input [31:0] io_cpu_memory_mmuRsp_ways_1_physical, + input io_cpu_memory_mmuRsp_ways_2_sel, + input [31:0] io_cpu_memory_mmuRsp_ways_2_physical, + input io_cpu_memory_mmuRsp_ways_3_sel, + input [31:0] io_cpu_memory_mmuRsp_ways_3_physical, + input io_cpu_memory_mmuRsp_ways_4_sel, + input [31:0] io_cpu_memory_mmuRsp_ways_4_physical, + input io_cpu_memory_mmuRsp_ways_5_sel, + input [31:0] io_cpu_memory_mmuRsp_ways_5_physical, + input io_cpu_writeBack_isValid, + input io_cpu_writeBack_isStuck, + input io_cpu_writeBack_isUser, + output reg io_cpu_writeBack_haltIt, + output io_cpu_writeBack_isWrite, + output reg [31:0] io_cpu_writeBack_data, + input [31:0] io_cpu_writeBack_address, + output io_cpu_writeBack_mmuException, + output io_cpu_writeBack_unalignedAccess, + output reg io_cpu_writeBack_accessError, + output io_cpu_writeBack_keepMemRspData, + input io_cpu_writeBack_fence_SW, + input io_cpu_writeBack_fence_SR, + input io_cpu_writeBack_fence_SO, + input io_cpu_writeBack_fence_SI, + input io_cpu_writeBack_fence_PW, + input io_cpu_writeBack_fence_PR, + input io_cpu_writeBack_fence_PO, + input io_cpu_writeBack_fence_PI, + input [3:0] io_cpu_writeBack_fence_FM, + output reg io_cpu_redo, + input io_cpu_flush_valid, + output reg io_cpu_flush_ready, + output reg io_mem_cmd_valid, + input io_mem_cmd_ready, + output reg io_mem_cmd_payload_wr, + output io_mem_cmd_payload_uncached, + output reg [31:0] io_mem_cmd_payload_address, + output [31:0] io_mem_cmd_payload_data, + output [3:0] io_mem_cmd_payload_mask, + output reg [2:0] io_mem_cmd_payload_length, + output io_mem_cmd_payload_last, + input io_mem_rsp_valid, + input io_mem_rsp_payload_last, + input [31:0] io_mem_rsp_payload_data, + input io_mem_rsp_payload_error, + input clk, + input reset +); + reg [21:0] _zz_10; + reg [31:0] _zz_11; + wire _zz_12; + wire _zz_13; + wire _zz_14; + wire _zz_15; + wire _zz_16; + wire _zz_17; + wire _zz_18; + wire [0:0] _zz_19; + wire [0:0] _zz_20; + wire [9:0] _zz_21; + wire [9:0] _zz_22; + wire [0:0] _zz_23; + wire [0:0] _zz_24; + wire [2:0] _zz_25; + wire [1:0] _zz_26; + wire [21:0] _zz_27; + reg _zz_1; + reg _zz_2; + wire haltCpu; + reg tagsReadCmd_valid; + reg [6:0] tagsReadCmd_payload; + reg tagsWriteCmd_valid; + reg [0:0] tagsWriteCmd_payload_way; + reg [6:0] tagsWriteCmd_payload_address; + reg tagsWriteCmd_payload_data_valid; + reg tagsWriteCmd_payload_data_error; + reg [19:0] tagsWriteCmd_payload_data_address; + reg tagsWriteLastCmd_valid; + reg [0:0] tagsWriteLastCmd_payload_way; + reg [6:0] tagsWriteLastCmd_payload_address; + reg tagsWriteLastCmd_payload_data_valid; + reg tagsWriteLastCmd_payload_data_error; + reg [19:0] tagsWriteLastCmd_payload_data_address; + reg dataReadCmd_valid; + reg [9:0] dataReadCmd_payload; + reg dataWriteCmd_valid; + reg [0:0] dataWriteCmd_payload_way; + reg [9:0] dataWriteCmd_payload_address; + reg [31:0] dataWriteCmd_payload_data; + reg [3:0] dataWriteCmd_payload_mask; + wire _zz_3; + wire ways_0_tagsReadRsp_valid; + wire ways_0_tagsReadRsp_error; + wire [19:0] ways_0_tagsReadRsp_address; + wire [21:0] _zz_4; + wire _zz_5; + wire [31:0] ways_0_dataReadRspMem; + wire [31:0] ways_0_dataReadRsp; + wire rspSync; + wire rspLast; + reg memCmdSent; + reg [3:0] _zz_6; + wire [3:0] stage0_mask; + wire [0:0] stage0_dataColisions; + wire [0:0] stage0_wayInvalidate; + wire stage0_isAmo; + reg stageA_request_wr; + reg [31:0] stageA_request_data; + reg [1:0] stageA_request_size; + reg stageA_request_totalyConsistent; + reg [3:0] stageA_mask; + wire stageA_isAmo; + wire stageA_isLrsc; + wire [0:0] stageA_wayHits; + wire [0:0] _zz_7; + reg [0:0] stageA_wayInvalidate; + reg [0:0] stage0_dataColisions_regNextWhen; + wire [0:0] _zz_8; + wire [0:0] stageA_dataColisions; + reg stageB_request_wr; + reg [31:0] stageB_request_data; + reg [1:0] stageB_request_size; + reg stageB_request_totalyConsistent; + reg stageB_mmuRspFreeze; + reg [31:0] stageB_mmuRsp_physicalAddress; + reg stageB_mmuRsp_isIoAccess; + reg stageB_mmuRsp_isPaging; + reg stageB_mmuRsp_allowRead; + reg stageB_mmuRsp_allowWrite; + reg stageB_mmuRsp_allowExecute; + reg stageB_mmuRsp_exception; + reg stageB_mmuRsp_refilling; + reg stageB_mmuRsp_bypassTranslation; + reg stageB_mmuRsp_ways_0_sel; + reg [31:0] stageB_mmuRsp_ways_0_physical; + reg stageB_mmuRsp_ways_1_sel; + reg [31:0] stageB_mmuRsp_ways_1_physical; + reg stageB_mmuRsp_ways_2_sel; + reg [31:0] stageB_mmuRsp_ways_2_physical; + reg stageB_mmuRsp_ways_3_sel; + reg [31:0] stageB_mmuRsp_ways_3_physical; + reg stageB_mmuRsp_ways_4_sel; + reg [31:0] stageB_mmuRsp_ways_4_physical; + reg stageB_mmuRsp_ways_5_sel; + reg [31:0] stageB_mmuRsp_ways_5_physical; + reg stageB_tagsReadRsp_0_valid; + reg stageB_tagsReadRsp_0_error; + reg [19:0] stageB_tagsReadRsp_0_address; + reg [31:0] stageB_dataReadRsp_0; + reg [0:0] stageB_wayInvalidate; + wire stageB_consistancyHazard; + reg [0:0] stageB_dataColisions; + reg stageB_unaligned; + reg [0:0] stageB_waysHitsBeforeInvalidate; + wire [0:0] stageB_waysHits; + wire stageB_waysHit; + wire [31:0] stageB_dataMux; + reg [3:0] stageB_mask; + reg stageB_loaderValid; + wire [31:0] stageB_ioMemRspMuxed; + reg stageB_flusher_valid; + wire stageB_flusher_hold; + reg stageB_flusher_start; + wire stageB_isAmo; + wire stageB_isAmoCached; + wire stageB_isExternalLsrc; + wire stageB_isExternalAmo; + wire [31:0] stageB_requestDataBypass; + reg stageB_cpuWriteToCache; + wire stageB_badPermissions; + wire stageB_loadStoreFault; + wire stageB_bypassCache; + wire [0:0] _zz_9; + reg loader_valid; + reg loader_counter_willIncrement; + wire loader_counter_willClear; + reg [2:0] loader_counter_valueNext; + reg [2:0] loader_counter_value; + wire loader_counter_willOverflowIfInc; + wire loader_counter_willOverflow; + reg [0:0] loader_waysAllocator; + reg loader_error; + wire loader_kill; + reg loader_killReg; + wire loader_done; + reg loader_valid_regNext; + reg [21:0] ways_0_tags [0:127]; + reg [7:0] ways_0_data_symbol0 [0:1023]; + reg [7:0] ways_0_data_symbol1 [0:1023]; + reg [7:0] ways_0_data_symbol2 [0:1023]; + reg [7:0] ways_0_data_symbol3 [0:1023]; + reg [7:0] _zz_28; + reg [7:0] _zz_29; + reg [7:0] _zz_30; + reg [7:0] _zz_31; + + assign _zz_12 = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck)); + assign _zz_13 = ((((stageB_consistancyHazard || stageB_mmuRsp_refilling) || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess); + assign _zz_14 = ((loader_valid && io_mem_rsp_valid) && rspLast); + assign _zz_15 = (stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc); + assign _zz_16 = (stageB_waysHit || (stageB_request_wr && (! stageB_isAmoCached))); + assign _zz_17 = (! stageB_flusher_hold); + assign _zz_18 = (stageB_mmuRsp_physicalAddress[11 : 5] != 7'h7f); + assign _zz_19 = _zz_4[0 : 0]; + assign _zz_20 = _zz_4[1 : 1]; + assign _zz_21 = (io_cpu_execute_address[11 : 2] >>> 0); + assign _zz_22 = (io_cpu_memory_address[11 : 2] >>> 0); + assign _zz_23 = 1'b1; + assign _zz_24 = loader_counter_willIncrement; + assign _zz_25 = {2'd0, _zz_24}; + assign _zz_26 = {loader_waysAllocator,loader_waysAllocator[0]}; + assign _zz_27 = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; + always @ (posedge clk) begin + if(_zz_3) begin + _zz_10 <= ways_0_tags[tagsReadCmd_payload]; + end + end + + always @ (posedge clk) begin + if(_zz_2) begin + ways_0_tags[tagsWriteCmd_payload_address] <= _zz_27; + end + end + + always @ (*) begin + _zz_11 = {_zz_31, _zz_30, _zz_29, _zz_28}; + end + always @ (posedge clk) begin + if(_zz_5) begin + _zz_28 <= ways_0_data_symbol0[dataReadCmd_payload]; + _zz_29 <= ways_0_data_symbol1[dataReadCmd_payload]; + _zz_30 <= ways_0_data_symbol2[dataReadCmd_payload]; + _zz_31 <= ways_0_data_symbol3[dataReadCmd_payload]; + end + end + + always @ (posedge clk) begin + if(dataWriteCmd_payload_mask[0] && _zz_1) begin + ways_0_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0]; + end + if(dataWriteCmd_payload_mask[1] && _zz_1) begin + ways_0_data_symbol1[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[15 : 8]; + end + if(dataWriteCmd_payload_mask[2] && _zz_1) begin + ways_0_data_symbol2[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[23 : 16]; + end + if(dataWriteCmd_payload_mask[3] && _zz_1) begin + ways_0_data_symbol3[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[31 : 24]; + end + end + + always @ (*) begin + _zz_1 = 1'b0; + if((dataWriteCmd_valid && dataWriteCmd_payload_way[0]))begin + _zz_1 = 1'b1; + end + end + + always @ (*) begin + _zz_2 = 1'b0; + if((tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]))begin + _zz_2 = 1'b1; + end + end + + assign haltCpu = 1'b0; + assign _zz_3 = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); + assign _zz_4 = _zz_10; + assign ways_0_tagsReadRsp_valid = _zz_19[0]; + assign ways_0_tagsReadRsp_error = _zz_20[0]; + assign ways_0_tagsReadRsp_address = _zz_4[21 : 2]; + assign _zz_5 = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); + assign ways_0_dataReadRspMem = _zz_11; + assign ways_0_dataReadRsp = ways_0_dataReadRspMem[31 : 0]; + always @ (*) begin + tagsReadCmd_valid = 1'b0; + if(_zz_12)begin + tagsReadCmd_valid = 1'b1; + end + end + + always @ (*) begin + tagsReadCmd_payload = 7'h0; + if(_zz_12)begin + tagsReadCmd_payload = io_cpu_execute_address[11 : 5]; + end + end + + always @ (*) begin + dataReadCmd_valid = 1'b0; + if(_zz_12)begin + dataReadCmd_valid = 1'b1; + end + end + + always @ (*) begin + dataReadCmd_payload = 10'h0; + if(_zz_12)begin + dataReadCmd_payload = io_cpu_execute_address[11 : 2]; + end + end + + always @ (*) begin + tagsWriteCmd_valid = 1'b0; + if(stageB_flusher_valid)begin + tagsWriteCmd_valid = stageB_flusher_valid; + end + if(_zz_13)begin + tagsWriteCmd_valid = 1'b0; + end + if(loader_done)begin + tagsWriteCmd_valid = 1'b1; + end + end + + always @ (*) begin + tagsWriteCmd_payload_way = 1'bx; + if(stageB_flusher_valid)begin + tagsWriteCmd_payload_way = 1'b1; + end + if(loader_done)begin + tagsWriteCmd_payload_way = loader_waysAllocator; + end + end + + always @ (*) begin + tagsWriteCmd_payload_address = 7'h0; + if(stageB_flusher_valid)begin + tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; + end + if(loader_done)begin + tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; + end + end + + always @ (*) begin + tagsWriteCmd_payload_data_valid = 1'bx; + if(stageB_flusher_valid)begin + tagsWriteCmd_payload_data_valid = 1'b0; + end + if(loader_done)begin + tagsWriteCmd_payload_data_valid = (! (loader_kill || loader_killReg)); + end + end + + always @ (*) begin + tagsWriteCmd_payload_data_error = 1'bx; + if(loader_done)begin + tagsWriteCmd_payload_data_error = (loader_error || (io_mem_rsp_valid && io_mem_rsp_payload_error)); + end + end + + always @ (*) begin + tagsWriteCmd_payload_data_address = 20'h0; + if(loader_done)begin + tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 12]; + end + end + + always @ (*) begin + dataWriteCmd_valid = 1'b0; + if(stageB_cpuWriteToCache)begin + if((stageB_request_wr && stageB_waysHit))begin + dataWriteCmd_valid = 1'b1; + end + end + if(_zz_13)begin + dataWriteCmd_valid = 1'b0; + end + if(_zz_14)begin + dataWriteCmd_valid = 1'b1; + end + end + + always @ (*) begin + dataWriteCmd_payload_way = 1'bx; + if(stageB_cpuWriteToCache)begin + dataWriteCmd_payload_way = stageB_waysHits; + end + if(_zz_14)begin + dataWriteCmd_payload_way = loader_waysAllocator; + end + end + + always @ (*) begin + dataWriteCmd_payload_address = 10'h0; + if(stageB_cpuWriteToCache)begin + dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 2]; + end + if(_zz_14)begin + dataWriteCmd_payload_address = {stageB_mmuRsp_physicalAddress[11 : 5],loader_counter_value}; + end + end + + always @ (*) begin + dataWriteCmd_payload_data = 32'h0; + if(stageB_cpuWriteToCache)begin + dataWriteCmd_payload_data[31 : 0] = stageB_requestDataBypass; + end + if(_zz_14)begin + dataWriteCmd_payload_data = io_mem_rsp_payload_data; + end + end + + always @ (*) begin + dataWriteCmd_payload_mask = 4'bxxxx; + if(stageB_cpuWriteToCache)begin + dataWriteCmd_payload_mask = 4'b0000; + if(_zz_23[0])begin + dataWriteCmd_payload_mask[3 : 0] = stageB_mask; + end + end + if(_zz_14)begin + dataWriteCmd_payload_mask = 4'b1111; + end + end + + assign io_cpu_execute_haltIt = 1'b0; + assign rspSync = 1'b1; + assign rspLast = 1'b1; + always @ (*) begin + case(io_cpu_execute_args_size) + 2'b00 : begin + _zz_6 = 4'b0001; + end + 2'b01 : begin + _zz_6 = 4'b0011; + end + default : begin + _zz_6 = 4'b1111; + end + endcase + end + + assign stage0_mask = (_zz_6 <<< io_cpu_execute_address[1 : 0]); + assign stage0_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_21)) && ((stage0_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); + assign stage0_wayInvalidate = 1'b0; + assign stage0_isAmo = 1'b0; + assign io_cpu_memory_isWrite = stageA_request_wr; + assign stageA_isAmo = 1'b0; + assign stageA_isLrsc = 1'b0; + assign _zz_7[0] = ((io_cpu_memory_mmuRsp_physicalAddress[31 : 12] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid); + assign stageA_wayHits = _zz_7; + assign _zz_8[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_22)) && ((stageA_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); + assign stageA_dataColisions = (stage0_dataColisions_regNextWhen | _zz_8); + always @ (*) begin + stageB_mmuRspFreeze = 1'b0; + if((stageB_loaderValid || loader_valid))begin + stageB_mmuRspFreeze = 1'b1; + end + end + + assign stageB_consistancyHazard = 1'b0; + assign stageB_waysHits = (stageB_waysHitsBeforeInvalidate & (~ stageB_wayInvalidate)); + assign stageB_waysHit = (stageB_waysHits != 1'b0); + assign stageB_dataMux = stageB_dataReadRsp_0; + always @ (*) begin + stageB_loaderValid = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_15) begin + if(! _zz_16) begin + if(io_mem_cmd_ready)begin + stageB_loaderValid = 1'b1; + end + end + end + end + end + if(_zz_13)begin + stageB_loaderValid = 1'b0; + end + end + + assign stageB_ioMemRspMuxed = io_mem_rsp_payload_data[31 : 0]; + always @ (*) begin + io_cpu_writeBack_haltIt = io_cpu_writeBack_isValid; + if(stageB_flusher_valid)begin + io_cpu_writeBack_haltIt = 1'b1; + end + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(_zz_15)begin + if(((! stageB_request_wr) ? (io_mem_rsp_valid && rspSync) : io_mem_cmd_ready))begin + io_cpu_writeBack_haltIt = 1'b0; + end + end else begin + if(_zz_16)begin + if(((! stageB_request_wr) || io_mem_cmd_ready))begin + io_cpu_writeBack_haltIt = 1'b0; + end + end + end + end + end + if(_zz_13)begin + io_cpu_writeBack_haltIt = 1'b0; + end + end + + assign stageB_flusher_hold = 1'b0; + always @ (*) begin + io_cpu_flush_ready = 1'b0; + if(stageB_flusher_start)begin + io_cpu_flush_ready = 1'b1; + end + end + + assign stageB_isAmo = 1'b0; + assign stageB_isAmoCached = 1'b0; + assign stageB_isExternalLsrc = 1'b0; + assign stageB_isExternalAmo = 1'b0; + assign stageB_requestDataBypass = stageB_request_data; + always @ (*) begin + stageB_cpuWriteToCache = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_15) begin + if(_zz_16)begin + stageB_cpuWriteToCache = 1'b1; + end + end + end + end + end + + assign stageB_badPermissions = (((! stageB_mmuRsp_allowWrite) && stageB_request_wr) || ((! stageB_mmuRsp_allowRead) && ((! stageB_request_wr) || stageB_isAmo))); + assign stageB_loadStoreFault = (io_cpu_writeBack_isValid && (stageB_mmuRsp_exception || stageB_badPermissions)); + always @ (*) begin + io_cpu_redo = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_15) begin + if(_zz_16)begin + if((((! stageB_request_wr) || stageB_isAmoCached) && ((stageB_dataColisions & stageB_waysHits) != 1'b0)))begin + io_cpu_redo = 1'b1; + end + end + end + end + end + if((io_cpu_writeBack_isValid && (stageB_mmuRsp_refilling || stageB_consistancyHazard)))begin + io_cpu_redo = 1'b1; + end + if((loader_valid && (! loader_valid_regNext)))begin + io_cpu_redo = 1'b1; + end + end + + always @ (*) begin + io_cpu_writeBack_accessError = 1'b0; + if(stageB_bypassCache)begin + io_cpu_writeBack_accessError = ((((! stageB_request_wr) && 1'b1) && io_mem_rsp_valid) && io_mem_rsp_payload_error); + end else begin + io_cpu_writeBack_accessError = (((stageB_waysHits & _zz_9) != 1'b0) || (stageB_loadStoreFault && (! stageB_mmuRsp_isPaging))); + end + end + + assign io_cpu_writeBack_mmuException = (stageB_loadStoreFault && stageB_mmuRsp_isPaging); + assign io_cpu_writeBack_unalignedAccess = (io_cpu_writeBack_isValid && stageB_unaligned); + assign io_cpu_writeBack_isWrite = stageB_request_wr; + always @ (*) begin + io_mem_cmd_valid = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(_zz_15)begin + io_mem_cmd_valid = (! memCmdSent); + end else begin + if(_zz_16)begin + if(stageB_request_wr)begin + io_mem_cmd_valid = 1'b1; + end + end else begin + if((! memCmdSent))begin + io_mem_cmd_valid = 1'b1; + end + end + end + end + end + if(_zz_13)begin + io_mem_cmd_valid = 1'b0; + end + end + + always @ (*) begin + io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],2'b00}; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_15) begin + if(_zz_16)begin + io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],2'b00}; + end else begin + io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 5],5'h0}; + end + end + end + end + end + + always @ (*) begin + io_mem_cmd_payload_length = 3'b000; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_15) begin + if(_zz_16)begin + io_mem_cmd_payload_length = 3'b000; + end else begin + io_mem_cmd_payload_length = 3'b111; + end + end + end + end + end + + assign io_mem_cmd_payload_last = 1'b1; + always @ (*) begin + io_mem_cmd_payload_wr = stageB_request_wr; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_15) begin + if(! _zz_16) begin + io_mem_cmd_payload_wr = 1'b0; + end + end + end + end + end + + assign io_mem_cmd_payload_mask = stageB_mask; + assign io_mem_cmd_payload_data = stageB_requestDataBypass; + assign io_mem_cmd_payload_uncached = stageB_mmuRsp_isIoAccess; + assign stageB_bypassCache = ((stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc) || stageB_isExternalAmo); + assign io_cpu_writeBack_keepMemRspData = 1'b0; + always @ (*) begin + if(stageB_bypassCache)begin + io_cpu_writeBack_data = stageB_ioMemRspMuxed; + end else begin + io_cpu_writeBack_data = stageB_dataMux; + end + end + + assign _zz_9[0] = stageB_tagsReadRsp_0_error; + always @ (*) begin + loader_counter_willIncrement = 1'b0; + if(_zz_14)begin + loader_counter_willIncrement = 1'b1; + end + end + + assign loader_counter_willClear = 1'b0; + assign loader_counter_willOverflowIfInc = (loader_counter_value == 3'b111); + assign loader_counter_willOverflow = (loader_counter_willOverflowIfInc && loader_counter_willIncrement); + always @ (*) begin + loader_counter_valueNext = (loader_counter_value + _zz_25); + if(loader_counter_willClear)begin + loader_counter_valueNext = 3'b000; + end + end + + assign loader_kill = 1'b0; + assign loader_done = loader_counter_willOverflow; + assign io_cpu_execute_refilling = loader_valid; + always @ (posedge clk) begin + tagsWriteLastCmd_valid <= tagsWriteCmd_valid; + tagsWriteLastCmd_payload_way <= tagsWriteCmd_payload_way; + tagsWriteLastCmd_payload_address <= tagsWriteCmd_payload_address; + tagsWriteLastCmd_payload_data_valid <= tagsWriteCmd_payload_data_valid; + tagsWriteLastCmd_payload_data_error <= tagsWriteCmd_payload_data_error; + tagsWriteLastCmd_payload_data_address <= tagsWriteCmd_payload_data_address; + if((! io_cpu_memory_isStuck))begin + stageA_request_wr <= io_cpu_execute_args_wr; + stageA_request_data <= io_cpu_execute_args_data; + stageA_request_size <= io_cpu_execute_args_size; + stageA_request_totalyConsistent <= io_cpu_execute_args_totalyConsistent; + end + if((! io_cpu_memory_isStuck))begin + stageA_mask <= stage0_mask; + end + if((! io_cpu_memory_isStuck))begin + stageA_wayInvalidate <= stage0_wayInvalidate; + end + if((! io_cpu_memory_isStuck))begin + stage0_dataColisions_regNextWhen <= stage0_dataColisions; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_request_wr <= stageA_request_wr; + stageB_request_data <= stageA_request_data; + stageB_request_size <= stageA_request_size; + stageB_request_totalyConsistent <= stageA_request_totalyConsistent; + end + if(((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze)))begin + stageB_mmuRsp_physicalAddress <= io_cpu_memory_mmuRsp_physicalAddress; + stageB_mmuRsp_isIoAccess <= io_cpu_memory_mmuRsp_isIoAccess; + stageB_mmuRsp_isPaging <= io_cpu_memory_mmuRsp_isPaging; + stageB_mmuRsp_allowRead <= io_cpu_memory_mmuRsp_allowRead; + stageB_mmuRsp_allowWrite <= io_cpu_memory_mmuRsp_allowWrite; + stageB_mmuRsp_allowExecute <= io_cpu_memory_mmuRsp_allowExecute; + stageB_mmuRsp_exception <= io_cpu_memory_mmuRsp_exception; + stageB_mmuRsp_refilling <= io_cpu_memory_mmuRsp_refilling; + stageB_mmuRsp_bypassTranslation <= io_cpu_memory_mmuRsp_bypassTranslation; + stageB_mmuRsp_ways_0_sel <= io_cpu_memory_mmuRsp_ways_0_sel; + stageB_mmuRsp_ways_0_physical <= io_cpu_memory_mmuRsp_ways_0_physical; + stageB_mmuRsp_ways_1_sel <= io_cpu_memory_mmuRsp_ways_1_sel; + stageB_mmuRsp_ways_1_physical <= io_cpu_memory_mmuRsp_ways_1_physical; + stageB_mmuRsp_ways_2_sel <= io_cpu_memory_mmuRsp_ways_2_sel; + stageB_mmuRsp_ways_2_physical <= io_cpu_memory_mmuRsp_ways_2_physical; + stageB_mmuRsp_ways_3_sel <= io_cpu_memory_mmuRsp_ways_3_sel; + stageB_mmuRsp_ways_3_physical <= io_cpu_memory_mmuRsp_ways_3_physical; + stageB_mmuRsp_ways_4_sel <= io_cpu_memory_mmuRsp_ways_4_sel; + stageB_mmuRsp_ways_4_physical <= io_cpu_memory_mmuRsp_ways_4_physical; + stageB_mmuRsp_ways_5_sel <= io_cpu_memory_mmuRsp_ways_5_sel; + stageB_mmuRsp_ways_5_physical <= io_cpu_memory_mmuRsp_ways_5_physical; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_tagsReadRsp_0_valid <= ways_0_tagsReadRsp_valid; + stageB_tagsReadRsp_0_error <= ways_0_tagsReadRsp_error; + stageB_tagsReadRsp_0_address <= ways_0_tagsReadRsp_address; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_dataReadRsp_0 <= ways_0_dataReadRsp; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_wayInvalidate <= stageA_wayInvalidate; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_dataColisions <= stageA_dataColisions; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_unaligned <= (((stageA_request_size == 2'b10) && (io_cpu_memory_address[1 : 0] != 2'b00)) || ((stageA_request_size == 2'b01) && (io_cpu_memory_address[0 : 0] != 1'b0))); + end + if((! io_cpu_writeBack_isStuck))begin + stageB_waysHitsBeforeInvalidate <= stageA_wayHits; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_mask <= stageA_mask; + end + if(stageB_flusher_valid)begin + if(_zz_17)begin + if(_zz_18)begin + stageB_mmuRsp_physicalAddress[11 : 5] <= (stageB_mmuRsp_physicalAddress[11 : 5] + 7'h01); + end + end + end + if(stageB_flusher_start)begin + stageB_mmuRsp_physicalAddress[11 : 5] <= 7'h0; + end + loader_valid_regNext <= loader_valid; + end + + always @ (posedge clk or posedge reset) begin + if (reset) begin + memCmdSent <= 1'b0; + stageB_flusher_valid <= 1'b0; + stageB_flusher_start <= 1'b1; + loader_valid <= 1'b0; + loader_counter_value <= 3'b000; + loader_waysAllocator <= 1'b1; + loader_error <= 1'b0; + loader_killReg <= 1'b0; + end else begin + if(io_mem_cmd_ready)begin + memCmdSent <= 1'b1; + end + if((! io_cpu_writeBack_isStuck))begin + memCmdSent <= 1'b0; + end + if(stageB_flusher_valid)begin + if(_zz_17)begin + if(! _zz_18) begin + stageB_flusher_valid <= 1'b0; + end + end + end + stageB_flusher_start <= ((((((! stageB_flusher_start) && io_cpu_flush_valid) && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo)); + if(stageB_flusher_start)begin + stageB_flusher_valid <= 1'b1; + end + `ifndef SYNTHESIS + `ifdef FORMAL + assert((! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))); + `else + if(!(! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))) begin + $display("FAILURE writeBack stuck by another plugin is not allowed"); + $finish; + end + `endif + `endif + if(stageB_loaderValid)begin + loader_valid <= 1'b1; + end + loader_counter_value <= loader_counter_valueNext; + if(loader_kill)begin + loader_killReg <= 1'b1; + end + if(_zz_14)begin + loader_error <= (loader_error || io_mem_rsp_payload_error); + end + if(loader_done)begin + loader_valid <= 1'b0; + loader_error <= 1'b0; + loader_killReg <= 1'b0; + end + if((! loader_valid))begin + loader_waysAllocator <= _zz_26[0:0]; + end + end + end + + +endmodule + +module InstructionCache ( + input io_flush, + input io_cpu_prefetch_isValid, + output reg io_cpu_prefetch_haltIt, + input [31:0] io_cpu_prefetch_pc, + input io_cpu_fetch_isValid, + input io_cpu_fetch_isStuck, + input io_cpu_fetch_isRemoved, + input [31:0] io_cpu_fetch_pc, + output [31:0] io_cpu_fetch_data, + input [31:0] io_cpu_fetch_mmuRsp_physicalAddress, + input io_cpu_fetch_mmuRsp_isIoAccess, + input io_cpu_fetch_mmuRsp_isPaging, + input io_cpu_fetch_mmuRsp_allowRead, + input io_cpu_fetch_mmuRsp_allowWrite, + input io_cpu_fetch_mmuRsp_allowExecute, + input io_cpu_fetch_mmuRsp_exception, + input io_cpu_fetch_mmuRsp_refilling, + input io_cpu_fetch_mmuRsp_bypassTranslation, + input io_cpu_fetch_mmuRsp_ways_0_sel, + input [31:0] io_cpu_fetch_mmuRsp_ways_0_physical, + input io_cpu_fetch_mmuRsp_ways_1_sel, + input [31:0] io_cpu_fetch_mmuRsp_ways_1_physical, + input io_cpu_fetch_mmuRsp_ways_2_sel, + input [31:0] io_cpu_fetch_mmuRsp_ways_2_physical, + input io_cpu_fetch_mmuRsp_ways_3_sel, + input [31:0] io_cpu_fetch_mmuRsp_ways_3_physical, + output [31:0] io_cpu_fetch_physicalAddress, + input io_cpu_decode_isValid, + input io_cpu_decode_isStuck, + input [31:0] io_cpu_decode_pc, + output [31:0] io_cpu_decode_physicalAddress, + output [31:0] io_cpu_decode_data, + output io_cpu_decode_cacheMiss, + output io_cpu_decode_error, + output io_cpu_decode_mmuRefilling, + output io_cpu_decode_mmuException, + input io_cpu_decode_isUser, + input io_cpu_fill_valid, + input [31:0] io_cpu_fill_payload, + output io_mem_cmd_valid, + input io_mem_cmd_ready, + output [31:0] io_mem_cmd_payload_address, + output [2:0] io_mem_cmd_payload_size, + input io_mem_rsp_valid, + input [31:0] io_mem_rsp_payload_data, + input io_mem_rsp_payload_error, + input [2:0] _zz_10, + input [31:0] _zz_11, + input clk, + input reset +); + reg [31:0] _zz_12; + reg [21:0] _zz_13; + wire _zz_14; + wire _zz_15; + wire [0:0] _zz_16; + wire [0:0] _zz_17; + wire [21:0] _zz_18; + reg _zz_1; + reg _zz_2; + reg lineLoader_fire; + reg lineLoader_valid; + (* keep , syn_keep *) reg [31:0] lineLoader_address /* synthesis syn_keep = 1 */ ; + reg lineLoader_hadError; + reg lineLoader_flushPending; + reg [7:0] lineLoader_flushCounter; + reg _zz_3; + reg lineLoader_cmdSent; + reg lineLoader_wayToAllocate_willIncrement; + wire lineLoader_wayToAllocate_willClear; + wire lineLoader_wayToAllocate_willOverflowIfInc; + wire lineLoader_wayToAllocate_willOverflow; + (* keep , syn_keep *) reg [2:0] lineLoader_wordIndex /* synthesis syn_keep = 1 */ ; + wire lineLoader_write_tag_0_valid; + wire [6:0] lineLoader_write_tag_0_payload_address; + wire lineLoader_write_tag_0_payload_data_valid; + wire lineLoader_write_tag_0_payload_data_error; + wire [19:0] lineLoader_write_tag_0_payload_data_address; + wire lineLoader_write_data_0_valid; + wire [9:0] lineLoader_write_data_0_payload_address; + wire [31:0] lineLoader_write_data_0_payload_data; + wire [9:0] _zz_4; + wire _zz_5; + wire [31:0] fetchStage_read_banksValue_0_dataMem; + wire [31:0] fetchStage_read_banksValue_0_data; + wire [6:0] _zz_6; + wire _zz_7; + wire fetchStage_read_waysValues_0_tag_valid; + wire fetchStage_read_waysValues_0_tag_error; + wire [19:0] fetchStage_read_waysValues_0_tag_address; + wire [21:0] _zz_8; + reg [31:0] decodeStage_mmuRsp_physicalAddress; + reg decodeStage_mmuRsp_isIoAccess; + reg decodeStage_mmuRsp_isPaging; + reg decodeStage_mmuRsp_allowRead; + reg decodeStage_mmuRsp_allowWrite; + reg decodeStage_mmuRsp_allowExecute; + reg decodeStage_mmuRsp_exception; + reg decodeStage_mmuRsp_refilling; + reg decodeStage_mmuRsp_bypassTranslation; + reg decodeStage_mmuRsp_ways_0_sel; + reg [31:0] decodeStage_mmuRsp_ways_0_physical; + reg decodeStage_mmuRsp_ways_1_sel; + reg [31:0] decodeStage_mmuRsp_ways_1_physical; + reg decodeStage_mmuRsp_ways_2_sel; + reg [31:0] decodeStage_mmuRsp_ways_2_physical; + reg decodeStage_mmuRsp_ways_3_sel; + reg [31:0] decodeStage_mmuRsp_ways_3_physical; + reg decodeStage_hit_tags_0_valid; + reg decodeStage_hit_tags_0_error; + reg [19:0] decodeStage_hit_tags_0_address; + wire decodeStage_hit_hits_0; + wire decodeStage_hit_valid; + reg [31:0] _zz_9; + wire [31:0] decodeStage_hit_data; + reg [31:0] banks_0 [0:1023]; + reg [21:0] ways_0_tags [0:127]; + + assign _zz_14 = (! lineLoader_flushCounter[7]); + assign _zz_15 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); + assign _zz_16 = _zz_8[0 : 0]; + assign _zz_17 = _zz_8[1 : 1]; + assign _zz_18 = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; + always @ (posedge clk) begin + if(_zz_1) begin + banks_0[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data; + end + end + + always @ (posedge clk) begin + if(_zz_5) begin + _zz_12 <= banks_0[_zz_4]; + end + end + + always @ (posedge clk) begin + if(_zz_2) begin + ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_18; + end + end + + always @ (posedge clk) begin + if(_zz_7) begin + _zz_13 <= ways_0_tags[_zz_6]; + end + end + + always @ (*) begin + _zz_1 = 1'b0; + if(lineLoader_write_data_0_valid)begin + _zz_1 = 1'b1; + end + end + + always @ (*) begin + _zz_2 = 1'b0; + if(lineLoader_write_tag_0_valid)begin + _zz_2 = 1'b1; + end + end + + always @ (*) begin + lineLoader_fire = 1'b0; + if(io_mem_rsp_valid)begin + if((lineLoader_wordIndex == 3'b111))begin + lineLoader_fire = 1'b1; + end + end + end + + always @ (*) begin + io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending); + if(_zz_14)begin + io_cpu_prefetch_haltIt = 1'b1; + end + if((! _zz_3))begin + io_cpu_prefetch_haltIt = 1'b1; + end + if(io_flush)begin + io_cpu_prefetch_haltIt = 1'b1; + end + end + + assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent)); + assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],5'h0}; + assign io_mem_cmd_payload_size = 3'b101; + always @ (*) begin + lineLoader_wayToAllocate_willIncrement = 1'b0; + if((! lineLoader_valid))begin + lineLoader_wayToAllocate_willIncrement = 1'b1; + end + end + + assign lineLoader_wayToAllocate_willClear = 1'b0; + assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1; + assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement); + assign lineLoader_write_tag_0_valid = ((1'b1 && lineLoader_fire) || (! lineLoader_flushCounter[7])); + assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[7] ? lineLoader_address[11 : 5] : lineLoader_flushCounter[6 : 0]); + assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[7]; + assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error); + assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 12]; + assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && 1'b1); + assign lineLoader_write_data_0_payload_address = {lineLoader_address[11 : 5],lineLoader_wordIndex}; + assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data; + assign _zz_4 = io_cpu_prefetch_pc[11 : 2]; + assign _zz_5 = (! io_cpu_fetch_isStuck); + assign fetchStage_read_banksValue_0_dataMem = _zz_12; + assign fetchStage_read_banksValue_0_data = fetchStage_read_banksValue_0_dataMem[31 : 0]; + assign _zz_6 = io_cpu_prefetch_pc[11 : 5]; + assign _zz_7 = (! io_cpu_fetch_isStuck); + assign _zz_8 = _zz_13; + assign fetchStage_read_waysValues_0_tag_valid = _zz_16[0]; + assign fetchStage_read_waysValues_0_tag_error = _zz_17[0]; + assign fetchStage_read_waysValues_0_tag_address = _zz_8[21 : 2]; + assign io_cpu_fetch_data = fetchStage_read_banksValue_0_data; + assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuRsp_physicalAddress; + assign decodeStage_hit_hits_0 = (decodeStage_hit_tags_0_valid && (decodeStage_hit_tags_0_address == decodeStage_mmuRsp_physicalAddress[31 : 12])); + assign decodeStage_hit_valid = (decodeStage_hit_hits_0 != 1'b0); + assign decodeStage_hit_data = _zz_9; + assign io_cpu_decode_data = decodeStage_hit_data; + assign io_cpu_decode_cacheMiss = (! decodeStage_hit_valid); + assign io_cpu_decode_error = (decodeStage_hit_tags_0_error || ((! decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute)))); + assign io_cpu_decode_mmuRefilling = decodeStage_mmuRsp_refilling; + assign io_cpu_decode_mmuException = (((! decodeStage_mmuRsp_refilling) && decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute))); + assign io_cpu_decode_physicalAddress = decodeStage_mmuRsp_physicalAddress; + always @ (posedge clk or posedge reset) begin + if (reset) begin + lineLoader_valid <= 1'b0; + lineLoader_hadError <= 1'b0; + lineLoader_flushPending <= 1'b1; + lineLoader_cmdSent <= 1'b0; + lineLoader_wordIndex <= 3'b000; + end else begin + if(lineLoader_fire)begin + lineLoader_valid <= 1'b0; + end + if(lineLoader_fire)begin + lineLoader_hadError <= 1'b0; + end + if(io_cpu_fill_valid)begin + lineLoader_valid <= 1'b1; + end + if(io_flush)begin + lineLoader_flushPending <= 1'b1; + end + if(_zz_15)begin + lineLoader_flushPending <= 1'b0; + end + if((io_mem_cmd_valid && io_mem_cmd_ready))begin + lineLoader_cmdSent <= 1'b1; + end + if(lineLoader_fire)begin + lineLoader_cmdSent <= 1'b0; + end + if(io_mem_rsp_valid)begin + lineLoader_wordIndex <= (lineLoader_wordIndex + 3'b001); + if(io_mem_rsp_payload_error)begin + lineLoader_hadError <= 1'b1; + end + end + end + end + + always @ (posedge clk) begin + if(io_cpu_fill_valid)begin + lineLoader_address <= io_cpu_fill_payload; + end + if(_zz_14)begin + lineLoader_flushCounter <= (lineLoader_flushCounter + 8'h01); + end + _zz_3 <= lineLoader_flushCounter[7]; + if(_zz_15)begin + lineLoader_flushCounter <= 8'h0; + end + if((! io_cpu_decode_isStuck))begin + decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuRsp_physicalAddress; + decodeStage_mmuRsp_isIoAccess <= io_cpu_fetch_mmuRsp_isIoAccess; + decodeStage_mmuRsp_isPaging <= io_cpu_fetch_mmuRsp_isPaging; + decodeStage_mmuRsp_allowRead <= io_cpu_fetch_mmuRsp_allowRead; + decodeStage_mmuRsp_allowWrite <= io_cpu_fetch_mmuRsp_allowWrite; + decodeStage_mmuRsp_allowExecute <= io_cpu_fetch_mmuRsp_allowExecute; + decodeStage_mmuRsp_exception <= io_cpu_fetch_mmuRsp_exception; + decodeStage_mmuRsp_refilling <= io_cpu_fetch_mmuRsp_refilling; + decodeStage_mmuRsp_bypassTranslation <= io_cpu_fetch_mmuRsp_bypassTranslation; + decodeStage_mmuRsp_ways_0_sel <= io_cpu_fetch_mmuRsp_ways_0_sel; + decodeStage_mmuRsp_ways_0_physical <= io_cpu_fetch_mmuRsp_ways_0_physical; + decodeStage_mmuRsp_ways_1_sel <= io_cpu_fetch_mmuRsp_ways_1_sel; + decodeStage_mmuRsp_ways_1_physical <= io_cpu_fetch_mmuRsp_ways_1_physical; + decodeStage_mmuRsp_ways_2_sel <= io_cpu_fetch_mmuRsp_ways_2_sel; + decodeStage_mmuRsp_ways_2_physical <= io_cpu_fetch_mmuRsp_ways_2_physical; + decodeStage_mmuRsp_ways_3_sel <= io_cpu_fetch_mmuRsp_ways_3_sel; + decodeStage_mmuRsp_ways_3_physical <= io_cpu_fetch_mmuRsp_ways_3_physical; + end + if((! io_cpu_decode_isStuck))begin + decodeStage_hit_tags_0_valid <= fetchStage_read_waysValues_0_tag_valid; + decodeStage_hit_tags_0_error <= fetchStage_read_waysValues_0_tag_error; + decodeStage_hit_tags_0_address <= fetchStage_read_waysValues_0_tag_address; + end + if((! io_cpu_decode_isStuck))begin + _zz_9 <= fetchStage_read_banksValue_0_data; + end + if((_zz_10 != 3'b000))begin + _zz_9 <= _zz_11; + end + end + + +endmodule diff --git a/openfpga_flow/benchmarks/processor/vexriscv/vexriscv_linux.v b/openfpga_flow/benchmarks/processor/vexriscv/vexriscv_linux.v new file mode 100644 index 0000000000..b060c3002e --- /dev/null +++ b/openfpga_flow/benchmarks/processor/vexriscv/vexriscv_linux.v @@ -0,0 +1,8639 @@ +// Generator : SpinalHDL v1.5.0 git head : 83a031922866b078c411ec5529e00f1b6e79f8e7 +// Component : VexRiscv +// Git hash : d67fe72de9f5ce288f2667b150314c926f4bbf4d + + +`define BranchCtrlEnum_defaultEncoding_type [1:0] +`define BranchCtrlEnum_defaultEncoding_INC 2'b00 +`define BranchCtrlEnum_defaultEncoding_B 2'b01 +`define BranchCtrlEnum_defaultEncoding_JAL 2'b10 +`define BranchCtrlEnum_defaultEncoding_JALR 2'b11 + +`define EnvCtrlEnum_defaultEncoding_type [1:0] +`define EnvCtrlEnum_defaultEncoding_NONE 2'b00 +`define EnvCtrlEnum_defaultEncoding_XRET 2'b01 +`define EnvCtrlEnum_defaultEncoding_WFI 2'b10 +`define EnvCtrlEnum_defaultEncoding_ECALL 2'b11 + +`define ShiftCtrlEnum_defaultEncoding_type [1:0] +`define ShiftCtrlEnum_defaultEncoding_DISABLE 2'b00 +`define ShiftCtrlEnum_defaultEncoding_SLL 2'b01 +`define ShiftCtrlEnum_defaultEncoding_SRL 2'b10 +`define ShiftCtrlEnum_defaultEncoding_SRA 2'b11 + +`define AluBitwiseCtrlEnum_defaultEncoding_type [1:0] +`define AluBitwiseCtrlEnum_defaultEncoding_XOR 2'b00 +`define AluBitwiseCtrlEnum_defaultEncoding_OR 2'b01 +`define AluBitwiseCtrlEnum_defaultEncoding_AND 2'b10 + +`define AluCtrlEnum_defaultEncoding_type [1:0] +`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00 +`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01 +`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10 + +`define Src2CtrlEnum_defaultEncoding_type [1:0] +`define Src2CtrlEnum_defaultEncoding_RS 2'b00 +`define Src2CtrlEnum_defaultEncoding_IMI 2'b01 +`define Src2CtrlEnum_defaultEncoding_IMS 2'b10 +`define Src2CtrlEnum_defaultEncoding_PC 2'b11 + +`define Src1CtrlEnum_defaultEncoding_type [1:0] +`define Src1CtrlEnum_defaultEncoding_RS 2'b00 +`define Src1CtrlEnum_defaultEncoding_IMU 2'b01 +`define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10 +`define Src1CtrlEnum_defaultEncoding_URS1 2'b11 + +`define MmuPlugin_shared_State_defaultEncoding_type [2:0] +`define MmuPlugin_shared_State_defaultEncoding_IDLE 3'b000 +`define MmuPlugin_shared_State_defaultEncoding_L1_CMD 3'b001 +`define MmuPlugin_shared_State_defaultEncoding_L1_RSP 3'b010 +`define MmuPlugin_shared_State_defaultEncoding_L0_CMD 3'b011 +`define MmuPlugin_shared_State_defaultEncoding_L0_RSP 3'b100 + + +module VexRiscv ( + output dBus_cmd_valid, + input dBus_cmd_ready, + output dBus_cmd_payload_wr, + output dBus_cmd_payload_uncached, + output [31:0] dBus_cmd_payload_address, + output [31:0] dBus_cmd_payload_data, + output [3:0] dBus_cmd_payload_mask, + output [2:0] dBus_cmd_payload_size, + output dBus_cmd_payload_last, + input dBus_rsp_valid, + input dBus_rsp_payload_last, + input [31:0] dBus_rsp_payload_data, + input dBus_rsp_payload_error, + input timerInterrupt, + input externalInterrupt, + input softwareInterrupt, + input externalInterruptS, + input debug_bus_cmd_valid, + output reg debug_bus_cmd_ready, + input debug_bus_cmd_payload_wr, + input [7:0] debug_bus_cmd_payload_address, + input [31:0] debug_bus_cmd_payload_data, + output reg [31:0] debug_bus_rsp_data, + output debug_resetOut, + output iBus_cmd_valid, + input iBus_cmd_ready, + output reg [31:0] iBus_cmd_payload_address, + output [2:0] iBus_cmd_payload_size, + input iBus_rsp_valid, + input [31:0] iBus_rsp_payload_data, + input iBus_rsp_payload_error, + input clk, + input reset, + input debugReset +); + wire IBusCachedPlugin_cache_io_flush; + wire IBusCachedPlugin_cache_io_cpu_prefetch_isValid; + wire IBusCachedPlugin_cache_io_cpu_fetch_isValid; + wire IBusCachedPlugin_cache_io_cpu_fetch_isStuck; + wire IBusCachedPlugin_cache_io_cpu_fetch_isRemoved; + wire IBusCachedPlugin_cache_io_cpu_decode_isValid; + wire IBusCachedPlugin_cache_io_cpu_decode_isStuck; + wire IBusCachedPlugin_cache_io_cpu_decode_isUser; + reg IBusCachedPlugin_cache_io_cpu_fill_valid; + reg dataCache_1_io_cpu_execute_isValid; + reg [31:0] dataCache_1_io_cpu_execute_address; + reg dataCache_1_io_cpu_execute_args_wr; + reg [1:0] dataCache_1_io_cpu_execute_args_size; + reg dataCache_1_io_cpu_execute_args_isLrsc; + wire dataCache_1_io_cpu_execute_args_amoCtrl_swap; + wire [2:0] dataCache_1_io_cpu_execute_args_amoCtrl_alu; + reg dataCache_1_io_cpu_memory_isValid; + wire [31:0] dataCache_1_io_cpu_memory_address; + reg dataCache_1_io_cpu_memory_mmuRsp_isIoAccess; + reg dataCache_1_io_cpu_writeBack_isValid; + wire dataCache_1_io_cpu_writeBack_isUser; + wire [31:0] dataCache_1_io_cpu_writeBack_storeData; + wire [31:0] dataCache_1_io_cpu_writeBack_address; + wire dataCache_1_io_cpu_writeBack_fence_SW; + wire dataCache_1_io_cpu_writeBack_fence_SR; + wire dataCache_1_io_cpu_writeBack_fence_SO; + wire dataCache_1_io_cpu_writeBack_fence_SI; + wire dataCache_1_io_cpu_writeBack_fence_PW; + wire dataCache_1_io_cpu_writeBack_fence_PR; + wire dataCache_1_io_cpu_writeBack_fence_PO; + wire dataCache_1_io_cpu_writeBack_fence_PI; + wire [3:0] dataCache_1_io_cpu_writeBack_fence_FM; + wire dataCache_1_io_cpu_flush_valid; + wire dataCache_1_io_mem_cmd_ready; + reg [31:0] _zz_RegFilePlugin_regFile_port0; + reg [31:0] _zz_RegFilePlugin_regFile_port1; + wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; + wire IBusCachedPlugin_cache_io_cpu_decode_error; + wire IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling; + wire IBusCachedPlugin_cache_io_cpu_decode_mmuException; + wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_data; + wire IBusCachedPlugin_cache_io_cpu_decode_cacheMiss; + wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_physicalAddress; + wire IBusCachedPlugin_cache_io_mem_cmd_valid; + wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address; + wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size; + wire dataCache_1_io_cpu_execute_haltIt; + wire dataCache_1_io_cpu_execute_refilling; + wire dataCache_1_io_cpu_memory_isWrite; + wire dataCache_1_io_cpu_writeBack_haltIt; + wire [31:0] dataCache_1_io_cpu_writeBack_data; + wire dataCache_1_io_cpu_writeBack_mmuException; + wire dataCache_1_io_cpu_writeBack_unalignedAccess; + wire dataCache_1_io_cpu_writeBack_accessError; + wire dataCache_1_io_cpu_writeBack_isWrite; + wire dataCache_1_io_cpu_writeBack_keepMemRspData; + wire dataCache_1_io_cpu_writeBack_exclusiveOk; + wire dataCache_1_io_cpu_flush_ready; + wire dataCache_1_io_cpu_redo; + wire dataCache_1_io_mem_cmd_valid; + wire dataCache_1_io_mem_cmd_payload_wr; + wire dataCache_1_io_mem_cmd_payload_uncached; + wire [31:0] dataCache_1_io_mem_cmd_payload_address; + wire [31:0] dataCache_1_io_mem_cmd_payload_data; + wire [3:0] dataCache_1_io_mem_cmd_payload_mask; + wire [2:0] dataCache_1_io_mem_cmd_payload_size; + wire dataCache_1_io_mem_cmd_payload_last; + wire [51:0] _zz_memory_MUL_LOW; + wire [51:0] _zz_memory_MUL_LOW_1; + wire [51:0] _zz_memory_MUL_LOW_2; + wire [51:0] _zz_memory_MUL_LOW_3; + wire [32:0] _zz_memory_MUL_LOW_4; + wire [51:0] _zz_memory_MUL_LOW_5; + wire [49:0] _zz_memory_MUL_LOW_6; + wire [51:0] _zz_memory_MUL_LOW_7; + wire [49:0] _zz_memory_MUL_LOW_8; + wire [31:0] _zz_execute_SHIFT_RIGHT; + wire [32:0] _zz_execute_SHIFT_RIGHT_1; + wire [32:0] _zz_execute_SHIFT_RIGHT_2; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_1; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_2; + wire _zz_decode_LEGAL_INSTRUCTION_3; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_4; + wire [17:0] _zz_decode_LEGAL_INSTRUCTION_5; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_6; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_7; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_8; + wire _zz_decode_LEGAL_INSTRUCTION_9; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_10; + wire [11:0] _zz_decode_LEGAL_INSTRUCTION_11; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_12; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_13; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_14; + wire _zz_decode_LEGAL_INSTRUCTION_15; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_16; + wire [5:0] _zz_decode_LEGAL_INSTRUCTION_17; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_18; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_19; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_20; + wire _zz_decode_LEGAL_INSTRUCTION_21; + wire _zz_decode_LEGAL_INSTRUCTION_22; + wire [4:0] _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1; + reg [31:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_6; + wire [2:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_7; + wire [31:0] _zz_IBusCachedPlugin_fetchPc_pc; + wire [2:0] _zz_IBusCachedPlugin_fetchPc_pc_1; + wire [11:0] _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + wire [31:0] _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2; + wire [19:0] _zz__zz_2; + wire [11:0] _zz__zz_4; + wire [31:0] _zz__zz_6; + wire [31:0] _zz__zz_6_1; + wire [19:0] _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload; + wire [11:0] _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_4; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_5; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_6; + wire [2:0] _zz_DBusCachedPlugin_exceptionBus_payload_code; + wire [2:0] _zz_DBusCachedPlugin_exceptionBus_payload_code_1; + reg [7:0] _zz_writeBack_DBusCachedPlugin_rspShifted; + wire [1:0] _zz_writeBack_DBusCachedPlugin_rspShifted_1; + reg [7:0] _zz_writeBack_DBusCachedPlugin_rspShifted_2; + wire [0:0] _zz_writeBack_DBusCachedPlugin_rspShifted_3; + wire [0:0] _zz_writeBack_DBusCachedPlugin_rspRf; + wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2; + wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_1; + wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_2; + wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_3; + wire _zz__zz_decode_IS_SFENCE_VMA2_4; + wire [0:0] _zz__zz_decode_IS_SFENCE_VMA2_5; + wire [0:0] _zz__zz_decode_IS_SFENCE_VMA2_6; + wire _zz__zz_decode_IS_SFENCE_VMA2_7; + wire [0:0] _zz__zz_decode_IS_SFENCE_VMA2_8; + wire _zz__zz_decode_IS_SFENCE_VMA2_9; + wire _zz__zz_decode_IS_SFENCE_VMA2_10; + wire [30:0] _zz__zz_decode_IS_SFENCE_VMA2_11; + wire _zz__zz_decode_IS_SFENCE_VMA2_12; + wire [1:0] _zz__zz_decode_IS_SFENCE_VMA2_13; + wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_14; + wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_15; + wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_16; + wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_17; + wire [1:0] _zz__zz_decode_IS_SFENCE_VMA2_18; + wire _zz__zz_decode_IS_SFENCE_VMA2_19; + wire [0:0] _zz__zz_decode_IS_SFENCE_VMA2_20; + wire [26:0] _zz__zz_decode_IS_SFENCE_VMA2_21; + wire [0:0] _zz__zz_decode_IS_SFENCE_VMA2_22; + wire [0:0] _zz__zz_decode_IS_SFENCE_VMA2_23; + wire _zz__zz_decode_IS_SFENCE_VMA2_24; + wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_25; + wire [0:0] _zz__zz_decode_IS_SFENCE_VMA2_26; + wire _zz__zz_decode_IS_SFENCE_VMA2_27; + wire _zz__zz_decode_IS_SFENCE_VMA2_28; + wire [23:0] _zz__zz_decode_IS_SFENCE_VMA2_29; + wire [0:0] _zz__zz_decode_IS_SFENCE_VMA2_30; + wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_31; + wire [1:0] _zz__zz_decode_IS_SFENCE_VMA2_32; + wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_33; + wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_34; + wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_35; + wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_36; + wire [0:0] _zz__zz_decode_IS_SFENCE_VMA2_37; + wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_38; + wire [0:0] _zz__zz_decode_IS_SFENCE_VMA2_39; + wire _zz__zz_decode_IS_SFENCE_VMA2_40; + wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_41; + wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_42; + wire [0:0] _zz__zz_decode_IS_SFENCE_VMA2_43; + wire [0:0] _zz__zz_decode_IS_SFENCE_VMA2_44; + wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_45; + wire [0:0] _zz__zz_decode_IS_SFENCE_VMA2_46; + wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_47; + wire [19:0] _zz__zz_decode_IS_SFENCE_VMA2_48; + wire [0:0] _zz__zz_decode_IS_SFENCE_VMA2_49; + wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_50; + wire [0:0] _zz__zz_decode_IS_SFENCE_VMA2_51; + wire _zz__zz_decode_IS_SFENCE_VMA2_52; + wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_53; + wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_54; + wire [0:0] _zz__zz_decode_IS_SFENCE_VMA2_55; + wire [0:0] _zz__zz_decode_IS_SFENCE_VMA2_56; + wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_57; + wire [2:0] _zz__zz_decode_IS_SFENCE_VMA2_58; + wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_59; + wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_60; + wire _zz__zz_decode_IS_SFENCE_VMA2_61; + wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_62; + wire _zz__zz_decode_IS_SFENCE_VMA2_63; + wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_64; + wire [16:0] _zz__zz_decode_IS_SFENCE_VMA2_65; + wire [0:0] _zz__zz_decode_IS_SFENCE_VMA2_66; + wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_67; + wire [0:0] _zz__zz_decode_IS_SFENCE_VMA2_68; + wire _zz__zz_decode_IS_SFENCE_VMA2_69; + wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_70; + wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_71; + wire [0:0] _zz__zz_decode_IS_SFENCE_VMA2_72; + wire [0:0] _zz__zz_decode_IS_SFENCE_VMA2_73; + wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_74; + wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_75; + wire [4:0] _zz__zz_decode_IS_SFENCE_VMA2_76; + wire _zz__zz_decode_IS_SFENCE_VMA2_77; + wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_78; + wire [0:0] _zz__zz_decode_IS_SFENCE_VMA2_79; + wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_80; + wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_81; + wire [2:0] _zz__zz_decode_IS_SFENCE_VMA2_82; + wire _zz__zz_decode_IS_SFENCE_VMA2_83; + wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_84; + wire [0:0] _zz__zz_decode_IS_SFENCE_VMA2_85; + wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_86; + wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_87; + wire [0:0] _zz__zz_decode_IS_SFENCE_VMA2_88; + wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_89; + wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_90; + wire [13:0] _zz__zz_decode_IS_SFENCE_VMA2_91; + wire [2:0] _zz__zz_decode_IS_SFENCE_VMA2_92; + wire _zz__zz_decode_IS_SFENCE_VMA2_93; + wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_94; + wire [0:0] _zz__zz_decode_IS_SFENCE_VMA2_95; + wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_96; + wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_97; + wire [0:0] _zz__zz_decode_IS_SFENCE_VMA2_98; + wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_99; + wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_100; + wire [2:0] _zz__zz_decode_IS_SFENCE_VMA2_101; + wire _zz__zz_decode_IS_SFENCE_VMA2_102; + wire [0:0] _zz__zz_decode_IS_SFENCE_VMA2_103; + wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_104; + wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_105; + wire [3:0] _zz__zz_decode_IS_SFENCE_VMA2_106; + wire _zz__zz_decode_IS_SFENCE_VMA2_107; + wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_108; + wire [0:0] _zz__zz_decode_IS_SFENCE_VMA2_109; + wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_110; + wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_111; + wire [1:0] _zz__zz_decode_IS_SFENCE_VMA2_112; + wire _zz__zz_decode_IS_SFENCE_VMA2_113; + wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_114; + wire [0:0] _zz__zz_decode_IS_SFENCE_VMA2_115; + wire [4:0] _zz__zz_decode_IS_SFENCE_VMA2_116; + wire [0:0] _zz__zz_decode_IS_SFENCE_VMA2_117; + wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_118; + wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_119; + wire [2:0] _zz__zz_decode_IS_SFENCE_VMA2_120; + wire _zz__zz_decode_IS_SFENCE_VMA2_121; + wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_122; + wire [0:0] _zz__zz_decode_IS_SFENCE_VMA2_123; + wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_124; + wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_125; + wire [0:0] _zz__zz_decode_IS_SFENCE_VMA2_126; + wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_127; + wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_128; + wire [4:0] _zz__zz_decode_IS_SFENCE_VMA2_129; + wire [10:0] _zz__zz_decode_IS_SFENCE_VMA2_130; + wire _zz__zz_decode_IS_SFENCE_VMA2_131; + wire [0:0] _zz__zz_decode_IS_SFENCE_VMA2_132; + wire [5:0] _zz__zz_decode_IS_SFENCE_VMA2_133; + wire _zz__zz_decode_IS_SFENCE_VMA2_134; + wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_135; + wire [0:0] _zz__zz_decode_IS_SFENCE_VMA2_136; + wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_137; + wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_138; + wire [3:0] _zz__zz_decode_IS_SFENCE_VMA2_139; + wire _zz__zz_decode_IS_SFENCE_VMA2_140; + wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_141; + wire [0:0] _zz__zz_decode_IS_SFENCE_VMA2_142; + wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_143; + wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_144; + wire [1:0] _zz__zz_decode_IS_SFENCE_VMA2_145; + wire _zz__zz_decode_IS_SFENCE_VMA2_146; + wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_147; + wire [0:0] _zz__zz_decode_IS_SFENCE_VMA2_148; + wire [1:0] _zz__zz_decode_IS_SFENCE_VMA2_149; + wire _zz__zz_decode_IS_SFENCE_VMA2_150; + wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_151; + wire [1:0] _zz__zz_decode_IS_SFENCE_VMA2_152; + wire [8:0] _zz__zz_decode_IS_SFENCE_VMA2_153; + wire _zz__zz_decode_IS_SFENCE_VMA2_154; + wire [0:0] _zz__zz_decode_IS_SFENCE_VMA2_155; + wire [0:0] _zz__zz_decode_IS_SFENCE_VMA2_156; + wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_157; + wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_158; + wire [0:0] _zz__zz_decode_IS_SFENCE_VMA2_159; + wire [0:0] _zz__zz_decode_IS_SFENCE_VMA2_160; + wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_161; + wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_162; + wire [0:0] _zz__zz_decode_IS_SFENCE_VMA2_163; + wire [6:0] _zz__zz_decode_IS_SFENCE_VMA2_164; + wire _zz__zz_decode_IS_SFENCE_VMA2_165; + wire _zz__zz_decode_IS_SFENCE_VMA2_166; + wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_167; + wire [0:0] _zz__zz_decode_IS_SFENCE_VMA2_168; + wire [4:0] _zz__zz_decode_IS_SFENCE_VMA2_169; + wire _zz__zz_decode_IS_SFENCE_VMA2_170; + wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_171; + wire [0:0] _zz__zz_decode_IS_SFENCE_VMA2_172; + wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_173; + wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_174; + wire [2:0] _zz__zz_decode_IS_SFENCE_VMA2_175; + wire _zz__zz_decode_IS_SFENCE_VMA2_176; + wire [0:0] _zz__zz_decode_IS_SFENCE_VMA2_177; + wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_178; + wire [0:0] _zz__zz_decode_IS_SFENCE_VMA2_179; + wire [4:0] _zz__zz_decode_IS_SFENCE_VMA2_180; + wire [4:0] _zz__zz_decode_IS_SFENCE_VMA2_181; + wire _zz__zz_decode_IS_SFENCE_VMA2_182; + wire [0:0] _zz__zz_decode_IS_SFENCE_VMA2_183; + wire [0:0] _zz__zz_decode_IS_SFENCE_VMA2_184; + wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_185; + wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_186; + wire [0:0] _zz__zz_decode_IS_SFENCE_VMA2_187; + wire [2:0] _zz__zz_decode_IS_SFENCE_VMA2_188; + wire _zz__zz_decode_IS_SFENCE_VMA2_189; + wire [0:0] _zz__zz_decode_IS_SFENCE_VMA2_190; + wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_191; + wire [0:0] _zz__zz_decode_IS_SFENCE_VMA2_192; + wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_193; + wire [2:0] _zz__zz_decode_IS_SFENCE_VMA2_194; + wire [2:0] _zz__zz_decode_IS_SFENCE_VMA2_195; + wire _zz__zz_decode_IS_SFENCE_VMA2_196; + wire [0:0] _zz__zz_decode_IS_SFENCE_VMA2_197; + wire [1:0] _zz__zz_decode_IS_SFENCE_VMA2_198; + wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_199; + wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_200; + wire [0:0] _zz__zz_decode_IS_SFENCE_VMA2_201; + wire [1:0] _zz__zz_decode_IS_SFENCE_VMA2_202; + wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_203; + wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_204; + wire [1:0] _zz__zz_decode_IS_SFENCE_VMA2_205; + wire [0:0] _zz__zz_decode_IS_SFENCE_VMA2_206; + wire [0:0] _zz__zz_decode_IS_SFENCE_VMA2_207; + wire [31:0] _zz__zz_decode_IS_SFENCE_VMA2_208; + wire [0:0] _zz__zz_decode_IS_SFENCE_VMA2_209; + wire _zz_RegFilePlugin_regFile_port; + wire _zz_decode_RegFilePlugin_rs1Data; + wire _zz_RegFilePlugin_regFile_port_1; + wire _zz_decode_RegFilePlugin_rs2Data; + wire [0:0] _zz__zz_execute_REGFILE_WRITE_DATA; + wire [2:0] _zz__zz_decode_SRC1_1; + wire [4:0] _zz__zz_decode_SRC1_1_1; + wire [11:0] _zz__zz_decode_SRC2_4; + wire [31:0] _zz_execute_SrcPlugin_addSub; + wire [31:0] _zz_execute_SrcPlugin_addSub_1; + wire [31:0] _zz_execute_SrcPlugin_addSub_2; + wire [31:0] _zz_execute_SrcPlugin_addSub_3; + wire [31:0] _zz_execute_SrcPlugin_addSub_4; + wire [31:0] _zz_execute_SrcPlugin_addSub_5; + wire [31:0] _zz_execute_SrcPlugin_addSub_6; + wire [65:0] _zz_writeBack_MulPlugin_result; + wire [65:0] _zz_writeBack_MulPlugin_result_1; + wire [31:0] _zz__zz_decode_RS2_2; + wire [31:0] _zz__zz_decode_RS2_2_1; + wire [5:0] _zz_memory_MulDivIterativePlugin_div_counter_valueNext; + wire [0:0] _zz_memory_MulDivIterativePlugin_div_counter_valueNext_1; + wire [32:0] _zz_memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator; + wire [31:0] _zz_memory_MulDivIterativePlugin_div_stage_0_outRemainder; + wire [31:0] _zz_memory_MulDivIterativePlugin_div_stage_0_outRemainder_1; + wire [32:0] _zz_memory_MulDivIterativePlugin_div_stage_0_outNumerator; + wire [32:0] _zz_memory_MulDivIterativePlugin_div_result_1; + wire [32:0] _zz_memory_MulDivIterativePlugin_div_result_2; + wire [32:0] _zz_memory_MulDivIterativePlugin_div_result_3; + wire [32:0] _zz_memory_MulDivIterativePlugin_div_result_4; + wire [0:0] _zz_memory_MulDivIterativePlugin_div_result_5; + wire [32:0] _zz_memory_MulDivIterativePlugin_rs1_2; + wire [0:0] _zz_memory_MulDivIterativePlugin_rs1_3; + wire [31:0] _zz_memory_MulDivIterativePlugin_rs2_1; + wire [0:0] _zz_memory_MulDivIterativePlugin_rs2_2; + wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1; + wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1; + wire _zz_when; + wire [19:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_2; + wire [11:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_4; + wire [31:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_6; + wire [31:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_6_1; + wire [31:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_6_2; + wire [19:0] _zz__zz_execute_BranchPlugin_branch_src2_2; + wire [11:0] _zz__zz_execute_BranchPlugin_branch_src2_4; + wire _zz_execute_BranchPlugin_branch_src2_6; + wire _zz_execute_BranchPlugin_branch_src2_7; + wire _zz_execute_BranchPlugin_branch_src2_8; + wire [2:0] _zz_execute_BranchPlugin_branch_src2_9; + wire [9:0] _zz_MmuPlugin_ports_0_cacheHitsCalc; + wire [9:0] _zz_MmuPlugin_ports_0_cacheHitsCalc_1; + wire _zz_MmuPlugin_ports_0_cacheHitsCalc_2; + wire _zz_MmuPlugin_ports_0_cacheHitsCalc_3; + wire _zz_MmuPlugin_ports_0_cacheHitsCalc_4; + wire _zz_MmuPlugin_ports_0_cacheHitsCalc_5; + reg _zz_MmuPlugin_ports_0_cacheLine_valid_4; + reg _zz_MmuPlugin_ports_0_cacheLine_exception; + reg _zz_MmuPlugin_ports_0_cacheLine_superPage; + reg [9:0] _zz_MmuPlugin_ports_0_cacheLine_virtualAddress_0; + reg [9:0] _zz_MmuPlugin_ports_0_cacheLine_virtualAddress_1; + reg [9:0] _zz_MmuPlugin_ports_0_cacheLine_physicalAddress_0; + reg [9:0] _zz_MmuPlugin_ports_0_cacheLine_physicalAddress_1; + reg _zz_MmuPlugin_ports_0_cacheLine_allowRead; + reg _zz_MmuPlugin_ports_0_cacheLine_allowWrite; + reg _zz_MmuPlugin_ports_0_cacheLine_allowExecute; + reg _zz_MmuPlugin_ports_0_cacheLine_allowUser; + wire [1:0] _zz_MmuPlugin_ports_0_entryToReplace_valueNext; + wire [0:0] _zz_MmuPlugin_ports_0_entryToReplace_valueNext_1; + wire [9:0] _zz_MmuPlugin_ports_1_cacheHitsCalc; + wire [9:0] _zz_MmuPlugin_ports_1_cacheHitsCalc_1; + wire _zz_MmuPlugin_ports_1_cacheHitsCalc_2; + wire _zz_MmuPlugin_ports_1_cacheHitsCalc_3; + wire _zz_MmuPlugin_ports_1_cacheHitsCalc_4; + wire _zz_MmuPlugin_ports_1_cacheHitsCalc_5; + reg _zz_MmuPlugin_ports_1_cacheLine_valid_4; + reg _zz_MmuPlugin_ports_1_cacheLine_exception; + reg _zz_MmuPlugin_ports_1_cacheLine_superPage; + reg [9:0] _zz_MmuPlugin_ports_1_cacheLine_virtualAddress_0; + reg [9:0] _zz_MmuPlugin_ports_1_cacheLine_virtualAddress_1; + reg [9:0] _zz_MmuPlugin_ports_1_cacheLine_physicalAddress_0; + reg [9:0] _zz_MmuPlugin_ports_1_cacheLine_physicalAddress_1; + reg _zz_MmuPlugin_ports_1_cacheLine_allowRead; + reg _zz_MmuPlugin_ports_1_cacheLine_allowWrite; + reg _zz_MmuPlugin_ports_1_cacheLine_allowExecute; + reg _zz_MmuPlugin_ports_1_cacheLine_allowUser; + wire [1:0] _zz_MmuPlugin_ports_1_entryToReplace_valueNext; + wire [0:0] _zz_MmuPlugin_ports_1_entryToReplace_valueNext_1; + wire [1:0] _zz__zz_MmuPlugin_shared_refills_2; + wire [31:0] _zz_CsrPlugin_csrMapping_readDataInit_19; + wire [51:0] memory_MUL_LOW; + wire [31:0] execute_BRANCH_CALC; + wire execute_BRANCH_DO; + wire [33:0] memory_MUL_HH; + wire [33:0] execute_MUL_HH; + wire [33:0] execute_MUL_HL; + wire [33:0] execute_MUL_LH; + wire [31:0] execute_MUL_LL; + wire [31:0] execute_SHIFT_RIGHT; + wire [31:0] execute_REGFILE_WRITE_DATA; + wire execute_IS_DBUS_SHARING; + wire [31:0] memory_MEMORY_STORE_DATA_RF; + wire [31:0] execute_MEMORY_STORE_DATA_RF; + wire decode_PREDICTION_HAD_BRANCHED2; + wire decode_DO_EBREAK; + wire decode_CSR_READ_OPCODE; + wire decode_CSR_WRITE_OPCODE; + wire [31:0] decode_SRC2; + wire [31:0] decode_SRC1; + wire decode_SRC2_FORCE_ZERO; + wire `BranchCtrlEnum_defaultEncoding_type _zz_decode_to_execute_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_decode_to_execute_BRANCH_CTRL_1; + wire decode_IS_SFENCE_VMA2; + wire decode_IS_SFENCE_VMA; + wire `EnvCtrlEnum_defaultEncoding_type _zz_memory_to_writeBack_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_memory_to_writeBack_ENV_CTRL_1; + wire `EnvCtrlEnum_defaultEncoding_type _zz_execute_to_memory_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_execute_to_memory_ENV_CTRL_1; + wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_decode_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_decode_to_execute_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_decode_to_execute_ENV_CTRL_1; + wire decode_IS_CSR; + wire decode_IS_RS2_SIGNED; + wire decode_IS_RS1_SIGNED; + wire decode_IS_DIV; + wire memory_IS_MUL; + wire execute_IS_MUL; + wire decode_IS_MUL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_execute_to_memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_execute_to_memory_SHIFT_CTRL_1; + wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_decode_to_execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_decode_to_execute_SHIFT_CTRL_1; + wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_decode_to_execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_decode_to_execute_ALU_BITWISE_CTRL_1; + wire decode_SRC_LESS_UNSIGNED; + wire decode_MEMORY_MANAGMENT; + wire memory_MEMORY_LRSC; + wire memory_MEMORY_WR; + wire decode_MEMORY_WR; + wire execute_BYPASSABLE_MEMORY_STAGE; + wire decode_BYPASSABLE_MEMORY_STAGE; + wire decode_BYPASSABLE_EXECUTE_STAGE; + wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_decode_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_decode_to_execute_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_decode_to_execute_ALU_CTRL_1; + wire decode_MEMORY_FORCE_CONSTISTENCY; + wire [31:0] writeBack_FORMAL_PC_NEXT; + wire [31:0] memory_FORMAL_PC_NEXT; + wire [31:0] execute_FORMAL_PC_NEXT; + wire [31:0] decode_FORMAL_PC_NEXT; + wire [31:0] memory_PC; + wire execute_IS_SFENCE_VMA2; + wire [31:0] memory_BRANCH_CALC; + wire memory_BRANCH_DO; + wire execute_PREDICTION_HAD_BRANCHED2; + wire execute_BRANCH_COND_RESULT; + wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_execute_BRANCH_CTRL; + wire [31:0] execute_PC; + wire execute_DO_EBREAK; + wire decode_IS_EBREAK; + wire execute_CSR_READ_OPCODE; + wire execute_CSR_WRITE_OPCODE; + wire execute_IS_CSR; + wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_memory_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_execute_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_writeBack_ENV_CTRL; + wire execute_IS_SFENCE_VMA; + wire execute_IS_RS1_SIGNED; + wire execute_IS_DIV; + wire execute_IS_RS2_SIGNED; + wire memory_IS_DIV; + wire writeBack_IS_MUL; + wire [33:0] writeBack_MUL_HH; + wire [51:0] writeBack_MUL_LOW; + wire [33:0] memory_MUL_HL; + wire [33:0] memory_MUL_LH; + wire [31:0] memory_MUL_LL; + (* keep , syn_keep *) wire [31:0] execute_RS1 /* synthesis syn_keep = 1 */ ; + wire decode_RS2_USE; + wire decode_RS1_USE; + reg [31:0] _zz_decode_RS2; + wire execute_REGFILE_WRITE_VALID; + wire execute_BYPASSABLE_EXECUTE_STAGE; + wire memory_REGFILE_WRITE_VALID; + wire [31:0] memory_INSTRUCTION; + wire memory_BYPASSABLE_MEMORY_STAGE; + wire writeBack_REGFILE_WRITE_VALID; + reg [31:0] decode_RS2; + reg [31:0] decode_RS1; + wire [31:0] memory_SHIFT_RIGHT; + reg [31:0] _zz_decode_RS2_1; + wire `ShiftCtrlEnum_defaultEncoding_type memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_execute_SHIFT_CTRL; + wire execute_SRC_LESS_UNSIGNED; + wire execute_SRC2_FORCE_ZERO; + wire execute_SRC_USE_SUB_LESS; + wire [31:0] _zz_decode_SRC2; + wire [31:0] _zz_decode_SRC2_1; + wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; + wire `Src2CtrlEnum_defaultEncoding_type _zz_decode_SRC2_CTRL; + wire [31:0] _zz_decode_SRC1; + wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; + wire `Src1CtrlEnum_defaultEncoding_type _zz_decode_SRC1_CTRL; + wire decode_SRC_USE_SUB_LESS; + wire decode_SRC_ADD_ZERO; + wire [31:0] execute_SRC_ADD_SUB; + wire execute_SRC_LESS; + wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_execute_ALU_CTRL; + wire [31:0] execute_SRC2; + wire [31:0] execute_SRC1; + wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_execute_ALU_BITWISE_CTRL; + wire [31:0] _zz_lastStageRegFileWrite_payload_address; + wire _zz_lastStageRegFileWrite_valid; + reg _zz_1; + wire [31:0] decode_INSTRUCTION_ANTICIPATED; + reg decode_REGFILE_WRITE_VALID; + wire decode_LEGAL_INSTRUCTION; + wire `BranchCtrlEnum_defaultEncoding_type _zz_decode_BRANCH_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_decode_ENV_CTRL_1; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_decode_SHIFT_CTRL_1; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_decode_ALU_BITWISE_CTRL_1; + wire `Src2CtrlEnum_defaultEncoding_type _zz_decode_SRC2_CTRL_1; + wire `AluCtrlEnum_defaultEncoding_type _zz_decode_ALU_CTRL_1; + wire `Src1CtrlEnum_defaultEncoding_type _zz_decode_SRC1_CTRL_1; + wire writeBack_IS_DBUS_SHARING; + wire memory_IS_DBUS_SHARING; + reg [31:0] _zz_decode_RS2_2; + wire writeBack_MEMORY_LRSC; + wire writeBack_MEMORY_WR; + wire [31:0] writeBack_MEMORY_STORE_DATA_RF; + wire [31:0] writeBack_REGFILE_WRITE_DATA; + wire writeBack_MEMORY_ENABLE; + wire [31:0] memory_REGFILE_WRITE_DATA; + wire memory_MEMORY_ENABLE; + reg execute_MEMORY_AMO; + reg execute_MEMORY_LRSC; + wire execute_MEMORY_FORCE_CONSTISTENCY; + wire execute_MEMORY_MANAGMENT; + (* keep , syn_keep *) wire [31:0] execute_RS2 /* synthesis syn_keep = 1 */ ; + wire execute_MEMORY_WR; + wire [31:0] execute_SRC_ADD; + wire execute_MEMORY_ENABLE; + wire [31:0] execute_INSTRUCTION; + wire decode_MEMORY_AMO; + wire decode_MEMORY_LRSC; + reg _zz_decode_MEMORY_FORCE_CONSTISTENCY; + wire decode_MEMORY_ENABLE; + wire decode_FLUSH_ALL; + reg IBusCachedPlugin_rsp_issueDetected_4; + reg IBusCachedPlugin_rsp_issueDetected_3; + reg IBusCachedPlugin_rsp_issueDetected_2; + reg IBusCachedPlugin_rsp_issueDetected_1; + wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_decode_BRANCH_CTRL_1; + wire [31:0] decode_INSTRUCTION; + reg [31:0] _zz_memory_to_writeBack_FORMAL_PC_NEXT; + reg [31:0] _zz_execute_to_memory_FORMAL_PC_NEXT; + reg [31:0] _zz_decode_to_execute_FORMAL_PC_NEXT; + wire [31:0] decode_PC; + wire [31:0] writeBack_PC; + wire [31:0] writeBack_INSTRUCTION; + reg decode_arbitration_haltItself; + reg decode_arbitration_haltByOther; + reg decode_arbitration_removeIt; + wire decode_arbitration_flushIt; + reg decode_arbitration_flushNext; + reg decode_arbitration_isValid; + wire decode_arbitration_isStuck; + wire decode_arbitration_isStuckByOthers; + wire decode_arbitration_isFlushed; + wire decode_arbitration_isMoving; + wire decode_arbitration_isFiring; + reg execute_arbitration_haltItself; + reg execute_arbitration_haltByOther; + reg execute_arbitration_removeIt; + reg execute_arbitration_flushIt; + reg execute_arbitration_flushNext; + reg execute_arbitration_isValid; + wire execute_arbitration_isStuck; + wire execute_arbitration_isStuckByOthers; + wire execute_arbitration_isFlushed; + wire execute_arbitration_isMoving; + wire execute_arbitration_isFiring; + reg memory_arbitration_haltItself; + wire memory_arbitration_haltByOther; + reg memory_arbitration_removeIt; + wire memory_arbitration_flushIt; + reg memory_arbitration_flushNext; + reg memory_arbitration_isValid; + wire memory_arbitration_isStuck; + wire memory_arbitration_isStuckByOthers; + wire memory_arbitration_isFlushed; + wire memory_arbitration_isMoving; + wire memory_arbitration_isFiring; + reg writeBack_arbitration_haltItself; + wire writeBack_arbitration_haltByOther; + reg writeBack_arbitration_removeIt; + reg writeBack_arbitration_flushIt; + reg writeBack_arbitration_flushNext; + reg writeBack_arbitration_isValid; + wire writeBack_arbitration_isStuck; + wire writeBack_arbitration_isStuckByOthers; + wire writeBack_arbitration_isFlushed; + wire writeBack_arbitration_isMoving; + wire writeBack_arbitration_isFiring; + wire [31:0] lastStageInstruction /* verilator public */ ; + wire [31:0] lastStagePc /* verilator public */ ; + wire lastStageIsValid /* verilator public */ ; + wire lastStageIsFiring /* verilator public */ ; + reg IBusCachedPlugin_fetcherHalt; + reg IBusCachedPlugin_incomingInstruction; + wire IBusCachedPlugin_predictionJumpInterface_valid; + (* keep , syn_keep *) wire [31:0] IBusCachedPlugin_predictionJumpInterface_payload /* synthesis syn_keep = 1 */ ; + reg IBusCachedPlugin_decodePrediction_cmd_hadBranch; + wire IBusCachedPlugin_decodePrediction_rsp_wasWrong; + wire IBusCachedPlugin_pcValids_0; + wire IBusCachedPlugin_pcValids_1; + wire IBusCachedPlugin_pcValids_2; + wire IBusCachedPlugin_pcValids_3; + reg IBusCachedPlugin_decodeExceptionPort_valid; + reg [3:0] IBusCachedPlugin_decodeExceptionPort_payload_code; + wire [31:0] IBusCachedPlugin_decodeExceptionPort_payload_badAddr; + wire IBusCachedPlugin_mmuBus_cmd_0_isValid; + wire IBusCachedPlugin_mmuBus_cmd_0_isStuck; + wire [31:0] IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + wire IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation; + reg [31:0] IBusCachedPlugin_mmuBus_rsp_physicalAddress; + wire IBusCachedPlugin_mmuBus_rsp_isIoAccess; + reg IBusCachedPlugin_mmuBus_rsp_isPaging; + reg IBusCachedPlugin_mmuBus_rsp_allowRead; + reg IBusCachedPlugin_mmuBus_rsp_allowWrite; + reg IBusCachedPlugin_mmuBus_rsp_allowExecute; + reg IBusCachedPlugin_mmuBus_rsp_exception; + reg IBusCachedPlugin_mmuBus_rsp_refilling; + wire IBusCachedPlugin_mmuBus_rsp_bypassTranslation; + wire IBusCachedPlugin_mmuBus_rsp_ways_0_sel; + wire [31:0] IBusCachedPlugin_mmuBus_rsp_ways_0_physical; + wire IBusCachedPlugin_mmuBus_rsp_ways_1_sel; + wire [31:0] IBusCachedPlugin_mmuBus_rsp_ways_1_physical; + wire IBusCachedPlugin_mmuBus_rsp_ways_2_sel; + wire [31:0] IBusCachedPlugin_mmuBus_rsp_ways_2_physical; + wire IBusCachedPlugin_mmuBus_rsp_ways_3_sel; + wire [31:0] IBusCachedPlugin_mmuBus_rsp_ways_3_physical; + wire IBusCachedPlugin_mmuBus_end; + wire IBusCachedPlugin_mmuBus_busy; + wire DBusCachedPlugin_mmuBus_cmd_0_isValid; + wire DBusCachedPlugin_mmuBus_cmd_0_isStuck; + wire [31:0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + reg DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation; + reg [31:0] DBusCachedPlugin_mmuBus_rsp_physicalAddress; + wire DBusCachedPlugin_mmuBus_rsp_isIoAccess; + reg DBusCachedPlugin_mmuBus_rsp_isPaging; + reg DBusCachedPlugin_mmuBus_rsp_allowRead; + reg DBusCachedPlugin_mmuBus_rsp_allowWrite; + reg DBusCachedPlugin_mmuBus_rsp_allowExecute; + reg DBusCachedPlugin_mmuBus_rsp_exception; + reg DBusCachedPlugin_mmuBus_rsp_refilling; + wire DBusCachedPlugin_mmuBus_rsp_bypassTranslation; + wire DBusCachedPlugin_mmuBus_rsp_ways_0_sel; + wire [31:0] DBusCachedPlugin_mmuBus_rsp_ways_0_physical; + wire DBusCachedPlugin_mmuBus_rsp_ways_1_sel; + wire [31:0] DBusCachedPlugin_mmuBus_rsp_ways_1_physical; + wire DBusCachedPlugin_mmuBus_rsp_ways_2_sel; + wire [31:0] DBusCachedPlugin_mmuBus_rsp_ways_2_physical; + wire DBusCachedPlugin_mmuBus_rsp_ways_3_sel; + wire [31:0] DBusCachedPlugin_mmuBus_rsp_ways_3_physical; + wire DBusCachedPlugin_mmuBus_end; + wire DBusCachedPlugin_mmuBus_busy; + reg DBusCachedPlugin_redoBranch_valid; + wire [31:0] DBusCachedPlugin_redoBranch_payload; + reg DBusCachedPlugin_exceptionBus_valid; + reg [3:0] DBusCachedPlugin_exceptionBus_payload_code; + wire [31:0] DBusCachedPlugin_exceptionBus_payload_badAddr; + reg _zz_when_DBusCachedPlugin_l386; + wire decodeExceptionPort_valid; + wire [3:0] decodeExceptionPort_payload_code; + wire [31:0] decodeExceptionPort_payload_badAddr; + wire [31:0] CsrPlugin_csrMapping_readDataSignal; + wire [31:0] CsrPlugin_csrMapping_readDataInit; + wire [31:0] CsrPlugin_csrMapping_writeDataSignal; + wire CsrPlugin_csrMapping_allowCsrSignal; + wire CsrPlugin_csrMapping_hazardFree; + reg CsrPlugin_inWfi /* verilator public */ ; + reg CsrPlugin_thirdPartyWake; + reg CsrPlugin_jumpInterface_valid; + reg [31:0] CsrPlugin_jumpInterface_payload; + reg CsrPlugin_redoInterface_valid; + wire [31:0] CsrPlugin_redoInterface_payload; + wire CsrPlugin_exceptionPendings_0; + wire CsrPlugin_exceptionPendings_1; + wire CsrPlugin_exceptionPendings_2; + wire CsrPlugin_exceptionPendings_3; + wire contextSwitching; + reg [1:0] CsrPlugin_privilege; + reg CsrPlugin_forceMachineWire; + reg CsrPlugin_selfException_valid; + reg [3:0] CsrPlugin_selfException_payload_code; + wire [31:0] CsrPlugin_selfException_payload_badAddr; + reg CsrPlugin_allowInterrupts; + reg CsrPlugin_allowException; + reg CsrPlugin_allowEbreakException; + reg IBusCachedPlugin_injectionPort_valid; + reg IBusCachedPlugin_injectionPort_ready; + wire [31:0] IBusCachedPlugin_injectionPort_payload; + wire BranchPlugin_jumpInterface_valid; + wire [31:0] BranchPlugin_jumpInterface_payload; + wire BranchPlugin_branchExceptionPort_valid; + wire [3:0] BranchPlugin_branchExceptionPort_payload_code; + wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr; + reg MmuPlugin_dBusAccess_cmd_valid; + reg MmuPlugin_dBusAccess_cmd_ready; + reg [31:0] MmuPlugin_dBusAccess_cmd_payload_address; + wire [1:0] MmuPlugin_dBusAccess_cmd_payload_size; + wire MmuPlugin_dBusAccess_cmd_payload_write; + wire [31:0] MmuPlugin_dBusAccess_cmd_payload_data; + wire [3:0] MmuPlugin_dBusAccess_cmd_payload_writeMask; + wire MmuPlugin_dBusAccess_rsp_valid; + wire [31:0] MmuPlugin_dBusAccess_rsp_payload_data; + wire MmuPlugin_dBusAccess_rsp_payload_error; + wire MmuPlugin_dBusAccess_rsp_payload_redo; + wire IBusCachedPlugin_externalFlush; + wire IBusCachedPlugin_jump_pcLoad_valid; + wire [31:0] IBusCachedPlugin_jump_pcLoad_payload; + wire [4:0] _zz_IBusCachedPlugin_jump_pcLoad_payload; + wire [4:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_1; + wire _zz_IBusCachedPlugin_jump_pcLoad_payload_2; + wire _zz_IBusCachedPlugin_jump_pcLoad_payload_3; + wire _zz_IBusCachedPlugin_jump_pcLoad_payload_4; + wire _zz_IBusCachedPlugin_jump_pcLoad_payload_5; + wire IBusCachedPlugin_fetchPc_output_valid; + wire IBusCachedPlugin_fetchPc_output_ready; + wire [31:0] IBusCachedPlugin_fetchPc_output_payload; + reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ; + reg IBusCachedPlugin_fetchPc_correction; + reg IBusCachedPlugin_fetchPc_correctionReg; + wire when_Fetcher_l127; + wire IBusCachedPlugin_fetchPc_corrected; + reg IBusCachedPlugin_fetchPc_pcRegPropagate; + reg IBusCachedPlugin_fetchPc_booted; + reg IBusCachedPlugin_fetchPc_inc; + wire when_Fetcher_l131; + wire when_Fetcher_l131_1; + wire when_Fetcher_l131_2; + reg [31:0] IBusCachedPlugin_fetchPc_pc; + wire IBusCachedPlugin_fetchPc_redo_valid; + wire [31:0] IBusCachedPlugin_fetchPc_redo_payload; + reg IBusCachedPlugin_fetchPc_flushed; + wire when_Fetcher_l158; + reg IBusCachedPlugin_iBusRsp_redoFetch; + wire IBusCachedPlugin_iBusRsp_stages_0_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_0_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_0_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_0_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_0_halt; + wire IBusCachedPlugin_iBusRsp_stages_1_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_1_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_1_halt; + wire IBusCachedPlugin_iBusRsp_stages_2_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_2_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_2_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_2_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_2_halt; + wire _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready; + wire _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready; + wire _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready; + wire IBusCachedPlugin_iBusRsp_flush; + wire _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready; + wire _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1; + reg _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2; + wire IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; + reg _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + reg [31:0] _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; + reg IBusCachedPlugin_iBusRsp_readyForError; + wire IBusCachedPlugin_iBusRsp_output_valid; + wire IBusCachedPlugin_iBusRsp_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_pc; + wire IBusCachedPlugin_iBusRsp_output_payload_rsp_error; + wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; + wire IBusCachedPlugin_iBusRsp_output_payload_isRvc; + wire when_Fetcher_l240; + wire when_Fetcher_l320; + reg IBusCachedPlugin_injector_nextPcCalc_valids_0; + wire when_Fetcher_l329; + reg IBusCachedPlugin_injector_nextPcCalc_valids_1; + wire when_Fetcher_l329_1; + reg IBusCachedPlugin_injector_nextPcCalc_valids_2; + wire when_Fetcher_l329_2; + reg IBusCachedPlugin_injector_nextPcCalc_valids_3; + wire when_Fetcher_l329_3; + reg IBusCachedPlugin_injector_nextPcCalc_valids_4; + wire when_Fetcher_l329_4; + wire _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + reg [18:0] _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1; + wire _zz_2; + reg [10:0] _zz_3; + wire _zz_4; + reg [18:0] _zz_5; + reg _zz_6; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload; + reg [10:0] _zz_IBusCachedPlugin_predictionJumpInterface_payload_1; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + reg [18:0] _zz_IBusCachedPlugin_predictionJumpInterface_payload_3; + wire [31:0] _zz_IBusCachedPlugin_rspCounter; + reg [31:0] IBusCachedPlugin_rspCounter; + wire IBusCachedPlugin_s0_tightlyCoupledHit; + reg IBusCachedPlugin_s1_tightlyCoupledHit; + reg IBusCachedPlugin_s2_tightlyCoupledHit; + wire IBusCachedPlugin_rsp_iBusRspOutputHalt; + wire IBusCachedPlugin_rsp_issueDetected; + reg IBusCachedPlugin_rsp_redoFetch; + wire when_IBusCachedPlugin_l239; + wire when_IBusCachedPlugin_l244; + wire when_IBusCachedPlugin_l250; + wire when_IBusCachedPlugin_l256; + wire when_IBusCachedPlugin_l267; + wire dataCache_1_io_mem_cmd_s2mPipe_valid; + wire dataCache_1_io_mem_cmd_s2mPipe_ready; + wire dataCache_1_io_mem_cmd_s2mPipe_payload_wr; + wire dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_address; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_data; + wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_payload_mask; + wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_payload_size; + wire dataCache_1_io_mem_cmd_s2mPipe_payload_last; + reg dataCache_1_io_mem_cmd_s2mPipe_rValid; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_wr; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_uncached; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_address; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_data; + reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_rData_mask; + reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_rData_size; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_last; + wire when_Stream_l365; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; + wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; + wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; + reg dataCache_1_io_mem_cmd_s2mPipe_rValid_1; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_wr_1; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_uncached_1; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_address_1; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_data_1; + reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_rData_mask_1; + reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_rData_size_1; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_last_1; + reg dBus_rsp_regNext_valid; + reg dBus_rsp_regNext_payload_last; + reg [31:0] dBus_rsp_regNext_payload_data; + reg dBus_rsp_regNext_payload_error; + wire [31:0] _zz_DBusCachedPlugin_rspCounter; + reg [31:0] DBusCachedPlugin_rspCounter; + wire when_DBusCachedPlugin_l303; + wire when_DBusCachedPlugin_l311; + wire [1:0] execute_DBusCachedPlugin_size; + reg [31:0] _zz_execute_MEMORY_STORE_DATA_RF; + wire when_DBusCachedPlugin_l343; + wire when_DBusCachedPlugin_l359; + wire when_DBusCachedPlugin_l386; + wire when_DBusCachedPlugin_l438; + wire when_DBusCachedPlugin_l458; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_0; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_1; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_2; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_3; + reg [31:0] writeBack_DBusCachedPlugin_rspShifted; + reg [31:0] writeBack_DBusCachedPlugin_rspRf; + wire when_DBusCachedPlugin_l474; + wire [1:0] switch_Misc_l199; + wire _zz_writeBack_DBusCachedPlugin_rspFormated; + reg [31:0] _zz_writeBack_DBusCachedPlugin_rspFormated_1; + wire _zz_writeBack_DBusCachedPlugin_rspFormated_2; + reg [31:0] _zz_writeBack_DBusCachedPlugin_rspFormated_3; + reg [31:0] writeBack_DBusCachedPlugin_rspFormated; + wire when_DBusCachedPlugin_l484; + reg DBusCachedPlugin_forceDatapath; + wire when_DBusCachedPlugin_l498; + wire when_DBusCachedPlugin_l499; + wire [36:0] _zz_decode_IS_SFENCE_VMA2; + wire _zz_decode_IS_SFENCE_VMA2_1; + wire _zz_decode_IS_SFENCE_VMA2_2; + wire _zz_decode_IS_SFENCE_VMA2_3; + wire _zz_decode_IS_SFENCE_VMA2_4; + wire _zz_decode_IS_SFENCE_VMA2_5; + wire _zz_decode_IS_SFENCE_VMA2_6; + wire _zz_decode_IS_SFENCE_VMA2_7; + wire `Src1CtrlEnum_defaultEncoding_type _zz_decode_SRC1_CTRL_2; + wire `AluCtrlEnum_defaultEncoding_type _zz_decode_ALU_CTRL_2; + wire `Src2CtrlEnum_defaultEncoding_type _zz_decode_SRC2_CTRL_2; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_decode_ALU_BITWISE_CTRL_2; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_decode_SHIFT_CTRL_2; + wire `EnvCtrlEnum_defaultEncoding_type _zz_decode_ENV_CTRL_2; + wire `BranchCtrlEnum_defaultEncoding_type _zz_decode_BRANCH_CTRL_2; + wire when_RegFilePlugin_l63; + wire [4:0] decode_RegFilePlugin_regFileReadAddress1; + wire [4:0] decode_RegFilePlugin_regFileReadAddress2; + wire [31:0] decode_RegFilePlugin_rs1Data; + wire [31:0] decode_RegFilePlugin_rs2Data; + reg lastStageRegFileWrite_valid /* verilator public */ ; + reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; + reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; + reg _zz_7; + reg [31:0] execute_IntAluPlugin_bitwise; + reg [31:0] _zz_execute_REGFILE_WRITE_DATA; + reg [31:0] _zz_decode_SRC1_1; + wire _zz_decode_SRC2_2; + reg [19:0] _zz_decode_SRC2_3; + wire _zz_decode_SRC2_4; + reg [19:0] _zz_decode_SRC2_5; + reg [31:0] _zz_decode_SRC2_6; + reg [31:0] execute_SrcPlugin_addSub; + wire execute_SrcPlugin_less; + wire [4:0] execute_FullBarrelShifterPlugin_amplitude; + reg [31:0] _zz_execute_FullBarrelShifterPlugin_reversed; + wire [31:0] execute_FullBarrelShifterPlugin_reversed; + reg [31:0] _zz_decode_RS2_3; + reg HazardSimplePlugin_src0Hazard; + reg HazardSimplePlugin_src1Hazard; + wire HazardSimplePlugin_writeBackWrites_valid; + wire [4:0] HazardSimplePlugin_writeBackWrites_payload_address; + wire [31:0] HazardSimplePlugin_writeBackWrites_payload_data; + reg HazardSimplePlugin_writeBackBuffer_valid; + reg [4:0] HazardSimplePlugin_writeBackBuffer_payload_address; + reg [31:0] HazardSimplePlugin_writeBackBuffer_payload_data; + wire HazardSimplePlugin_addr0Match; + wire HazardSimplePlugin_addr1Match; + wire when_HazardSimplePlugin_l47; + wire when_HazardSimplePlugin_l48; + wire when_HazardSimplePlugin_l51; + wire when_HazardSimplePlugin_l45; + wire when_HazardSimplePlugin_l57; + wire when_HazardSimplePlugin_l58; + wire when_HazardSimplePlugin_l48_1; + wire when_HazardSimplePlugin_l51_1; + wire when_HazardSimplePlugin_l45_1; + wire when_HazardSimplePlugin_l57_1; + wire when_HazardSimplePlugin_l58_1; + wire when_HazardSimplePlugin_l48_2; + wire when_HazardSimplePlugin_l51_2; + wire when_HazardSimplePlugin_l45_2; + wire when_HazardSimplePlugin_l57_2; + wire when_HazardSimplePlugin_l58_2; + wire when_HazardSimplePlugin_l105; + wire when_HazardSimplePlugin_l108; + wire when_HazardSimplePlugin_l113; + reg execute_MulPlugin_aSigned; + reg execute_MulPlugin_bSigned; + wire [31:0] execute_MulPlugin_a; + wire [31:0] execute_MulPlugin_b; + wire [1:0] switch_MulPlugin_l87; + wire [15:0] execute_MulPlugin_aULow; + wire [15:0] execute_MulPlugin_bULow; + wire [16:0] execute_MulPlugin_aSLow; + wire [16:0] execute_MulPlugin_bSLow; + wire [16:0] execute_MulPlugin_aHigh; + wire [16:0] execute_MulPlugin_bHigh; + wire [65:0] writeBack_MulPlugin_result; + wire when_MulPlugin_l147; + wire [1:0] switch_MulPlugin_l148; + reg [32:0] memory_MulDivIterativePlugin_rs1; + reg [31:0] memory_MulDivIterativePlugin_rs2; + reg [64:0] memory_MulDivIterativePlugin_accumulator; + wire memory_MulDivIterativePlugin_frontendOk; + reg memory_MulDivIterativePlugin_div_needRevert; + reg memory_MulDivIterativePlugin_div_counter_willIncrement; + reg memory_MulDivIterativePlugin_div_counter_willClear; + reg [5:0] memory_MulDivIterativePlugin_div_counter_valueNext; + reg [5:0] memory_MulDivIterativePlugin_div_counter_value; + wire memory_MulDivIterativePlugin_div_counter_willOverflowIfInc; + wire memory_MulDivIterativePlugin_div_counter_willOverflow; + reg memory_MulDivIterativePlugin_div_done; + wire when_MulDivIterativePlugin_l126; + wire when_MulDivIterativePlugin_l126_1; + reg [31:0] memory_MulDivIterativePlugin_div_result; + wire when_MulDivIterativePlugin_l128; + wire when_MulDivIterativePlugin_l129; + wire when_MulDivIterativePlugin_l132; + wire [31:0] _zz_memory_MulDivIterativePlugin_div_stage_0_remainderShifted; + wire [32:0] memory_MulDivIterativePlugin_div_stage_0_remainderShifted; + wire [32:0] memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator; + wire [31:0] memory_MulDivIterativePlugin_div_stage_0_outRemainder; + wire [31:0] memory_MulDivIterativePlugin_div_stage_0_outNumerator; + wire when_MulDivIterativePlugin_l151; + wire [31:0] _zz_memory_MulDivIterativePlugin_div_result; + wire when_MulDivIterativePlugin_l162; + wire _zz_memory_MulDivIterativePlugin_rs2; + wire _zz_memory_MulDivIterativePlugin_rs1; + reg [32:0] _zz_memory_MulDivIterativePlugin_rs1_1; + reg [1:0] _zz_CsrPlugin_privilege; + wire [1:0] CsrPlugin_misa_base; + wire [25:0] CsrPlugin_misa_extensions; + reg [1:0] CsrPlugin_mtvec_mode; + reg [29:0] CsrPlugin_mtvec_base; + reg [31:0] CsrPlugin_mepc; + reg CsrPlugin_mstatus_MIE; + reg CsrPlugin_mstatus_MPIE; + reg [1:0] CsrPlugin_mstatus_MPP; + reg CsrPlugin_mip_MEIP; + reg CsrPlugin_mip_MTIP; + reg CsrPlugin_mip_MSIP; + reg CsrPlugin_mie_MEIE; + reg CsrPlugin_mie_MTIE; + reg CsrPlugin_mie_MSIE; + reg [31:0] CsrPlugin_mscratch; + reg CsrPlugin_mcause_interrupt; + reg [3:0] CsrPlugin_mcause_exceptionCode; + reg [31:0] CsrPlugin_mtval; + reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; + reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; + reg CsrPlugin_medeleg_IAM; + reg CsrPlugin_medeleg_IAF; + reg CsrPlugin_medeleg_II; + reg CsrPlugin_medeleg_LAM; + reg CsrPlugin_medeleg_LAF; + reg CsrPlugin_medeleg_SAM; + reg CsrPlugin_medeleg_SAF; + reg CsrPlugin_medeleg_EU; + reg CsrPlugin_medeleg_ES; + reg CsrPlugin_medeleg_IPF; + reg CsrPlugin_medeleg_LPF; + reg CsrPlugin_medeleg_SPF; + reg CsrPlugin_mideleg_ST; + reg CsrPlugin_mideleg_SE; + reg CsrPlugin_mideleg_SS; + reg CsrPlugin_sstatus_SIE; + reg CsrPlugin_sstatus_SPIE; + reg [0:0] CsrPlugin_sstatus_SPP; + reg CsrPlugin_sip_SEIP_SOFT; + reg CsrPlugin_sip_SEIP_INPUT; + wire CsrPlugin_sip_SEIP_OR; + reg CsrPlugin_sip_STIP; + reg CsrPlugin_sip_SSIP; + reg CsrPlugin_sie_SEIE; + reg CsrPlugin_sie_STIE; + reg CsrPlugin_sie_SSIE; + reg [1:0] CsrPlugin_stvec_mode; + reg [29:0] CsrPlugin_stvec_base; + reg [31:0] CsrPlugin_sscratch; + reg CsrPlugin_scause_interrupt; + reg [3:0] CsrPlugin_scause_exceptionCode; + reg [31:0] CsrPlugin_stval; + reg [31:0] CsrPlugin_sepc; + reg [21:0] CsrPlugin_satp_PPN; + reg [8:0] CsrPlugin_satp_ASID; + reg [0:0] CsrPlugin_satp_MODE; + reg CsrPlugin_rescheduleLogic_rescheduleNext; + wire when_CsrPlugin_l803; + wire _zz_when_CsrPlugin_l952; + wire _zz_when_CsrPlugin_l952_1; + wire _zz_when_CsrPlugin_l952_2; + wire _zz_when_CsrPlugin_l952_3; + wire _zz_when_CsrPlugin_l952_4; + wire _zz_when_CsrPlugin_l952_5; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code; + reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + reg [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; + wire when_CsrPlugin_l866; + wire when_CsrPlugin_l866_1; + wire when_CsrPlugin_l866_2; + wire when_CsrPlugin_l866_3; + wire when_CsrPlugin_l866_4; + wire when_CsrPlugin_l866_5; + wire when_CsrPlugin_l866_6; + wire when_CsrPlugin_l866_7; + wire when_CsrPlugin_l866_8; + wire when_CsrPlugin_l866_9; + wire when_CsrPlugin_l866_10; + wire when_CsrPlugin_l866_11; + wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; + wire [1:0] _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code; + wire _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1; + wire when_CsrPlugin_l909; + wire when_CsrPlugin_l909_1; + wire when_CsrPlugin_l909_2; + wire when_CsrPlugin_l909_3; + wire when_CsrPlugin_l922; + reg CsrPlugin_interrupt_valid; + reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; + reg [1:0] CsrPlugin_interrupt_targetPrivilege; + wire when_CsrPlugin_l946; + wire when_CsrPlugin_l946_1; + wire when_CsrPlugin_l952; + wire when_CsrPlugin_l952_1; + wire when_CsrPlugin_l952_2; + wire when_CsrPlugin_l952_3; + wire when_CsrPlugin_l952_4; + wire when_CsrPlugin_l952_5; + wire when_CsrPlugin_l952_6; + wire when_CsrPlugin_l952_7; + wire when_CsrPlugin_l952_8; + wire CsrPlugin_exception; + reg CsrPlugin_lastStageWasWfi; + reg CsrPlugin_pipelineLiberator_pcValids_0; + reg CsrPlugin_pipelineLiberator_pcValids_1; + reg CsrPlugin_pipelineLiberator_pcValids_2; + wire CsrPlugin_pipelineLiberator_active; + wire when_CsrPlugin_l980; + wire when_CsrPlugin_l980_1; + wire when_CsrPlugin_l980_2; + wire when_CsrPlugin_l985; + reg CsrPlugin_pipelineLiberator_done; + wire when_CsrPlugin_l991; + wire CsrPlugin_interruptJump /* verilator public */ ; + reg CsrPlugin_hadException /* verilator public */ ; + reg [1:0] CsrPlugin_targetPrivilege; + reg [3:0] CsrPlugin_trapCause; + reg [1:0] CsrPlugin_xtvec_mode; + reg [29:0] CsrPlugin_xtvec_base; + wire when_CsrPlugin_l1019; + wire when_CsrPlugin_l1064; + wire [1:0] switch_CsrPlugin_l1068; + reg execute_CsrPlugin_wfiWake; + wire when_CsrPlugin_l1108; + wire when_CsrPlugin_l1110; + wire when_CsrPlugin_l1116; + wire execute_CsrPlugin_blockedBySideEffects; + reg execute_CsrPlugin_illegalAccess; + reg execute_CsrPlugin_illegalInstruction; + wire when_CsrPlugin_l1129; + wire when_CsrPlugin_l1136; + wire when_CsrPlugin_l1137; + wire when_CsrPlugin_l1144; + reg execute_CsrPlugin_writeInstruction; + reg execute_CsrPlugin_readInstruction; + wire execute_CsrPlugin_writeEnable; + wire execute_CsrPlugin_readEnable; + reg [31:0] execute_CsrPlugin_readToWriteData; + wire switch_Misc_l199_1; + reg [31:0] _zz_CsrPlugin_csrMapping_writeDataSignal; + wire when_CsrPlugin_l1176; + wire when_CsrPlugin_l1180; + wire [11:0] execute_CsrPlugin_csrAddress; + reg DebugPlugin_firstCycle; + reg DebugPlugin_secondCycle; + reg DebugPlugin_resetIt; + reg DebugPlugin_haltIt; + reg DebugPlugin_stepIt; + reg DebugPlugin_isPipBusy; + reg DebugPlugin_godmode; + wire when_DebugPlugin_l225; + reg DebugPlugin_haltedByBreak; + reg DebugPlugin_debugUsed /* verilator public */ ; + reg DebugPlugin_disableEbreak; + wire DebugPlugin_allowEBreak; + reg [31:0] DebugPlugin_busReadDataReg; + reg _zz_when_DebugPlugin_l244; + wire when_DebugPlugin_l244; + wire [5:0] switch_DebugPlugin_l256; + wire when_DebugPlugin_l260; + wire when_DebugPlugin_l260_1; + wire when_DebugPlugin_l261; + wire when_DebugPlugin_l261_1; + wire when_DebugPlugin_l262; + wire when_DebugPlugin_l263; + wire when_DebugPlugin_l264; + wire when_DebugPlugin_l264_1; + wire when_DebugPlugin_l284; + wire when_DebugPlugin_l287; + wire when_DebugPlugin_l300; + reg DebugPlugin_resetIt_regNext; + wire when_DebugPlugin_l316; + wire execute_BranchPlugin_eq; + wire [2:0] switch_Misc_l199_2; + reg _zz_execute_BRANCH_COND_RESULT; + reg _zz_execute_BRANCH_COND_RESULT_1; + wire _zz_execute_BranchPlugin_missAlignedTarget; + reg [19:0] _zz_execute_BranchPlugin_missAlignedTarget_1; + wire _zz_execute_BranchPlugin_missAlignedTarget_2; + reg [10:0] _zz_execute_BranchPlugin_missAlignedTarget_3; + wire _zz_execute_BranchPlugin_missAlignedTarget_4; + reg [18:0] _zz_execute_BranchPlugin_missAlignedTarget_5; + reg _zz_execute_BranchPlugin_missAlignedTarget_6; + wire execute_BranchPlugin_missAlignedTarget; + reg [31:0] execute_BranchPlugin_branch_src1; + reg [31:0] execute_BranchPlugin_branch_src2; + wire _zz_execute_BranchPlugin_branch_src2; + reg [19:0] _zz_execute_BranchPlugin_branch_src2_1; + wire _zz_execute_BranchPlugin_branch_src2_2; + reg [10:0] _zz_execute_BranchPlugin_branch_src2_3; + wire _zz_execute_BranchPlugin_branch_src2_4; + reg [18:0] _zz_execute_BranchPlugin_branch_src2_5; + wire [31:0] execute_BranchPlugin_branchAdder; + reg MmuPlugin_status_sum; + reg MmuPlugin_status_mxr; + reg MmuPlugin_status_mprv; + reg MmuPlugin_satp_mode; + reg [8:0] MmuPlugin_satp_asid; + reg [19:0] MmuPlugin_satp_ppn; + reg MmuPlugin_ports_0_cache_0_valid; + reg MmuPlugin_ports_0_cache_0_exception; + reg MmuPlugin_ports_0_cache_0_superPage; + reg [9:0] MmuPlugin_ports_0_cache_0_virtualAddress_0; + reg [9:0] MmuPlugin_ports_0_cache_0_virtualAddress_1; + reg [9:0] MmuPlugin_ports_0_cache_0_physicalAddress_0; + reg [9:0] MmuPlugin_ports_0_cache_0_physicalAddress_1; + reg MmuPlugin_ports_0_cache_0_allowRead; + reg MmuPlugin_ports_0_cache_0_allowWrite; + reg MmuPlugin_ports_0_cache_0_allowExecute; + reg MmuPlugin_ports_0_cache_0_allowUser; + reg MmuPlugin_ports_0_cache_1_valid; + reg MmuPlugin_ports_0_cache_1_exception; + reg MmuPlugin_ports_0_cache_1_superPage; + reg [9:0] MmuPlugin_ports_0_cache_1_virtualAddress_0; + reg [9:0] MmuPlugin_ports_0_cache_1_virtualAddress_1; + reg [9:0] MmuPlugin_ports_0_cache_1_physicalAddress_0; + reg [9:0] MmuPlugin_ports_0_cache_1_physicalAddress_1; + reg MmuPlugin_ports_0_cache_1_allowRead; + reg MmuPlugin_ports_0_cache_1_allowWrite; + reg MmuPlugin_ports_0_cache_1_allowExecute; + reg MmuPlugin_ports_0_cache_1_allowUser; + reg MmuPlugin_ports_0_cache_2_valid; + reg MmuPlugin_ports_0_cache_2_exception; + reg MmuPlugin_ports_0_cache_2_superPage; + reg [9:0] MmuPlugin_ports_0_cache_2_virtualAddress_0; + reg [9:0] MmuPlugin_ports_0_cache_2_virtualAddress_1; + reg [9:0] MmuPlugin_ports_0_cache_2_physicalAddress_0; + reg [9:0] MmuPlugin_ports_0_cache_2_physicalAddress_1; + reg MmuPlugin_ports_0_cache_2_allowRead; + reg MmuPlugin_ports_0_cache_2_allowWrite; + reg MmuPlugin_ports_0_cache_2_allowExecute; + reg MmuPlugin_ports_0_cache_2_allowUser; + reg MmuPlugin_ports_0_cache_3_valid; + reg MmuPlugin_ports_0_cache_3_exception; + reg MmuPlugin_ports_0_cache_3_superPage; + reg [9:0] MmuPlugin_ports_0_cache_3_virtualAddress_0; + reg [9:0] MmuPlugin_ports_0_cache_3_virtualAddress_1; + reg [9:0] MmuPlugin_ports_0_cache_3_physicalAddress_0; + reg [9:0] MmuPlugin_ports_0_cache_3_physicalAddress_1; + reg MmuPlugin_ports_0_cache_3_allowRead; + reg MmuPlugin_ports_0_cache_3_allowWrite; + reg MmuPlugin_ports_0_cache_3_allowExecute; + reg MmuPlugin_ports_0_cache_3_allowUser; + wire MmuPlugin_ports_0_dirty; + reg MmuPlugin_ports_0_requireMmuLockupCalc; + wire when_MmuPlugin_l125; + wire when_MmuPlugin_l126; + wire [3:0] MmuPlugin_ports_0_cacheHitsCalc; + wire MmuPlugin_ports_0_cacheHit; + wire _zz_MmuPlugin_ports_0_cacheLine_valid; + wire _zz_MmuPlugin_ports_0_cacheLine_valid_1; + wire _zz_MmuPlugin_ports_0_cacheLine_valid_2; + wire [1:0] _zz_MmuPlugin_ports_0_cacheLine_valid_3; + wire MmuPlugin_ports_0_cacheLine_valid; + wire MmuPlugin_ports_0_cacheLine_exception; + wire MmuPlugin_ports_0_cacheLine_superPage; + wire [9:0] MmuPlugin_ports_0_cacheLine_virtualAddress_0; + wire [9:0] MmuPlugin_ports_0_cacheLine_virtualAddress_1; + wire [9:0] MmuPlugin_ports_0_cacheLine_physicalAddress_0; + wire [9:0] MmuPlugin_ports_0_cacheLine_physicalAddress_1; + wire MmuPlugin_ports_0_cacheLine_allowRead; + wire MmuPlugin_ports_0_cacheLine_allowWrite; + wire MmuPlugin_ports_0_cacheLine_allowExecute; + wire MmuPlugin_ports_0_cacheLine_allowUser; + reg MmuPlugin_ports_0_entryToReplace_willIncrement; + wire MmuPlugin_ports_0_entryToReplace_willClear; + reg [1:0] MmuPlugin_ports_0_entryToReplace_valueNext; + reg [1:0] MmuPlugin_ports_0_entryToReplace_value; + wire MmuPlugin_ports_0_entryToReplace_willOverflowIfInc; + wire MmuPlugin_ports_0_entryToReplace_willOverflow; + reg MmuPlugin_ports_1_cache_0_valid; + reg MmuPlugin_ports_1_cache_0_exception; + reg MmuPlugin_ports_1_cache_0_superPage; + reg [9:0] MmuPlugin_ports_1_cache_0_virtualAddress_0; + reg [9:0] MmuPlugin_ports_1_cache_0_virtualAddress_1; + reg [9:0] MmuPlugin_ports_1_cache_0_physicalAddress_0; + reg [9:0] MmuPlugin_ports_1_cache_0_physicalAddress_1; + reg MmuPlugin_ports_1_cache_0_allowRead; + reg MmuPlugin_ports_1_cache_0_allowWrite; + reg MmuPlugin_ports_1_cache_0_allowExecute; + reg MmuPlugin_ports_1_cache_0_allowUser; + reg MmuPlugin_ports_1_cache_1_valid; + reg MmuPlugin_ports_1_cache_1_exception; + reg MmuPlugin_ports_1_cache_1_superPage; + reg [9:0] MmuPlugin_ports_1_cache_1_virtualAddress_0; + reg [9:0] MmuPlugin_ports_1_cache_1_virtualAddress_1; + reg [9:0] MmuPlugin_ports_1_cache_1_physicalAddress_0; + reg [9:0] MmuPlugin_ports_1_cache_1_physicalAddress_1; + reg MmuPlugin_ports_1_cache_1_allowRead; + reg MmuPlugin_ports_1_cache_1_allowWrite; + reg MmuPlugin_ports_1_cache_1_allowExecute; + reg MmuPlugin_ports_1_cache_1_allowUser; + reg MmuPlugin_ports_1_cache_2_valid; + reg MmuPlugin_ports_1_cache_2_exception; + reg MmuPlugin_ports_1_cache_2_superPage; + reg [9:0] MmuPlugin_ports_1_cache_2_virtualAddress_0; + reg [9:0] MmuPlugin_ports_1_cache_2_virtualAddress_1; + reg [9:0] MmuPlugin_ports_1_cache_2_physicalAddress_0; + reg [9:0] MmuPlugin_ports_1_cache_2_physicalAddress_1; + reg MmuPlugin_ports_1_cache_2_allowRead; + reg MmuPlugin_ports_1_cache_2_allowWrite; + reg MmuPlugin_ports_1_cache_2_allowExecute; + reg MmuPlugin_ports_1_cache_2_allowUser; + reg MmuPlugin_ports_1_cache_3_valid; + reg MmuPlugin_ports_1_cache_3_exception; + reg MmuPlugin_ports_1_cache_3_superPage; + reg [9:0] MmuPlugin_ports_1_cache_3_virtualAddress_0; + reg [9:0] MmuPlugin_ports_1_cache_3_virtualAddress_1; + reg [9:0] MmuPlugin_ports_1_cache_3_physicalAddress_0; + reg [9:0] MmuPlugin_ports_1_cache_3_physicalAddress_1; + reg MmuPlugin_ports_1_cache_3_allowRead; + reg MmuPlugin_ports_1_cache_3_allowWrite; + reg MmuPlugin_ports_1_cache_3_allowExecute; + reg MmuPlugin_ports_1_cache_3_allowUser; + wire MmuPlugin_ports_1_dirty; + reg MmuPlugin_ports_1_requireMmuLockupCalc; + wire when_MmuPlugin_l125_1; + wire when_MmuPlugin_l126_1; + wire when_MmuPlugin_l128; + wire [3:0] MmuPlugin_ports_1_cacheHitsCalc; + wire MmuPlugin_ports_1_cacheHit; + wire _zz_MmuPlugin_ports_1_cacheLine_valid; + wire _zz_MmuPlugin_ports_1_cacheLine_valid_1; + wire _zz_MmuPlugin_ports_1_cacheLine_valid_2; + wire [1:0] _zz_MmuPlugin_ports_1_cacheLine_valid_3; + wire MmuPlugin_ports_1_cacheLine_valid; + wire MmuPlugin_ports_1_cacheLine_exception; + wire MmuPlugin_ports_1_cacheLine_superPage; + wire [9:0] MmuPlugin_ports_1_cacheLine_virtualAddress_0; + wire [9:0] MmuPlugin_ports_1_cacheLine_virtualAddress_1; + wire [9:0] MmuPlugin_ports_1_cacheLine_physicalAddress_0; + wire [9:0] MmuPlugin_ports_1_cacheLine_physicalAddress_1; + wire MmuPlugin_ports_1_cacheLine_allowRead; + wire MmuPlugin_ports_1_cacheLine_allowWrite; + wire MmuPlugin_ports_1_cacheLine_allowExecute; + wire MmuPlugin_ports_1_cacheLine_allowUser; + reg MmuPlugin_ports_1_entryToReplace_willIncrement; + wire MmuPlugin_ports_1_entryToReplace_willClear; + reg [1:0] MmuPlugin_ports_1_entryToReplace_valueNext; + reg [1:0] MmuPlugin_ports_1_entryToReplace_value; + wire MmuPlugin_ports_1_entryToReplace_willOverflowIfInc; + wire MmuPlugin_ports_1_entryToReplace_willOverflow; + reg `MmuPlugin_shared_State_defaultEncoding_type MmuPlugin_shared_state_1; + reg [9:0] MmuPlugin_shared_vpn_0; + reg [9:0] MmuPlugin_shared_vpn_1; + reg [1:0] MmuPlugin_shared_portSortedOh; + reg MmuPlugin_shared_dBusRspStaged_valid; + reg [31:0] MmuPlugin_shared_dBusRspStaged_payload_data; + reg MmuPlugin_shared_dBusRspStaged_payload_error; + reg MmuPlugin_shared_dBusRspStaged_payload_redo; + wire MmuPlugin_shared_dBusRsp_pte_V; + wire MmuPlugin_shared_dBusRsp_pte_R; + wire MmuPlugin_shared_dBusRsp_pte_W; + wire MmuPlugin_shared_dBusRsp_pte_X; + wire MmuPlugin_shared_dBusRsp_pte_U; + wire MmuPlugin_shared_dBusRsp_pte_G; + wire MmuPlugin_shared_dBusRsp_pte_A; + wire MmuPlugin_shared_dBusRsp_pte_D; + wire [1:0] MmuPlugin_shared_dBusRsp_pte_RSW; + wire [9:0] MmuPlugin_shared_dBusRsp_pte_PPN0; + wire [11:0] MmuPlugin_shared_dBusRsp_pte_PPN1; + wire MmuPlugin_shared_dBusRsp_exception; + wire MmuPlugin_shared_dBusRsp_leaf; + wire when_MmuPlugin_l205; + reg MmuPlugin_shared_pteBuffer_V; + reg MmuPlugin_shared_pteBuffer_R; + reg MmuPlugin_shared_pteBuffer_W; + reg MmuPlugin_shared_pteBuffer_X; + reg MmuPlugin_shared_pteBuffer_U; + reg MmuPlugin_shared_pteBuffer_G; + reg MmuPlugin_shared_pteBuffer_A; + reg MmuPlugin_shared_pteBuffer_D; + reg [1:0] MmuPlugin_shared_pteBuffer_RSW; + reg [9:0] MmuPlugin_shared_pteBuffer_PPN0; + reg [11:0] MmuPlugin_shared_pteBuffer_PPN1; + wire [1:0] _zz_MmuPlugin_shared_refills; + reg [1:0] _zz_MmuPlugin_shared_refills_1; + wire [1:0] MmuPlugin_shared_refills; + wire [1:0] _zz_MmuPlugin_shared_refills_2; + reg [1:0] _zz_MmuPlugin_shared_refills_3; + wire when_MmuPlugin_l217; + wire [31:0] _zz_MmuPlugin_shared_vpn_0; + wire when_MmuPlugin_l243; + wire when_MmuPlugin_l272; + wire when_MmuPlugin_l274; + wire when_MmuPlugin_l280; + wire when_MmuPlugin_l280_1; + wire when_MmuPlugin_l280_2; + wire when_MmuPlugin_l280_3; + wire when_MmuPlugin_l274_1; + wire when_MmuPlugin_l280_4; + wire when_MmuPlugin_l280_5; + wire when_MmuPlugin_l280_6; + wire when_MmuPlugin_l280_7; + wire when_MmuPlugin_l304; + wire when_Pipeline_l124; + reg [31:0] decode_to_execute_PC; + wire when_Pipeline_l124_1; + reg [31:0] execute_to_memory_PC; + wire when_Pipeline_l124_2; + reg [31:0] memory_to_writeBack_PC; + wire when_Pipeline_l124_3; + reg [31:0] decode_to_execute_INSTRUCTION; + wire when_Pipeline_l124_4; + reg [31:0] execute_to_memory_INSTRUCTION; + wire when_Pipeline_l124_5; + reg [31:0] memory_to_writeBack_INSTRUCTION; + wire when_Pipeline_l124_6; + reg [31:0] decode_to_execute_FORMAL_PC_NEXT; + wire when_Pipeline_l124_7; + reg [31:0] execute_to_memory_FORMAL_PC_NEXT; + wire when_Pipeline_l124_8; + reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; + wire when_Pipeline_l124_9; + reg decode_to_execute_MEMORY_FORCE_CONSTISTENCY; + wire when_Pipeline_l124_10; + reg decode_to_execute_SRC_USE_SUB_LESS; + wire when_Pipeline_l124_11; + reg decode_to_execute_MEMORY_ENABLE; + wire when_Pipeline_l124_12; + reg execute_to_memory_MEMORY_ENABLE; + wire when_Pipeline_l124_13; + reg memory_to_writeBack_MEMORY_ENABLE; + wire when_Pipeline_l124_14; + reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; + wire when_Pipeline_l124_15; + reg decode_to_execute_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_16; + reg execute_to_memory_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_17; + reg memory_to_writeBack_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_18; + reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + wire when_Pipeline_l124_19; + reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; + wire when_Pipeline_l124_20; + reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; + wire when_Pipeline_l124_21; + reg decode_to_execute_MEMORY_WR; + wire when_Pipeline_l124_22; + reg execute_to_memory_MEMORY_WR; + wire when_Pipeline_l124_23; + reg memory_to_writeBack_MEMORY_WR; + wire when_Pipeline_l124_24; + reg decode_to_execute_MEMORY_LRSC; + wire when_Pipeline_l124_25; + reg execute_to_memory_MEMORY_LRSC; + wire when_Pipeline_l124_26; + reg memory_to_writeBack_MEMORY_LRSC; + wire when_Pipeline_l124_27; + reg decode_to_execute_MEMORY_AMO; + wire when_Pipeline_l124_28; + reg decode_to_execute_MEMORY_MANAGMENT; + wire when_Pipeline_l124_29; + reg decode_to_execute_SRC_LESS_UNSIGNED; + wire when_Pipeline_l124_30; + reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; + wire when_Pipeline_l124_31; + reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; + wire when_Pipeline_l124_32; + reg `ShiftCtrlEnum_defaultEncoding_type execute_to_memory_SHIFT_CTRL; + wire when_Pipeline_l124_33; + reg decode_to_execute_IS_MUL; + wire when_Pipeline_l124_34; + reg execute_to_memory_IS_MUL; + wire when_Pipeline_l124_35; + reg memory_to_writeBack_IS_MUL; + wire when_Pipeline_l124_36; + reg decode_to_execute_IS_DIV; + wire when_Pipeline_l124_37; + reg execute_to_memory_IS_DIV; + wire when_Pipeline_l124_38; + reg decode_to_execute_IS_RS1_SIGNED; + wire when_Pipeline_l124_39; + reg decode_to_execute_IS_RS2_SIGNED; + wire when_Pipeline_l124_40; + reg decode_to_execute_IS_CSR; + wire when_Pipeline_l124_41; + reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; + wire when_Pipeline_l124_42; + reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL; + wire when_Pipeline_l124_43; + reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL; + wire when_Pipeline_l124_44; + reg decode_to_execute_IS_SFENCE_VMA; + wire when_Pipeline_l124_45; + reg decode_to_execute_IS_SFENCE_VMA2; + wire when_Pipeline_l124_46; + reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; + wire when_Pipeline_l124_47; + reg [31:0] decode_to_execute_RS1; + wire when_Pipeline_l124_48; + reg [31:0] decode_to_execute_RS2; + wire when_Pipeline_l124_49; + reg decode_to_execute_SRC2_FORCE_ZERO; + wire when_Pipeline_l124_50; + reg [31:0] decode_to_execute_SRC1; + wire when_Pipeline_l124_51; + reg [31:0] decode_to_execute_SRC2; + wire when_Pipeline_l124_52; + reg decode_to_execute_CSR_WRITE_OPCODE; + wire when_Pipeline_l124_53; + reg decode_to_execute_CSR_READ_OPCODE; + wire when_Pipeline_l124_54; + reg decode_to_execute_DO_EBREAK; + wire when_Pipeline_l124_55; + reg decode_to_execute_PREDICTION_HAD_BRANCHED2; + wire when_Pipeline_l124_56; + reg [31:0] execute_to_memory_MEMORY_STORE_DATA_RF; + wire when_Pipeline_l124_57; + reg [31:0] memory_to_writeBack_MEMORY_STORE_DATA_RF; + wire when_Pipeline_l124_58; + reg execute_to_memory_IS_DBUS_SHARING; + wire when_Pipeline_l124_59; + reg memory_to_writeBack_IS_DBUS_SHARING; + wire when_Pipeline_l124_60; + reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; + wire when_Pipeline_l124_61; + reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; + wire when_Pipeline_l124_62; + reg [31:0] execute_to_memory_SHIFT_RIGHT; + wire when_Pipeline_l124_63; + reg [31:0] execute_to_memory_MUL_LL; + wire when_Pipeline_l124_64; + reg [33:0] execute_to_memory_MUL_LH; + wire when_Pipeline_l124_65; + reg [33:0] execute_to_memory_MUL_HL; + wire when_Pipeline_l124_66; + reg [33:0] execute_to_memory_MUL_HH; + wire when_Pipeline_l124_67; + reg [33:0] memory_to_writeBack_MUL_HH; + wire when_Pipeline_l124_68; + reg execute_to_memory_BRANCH_DO; + wire when_Pipeline_l124_69; + reg [31:0] execute_to_memory_BRANCH_CALC; + wire when_Pipeline_l124_70; + reg [51:0] memory_to_writeBack_MUL_LOW; + wire when_Pipeline_l151; + wire when_Pipeline_l154; + wire when_Pipeline_l151_1; + wire when_Pipeline_l154_1; + wire when_Pipeline_l151_2; + wire when_Pipeline_l154_2; + reg [2:0] switch_Fetcher_l362; + wire when_Fetcher_l378; + wire when_CsrPlugin_l1264; + reg execute_CsrPlugin_csr_3857; + wire when_CsrPlugin_l1264_1; + reg execute_CsrPlugin_csr_3858; + wire when_CsrPlugin_l1264_2; + reg execute_CsrPlugin_csr_3859; + wire when_CsrPlugin_l1264_3; + reg execute_CsrPlugin_csr_3860; + wire when_CsrPlugin_l1264_4; + reg execute_CsrPlugin_csr_768; + wire when_CsrPlugin_l1264_5; + reg execute_CsrPlugin_csr_836; + wire when_CsrPlugin_l1264_6; + reg execute_CsrPlugin_csr_772; + wire when_CsrPlugin_l1264_7; + reg execute_CsrPlugin_csr_773; + wire when_CsrPlugin_l1264_8; + reg execute_CsrPlugin_csr_833; + wire when_CsrPlugin_l1264_9; + reg execute_CsrPlugin_csr_832; + wire when_CsrPlugin_l1264_10; + reg execute_CsrPlugin_csr_834; + wire when_CsrPlugin_l1264_11; + reg execute_CsrPlugin_csr_835; + wire when_CsrPlugin_l1264_12; + reg execute_CsrPlugin_csr_770; + wire when_CsrPlugin_l1264_13; + reg execute_CsrPlugin_csr_771; + wire when_CsrPlugin_l1264_14; + reg execute_CsrPlugin_csr_256; + wire when_CsrPlugin_l1264_15; + reg execute_CsrPlugin_csr_324; + wire when_CsrPlugin_l1264_16; + reg execute_CsrPlugin_csr_260; + wire when_CsrPlugin_l1264_17; + reg execute_CsrPlugin_csr_261; + wire when_CsrPlugin_l1264_18; + reg execute_CsrPlugin_csr_321; + wire when_CsrPlugin_l1264_19; + reg execute_CsrPlugin_csr_320; + wire when_CsrPlugin_l1264_20; + reg execute_CsrPlugin_csr_322; + wire when_CsrPlugin_l1264_21; + reg execute_CsrPlugin_csr_323; + wire when_CsrPlugin_l1264_22; + reg execute_CsrPlugin_csr_384; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_1; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_2; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_3; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_4; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_5; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_6; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_7; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_8; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_9; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_10; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_11; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_12; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_13; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_14; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_15; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_16; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_17; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_18; + wire when_CsrPlugin_l1297; + wire when_CsrPlugin_l1302; + `ifndef SYNTHESIS + reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_string; + reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_1_string; + reg [39:0] _zz_memory_to_writeBack_ENV_CTRL_string; + reg [39:0] _zz_memory_to_writeBack_ENV_CTRL_1_string; + reg [39:0] _zz_execute_to_memory_ENV_CTRL_string; + reg [39:0] _zz_execute_to_memory_ENV_CTRL_1_string; + reg [39:0] decode_ENV_CTRL_string; + reg [39:0] _zz_decode_ENV_CTRL_string; + reg [39:0] _zz_decode_to_execute_ENV_CTRL_string; + reg [39:0] _zz_decode_to_execute_ENV_CTRL_1_string; + reg [55:0] _zz_execute_to_memory_SHIFT_CTRL_string; + reg [55:0] _zz_execute_to_memory_SHIFT_CTRL_1_string; + reg [55:0] decode_SHIFT_CTRL_string; + reg [55:0] _zz_decode_SHIFT_CTRL_string; + reg [55:0] _zz_decode_to_execute_SHIFT_CTRL_string; + reg [55:0] _zz_decode_to_execute_SHIFT_CTRL_1_string; + reg [23:0] decode_ALU_BITWISE_CTRL_string; + reg [23:0] _zz_decode_ALU_BITWISE_CTRL_string; + reg [23:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_string; + reg [23:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string; + reg [63:0] decode_ALU_CTRL_string; + reg [63:0] _zz_decode_ALU_CTRL_string; + reg [63:0] _zz_decode_to_execute_ALU_CTRL_string; + reg [63:0] _zz_decode_to_execute_ALU_CTRL_1_string; + reg [31:0] execute_BRANCH_CTRL_string; + reg [31:0] _zz_execute_BRANCH_CTRL_string; + reg [39:0] memory_ENV_CTRL_string; + reg [39:0] _zz_memory_ENV_CTRL_string; + reg [39:0] execute_ENV_CTRL_string; + reg [39:0] _zz_execute_ENV_CTRL_string; + reg [39:0] writeBack_ENV_CTRL_string; + reg [39:0] _zz_writeBack_ENV_CTRL_string; + reg [55:0] memory_SHIFT_CTRL_string; + reg [55:0] _zz_memory_SHIFT_CTRL_string; + reg [55:0] execute_SHIFT_CTRL_string; + reg [55:0] _zz_execute_SHIFT_CTRL_string; + reg [23:0] decode_SRC2_CTRL_string; + reg [23:0] _zz_decode_SRC2_CTRL_string; + reg [95:0] decode_SRC1_CTRL_string; + reg [95:0] _zz_decode_SRC1_CTRL_string; + reg [63:0] execute_ALU_CTRL_string; + reg [63:0] _zz_execute_ALU_CTRL_string; + reg [23:0] execute_ALU_BITWISE_CTRL_string; + reg [23:0] _zz_execute_ALU_BITWISE_CTRL_string; + reg [31:0] _zz_decode_BRANCH_CTRL_string; + reg [39:0] _zz_decode_ENV_CTRL_1_string; + reg [55:0] _zz_decode_SHIFT_CTRL_1_string; + reg [23:0] _zz_decode_ALU_BITWISE_CTRL_1_string; + reg [23:0] _zz_decode_SRC2_CTRL_1_string; + reg [63:0] _zz_decode_ALU_CTRL_1_string; + reg [95:0] _zz_decode_SRC1_CTRL_1_string; + reg [31:0] decode_BRANCH_CTRL_string; + reg [31:0] _zz_decode_BRANCH_CTRL_1_string; + reg [95:0] _zz_decode_SRC1_CTRL_2_string; + reg [63:0] _zz_decode_ALU_CTRL_2_string; + reg [23:0] _zz_decode_SRC2_CTRL_2_string; + reg [23:0] _zz_decode_ALU_BITWISE_CTRL_2_string; + reg [55:0] _zz_decode_SHIFT_CTRL_2_string; + reg [39:0] _zz_decode_ENV_CTRL_2_string; + reg [31:0] _zz_decode_BRANCH_CTRL_2_string; + reg [47:0] MmuPlugin_shared_state_1_string; + reg [63:0] decode_to_execute_ALU_CTRL_string; + reg [23:0] decode_to_execute_ALU_BITWISE_CTRL_string; + reg [55:0] decode_to_execute_SHIFT_CTRL_string; + reg [55:0] execute_to_memory_SHIFT_CTRL_string; + reg [39:0] decode_to_execute_ENV_CTRL_string; + reg [39:0] execute_to_memory_ENV_CTRL_string; + reg [39:0] memory_to_writeBack_ENV_CTRL_string; + reg [31:0] decode_to_execute_BRANCH_CTRL_string; + `endif + + reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; + + assign _zz_when = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); + assign _zz_memory_MUL_LOW = ($signed(_zz_memory_MUL_LOW_1) + $signed(_zz_memory_MUL_LOW_5)); + assign _zz_memory_MUL_LOW_1 = ($signed(_zz_memory_MUL_LOW_2) + $signed(_zz_memory_MUL_LOW_3)); + assign _zz_memory_MUL_LOW_2 = 52'h0; + assign _zz_memory_MUL_LOW_4 = {1'b0,memory_MUL_LL}; + assign _zz_memory_MUL_LOW_3 = {{19{_zz_memory_MUL_LOW_4[32]}}, _zz_memory_MUL_LOW_4}; + assign _zz_memory_MUL_LOW_6 = ({16'd0,memory_MUL_LH} <<< 16); + assign _zz_memory_MUL_LOW_5 = {{2{_zz_memory_MUL_LOW_6[49]}}, _zz_memory_MUL_LOW_6}; + assign _zz_memory_MUL_LOW_8 = ({16'd0,memory_MUL_HL} <<< 16); + assign _zz_memory_MUL_LOW_7 = {{2{_zz_memory_MUL_LOW_8[49]}}, _zz_memory_MUL_LOW_8}; + assign _zz_execute_SHIFT_RIGHT_1 = ($signed(_zz_execute_SHIFT_RIGHT_2) >>> execute_FullBarrelShifterPlugin_amplitude); + assign _zz_execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT_1[31 : 0]; + assign _zz_execute_SHIFT_RIGHT_2 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; + assign _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1 = (_zz_IBusCachedPlugin_jump_pcLoad_payload - 5'h01); + assign _zz_IBusCachedPlugin_fetchPc_pc_1 = {IBusCachedPlugin_fetchPc_inc,2'b00}; + assign _zz_IBusCachedPlugin_fetchPc_pc = {29'd0, _zz_IBusCachedPlugin_fetchPc_pc_1}; + assign _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2 = {{_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz__zz_2 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz__zz_4 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz__zz_6 = {{_zz_3,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz__zz_6_1 = {{_zz_5,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); + assign _zz_DBusCachedPlugin_exceptionBus_payload_code_1 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); + assign _zz_writeBack_DBusCachedPlugin_rspRf = (! dataCache_1_io_cpu_writeBack_exclusiveOk); + assign _zz__zz_execute_REGFILE_WRITE_DATA = execute_SRC_LESS; + assign _zz__zz_decode_SRC1_1 = 3'b100; + assign _zz__zz_decode_SRC1_1_1 = decode_INSTRUCTION[19 : 15]; + assign _zz__zz_decode_SRC2_4 = {decode_INSTRUCTION[31 : 25],decode_INSTRUCTION[11 : 7]}; + assign _zz_execute_SrcPlugin_addSub = ($signed(_zz_execute_SrcPlugin_addSub_1) + $signed(_zz_execute_SrcPlugin_addSub_4)); + assign _zz_execute_SrcPlugin_addSub_1 = ($signed(_zz_execute_SrcPlugin_addSub_2) + $signed(_zz_execute_SrcPlugin_addSub_3)); + assign _zz_execute_SrcPlugin_addSub_2 = execute_SRC1; + assign _zz_execute_SrcPlugin_addSub_3 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_execute_SrcPlugin_addSub_4 = (execute_SRC_USE_SUB_LESS ? _zz_execute_SrcPlugin_addSub_5 : _zz_execute_SrcPlugin_addSub_6); + assign _zz_execute_SrcPlugin_addSub_5 = 32'h00000001; + assign _zz_execute_SrcPlugin_addSub_6 = 32'h0; + assign _zz_writeBack_MulPlugin_result = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; + assign _zz_writeBack_MulPlugin_result_1 = ({32'd0,writeBack_MUL_HH} <<< 32); + assign _zz__zz_decode_RS2_2 = writeBack_MUL_LOW[31 : 0]; + assign _zz__zz_decode_RS2_2_1 = writeBack_MulPlugin_result[63 : 32]; + assign _zz_memory_MulDivIterativePlugin_div_counter_valueNext_1 = memory_MulDivIterativePlugin_div_counter_willIncrement; + assign _zz_memory_MulDivIterativePlugin_div_counter_valueNext = {5'd0, _zz_memory_MulDivIterativePlugin_div_counter_valueNext_1}; + assign _zz_memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator = {1'd0, memory_MulDivIterativePlugin_rs2}; + assign _zz_memory_MulDivIterativePlugin_div_stage_0_outRemainder = memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[31:0]; + assign _zz_memory_MulDivIterativePlugin_div_stage_0_outRemainder_1 = memory_MulDivIterativePlugin_div_stage_0_remainderShifted[31:0]; + assign _zz_memory_MulDivIterativePlugin_div_stage_0_outNumerator = {_zz_memory_MulDivIterativePlugin_div_stage_0_remainderShifted,(! memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[32])}; + assign _zz_memory_MulDivIterativePlugin_div_result_1 = _zz_memory_MulDivIterativePlugin_div_result_2; + assign _zz_memory_MulDivIterativePlugin_div_result_2 = _zz_memory_MulDivIterativePlugin_div_result_3; + assign _zz_memory_MulDivIterativePlugin_div_result_3 = ({memory_MulDivIterativePlugin_div_needRevert,(memory_MulDivIterativePlugin_div_needRevert ? (~ _zz_memory_MulDivIterativePlugin_div_result) : _zz_memory_MulDivIterativePlugin_div_result)} + _zz_memory_MulDivIterativePlugin_div_result_4); + assign _zz_memory_MulDivIterativePlugin_div_result_5 = memory_MulDivIterativePlugin_div_needRevert; + assign _zz_memory_MulDivIterativePlugin_div_result_4 = {32'd0, _zz_memory_MulDivIterativePlugin_div_result_5}; + assign _zz_memory_MulDivIterativePlugin_rs1_3 = _zz_memory_MulDivIterativePlugin_rs1; + assign _zz_memory_MulDivIterativePlugin_rs1_2 = {32'd0, _zz_memory_MulDivIterativePlugin_rs1_3}; + assign _zz_memory_MulDivIterativePlugin_rs2_2 = _zz_memory_MulDivIterativePlugin_rs2; + assign _zz_memory_MulDivIterativePlugin_rs2_1 = {31'd0, _zz_memory_MulDivIterativePlugin_rs2_2}; + assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code & (~ _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1)); + assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code - 2'b01); + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_2 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_4 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_6 = {_zz_execute_BranchPlugin_missAlignedTarget_1,execute_INSTRUCTION[31 : 20]}; + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_6_1 = {{_zz_execute_BranchPlugin_missAlignedTarget_3,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_6_2 = {{_zz_execute_BranchPlugin_missAlignedTarget_5,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz__zz_execute_BranchPlugin_branch_src2_2 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz__zz_execute_BranchPlugin_branch_src2_4 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_execute_BranchPlugin_branch_src2_9 = 3'b100; + assign _zz_MmuPlugin_ports_0_entryToReplace_valueNext_1 = MmuPlugin_ports_0_entryToReplace_willIncrement; + assign _zz_MmuPlugin_ports_0_entryToReplace_valueNext = {1'd0, _zz_MmuPlugin_ports_0_entryToReplace_valueNext_1}; + assign _zz_MmuPlugin_ports_1_entryToReplace_valueNext_1 = MmuPlugin_ports_1_entryToReplace_willIncrement; + assign _zz_MmuPlugin_ports_1_entryToReplace_valueNext = {1'd0, _zz_MmuPlugin_ports_1_entryToReplace_valueNext_1}; + assign _zz__zz_MmuPlugin_shared_refills_2 = (_zz_MmuPlugin_shared_refills_1 - 2'b01); + assign _zz_decode_RegFilePlugin_rs1Data = 1'b1; + assign _zz_decode_RegFilePlugin_rs2Data = 1'b1; + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_7 = {_zz_IBusCachedPlugin_jump_pcLoad_payload_3,{_zz_IBusCachedPlugin_jump_pcLoad_payload_5,_zz_IBusCachedPlugin_jump_pcLoad_payload_4}}; + assign _zz_writeBack_DBusCachedPlugin_rspShifted_1 = dataCache_1_io_cpu_writeBack_address[1 : 0]; + assign _zz_writeBack_DBusCachedPlugin_rspShifted_3 = dataCache_1_io_cpu_writeBack_address[1 : 1]; + assign _zz_decode_LEGAL_INSTRUCTION = 32'h0000107f; + assign _zz_decode_LEGAL_INSTRUCTION_1 = (decode_INSTRUCTION & 32'h0000207f); + assign _zz_decode_LEGAL_INSTRUCTION_2 = 32'h00002073; + assign _zz_decode_LEGAL_INSTRUCTION_3 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_decode_LEGAL_INSTRUCTION_4 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013); + assign _zz_decode_LEGAL_INSTRUCTION_5 = {((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_6) == 32'h00000003),{(_zz_decode_LEGAL_INSTRUCTION_7 == _zz_decode_LEGAL_INSTRUCTION_8),{_zz_decode_LEGAL_INSTRUCTION_9,{_zz_decode_LEGAL_INSTRUCTION_10,_zz_decode_LEGAL_INSTRUCTION_11}}}}}}; + assign _zz_decode_LEGAL_INSTRUCTION_6 = 32'h0000505f; + assign _zz_decode_LEGAL_INSTRUCTION_7 = (decode_INSTRUCTION & 32'h0000707b); + assign _zz_decode_LEGAL_INSTRUCTION_8 = 32'h00000063; + assign _zz_decode_LEGAL_INSTRUCTION_9 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_decode_LEGAL_INSTRUCTION_10 = ((decode_INSTRUCTION & 32'h1800707f) == 32'h0000202f); + assign _zz_decode_LEGAL_INSTRUCTION_11 = {((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'he800707f) == 32'h0800202f),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_12) == 32'h0000500f),{(_zz_decode_LEGAL_INSTRUCTION_13 == _zz_decode_LEGAL_INSTRUCTION_14),{_zz_decode_LEGAL_INSTRUCTION_15,{_zz_decode_LEGAL_INSTRUCTION_16,_zz_decode_LEGAL_INSTRUCTION_17}}}}}}; + assign _zz_decode_LEGAL_INSTRUCTION_12 = 32'h01f0707f; + assign _zz_decode_LEGAL_INSTRUCTION_13 = (decode_INSTRUCTION & 32'hbc00707f); + assign _zz_decode_LEGAL_INSTRUCTION_14 = 32'h00005013; + assign _zz_decode_LEGAL_INSTRUCTION_15 = ((decode_INSTRUCTION & 32'hfc00307f) == 32'h00001013); + assign _zz_decode_LEGAL_INSTRUCTION_16 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033); + assign _zz_decode_LEGAL_INSTRUCTION_17 = {((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033),{((decode_INSTRUCTION & 32'hf9f0707f) == 32'h1000202f),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_18) == 32'h12000073),{(_zz_decode_LEGAL_INSTRUCTION_19 == _zz_decode_LEGAL_INSTRUCTION_20),{_zz_decode_LEGAL_INSTRUCTION_21,_zz_decode_LEGAL_INSTRUCTION_22}}}}}; + assign _zz_decode_LEGAL_INSTRUCTION_18 = 32'hfe007fff; + assign _zz_decode_LEGAL_INSTRUCTION_19 = (decode_INSTRUCTION & 32'hdfffffff); + assign _zz_decode_LEGAL_INSTRUCTION_20 = 32'h10200073; + assign _zz_decode_LEGAL_INSTRUCTION_21 = ((decode_INSTRUCTION & 32'hffefffff) == 32'h00000073); + assign _zz_decode_LEGAL_INSTRUCTION_22 = ((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073); + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_4 = decode_INSTRUCTION[31]; + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_5 = decode_INSTRUCTION[31]; + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_6 = decode_INSTRUCTION[7]; + assign _zz__zz_decode_IS_SFENCE_VMA2 = (decode_INSTRUCTION & 32'h0000001c); + assign _zz__zz_decode_IS_SFENCE_VMA2_1 = 32'h00000004; + assign _zz__zz_decode_IS_SFENCE_VMA2_2 = (decode_INSTRUCTION & 32'h00000058); + assign _zz__zz_decode_IS_SFENCE_VMA2_3 = 32'h00000040; + assign _zz__zz_decode_IS_SFENCE_VMA2_4 = ((decode_INSTRUCTION & 32'h10103050) == 32'h00100050); + assign _zz__zz_decode_IS_SFENCE_VMA2_5 = _zz_decode_IS_SFENCE_VMA2_7; + assign _zz__zz_decode_IS_SFENCE_VMA2_6 = 1'b0; + assign _zz__zz_decode_IS_SFENCE_VMA2_7 = (_zz_decode_IS_SFENCE_VMA2_7 != 1'b0); + assign _zz__zz_decode_IS_SFENCE_VMA2_8 = ({_zz__zz_decode_IS_SFENCE_VMA2_9,_zz__zz_decode_IS_SFENCE_VMA2_10} != 2'b00); + assign _zz__zz_decode_IS_SFENCE_VMA2_11 = {(_zz__zz_decode_IS_SFENCE_VMA2_12 != 1'b0),{(_zz__zz_decode_IS_SFENCE_VMA2_13 != _zz__zz_decode_IS_SFENCE_VMA2_18),{_zz__zz_decode_IS_SFENCE_VMA2_19,{_zz__zz_decode_IS_SFENCE_VMA2_20,_zz__zz_decode_IS_SFENCE_VMA2_21}}}}; + assign _zz__zz_decode_IS_SFENCE_VMA2_9 = ((decode_INSTRUCTION & 32'h10103050) == 32'h00000050); + assign _zz__zz_decode_IS_SFENCE_VMA2_10 = ((decode_INSTRUCTION & 32'h12203050) == 32'h10000050); + assign _zz__zz_decode_IS_SFENCE_VMA2_12 = ((decode_INSTRUCTION & 32'h02103050) == 32'h00000050); + assign _zz__zz_decode_IS_SFENCE_VMA2_13 = {(_zz__zz_decode_IS_SFENCE_VMA2_14 == _zz__zz_decode_IS_SFENCE_VMA2_15),(_zz__zz_decode_IS_SFENCE_VMA2_16 == _zz__zz_decode_IS_SFENCE_VMA2_17)}; + assign _zz__zz_decode_IS_SFENCE_VMA2_18 = 2'b00; + assign _zz__zz_decode_IS_SFENCE_VMA2_19 = (_zz_decode_IS_SFENCE_VMA2_6 != 1'b0); + assign _zz__zz_decode_IS_SFENCE_VMA2_20 = (_zz_decode_IS_SFENCE_VMA2_6 != 1'b0); + assign _zz__zz_decode_IS_SFENCE_VMA2_21 = {(_zz__zz_decode_IS_SFENCE_VMA2_22 != _zz__zz_decode_IS_SFENCE_VMA2_23),{_zz__zz_decode_IS_SFENCE_VMA2_24,{_zz__zz_decode_IS_SFENCE_VMA2_26,_zz__zz_decode_IS_SFENCE_VMA2_29}}}; + assign _zz__zz_decode_IS_SFENCE_VMA2_14 = (decode_INSTRUCTION & 32'h00001050); + assign _zz__zz_decode_IS_SFENCE_VMA2_15 = 32'h00001050; + assign _zz__zz_decode_IS_SFENCE_VMA2_16 = (decode_INSTRUCTION & 32'h00002050); + assign _zz__zz_decode_IS_SFENCE_VMA2_17 = 32'h00002050; + assign _zz__zz_decode_IS_SFENCE_VMA2_22 = ((decode_INSTRUCTION & 32'h02004064) == 32'h02004020); + assign _zz__zz_decode_IS_SFENCE_VMA2_23 = 1'b0; + assign _zz__zz_decode_IS_SFENCE_VMA2_24 = (((decode_INSTRUCTION & _zz__zz_decode_IS_SFENCE_VMA2_25) == 32'h02000030) != 1'b0); + assign _zz__zz_decode_IS_SFENCE_VMA2_26 = ({_zz__zz_decode_IS_SFENCE_VMA2_27,_zz__zz_decode_IS_SFENCE_VMA2_28} != 2'b00); + assign _zz__zz_decode_IS_SFENCE_VMA2_29 = {({_zz__zz_decode_IS_SFENCE_VMA2_30,_zz__zz_decode_IS_SFENCE_VMA2_32} != 3'b000),{(_zz__zz_decode_IS_SFENCE_VMA2_37 != _zz__zz_decode_IS_SFENCE_VMA2_39),{_zz__zz_decode_IS_SFENCE_VMA2_40,{_zz__zz_decode_IS_SFENCE_VMA2_43,_zz__zz_decode_IS_SFENCE_VMA2_48}}}}; + assign _zz__zz_decode_IS_SFENCE_VMA2_25 = 32'h02004074; + assign _zz__zz_decode_IS_SFENCE_VMA2_27 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00005010); + assign _zz__zz_decode_IS_SFENCE_VMA2_28 = ((decode_INSTRUCTION & 32'h02007064) == 32'h00005020); + assign _zz__zz_decode_IS_SFENCE_VMA2_30 = ((decode_INSTRUCTION & _zz__zz_decode_IS_SFENCE_VMA2_31) == 32'h40001010); + assign _zz__zz_decode_IS_SFENCE_VMA2_32 = {(_zz__zz_decode_IS_SFENCE_VMA2_33 == _zz__zz_decode_IS_SFENCE_VMA2_34),(_zz__zz_decode_IS_SFENCE_VMA2_35 == _zz__zz_decode_IS_SFENCE_VMA2_36)}; + assign _zz__zz_decode_IS_SFENCE_VMA2_37 = ((decode_INSTRUCTION & _zz__zz_decode_IS_SFENCE_VMA2_38) == 32'h00001000); + assign _zz__zz_decode_IS_SFENCE_VMA2_39 = 1'b0; + assign _zz__zz_decode_IS_SFENCE_VMA2_40 = ((_zz__zz_decode_IS_SFENCE_VMA2_41 == _zz__zz_decode_IS_SFENCE_VMA2_42) != 1'b0); + assign _zz__zz_decode_IS_SFENCE_VMA2_43 = ({_zz__zz_decode_IS_SFENCE_VMA2_44,_zz__zz_decode_IS_SFENCE_VMA2_46} != 2'b00); + assign _zz__zz_decode_IS_SFENCE_VMA2_48 = {(_zz__zz_decode_IS_SFENCE_VMA2_49 != _zz__zz_decode_IS_SFENCE_VMA2_51),{_zz__zz_decode_IS_SFENCE_VMA2_52,{_zz__zz_decode_IS_SFENCE_VMA2_55,_zz__zz_decode_IS_SFENCE_VMA2_65}}}; + assign _zz__zz_decode_IS_SFENCE_VMA2_31 = 32'h40003054; + assign _zz__zz_decode_IS_SFENCE_VMA2_33 = (decode_INSTRUCTION & 32'h00007034); + assign _zz__zz_decode_IS_SFENCE_VMA2_34 = 32'h00001010; + assign _zz__zz_decode_IS_SFENCE_VMA2_35 = (decode_INSTRUCTION & 32'h02007054); + assign _zz__zz_decode_IS_SFENCE_VMA2_36 = 32'h00001010; + assign _zz__zz_decode_IS_SFENCE_VMA2_38 = 32'h00001000; + assign _zz__zz_decode_IS_SFENCE_VMA2_41 = (decode_INSTRUCTION & 32'h00003000); + assign _zz__zz_decode_IS_SFENCE_VMA2_42 = 32'h00002000; + assign _zz__zz_decode_IS_SFENCE_VMA2_44 = ((decode_INSTRUCTION & _zz__zz_decode_IS_SFENCE_VMA2_45) == 32'h00002000); + assign _zz__zz_decode_IS_SFENCE_VMA2_46 = ((decode_INSTRUCTION & _zz__zz_decode_IS_SFENCE_VMA2_47) == 32'h00001000); + assign _zz__zz_decode_IS_SFENCE_VMA2_49 = ((decode_INSTRUCTION & _zz__zz_decode_IS_SFENCE_VMA2_50) == 32'h00004008); + assign _zz__zz_decode_IS_SFENCE_VMA2_51 = 1'b0; + assign _zz__zz_decode_IS_SFENCE_VMA2_52 = ((_zz__zz_decode_IS_SFENCE_VMA2_53 == _zz__zz_decode_IS_SFENCE_VMA2_54) != 1'b0); + assign _zz__zz_decode_IS_SFENCE_VMA2_55 = ({_zz__zz_decode_IS_SFENCE_VMA2_56,_zz__zz_decode_IS_SFENCE_VMA2_58} != 4'b0000); + assign _zz__zz_decode_IS_SFENCE_VMA2_65 = {(_zz__zz_decode_IS_SFENCE_VMA2_66 != _zz__zz_decode_IS_SFENCE_VMA2_68),{_zz__zz_decode_IS_SFENCE_VMA2_69,{_zz__zz_decode_IS_SFENCE_VMA2_72,_zz__zz_decode_IS_SFENCE_VMA2_91}}}; + assign _zz__zz_decode_IS_SFENCE_VMA2_45 = 32'h00002010; + assign _zz__zz_decode_IS_SFENCE_VMA2_47 = 32'h00005000; + assign _zz__zz_decode_IS_SFENCE_VMA2_50 = 32'h00004048; + assign _zz__zz_decode_IS_SFENCE_VMA2_53 = (decode_INSTRUCTION & 32'h00000064); + assign _zz__zz_decode_IS_SFENCE_VMA2_54 = 32'h00000024; + assign _zz__zz_decode_IS_SFENCE_VMA2_56 = ((decode_INSTRUCTION & _zz__zz_decode_IS_SFENCE_VMA2_57) == 32'h00000020); + assign _zz__zz_decode_IS_SFENCE_VMA2_58 = {(_zz__zz_decode_IS_SFENCE_VMA2_59 == _zz__zz_decode_IS_SFENCE_VMA2_60),{_zz__zz_decode_IS_SFENCE_VMA2_61,_zz__zz_decode_IS_SFENCE_VMA2_63}}; + assign _zz__zz_decode_IS_SFENCE_VMA2_66 = ((decode_INSTRUCTION & _zz__zz_decode_IS_SFENCE_VMA2_67) == 32'h00000008); + assign _zz__zz_decode_IS_SFENCE_VMA2_68 = 1'b0; + assign _zz__zz_decode_IS_SFENCE_VMA2_69 = ((_zz__zz_decode_IS_SFENCE_VMA2_70 == _zz__zz_decode_IS_SFENCE_VMA2_71) != 1'b0); + assign _zz__zz_decode_IS_SFENCE_VMA2_72 = ({_zz__zz_decode_IS_SFENCE_VMA2_73,_zz__zz_decode_IS_SFENCE_VMA2_76} != 6'h0); + assign _zz__zz_decode_IS_SFENCE_VMA2_91 = {(_zz__zz_decode_IS_SFENCE_VMA2_92 != _zz__zz_decode_IS_SFENCE_VMA2_101),{_zz__zz_decode_IS_SFENCE_VMA2_102,{_zz__zz_decode_IS_SFENCE_VMA2_115,_zz__zz_decode_IS_SFENCE_VMA2_130}}}; + assign _zz__zz_decode_IS_SFENCE_VMA2_57 = 32'h00000034; + assign _zz__zz_decode_IS_SFENCE_VMA2_59 = (decode_INSTRUCTION & 32'h00000064); + assign _zz__zz_decode_IS_SFENCE_VMA2_60 = 32'h00000020; + assign _zz__zz_decode_IS_SFENCE_VMA2_61 = ((decode_INSTRUCTION & _zz__zz_decode_IS_SFENCE_VMA2_62) == 32'h08000020); + assign _zz__zz_decode_IS_SFENCE_VMA2_63 = ((decode_INSTRUCTION & _zz__zz_decode_IS_SFENCE_VMA2_64) == 32'h00000020); + assign _zz__zz_decode_IS_SFENCE_VMA2_67 = 32'h10000008; + assign _zz__zz_decode_IS_SFENCE_VMA2_70 = (decode_INSTRUCTION & 32'h10000008); + assign _zz__zz_decode_IS_SFENCE_VMA2_71 = 32'h10000008; + assign _zz__zz_decode_IS_SFENCE_VMA2_73 = (_zz__zz_decode_IS_SFENCE_VMA2_74 == _zz__zz_decode_IS_SFENCE_VMA2_75); + assign _zz__zz_decode_IS_SFENCE_VMA2_76 = {_zz__zz_decode_IS_SFENCE_VMA2_77,{_zz__zz_decode_IS_SFENCE_VMA2_79,_zz__zz_decode_IS_SFENCE_VMA2_82}}; + assign _zz__zz_decode_IS_SFENCE_VMA2_92 = {_zz__zz_decode_IS_SFENCE_VMA2_93,{_zz__zz_decode_IS_SFENCE_VMA2_95,_zz__zz_decode_IS_SFENCE_VMA2_98}}; + assign _zz__zz_decode_IS_SFENCE_VMA2_101 = 3'b000; + assign _zz__zz_decode_IS_SFENCE_VMA2_102 = ({_zz__zz_decode_IS_SFENCE_VMA2_103,_zz__zz_decode_IS_SFENCE_VMA2_106} != 5'h0); + assign _zz__zz_decode_IS_SFENCE_VMA2_115 = (_zz__zz_decode_IS_SFENCE_VMA2_116 != _zz__zz_decode_IS_SFENCE_VMA2_129); + assign _zz__zz_decode_IS_SFENCE_VMA2_130 = {_zz__zz_decode_IS_SFENCE_VMA2_131,{_zz__zz_decode_IS_SFENCE_VMA2_148,_zz__zz_decode_IS_SFENCE_VMA2_153}}; + assign _zz__zz_decode_IS_SFENCE_VMA2_62 = 32'h08000070; + assign _zz__zz_decode_IS_SFENCE_VMA2_64 = 32'h10000070; + assign _zz__zz_decode_IS_SFENCE_VMA2_74 = (decode_INSTRUCTION & 32'h00002040); + assign _zz__zz_decode_IS_SFENCE_VMA2_75 = 32'h00002040; + assign _zz__zz_decode_IS_SFENCE_VMA2_77 = ((decode_INSTRUCTION & _zz__zz_decode_IS_SFENCE_VMA2_78) == 32'h00001040); + assign _zz__zz_decode_IS_SFENCE_VMA2_79 = (_zz__zz_decode_IS_SFENCE_VMA2_80 == _zz__zz_decode_IS_SFENCE_VMA2_81); + assign _zz__zz_decode_IS_SFENCE_VMA2_82 = {_zz__zz_decode_IS_SFENCE_VMA2_83,{_zz__zz_decode_IS_SFENCE_VMA2_85,_zz__zz_decode_IS_SFENCE_VMA2_88}}; + assign _zz__zz_decode_IS_SFENCE_VMA2_93 = ((decode_INSTRUCTION & _zz__zz_decode_IS_SFENCE_VMA2_94) == 32'h08000020); + assign _zz__zz_decode_IS_SFENCE_VMA2_95 = (_zz__zz_decode_IS_SFENCE_VMA2_96 == _zz__zz_decode_IS_SFENCE_VMA2_97); + assign _zz__zz_decode_IS_SFENCE_VMA2_98 = (_zz__zz_decode_IS_SFENCE_VMA2_99 == _zz__zz_decode_IS_SFENCE_VMA2_100); + assign _zz__zz_decode_IS_SFENCE_VMA2_103 = (_zz__zz_decode_IS_SFENCE_VMA2_104 == _zz__zz_decode_IS_SFENCE_VMA2_105); + assign _zz__zz_decode_IS_SFENCE_VMA2_106 = {_zz__zz_decode_IS_SFENCE_VMA2_107,{_zz__zz_decode_IS_SFENCE_VMA2_109,_zz__zz_decode_IS_SFENCE_VMA2_112}}; + assign _zz__zz_decode_IS_SFENCE_VMA2_116 = {_zz_decode_IS_SFENCE_VMA2_5,{_zz__zz_decode_IS_SFENCE_VMA2_117,_zz__zz_decode_IS_SFENCE_VMA2_120}}; + assign _zz__zz_decode_IS_SFENCE_VMA2_129 = 5'h0; + assign _zz__zz_decode_IS_SFENCE_VMA2_131 = ({_zz__zz_decode_IS_SFENCE_VMA2_132,_zz__zz_decode_IS_SFENCE_VMA2_133} != 7'h0); + assign _zz__zz_decode_IS_SFENCE_VMA2_148 = (_zz__zz_decode_IS_SFENCE_VMA2_149 != _zz__zz_decode_IS_SFENCE_VMA2_152); + assign _zz__zz_decode_IS_SFENCE_VMA2_153 = {_zz__zz_decode_IS_SFENCE_VMA2_154,{_zz__zz_decode_IS_SFENCE_VMA2_159,_zz__zz_decode_IS_SFENCE_VMA2_164}}; + assign _zz__zz_decode_IS_SFENCE_VMA2_78 = 32'h00001040; + assign _zz__zz_decode_IS_SFENCE_VMA2_80 = (decode_INSTRUCTION & 32'h00000050); + assign _zz__zz_decode_IS_SFENCE_VMA2_81 = 32'h00000040; + assign _zz__zz_decode_IS_SFENCE_VMA2_83 = ((decode_INSTRUCTION & _zz__zz_decode_IS_SFENCE_VMA2_84) == 32'h00000040); + assign _zz__zz_decode_IS_SFENCE_VMA2_85 = (_zz__zz_decode_IS_SFENCE_VMA2_86 == _zz__zz_decode_IS_SFENCE_VMA2_87); + assign _zz__zz_decode_IS_SFENCE_VMA2_88 = (_zz__zz_decode_IS_SFENCE_VMA2_89 == _zz__zz_decode_IS_SFENCE_VMA2_90); + assign _zz__zz_decode_IS_SFENCE_VMA2_94 = 32'h08000020; + assign _zz__zz_decode_IS_SFENCE_VMA2_96 = (decode_INSTRUCTION & 32'h10000020); + assign _zz__zz_decode_IS_SFENCE_VMA2_97 = 32'h00000020; + assign _zz__zz_decode_IS_SFENCE_VMA2_99 = (decode_INSTRUCTION & 32'h00000028); + assign _zz__zz_decode_IS_SFENCE_VMA2_100 = 32'h00000020; + assign _zz__zz_decode_IS_SFENCE_VMA2_104 = (decode_INSTRUCTION & 32'h00000040); + assign _zz__zz_decode_IS_SFENCE_VMA2_105 = 32'h00000040; + assign _zz__zz_decode_IS_SFENCE_VMA2_107 = ((decode_INSTRUCTION & _zz__zz_decode_IS_SFENCE_VMA2_108) == 32'h00004020); + assign _zz__zz_decode_IS_SFENCE_VMA2_109 = (_zz__zz_decode_IS_SFENCE_VMA2_110 == _zz__zz_decode_IS_SFENCE_VMA2_111); + assign _zz__zz_decode_IS_SFENCE_VMA2_112 = {_zz_decode_IS_SFENCE_VMA2_5,_zz__zz_decode_IS_SFENCE_VMA2_113}; + assign _zz__zz_decode_IS_SFENCE_VMA2_117 = (_zz__zz_decode_IS_SFENCE_VMA2_118 == _zz__zz_decode_IS_SFENCE_VMA2_119); + assign _zz__zz_decode_IS_SFENCE_VMA2_120 = {_zz__zz_decode_IS_SFENCE_VMA2_121,{_zz__zz_decode_IS_SFENCE_VMA2_123,_zz__zz_decode_IS_SFENCE_VMA2_126}}; + assign _zz__zz_decode_IS_SFENCE_VMA2_132 = _zz_decode_IS_SFENCE_VMA2_2; + assign _zz__zz_decode_IS_SFENCE_VMA2_133 = {_zz__zz_decode_IS_SFENCE_VMA2_134,{_zz__zz_decode_IS_SFENCE_VMA2_136,_zz__zz_decode_IS_SFENCE_VMA2_139}}; + assign _zz__zz_decode_IS_SFENCE_VMA2_149 = {_zz_decode_IS_SFENCE_VMA2_4,_zz__zz_decode_IS_SFENCE_VMA2_150}; + assign _zz__zz_decode_IS_SFENCE_VMA2_152 = 2'b00; + assign _zz__zz_decode_IS_SFENCE_VMA2_154 = ({_zz__zz_decode_IS_SFENCE_VMA2_155,_zz__zz_decode_IS_SFENCE_VMA2_156} != 2'b00); + assign _zz__zz_decode_IS_SFENCE_VMA2_159 = (_zz__zz_decode_IS_SFENCE_VMA2_160 != _zz__zz_decode_IS_SFENCE_VMA2_163); + assign _zz__zz_decode_IS_SFENCE_VMA2_164 = {_zz__zz_decode_IS_SFENCE_VMA2_165,{_zz__zz_decode_IS_SFENCE_VMA2_168,_zz__zz_decode_IS_SFENCE_VMA2_181}}; + assign _zz__zz_decode_IS_SFENCE_VMA2_84 = 32'h02100040; + assign _zz__zz_decode_IS_SFENCE_VMA2_86 = (decode_INSTRUCTION & 32'h00000038); + assign _zz__zz_decode_IS_SFENCE_VMA2_87 = 32'h0; + assign _zz__zz_decode_IS_SFENCE_VMA2_89 = (decode_INSTRUCTION & 32'h18002008); + assign _zz__zz_decode_IS_SFENCE_VMA2_90 = 32'h10002008; + assign _zz__zz_decode_IS_SFENCE_VMA2_108 = 32'h00004020; + assign _zz__zz_decode_IS_SFENCE_VMA2_110 = (decode_INSTRUCTION & 32'h00000030); + assign _zz__zz_decode_IS_SFENCE_VMA2_111 = 32'h00000010; + assign _zz__zz_decode_IS_SFENCE_VMA2_113 = ((decode_INSTRUCTION & _zz__zz_decode_IS_SFENCE_VMA2_114) == 32'h00000020); + assign _zz__zz_decode_IS_SFENCE_VMA2_118 = (decode_INSTRUCTION & 32'h00002030); + assign _zz__zz_decode_IS_SFENCE_VMA2_119 = 32'h00002010; + assign _zz__zz_decode_IS_SFENCE_VMA2_121 = ((decode_INSTRUCTION & _zz__zz_decode_IS_SFENCE_VMA2_122) == 32'h00000010); + assign _zz__zz_decode_IS_SFENCE_VMA2_123 = (_zz__zz_decode_IS_SFENCE_VMA2_124 == _zz__zz_decode_IS_SFENCE_VMA2_125); + assign _zz__zz_decode_IS_SFENCE_VMA2_126 = (_zz__zz_decode_IS_SFENCE_VMA2_127 == _zz__zz_decode_IS_SFENCE_VMA2_128); + assign _zz__zz_decode_IS_SFENCE_VMA2_134 = ((decode_INSTRUCTION & _zz__zz_decode_IS_SFENCE_VMA2_135) == 32'h00001010); + assign _zz__zz_decode_IS_SFENCE_VMA2_136 = (_zz__zz_decode_IS_SFENCE_VMA2_137 == _zz__zz_decode_IS_SFENCE_VMA2_138); + assign _zz__zz_decode_IS_SFENCE_VMA2_139 = {_zz__zz_decode_IS_SFENCE_VMA2_140,{_zz__zz_decode_IS_SFENCE_VMA2_142,_zz__zz_decode_IS_SFENCE_VMA2_145}}; + assign _zz__zz_decode_IS_SFENCE_VMA2_150 = ((decode_INSTRUCTION & _zz__zz_decode_IS_SFENCE_VMA2_151) == 32'h00000020); + assign _zz__zz_decode_IS_SFENCE_VMA2_155 = _zz_decode_IS_SFENCE_VMA2_4; + assign _zz__zz_decode_IS_SFENCE_VMA2_156 = (_zz__zz_decode_IS_SFENCE_VMA2_157 == _zz__zz_decode_IS_SFENCE_VMA2_158); + assign _zz__zz_decode_IS_SFENCE_VMA2_160 = (_zz__zz_decode_IS_SFENCE_VMA2_161 == _zz__zz_decode_IS_SFENCE_VMA2_162); + assign _zz__zz_decode_IS_SFENCE_VMA2_163 = 1'b0; + assign _zz__zz_decode_IS_SFENCE_VMA2_165 = (_zz__zz_decode_IS_SFENCE_VMA2_166 != 1'b0); + assign _zz__zz_decode_IS_SFENCE_VMA2_168 = (_zz__zz_decode_IS_SFENCE_VMA2_169 != _zz__zz_decode_IS_SFENCE_VMA2_180); + assign _zz__zz_decode_IS_SFENCE_VMA2_181 = {_zz__zz_decode_IS_SFENCE_VMA2_182,{_zz__zz_decode_IS_SFENCE_VMA2_187,_zz__zz_decode_IS_SFENCE_VMA2_195}}; + assign _zz__zz_decode_IS_SFENCE_VMA2_114 = 32'h02000028; + assign _zz__zz_decode_IS_SFENCE_VMA2_122 = 32'h00001030; + assign _zz__zz_decode_IS_SFENCE_VMA2_124 = (decode_INSTRUCTION & 32'h02003020); + assign _zz__zz_decode_IS_SFENCE_VMA2_125 = 32'h00000020; + assign _zz__zz_decode_IS_SFENCE_VMA2_127 = (decode_INSTRUCTION & 32'h02002068); + assign _zz__zz_decode_IS_SFENCE_VMA2_128 = 32'h00002020; + assign _zz__zz_decode_IS_SFENCE_VMA2_135 = 32'h00001010; + assign _zz__zz_decode_IS_SFENCE_VMA2_137 = (decode_INSTRUCTION & 32'h00002010); + assign _zz__zz_decode_IS_SFENCE_VMA2_138 = 32'h00002010; + assign _zz__zz_decode_IS_SFENCE_VMA2_140 = ((decode_INSTRUCTION & _zz__zz_decode_IS_SFENCE_VMA2_141) == 32'h00002008); + assign _zz__zz_decode_IS_SFENCE_VMA2_142 = (_zz__zz_decode_IS_SFENCE_VMA2_143 == _zz__zz_decode_IS_SFENCE_VMA2_144); + assign _zz__zz_decode_IS_SFENCE_VMA2_145 = {_zz_decode_IS_SFENCE_VMA2_5,_zz__zz_decode_IS_SFENCE_VMA2_146}; + assign _zz__zz_decode_IS_SFENCE_VMA2_151 = 32'h00000070; + assign _zz__zz_decode_IS_SFENCE_VMA2_157 = (decode_INSTRUCTION & 32'h00000020); + assign _zz__zz_decode_IS_SFENCE_VMA2_158 = 32'h0; + assign _zz__zz_decode_IS_SFENCE_VMA2_161 = (decode_INSTRUCTION & 32'h00004014); + assign _zz__zz_decode_IS_SFENCE_VMA2_162 = 32'h00004010; + assign _zz__zz_decode_IS_SFENCE_VMA2_166 = ((decode_INSTRUCTION & _zz__zz_decode_IS_SFENCE_VMA2_167) == 32'h00002010); + assign _zz__zz_decode_IS_SFENCE_VMA2_169 = {_zz__zz_decode_IS_SFENCE_VMA2_170,{_zz__zz_decode_IS_SFENCE_VMA2_172,_zz__zz_decode_IS_SFENCE_VMA2_175}}; + assign _zz__zz_decode_IS_SFENCE_VMA2_180 = 5'h0; + assign _zz__zz_decode_IS_SFENCE_VMA2_182 = ({_zz__zz_decode_IS_SFENCE_VMA2_183,_zz__zz_decode_IS_SFENCE_VMA2_184} != 2'b00); + assign _zz__zz_decode_IS_SFENCE_VMA2_187 = (_zz__zz_decode_IS_SFENCE_VMA2_188 != _zz__zz_decode_IS_SFENCE_VMA2_194); + assign _zz__zz_decode_IS_SFENCE_VMA2_195 = {_zz__zz_decode_IS_SFENCE_VMA2_196,{_zz__zz_decode_IS_SFENCE_VMA2_201,_zz__zz_decode_IS_SFENCE_VMA2_206}}; + assign _zz__zz_decode_IS_SFENCE_VMA2_141 = 32'h00002008; + assign _zz__zz_decode_IS_SFENCE_VMA2_143 = (decode_INSTRUCTION & 32'h00000050); + assign _zz__zz_decode_IS_SFENCE_VMA2_144 = 32'h00000010; + assign _zz__zz_decode_IS_SFENCE_VMA2_146 = ((decode_INSTRUCTION & _zz__zz_decode_IS_SFENCE_VMA2_147) == 32'h0); + assign _zz__zz_decode_IS_SFENCE_VMA2_167 = 32'h00006014; + assign _zz__zz_decode_IS_SFENCE_VMA2_170 = ((decode_INSTRUCTION & _zz__zz_decode_IS_SFENCE_VMA2_171) == 32'h0); + assign _zz__zz_decode_IS_SFENCE_VMA2_172 = (_zz__zz_decode_IS_SFENCE_VMA2_173 == _zz__zz_decode_IS_SFENCE_VMA2_174); + assign _zz__zz_decode_IS_SFENCE_VMA2_175 = {_zz__zz_decode_IS_SFENCE_VMA2_176,{_zz__zz_decode_IS_SFENCE_VMA2_177,_zz__zz_decode_IS_SFENCE_VMA2_179}}; + assign _zz__zz_decode_IS_SFENCE_VMA2_183 = _zz_decode_IS_SFENCE_VMA2_3; + assign _zz__zz_decode_IS_SFENCE_VMA2_184 = (_zz__zz_decode_IS_SFENCE_VMA2_185 == _zz__zz_decode_IS_SFENCE_VMA2_186); + assign _zz__zz_decode_IS_SFENCE_VMA2_188 = {_zz__zz_decode_IS_SFENCE_VMA2_189,{_zz__zz_decode_IS_SFENCE_VMA2_190,_zz__zz_decode_IS_SFENCE_VMA2_192}}; + assign _zz__zz_decode_IS_SFENCE_VMA2_194 = 3'b000; + assign _zz__zz_decode_IS_SFENCE_VMA2_196 = ({_zz__zz_decode_IS_SFENCE_VMA2_197,_zz__zz_decode_IS_SFENCE_VMA2_198} != 3'b000); + assign _zz__zz_decode_IS_SFENCE_VMA2_201 = (_zz__zz_decode_IS_SFENCE_VMA2_202 != _zz__zz_decode_IS_SFENCE_VMA2_205); + assign _zz__zz_decode_IS_SFENCE_VMA2_206 = (_zz__zz_decode_IS_SFENCE_VMA2_207 != _zz__zz_decode_IS_SFENCE_VMA2_209); + assign _zz__zz_decode_IS_SFENCE_VMA2_147 = 32'h00000028; + assign _zz__zz_decode_IS_SFENCE_VMA2_171 = 32'h00000044; + assign _zz__zz_decode_IS_SFENCE_VMA2_173 = (decode_INSTRUCTION & 32'h00000018); + assign _zz__zz_decode_IS_SFENCE_VMA2_174 = 32'h0; + assign _zz__zz_decode_IS_SFENCE_VMA2_176 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); + assign _zz__zz_decode_IS_SFENCE_VMA2_177 = ((decode_INSTRUCTION & _zz__zz_decode_IS_SFENCE_VMA2_178) == 32'h00001000); + assign _zz__zz_decode_IS_SFENCE_VMA2_179 = _zz_decode_IS_SFENCE_VMA2_3; + assign _zz__zz_decode_IS_SFENCE_VMA2_185 = (decode_INSTRUCTION & 32'h00000058); + assign _zz__zz_decode_IS_SFENCE_VMA2_186 = 32'h0; + assign _zz__zz_decode_IS_SFENCE_VMA2_189 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040); + assign _zz__zz_decode_IS_SFENCE_VMA2_190 = ((decode_INSTRUCTION & _zz__zz_decode_IS_SFENCE_VMA2_191) == 32'h00002010); + assign _zz__zz_decode_IS_SFENCE_VMA2_192 = ((decode_INSTRUCTION & _zz__zz_decode_IS_SFENCE_VMA2_193) == 32'h40000030); + assign _zz__zz_decode_IS_SFENCE_VMA2_197 = _zz_decode_IS_SFENCE_VMA2_2; + assign _zz__zz_decode_IS_SFENCE_VMA2_198 = {_zz_decode_IS_SFENCE_VMA2_1,(_zz__zz_decode_IS_SFENCE_VMA2_199 == _zz__zz_decode_IS_SFENCE_VMA2_200)}; + assign _zz__zz_decode_IS_SFENCE_VMA2_202 = {_zz_decode_IS_SFENCE_VMA2_1,(_zz__zz_decode_IS_SFENCE_VMA2_203 == _zz__zz_decode_IS_SFENCE_VMA2_204)}; + assign _zz__zz_decode_IS_SFENCE_VMA2_205 = 2'b00; + assign _zz__zz_decode_IS_SFENCE_VMA2_207 = ((decode_INSTRUCTION & _zz__zz_decode_IS_SFENCE_VMA2_208) == 32'h00001008); + assign _zz__zz_decode_IS_SFENCE_VMA2_209 = 1'b0; + assign _zz__zz_decode_IS_SFENCE_VMA2_178 = 32'h00005004; + assign _zz__zz_decode_IS_SFENCE_VMA2_191 = 32'h00002014; + assign _zz__zz_decode_IS_SFENCE_VMA2_193 = 32'h40000034; + assign _zz__zz_decode_IS_SFENCE_VMA2_199 = (decode_INSTRUCTION & 32'h00002014); + assign _zz__zz_decode_IS_SFENCE_VMA2_200 = 32'h00000004; + assign _zz__zz_decode_IS_SFENCE_VMA2_203 = (decode_INSTRUCTION & 32'h0000004c); + assign _zz__zz_decode_IS_SFENCE_VMA2_204 = 32'h00000004; + assign _zz__zz_decode_IS_SFENCE_VMA2_208 = 32'h00005048; + assign _zz_execute_BranchPlugin_branch_src2_6 = execute_INSTRUCTION[31]; + assign _zz_execute_BranchPlugin_branch_src2_7 = execute_INSTRUCTION[31]; + assign _zz_execute_BranchPlugin_branch_src2_8 = execute_INSTRUCTION[7]; + assign _zz_MmuPlugin_ports_0_cacheHitsCalc = IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22]; + assign _zz_MmuPlugin_ports_0_cacheHitsCalc_1 = IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]; + assign _zz_MmuPlugin_ports_0_cacheHitsCalc_2 = (MmuPlugin_ports_0_cache_1_virtualAddress_1 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22]); + assign _zz_MmuPlugin_ports_0_cacheHitsCalc_3 = (MmuPlugin_ports_0_cache_1_virtualAddress_0 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]); + assign _zz_MmuPlugin_ports_0_cacheHitsCalc_4 = (MmuPlugin_ports_0_cache_0_virtualAddress_1 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22]); + assign _zz_MmuPlugin_ports_0_cacheHitsCalc_5 = (MmuPlugin_ports_0_cache_0_virtualAddress_0 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]); + assign _zz_MmuPlugin_ports_1_cacheHitsCalc = DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22]; + assign _zz_MmuPlugin_ports_1_cacheHitsCalc_1 = DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]; + assign _zz_MmuPlugin_ports_1_cacheHitsCalc_2 = (MmuPlugin_ports_1_cache_1_virtualAddress_1 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22]); + assign _zz_MmuPlugin_ports_1_cacheHitsCalc_3 = (MmuPlugin_ports_1_cache_1_virtualAddress_0 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]); + assign _zz_MmuPlugin_ports_1_cacheHitsCalc_4 = (MmuPlugin_ports_1_cache_0_virtualAddress_1 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22]); + assign _zz_MmuPlugin_ports_1_cacheHitsCalc_5 = (MmuPlugin_ports_1_cache_0_virtualAddress_0 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]); + assign _zz_CsrPlugin_csrMapping_readDataInit_19 = 32'h0; + always @(posedge clk) begin + if(_zz_decode_RegFilePlugin_rs1Data) begin + _zz_RegFilePlugin_regFile_port0 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + end + end + + always @(posedge clk) begin + if(_zz_decode_RegFilePlugin_rs2Data) begin + _zz_RegFilePlugin_regFile_port1 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + end + end + + always @(posedge clk) begin + if(_zz_1) begin + RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; + end + end + + InstructionCache IBusCachedPlugin_cache ( + .io_flush (IBusCachedPlugin_cache_io_flush ), //i + .io_cpu_prefetch_isValid (IBusCachedPlugin_cache_io_cpu_prefetch_isValid ), //i + .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o + .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload ), //i + .io_cpu_fetch_isValid (IBusCachedPlugin_cache_io_cpu_fetch_isValid ), //i + .io_cpu_fetch_isStuck (IBusCachedPlugin_cache_io_cpu_fetch_isStuck ), //i + .io_cpu_fetch_isRemoved (IBusCachedPlugin_cache_io_cpu_fetch_isRemoved ), //i + .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload ), //i + .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data ), //o + .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress ), //i + .io_cpu_fetch_mmuRsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i + .io_cpu_fetch_mmuRsp_isPaging (IBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_fetch_mmuRsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_fetch_mmuRsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_fetch_mmuRsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_fetch_mmuRsp_exception (IBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_fetch_mmuRsp_ways_0_sel (IBusCachedPlugin_mmuBus_rsp_ways_0_sel ), //i + .io_cpu_fetch_mmuRsp_ways_0_physical (IBusCachedPlugin_mmuBus_rsp_ways_0_physical ), //i + .io_cpu_fetch_mmuRsp_ways_1_sel (IBusCachedPlugin_mmuBus_rsp_ways_1_sel ), //i + .io_cpu_fetch_mmuRsp_ways_1_physical (IBusCachedPlugin_mmuBus_rsp_ways_1_physical ), //i + .io_cpu_fetch_mmuRsp_ways_2_sel (IBusCachedPlugin_mmuBus_rsp_ways_2_sel ), //i + .io_cpu_fetch_mmuRsp_ways_2_physical (IBusCachedPlugin_mmuBus_rsp_ways_2_physical ), //i + .io_cpu_fetch_mmuRsp_ways_3_sel (IBusCachedPlugin_mmuBus_rsp_ways_3_sel ), //i + .io_cpu_fetch_mmuRsp_ways_3_physical (IBusCachedPlugin_mmuBus_rsp_ways_3_physical ), //i + .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress ), //o + .io_cpu_decode_isValid (IBusCachedPlugin_cache_io_cpu_decode_isValid ), //i + .io_cpu_decode_isStuck (IBusCachedPlugin_cache_io_cpu_decode_isStuck ), //i + .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload ), //i + .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress ), //o + .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data ), //o + .io_cpu_decode_cacheMiss (IBusCachedPlugin_cache_io_cpu_decode_cacheMiss ), //o + .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o + .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o + .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o + .io_cpu_decode_isUser (IBusCachedPlugin_cache_io_cpu_decode_isUser ), //i + .io_cpu_fill_valid (IBusCachedPlugin_cache_io_cpu_fill_valid ), //i + .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress ), //i + .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (iBus_cmd_ready ), //i + .io_mem_cmd_payload_address (IBusCachedPlugin_cache_io_mem_cmd_payload_address ), //o + .io_mem_cmd_payload_size (IBusCachedPlugin_cache_io_mem_cmd_payload_size ), //o + .io_mem_rsp_valid (iBus_rsp_valid ), //i + .io_mem_rsp_payload_data (iBus_rsp_payload_data ), //i + .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i + ._zz_when_Fetcher_l398 (switch_Fetcher_l362 ), //i + ._zz_io_cpu_fetch_data_regNextWhen (IBusCachedPlugin_injectionPort_payload ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + DataCache dataCache_1 ( + .io_cpu_execute_isValid (dataCache_1_io_cpu_execute_isValid ), //i + .io_cpu_execute_address (dataCache_1_io_cpu_execute_address ), //i + .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o + .io_cpu_execute_args_wr (dataCache_1_io_cpu_execute_args_wr ), //i + .io_cpu_execute_args_size (dataCache_1_io_cpu_execute_args_size ), //i + .io_cpu_execute_args_isLrsc (dataCache_1_io_cpu_execute_args_isLrsc ), //i + .io_cpu_execute_args_isAmo (execute_MEMORY_AMO ), //i + .io_cpu_execute_args_amoCtrl_swap (dataCache_1_io_cpu_execute_args_amoCtrl_swap ), //i + .io_cpu_execute_args_amoCtrl_alu (dataCache_1_io_cpu_execute_args_amoCtrl_alu ), //i + .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i + .io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o + .io_cpu_memory_isValid (dataCache_1_io_cpu_memory_isValid ), //i + .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i + .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o + .io_cpu_memory_address (dataCache_1_io_cpu_memory_address ), //i + .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress ), //i + .io_cpu_memory_mmuRsp_isIoAccess (dataCache_1_io_cpu_memory_mmuRsp_isIoAccess ), //i + .io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_memory_mmuRsp_allowExecute (DBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_memory_mmuRsp_ways_0_sel (DBusCachedPlugin_mmuBus_rsp_ways_0_sel ), //i + .io_cpu_memory_mmuRsp_ways_0_physical (DBusCachedPlugin_mmuBus_rsp_ways_0_physical ), //i + .io_cpu_memory_mmuRsp_ways_1_sel (DBusCachedPlugin_mmuBus_rsp_ways_1_sel ), //i + .io_cpu_memory_mmuRsp_ways_1_physical (DBusCachedPlugin_mmuBus_rsp_ways_1_physical ), //i + .io_cpu_memory_mmuRsp_ways_2_sel (DBusCachedPlugin_mmuBus_rsp_ways_2_sel ), //i + .io_cpu_memory_mmuRsp_ways_2_physical (DBusCachedPlugin_mmuBus_rsp_ways_2_physical ), //i + .io_cpu_memory_mmuRsp_ways_3_sel (DBusCachedPlugin_mmuBus_rsp_ways_3_sel ), //i + .io_cpu_memory_mmuRsp_ways_3_physical (DBusCachedPlugin_mmuBus_rsp_ways_3_physical ), //i + .io_cpu_writeBack_isValid (dataCache_1_io_cpu_writeBack_isValid ), //i + .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i + .io_cpu_writeBack_isUser (dataCache_1_io_cpu_writeBack_isUser ), //i + .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o + .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o + .io_cpu_writeBack_storeData (dataCache_1_io_cpu_writeBack_storeData ), //i + .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data ), //o + .io_cpu_writeBack_address (dataCache_1_io_cpu_writeBack_address ), //i + .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o + .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o + .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o + .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o + .io_cpu_writeBack_fence_SW (dataCache_1_io_cpu_writeBack_fence_SW ), //i + .io_cpu_writeBack_fence_SR (dataCache_1_io_cpu_writeBack_fence_SR ), //i + .io_cpu_writeBack_fence_SO (dataCache_1_io_cpu_writeBack_fence_SO ), //i + .io_cpu_writeBack_fence_SI (dataCache_1_io_cpu_writeBack_fence_SI ), //i + .io_cpu_writeBack_fence_PW (dataCache_1_io_cpu_writeBack_fence_PW ), //i + .io_cpu_writeBack_fence_PR (dataCache_1_io_cpu_writeBack_fence_PR ), //i + .io_cpu_writeBack_fence_PO (dataCache_1_io_cpu_writeBack_fence_PO ), //i + .io_cpu_writeBack_fence_PI (dataCache_1_io_cpu_writeBack_fence_PI ), //i + .io_cpu_writeBack_fence_FM (dataCache_1_io_cpu_writeBack_fence_FM ), //i + .io_cpu_writeBack_exclusiveOk (dataCache_1_io_cpu_writeBack_exclusiveOk ), //o + .io_cpu_redo (dataCache_1_io_cpu_redo ), //o + .io_cpu_flush_valid (dataCache_1_io_cpu_flush_valid ), //i + .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o + .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (dataCache_1_io_mem_cmd_ready ), //i + .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o + .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o + .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address ), //o + .io_mem_cmd_payload_data (dataCache_1_io_mem_cmd_payload_data ), //o + .io_mem_cmd_payload_mask (dataCache_1_io_mem_cmd_payload_mask ), //o + .io_mem_cmd_payload_size (dataCache_1_io_mem_cmd_payload_size ), //o + .io_mem_cmd_payload_last (dataCache_1_io_mem_cmd_payload_last ), //o + .io_mem_rsp_valid (dBus_rsp_regNext_valid ), //i + .io_mem_rsp_payload_last (dBus_rsp_regNext_payload_last ), //i + .io_mem_rsp_payload_data (dBus_rsp_regNext_payload_data ), //i + .io_mem_rsp_payload_error (dBus_rsp_regNext_payload_error ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + always @(*) begin + case(_zz_IBusCachedPlugin_jump_pcLoad_payload_7) + 3'b000 : begin + _zz_IBusCachedPlugin_jump_pcLoad_payload_6 = DBusCachedPlugin_redoBranch_payload; + end + 3'b001 : begin + _zz_IBusCachedPlugin_jump_pcLoad_payload_6 = CsrPlugin_jumpInterface_payload; + end + 3'b010 : begin + _zz_IBusCachedPlugin_jump_pcLoad_payload_6 = BranchPlugin_jumpInterface_payload; + end + 3'b011 : begin + _zz_IBusCachedPlugin_jump_pcLoad_payload_6 = CsrPlugin_redoInterface_payload; + end + default : begin + _zz_IBusCachedPlugin_jump_pcLoad_payload_6 = IBusCachedPlugin_predictionJumpInterface_payload; + end + endcase + end + + always @(*) begin + case(_zz_writeBack_DBusCachedPlugin_rspShifted_1) + 2'b00 : begin + _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_0; + end + 2'b01 : begin + _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_1; + end + 2'b10 : begin + _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_2; + end + default : begin + _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_3; + end + endcase + end + + always @(*) begin + case(_zz_writeBack_DBusCachedPlugin_rspShifted_3) + 1'b0 : begin + _zz_writeBack_DBusCachedPlugin_rspShifted_2 = writeBack_DBusCachedPlugin_rspSplits_1; + end + default : begin + _zz_writeBack_DBusCachedPlugin_rspShifted_2 = writeBack_DBusCachedPlugin_rspSplits_3; + end + endcase + end + + always @(*) begin + case(_zz_MmuPlugin_ports_0_cacheLine_valid_3) + 2'b00 : begin + _zz_MmuPlugin_ports_0_cacheLine_valid_4 = MmuPlugin_ports_0_cache_0_valid; + _zz_MmuPlugin_ports_0_cacheLine_exception = MmuPlugin_ports_0_cache_0_exception; + _zz_MmuPlugin_ports_0_cacheLine_superPage = MmuPlugin_ports_0_cache_0_superPage; + _zz_MmuPlugin_ports_0_cacheLine_virtualAddress_0 = MmuPlugin_ports_0_cache_0_virtualAddress_0; + _zz_MmuPlugin_ports_0_cacheLine_virtualAddress_1 = MmuPlugin_ports_0_cache_0_virtualAddress_1; + _zz_MmuPlugin_ports_0_cacheLine_physicalAddress_0 = MmuPlugin_ports_0_cache_0_physicalAddress_0; + _zz_MmuPlugin_ports_0_cacheLine_physicalAddress_1 = MmuPlugin_ports_0_cache_0_physicalAddress_1; + _zz_MmuPlugin_ports_0_cacheLine_allowRead = MmuPlugin_ports_0_cache_0_allowRead; + _zz_MmuPlugin_ports_0_cacheLine_allowWrite = MmuPlugin_ports_0_cache_0_allowWrite; + _zz_MmuPlugin_ports_0_cacheLine_allowExecute = MmuPlugin_ports_0_cache_0_allowExecute; + _zz_MmuPlugin_ports_0_cacheLine_allowUser = MmuPlugin_ports_0_cache_0_allowUser; + end + 2'b01 : begin + _zz_MmuPlugin_ports_0_cacheLine_valid_4 = MmuPlugin_ports_0_cache_1_valid; + _zz_MmuPlugin_ports_0_cacheLine_exception = MmuPlugin_ports_0_cache_1_exception; + _zz_MmuPlugin_ports_0_cacheLine_superPage = MmuPlugin_ports_0_cache_1_superPage; + _zz_MmuPlugin_ports_0_cacheLine_virtualAddress_0 = MmuPlugin_ports_0_cache_1_virtualAddress_0; + _zz_MmuPlugin_ports_0_cacheLine_virtualAddress_1 = MmuPlugin_ports_0_cache_1_virtualAddress_1; + _zz_MmuPlugin_ports_0_cacheLine_physicalAddress_0 = MmuPlugin_ports_0_cache_1_physicalAddress_0; + _zz_MmuPlugin_ports_0_cacheLine_physicalAddress_1 = MmuPlugin_ports_0_cache_1_physicalAddress_1; + _zz_MmuPlugin_ports_0_cacheLine_allowRead = MmuPlugin_ports_0_cache_1_allowRead; + _zz_MmuPlugin_ports_0_cacheLine_allowWrite = MmuPlugin_ports_0_cache_1_allowWrite; + _zz_MmuPlugin_ports_0_cacheLine_allowExecute = MmuPlugin_ports_0_cache_1_allowExecute; + _zz_MmuPlugin_ports_0_cacheLine_allowUser = MmuPlugin_ports_0_cache_1_allowUser; + end + 2'b10 : begin + _zz_MmuPlugin_ports_0_cacheLine_valid_4 = MmuPlugin_ports_0_cache_2_valid; + _zz_MmuPlugin_ports_0_cacheLine_exception = MmuPlugin_ports_0_cache_2_exception; + _zz_MmuPlugin_ports_0_cacheLine_superPage = MmuPlugin_ports_0_cache_2_superPage; + _zz_MmuPlugin_ports_0_cacheLine_virtualAddress_0 = MmuPlugin_ports_0_cache_2_virtualAddress_0; + _zz_MmuPlugin_ports_0_cacheLine_virtualAddress_1 = MmuPlugin_ports_0_cache_2_virtualAddress_1; + _zz_MmuPlugin_ports_0_cacheLine_physicalAddress_0 = MmuPlugin_ports_0_cache_2_physicalAddress_0; + _zz_MmuPlugin_ports_0_cacheLine_physicalAddress_1 = MmuPlugin_ports_0_cache_2_physicalAddress_1; + _zz_MmuPlugin_ports_0_cacheLine_allowRead = MmuPlugin_ports_0_cache_2_allowRead; + _zz_MmuPlugin_ports_0_cacheLine_allowWrite = MmuPlugin_ports_0_cache_2_allowWrite; + _zz_MmuPlugin_ports_0_cacheLine_allowExecute = MmuPlugin_ports_0_cache_2_allowExecute; + _zz_MmuPlugin_ports_0_cacheLine_allowUser = MmuPlugin_ports_0_cache_2_allowUser; + end + default : begin + _zz_MmuPlugin_ports_0_cacheLine_valid_4 = MmuPlugin_ports_0_cache_3_valid; + _zz_MmuPlugin_ports_0_cacheLine_exception = MmuPlugin_ports_0_cache_3_exception; + _zz_MmuPlugin_ports_0_cacheLine_superPage = MmuPlugin_ports_0_cache_3_superPage; + _zz_MmuPlugin_ports_0_cacheLine_virtualAddress_0 = MmuPlugin_ports_0_cache_3_virtualAddress_0; + _zz_MmuPlugin_ports_0_cacheLine_virtualAddress_1 = MmuPlugin_ports_0_cache_3_virtualAddress_1; + _zz_MmuPlugin_ports_0_cacheLine_physicalAddress_0 = MmuPlugin_ports_0_cache_3_physicalAddress_0; + _zz_MmuPlugin_ports_0_cacheLine_physicalAddress_1 = MmuPlugin_ports_0_cache_3_physicalAddress_1; + _zz_MmuPlugin_ports_0_cacheLine_allowRead = MmuPlugin_ports_0_cache_3_allowRead; + _zz_MmuPlugin_ports_0_cacheLine_allowWrite = MmuPlugin_ports_0_cache_3_allowWrite; + _zz_MmuPlugin_ports_0_cacheLine_allowExecute = MmuPlugin_ports_0_cache_3_allowExecute; + _zz_MmuPlugin_ports_0_cacheLine_allowUser = MmuPlugin_ports_0_cache_3_allowUser; + end + endcase + end + + always @(*) begin + case(_zz_MmuPlugin_ports_1_cacheLine_valid_3) + 2'b00 : begin + _zz_MmuPlugin_ports_1_cacheLine_valid_4 = MmuPlugin_ports_1_cache_0_valid; + _zz_MmuPlugin_ports_1_cacheLine_exception = MmuPlugin_ports_1_cache_0_exception; + _zz_MmuPlugin_ports_1_cacheLine_superPage = MmuPlugin_ports_1_cache_0_superPage; + _zz_MmuPlugin_ports_1_cacheLine_virtualAddress_0 = MmuPlugin_ports_1_cache_0_virtualAddress_0; + _zz_MmuPlugin_ports_1_cacheLine_virtualAddress_1 = MmuPlugin_ports_1_cache_0_virtualAddress_1; + _zz_MmuPlugin_ports_1_cacheLine_physicalAddress_0 = MmuPlugin_ports_1_cache_0_physicalAddress_0; + _zz_MmuPlugin_ports_1_cacheLine_physicalAddress_1 = MmuPlugin_ports_1_cache_0_physicalAddress_1; + _zz_MmuPlugin_ports_1_cacheLine_allowRead = MmuPlugin_ports_1_cache_0_allowRead; + _zz_MmuPlugin_ports_1_cacheLine_allowWrite = MmuPlugin_ports_1_cache_0_allowWrite; + _zz_MmuPlugin_ports_1_cacheLine_allowExecute = MmuPlugin_ports_1_cache_0_allowExecute; + _zz_MmuPlugin_ports_1_cacheLine_allowUser = MmuPlugin_ports_1_cache_0_allowUser; + end + 2'b01 : begin + _zz_MmuPlugin_ports_1_cacheLine_valid_4 = MmuPlugin_ports_1_cache_1_valid; + _zz_MmuPlugin_ports_1_cacheLine_exception = MmuPlugin_ports_1_cache_1_exception; + _zz_MmuPlugin_ports_1_cacheLine_superPage = MmuPlugin_ports_1_cache_1_superPage; + _zz_MmuPlugin_ports_1_cacheLine_virtualAddress_0 = MmuPlugin_ports_1_cache_1_virtualAddress_0; + _zz_MmuPlugin_ports_1_cacheLine_virtualAddress_1 = MmuPlugin_ports_1_cache_1_virtualAddress_1; + _zz_MmuPlugin_ports_1_cacheLine_physicalAddress_0 = MmuPlugin_ports_1_cache_1_physicalAddress_0; + _zz_MmuPlugin_ports_1_cacheLine_physicalAddress_1 = MmuPlugin_ports_1_cache_1_physicalAddress_1; + _zz_MmuPlugin_ports_1_cacheLine_allowRead = MmuPlugin_ports_1_cache_1_allowRead; + _zz_MmuPlugin_ports_1_cacheLine_allowWrite = MmuPlugin_ports_1_cache_1_allowWrite; + _zz_MmuPlugin_ports_1_cacheLine_allowExecute = MmuPlugin_ports_1_cache_1_allowExecute; + _zz_MmuPlugin_ports_1_cacheLine_allowUser = MmuPlugin_ports_1_cache_1_allowUser; + end + 2'b10 : begin + _zz_MmuPlugin_ports_1_cacheLine_valid_4 = MmuPlugin_ports_1_cache_2_valid; + _zz_MmuPlugin_ports_1_cacheLine_exception = MmuPlugin_ports_1_cache_2_exception; + _zz_MmuPlugin_ports_1_cacheLine_superPage = MmuPlugin_ports_1_cache_2_superPage; + _zz_MmuPlugin_ports_1_cacheLine_virtualAddress_0 = MmuPlugin_ports_1_cache_2_virtualAddress_0; + _zz_MmuPlugin_ports_1_cacheLine_virtualAddress_1 = MmuPlugin_ports_1_cache_2_virtualAddress_1; + _zz_MmuPlugin_ports_1_cacheLine_physicalAddress_0 = MmuPlugin_ports_1_cache_2_physicalAddress_0; + _zz_MmuPlugin_ports_1_cacheLine_physicalAddress_1 = MmuPlugin_ports_1_cache_2_physicalAddress_1; + _zz_MmuPlugin_ports_1_cacheLine_allowRead = MmuPlugin_ports_1_cache_2_allowRead; + _zz_MmuPlugin_ports_1_cacheLine_allowWrite = MmuPlugin_ports_1_cache_2_allowWrite; + _zz_MmuPlugin_ports_1_cacheLine_allowExecute = MmuPlugin_ports_1_cache_2_allowExecute; + _zz_MmuPlugin_ports_1_cacheLine_allowUser = MmuPlugin_ports_1_cache_2_allowUser; + end + default : begin + _zz_MmuPlugin_ports_1_cacheLine_valid_4 = MmuPlugin_ports_1_cache_3_valid; + _zz_MmuPlugin_ports_1_cacheLine_exception = MmuPlugin_ports_1_cache_3_exception; + _zz_MmuPlugin_ports_1_cacheLine_superPage = MmuPlugin_ports_1_cache_3_superPage; + _zz_MmuPlugin_ports_1_cacheLine_virtualAddress_0 = MmuPlugin_ports_1_cache_3_virtualAddress_0; + _zz_MmuPlugin_ports_1_cacheLine_virtualAddress_1 = MmuPlugin_ports_1_cache_3_virtualAddress_1; + _zz_MmuPlugin_ports_1_cacheLine_physicalAddress_0 = MmuPlugin_ports_1_cache_3_physicalAddress_0; + _zz_MmuPlugin_ports_1_cacheLine_physicalAddress_1 = MmuPlugin_ports_1_cache_3_physicalAddress_1; + _zz_MmuPlugin_ports_1_cacheLine_allowRead = MmuPlugin_ports_1_cache_3_allowRead; + _zz_MmuPlugin_ports_1_cacheLine_allowWrite = MmuPlugin_ports_1_cache_3_allowWrite; + _zz_MmuPlugin_ports_1_cacheLine_allowExecute = MmuPlugin_ports_1_cache_3_allowExecute; + _zz_MmuPlugin_ports_1_cacheLine_allowUser = MmuPlugin_ports_1_cache_3_allowUser; + end + endcase + end + + `ifndef SYNTHESIS + always @(*) begin + case(_zz_decode_to_execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : _zz_decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_decode_to_execute_BRANCH_CTRL_string = "JALR"; + default : _zz_decode_to_execute_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_decode_to_execute_BRANCH_CTRL_1) + `BranchCtrlEnum_defaultEncoding_INC : _zz_decode_to_execute_BRANCH_CTRL_1_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_decode_to_execute_BRANCH_CTRL_1_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JALR"; + default : _zz_decode_to_execute_BRANCH_CTRL_1_string = "????"; + endcase + end + always @(*) begin + case(_zz_memory_to_writeBack_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_memory_to_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_memory_to_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_memory_to_writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_memory_to_writeBack_ENV_CTRL_string = "ECALL"; + default : _zz_memory_to_writeBack_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_memory_to_writeBack_ENV_CTRL_1) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_memory_to_writeBack_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_memory_to_writeBack_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_memory_to_writeBack_ENV_CTRL_1_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_memory_to_writeBack_ENV_CTRL_1_string = "ECALL"; + default : _zz_memory_to_writeBack_ENV_CTRL_1_string = "?????"; + endcase + end + always @(*) begin + case(_zz_execute_to_memory_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_execute_to_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_execute_to_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_execute_to_memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_execute_to_memory_ENV_CTRL_string = "ECALL"; + default : _zz_execute_to_memory_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_execute_to_memory_ENV_CTRL_1) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_execute_to_memory_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_execute_to_memory_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_execute_to_memory_ENV_CTRL_1_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_execute_to_memory_ENV_CTRL_1_string = "ECALL"; + default : _zz_execute_to_memory_ENV_CTRL_1_string = "?????"; + endcase + end + always @(*) begin + case(decode_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : decode_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : decode_ENV_CTRL_string = "ECALL"; + default : decode_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_decode_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_decode_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_decode_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_decode_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_decode_ENV_CTRL_string = "ECALL"; + default : _zz_decode_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_decode_to_execute_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_decode_to_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_decode_to_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_decode_to_execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_decode_to_execute_ENV_CTRL_string = "ECALL"; + default : _zz_decode_to_execute_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_decode_to_execute_ENV_CTRL_1) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_decode_to_execute_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_decode_to_execute_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_decode_to_execute_ENV_CTRL_1_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_decode_to_execute_ENV_CTRL_1_string = "ECALL"; + default : _zz_decode_to_execute_ENV_CTRL_1_string = "?????"; + endcase + end + always @(*) begin + case(_zz_execute_to_memory_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE : _zz_execute_to_memory_SHIFT_CTRL_string = "DISABLE"; + `ShiftCtrlEnum_defaultEncoding_SLL : _zz_execute_to_memory_SHIFT_CTRL_string = "SLL "; + `ShiftCtrlEnum_defaultEncoding_SRL : _zz_execute_to_memory_SHIFT_CTRL_string = "SRL "; + `ShiftCtrlEnum_defaultEncoding_SRA : _zz_execute_to_memory_SHIFT_CTRL_string = "SRA "; + default : _zz_execute_to_memory_SHIFT_CTRL_string = "???????"; + endcase + end + always @(*) begin + case(_zz_execute_to_memory_SHIFT_CTRL_1) + `ShiftCtrlEnum_defaultEncoding_DISABLE : _zz_execute_to_memory_SHIFT_CTRL_1_string = "DISABLE"; + `ShiftCtrlEnum_defaultEncoding_SLL : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SLL "; + `ShiftCtrlEnum_defaultEncoding_SRL : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SRL "; + `ShiftCtrlEnum_defaultEncoding_SRA : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SRA "; + default : _zz_execute_to_memory_SHIFT_CTRL_1_string = "???????"; + endcase + end + always @(*) begin + case(decode_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE : decode_SHIFT_CTRL_string = "DISABLE"; + `ShiftCtrlEnum_defaultEncoding_SLL : decode_SHIFT_CTRL_string = "SLL "; + `ShiftCtrlEnum_defaultEncoding_SRL : decode_SHIFT_CTRL_string = "SRL "; + `ShiftCtrlEnum_defaultEncoding_SRA : decode_SHIFT_CTRL_string = "SRA "; + default : decode_SHIFT_CTRL_string = "???????"; + endcase + end + always @(*) begin + case(_zz_decode_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE : _zz_decode_SHIFT_CTRL_string = "DISABLE"; + `ShiftCtrlEnum_defaultEncoding_SLL : _zz_decode_SHIFT_CTRL_string = "SLL "; + `ShiftCtrlEnum_defaultEncoding_SRL : _zz_decode_SHIFT_CTRL_string = "SRL "; + `ShiftCtrlEnum_defaultEncoding_SRA : _zz_decode_SHIFT_CTRL_string = "SRA "; + default : _zz_decode_SHIFT_CTRL_string = "???????"; + endcase + end + always @(*) begin + case(_zz_decode_to_execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE : _zz_decode_to_execute_SHIFT_CTRL_string = "DISABLE"; + `ShiftCtrlEnum_defaultEncoding_SLL : _zz_decode_to_execute_SHIFT_CTRL_string = "SLL "; + `ShiftCtrlEnum_defaultEncoding_SRL : _zz_decode_to_execute_SHIFT_CTRL_string = "SRL "; + `ShiftCtrlEnum_defaultEncoding_SRA : _zz_decode_to_execute_SHIFT_CTRL_string = "SRA "; + default : _zz_decode_to_execute_SHIFT_CTRL_string = "???????"; + endcase + end + always @(*) begin + case(_zz_decode_to_execute_SHIFT_CTRL_1) + `ShiftCtrlEnum_defaultEncoding_DISABLE : _zz_decode_to_execute_SHIFT_CTRL_1_string = "DISABLE"; + `ShiftCtrlEnum_defaultEncoding_SLL : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SLL "; + `ShiftCtrlEnum_defaultEncoding_SRL : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRL "; + `ShiftCtrlEnum_defaultEncoding_SRA : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRA "; + default : _zz_decode_to_execute_SHIFT_CTRL_1_string = "???????"; + endcase + end + always @(*) begin + case(decode_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR : decode_ALU_BITWISE_CTRL_string = "XOR"; + `AluBitwiseCtrlEnum_defaultEncoding_OR : decode_ALU_BITWISE_CTRL_string = "OR "; + `AluBitwiseCtrlEnum_defaultEncoding_AND : decode_ALU_BITWISE_CTRL_string = "AND"; + default : decode_ALU_BITWISE_CTRL_string = "???"; + endcase + end + always @(*) begin + case(_zz_decode_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR : _zz_decode_ALU_BITWISE_CTRL_string = "XOR"; + `AluBitwiseCtrlEnum_defaultEncoding_OR : _zz_decode_ALU_BITWISE_CTRL_string = "OR "; + `AluBitwiseCtrlEnum_defaultEncoding_AND : _zz_decode_ALU_BITWISE_CTRL_string = "AND"; + default : _zz_decode_ALU_BITWISE_CTRL_string = "???"; + endcase + end + always @(*) begin + case(_zz_decode_to_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "XOR"; + `AluBitwiseCtrlEnum_defaultEncoding_OR : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "OR "; + `AluBitwiseCtrlEnum_defaultEncoding_AND : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "AND"; + default : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "???"; + endcase + end + always @(*) begin + case(_zz_decode_to_execute_ALU_BITWISE_CTRL_1) + `AluBitwiseCtrlEnum_defaultEncoding_XOR : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "XOR"; + `AluBitwiseCtrlEnum_defaultEncoding_OR : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "OR "; + `AluBitwiseCtrlEnum_defaultEncoding_AND : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "AND"; + default : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "???"; + endcase + end + always @(*) begin + case(decode_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; + default : decode_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_decode_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_decode_ALU_CTRL_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_decode_to_execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_decode_to_execute_ALU_CTRL_string = "BITWISE "; + default : _zz_decode_to_execute_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_decode_to_execute_ALU_CTRL_1) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_1_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_1_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_decode_to_execute_ALU_CTRL_1_string = "BITWISE "; + default : _zz_decode_to_execute_ALU_CTRL_1_string = "????????"; + endcase + end + always @(*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : execute_BRANCH_CTRL_string = "JALR"; + default : execute_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : _zz_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_execute_BRANCH_CTRL_string = "JALR"; + default : _zz_execute_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(memory_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : memory_ENV_CTRL_string = "ECALL"; + default : memory_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_memory_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_memory_ENV_CTRL_string = "ECALL"; + default : _zz_memory_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(execute_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : execute_ENV_CTRL_string = "ECALL"; + default : execute_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_execute_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_execute_ENV_CTRL_string = "ECALL"; + default : _zz_execute_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(writeBack_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : writeBack_ENV_CTRL_string = "ECALL"; + default : writeBack_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_writeBack_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_writeBack_ENV_CTRL_string = "ECALL"; + default : _zz_writeBack_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(memory_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE : memory_SHIFT_CTRL_string = "DISABLE"; + `ShiftCtrlEnum_defaultEncoding_SLL : memory_SHIFT_CTRL_string = "SLL "; + `ShiftCtrlEnum_defaultEncoding_SRL : memory_SHIFT_CTRL_string = "SRL "; + `ShiftCtrlEnum_defaultEncoding_SRA : memory_SHIFT_CTRL_string = "SRA "; + default : memory_SHIFT_CTRL_string = "???????"; + endcase + end + always @(*) begin + case(_zz_memory_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE : _zz_memory_SHIFT_CTRL_string = "DISABLE"; + `ShiftCtrlEnum_defaultEncoding_SLL : _zz_memory_SHIFT_CTRL_string = "SLL "; + `ShiftCtrlEnum_defaultEncoding_SRL : _zz_memory_SHIFT_CTRL_string = "SRL "; + `ShiftCtrlEnum_defaultEncoding_SRA : _zz_memory_SHIFT_CTRL_string = "SRA "; + default : _zz_memory_SHIFT_CTRL_string = "???????"; + endcase + end + always @(*) begin + case(execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE : execute_SHIFT_CTRL_string = "DISABLE"; + `ShiftCtrlEnum_defaultEncoding_SLL : execute_SHIFT_CTRL_string = "SLL "; + `ShiftCtrlEnum_defaultEncoding_SRL : execute_SHIFT_CTRL_string = "SRL "; + `ShiftCtrlEnum_defaultEncoding_SRA : execute_SHIFT_CTRL_string = "SRA "; + default : execute_SHIFT_CTRL_string = "???????"; + endcase + end + always @(*) begin + case(_zz_execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE : _zz_execute_SHIFT_CTRL_string = "DISABLE"; + `ShiftCtrlEnum_defaultEncoding_SLL : _zz_execute_SHIFT_CTRL_string = "SLL "; + `ShiftCtrlEnum_defaultEncoding_SRL : _zz_execute_SHIFT_CTRL_string = "SRL "; + `ShiftCtrlEnum_defaultEncoding_SRA : _zz_execute_SHIFT_CTRL_string = "SRA "; + default : _zz_execute_SHIFT_CTRL_string = "???????"; + endcase + end + always @(*) begin + case(decode_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; + default : decode_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(_zz_decode_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : _zz_decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_decode_SRC2_CTRL_string = "PC "; + default : _zz_decode_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(decode_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; + default : decode_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_decode_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : _zz_decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_decode_SRC1_CTRL_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : execute_ALU_CTRL_string = "BITWISE "; + default : execute_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_execute_ALU_CTRL_string = "BITWISE "; + default : _zz_execute_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR : execute_ALU_BITWISE_CTRL_string = "XOR"; + `AluBitwiseCtrlEnum_defaultEncoding_OR : execute_ALU_BITWISE_CTRL_string = "OR "; + `AluBitwiseCtrlEnum_defaultEncoding_AND : execute_ALU_BITWISE_CTRL_string = "AND"; + default : execute_ALU_BITWISE_CTRL_string = "???"; + endcase + end + always @(*) begin + case(_zz_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR : _zz_execute_ALU_BITWISE_CTRL_string = "XOR"; + `AluBitwiseCtrlEnum_defaultEncoding_OR : _zz_execute_ALU_BITWISE_CTRL_string = "OR "; + `AluBitwiseCtrlEnum_defaultEncoding_AND : _zz_execute_ALU_BITWISE_CTRL_string = "AND"; + default : _zz_execute_ALU_BITWISE_CTRL_string = "???"; + endcase + end + always @(*) begin + case(_zz_decode_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : _zz_decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_decode_BRANCH_CTRL_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_decode_ENV_CTRL_1) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_decode_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_decode_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_decode_ENV_CTRL_1_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_decode_ENV_CTRL_1_string = "ECALL"; + default : _zz_decode_ENV_CTRL_1_string = "?????"; + endcase + end + always @(*) begin + case(_zz_decode_SHIFT_CTRL_1) + `ShiftCtrlEnum_defaultEncoding_DISABLE : _zz_decode_SHIFT_CTRL_1_string = "DISABLE"; + `ShiftCtrlEnum_defaultEncoding_SLL : _zz_decode_SHIFT_CTRL_1_string = "SLL "; + `ShiftCtrlEnum_defaultEncoding_SRL : _zz_decode_SHIFT_CTRL_1_string = "SRL "; + `ShiftCtrlEnum_defaultEncoding_SRA : _zz_decode_SHIFT_CTRL_1_string = "SRA "; + default : _zz_decode_SHIFT_CTRL_1_string = "???????"; + endcase + end + always @(*) begin + case(_zz_decode_ALU_BITWISE_CTRL_1) + `AluBitwiseCtrlEnum_defaultEncoding_XOR : _zz_decode_ALU_BITWISE_CTRL_1_string = "XOR"; + `AluBitwiseCtrlEnum_defaultEncoding_OR : _zz_decode_ALU_BITWISE_CTRL_1_string = "OR "; + `AluBitwiseCtrlEnum_defaultEncoding_AND : _zz_decode_ALU_BITWISE_CTRL_1_string = "AND"; + default : _zz_decode_ALU_BITWISE_CTRL_1_string = "???"; + endcase + end + always @(*) begin + case(_zz_decode_SRC2_CTRL_1) + `Src2CtrlEnum_defaultEncoding_RS : _zz_decode_SRC2_CTRL_1_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_decode_SRC2_CTRL_1_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_decode_SRC2_CTRL_1_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_decode_SRC2_CTRL_1_string = "PC "; + default : _zz_decode_SRC2_CTRL_1_string = "???"; + endcase + end + always @(*) begin + case(_zz_decode_ALU_CTRL_1) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_decode_ALU_CTRL_1_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_decode_ALU_CTRL_1_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_decode_ALU_CTRL_1_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_1_string = "????????"; + endcase + end + always @(*) begin + case(_zz_decode_SRC1_CTRL_1) + `Src1CtrlEnum_defaultEncoding_RS : _zz_decode_SRC1_CTRL_1_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_decode_SRC1_CTRL_1_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_decode_SRC1_CTRL_1_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_decode_SRC1_CTRL_1_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_1_string = "????????????"; + endcase + end + always @(*) begin + case(decode_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR"; + default : decode_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_decode_BRANCH_CTRL_1) + `BranchCtrlEnum_defaultEncoding_INC : _zz_decode_BRANCH_CTRL_1_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_decode_BRANCH_CTRL_1_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_decode_BRANCH_CTRL_1_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_decode_BRANCH_CTRL_1_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_1_string = "????"; + endcase + end + always @(*) begin + case(_zz_decode_SRC1_CTRL_2) + `Src1CtrlEnum_defaultEncoding_RS : _zz_decode_SRC1_CTRL_2_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_decode_SRC1_CTRL_2_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_decode_SRC1_CTRL_2_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_decode_SRC1_CTRL_2_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_2_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_decode_ALU_CTRL_2) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_decode_ALU_CTRL_2_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_decode_ALU_CTRL_2_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_decode_ALU_CTRL_2_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_2_string = "????????"; + endcase + end + always @(*) begin + case(_zz_decode_SRC2_CTRL_2) + `Src2CtrlEnum_defaultEncoding_RS : _zz_decode_SRC2_CTRL_2_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_decode_SRC2_CTRL_2_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_decode_SRC2_CTRL_2_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_decode_SRC2_CTRL_2_string = "PC "; + default : _zz_decode_SRC2_CTRL_2_string = "???"; + endcase + end + always @(*) begin + case(_zz_decode_ALU_BITWISE_CTRL_2) + `AluBitwiseCtrlEnum_defaultEncoding_XOR : _zz_decode_ALU_BITWISE_CTRL_2_string = "XOR"; + `AluBitwiseCtrlEnum_defaultEncoding_OR : _zz_decode_ALU_BITWISE_CTRL_2_string = "OR "; + `AluBitwiseCtrlEnum_defaultEncoding_AND : _zz_decode_ALU_BITWISE_CTRL_2_string = "AND"; + default : _zz_decode_ALU_BITWISE_CTRL_2_string = "???"; + endcase + end + always @(*) begin + case(_zz_decode_SHIFT_CTRL_2) + `ShiftCtrlEnum_defaultEncoding_DISABLE : _zz_decode_SHIFT_CTRL_2_string = "DISABLE"; + `ShiftCtrlEnum_defaultEncoding_SLL : _zz_decode_SHIFT_CTRL_2_string = "SLL "; + `ShiftCtrlEnum_defaultEncoding_SRL : _zz_decode_SHIFT_CTRL_2_string = "SRL "; + `ShiftCtrlEnum_defaultEncoding_SRA : _zz_decode_SHIFT_CTRL_2_string = "SRA "; + default : _zz_decode_SHIFT_CTRL_2_string = "???????"; + endcase + end + always @(*) begin + case(_zz_decode_ENV_CTRL_2) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_decode_ENV_CTRL_2_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_decode_ENV_CTRL_2_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_decode_ENV_CTRL_2_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_decode_ENV_CTRL_2_string = "ECALL"; + default : _zz_decode_ENV_CTRL_2_string = "?????"; + endcase + end + always @(*) begin + case(_zz_decode_BRANCH_CTRL_2) + `BranchCtrlEnum_defaultEncoding_INC : _zz_decode_BRANCH_CTRL_2_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_decode_BRANCH_CTRL_2_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_decode_BRANCH_CTRL_2_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_decode_BRANCH_CTRL_2_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_2_string = "????"; + endcase + end + always @(*) begin + case(MmuPlugin_shared_state_1) + `MmuPlugin_shared_State_defaultEncoding_IDLE : MmuPlugin_shared_state_1_string = "IDLE "; + `MmuPlugin_shared_State_defaultEncoding_L1_CMD : MmuPlugin_shared_state_1_string = "L1_CMD"; + `MmuPlugin_shared_State_defaultEncoding_L1_RSP : MmuPlugin_shared_state_1_string = "L1_RSP"; + `MmuPlugin_shared_State_defaultEncoding_L0_CMD : MmuPlugin_shared_state_1_string = "L0_CMD"; + `MmuPlugin_shared_State_defaultEncoding_L0_RSP : MmuPlugin_shared_state_1_string = "L0_RSP"; + default : MmuPlugin_shared_state_1_string = "??????"; + endcase + end + always @(*) begin + case(decode_to_execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; + default : decode_to_execute_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(decode_to_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR"; + `AluBitwiseCtrlEnum_defaultEncoding_OR : decode_to_execute_ALU_BITWISE_CTRL_string = "OR "; + `AluBitwiseCtrlEnum_defaultEncoding_AND : decode_to_execute_ALU_BITWISE_CTRL_string = "AND"; + default : decode_to_execute_ALU_BITWISE_CTRL_string = "???"; + endcase + end + always @(*) begin + case(decode_to_execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE : decode_to_execute_SHIFT_CTRL_string = "DISABLE"; + `ShiftCtrlEnum_defaultEncoding_SLL : decode_to_execute_SHIFT_CTRL_string = "SLL "; + `ShiftCtrlEnum_defaultEncoding_SRL : decode_to_execute_SHIFT_CTRL_string = "SRL "; + `ShiftCtrlEnum_defaultEncoding_SRA : decode_to_execute_SHIFT_CTRL_string = "SRA "; + default : decode_to_execute_SHIFT_CTRL_string = "???????"; + endcase + end + always @(*) begin + case(execute_to_memory_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE : execute_to_memory_SHIFT_CTRL_string = "DISABLE"; + `ShiftCtrlEnum_defaultEncoding_SLL : execute_to_memory_SHIFT_CTRL_string = "SLL "; + `ShiftCtrlEnum_defaultEncoding_SRL : execute_to_memory_SHIFT_CTRL_string = "SRL "; + `ShiftCtrlEnum_defaultEncoding_SRA : execute_to_memory_SHIFT_CTRL_string = "SRA "; + default : execute_to_memory_SHIFT_CTRL_string = "???????"; + endcase + end + always @(*) begin + case(decode_to_execute_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : decode_to_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : decode_to_execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL"; + default : decode_to_execute_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(execute_to_memory_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : execute_to_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : execute_to_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : execute_to_memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL"; + default : execute_to_memory_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(memory_to_writeBack_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : memory_to_writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL"; + default : memory_to_writeBack_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(decode_to_execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; + default : decode_to_execute_BRANCH_CTRL_string = "????"; + endcase + end + `endif + + assign memory_MUL_LOW = ($signed(_zz_memory_MUL_LOW) + $signed(_zz_memory_MUL_LOW_7)); + assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; + assign execute_BRANCH_DO = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget); + assign memory_MUL_HH = execute_to_memory_MUL_HH; + assign execute_MUL_HH = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh)); + assign execute_MUL_HL = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow)); + assign execute_MUL_LH = ($signed(execute_MulPlugin_aSLow) * $signed(execute_MulPlugin_bHigh)); + assign execute_MUL_LL = (execute_MulPlugin_aULow * execute_MulPlugin_bULow); + assign execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT; + assign execute_REGFILE_WRITE_DATA = _zz_execute_REGFILE_WRITE_DATA; + assign execute_IS_DBUS_SHARING = (MmuPlugin_dBusAccess_cmd_valid && MmuPlugin_dBusAccess_cmd_ready); + assign memory_MEMORY_STORE_DATA_RF = execute_to_memory_MEMORY_STORE_DATA_RF; + assign execute_MEMORY_STORE_DATA_RF = _zz_execute_MEMORY_STORE_DATA_RF; + assign decode_PREDICTION_HAD_BRANCHED2 = IBusCachedPlugin_decodePrediction_cmd_hadBranch; + assign decode_DO_EBREAK = (((! DebugPlugin_haltIt) && (decode_IS_EBREAK || 1'b0)) && DebugPlugin_allowEBreak); + assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); + assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); + assign decode_SRC2 = _zz_decode_SRC2_6; + assign decode_SRC1 = _zz_decode_SRC1_1; + assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); + assign _zz_decode_to_execute_BRANCH_CTRL = _zz_decode_to_execute_BRANCH_CTRL_1; + assign decode_IS_SFENCE_VMA2 = _zz_decode_IS_SFENCE_VMA2[33]; + assign decode_IS_SFENCE_VMA = _zz_decode_IS_SFENCE_VMA2[32]; + assign _zz_memory_to_writeBack_ENV_CTRL = _zz_memory_to_writeBack_ENV_CTRL_1; + assign _zz_execute_to_memory_ENV_CTRL = _zz_execute_to_memory_ENV_CTRL_1; + assign decode_ENV_CTRL = _zz_decode_ENV_CTRL; + assign _zz_decode_to_execute_ENV_CTRL = _zz_decode_to_execute_ENV_CTRL_1; + assign decode_IS_CSR = _zz_decode_IS_SFENCE_VMA2[29]; + assign decode_IS_RS2_SIGNED = _zz_decode_IS_SFENCE_VMA2[28]; + assign decode_IS_RS1_SIGNED = _zz_decode_IS_SFENCE_VMA2[27]; + assign decode_IS_DIV = _zz_decode_IS_SFENCE_VMA2[26]; + assign memory_IS_MUL = execute_to_memory_IS_MUL; + assign execute_IS_MUL = decode_to_execute_IS_MUL; + assign decode_IS_MUL = _zz_decode_IS_SFENCE_VMA2[25]; + assign _zz_execute_to_memory_SHIFT_CTRL = _zz_execute_to_memory_SHIFT_CTRL_1; + assign decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL; + assign _zz_decode_to_execute_SHIFT_CTRL = _zz_decode_to_execute_SHIFT_CTRL_1; + assign decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL; + assign _zz_decode_to_execute_ALU_BITWISE_CTRL = _zz_decode_to_execute_ALU_BITWISE_CTRL_1; + assign decode_SRC_LESS_UNSIGNED = _zz_decode_IS_SFENCE_VMA2[20]; + assign decode_MEMORY_MANAGMENT = _zz_decode_IS_SFENCE_VMA2[19]; + assign memory_MEMORY_LRSC = execute_to_memory_MEMORY_LRSC; + assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR; + assign decode_MEMORY_WR = _zz_decode_IS_SFENCE_VMA2[13]; + assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_decode_IS_SFENCE_VMA2[12]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_decode_IS_SFENCE_VMA2[11]; + assign decode_ALU_CTRL = _zz_decode_ALU_CTRL; + assign _zz_decode_to_execute_ALU_CTRL = _zz_decode_to_execute_ALU_CTRL_1; + assign decode_MEMORY_FORCE_CONSTISTENCY = _zz_decode_MEMORY_FORCE_CONSTISTENCY; + assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; + assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; + assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; + assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004); + assign memory_PC = execute_to_memory_PC; + assign execute_IS_SFENCE_VMA2 = decode_to_execute_IS_SFENCE_VMA2; + assign memory_BRANCH_CALC = execute_to_memory_BRANCH_CALC; + assign memory_BRANCH_DO = execute_to_memory_BRANCH_DO; + assign execute_PREDICTION_HAD_BRANCHED2 = decode_to_execute_PREDICTION_HAD_BRANCHED2; + assign execute_BRANCH_COND_RESULT = _zz_execute_BRANCH_COND_RESULT_1; + assign execute_BRANCH_CTRL = _zz_execute_BRANCH_CTRL; + assign execute_PC = decode_to_execute_PC; + assign execute_DO_EBREAK = decode_to_execute_DO_EBREAK; + assign decode_IS_EBREAK = _zz_decode_IS_SFENCE_VMA2[34]; + assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; + assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; + assign execute_IS_CSR = decode_to_execute_IS_CSR; + assign memory_ENV_CTRL = _zz_memory_ENV_CTRL; + assign execute_ENV_CTRL = _zz_execute_ENV_CTRL; + assign writeBack_ENV_CTRL = _zz_writeBack_ENV_CTRL; + assign execute_IS_SFENCE_VMA = decode_to_execute_IS_SFENCE_VMA; + assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED; + assign execute_IS_DIV = decode_to_execute_IS_DIV; + assign execute_IS_RS2_SIGNED = decode_to_execute_IS_RS2_SIGNED; + assign memory_IS_DIV = execute_to_memory_IS_DIV; + assign writeBack_IS_MUL = memory_to_writeBack_IS_MUL; + assign writeBack_MUL_HH = memory_to_writeBack_MUL_HH; + assign writeBack_MUL_LOW = memory_to_writeBack_MUL_LOW; + assign memory_MUL_HL = execute_to_memory_MUL_HL; + assign memory_MUL_LH = execute_to_memory_MUL_LH; + assign memory_MUL_LL = execute_to_memory_MUL_LL; + assign execute_RS1 = decode_to_execute_RS1; + assign decode_RS2_USE = _zz_decode_IS_SFENCE_VMA2[17]; + assign decode_RS1_USE = _zz_decode_IS_SFENCE_VMA2[5]; + always @(*) begin + _zz_decode_RS2 = execute_REGFILE_WRITE_DATA; + if(when_CsrPlugin_l1176) begin + _zz_decode_RS2 = CsrPlugin_csrMapping_readDataSignal; + end + if(DBusCachedPlugin_forceDatapath) begin + _zz_decode_RS2 = MmuPlugin_dBusAccess_cmd_payload_address; + end + end + + assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID; + assign execute_BYPASSABLE_EXECUTE_STAGE = decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + assign memory_REGFILE_WRITE_VALID = execute_to_memory_REGFILE_WRITE_VALID; + assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION; + assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE; + assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; + always @(*) begin + decode_RS2 = decode_RegFilePlugin_rs2Data; + if(HazardSimplePlugin_writeBackBuffer_valid) begin + if(HazardSimplePlugin_addr1Match) begin + decode_RS2 = HazardSimplePlugin_writeBackBuffer_payload_data; + end + end + if(when_HazardSimplePlugin_l45) begin + if(when_HazardSimplePlugin_l47) begin + if(when_HazardSimplePlugin_l51) begin + decode_RS2 = _zz_decode_RS2_2; + end + end + end + if(when_HazardSimplePlugin_l45_1) begin + if(memory_BYPASSABLE_MEMORY_STAGE) begin + if(when_HazardSimplePlugin_l51_1) begin + decode_RS2 = _zz_decode_RS2_1; + end + end + end + if(when_HazardSimplePlugin_l45_2) begin + if(execute_BYPASSABLE_EXECUTE_STAGE) begin + if(when_HazardSimplePlugin_l51_2) begin + decode_RS2 = _zz_decode_RS2; + end + end + end + end + + always @(*) begin + decode_RS1 = decode_RegFilePlugin_rs1Data; + if(HazardSimplePlugin_writeBackBuffer_valid) begin + if(HazardSimplePlugin_addr0Match) begin + decode_RS1 = HazardSimplePlugin_writeBackBuffer_payload_data; + end + end + if(when_HazardSimplePlugin_l45) begin + if(when_HazardSimplePlugin_l47) begin + if(when_HazardSimplePlugin_l48) begin + decode_RS1 = _zz_decode_RS2_2; + end + end + end + if(when_HazardSimplePlugin_l45_1) begin + if(memory_BYPASSABLE_MEMORY_STAGE) begin + if(when_HazardSimplePlugin_l48_1) begin + decode_RS1 = _zz_decode_RS2_1; + end + end + end + if(when_HazardSimplePlugin_l45_2) begin + if(execute_BYPASSABLE_EXECUTE_STAGE) begin + if(when_HazardSimplePlugin_l48_2) begin + decode_RS1 = _zz_decode_RS2; + end + end + end + end + + assign memory_SHIFT_RIGHT = execute_to_memory_SHIFT_RIGHT; + always @(*) begin + _zz_decode_RS2_1 = memory_REGFILE_WRITE_DATA; + if(memory_arbitration_isValid) begin + case(memory_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_SLL : begin + _zz_decode_RS2_1 = _zz_decode_RS2_3; + end + `ShiftCtrlEnum_defaultEncoding_SRL, `ShiftCtrlEnum_defaultEncoding_SRA : begin + _zz_decode_RS2_1 = memory_SHIFT_RIGHT; + end + default : begin + end + endcase + end + if(when_MulDivIterativePlugin_l128) begin + _zz_decode_RS2_1 = memory_MulDivIterativePlugin_div_result; + end + end + + assign memory_SHIFT_CTRL = _zz_memory_SHIFT_CTRL; + assign execute_SHIFT_CTRL = _zz_execute_SHIFT_CTRL; + assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; + assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; + assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; + assign _zz_decode_SRC2 = decode_PC; + assign _zz_decode_SRC2_1 = decode_RS2; + assign decode_SRC2_CTRL = _zz_decode_SRC2_CTRL; + assign _zz_decode_SRC1 = decode_RS1; + assign decode_SRC1_CTRL = _zz_decode_SRC1_CTRL; + assign decode_SRC_USE_SUB_LESS = _zz_decode_IS_SFENCE_VMA2[3]; + assign decode_SRC_ADD_ZERO = _zz_decode_IS_SFENCE_VMA2[18]; + assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; + assign execute_SRC_LESS = execute_SrcPlugin_less; + assign execute_ALU_CTRL = _zz_execute_ALU_CTRL; + assign execute_SRC2 = decode_to_execute_SRC2; + assign execute_SRC1 = decode_to_execute_SRC1; + assign execute_ALU_BITWISE_CTRL = _zz_execute_ALU_BITWISE_CTRL; + assign _zz_lastStageRegFileWrite_payload_address = writeBack_INSTRUCTION; + assign _zz_lastStageRegFileWrite_valid = writeBack_REGFILE_WRITE_VALID; + always @(*) begin + _zz_1 = 1'b0; + if(lastStageRegFileWrite_valid) begin + _zz_1 = 1'b1; + end + end + + assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); + always @(*) begin + decode_REGFILE_WRITE_VALID = _zz_decode_IS_SFENCE_VMA2[10]; + if(when_RegFilePlugin_l63) begin + decode_REGFILE_WRITE_VALID = 1'b0; + end + end + + assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION) == 32'h00001073),{(_zz_decode_LEGAL_INSTRUCTION_1 == _zz_decode_LEGAL_INSTRUCTION_2),{_zz_decode_LEGAL_INSTRUCTION_3,{_zz_decode_LEGAL_INSTRUCTION_4,_zz_decode_LEGAL_INSTRUCTION_5}}}}}}} != 25'h0); + assign writeBack_IS_DBUS_SHARING = memory_to_writeBack_IS_DBUS_SHARING; + assign memory_IS_DBUS_SHARING = execute_to_memory_IS_DBUS_SHARING; + always @(*) begin + _zz_decode_RS2_2 = writeBack_REGFILE_WRITE_DATA; + if(when_DBusCachedPlugin_l484) begin + _zz_decode_RS2_2 = writeBack_DBusCachedPlugin_rspFormated; + end + if(when_MulPlugin_l147) begin + case(switch_MulPlugin_l148) + 2'b00 : begin + _zz_decode_RS2_2 = _zz__zz_decode_RS2_2; + end + default : begin + _zz_decode_RS2_2 = _zz__zz_decode_RS2_2_1; + end + endcase + end + end + + assign writeBack_MEMORY_LRSC = memory_to_writeBack_MEMORY_LRSC; + assign writeBack_MEMORY_WR = memory_to_writeBack_MEMORY_WR; + assign writeBack_MEMORY_STORE_DATA_RF = memory_to_writeBack_MEMORY_STORE_DATA_RF; + assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA; + assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE; + assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA; + assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE; + always @(*) begin + execute_MEMORY_AMO = decode_to_execute_MEMORY_AMO; + if(MmuPlugin_dBusAccess_cmd_valid) begin + if(when_DBusCachedPlugin_l498) begin + execute_MEMORY_AMO = 1'b0; + end + end + end + + always @(*) begin + execute_MEMORY_LRSC = decode_to_execute_MEMORY_LRSC; + if(MmuPlugin_dBusAccess_cmd_valid) begin + if(when_DBusCachedPlugin_l498) begin + execute_MEMORY_LRSC = 1'b0; + end + end + end + + assign execute_MEMORY_FORCE_CONSTISTENCY = decode_to_execute_MEMORY_FORCE_CONSTISTENCY; + assign execute_MEMORY_MANAGMENT = decode_to_execute_MEMORY_MANAGMENT; + assign execute_RS2 = decode_to_execute_RS2; + assign execute_MEMORY_WR = decode_to_execute_MEMORY_WR; + assign execute_SRC_ADD = execute_SrcPlugin_addSub; + assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; + assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; + assign decode_MEMORY_AMO = _zz_decode_IS_SFENCE_VMA2[16]; + assign decode_MEMORY_LRSC = _zz_decode_IS_SFENCE_VMA2[15]; + assign decode_MEMORY_ENABLE = _zz_decode_IS_SFENCE_VMA2[4]; + assign decode_FLUSH_ALL = _zz_decode_IS_SFENCE_VMA2[0]; + always @(*) begin + IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3; + if(when_IBusCachedPlugin_l256) begin + IBusCachedPlugin_rsp_issueDetected_4 = 1'b1; + end + end + + always @(*) begin + IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2; + if(when_IBusCachedPlugin_l250) begin + IBusCachedPlugin_rsp_issueDetected_3 = 1'b1; + end + end + + always @(*) begin + IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1; + if(when_IBusCachedPlugin_l244) begin + IBusCachedPlugin_rsp_issueDetected_2 = 1'b1; + end + end + + always @(*) begin + IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected; + if(when_IBusCachedPlugin_l239) begin + IBusCachedPlugin_rsp_issueDetected_1 = 1'b1; + end + end + + assign decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL_1; + assign decode_INSTRUCTION = IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; + always @(*) begin + _zz_memory_to_writeBack_FORMAL_PC_NEXT = memory_FORMAL_PC_NEXT; + if(BranchPlugin_jumpInterface_valid) begin + _zz_memory_to_writeBack_FORMAL_PC_NEXT = BranchPlugin_jumpInterface_payload; + end + end + + always @(*) begin + _zz_execute_to_memory_FORMAL_PC_NEXT = execute_FORMAL_PC_NEXT; + if(CsrPlugin_redoInterface_valid) begin + _zz_execute_to_memory_FORMAL_PC_NEXT = CsrPlugin_redoInterface_payload; + end + end + + always @(*) begin + _zz_decode_to_execute_FORMAL_PC_NEXT = decode_FORMAL_PC_NEXT; + if(IBusCachedPlugin_predictionJumpInterface_valid) begin + _zz_decode_to_execute_FORMAL_PC_NEXT = IBusCachedPlugin_predictionJumpInterface_payload; + end + end + + assign decode_PC = IBusCachedPlugin_iBusRsp_output_payload_pc; + assign writeBack_PC = memory_to_writeBack_PC; + assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION; + always @(*) begin + decode_arbitration_haltItself = 1'b0; + if(when_DBusCachedPlugin_l303) begin + decode_arbitration_haltItself = 1'b1; + end + case(switch_Fetcher_l362) + 3'b010 : begin + decode_arbitration_haltItself = 1'b1; + end + default : begin + end + endcase + end + + always @(*) begin + decode_arbitration_haltByOther = 1'b0; + if(MmuPlugin_dBusAccess_cmd_valid) begin + decode_arbitration_haltByOther = 1'b1; + end + if(when_HazardSimplePlugin_l113) begin + decode_arbitration_haltByOther = 1'b1; + end + if(CsrPlugin_rescheduleLogic_rescheduleNext) begin + decode_arbitration_haltByOther = 1'b1; + end + if(CsrPlugin_pipelineLiberator_active) begin + decode_arbitration_haltByOther = 1'b1; + end + if(when_CsrPlugin_l1116) begin + decode_arbitration_haltByOther = 1'b1; + end + end + + always @(*) begin + decode_arbitration_removeIt = 1'b0; + if(_zz_when) begin + decode_arbitration_removeIt = 1'b1; + end + if(decode_arbitration_isFlushed) begin + decode_arbitration_removeIt = 1'b1; + end + end + + assign decode_arbitration_flushIt = 1'b0; + always @(*) begin + decode_arbitration_flushNext = 1'b0; + if(IBusCachedPlugin_predictionJumpInterface_valid) begin + decode_arbitration_flushNext = 1'b1; + end + if(_zz_when) begin + decode_arbitration_flushNext = 1'b1; + end + end + + always @(*) begin + execute_arbitration_haltItself = 1'b0; + if(when_DBusCachedPlugin_l343) begin + execute_arbitration_haltItself = 1'b1; + end + if(when_CsrPlugin_l1108) begin + if(when_CsrPlugin_l1110) begin + execute_arbitration_haltItself = 1'b1; + end + end + if(when_CsrPlugin_l1180) begin + if(execute_CsrPlugin_blockedBySideEffects) begin + execute_arbitration_haltItself = 1'b1; + end + end + end + + always @(*) begin + execute_arbitration_haltByOther = 1'b0; + if(when_DBusCachedPlugin_l359) begin + execute_arbitration_haltByOther = 1'b1; + end + if(when_DebugPlugin_l284) begin + execute_arbitration_haltByOther = 1'b1; + end + end + + always @(*) begin + execute_arbitration_removeIt = 1'b0; + if(CsrPlugin_selfException_valid) begin + execute_arbitration_removeIt = 1'b1; + end + if(execute_arbitration_isFlushed) begin + execute_arbitration_removeIt = 1'b1; + end + end + + always @(*) begin + execute_arbitration_flushIt = 1'b0; + if(when_DebugPlugin_l284) begin + if(when_DebugPlugin_l287) begin + execute_arbitration_flushIt = 1'b1; + end + end + end + + always @(*) begin + execute_arbitration_flushNext = 1'b0; + if(CsrPlugin_rescheduleLogic_rescheduleNext) begin + execute_arbitration_flushNext = 1'b1; + end + if(CsrPlugin_selfException_valid) begin + execute_arbitration_flushNext = 1'b1; + end + if(when_DebugPlugin_l284) begin + if(when_DebugPlugin_l287) begin + execute_arbitration_flushNext = 1'b1; + end + end + end + + always @(*) begin + memory_arbitration_haltItself = 1'b0; + if(when_MulDivIterativePlugin_l128) begin + if(when_MulDivIterativePlugin_l129) begin + memory_arbitration_haltItself = 1'b1; + end + end + end + + assign memory_arbitration_haltByOther = 1'b0; + always @(*) begin + memory_arbitration_removeIt = 1'b0; + if(BranchPlugin_branchExceptionPort_valid) begin + memory_arbitration_removeIt = 1'b1; + end + if(memory_arbitration_isFlushed) begin + memory_arbitration_removeIt = 1'b1; + end + end + + assign memory_arbitration_flushIt = 1'b0; + always @(*) begin + memory_arbitration_flushNext = 1'b0; + if(BranchPlugin_branchExceptionPort_valid) begin + memory_arbitration_flushNext = 1'b1; + end + if(BranchPlugin_jumpInterface_valid) begin + memory_arbitration_flushNext = 1'b1; + end + end + + always @(*) begin + writeBack_arbitration_haltItself = 1'b0; + if(when_DBusCachedPlugin_l458) begin + writeBack_arbitration_haltItself = 1'b1; + end + end + + assign writeBack_arbitration_haltByOther = 1'b0; + always @(*) begin + writeBack_arbitration_removeIt = 1'b0; + if(DBusCachedPlugin_exceptionBus_valid) begin + writeBack_arbitration_removeIt = 1'b1; + end + if(writeBack_arbitration_isFlushed) begin + writeBack_arbitration_removeIt = 1'b1; + end + end + + always @(*) begin + writeBack_arbitration_flushIt = 1'b0; + if(DBusCachedPlugin_redoBranch_valid) begin + writeBack_arbitration_flushIt = 1'b1; + end + end + + always @(*) begin + writeBack_arbitration_flushNext = 1'b0; + if(DBusCachedPlugin_redoBranch_valid) begin + writeBack_arbitration_flushNext = 1'b1; + end + if(DBusCachedPlugin_exceptionBus_valid) begin + writeBack_arbitration_flushNext = 1'b1; + end + if(when_CsrPlugin_l1019) begin + writeBack_arbitration_flushNext = 1'b1; + end + if(when_CsrPlugin_l1064) begin + writeBack_arbitration_flushNext = 1'b1; + end + end + + assign lastStageInstruction = writeBack_INSTRUCTION; + assign lastStagePc = writeBack_PC; + assign lastStageIsValid = writeBack_arbitration_isValid; + assign lastStageIsFiring = writeBack_arbitration_isFiring; + always @(*) begin + IBusCachedPlugin_fetcherHalt = 1'b0; + if(when_CsrPlugin_l922) begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(when_CsrPlugin_l1019) begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(when_CsrPlugin_l1064) begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(when_DebugPlugin_l284) begin + if(when_DebugPlugin_l287) begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + end + if(DebugPlugin_haltIt) begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(when_DebugPlugin_l300) begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + end + + always @(*) begin + IBusCachedPlugin_incomingInstruction = 1'b0; + if(when_Fetcher_l240) begin + IBusCachedPlugin_incomingInstruction = 1'b1; + end + end + + always @(*) begin + _zz_when_DBusCachedPlugin_l386 = 1'b0; + if(DebugPlugin_godmode) begin + _zz_when_DBusCachedPlugin_l386 = 1'b1; + end + end + + assign CsrPlugin_csrMapping_allowCsrSignal = 1'b0; + assign CsrPlugin_csrMapping_readDataSignal = CsrPlugin_csrMapping_readDataInit; + always @(*) begin + CsrPlugin_inWfi = 1'b0; + if(when_CsrPlugin_l1108) begin + CsrPlugin_inWfi = 1'b1; + end + end + + always @(*) begin + CsrPlugin_thirdPartyWake = 1'b0; + if(DebugPlugin_haltIt) begin + CsrPlugin_thirdPartyWake = 1'b1; + end + end + + always @(*) begin + CsrPlugin_jumpInterface_valid = 1'b0; + if(when_CsrPlugin_l1019) begin + CsrPlugin_jumpInterface_valid = 1'b1; + end + if(when_CsrPlugin_l1064) begin + CsrPlugin_jumpInterface_valid = 1'b1; + end + end + + always @(*) begin + CsrPlugin_jumpInterface_payload = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + if(when_CsrPlugin_l1019) begin + CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; + end + if(when_CsrPlugin_l1064) begin + case(switch_CsrPlugin_l1068) + 2'b11 : begin + CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; + end + 2'b01 : begin + CsrPlugin_jumpInterface_payload = CsrPlugin_sepc; + end + default : begin + end + endcase + end + end + + always @(*) begin + CsrPlugin_forceMachineWire = 1'b0; + if(DebugPlugin_godmode) begin + CsrPlugin_forceMachineWire = 1'b1; + end + end + + always @(*) begin + CsrPlugin_allowInterrupts = 1'b1; + if(when_DebugPlugin_l316) begin + CsrPlugin_allowInterrupts = 1'b0; + end + end + + always @(*) begin + CsrPlugin_allowException = 1'b1; + if(DebugPlugin_godmode) begin + CsrPlugin_allowException = 1'b0; + end + end + + always @(*) begin + CsrPlugin_allowEbreakException = 1'b1; + if(DebugPlugin_allowEBreak) begin + CsrPlugin_allowEbreakException = 1'b0; + end + end + + assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); + assign IBusCachedPlugin_jump_pcLoad_valid = ({BranchPlugin_jumpInterface_valid,{CsrPlugin_redoInterface_valid,{CsrPlugin_jumpInterface_valid,{DBusCachedPlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}}} != 5'h0); + assign _zz_IBusCachedPlugin_jump_pcLoad_payload = {IBusCachedPlugin_predictionJumpInterface_valid,{CsrPlugin_redoInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}}; + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_1 = (_zz_IBusCachedPlugin_jump_pcLoad_payload & (~ _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1)); + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_2 = _zz_IBusCachedPlugin_jump_pcLoad_payload_1[3]; + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_3 = _zz_IBusCachedPlugin_jump_pcLoad_payload_1[4]; + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_4 = (_zz_IBusCachedPlugin_jump_pcLoad_payload_1[1] || _zz_IBusCachedPlugin_jump_pcLoad_payload_2); + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_5 = (_zz_IBusCachedPlugin_jump_pcLoad_payload_1[2] || _zz_IBusCachedPlugin_jump_pcLoad_payload_2); + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_IBusCachedPlugin_jump_pcLoad_payload_6; + always @(*) begin + IBusCachedPlugin_fetchPc_correction = 1'b0; + if(IBusCachedPlugin_fetchPc_redo_valid) begin + IBusCachedPlugin_fetchPc_correction = 1'b1; + end + if(IBusCachedPlugin_jump_pcLoad_valid) begin + IBusCachedPlugin_fetchPc_correction = 1'b1; + end + end + + assign when_Fetcher_l127 = (IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready); + assign IBusCachedPlugin_fetchPc_corrected = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_correctionReg); + always @(*) begin + IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b0; + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready) begin + IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b1; + end + end + + assign when_Fetcher_l131 = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_pcRegPropagate); + assign when_Fetcher_l131_1 = (IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready); + assign when_Fetcher_l131_2 = ((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready); + always @(*) begin + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_IBusCachedPlugin_fetchPc_pc); + if(IBusCachedPlugin_fetchPc_redo_valid) begin + IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload; + end + if(IBusCachedPlugin_jump_pcLoad_valid) begin + IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_jump_pcLoad_payload; + end + IBusCachedPlugin_fetchPc_pc[0] = 1'b0; + IBusCachedPlugin_fetchPc_pc[1] = 1'b0; + end + + always @(*) begin + IBusCachedPlugin_fetchPc_flushed = 1'b0; + if(IBusCachedPlugin_fetchPc_redo_valid) begin + IBusCachedPlugin_fetchPc_flushed = 1'b1; + end + if(IBusCachedPlugin_jump_pcLoad_valid) begin + IBusCachedPlugin_fetchPc_flushed = 1'b1; + end + end + + assign when_Fetcher_l158 = (IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetchPc_correction) || IBusCachedPlugin_fetchPc_pcRegPropagate)); + assign IBusCachedPlugin_fetchPc_output_valid = ((! IBusCachedPlugin_fetcherHalt) && IBusCachedPlugin_fetchPc_booted); + assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_pc; + always @(*) begin + IBusCachedPlugin_iBusRsp_redoFetch = 1'b0; + if(IBusCachedPlugin_rsp_redoFetch) begin + IBusCachedPlugin_iBusRsp_redoFetch = 1'b1; + end + end + + assign IBusCachedPlugin_iBusRsp_stages_0_input_valid = IBusCachedPlugin_fetchPc_output_valid; + assign IBusCachedPlugin_fetchPc_output_ready = IBusCachedPlugin_iBusRsp_stages_0_input_ready; + assign IBusCachedPlugin_iBusRsp_stages_0_input_payload = IBusCachedPlugin_fetchPc_output_payload; + always @(*) begin + IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b0; + if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt) begin + IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b1; + end + end + + assign _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready = (! IBusCachedPlugin_iBusRsp_stages_0_halt); + assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload; + always @(*) begin + IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b0; + if(IBusCachedPlugin_mmuBus_busy) begin + IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b1; + end + end + + assign _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready = (! IBusCachedPlugin_iBusRsp_stages_1_halt); + assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_1_output_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload; + always @(*) begin + IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b0; + if(when_IBusCachedPlugin_l267) begin + IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b1; + end + end + + assign _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready = (! IBusCachedPlugin_iBusRsp_stages_2_halt); + assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_2_output_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; + assign IBusCachedPlugin_fetchPc_redo_valid = IBusCachedPlugin_iBusRsp_redoFetch; + assign IBusCachedPlugin_fetchPc_redo_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; + assign IBusCachedPlugin_iBusRsp_flush = ((decode_arbitration_removeIt || (decode_arbitration_flushNext && (! decode_arbitration_isStuck))) || IBusCachedPlugin_iBusRsp_redoFetch); + assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready; + assign _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready = ((1'b0 && (! _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1 = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2; + assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1; + assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = IBusCachedPlugin_fetchPc_pcReg; + assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid)) || IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready); + assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid = _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload = _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; + assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready = IBusCachedPlugin_iBusRsp_stages_2_input_ready; + assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; + always @(*) begin + IBusCachedPlugin_iBusRsp_readyForError = 1'b1; + if(when_Fetcher_l320) begin + IBusCachedPlugin_iBusRsp_readyForError = 1'b0; + end + end + + assign when_Fetcher_l240 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_stages_2_input_valid); + assign when_Fetcher_l320 = (! IBusCachedPlugin_pcValids_0); + assign when_Fetcher_l329 = (! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready)); + assign when_Fetcher_l329_1 = (! (! IBusCachedPlugin_iBusRsp_stages_2_input_ready)); + assign when_Fetcher_l329_2 = (! execute_arbitration_isStuck); + assign when_Fetcher_l329_3 = (! memory_arbitration_isStuck); + assign when_Fetcher_l329_4 = (! writeBack_arbitration_isStuck); + assign IBusCachedPlugin_pcValids_0 = IBusCachedPlugin_injector_nextPcCalc_valids_1; + assign IBusCachedPlugin_pcValids_1 = IBusCachedPlugin_injector_nextPcCalc_valids_2; + assign IBusCachedPlugin_pcValids_2 = IBusCachedPlugin_injector_nextPcCalc_valids_3; + assign IBusCachedPlugin_pcValids_3 = IBusCachedPlugin_injector_nextPcCalc_valids_4; + assign IBusCachedPlugin_iBusRsp_output_ready = (! decode_arbitration_isStuck); + always @(*) begin + decode_arbitration_isValid = IBusCachedPlugin_iBusRsp_output_valid; + case(switch_Fetcher_l362) + 3'b010 : begin + decode_arbitration_isValid = 1'b1; + end + 3'b011 : begin + decode_arbitration_isValid = 1'b1; + end + default : begin + end + endcase + end + + assign _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch = _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch[11]; + always @(*) begin + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[18] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[17] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[16] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[15] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[14] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[13] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[12] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[11] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[10] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[9] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[8] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[7] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[6] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[5] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[4] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[3] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[2] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[1] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[0] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + end + + always @(*) begin + IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2[31])); + if(_zz_6) begin + IBusCachedPlugin_decodePrediction_cmd_hadBranch = 1'b0; + end + end + + assign _zz_2 = _zz__zz_2[19]; + always @(*) begin + _zz_3[10] = _zz_2; + _zz_3[9] = _zz_2; + _zz_3[8] = _zz_2; + _zz_3[7] = _zz_2; + _zz_3[6] = _zz_2; + _zz_3[5] = _zz_2; + _zz_3[4] = _zz_2; + _zz_3[3] = _zz_2; + _zz_3[2] = _zz_2; + _zz_3[1] = _zz_2; + _zz_3[0] = _zz_2; + end + + assign _zz_4 = _zz__zz_4[11]; + always @(*) begin + _zz_5[18] = _zz_4; + _zz_5[17] = _zz_4; + _zz_5[16] = _zz_4; + _zz_5[15] = _zz_4; + _zz_5[14] = _zz_4; + _zz_5[13] = _zz_4; + _zz_5[12] = _zz_4; + _zz_5[11] = _zz_4; + _zz_5[10] = _zz_4; + _zz_5[9] = _zz_4; + _zz_5[8] = _zz_4; + _zz_5[7] = _zz_4; + _zz_5[6] = _zz_4; + _zz_5[5] = _zz_4; + _zz_5[4] = _zz_4; + _zz_5[3] = _zz_4; + _zz_5[2] = _zz_4; + _zz_5[1] = _zz_4; + _zz_5[0] = _zz_4; + end + + always @(*) begin + case(decode_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JAL : begin + _zz_6 = _zz__zz_6[1]; + end + default : begin + _zz_6 = _zz__zz_6_1[1]; + end + endcase + end + + assign IBusCachedPlugin_predictionJumpInterface_valid = (decode_arbitration_isValid && IBusCachedPlugin_decodePrediction_cmd_hadBranch); + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload = _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload[19]; + always @(*) begin + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[10] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[9] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[8] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[7] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[6] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[5] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[4] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[3] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[2] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[1] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[0] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + end + + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_2 = _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2[11]; + always @(*) begin + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[18] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[17] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[16] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[15] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[14] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[13] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[12] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[11] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[10] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[9] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[8] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[7] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[6] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[5] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[4] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[3] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[2] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[1] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[0] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + end + + assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_IBusCachedPlugin_predictionJumpInterface_payload_1,{{{_zz_IBusCachedPlugin_predictionJumpInterface_payload_4,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_IBusCachedPlugin_predictionJumpInterface_payload_3,{{{_zz_IBusCachedPlugin_predictionJumpInterface_payload_5,_zz_IBusCachedPlugin_predictionJumpInterface_payload_6},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); + assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; + always @(*) begin + iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; + iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; + end + + assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; + assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; + assign IBusCachedPlugin_cache_io_cpu_prefetch_isValid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign IBusCachedPlugin_cache_io_cpu_fetch_isValid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign IBusCachedPlugin_cache_io_cpu_fetch_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_isValid = IBusCachedPlugin_cache_io_cpu_fetch_isValid; + assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload; + assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; + assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush); + assign IBusCachedPlugin_cache_io_cpu_decode_isValid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); + assign IBusCachedPlugin_cache_io_cpu_decode_isStuck = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign IBusCachedPlugin_cache_io_cpu_decode_isUser = (CsrPlugin_privilege == 2'b00); + assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; + assign IBusCachedPlugin_rsp_issueDetected = 1'b0; + always @(*) begin + IBusCachedPlugin_rsp_redoFetch = 1'b0; + if(when_IBusCachedPlugin_l239) begin + IBusCachedPlugin_rsp_redoFetch = 1'b1; + end + if(when_IBusCachedPlugin_l250) begin + IBusCachedPlugin_rsp_redoFetch = 1'b1; + end + end + + always @(*) begin + IBusCachedPlugin_cache_io_cpu_fill_valid = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); + if(when_IBusCachedPlugin_l250) begin + IBusCachedPlugin_cache_io_cpu_fill_valid = 1'b1; + end + end + + always @(*) begin + IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; + if(when_IBusCachedPlugin_l244) begin + IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; + end + if(when_IBusCachedPlugin_l256) begin + IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; + end + end + + always @(*) begin + IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx; + if(when_IBusCachedPlugin_l244) begin + IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100; + end + if(when_IBusCachedPlugin_l256) begin + IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001; + end + end + + assign IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_stages_2_input_payload[31 : 2],2'b00}; + assign when_IBusCachedPlugin_l239 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); + assign when_IBusCachedPlugin_l244 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); + assign when_IBusCachedPlugin_l250 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); + assign when_IBusCachedPlugin_l256 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); + assign when_IBusCachedPlugin_l267 = (IBusCachedPlugin_rsp_issueDetected_4 || IBusCachedPlugin_rsp_iBusRspOutputHalt); + assign IBusCachedPlugin_iBusRsp_output_valid = IBusCachedPlugin_iBusRsp_stages_2_output_valid; + assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready; + assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; + assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload; + assign IBusCachedPlugin_cache_io_flush = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_s2mPipe_rValid); + assign dataCache_1_io_mem_cmd_ready = (! dataCache_1_io_mem_cmd_s2mPipe_rValid); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_wr : dataCache_1_io_mem_cmd_payload_wr); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_address : dataCache_1_io_mem_cmd_payload_address); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_data = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_data : dataCache_1_io_mem_cmd_payload_data); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_mask = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_mask : dataCache_1_io_mem_cmd_payload_mask); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_size = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_size : dataCache_1_io_mem_cmd_payload_size); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_last = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_last : dataCache_1_io_mem_cmd_payload_last); + assign when_Stream_l365 = (dataCache_1_io_mem_cmd_ready && (! dataCache_1_io_mem_cmd_s2mPipe_ready)); + assign dataCache_1_io_mem_cmd_s2mPipe_ready = ((1'b1 && (! dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid)) || dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready); + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid = dataCache_1_io_mem_cmd_s2mPipe_rValid_1; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_rData_wr_1; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_rData_uncached_1; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address = dataCache_1_io_mem_cmd_s2mPipe_rData_address_1; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data = dataCache_1_io_mem_cmd_s2mPipe_rData_data_1; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_rData_mask_1; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size = dataCache_1_io_mem_cmd_s2mPipe_rData_size_1; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last = dataCache_1_io_mem_cmd_s2mPipe_rData_last_1; + assign dBus_cmd_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready = dBus_cmd_ready; + assign dBus_cmd_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; + assign dBus_cmd_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached; + assign dBus_cmd_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; + assign dBus_cmd_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; + assign dBus_cmd_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; + assign dBus_cmd_payload_size = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size; + assign dBus_cmd_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; + assign when_DBusCachedPlugin_l303 = ((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE); + always @(*) begin + _zz_decode_MEMORY_FORCE_CONSTISTENCY = 1'b0; + if(when_DBusCachedPlugin_l311) begin + if(decode_MEMORY_LRSC) begin + _zz_decode_MEMORY_FORCE_CONSTISTENCY = 1'b1; + end + if(decode_MEMORY_AMO) begin + _zz_decode_MEMORY_FORCE_CONSTISTENCY = 1'b1; + end + end + end + + assign when_DBusCachedPlugin_l311 = decode_INSTRUCTION[25]; + assign execute_DBusCachedPlugin_size = execute_INSTRUCTION[13 : 12]; + always @(*) begin + dataCache_1_io_cpu_execute_isValid = (execute_arbitration_isValid && execute_MEMORY_ENABLE); + if(MmuPlugin_dBusAccess_cmd_valid) begin + if(when_DBusCachedPlugin_l498) begin + if(when_DBusCachedPlugin_l499) begin + dataCache_1_io_cpu_execute_isValid = 1'b1; + end + end + end + end + + always @(*) begin + dataCache_1_io_cpu_execute_address = execute_SRC_ADD; + if(MmuPlugin_dBusAccess_cmd_valid) begin + if(when_DBusCachedPlugin_l498) begin + dataCache_1_io_cpu_execute_address = MmuPlugin_dBusAccess_cmd_payload_address; + end + end + end + + always @(*) begin + dataCache_1_io_cpu_execute_args_wr = execute_MEMORY_WR; + if(MmuPlugin_dBusAccess_cmd_valid) begin + if(when_DBusCachedPlugin_l498) begin + dataCache_1_io_cpu_execute_args_wr = 1'b0; + end + end + end + + always @(*) begin + case(execute_DBusCachedPlugin_size) + 2'b00 : begin + _zz_execute_MEMORY_STORE_DATA_RF = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; + end + 2'b01 : begin + _zz_execute_MEMORY_STORE_DATA_RF = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; + end + default : begin + _zz_execute_MEMORY_STORE_DATA_RF = execute_RS2[31 : 0]; + end + endcase + end + + always @(*) begin + dataCache_1_io_cpu_execute_args_size = execute_DBusCachedPlugin_size; + if(MmuPlugin_dBusAccess_cmd_valid) begin + if(when_DBusCachedPlugin_l498) begin + dataCache_1_io_cpu_execute_args_size = MmuPlugin_dBusAccess_cmd_payload_size; + end + end + end + + assign dataCache_1_io_cpu_flush_valid = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); + assign when_DBusCachedPlugin_l343 = ((dataCache_1_io_cpu_flush_valid && (! dataCache_1_io_cpu_flush_ready)) || dataCache_1_io_cpu_execute_haltIt); + always @(*) begin + dataCache_1_io_cpu_execute_args_isLrsc = 1'b0; + if(execute_MEMORY_LRSC) begin + dataCache_1_io_cpu_execute_args_isLrsc = 1'b1; + end + end + + assign dataCache_1_io_cpu_execute_args_amoCtrl_alu = execute_INSTRUCTION[31 : 29]; + assign dataCache_1_io_cpu_execute_args_amoCtrl_swap = execute_INSTRUCTION[27]; + assign when_DBusCachedPlugin_l359 = (dataCache_1_io_cpu_execute_refilling && execute_arbitration_isValid); + always @(*) begin + dataCache_1_io_cpu_memory_isValid = (memory_arbitration_isValid && memory_MEMORY_ENABLE); + if(memory_IS_DBUS_SHARING) begin + dataCache_1_io_cpu_memory_isValid = 1'b1; + end + end + + assign dataCache_1_io_cpu_memory_address = memory_REGFILE_WRITE_DATA; + assign DBusCachedPlugin_mmuBus_cmd_0_isValid = dataCache_1_io_cpu_memory_isValid; + assign DBusCachedPlugin_mmuBus_cmd_0_isStuck = memory_arbitration_isStuck; + assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = dataCache_1_io_cpu_memory_address; + always @(*) begin + DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; + if(memory_IS_DBUS_SHARING) begin + DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b1; + end + end + + assign DBusCachedPlugin_mmuBus_end = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); + always @(*) begin + dataCache_1_io_cpu_memory_mmuRsp_isIoAccess = DBusCachedPlugin_mmuBus_rsp_isIoAccess; + if(when_DBusCachedPlugin_l386) begin + dataCache_1_io_cpu_memory_mmuRsp_isIoAccess = 1'b1; + end + end + + assign when_DBusCachedPlugin_l386 = (_zz_when_DBusCachedPlugin_l386 && (! dataCache_1_io_cpu_memory_isWrite)); + always @(*) begin + dataCache_1_io_cpu_writeBack_isValid = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + if(writeBack_IS_DBUS_SHARING) begin + dataCache_1_io_cpu_writeBack_isValid = 1'b1; + end + if(writeBack_arbitration_haltByOther) begin + dataCache_1_io_cpu_writeBack_isValid = 1'b0; + end + end + + assign dataCache_1_io_cpu_writeBack_isUser = (CsrPlugin_privilege == 2'b00); + assign dataCache_1_io_cpu_writeBack_address = writeBack_REGFILE_WRITE_DATA; + assign dataCache_1_io_cpu_writeBack_storeData[31 : 0] = writeBack_MEMORY_STORE_DATA_RF; + always @(*) begin + DBusCachedPlugin_redoBranch_valid = 1'b0; + if(when_DBusCachedPlugin_l438) begin + if(dataCache_1_io_cpu_redo) begin + DBusCachedPlugin_redoBranch_valid = 1'b1; + end + end + end + + assign DBusCachedPlugin_redoBranch_payload = writeBack_PC; + always @(*) begin + DBusCachedPlugin_exceptionBus_valid = 1'b0; + if(when_DBusCachedPlugin_l438) begin + if(dataCache_1_io_cpu_writeBack_accessError) begin + DBusCachedPlugin_exceptionBus_valid = 1'b1; + end + if(dataCache_1_io_cpu_writeBack_mmuException) begin + DBusCachedPlugin_exceptionBus_valid = 1'b1; + end + if(dataCache_1_io_cpu_writeBack_unalignedAccess) begin + DBusCachedPlugin_exceptionBus_valid = 1'b1; + end + if(dataCache_1_io_cpu_redo) begin + DBusCachedPlugin_exceptionBus_valid = 1'b0; + end + end + end + + assign DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_REGFILE_WRITE_DATA; + always @(*) begin + DBusCachedPlugin_exceptionBus_payload_code = 4'bxxxx; + if(when_DBusCachedPlugin_l438) begin + if(dataCache_1_io_cpu_writeBack_accessError) begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_DBusCachedPlugin_exceptionBus_payload_code}; + end + if(dataCache_1_io_cpu_writeBack_mmuException) begin + DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 4'b1111 : 4'b1101); + end + if(dataCache_1_io_cpu_writeBack_unalignedAccess) begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_DBusCachedPlugin_exceptionBus_payload_code_1}; + end + end + end + + assign when_DBusCachedPlugin_l438 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign when_DBusCachedPlugin_l458 = (dataCache_1_io_cpu_writeBack_isValid && dataCache_1_io_cpu_writeBack_haltIt); + assign writeBack_DBusCachedPlugin_rspSplits_0 = dataCache_1_io_cpu_writeBack_data[7 : 0]; + assign writeBack_DBusCachedPlugin_rspSplits_1 = dataCache_1_io_cpu_writeBack_data[15 : 8]; + assign writeBack_DBusCachedPlugin_rspSplits_2 = dataCache_1_io_cpu_writeBack_data[23 : 16]; + assign writeBack_DBusCachedPlugin_rspSplits_3 = dataCache_1_io_cpu_writeBack_data[31 : 24]; + always @(*) begin + writeBack_DBusCachedPlugin_rspShifted[7 : 0] = _zz_writeBack_DBusCachedPlugin_rspShifted; + writeBack_DBusCachedPlugin_rspShifted[15 : 8] = _zz_writeBack_DBusCachedPlugin_rspShifted_2; + writeBack_DBusCachedPlugin_rspShifted[23 : 16] = writeBack_DBusCachedPlugin_rspSplits_2; + writeBack_DBusCachedPlugin_rspShifted[31 : 24] = writeBack_DBusCachedPlugin_rspSplits_3; + end + + always @(*) begin + writeBack_DBusCachedPlugin_rspRf = writeBack_DBusCachedPlugin_rspShifted[31 : 0]; + if(when_DBusCachedPlugin_l474) begin + writeBack_DBusCachedPlugin_rspRf = {31'd0, _zz_writeBack_DBusCachedPlugin_rspRf}; + end + end + + assign when_DBusCachedPlugin_l474 = (writeBack_MEMORY_LRSC && writeBack_MEMORY_WR); + assign switch_Misc_l199 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_writeBack_DBusCachedPlugin_rspFormated = (writeBack_DBusCachedPlugin_rspRf[7] && (! writeBack_INSTRUCTION[14])); + always @(*) begin + _zz_writeBack_DBusCachedPlugin_rspFormated_1[31] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[30] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[29] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[28] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[27] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[26] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[25] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[24] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[23] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[22] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[21] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[20] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[19] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[18] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[17] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[16] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[15] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[14] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[13] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[12] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[11] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[10] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[9] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[8] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[7 : 0] = writeBack_DBusCachedPlugin_rspRf[7 : 0]; + end + + assign _zz_writeBack_DBusCachedPlugin_rspFormated_2 = (writeBack_DBusCachedPlugin_rspRf[15] && (! writeBack_INSTRUCTION[14])); + always @(*) begin + _zz_writeBack_DBusCachedPlugin_rspFormated_3[31] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[30] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[29] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[28] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[27] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[26] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[25] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[24] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[23] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[22] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[21] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[20] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[19] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[18] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[17] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[16] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[15 : 0] = writeBack_DBusCachedPlugin_rspRf[15 : 0]; + end + + always @(*) begin + case(switch_Misc_l199) + 2'b00 : begin + writeBack_DBusCachedPlugin_rspFormated = _zz_writeBack_DBusCachedPlugin_rspFormated_1; + end + 2'b01 : begin + writeBack_DBusCachedPlugin_rspFormated = _zz_writeBack_DBusCachedPlugin_rspFormated_3; + end + default : begin + writeBack_DBusCachedPlugin_rspFormated = writeBack_DBusCachedPlugin_rspRf; + end + endcase + end + + assign when_DBusCachedPlugin_l484 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + always @(*) begin + MmuPlugin_dBusAccess_cmd_ready = 1'b0; + if(MmuPlugin_dBusAccess_cmd_valid) begin + if(when_DBusCachedPlugin_l498) begin + if(when_DBusCachedPlugin_l499) begin + MmuPlugin_dBusAccess_cmd_ready = (! execute_arbitration_isStuck); + end + end + end + end + + always @(*) begin + DBusCachedPlugin_forceDatapath = 1'b0; + if(MmuPlugin_dBusAccess_cmd_valid) begin + if(when_DBusCachedPlugin_l498) begin + DBusCachedPlugin_forceDatapath = 1'b1; + end + end + end + + assign when_DBusCachedPlugin_l498 = (! ({(writeBack_arbitration_isValid || CsrPlugin_exceptionPendings_3),{(memory_arbitration_isValid || CsrPlugin_exceptionPendings_2),(execute_arbitration_isValid || CsrPlugin_exceptionPendings_1)}} != 3'b000)); + assign when_DBusCachedPlugin_l499 = (! dataCache_1_io_cpu_execute_refilling); + assign MmuPlugin_dBusAccess_rsp_valid = ((writeBack_IS_DBUS_SHARING && (! dataCache_1_io_cpu_writeBack_isWrite)) && (dataCache_1_io_cpu_redo || (! dataCache_1_io_cpu_writeBack_haltIt))); + assign MmuPlugin_dBusAccess_rsp_payload_data = writeBack_DBusCachedPlugin_rspRf; + assign MmuPlugin_dBusAccess_rsp_payload_error = (dataCache_1_io_cpu_writeBack_unalignedAccess || dataCache_1_io_cpu_writeBack_accessError); + assign MmuPlugin_dBusAccess_rsp_payload_redo = dataCache_1_io_cpu_redo; + assign _zz_decode_IS_SFENCE_VMA2_1 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); + assign _zz_decode_IS_SFENCE_VMA2_2 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); + assign _zz_decode_IS_SFENCE_VMA2_3 = ((decode_INSTRUCTION & 32'h00002050) == 32'h00002000); + assign _zz_decode_IS_SFENCE_VMA2_4 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); + assign _zz_decode_IS_SFENCE_VMA2_5 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000004); + assign _zz_decode_IS_SFENCE_VMA2_6 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); + assign _zz_decode_IS_SFENCE_VMA2_7 = ((decode_INSTRUCTION & 32'h02003050) == 32'h02000050); + assign _zz_decode_IS_SFENCE_VMA2 = {({_zz_decode_IS_SFENCE_VMA2_2,(_zz__zz_decode_IS_SFENCE_VMA2 == _zz__zz_decode_IS_SFENCE_VMA2_1)} != 2'b00),{((_zz__zz_decode_IS_SFENCE_VMA2_2 == _zz__zz_decode_IS_SFENCE_VMA2_3) != 1'b0),{(_zz__zz_decode_IS_SFENCE_VMA2_4 != 1'b0),{(_zz__zz_decode_IS_SFENCE_VMA2_5 != _zz__zz_decode_IS_SFENCE_VMA2_6),{_zz__zz_decode_IS_SFENCE_VMA2_7,{_zz__zz_decode_IS_SFENCE_VMA2_8,_zz__zz_decode_IS_SFENCE_VMA2_11}}}}}}; + assign _zz_decode_SRC1_CTRL_2 = _zz_decode_IS_SFENCE_VMA2[2 : 1]; + assign _zz_decode_SRC1_CTRL_1 = _zz_decode_SRC1_CTRL_2; + assign _zz_decode_ALU_CTRL_2 = _zz_decode_IS_SFENCE_VMA2[7 : 6]; + assign _zz_decode_ALU_CTRL_1 = _zz_decode_ALU_CTRL_2; + assign _zz_decode_SRC2_CTRL_2 = _zz_decode_IS_SFENCE_VMA2[9 : 8]; + assign _zz_decode_SRC2_CTRL_1 = _zz_decode_SRC2_CTRL_2; + assign _zz_decode_ALU_BITWISE_CTRL_2 = _zz_decode_IS_SFENCE_VMA2[22 : 21]; + assign _zz_decode_ALU_BITWISE_CTRL_1 = _zz_decode_ALU_BITWISE_CTRL_2; + assign _zz_decode_SHIFT_CTRL_2 = _zz_decode_IS_SFENCE_VMA2[24 : 23]; + assign _zz_decode_SHIFT_CTRL_1 = _zz_decode_SHIFT_CTRL_2; + assign _zz_decode_ENV_CTRL_2 = _zz_decode_IS_SFENCE_VMA2[31 : 30]; + assign _zz_decode_ENV_CTRL_1 = _zz_decode_ENV_CTRL_2; + assign _zz_decode_BRANCH_CTRL_2 = _zz_decode_IS_SFENCE_VMA2[36 : 35]; + assign _zz_decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL_2; + assign decodeExceptionPort_valid = (decode_arbitration_isValid && (! decode_LEGAL_INSTRUCTION)); + assign decodeExceptionPort_payload_code = 4'b0010; + assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; + assign when_RegFilePlugin_l63 = (decode_INSTRUCTION[11 : 7] == 5'h0); + assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; + assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; + assign decode_RegFilePlugin_rs1Data = _zz_RegFilePlugin_regFile_port0; + assign decode_RegFilePlugin_rs2Data = _zz_RegFilePlugin_regFile_port1; + always @(*) begin + lastStageRegFileWrite_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring); + if(_zz_7) begin + lastStageRegFileWrite_valid = 1'b1; + end + end + + always @(*) begin + lastStageRegFileWrite_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7]; + if(_zz_7) begin + lastStageRegFileWrite_payload_address = 5'h0; + end + end + + always @(*) begin + lastStageRegFileWrite_payload_data = _zz_decode_RS2_2; + if(_zz_7) begin + lastStageRegFileWrite_payload_data = 32'h0; + end + end + + always @(*) begin + case(execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_AND : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2); + end + `AluBitwiseCtrlEnum_defaultEncoding_OR : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2); + end + default : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 ^ execute_SRC2); + end + endcase + end + + always @(*) begin + case(execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_BITWISE : begin + _zz_execute_REGFILE_WRITE_DATA = execute_IntAluPlugin_bitwise; + end + `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin + _zz_execute_REGFILE_WRITE_DATA = {31'd0, _zz__zz_execute_REGFILE_WRITE_DATA}; + end + default : begin + _zz_execute_REGFILE_WRITE_DATA = execute_SRC_ADD_SUB; + end + endcase + end + + always @(*) begin + case(decode_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : begin + _zz_decode_SRC1_1 = _zz_decode_SRC1; + end + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin + _zz_decode_SRC1_1 = {29'd0, _zz__zz_decode_SRC1_1}; + end + `Src1CtrlEnum_defaultEncoding_IMU : begin + _zz_decode_SRC1_1 = {decode_INSTRUCTION[31 : 12],12'h0}; + end + default : begin + _zz_decode_SRC1_1 = {27'd0, _zz__zz_decode_SRC1_1_1}; + end + endcase + end + + assign _zz_decode_SRC2_2 = decode_INSTRUCTION[31]; + always @(*) begin + _zz_decode_SRC2_3[19] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[18] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[17] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[16] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[15] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[14] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[13] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[12] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[11] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[10] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[9] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[8] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[7] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[6] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[5] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[4] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[3] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[2] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[1] = _zz_decode_SRC2_2; + _zz_decode_SRC2_3[0] = _zz_decode_SRC2_2; + end + + assign _zz_decode_SRC2_4 = _zz__zz_decode_SRC2_4[11]; + always @(*) begin + _zz_decode_SRC2_5[19] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[18] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[17] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[16] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[15] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[14] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[13] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[12] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[11] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[10] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[9] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[8] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[7] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[6] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[5] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[4] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[3] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[2] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[1] = _zz_decode_SRC2_4; + _zz_decode_SRC2_5[0] = _zz_decode_SRC2_4; + end + + always @(*) begin + case(decode_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : begin + _zz_decode_SRC2_6 = _zz_decode_SRC2_1; + end + `Src2CtrlEnum_defaultEncoding_IMI : begin + _zz_decode_SRC2_6 = {_zz_decode_SRC2_3,decode_INSTRUCTION[31 : 20]}; + end + `Src2CtrlEnum_defaultEncoding_IMS : begin + _zz_decode_SRC2_6 = {_zz_decode_SRC2_5,{decode_INSTRUCTION[31 : 25],decode_INSTRUCTION[11 : 7]}}; + end + default : begin + _zz_decode_SRC2_6 = _zz_decode_SRC2; + end + endcase + end + + always @(*) begin + execute_SrcPlugin_addSub = _zz_execute_SrcPlugin_addSub; + if(execute_SRC2_FORCE_ZERO) begin + execute_SrcPlugin_addSub = execute_SRC1; + end + end + + assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); + assign execute_FullBarrelShifterPlugin_amplitude = execute_SRC2[4 : 0]; + always @(*) begin + _zz_execute_FullBarrelShifterPlugin_reversed[0] = execute_SRC1[31]; + _zz_execute_FullBarrelShifterPlugin_reversed[1] = execute_SRC1[30]; + _zz_execute_FullBarrelShifterPlugin_reversed[2] = execute_SRC1[29]; + _zz_execute_FullBarrelShifterPlugin_reversed[3] = execute_SRC1[28]; + _zz_execute_FullBarrelShifterPlugin_reversed[4] = execute_SRC1[27]; + _zz_execute_FullBarrelShifterPlugin_reversed[5] = execute_SRC1[26]; + _zz_execute_FullBarrelShifterPlugin_reversed[6] = execute_SRC1[25]; + _zz_execute_FullBarrelShifterPlugin_reversed[7] = execute_SRC1[24]; + _zz_execute_FullBarrelShifterPlugin_reversed[8] = execute_SRC1[23]; + _zz_execute_FullBarrelShifterPlugin_reversed[9] = execute_SRC1[22]; + _zz_execute_FullBarrelShifterPlugin_reversed[10] = execute_SRC1[21]; + _zz_execute_FullBarrelShifterPlugin_reversed[11] = execute_SRC1[20]; + _zz_execute_FullBarrelShifterPlugin_reversed[12] = execute_SRC1[19]; + _zz_execute_FullBarrelShifterPlugin_reversed[13] = execute_SRC1[18]; + _zz_execute_FullBarrelShifterPlugin_reversed[14] = execute_SRC1[17]; + _zz_execute_FullBarrelShifterPlugin_reversed[15] = execute_SRC1[16]; + _zz_execute_FullBarrelShifterPlugin_reversed[16] = execute_SRC1[15]; + _zz_execute_FullBarrelShifterPlugin_reversed[17] = execute_SRC1[14]; + _zz_execute_FullBarrelShifterPlugin_reversed[18] = execute_SRC1[13]; + _zz_execute_FullBarrelShifterPlugin_reversed[19] = execute_SRC1[12]; + _zz_execute_FullBarrelShifterPlugin_reversed[20] = execute_SRC1[11]; + _zz_execute_FullBarrelShifterPlugin_reversed[21] = execute_SRC1[10]; + _zz_execute_FullBarrelShifterPlugin_reversed[22] = execute_SRC1[9]; + _zz_execute_FullBarrelShifterPlugin_reversed[23] = execute_SRC1[8]; + _zz_execute_FullBarrelShifterPlugin_reversed[24] = execute_SRC1[7]; + _zz_execute_FullBarrelShifterPlugin_reversed[25] = execute_SRC1[6]; + _zz_execute_FullBarrelShifterPlugin_reversed[26] = execute_SRC1[5]; + _zz_execute_FullBarrelShifterPlugin_reversed[27] = execute_SRC1[4]; + _zz_execute_FullBarrelShifterPlugin_reversed[28] = execute_SRC1[3]; + _zz_execute_FullBarrelShifterPlugin_reversed[29] = execute_SRC1[2]; + _zz_execute_FullBarrelShifterPlugin_reversed[30] = execute_SRC1[1]; + _zz_execute_FullBarrelShifterPlugin_reversed[31] = execute_SRC1[0]; + end + + assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SLL) ? _zz_execute_FullBarrelShifterPlugin_reversed : execute_SRC1); + always @(*) begin + _zz_decode_RS2_3[0] = memory_SHIFT_RIGHT[31]; + _zz_decode_RS2_3[1] = memory_SHIFT_RIGHT[30]; + _zz_decode_RS2_3[2] = memory_SHIFT_RIGHT[29]; + _zz_decode_RS2_3[3] = memory_SHIFT_RIGHT[28]; + _zz_decode_RS2_3[4] = memory_SHIFT_RIGHT[27]; + _zz_decode_RS2_3[5] = memory_SHIFT_RIGHT[26]; + _zz_decode_RS2_3[6] = memory_SHIFT_RIGHT[25]; + _zz_decode_RS2_3[7] = memory_SHIFT_RIGHT[24]; + _zz_decode_RS2_3[8] = memory_SHIFT_RIGHT[23]; + _zz_decode_RS2_3[9] = memory_SHIFT_RIGHT[22]; + _zz_decode_RS2_3[10] = memory_SHIFT_RIGHT[21]; + _zz_decode_RS2_3[11] = memory_SHIFT_RIGHT[20]; + _zz_decode_RS2_3[12] = memory_SHIFT_RIGHT[19]; + _zz_decode_RS2_3[13] = memory_SHIFT_RIGHT[18]; + _zz_decode_RS2_3[14] = memory_SHIFT_RIGHT[17]; + _zz_decode_RS2_3[15] = memory_SHIFT_RIGHT[16]; + _zz_decode_RS2_3[16] = memory_SHIFT_RIGHT[15]; + _zz_decode_RS2_3[17] = memory_SHIFT_RIGHT[14]; + _zz_decode_RS2_3[18] = memory_SHIFT_RIGHT[13]; + _zz_decode_RS2_3[19] = memory_SHIFT_RIGHT[12]; + _zz_decode_RS2_3[20] = memory_SHIFT_RIGHT[11]; + _zz_decode_RS2_3[21] = memory_SHIFT_RIGHT[10]; + _zz_decode_RS2_3[22] = memory_SHIFT_RIGHT[9]; + _zz_decode_RS2_3[23] = memory_SHIFT_RIGHT[8]; + _zz_decode_RS2_3[24] = memory_SHIFT_RIGHT[7]; + _zz_decode_RS2_3[25] = memory_SHIFT_RIGHT[6]; + _zz_decode_RS2_3[26] = memory_SHIFT_RIGHT[5]; + _zz_decode_RS2_3[27] = memory_SHIFT_RIGHT[4]; + _zz_decode_RS2_3[28] = memory_SHIFT_RIGHT[3]; + _zz_decode_RS2_3[29] = memory_SHIFT_RIGHT[2]; + _zz_decode_RS2_3[30] = memory_SHIFT_RIGHT[1]; + _zz_decode_RS2_3[31] = memory_SHIFT_RIGHT[0]; + end + + always @(*) begin + HazardSimplePlugin_src0Hazard = 1'b0; + if(when_HazardSimplePlugin_l57) begin + if(when_HazardSimplePlugin_l58) begin + if(when_HazardSimplePlugin_l48) begin + HazardSimplePlugin_src0Hazard = 1'b1; + end + end + end + if(when_HazardSimplePlugin_l57_1) begin + if(when_HazardSimplePlugin_l58_1) begin + if(when_HazardSimplePlugin_l48_1) begin + HazardSimplePlugin_src0Hazard = 1'b1; + end + end + end + if(when_HazardSimplePlugin_l57_2) begin + if(when_HazardSimplePlugin_l58_2) begin + if(when_HazardSimplePlugin_l48_2) begin + HazardSimplePlugin_src0Hazard = 1'b1; + end + end + end + if(when_HazardSimplePlugin_l105) begin + HazardSimplePlugin_src0Hazard = 1'b0; + end + end + + always @(*) begin + HazardSimplePlugin_src1Hazard = 1'b0; + if(when_HazardSimplePlugin_l57) begin + if(when_HazardSimplePlugin_l58) begin + if(when_HazardSimplePlugin_l51) begin + HazardSimplePlugin_src1Hazard = 1'b1; + end + end + end + if(when_HazardSimplePlugin_l57_1) begin + if(when_HazardSimplePlugin_l58_1) begin + if(when_HazardSimplePlugin_l51_1) begin + HazardSimplePlugin_src1Hazard = 1'b1; + end + end + end + if(when_HazardSimplePlugin_l57_2) begin + if(when_HazardSimplePlugin_l58_2) begin + if(when_HazardSimplePlugin_l51_2) begin + HazardSimplePlugin_src1Hazard = 1'b1; + end + end + end + if(when_HazardSimplePlugin_l108) begin + HazardSimplePlugin_src1Hazard = 1'b0; + end + end + + assign HazardSimplePlugin_writeBackWrites_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring); + assign HazardSimplePlugin_writeBackWrites_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7]; + assign HazardSimplePlugin_writeBackWrites_payload_data = _zz_decode_RS2_2; + assign HazardSimplePlugin_addr0Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[19 : 15]); + assign HazardSimplePlugin_addr1Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l47 = 1'b1; + assign when_HazardSimplePlugin_l48 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l51 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l45 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l57 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58 = (1'b0 || (! when_HazardSimplePlugin_l47)); + assign when_HazardSimplePlugin_l48_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l51_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l45_1 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l57_1 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58_1 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign when_HazardSimplePlugin_l48_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l51_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l45_2 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l57_2 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58_2 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign when_HazardSimplePlugin_l105 = (! decode_RS1_USE); + assign when_HazardSimplePlugin_l108 = (! decode_RS2_USE); + assign when_HazardSimplePlugin_l113 = (decode_arbitration_isValid && (HazardSimplePlugin_src0Hazard || HazardSimplePlugin_src1Hazard)); + assign execute_MulPlugin_a = execute_RS1; + assign execute_MulPlugin_b = execute_RS2; + assign switch_MulPlugin_l87 = execute_INSTRUCTION[13 : 12]; + always @(*) begin + case(switch_MulPlugin_l87) + 2'b01 : begin + execute_MulPlugin_aSigned = 1'b1; + end + 2'b10 : begin + execute_MulPlugin_aSigned = 1'b1; + end + default : begin + execute_MulPlugin_aSigned = 1'b0; + end + endcase + end + + always @(*) begin + case(switch_MulPlugin_l87) + 2'b01 : begin + execute_MulPlugin_bSigned = 1'b1; + end + 2'b10 : begin + execute_MulPlugin_bSigned = 1'b0; + end + default : begin + execute_MulPlugin_bSigned = 1'b0; + end + endcase + end + + assign execute_MulPlugin_aULow = execute_MulPlugin_a[15 : 0]; + assign execute_MulPlugin_bULow = execute_MulPlugin_b[15 : 0]; + assign execute_MulPlugin_aSLow = {1'b0,execute_MulPlugin_a[15 : 0]}; + assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]}; + assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]}; + assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]}; + assign writeBack_MulPlugin_result = ($signed(_zz_writeBack_MulPlugin_result) + $signed(_zz_writeBack_MulPlugin_result_1)); + assign when_MulPlugin_l147 = (writeBack_arbitration_isValid && writeBack_IS_MUL); + assign switch_MulPlugin_l148 = writeBack_INSTRUCTION[13 : 12]; + assign memory_MulDivIterativePlugin_frontendOk = 1'b1; + always @(*) begin + memory_MulDivIterativePlugin_div_counter_willIncrement = 1'b0; + if(when_MulDivIterativePlugin_l128) begin + if(when_MulDivIterativePlugin_l132) begin + memory_MulDivIterativePlugin_div_counter_willIncrement = 1'b1; + end + end + end + + always @(*) begin + memory_MulDivIterativePlugin_div_counter_willClear = 1'b0; + if(when_MulDivIterativePlugin_l162) begin + memory_MulDivIterativePlugin_div_counter_willClear = 1'b1; + end + end + + assign memory_MulDivIterativePlugin_div_counter_willOverflowIfInc = (memory_MulDivIterativePlugin_div_counter_value == 6'h21); + assign memory_MulDivIterativePlugin_div_counter_willOverflow = (memory_MulDivIterativePlugin_div_counter_willOverflowIfInc && memory_MulDivIterativePlugin_div_counter_willIncrement); + always @(*) begin + if(memory_MulDivIterativePlugin_div_counter_willOverflow) begin + memory_MulDivIterativePlugin_div_counter_valueNext = 6'h0; + end else begin + memory_MulDivIterativePlugin_div_counter_valueNext = (memory_MulDivIterativePlugin_div_counter_value + _zz_memory_MulDivIterativePlugin_div_counter_valueNext); + end + if(memory_MulDivIterativePlugin_div_counter_willClear) begin + memory_MulDivIterativePlugin_div_counter_valueNext = 6'h0; + end + end + + assign when_MulDivIterativePlugin_l126 = (memory_MulDivIterativePlugin_div_counter_value == 6'h20); + assign when_MulDivIterativePlugin_l126_1 = (! memory_arbitration_isStuck); + assign when_MulDivIterativePlugin_l128 = (memory_arbitration_isValid && memory_IS_DIV); + assign when_MulDivIterativePlugin_l129 = ((! memory_MulDivIterativePlugin_frontendOk) || (! memory_MulDivIterativePlugin_div_done)); + assign when_MulDivIterativePlugin_l132 = (memory_MulDivIterativePlugin_frontendOk && (! memory_MulDivIterativePlugin_div_done)); + assign _zz_memory_MulDivIterativePlugin_div_stage_0_remainderShifted = memory_MulDivIterativePlugin_rs1[31 : 0]; + assign memory_MulDivIterativePlugin_div_stage_0_remainderShifted = {memory_MulDivIterativePlugin_accumulator[31 : 0],_zz_memory_MulDivIterativePlugin_div_stage_0_remainderShifted[31]}; + assign memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator = (memory_MulDivIterativePlugin_div_stage_0_remainderShifted - _zz_memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator); + assign memory_MulDivIterativePlugin_div_stage_0_outRemainder = ((! memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_memory_MulDivIterativePlugin_div_stage_0_outRemainder : _zz_memory_MulDivIterativePlugin_div_stage_0_outRemainder_1); + assign memory_MulDivIterativePlugin_div_stage_0_outNumerator = _zz_memory_MulDivIterativePlugin_div_stage_0_outNumerator[31:0]; + assign when_MulDivIterativePlugin_l151 = (memory_MulDivIterativePlugin_div_counter_value == 6'h20); + assign _zz_memory_MulDivIterativePlugin_div_result = (memory_INSTRUCTION[13] ? memory_MulDivIterativePlugin_accumulator[31 : 0] : memory_MulDivIterativePlugin_rs1[31 : 0]); + assign when_MulDivIterativePlugin_l162 = (! memory_arbitration_isStuck); + assign _zz_memory_MulDivIterativePlugin_rs2 = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_memory_MulDivIterativePlugin_rs1 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); + always @(*) begin + _zz_memory_MulDivIterativePlugin_rs1_1[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_memory_MulDivIterativePlugin_rs1_1[31 : 0] = execute_RS1; + end + + always @(*) begin + CsrPlugin_privilege = _zz_CsrPlugin_privilege; + if(CsrPlugin_forceMachineWire) begin + CsrPlugin_privilege = 2'b11; + end + end + + assign CsrPlugin_misa_base = 2'b01; + assign CsrPlugin_misa_extensions = 26'h0; + assign CsrPlugin_sip_SEIP_OR = (CsrPlugin_sip_SEIP_SOFT || CsrPlugin_sip_SEIP_INPUT); + always @(*) begin + CsrPlugin_redoInterface_valid = 1'b0; + if(CsrPlugin_rescheduleLogic_rescheduleNext) begin + CsrPlugin_redoInterface_valid = 1'b1; + end + end + + assign CsrPlugin_redoInterface_payload = decode_PC; + always @(*) begin + CsrPlugin_rescheduleLogic_rescheduleNext = 1'b0; + if(when_CsrPlugin_l803) begin + CsrPlugin_rescheduleLogic_rescheduleNext = 1'b1; + end + if(execute_CsrPlugin_csr_384) begin + if(execute_CsrPlugin_writeInstruction) begin + CsrPlugin_rescheduleLogic_rescheduleNext = 1'b1; + end + end + end + + assign when_CsrPlugin_l803 = (execute_arbitration_isValid && execute_IS_SFENCE_VMA); + assign _zz_when_CsrPlugin_l952 = (CsrPlugin_sip_STIP && CsrPlugin_sie_STIE); + assign _zz_when_CsrPlugin_l952_1 = (CsrPlugin_sip_SSIP && CsrPlugin_sie_SSIE); + assign _zz_when_CsrPlugin_l952_2 = (CsrPlugin_sip_SEIP_OR && CsrPlugin_sie_SEIE); + assign _zz_when_CsrPlugin_l952_3 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_when_CsrPlugin_l952_4 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_when_CsrPlugin_l952_5 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + always @(*) begin + CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; + case(CsrPlugin_exceptionPortCtrl_exceptionContext_code) + 4'b0000 : begin + if(when_CsrPlugin_l866) begin + CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; + end + end + 4'b0001 : begin + if(when_CsrPlugin_l866_1) begin + CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; + end + end + 4'b0010 : begin + if(when_CsrPlugin_l866_2) begin + CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; + end + end + 4'b0100 : begin + if(when_CsrPlugin_l866_3) begin + CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; + end + end + 4'b0101 : begin + if(when_CsrPlugin_l866_4) begin + CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; + end + end + 4'b0110 : begin + if(when_CsrPlugin_l866_5) begin + CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; + end + end + 4'b0111 : begin + if(when_CsrPlugin_l866_6) begin + CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; + end + end + 4'b1000 : begin + if(when_CsrPlugin_l866_7) begin + CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; + end + end + 4'b1001 : begin + if(when_CsrPlugin_l866_8) begin + CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; + end + end + 4'b1100 : begin + if(when_CsrPlugin_l866_9) begin + CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; + end + end + 4'b1101 : begin + if(when_CsrPlugin_l866_10) begin + CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; + end + end + 4'b1111 : begin + if(when_CsrPlugin_l866_11) begin + CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; + end + end + default : begin + end + endcase + end + + assign when_CsrPlugin_l866 = ((1'b1 && CsrPlugin_medeleg_IAM) && (! 1'b0)); + assign when_CsrPlugin_l866_1 = ((1'b1 && CsrPlugin_medeleg_IAF) && (! 1'b0)); + assign when_CsrPlugin_l866_2 = ((1'b1 && CsrPlugin_medeleg_II) && (! 1'b0)); + assign when_CsrPlugin_l866_3 = ((1'b1 && CsrPlugin_medeleg_LAM) && (! 1'b0)); + assign when_CsrPlugin_l866_4 = ((1'b1 && CsrPlugin_medeleg_LAF) && (! 1'b0)); + assign when_CsrPlugin_l866_5 = ((1'b1 && CsrPlugin_medeleg_SAM) && (! 1'b0)); + assign when_CsrPlugin_l866_6 = ((1'b1 && CsrPlugin_medeleg_SAF) && (! 1'b0)); + assign when_CsrPlugin_l866_7 = ((1'b1 && CsrPlugin_medeleg_EU) && (! 1'b0)); + assign when_CsrPlugin_l866_8 = ((1'b1 && CsrPlugin_medeleg_ES) && (! 1'b0)); + assign when_CsrPlugin_l866_9 = ((1'b1 && CsrPlugin_medeleg_IPF) && (! 1'b0)); + assign when_CsrPlugin_l866_10 = ((1'b1 && CsrPlugin_medeleg_LPF) && (! 1'b0)); + assign when_CsrPlugin_l866_11 = ((1'b1 && CsrPlugin_medeleg_SPF) && (! 1'b0)); + assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); + assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; + assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 = _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1[0]; + always @(*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + if(_zz_when) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; + end + if(decode_arbitration_isFlushed) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b0; + end + end + + always @(*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + if(CsrPlugin_selfException_valid) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1; + end + if(execute_arbitration_isFlushed) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b0; + end + end + + always @(*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + if(BranchPlugin_branchExceptionPort_valid) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1; + end + if(memory_arbitration_isFlushed) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b0; + end + end + + always @(*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + if(DBusCachedPlugin_exceptionBus_valid) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b1; + end + if(writeBack_arbitration_isFlushed) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b0; + end + end + + assign when_CsrPlugin_l909 = (! decode_arbitration_isStuck); + assign when_CsrPlugin_l909_1 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l909_2 = (! memory_arbitration_isStuck); + assign when_CsrPlugin_l909_3 = (! writeBack_arbitration_isStuck); + assign when_CsrPlugin_l922 = ({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000); + assign CsrPlugin_exceptionPendings_0 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + assign CsrPlugin_exceptionPendings_1 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + assign CsrPlugin_exceptionPendings_2 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + assign CsrPlugin_exceptionPendings_3 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + assign when_CsrPlugin_l946 = ((CsrPlugin_sstatus_SIE && (CsrPlugin_privilege == 2'b01)) || (CsrPlugin_privilege < 2'b01)); + assign when_CsrPlugin_l946_1 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign when_CsrPlugin_l952 = ((_zz_when_CsrPlugin_l952 && (1'b1 && CsrPlugin_mideleg_ST)) && (! 1'b0)); + assign when_CsrPlugin_l952_1 = ((_zz_when_CsrPlugin_l952_1 && (1'b1 && CsrPlugin_mideleg_SS)) && (! 1'b0)); + assign when_CsrPlugin_l952_2 = ((_zz_when_CsrPlugin_l952_2 && (1'b1 && CsrPlugin_mideleg_SE)) && (! 1'b0)); + assign when_CsrPlugin_l952_3 = ((_zz_when_CsrPlugin_l952 && 1'b1) && (! (CsrPlugin_mideleg_ST != 1'b0))); + assign when_CsrPlugin_l952_4 = ((_zz_when_CsrPlugin_l952_1 && 1'b1) && (! (CsrPlugin_mideleg_SS != 1'b0))); + assign when_CsrPlugin_l952_5 = ((_zz_when_CsrPlugin_l952_2 && 1'b1) && (! (CsrPlugin_mideleg_SE != 1'b0))); + assign when_CsrPlugin_l952_6 = ((_zz_when_CsrPlugin_l952_3 && 1'b1) && (! 1'b0)); + assign when_CsrPlugin_l952_7 = ((_zz_when_CsrPlugin_l952_4 && 1'b1) && (! 1'b0)); + assign when_CsrPlugin_l952_8 = ((_zz_when_CsrPlugin_l952_5 && 1'b1) && (! 1'b0)); + assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && CsrPlugin_allowException); + assign CsrPlugin_pipelineLiberator_active = ((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts) && decode_arbitration_isValid); + assign when_CsrPlugin_l980 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l980_1 = (! memory_arbitration_isStuck); + assign when_CsrPlugin_l980_2 = (! writeBack_arbitration_isStuck); + assign when_CsrPlugin_l985 = ((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt); + always @(*) begin + CsrPlugin_pipelineLiberator_done = CsrPlugin_pipelineLiberator_pcValids_2; + if(when_CsrPlugin_l991) begin + CsrPlugin_pipelineLiberator_done = 1'b0; + end + if(CsrPlugin_hadException) begin + CsrPlugin_pipelineLiberator_done = 1'b0; + end + end + + assign when_CsrPlugin_l991 = ({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000); + assign CsrPlugin_interruptJump = ((CsrPlugin_interrupt_valid && CsrPlugin_pipelineLiberator_done) && CsrPlugin_allowInterrupts); + always @(*) begin + CsrPlugin_targetPrivilege = CsrPlugin_interrupt_targetPrivilege; + if(CsrPlugin_hadException) begin + CsrPlugin_targetPrivilege = CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; + end + end + + always @(*) begin + CsrPlugin_trapCause = CsrPlugin_interrupt_code; + if(CsrPlugin_hadException) begin + CsrPlugin_trapCause = CsrPlugin_exceptionPortCtrl_exceptionContext_code; + end + end + + always @(*) begin + CsrPlugin_xtvec_mode = 2'bxx; + case(CsrPlugin_targetPrivilege) + 2'b01 : begin + CsrPlugin_xtvec_mode = CsrPlugin_stvec_mode; + end + 2'b11 : begin + CsrPlugin_xtvec_mode = CsrPlugin_mtvec_mode; + end + default : begin + end + endcase + end + + always @(*) begin + CsrPlugin_xtvec_base = 30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + case(CsrPlugin_targetPrivilege) + 2'b01 : begin + CsrPlugin_xtvec_base = CsrPlugin_stvec_base; + end + 2'b11 : begin + CsrPlugin_xtvec_base = CsrPlugin_mtvec_base; + end + default : begin + end + endcase + end + + assign when_CsrPlugin_l1019 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign when_CsrPlugin_l1064 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); + assign switch_CsrPlugin_l1068 = writeBack_INSTRUCTION[29 : 28]; + assign contextSwitching = CsrPlugin_jumpInterface_valid; + assign when_CsrPlugin_l1108 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); + assign when_CsrPlugin_l1110 = (! execute_CsrPlugin_wfiWake); + assign when_CsrPlugin_l1116 = ({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET))}} != 3'b000); + assign execute_CsrPlugin_blockedBySideEffects = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) || 1'b0); + always @(*) begin + execute_CsrPlugin_illegalAccess = 1'b1; + if(execute_CsrPlugin_csr_3857) begin + if(execute_CSR_READ_OPCODE) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_3858) begin + if(execute_CSR_READ_OPCODE) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_3859) begin + if(execute_CSR_READ_OPCODE) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_3860) begin + if(execute_CSR_READ_OPCODE) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_768) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_836) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_772) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_773) begin + if(execute_CSR_WRITE_OPCODE) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_833) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_832) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_834) begin + if(execute_CSR_READ_OPCODE) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_835) begin + if(execute_CSR_READ_OPCODE) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_770) begin + if(execute_CSR_WRITE_OPCODE) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_771) begin + if(execute_CSR_WRITE_OPCODE) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_256) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_324) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_260) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_261) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_321) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_320) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_322) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_323) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_384) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(CsrPlugin_csrMapping_allowCsrSignal) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(when_CsrPlugin_l1297) begin + execute_CsrPlugin_illegalAccess = 1'b1; + end + if(when_CsrPlugin_l1302) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + + always @(*) begin + execute_CsrPlugin_illegalInstruction = 1'b0; + if(when_CsrPlugin_l1136) begin + if(when_CsrPlugin_l1137) begin + execute_CsrPlugin_illegalInstruction = 1'b1; + end + end + end + + always @(*) begin + CsrPlugin_selfException_valid = 1'b0; + if(when_CsrPlugin_l1129) begin + CsrPlugin_selfException_valid = 1'b1; + end + if(when_CsrPlugin_l1144) begin + CsrPlugin_selfException_valid = 1'b1; + end + end + + always @(*) begin + CsrPlugin_selfException_payload_code = 4'bxxxx; + if(when_CsrPlugin_l1129) begin + CsrPlugin_selfException_payload_code = 4'b0010; + end + if(when_CsrPlugin_l1144) begin + case(CsrPlugin_privilege) + 2'b00 : begin + CsrPlugin_selfException_payload_code = 4'b1000; + end + 2'b01 : begin + CsrPlugin_selfException_payload_code = 4'b1001; + end + default : begin + CsrPlugin_selfException_payload_code = 4'b1011; + end + endcase + end + end + + assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; + assign when_CsrPlugin_l1129 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); + assign when_CsrPlugin_l1136 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); + assign when_CsrPlugin_l1137 = (CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]); + assign when_CsrPlugin_l1144 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); + always @(*) begin + execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); + if(when_CsrPlugin_l1297) begin + execute_CsrPlugin_writeInstruction = 1'b0; + end + end + + always @(*) begin + execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); + if(when_CsrPlugin_l1297) begin + execute_CsrPlugin_readInstruction = 1'b0; + end + end + + assign execute_CsrPlugin_writeEnable = (execute_CsrPlugin_writeInstruction && (! execute_arbitration_isStuck)); + assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); + assign CsrPlugin_csrMapping_hazardFree = (! execute_CsrPlugin_blockedBySideEffects); + always @(*) begin + execute_CsrPlugin_readToWriteData = CsrPlugin_csrMapping_readDataSignal; + if(execute_CsrPlugin_csr_836) begin + execute_CsrPlugin_readToWriteData[9 : 9] = CsrPlugin_sip_SEIP_SOFT; + end + if(execute_CsrPlugin_csr_324) begin + execute_CsrPlugin_readToWriteData[9 : 9] = CsrPlugin_sip_SEIP_SOFT; + end + end + + assign switch_Misc_l199_1 = execute_INSTRUCTION[13]; + always @(*) begin + case(switch_Misc_l199_1) + 1'b0 : begin + _zz_CsrPlugin_csrMapping_writeDataSignal = execute_SRC1; + end + default : begin + _zz_CsrPlugin_csrMapping_writeDataSignal = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); + end + endcase + end + + assign CsrPlugin_csrMapping_writeDataSignal = _zz_CsrPlugin_csrMapping_writeDataSignal; + assign when_CsrPlugin_l1176 = (execute_arbitration_isValid && execute_IS_CSR); + assign when_CsrPlugin_l1180 = (execute_arbitration_isValid && (execute_IS_CSR || execute_IS_SFENCE_VMA)); + assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; + assign when_DebugPlugin_l225 = (DebugPlugin_haltIt && (! DebugPlugin_isPipBusy)); + assign DebugPlugin_allowEBreak = (DebugPlugin_debugUsed && (! DebugPlugin_disableEbreak)); + always @(*) begin + debug_bus_cmd_ready = 1'b1; + if(debug_bus_cmd_valid) begin + case(switch_DebugPlugin_l256) + 6'h01 : begin + if(debug_bus_cmd_payload_wr) begin + debug_bus_cmd_ready = IBusCachedPlugin_injectionPort_ready; + end + end + default : begin + end + endcase + end + end + + always @(*) begin + debug_bus_rsp_data = DebugPlugin_busReadDataReg; + if(when_DebugPlugin_l244) begin + debug_bus_rsp_data[0] = DebugPlugin_resetIt; + debug_bus_rsp_data[1] = DebugPlugin_haltIt; + debug_bus_rsp_data[2] = DebugPlugin_isPipBusy; + debug_bus_rsp_data[3] = DebugPlugin_haltedByBreak; + debug_bus_rsp_data[4] = DebugPlugin_stepIt; + end + end + + assign when_DebugPlugin_l244 = (! _zz_when_DebugPlugin_l244); + always @(*) begin + IBusCachedPlugin_injectionPort_valid = 1'b0; + if(debug_bus_cmd_valid) begin + case(switch_DebugPlugin_l256) + 6'h01 : begin + if(debug_bus_cmd_payload_wr) begin + IBusCachedPlugin_injectionPort_valid = 1'b1; + end + end + default : begin + end + endcase + end + end + + assign IBusCachedPlugin_injectionPort_payload = debug_bus_cmd_payload_data; + assign switch_DebugPlugin_l256 = debug_bus_cmd_payload_address[7 : 2]; + assign when_DebugPlugin_l260 = debug_bus_cmd_payload_data[16]; + assign when_DebugPlugin_l260_1 = debug_bus_cmd_payload_data[24]; + assign when_DebugPlugin_l261 = debug_bus_cmd_payload_data[17]; + assign when_DebugPlugin_l261_1 = debug_bus_cmd_payload_data[25]; + assign when_DebugPlugin_l262 = debug_bus_cmd_payload_data[25]; + assign when_DebugPlugin_l263 = debug_bus_cmd_payload_data[25]; + assign when_DebugPlugin_l264 = debug_bus_cmd_payload_data[18]; + assign when_DebugPlugin_l264_1 = debug_bus_cmd_payload_data[26]; + assign when_DebugPlugin_l284 = (execute_arbitration_isValid && execute_DO_EBREAK); + assign when_DebugPlugin_l287 = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) == 1'b0); + assign when_DebugPlugin_l300 = (DebugPlugin_stepIt && IBusCachedPlugin_incomingInstruction); + assign debug_resetOut = DebugPlugin_resetIt_regNext; + assign when_DebugPlugin_l316 = (DebugPlugin_haltIt || DebugPlugin_stepIt); + assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); + assign switch_Misc_l199_2 = execute_INSTRUCTION[14 : 12]; + always @(*) begin + casez(switch_Misc_l199_2) + 3'b000 : begin + _zz_execute_BRANCH_COND_RESULT = execute_BranchPlugin_eq; + end + 3'b001 : begin + _zz_execute_BRANCH_COND_RESULT = (! execute_BranchPlugin_eq); + end + 3'b1?1 : begin + _zz_execute_BRANCH_COND_RESULT = (! execute_SRC_LESS); + end + default : begin + _zz_execute_BRANCH_COND_RESULT = execute_SRC_LESS; + end + endcase + end + + always @(*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : begin + _zz_execute_BRANCH_COND_RESULT_1 = 1'b0; + end + `BranchCtrlEnum_defaultEncoding_JAL : begin + _zz_execute_BRANCH_COND_RESULT_1 = 1'b1; + end + `BranchCtrlEnum_defaultEncoding_JALR : begin + _zz_execute_BRANCH_COND_RESULT_1 = 1'b1; + end + default : begin + _zz_execute_BRANCH_COND_RESULT_1 = _zz_execute_BRANCH_COND_RESULT; + end + endcase + end + + assign _zz_execute_BranchPlugin_missAlignedTarget = execute_INSTRUCTION[31]; + always @(*) begin + _zz_execute_BranchPlugin_missAlignedTarget_1[19] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[18] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[17] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[16] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[15] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[14] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[13] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[12] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[11] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[10] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[9] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[8] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[7] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[6] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[5] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[4] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[3] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[2] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[1] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[0] = _zz_execute_BranchPlugin_missAlignedTarget; + end + + assign _zz_execute_BranchPlugin_missAlignedTarget_2 = _zz__zz_execute_BranchPlugin_missAlignedTarget_2[19]; + always @(*) begin + _zz_execute_BranchPlugin_missAlignedTarget_3[10] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[9] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[8] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[7] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[6] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[5] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[4] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[3] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[2] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[1] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[0] = _zz_execute_BranchPlugin_missAlignedTarget_2; + end + + assign _zz_execute_BranchPlugin_missAlignedTarget_4 = _zz__zz_execute_BranchPlugin_missAlignedTarget_4[11]; + always @(*) begin + _zz_execute_BranchPlugin_missAlignedTarget_5[18] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[17] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[16] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[15] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[14] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[13] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[12] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[11] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[10] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[9] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[8] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[7] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[6] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[5] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[4] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[3] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[2] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[1] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[0] = _zz_execute_BranchPlugin_missAlignedTarget_4; + end + + always @(*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JALR : begin + _zz_execute_BranchPlugin_missAlignedTarget_6 = (_zz__zz_execute_BranchPlugin_missAlignedTarget_6[1] ^ execute_RS1[1]); + end + `BranchCtrlEnum_defaultEncoding_JAL : begin + _zz_execute_BranchPlugin_missAlignedTarget_6 = _zz__zz_execute_BranchPlugin_missAlignedTarget_6_1[1]; + end + default : begin + _zz_execute_BranchPlugin_missAlignedTarget_6 = _zz__zz_execute_BranchPlugin_missAlignedTarget_6_2[1]; + end + endcase + end + + assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_execute_BranchPlugin_missAlignedTarget_6); + always @(*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JALR : begin + execute_BranchPlugin_branch_src1 = execute_RS1; + end + default : begin + execute_BranchPlugin_branch_src1 = execute_PC; + end + endcase + end + + assign _zz_execute_BranchPlugin_branch_src2 = execute_INSTRUCTION[31]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_1[19] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[18] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[17] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[16] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[15] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[14] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[13] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[12] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[11] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[10] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[9] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[8] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[7] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[6] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[5] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[4] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[3] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[2] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[1] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[0] = _zz_execute_BranchPlugin_branch_src2; + end + + always @(*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JALR : begin + execute_BranchPlugin_branch_src2 = {_zz_execute_BranchPlugin_branch_src2_1,execute_INSTRUCTION[31 : 20]}; + end + default : begin + execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_execute_BranchPlugin_branch_src2_3,{{{_zz_execute_BranchPlugin_branch_src2_6,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_execute_BranchPlugin_branch_src2_5,{{{_zz_execute_BranchPlugin_branch_src2_7,_zz_execute_BranchPlugin_branch_src2_8},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); + if(execute_PREDICTION_HAD_BRANCHED2) begin + execute_BranchPlugin_branch_src2 = {29'd0, _zz_execute_BranchPlugin_branch_src2_9}; + end + end + endcase + end + + assign _zz_execute_BranchPlugin_branch_src2_2 = _zz__zz_execute_BranchPlugin_branch_src2_2[19]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_3[10] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[9] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[8] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[7] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[6] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[5] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[4] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[3] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[2] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[1] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[0] = _zz_execute_BranchPlugin_branch_src2_2; + end + + assign _zz_execute_BranchPlugin_branch_src2_4 = _zz__zz_execute_BranchPlugin_branch_src2_4[11]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_5[18] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[17] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[16] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[15] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[14] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[13] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[12] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[11] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[10] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[9] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[8] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[7] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[6] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[5] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[4] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[3] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[2] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[1] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[0] = _zz_execute_BranchPlugin_branch_src2_4; + end + + assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); + assign BranchPlugin_jumpInterface_valid = ((memory_arbitration_isValid && memory_BRANCH_DO) && (! 1'b0)); + assign BranchPlugin_jumpInterface_payload = memory_BRANCH_CALC; + assign BranchPlugin_branchExceptionPort_valid = (memory_arbitration_isValid && (memory_BRANCH_DO && memory_BRANCH_CALC[1])); + assign BranchPlugin_branchExceptionPort_payload_code = 4'b0000; + assign BranchPlugin_branchExceptionPort_payload_badAddr = memory_BRANCH_CALC; + assign IBusCachedPlugin_decodePrediction_rsp_wasWrong = BranchPlugin_jumpInterface_valid; + assign MmuPlugin_ports_0_dirty = 1'b0; + always @(*) begin + MmuPlugin_ports_0_requireMmuLockupCalc = ((1'b1 && (! IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation)) && MmuPlugin_satp_mode); + if(when_MmuPlugin_l125) begin + MmuPlugin_ports_0_requireMmuLockupCalc = 1'b0; + end + if(when_MmuPlugin_l126) begin + MmuPlugin_ports_0_requireMmuLockupCalc = 1'b0; + end + end + + assign when_MmuPlugin_l125 = ((! MmuPlugin_status_mprv) && (CsrPlugin_privilege == 2'b11)); + assign when_MmuPlugin_l126 = (CsrPlugin_privilege == 2'b11); + assign MmuPlugin_ports_0_cacheHitsCalc = {((MmuPlugin_ports_0_cache_3_valid && (MmuPlugin_ports_0_cache_3_virtualAddress_1 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22])) && (MmuPlugin_ports_0_cache_3_superPage || (MmuPlugin_ports_0_cache_3_virtualAddress_0 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]))),{((MmuPlugin_ports_0_cache_2_valid && (MmuPlugin_ports_0_cache_2_virtualAddress_1 == _zz_MmuPlugin_ports_0_cacheHitsCalc)) && (MmuPlugin_ports_0_cache_2_superPage || (MmuPlugin_ports_0_cache_2_virtualAddress_0 == _zz_MmuPlugin_ports_0_cacheHitsCalc_1))),{((MmuPlugin_ports_0_cache_1_valid && _zz_MmuPlugin_ports_0_cacheHitsCalc_2) && (MmuPlugin_ports_0_cache_1_superPage || _zz_MmuPlugin_ports_0_cacheHitsCalc_3)),((MmuPlugin_ports_0_cache_0_valid && _zz_MmuPlugin_ports_0_cacheHitsCalc_4) && (MmuPlugin_ports_0_cache_0_superPage || _zz_MmuPlugin_ports_0_cacheHitsCalc_5))}}}; + assign MmuPlugin_ports_0_cacheHit = (MmuPlugin_ports_0_cacheHitsCalc != 4'b0000); + assign _zz_MmuPlugin_ports_0_cacheLine_valid = MmuPlugin_ports_0_cacheHitsCalc[3]; + assign _zz_MmuPlugin_ports_0_cacheLine_valid_1 = (MmuPlugin_ports_0_cacheHitsCalc[1] || _zz_MmuPlugin_ports_0_cacheLine_valid); + assign _zz_MmuPlugin_ports_0_cacheLine_valid_2 = (MmuPlugin_ports_0_cacheHitsCalc[2] || _zz_MmuPlugin_ports_0_cacheLine_valid); + assign _zz_MmuPlugin_ports_0_cacheLine_valid_3 = {_zz_MmuPlugin_ports_0_cacheLine_valid_2,_zz_MmuPlugin_ports_0_cacheLine_valid_1}; + assign MmuPlugin_ports_0_cacheLine_valid = _zz_MmuPlugin_ports_0_cacheLine_valid_4; + assign MmuPlugin_ports_0_cacheLine_exception = _zz_MmuPlugin_ports_0_cacheLine_exception; + assign MmuPlugin_ports_0_cacheLine_superPage = _zz_MmuPlugin_ports_0_cacheLine_superPage; + assign MmuPlugin_ports_0_cacheLine_virtualAddress_0 = _zz_MmuPlugin_ports_0_cacheLine_virtualAddress_0; + assign MmuPlugin_ports_0_cacheLine_virtualAddress_1 = _zz_MmuPlugin_ports_0_cacheLine_virtualAddress_1; + assign MmuPlugin_ports_0_cacheLine_physicalAddress_0 = _zz_MmuPlugin_ports_0_cacheLine_physicalAddress_0; + assign MmuPlugin_ports_0_cacheLine_physicalAddress_1 = _zz_MmuPlugin_ports_0_cacheLine_physicalAddress_1; + assign MmuPlugin_ports_0_cacheLine_allowRead = _zz_MmuPlugin_ports_0_cacheLine_allowRead; + assign MmuPlugin_ports_0_cacheLine_allowWrite = _zz_MmuPlugin_ports_0_cacheLine_allowWrite; + assign MmuPlugin_ports_0_cacheLine_allowExecute = _zz_MmuPlugin_ports_0_cacheLine_allowExecute; + assign MmuPlugin_ports_0_cacheLine_allowUser = _zz_MmuPlugin_ports_0_cacheLine_allowUser; + always @(*) begin + MmuPlugin_ports_0_entryToReplace_willIncrement = 1'b0; + if(when_MmuPlugin_l272) begin + if(when_MmuPlugin_l274) begin + MmuPlugin_ports_0_entryToReplace_willIncrement = 1'b1; + end + end + end + + assign MmuPlugin_ports_0_entryToReplace_willClear = 1'b0; + assign MmuPlugin_ports_0_entryToReplace_willOverflowIfInc = (MmuPlugin_ports_0_entryToReplace_value == 2'b11); + assign MmuPlugin_ports_0_entryToReplace_willOverflow = (MmuPlugin_ports_0_entryToReplace_willOverflowIfInc && MmuPlugin_ports_0_entryToReplace_willIncrement); + always @(*) begin + MmuPlugin_ports_0_entryToReplace_valueNext = (MmuPlugin_ports_0_entryToReplace_value + _zz_MmuPlugin_ports_0_entryToReplace_valueNext); + if(MmuPlugin_ports_0_entryToReplace_willClear) begin + MmuPlugin_ports_0_entryToReplace_valueNext = 2'b00; + end + end + + always @(*) begin + if(MmuPlugin_ports_0_requireMmuLockupCalc) begin + IBusCachedPlugin_mmuBus_rsp_physicalAddress = {{MmuPlugin_ports_0_cacheLine_physicalAddress_1,(MmuPlugin_ports_0_cacheLine_superPage ? IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_0_cacheLine_physicalAddress_0)},IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; + end else begin + IBusCachedPlugin_mmuBus_rsp_physicalAddress = IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + end + end + + always @(*) begin + if(MmuPlugin_ports_0_requireMmuLockupCalc) begin + IBusCachedPlugin_mmuBus_rsp_allowRead = (MmuPlugin_ports_0_cacheLine_allowRead || (MmuPlugin_status_mxr && MmuPlugin_ports_0_cacheLine_allowExecute)); + end else begin + IBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; + end + end + + always @(*) begin + if(MmuPlugin_ports_0_requireMmuLockupCalc) begin + IBusCachedPlugin_mmuBus_rsp_allowWrite = MmuPlugin_ports_0_cacheLine_allowWrite; + end else begin + IBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; + end + end + + always @(*) begin + if(MmuPlugin_ports_0_requireMmuLockupCalc) begin + IBusCachedPlugin_mmuBus_rsp_allowExecute = MmuPlugin_ports_0_cacheLine_allowExecute; + end else begin + IBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; + end + end + + always @(*) begin + if(MmuPlugin_ports_0_requireMmuLockupCalc) begin + IBusCachedPlugin_mmuBus_rsp_exception = (((! MmuPlugin_ports_0_dirty) && MmuPlugin_ports_0_cacheHit) && ((MmuPlugin_ports_0_cacheLine_exception || ((MmuPlugin_ports_0_cacheLine_allowUser && (CsrPlugin_privilege == 2'b01)) && (! MmuPlugin_status_sum))) || ((! MmuPlugin_ports_0_cacheLine_allowUser) && (CsrPlugin_privilege == 2'b00)))); + end else begin + IBusCachedPlugin_mmuBus_rsp_exception = 1'b0; + end + end + + always @(*) begin + if(MmuPlugin_ports_0_requireMmuLockupCalc) begin + IBusCachedPlugin_mmuBus_rsp_refilling = (MmuPlugin_ports_0_dirty || (! MmuPlugin_ports_0_cacheHit)); + end else begin + IBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; + end + end + + always @(*) begin + if(MmuPlugin_ports_0_requireMmuLockupCalc) begin + IBusCachedPlugin_mmuBus_rsp_isPaging = 1'b1; + end else begin + IBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0; + end + end + + assign IBusCachedPlugin_mmuBus_rsp_isIoAccess = (((IBusCachedPlugin_mmuBus_rsp_physicalAddress[31 : 28] == 4'b1011) || (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31 : 28] == 4'b1110)) || (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31 : 28] == 4'b1111)); + assign IBusCachedPlugin_mmuBus_rsp_bypassTranslation = (! MmuPlugin_ports_0_requireMmuLockupCalc); + assign IBusCachedPlugin_mmuBus_rsp_ways_0_sel = MmuPlugin_ports_0_cacheHitsCalc[0]; + assign IBusCachedPlugin_mmuBus_rsp_ways_0_physical = {{MmuPlugin_ports_0_cache_0_physicalAddress_1,(MmuPlugin_ports_0_cache_0_superPage ? IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_0_cache_0_physicalAddress_0)},IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; + assign IBusCachedPlugin_mmuBus_rsp_ways_1_sel = MmuPlugin_ports_0_cacheHitsCalc[1]; + assign IBusCachedPlugin_mmuBus_rsp_ways_1_physical = {{MmuPlugin_ports_0_cache_1_physicalAddress_1,(MmuPlugin_ports_0_cache_1_superPage ? IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_0_cache_1_physicalAddress_0)},IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; + assign IBusCachedPlugin_mmuBus_rsp_ways_2_sel = MmuPlugin_ports_0_cacheHitsCalc[2]; + assign IBusCachedPlugin_mmuBus_rsp_ways_2_physical = {{MmuPlugin_ports_0_cache_2_physicalAddress_1,(MmuPlugin_ports_0_cache_2_superPage ? IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_0_cache_2_physicalAddress_0)},IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; + assign IBusCachedPlugin_mmuBus_rsp_ways_3_sel = MmuPlugin_ports_0_cacheHitsCalc[3]; + assign IBusCachedPlugin_mmuBus_rsp_ways_3_physical = {{MmuPlugin_ports_0_cache_3_physicalAddress_1,(MmuPlugin_ports_0_cache_3_superPage ? IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_0_cache_3_physicalAddress_0)},IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; + assign MmuPlugin_ports_1_dirty = 1'b0; + always @(*) begin + MmuPlugin_ports_1_requireMmuLockupCalc = ((1'b1 && (! DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation)) && MmuPlugin_satp_mode); + if(when_MmuPlugin_l125_1) begin + MmuPlugin_ports_1_requireMmuLockupCalc = 1'b0; + end + if(when_MmuPlugin_l126_1) begin + if(when_MmuPlugin_l128) begin + MmuPlugin_ports_1_requireMmuLockupCalc = 1'b0; + end + end + end + + assign when_MmuPlugin_l125_1 = ((! MmuPlugin_status_mprv) && (CsrPlugin_privilege == 2'b11)); + assign when_MmuPlugin_l126_1 = (CsrPlugin_privilege == 2'b11); + assign when_MmuPlugin_l128 = ((! MmuPlugin_status_mprv) || (CsrPlugin_mstatus_MPP == 2'b11)); + assign MmuPlugin_ports_1_cacheHitsCalc = {((MmuPlugin_ports_1_cache_3_valid && (MmuPlugin_ports_1_cache_3_virtualAddress_1 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22])) && (MmuPlugin_ports_1_cache_3_superPage || (MmuPlugin_ports_1_cache_3_virtualAddress_0 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]))),{((MmuPlugin_ports_1_cache_2_valid && (MmuPlugin_ports_1_cache_2_virtualAddress_1 == _zz_MmuPlugin_ports_1_cacheHitsCalc)) && (MmuPlugin_ports_1_cache_2_superPage || (MmuPlugin_ports_1_cache_2_virtualAddress_0 == _zz_MmuPlugin_ports_1_cacheHitsCalc_1))),{((MmuPlugin_ports_1_cache_1_valid && _zz_MmuPlugin_ports_1_cacheHitsCalc_2) && (MmuPlugin_ports_1_cache_1_superPage || _zz_MmuPlugin_ports_1_cacheHitsCalc_3)),((MmuPlugin_ports_1_cache_0_valid && _zz_MmuPlugin_ports_1_cacheHitsCalc_4) && (MmuPlugin_ports_1_cache_0_superPage || _zz_MmuPlugin_ports_1_cacheHitsCalc_5))}}}; + assign MmuPlugin_ports_1_cacheHit = (MmuPlugin_ports_1_cacheHitsCalc != 4'b0000); + assign _zz_MmuPlugin_ports_1_cacheLine_valid = MmuPlugin_ports_1_cacheHitsCalc[3]; + assign _zz_MmuPlugin_ports_1_cacheLine_valid_1 = (MmuPlugin_ports_1_cacheHitsCalc[1] || _zz_MmuPlugin_ports_1_cacheLine_valid); + assign _zz_MmuPlugin_ports_1_cacheLine_valid_2 = (MmuPlugin_ports_1_cacheHitsCalc[2] || _zz_MmuPlugin_ports_1_cacheLine_valid); + assign _zz_MmuPlugin_ports_1_cacheLine_valid_3 = {_zz_MmuPlugin_ports_1_cacheLine_valid_2,_zz_MmuPlugin_ports_1_cacheLine_valid_1}; + assign MmuPlugin_ports_1_cacheLine_valid = _zz_MmuPlugin_ports_1_cacheLine_valid_4; + assign MmuPlugin_ports_1_cacheLine_exception = _zz_MmuPlugin_ports_1_cacheLine_exception; + assign MmuPlugin_ports_1_cacheLine_superPage = _zz_MmuPlugin_ports_1_cacheLine_superPage; + assign MmuPlugin_ports_1_cacheLine_virtualAddress_0 = _zz_MmuPlugin_ports_1_cacheLine_virtualAddress_0; + assign MmuPlugin_ports_1_cacheLine_virtualAddress_1 = _zz_MmuPlugin_ports_1_cacheLine_virtualAddress_1; + assign MmuPlugin_ports_1_cacheLine_physicalAddress_0 = _zz_MmuPlugin_ports_1_cacheLine_physicalAddress_0; + assign MmuPlugin_ports_1_cacheLine_physicalAddress_1 = _zz_MmuPlugin_ports_1_cacheLine_physicalAddress_1; + assign MmuPlugin_ports_1_cacheLine_allowRead = _zz_MmuPlugin_ports_1_cacheLine_allowRead; + assign MmuPlugin_ports_1_cacheLine_allowWrite = _zz_MmuPlugin_ports_1_cacheLine_allowWrite; + assign MmuPlugin_ports_1_cacheLine_allowExecute = _zz_MmuPlugin_ports_1_cacheLine_allowExecute; + assign MmuPlugin_ports_1_cacheLine_allowUser = _zz_MmuPlugin_ports_1_cacheLine_allowUser; + always @(*) begin + MmuPlugin_ports_1_entryToReplace_willIncrement = 1'b0; + if(when_MmuPlugin_l272) begin + if(when_MmuPlugin_l274_1) begin + MmuPlugin_ports_1_entryToReplace_willIncrement = 1'b1; + end + end + end + + assign MmuPlugin_ports_1_entryToReplace_willClear = 1'b0; + assign MmuPlugin_ports_1_entryToReplace_willOverflowIfInc = (MmuPlugin_ports_1_entryToReplace_value == 2'b11); + assign MmuPlugin_ports_1_entryToReplace_willOverflow = (MmuPlugin_ports_1_entryToReplace_willOverflowIfInc && MmuPlugin_ports_1_entryToReplace_willIncrement); + always @(*) begin + MmuPlugin_ports_1_entryToReplace_valueNext = (MmuPlugin_ports_1_entryToReplace_value + _zz_MmuPlugin_ports_1_entryToReplace_valueNext); + if(MmuPlugin_ports_1_entryToReplace_willClear) begin + MmuPlugin_ports_1_entryToReplace_valueNext = 2'b00; + end + end + + always @(*) begin + if(MmuPlugin_ports_1_requireMmuLockupCalc) begin + DBusCachedPlugin_mmuBus_rsp_physicalAddress = {{MmuPlugin_ports_1_cacheLine_physicalAddress_1,(MmuPlugin_ports_1_cacheLine_superPage ? DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_1_cacheLine_physicalAddress_0)},DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; + end else begin + DBusCachedPlugin_mmuBus_rsp_physicalAddress = DBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + end + end + + always @(*) begin + if(MmuPlugin_ports_1_requireMmuLockupCalc) begin + DBusCachedPlugin_mmuBus_rsp_allowRead = (MmuPlugin_ports_1_cacheLine_allowRead || (MmuPlugin_status_mxr && MmuPlugin_ports_1_cacheLine_allowExecute)); + end else begin + DBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; + end + end + + always @(*) begin + if(MmuPlugin_ports_1_requireMmuLockupCalc) begin + DBusCachedPlugin_mmuBus_rsp_allowWrite = MmuPlugin_ports_1_cacheLine_allowWrite; + end else begin + DBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; + end + end + + always @(*) begin + if(MmuPlugin_ports_1_requireMmuLockupCalc) begin + DBusCachedPlugin_mmuBus_rsp_allowExecute = MmuPlugin_ports_1_cacheLine_allowExecute; + end else begin + DBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; + end + end + + always @(*) begin + if(MmuPlugin_ports_1_requireMmuLockupCalc) begin + DBusCachedPlugin_mmuBus_rsp_exception = (((! MmuPlugin_ports_1_dirty) && MmuPlugin_ports_1_cacheHit) && ((MmuPlugin_ports_1_cacheLine_exception || ((MmuPlugin_ports_1_cacheLine_allowUser && (CsrPlugin_privilege == 2'b01)) && (! MmuPlugin_status_sum))) || ((! MmuPlugin_ports_1_cacheLine_allowUser) && (CsrPlugin_privilege == 2'b00)))); + end else begin + DBusCachedPlugin_mmuBus_rsp_exception = 1'b0; + end + end + + always @(*) begin + if(MmuPlugin_ports_1_requireMmuLockupCalc) begin + DBusCachedPlugin_mmuBus_rsp_refilling = (MmuPlugin_ports_1_dirty || (! MmuPlugin_ports_1_cacheHit)); + end else begin + DBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; + end + end + + always @(*) begin + if(MmuPlugin_ports_1_requireMmuLockupCalc) begin + DBusCachedPlugin_mmuBus_rsp_isPaging = 1'b1; + end else begin + DBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0; + end + end + + assign DBusCachedPlugin_mmuBus_rsp_isIoAccess = (((DBusCachedPlugin_mmuBus_rsp_physicalAddress[31 : 28] == 4'b1011) || (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31 : 28] == 4'b1110)) || (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31 : 28] == 4'b1111)); + assign DBusCachedPlugin_mmuBus_rsp_bypassTranslation = (! MmuPlugin_ports_1_requireMmuLockupCalc); + assign DBusCachedPlugin_mmuBus_rsp_ways_0_sel = MmuPlugin_ports_1_cacheHitsCalc[0]; + assign DBusCachedPlugin_mmuBus_rsp_ways_0_physical = {{MmuPlugin_ports_1_cache_0_physicalAddress_1,(MmuPlugin_ports_1_cache_0_superPage ? DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_1_cache_0_physicalAddress_0)},DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; + assign DBusCachedPlugin_mmuBus_rsp_ways_1_sel = MmuPlugin_ports_1_cacheHitsCalc[1]; + assign DBusCachedPlugin_mmuBus_rsp_ways_1_physical = {{MmuPlugin_ports_1_cache_1_physicalAddress_1,(MmuPlugin_ports_1_cache_1_superPage ? DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_1_cache_1_physicalAddress_0)},DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; + assign DBusCachedPlugin_mmuBus_rsp_ways_2_sel = MmuPlugin_ports_1_cacheHitsCalc[2]; + assign DBusCachedPlugin_mmuBus_rsp_ways_2_physical = {{MmuPlugin_ports_1_cache_2_physicalAddress_1,(MmuPlugin_ports_1_cache_2_superPage ? DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_1_cache_2_physicalAddress_0)},DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; + assign DBusCachedPlugin_mmuBus_rsp_ways_3_sel = MmuPlugin_ports_1_cacheHitsCalc[3]; + assign DBusCachedPlugin_mmuBus_rsp_ways_3_physical = {{MmuPlugin_ports_1_cache_3_physicalAddress_1,(MmuPlugin_ports_1_cache_3_superPage ? DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_1_cache_3_physicalAddress_0)},DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; + assign MmuPlugin_shared_dBusRsp_pte_V = MmuPlugin_shared_dBusRspStaged_payload_data[0]; + assign MmuPlugin_shared_dBusRsp_pte_R = MmuPlugin_shared_dBusRspStaged_payload_data[1]; + assign MmuPlugin_shared_dBusRsp_pte_W = MmuPlugin_shared_dBusRspStaged_payload_data[2]; + assign MmuPlugin_shared_dBusRsp_pte_X = MmuPlugin_shared_dBusRspStaged_payload_data[3]; + assign MmuPlugin_shared_dBusRsp_pte_U = MmuPlugin_shared_dBusRspStaged_payload_data[4]; + assign MmuPlugin_shared_dBusRsp_pte_G = MmuPlugin_shared_dBusRspStaged_payload_data[5]; + assign MmuPlugin_shared_dBusRsp_pte_A = MmuPlugin_shared_dBusRspStaged_payload_data[6]; + assign MmuPlugin_shared_dBusRsp_pte_D = MmuPlugin_shared_dBusRspStaged_payload_data[7]; + assign MmuPlugin_shared_dBusRsp_pte_RSW = MmuPlugin_shared_dBusRspStaged_payload_data[9 : 8]; + assign MmuPlugin_shared_dBusRsp_pte_PPN0 = MmuPlugin_shared_dBusRspStaged_payload_data[19 : 10]; + assign MmuPlugin_shared_dBusRsp_pte_PPN1 = MmuPlugin_shared_dBusRspStaged_payload_data[31 : 20]; + assign MmuPlugin_shared_dBusRsp_exception = (((! MmuPlugin_shared_dBusRsp_pte_V) || ((! MmuPlugin_shared_dBusRsp_pte_R) && MmuPlugin_shared_dBusRsp_pte_W)) || MmuPlugin_shared_dBusRspStaged_payload_error); + assign MmuPlugin_shared_dBusRsp_leaf = (MmuPlugin_shared_dBusRsp_pte_R || MmuPlugin_shared_dBusRsp_pte_X); + assign when_MmuPlugin_l205 = (MmuPlugin_shared_dBusRspStaged_valid && (! MmuPlugin_shared_dBusRspStaged_payload_redo)); + always @(*) begin + MmuPlugin_dBusAccess_cmd_valid = 1'b0; + case(MmuPlugin_shared_state_1) + `MmuPlugin_shared_State_defaultEncoding_IDLE : begin + end + `MmuPlugin_shared_State_defaultEncoding_L1_CMD : begin + MmuPlugin_dBusAccess_cmd_valid = 1'b1; + end + `MmuPlugin_shared_State_defaultEncoding_L1_RSP : begin + end + `MmuPlugin_shared_State_defaultEncoding_L0_CMD : begin + MmuPlugin_dBusAccess_cmd_valid = 1'b1; + end + default : begin + end + endcase + end + + assign MmuPlugin_dBusAccess_cmd_payload_write = 1'b0; + assign MmuPlugin_dBusAccess_cmd_payload_size = 2'b10; + always @(*) begin + MmuPlugin_dBusAccess_cmd_payload_address = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + case(MmuPlugin_shared_state_1) + `MmuPlugin_shared_State_defaultEncoding_IDLE : begin + end + `MmuPlugin_shared_State_defaultEncoding_L1_CMD : begin + MmuPlugin_dBusAccess_cmd_payload_address = {{MmuPlugin_satp_ppn,MmuPlugin_shared_vpn_1},2'b00}; + end + `MmuPlugin_shared_State_defaultEncoding_L1_RSP : begin + end + `MmuPlugin_shared_State_defaultEncoding_L0_CMD : begin + MmuPlugin_dBusAccess_cmd_payload_address = {{{MmuPlugin_shared_pteBuffer_PPN1[9 : 0],MmuPlugin_shared_pteBuffer_PPN0},MmuPlugin_shared_vpn_0},2'b00}; + end + default : begin + end + endcase + end + + assign MmuPlugin_dBusAccess_cmd_payload_data = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + assign MmuPlugin_dBusAccess_cmd_payload_writeMask = 4'bxxxx; + assign _zz_MmuPlugin_shared_refills = {(((DBusCachedPlugin_mmuBus_cmd_0_isValid && MmuPlugin_ports_1_requireMmuLockupCalc) && (! MmuPlugin_ports_1_dirty)) && (! MmuPlugin_ports_1_cacheHit)),(((IBusCachedPlugin_mmuBus_cmd_0_isValid && MmuPlugin_ports_0_requireMmuLockupCalc) && (! MmuPlugin_ports_0_dirty)) && (! MmuPlugin_ports_0_cacheHit))}; + always @(*) begin + _zz_MmuPlugin_shared_refills_1[0] = _zz_MmuPlugin_shared_refills[1]; + _zz_MmuPlugin_shared_refills_1[1] = _zz_MmuPlugin_shared_refills[0]; + end + + assign _zz_MmuPlugin_shared_refills_2 = (_zz_MmuPlugin_shared_refills_1 & (~ _zz__zz_MmuPlugin_shared_refills_2)); + always @(*) begin + _zz_MmuPlugin_shared_refills_3[0] = _zz_MmuPlugin_shared_refills_2[1]; + _zz_MmuPlugin_shared_refills_3[1] = _zz_MmuPlugin_shared_refills_2[0]; + end + + assign MmuPlugin_shared_refills = _zz_MmuPlugin_shared_refills_3; + assign when_MmuPlugin_l217 = (MmuPlugin_shared_refills != 2'b00); + assign _zz_MmuPlugin_shared_vpn_0 = (MmuPlugin_shared_refills[0] ? IBusCachedPlugin_mmuBus_cmd_0_virtualAddress : DBusCachedPlugin_mmuBus_cmd_0_virtualAddress); + assign when_MmuPlugin_l243 = (MmuPlugin_shared_dBusRsp_leaf || MmuPlugin_shared_dBusRsp_exception); + assign IBusCachedPlugin_mmuBus_busy = ((MmuPlugin_shared_state_1 != `MmuPlugin_shared_State_defaultEncoding_IDLE) && MmuPlugin_shared_portSortedOh[0]); + assign DBusCachedPlugin_mmuBus_busy = ((MmuPlugin_shared_state_1 != `MmuPlugin_shared_State_defaultEncoding_IDLE) && MmuPlugin_shared_portSortedOh[1]); + assign when_MmuPlugin_l272 = ((MmuPlugin_shared_dBusRspStaged_valid && (! MmuPlugin_shared_dBusRspStaged_payload_redo)) && (MmuPlugin_shared_dBusRsp_leaf || MmuPlugin_shared_dBusRsp_exception)); + assign when_MmuPlugin_l274 = MmuPlugin_shared_portSortedOh[0]; + assign when_MmuPlugin_l280 = (MmuPlugin_ports_0_entryToReplace_value == 2'b00); + assign when_MmuPlugin_l280_1 = (MmuPlugin_ports_0_entryToReplace_value == 2'b01); + assign when_MmuPlugin_l280_2 = (MmuPlugin_ports_0_entryToReplace_value == 2'b10); + assign when_MmuPlugin_l280_3 = (MmuPlugin_ports_0_entryToReplace_value == 2'b11); + assign when_MmuPlugin_l274_1 = MmuPlugin_shared_portSortedOh[1]; + assign when_MmuPlugin_l280_4 = (MmuPlugin_ports_1_entryToReplace_value == 2'b00); + assign when_MmuPlugin_l280_5 = (MmuPlugin_ports_1_entryToReplace_value == 2'b01); + assign when_MmuPlugin_l280_6 = (MmuPlugin_ports_1_entryToReplace_value == 2'b10); + assign when_MmuPlugin_l280_7 = (MmuPlugin_ports_1_entryToReplace_value == 2'b11); + assign when_MmuPlugin_l304 = ((execute_arbitration_isValid && execute_arbitration_isFiring) && execute_IS_SFENCE_VMA2); + assign when_Pipeline_l124 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_1 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_2 = ((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)); + assign when_Pipeline_l124_3 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_4 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_5 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_6 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_7 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_8 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_9 = (! execute_arbitration_isStuck); + assign _zz_decode_SRC1_CTRL = _zz_decode_SRC1_CTRL_1; + assign when_Pipeline_l124_10 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_11 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_12 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_13 = (! writeBack_arbitration_isStuck); + assign _zz_decode_to_execute_ALU_CTRL_1 = decode_ALU_CTRL; + assign _zz_decode_ALU_CTRL = _zz_decode_ALU_CTRL_1; + assign when_Pipeline_l124_14 = (! execute_arbitration_isStuck); + assign _zz_execute_ALU_CTRL = decode_to_execute_ALU_CTRL; + assign _zz_decode_SRC2_CTRL = _zz_decode_SRC2_CTRL_1; + assign when_Pipeline_l124_15 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_16 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_17 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_18 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_19 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_20 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_21 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_22 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_23 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_24 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_25 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_26 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_27 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_28 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_29 = (! execute_arbitration_isStuck); + assign _zz_decode_to_execute_ALU_BITWISE_CTRL_1 = decode_ALU_BITWISE_CTRL; + assign _zz_decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL_1; + assign when_Pipeline_l124_30 = (! execute_arbitration_isStuck); + assign _zz_execute_ALU_BITWISE_CTRL = decode_to_execute_ALU_BITWISE_CTRL; + assign _zz_decode_to_execute_SHIFT_CTRL_1 = decode_SHIFT_CTRL; + assign _zz_execute_to_memory_SHIFT_CTRL_1 = execute_SHIFT_CTRL; + assign _zz_decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL_1; + assign when_Pipeline_l124_31 = (! execute_arbitration_isStuck); + assign _zz_execute_SHIFT_CTRL = decode_to_execute_SHIFT_CTRL; + assign when_Pipeline_l124_32 = (! memory_arbitration_isStuck); + assign _zz_memory_SHIFT_CTRL = execute_to_memory_SHIFT_CTRL; + assign when_Pipeline_l124_33 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_34 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_35 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_36 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_37 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_38 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_39 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_40 = (! execute_arbitration_isStuck); + assign _zz_decode_to_execute_ENV_CTRL_1 = decode_ENV_CTRL; + assign _zz_execute_to_memory_ENV_CTRL_1 = execute_ENV_CTRL; + assign _zz_memory_to_writeBack_ENV_CTRL_1 = memory_ENV_CTRL; + assign _zz_decode_ENV_CTRL = _zz_decode_ENV_CTRL_1; + assign when_Pipeline_l124_41 = (! execute_arbitration_isStuck); + assign _zz_execute_ENV_CTRL = decode_to_execute_ENV_CTRL; + assign when_Pipeline_l124_42 = (! memory_arbitration_isStuck); + assign _zz_memory_ENV_CTRL = execute_to_memory_ENV_CTRL; + assign when_Pipeline_l124_43 = (! writeBack_arbitration_isStuck); + assign _zz_writeBack_ENV_CTRL = memory_to_writeBack_ENV_CTRL; + assign when_Pipeline_l124_44 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_45 = (! execute_arbitration_isStuck); + assign _zz_decode_to_execute_BRANCH_CTRL_1 = decode_BRANCH_CTRL; + assign _zz_decode_BRANCH_CTRL_1 = _zz_decode_BRANCH_CTRL; + assign when_Pipeline_l124_46 = (! execute_arbitration_isStuck); + assign _zz_execute_BRANCH_CTRL = decode_to_execute_BRANCH_CTRL; + assign when_Pipeline_l124_47 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_48 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_49 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_50 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_51 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_52 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_53 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_54 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_55 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_56 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_57 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_58 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_59 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_60 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_61 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_62 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_63 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_64 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_65 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_66 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_67 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_68 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_69 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_70 = (! writeBack_arbitration_isStuck); + assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != 3'b000) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != 4'b0000)); + assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != 2'b00) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != 3'b000)); + assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != 1'b0) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != 2'b00)); + assign writeBack_arbitration_isFlushed = (1'b0 || (writeBack_arbitration_flushIt != 1'b0)); + assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (((1'b0 || execute_arbitration_isStuck) || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); + assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers); + assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); + assign decode_arbitration_isFiring = ((decode_arbitration_isValid && (! decode_arbitration_isStuck)) && (! decode_arbitration_removeIt)); + assign execute_arbitration_isStuckByOthers = (execute_arbitration_haltByOther || ((1'b0 || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); + assign execute_arbitration_isStuck = (execute_arbitration_haltItself || execute_arbitration_isStuckByOthers); + assign execute_arbitration_isMoving = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); + assign execute_arbitration_isFiring = ((execute_arbitration_isValid && (! execute_arbitration_isStuck)) && (! execute_arbitration_removeIt)); + assign memory_arbitration_isStuckByOthers = (memory_arbitration_haltByOther || (1'b0 || writeBack_arbitration_isStuck)); + assign memory_arbitration_isStuck = (memory_arbitration_haltItself || memory_arbitration_isStuckByOthers); + assign memory_arbitration_isMoving = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)); + assign memory_arbitration_isFiring = ((memory_arbitration_isValid && (! memory_arbitration_isStuck)) && (! memory_arbitration_removeIt)); + assign writeBack_arbitration_isStuckByOthers = (writeBack_arbitration_haltByOther || 1'b0); + assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers); + assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); + assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); + assign when_Pipeline_l151 = ((! execute_arbitration_isStuck) || execute_arbitration_removeIt); + assign when_Pipeline_l154 = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); + assign when_Pipeline_l151_1 = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); + assign when_Pipeline_l154_1 = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); + assign when_Pipeline_l151_2 = ((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt); + assign when_Pipeline_l154_2 = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)); + always @(*) begin + IBusCachedPlugin_injectionPort_ready = 1'b0; + case(switch_Fetcher_l362) + 3'b100 : begin + IBusCachedPlugin_injectionPort_ready = 1'b1; + end + default : begin + end + endcase + end + + assign when_Fetcher_l378 = (! decode_arbitration_isStuck); + assign when_CsrPlugin_l1264 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_1 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_2 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_3 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_4 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_5 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_6 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_7 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_8 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_9 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_10 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_11 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_12 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_13 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_14 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_15 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_16 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_17 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_18 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_19 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_20 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_21 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_22 = (! execute_arbitration_isStuck); + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit = 32'h0; + if(execute_CsrPlugin_csr_3857) begin + _zz_CsrPlugin_csrMapping_readDataInit[0 : 0] = 1'b1; + end + end + + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_1 = 32'h0; + if(execute_CsrPlugin_csr_3858) begin + _zz_CsrPlugin_csrMapping_readDataInit_1[1 : 0] = 2'b10; + end + end + + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_2 = 32'h0; + if(execute_CsrPlugin_csr_3859) begin + _zz_CsrPlugin_csrMapping_readDataInit_2[1 : 0] = 2'b11; + end + end + + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_3 = 32'h0; + if(execute_CsrPlugin_csr_768) begin + _zz_CsrPlugin_csrMapping_readDataInit_3[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_CsrPlugin_csrMapping_readDataInit_3[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_CsrPlugin_csrMapping_readDataInit_3[3 : 3] = CsrPlugin_mstatus_MIE; + _zz_CsrPlugin_csrMapping_readDataInit_3[8 : 8] = CsrPlugin_sstatus_SPP; + _zz_CsrPlugin_csrMapping_readDataInit_3[5 : 5] = CsrPlugin_sstatus_SPIE; + _zz_CsrPlugin_csrMapping_readDataInit_3[1 : 1] = CsrPlugin_sstatus_SIE; + _zz_CsrPlugin_csrMapping_readDataInit_3[19 : 19] = MmuPlugin_status_mxr; + _zz_CsrPlugin_csrMapping_readDataInit_3[18 : 18] = MmuPlugin_status_sum; + _zz_CsrPlugin_csrMapping_readDataInit_3[17 : 17] = MmuPlugin_status_mprv; + end + end + + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_4 = 32'h0; + if(execute_CsrPlugin_csr_836) begin + _zz_CsrPlugin_csrMapping_readDataInit_4[11 : 11] = CsrPlugin_mip_MEIP; + _zz_CsrPlugin_csrMapping_readDataInit_4[7 : 7] = CsrPlugin_mip_MTIP; + _zz_CsrPlugin_csrMapping_readDataInit_4[3 : 3] = CsrPlugin_mip_MSIP; + _zz_CsrPlugin_csrMapping_readDataInit_4[5 : 5] = CsrPlugin_sip_STIP; + _zz_CsrPlugin_csrMapping_readDataInit_4[1 : 1] = CsrPlugin_sip_SSIP; + _zz_CsrPlugin_csrMapping_readDataInit_4[9 : 9] = CsrPlugin_sip_SEIP_OR; + end + end + + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_5 = 32'h0; + if(execute_CsrPlugin_csr_772) begin + _zz_CsrPlugin_csrMapping_readDataInit_5[11 : 11] = CsrPlugin_mie_MEIE; + _zz_CsrPlugin_csrMapping_readDataInit_5[7 : 7] = CsrPlugin_mie_MTIE; + _zz_CsrPlugin_csrMapping_readDataInit_5[3 : 3] = CsrPlugin_mie_MSIE; + _zz_CsrPlugin_csrMapping_readDataInit_5[9 : 9] = CsrPlugin_sie_SEIE; + _zz_CsrPlugin_csrMapping_readDataInit_5[5 : 5] = CsrPlugin_sie_STIE; + _zz_CsrPlugin_csrMapping_readDataInit_5[1 : 1] = CsrPlugin_sie_SSIE; + end + end + + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_6 = 32'h0; + if(execute_CsrPlugin_csr_833) begin + _zz_CsrPlugin_csrMapping_readDataInit_6[31 : 0] = CsrPlugin_mepc; + end + end + + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_7 = 32'h0; + if(execute_CsrPlugin_csr_832) begin + _zz_CsrPlugin_csrMapping_readDataInit_7[31 : 0] = CsrPlugin_mscratch; + end + end + + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_8 = 32'h0; + if(execute_CsrPlugin_csr_834) begin + _zz_CsrPlugin_csrMapping_readDataInit_8[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_CsrPlugin_csrMapping_readDataInit_8[3 : 0] = CsrPlugin_mcause_exceptionCode; + end + end + + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_9 = 32'h0; + if(execute_CsrPlugin_csr_835) begin + _zz_CsrPlugin_csrMapping_readDataInit_9[31 : 0] = CsrPlugin_mtval; + end + end + + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_10 = 32'h0; + if(execute_CsrPlugin_csr_256) begin + _zz_CsrPlugin_csrMapping_readDataInit_10[8 : 8] = CsrPlugin_sstatus_SPP; + _zz_CsrPlugin_csrMapping_readDataInit_10[5 : 5] = CsrPlugin_sstatus_SPIE; + _zz_CsrPlugin_csrMapping_readDataInit_10[1 : 1] = CsrPlugin_sstatus_SIE; + _zz_CsrPlugin_csrMapping_readDataInit_10[19 : 19] = MmuPlugin_status_mxr; + _zz_CsrPlugin_csrMapping_readDataInit_10[18 : 18] = MmuPlugin_status_sum; + _zz_CsrPlugin_csrMapping_readDataInit_10[17 : 17] = MmuPlugin_status_mprv; + end + end + + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_11 = 32'h0; + if(execute_CsrPlugin_csr_324) begin + _zz_CsrPlugin_csrMapping_readDataInit_11[5 : 5] = CsrPlugin_sip_STIP; + _zz_CsrPlugin_csrMapping_readDataInit_11[1 : 1] = CsrPlugin_sip_SSIP; + _zz_CsrPlugin_csrMapping_readDataInit_11[9 : 9] = CsrPlugin_sip_SEIP_OR; + end + end + + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_12 = 32'h0; + if(execute_CsrPlugin_csr_260) begin + _zz_CsrPlugin_csrMapping_readDataInit_12[9 : 9] = CsrPlugin_sie_SEIE; + _zz_CsrPlugin_csrMapping_readDataInit_12[5 : 5] = CsrPlugin_sie_STIE; + _zz_CsrPlugin_csrMapping_readDataInit_12[1 : 1] = CsrPlugin_sie_SSIE; + end + end + + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_13 = 32'h0; + if(execute_CsrPlugin_csr_261) begin + _zz_CsrPlugin_csrMapping_readDataInit_13[31 : 2] = CsrPlugin_stvec_base; + _zz_CsrPlugin_csrMapping_readDataInit_13[1 : 0] = CsrPlugin_stvec_mode; + end + end + + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_14 = 32'h0; + if(execute_CsrPlugin_csr_321) begin + _zz_CsrPlugin_csrMapping_readDataInit_14[31 : 0] = CsrPlugin_sepc; + end + end + + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_15 = 32'h0; + if(execute_CsrPlugin_csr_320) begin + _zz_CsrPlugin_csrMapping_readDataInit_15[31 : 0] = CsrPlugin_sscratch; + end + end + + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_16 = 32'h0; + if(execute_CsrPlugin_csr_322) begin + _zz_CsrPlugin_csrMapping_readDataInit_16[31 : 31] = CsrPlugin_scause_interrupt; + _zz_CsrPlugin_csrMapping_readDataInit_16[3 : 0] = CsrPlugin_scause_exceptionCode; + end + end + + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_17 = 32'h0; + if(execute_CsrPlugin_csr_323) begin + _zz_CsrPlugin_csrMapping_readDataInit_17[31 : 0] = CsrPlugin_stval; + end + end + + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_18 = 32'h0; + if(execute_CsrPlugin_csr_384) begin + _zz_CsrPlugin_csrMapping_readDataInit_18[31 : 31] = MmuPlugin_satp_mode; + _zz_CsrPlugin_csrMapping_readDataInit_18[30 : 22] = MmuPlugin_satp_asid; + _zz_CsrPlugin_csrMapping_readDataInit_18[19 : 0] = MmuPlugin_satp_ppn; + end + end + + assign CsrPlugin_csrMapping_readDataInit = (((((_zz_CsrPlugin_csrMapping_readDataInit | _zz_CsrPlugin_csrMapping_readDataInit_1) | (_zz_CsrPlugin_csrMapping_readDataInit_2 | _zz_CsrPlugin_csrMapping_readDataInit_19)) | ((_zz_CsrPlugin_csrMapping_readDataInit_3 | _zz_CsrPlugin_csrMapping_readDataInit_4) | (_zz_CsrPlugin_csrMapping_readDataInit_5 | _zz_CsrPlugin_csrMapping_readDataInit_6))) | (((_zz_CsrPlugin_csrMapping_readDataInit_7 | _zz_CsrPlugin_csrMapping_readDataInit_8) | (_zz_CsrPlugin_csrMapping_readDataInit_9 | _zz_CsrPlugin_csrMapping_readDataInit_10)) | ((_zz_CsrPlugin_csrMapping_readDataInit_11 | _zz_CsrPlugin_csrMapping_readDataInit_12) | (_zz_CsrPlugin_csrMapping_readDataInit_13 | _zz_CsrPlugin_csrMapping_readDataInit_14)))) | ((_zz_CsrPlugin_csrMapping_readDataInit_15 | _zz_CsrPlugin_csrMapping_readDataInit_16) | (_zz_CsrPlugin_csrMapping_readDataInit_17 | _zz_CsrPlugin_csrMapping_readDataInit_18))); + assign when_CsrPlugin_l1297 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign when_CsrPlugin_l1302 = ((! execute_arbitration_isValid) || (! execute_IS_CSR)); + always @(posedge clk or posedge reset) begin + if(reset) begin + IBusCachedPlugin_fetchPc_pcReg <= 32'h80000000; + IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; + IBusCachedPlugin_fetchPc_booted <= 1'b0; + IBusCachedPlugin_fetchPc_inc <= 1'b0; + _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= 1'b0; + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; + IBusCachedPlugin_rspCounter <= _zz_IBusCachedPlugin_rspCounter; + IBusCachedPlugin_rspCounter <= 32'h0; + dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; + dataCache_1_io_mem_cmd_s2mPipe_rValid_1 <= 1'b0; + dBus_rsp_regNext_valid <= 1'b0; + DBusCachedPlugin_rspCounter <= _zz_DBusCachedPlugin_rspCounter; + DBusCachedPlugin_rspCounter <= 32'h0; + _zz_7 <= 1'b1; + HazardSimplePlugin_writeBackBuffer_valid <= 1'b0; + memory_MulDivIterativePlugin_div_counter_value <= 6'h0; + _zz_CsrPlugin_privilege <= 2'b11; + CsrPlugin_mtvec_mode <= 2'b00; + CsrPlugin_mtvec_base <= 30'h20000008; + CsrPlugin_mstatus_MIE <= 1'b0; + CsrPlugin_mstatus_MPIE <= 1'b0; + CsrPlugin_mstatus_MPP <= 2'b11; + CsrPlugin_mie_MEIE <= 1'b0; + CsrPlugin_mie_MTIE <= 1'b0; + CsrPlugin_mie_MSIE <= 1'b0; + CsrPlugin_medeleg_IAM <= 1'b0; + CsrPlugin_medeleg_IAF <= 1'b0; + CsrPlugin_medeleg_II <= 1'b0; + CsrPlugin_medeleg_LAM <= 1'b0; + CsrPlugin_medeleg_LAF <= 1'b0; + CsrPlugin_medeleg_SAM <= 1'b0; + CsrPlugin_medeleg_SAF <= 1'b0; + CsrPlugin_medeleg_EU <= 1'b0; + CsrPlugin_medeleg_ES <= 1'b0; + CsrPlugin_medeleg_IPF <= 1'b0; + CsrPlugin_medeleg_LPF <= 1'b0; + CsrPlugin_medeleg_SPF <= 1'b0; + CsrPlugin_mideleg_ST <= 1'b0; + CsrPlugin_mideleg_SE <= 1'b0; + CsrPlugin_mideleg_SS <= 1'b0; + CsrPlugin_sstatus_SIE <= 1'b0; + CsrPlugin_sstatus_SPIE <= 1'b0; + CsrPlugin_sstatus_SPP <= 1'b1; + CsrPlugin_sip_SEIP_SOFT <= 1'b0; + CsrPlugin_sip_STIP <= 1'b0; + CsrPlugin_sip_SSIP <= 1'b0; + CsrPlugin_sie_SEIE <= 1'b0; + CsrPlugin_sie_STIE <= 1'b0; + CsrPlugin_sie_SSIE <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; + CsrPlugin_interrupt_valid <= 1'b0; + CsrPlugin_lastStageWasWfi <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; + CsrPlugin_hadException <= 1'b0; + execute_CsrPlugin_wfiWake <= 1'b0; + MmuPlugin_status_sum <= 1'b0; + MmuPlugin_status_mxr <= 1'b0; + MmuPlugin_status_mprv <= 1'b0; + MmuPlugin_satp_mode <= 1'b0; + MmuPlugin_ports_0_cache_0_valid <= 1'b0; + MmuPlugin_ports_0_cache_1_valid <= 1'b0; + MmuPlugin_ports_0_cache_2_valid <= 1'b0; + MmuPlugin_ports_0_cache_3_valid <= 1'b0; + MmuPlugin_ports_0_entryToReplace_value <= 2'b00; + MmuPlugin_ports_1_cache_0_valid <= 1'b0; + MmuPlugin_ports_1_cache_1_valid <= 1'b0; + MmuPlugin_ports_1_cache_2_valid <= 1'b0; + MmuPlugin_ports_1_cache_3_valid <= 1'b0; + MmuPlugin_ports_1_entryToReplace_value <= 2'b00; + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_IDLE; + MmuPlugin_shared_dBusRspStaged_valid <= 1'b0; + execute_arbitration_isValid <= 1'b0; + memory_arbitration_isValid <= 1'b0; + writeBack_arbitration_isValid <= 1'b0; + switch_Fetcher_l362 <= 3'b000; + execute_to_memory_IS_DBUS_SHARING <= 1'b0; + memory_to_writeBack_IS_DBUS_SHARING <= 1'b0; + end else begin + if(IBusCachedPlugin_fetchPc_correction) begin + IBusCachedPlugin_fetchPc_correctionReg <= 1'b1; + end + if(when_Fetcher_l127) begin + IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; + end + IBusCachedPlugin_fetchPc_booted <= 1'b1; + if(when_Fetcher_l131) begin + IBusCachedPlugin_fetchPc_inc <= 1'b0; + end + if(when_Fetcher_l131_1) begin + IBusCachedPlugin_fetchPc_inc <= 1'b1; + end + if(when_Fetcher_l131_2) begin + IBusCachedPlugin_fetchPc_inc <= 1'b0; + end + if(when_Fetcher_l158) begin + IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc; + end + if(IBusCachedPlugin_iBusRsp_flush) begin + _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= 1'b0; + end + if(_zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready) begin + _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); + end + if(IBusCachedPlugin_iBusRsp_flush) begin + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= 1'b0; + end + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready) begin + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); + end + if(IBusCachedPlugin_fetchPc_flushed) begin + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; + end + if(when_Fetcher_l329) begin + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b1; + end + if(IBusCachedPlugin_fetchPc_flushed) begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + end + if(when_Fetcher_l329_1) begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= IBusCachedPlugin_injector_nextPcCalc_valids_0; + end + if(IBusCachedPlugin_fetchPc_flushed) begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + end + if(IBusCachedPlugin_fetchPc_flushed) begin + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; + end + if(when_Fetcher_l329_2) begin + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= IBusCachedPlugin_injector_nextPcCalc_valids_1; + end + if(IBusCachedPlugin_fetchPc_flushed) begin + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; + end + if(IBusCachedPlugin_fetchPc_flushed) begin + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; + end + if(when_Fetcher_l329_3) begin + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= IBusCachedPlugin_injector_nextPcCalc_valids_2; + end + if(IBusCachedPlugin_fetchPc_flushed) begin + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; + end + if(IBusCachedPlugin_fetchPc_flushed) begin + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; + end + if(when_Fetcher_l329_4) begin + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= IBusCachedPlugin_injector_nextPcCalc_valids_3; + end + if(IBusCachedPlugin_fetchPc_flushed) begin + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; + end + if(iBus_rsp_valid) begin + IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + 32'h00000001); + end + if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin + dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; + end + if(when_Stream_l365) begin + dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_valid; + end + if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin + dataCache_1_io_mem_cmd_s2mPipe_rValid_1 <= dataCache_1_io_mem_cmd_s2mPipe_valid; + end + dBus_rsp_regNext_valid <= dBus_rsp_valid; + if(dBus_rsp_valid) begin + DBusCachedPlugin_rspCounter <= (DBusCachedPlugin_rspCounter + 32'h00000001); + end + _zz_7 <= 1'b0; + HazardSimplePlugin_writeBackBuffer_valid <= HazardSimplePlugin_writeBackWrites_valid; + memory_MulDivIterativePlugin_div_counter_value <= memory_MulDivIterativePlugin_div_counter_valueNext; + if(when_CsrPlugin_l909) begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= CsrPlugin_exceptionPortCtrl_exceptionValids_decode; + end + if(when_CsrPlugin_l909_1) begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= (CsrPlugin_exceptionPortCtrl_exceptionValids_decode && (! decode_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= CsrPlugin_exceptionPortCtrl_exceptionValids_execute; + end + if(when_CsrPlugin_l909_2) begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && (! execute_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= CsrPlugin_exceptionPortCtrl_exceptionValids_memory; + end + if(when_CsrPlugin_l909_3) begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= (CsrPlugin_exceptionPortCtrl_exceptionValids_memory && (! memory_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; + end + CsrPlugin_interrupt_valid <= 1'b0; + if(when_CsrPlugin_l946) begin + if(when_CsrPlugin_l952) begin + CsrPlugin_interrupt_valid <= 1'b1; + end + if(when_CsrPlugin_l952_1) begin + CsrPlugin_interrupt_valid <= 1'b1; + end + if(when_CsrPlugin_l952_2) begin + CsrPlugin_interrupt_valid <= 1'b1; + end + end + if(when_CsrPlugin_l946_1) begin + if(when_CsrPlugin_l952_3) begin + CsrPlugin_interrupt_valid <= 1'b1; + end + if(when_CsrPlugin_l952_4) begin + CsrPlugin_interrupt_valid <= 1'b1; + end + if(when_CsrPlugin_l952_5) begin + CsrPlugin_interrupt_valid <= 1'b1; + end + if(when_CsrPlugin_l952_6) begin + CsrPlugin_interrupt_valid <= 1'b1; + end + if(when_CsrPlugin_l952_7) begin + CsrPlugin_interrupt_valid <= 1'b1; + end + if(when_CsrPlugin_l952_8) begin + CsrPlugin_interrupt_valid <= 1'b1; + end + end + CsrPlugin_lastStageWasWfi <= (writeBack_arbitration_isFiring && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); + if(CsrPlugin_pipelineLiberator_active) begin + if(when_CsrPlugin_l980) begin + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b1; + end + if(when_CsrPlugin_l980_1) begin + CsrPlugin_pipelineLiberator_pcValids_1 <= CsrPlugin_pipelineLiberator_pcValids_0; + end + if(when_CsrPlugin_l980_2) begin + CsrPlugin_pipelineLiberator_pcValids_2 <= CsrPlugin_pipelineLiberator_pcValids_1; + end + end + if(when_CsrPlugin_l985) begin + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; + end + if(CsrPlugin_interruptJump) begin + CsrPlugin_interrupt_valid <= 1'b0; + end + CsrPlugin_hadException <= CsrPlugin_exception; + if(when_CsrPlugin_l1019) begin + _zz_CsrPlugin_privilege <= CsrPlugin_targetPrivilege; + case(CsrPlugin_targetPrivilege) + 2'b01 : begin + CsrPlugin_sstatus_SIE <= 1'b0; + CsrPlugin_sstatus_SPIE <= CsrPlugin_sstatus_SIE; + CsrPlugin_sstatus_SPP <= CsrPlugin_privilege[0 : 0]; + end + 2'b11 : begin + CsrPlugin_mstatus_MIE <= 1'b0; + CsrPlugin_mstatus_MPIE <= CsrPlugin_mstatus_MIE; + CsrPlugin_mstatus_MPP <= CsrPlugin_privilege; + end + default : begin + end + endcase + end + if(when_CsrPlugin_l1064) begin + case(switch_CsrPlugin_l1068) + 2'b11 : begin + CsrPlugin_mstatus_MPP <= 2'b00; + CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; + CsrPlugin_mstatus_MPIE <= 1'b1; + _zz_CsrPlugin_privilege <= CsrPlugin_mstatus_MPP; + end + 2'b01 : begin + CsrPlugin_sstatus_SPP <= 1'b0; + CsrPlugin_sstatus_SIE <= CsrPlugin_sstatus_SPIE; + CsrPlugin_sstatus_SPIE <= 1'b1; + _zz_CsrPlugin_privilege <= {1'b0,CsrPlugin_sstatus_SPP}; + end + default : begin + end + endcase + end + execute_CsrPlugin_wfiWake <= (({_zz_when_CsrPlugin_l952_5,{_zz_when_CsrPlugin_l952_4,{_zz_when_CsrPlugin_l952_3,{_zz_when_CsrPlugin_l952_2,{_zz_when_CsrPlugin_l952_1,_zz_when_CsrPlugin_l952}}}}} != 6'h0) || CsrPlugin_thirdPartyWake); + MmuPlugin_ports_0_entryToReplace_value <= MmuPlugin_ports_0_entryToReplace_valueNext; + if(contextSwitching) begin + if(MmuPlugin_ports_0_cache_0_exception) begin + MmuPlugin_ports_0_cache_0_valid <= 1'b0; + end + if(MmuPlugin_ports_0_cache_1_exception) begin + MmuPlugin_ports_0_cache_1_valid <= 1'b0; + end + if(MmuPlugin_ports_0_cache_2_exception) begin + MmuPlugin_ports_0_cache_2_valid <= 1'b0; + end + if(MmuPlugin_ports_0_cache_3_exception) begin + MmuPlugin_ports_0_cache_3_valid <= 1'b0; + end + end + MmuPlugin_ports_1_entryToReplace_value <= MmuPlugin_ports_1_entryToReplace_valueNext; + if(contextSwitching) begin + if(MmuPlugin_ports_1_cache_0_exception) begin + MmuPlugin_ports_1_cache_0_valid <= 1'b0; + end + if(MmuPlugin_ports_1_cache_1_exception) begin + MmuPlugin_ports_1_cache_1_valid <= 1'b0; + end + if(MmuPlugin_ports_1_cache_2_exception) begin + MmuPlugin_ports_1_cache_2_valid <= 1'b0; + end + if(MmuPlugin_ports_1_cache_3_exception) begin + MmuPlugin_ports_1_cache_3_valid <= 1'b0; + end + end + MmuPlugin_shared_dBusRspStaged_valid <= MmuPlugin_dBusAccess_rsp_valid; + case(MmuPlugin_shared_state_1) + `MmuPlugin_shared_State_defaultEncoding_IDLE : begin + if(when_MmuPlugin_l217) begin + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_L1_CMD; + end + end + `MmuPlugin_shared_State_defaultEncoding_L1_CMD : begin + if(MmuPlugin_dBusAccess_cmd_ready) begin + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_L1_RSP; + end + end + `MmuPlugin_shared_State_defaultEncoding_L1_RSP : begin + if(MmuPlugin_shared_dBusRspStaged_valid) begin + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_L0_CMD; + if(when_MmuPlugin_l243) begin + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_IDLE; + end + if(MmuPlugin_shared_dBusRspStaged_payload_redo) begin + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_L1_CMD; + end + end + end + `MmuPlugin_shared_State_defaultEncoding_L0_CMD : begin + if(MmuPlugin_dBusAccess_cmd_ready) begin + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_L0_RSP; + end + end + default : begin + if(MmuPlugin_shared_dBusRspStaged_valid) begin + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_IDLE; + if(MmuPlugin_shared_dBusRspStaged_payload_redo) begin + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_L0_CMD; + end + end + end + endcase + if(when_MmuPlugin_l272) begin + if(when_MmuPlugin_l274) begin + if(when_MmuPlugin_l280) begin + MmuPlugin_ports_0_cache_0_valid <= 1'b1; + end + if(when_MmuPlugin_l280_1) begin + MmuPlugin_ports_0_cache_1_valid <= 1'b1; + end + if(when_MmuPlugin_l280_2) begin + MmuPlugin_ports_0_cache_2_valid <= 1'b1; + end + if(when_MmuPlugin_l280_3) begin + MmuPlugin_ports_0_cache_3_valid <= 1'b1; + end + end + if(when_MmuPlugin_l274_1) begin + if(when_MmuPlugin_l280_4) begin + MmuPlugin_ports_1_cache_0_valid <= 1'b1; + end + if(when_MmuPlugin_l280_5) begin + MmuPlugin_ports_1_cache_1_valid <= 1'b1; + end + if(when_MmuPlugin_l280_6) begin + MmuPlugin_ports_1_cache_2_valid <= 1'b1; + end + if(when_MmuPlugin_l280_7) begin + MmuPlugin_ports_1_cache_3_valid <= 1'b1; + end + end + end + if(when_MmuPlugin_l304) begin + MmuPlugin_ports_0_cache_0_valid <= 1'b0; + MmuPlugin_ports_0_cache_1_valid <= 1'b0; + MmuPlugin_ports_0_cache_2_valid <= 1'b0; + MmuPlugin_ports_0_cache_3_valid <= 1'b0; + MmuPlugin_ports_1_cache_0_valid <= 1'b0; + MmuPlugin_ports_1_cache_1_valid <= 1'b0; + MmuPlugin_ports_1_cache_2_valid <= 1'b0; + MmuPlugin_ports_1_cache_3_valid <= 1'b0; + end + if(when_Pipeline_l124_58) begin + execute_to_memory_IS_DBUS_SHARING <= execute_IS_DBUS_SHARING; + end + if(when_Pipeline_l124_59) begin + memory_to_writeBack_IS_DBUS_SHARING <= memory_IS_DBUS_SHARING; + end + if(when_Pipeline_l151) begin + execute_arbitration_isValid <= 1'b0; + end + if(when_Pipeline_l154) begin + execute_arbitration_isValid <= decode_arbitration_isValid; + end + if(when_Pipeline_l151_1) begin + memory_arbitration_isValid <= 1'b0; + end + if(when_Pipeline_l154_1) begin + memory_arbitration_isValid <= execute_arbitration_isValid; + end + if(when_Pipeline_l151_2) begin + writeBack_arbitration_isValid <= 1'b0; + end + if(when_Pipeline_l154_2) begin + writeBack_arbitration_isValid <= memory_arbitration_isValid; + end + case(switch_Fetcher_l362) + 3'b000 : begin + if(IBusCachedPlugin_injectionPort_valid) begin + switch_Fetcher_l362 <= 3'b001; + end + end + 3'b001 : begin + switch_Fetcher_l362 <= 3'b010; + end + 3'b010 : begin + switch_Fetcher_l362 <= 3'b011; + end + 3'b011 : begin + if(when_Fetcher_l378) begin + switch_Fetcher_l362 <= 3'b100; + end + end + 3'b100 : begin + switch_Fetcher_l362 <= 3'b000; + end + default : begin + end + endcase + if(MmuPlugin_dBusAccess_rsp_valid) begin + memory_to_writeBack_IS_DBUS_SHARING <= 1'b0; + end + if(MmuPlugin_dBusAccess_rsp_valid) begin + memory_to_writeBack_IS_DBUS_SHARING <= 1'b0; + end + if(execute_CsrPlugin_csr_768) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mstatus_MPP <= CsrPlugin_csrMapping_writeDataSignal[12 : 11]; + CsrPlugin_mstatus_MPIE <= CsrPlugin_csrMapping_writeDataSignal[7]; + CsrPlugin_mstatus_MIE <= CsrPlugin_csrMapping_writeDataSignal[3]; + CsrPlugin_sstatus_SPP <= CsrPlugin_csrMapping_writeDataSignal[8 : 8]; + CsrPlugin_sstatus_SPIE <= CsrPlugin_csrMapping_writeDataSignal[5]; + CsrPlugin_sstatus_SIE <= CsrPlugin_csrMapping_writeDataSignal[1]; + MmuPlugin_status_mxr <= CsrPlugin_csrMapping_writeDataSignal[19]; + MmuPlugin_status_sum <= CsrPlugin_csrMapping_writeDataSignal[18]; + MmuPlugin_status_mprv <= CsrPlugin_csrMapping_writeDataSignal[17]; + end + end + if(execute_CsrPlugin_csr_836) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_sip_STIP <= CsrPlugin_csrMapping_writeDataSignal[5]; + CsrPlugin_sip_SSIP <= CsrPlugin_csrMapping_writeDataSignal[1]; + CsrPlugin_sip_SEIP_SOFT <= CsrPlugin_csrMapping_writeDataSignal[9]; + end + end + if(execute_CsrPlugin_csr_772) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mie_MEIE <= CsrPlugin_csrMapping_writeDataSignal[11]; + CsrPlugin_mie_MTIE <= CsrPlugin_csrMapping_writeDataSignal[7]; + CsrPlugin_mie_MSIE <= CsrPlugin_csrMapping_writeDataSignal[3]; + CsrPlugin_sie_SEIE <= CsrPlugin_csrMapping_writeDataSignal[9]; + CsrPlugin_sie_STIE <= CsrPlugin_csrMapping_writeDataSignal[5]; + CsrPlugin_sie_SSIE <= CsrPlugin_csrMapping_writeDataSignal[1]; + end + end + if(execute_CsrPlugin_csr_773) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mtvec_base <= CsrPlugin_csrMapping_writeDataSignal[31 : 2]; + CsrPlugin_mtvec_mode <= CsrPlugin_csrMapping_writeDataSignal[1 : 0]; + end + end + if(execute_CsrPlugin_csr_770) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_medeleg_IAM <= CsrPlugin_csrMapping_writeDataSignal[0]; + CsrPlugin_medeleg_IAF <= CsrPlugin_csrMapping_writeDataSignal[1]; + CsrPlugin_medeleg_II <= CsrPlugin_csrMapping_writeDataSignal[2]; + CsrPlugin_medeleg_LAM <= CsrPlugin_csrMapping_writeDataSignal[4]; + CsrPlugin_medeleg_LAF <= CsrPlugin_csrMapping_writeDataSignal[5]; + CsrPlugin_medeleg_SAM <= CsrPlugin_csrMapping_writeDataSignal[6]; + CsrPlugin_medeleg_SAF <= CsrPlugin_csrMapping_writeDataSignal[7]; + CsrPlugin_medeleg_EU <= CsrPlugin_csrMapping_writeDataSignal[8]; + CsrPlugin_medeleg_ES <= CsrPlugin_csrMapping_writeDataSignal[9]; + CsrPlugin_medeleg_IPF <= CsrPlugin_csrMapping_writeDataSignal[12]; + CsrPlugin_medeleg_LPF <= CsrPlugin_csrMapping_writeDataSignal[13]; + CsrPlugin_medeleg_SPF <= CsrPlugin_csrMapping_writeDataSignal[15]; + end + end + if(execute_CsrPlugin_csr_771) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mideleg_SE <= CsrPlugin_csrMapping_writeDataSignal[9]; + CsrPlugin_mideleg_ST <= CsrPlugin_csrMapping_writeDataSignal[5]; + CsrPlugin_mideleg_SS <= CsrPlugin_csrMapping_writeDataSignal[1]; + end + end + if(execute_CsrPlugin_csr_256) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_sstatus_SPP <= CsrPlugin_csrMapping_writeDataSignal[8 : 8]; + CsrPlugin_sstatus_SPIE <= CsrPlugin_csrMapping_writeDataSignal[5]; + CsrPlugin_sstatus_SIE <= CsrPlugin_csrMapping_writeDataSignal[1]; + MmuPlugin_status_mxr <= CsrPlugin_csrMapping_writeDataSignal[19]; + MmuPlugin_status_sum <= CsrPlugin_csrMapping_writeDataSignal[18]; + MmuPlugin_status_mprv <= CsrPlugin_csrMapping_writeDataSignal[17]; + end + end + if(execute_CsrPlugin_csr_324) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_sip_STIP <= CsrPlugin_csrMapping_writeDataSignal[5]; + CsrPlugin_sip_SSIP <= CsrPlugin_csrMapping_writeDataSignal[1]; + CsrPlugin_sip_SEIP_SOFT <= CsrPlugin_csrMapping_writeDataSignal[9]; + end + end + if(execute_CsrPlugin_csr_260) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_sie_SEIE <= CsrPlugin_csrMapping_writeDataSignal[9]; + CsrPlugin_sie_STIE <= CsrPlugin_csrMapping_writeDataSignal[5]; + CsrPlugin_sie_SSIE <= CsrPlugin_csrMapping_writeDataSignal[1]; + end + end + if(execute_CsrPlugin_csr_384) begin + if(execute_CsrPlugin_writeEnable) begin + MmuPlugin_satp_mode <= CsrPlugin_csrMapping_writeDataSignal[31]; + MmuPlugin_ports_0_cache_0_valid <= 1'b0; + MmuPlugin_ports_0_cache_1_valid <= 1'b0; + MmuPlugin_ports_0_cache_2_valid <= 1'b0; + MmuPlugin_ports_0_cache_3_valid <= 1'b0; + MmuPlugin_ports_1_cache_0_valid <= 1'b0; + MmuPlugin_ports_1_cache_1_valid <= 1'b0; + MmuPlugin_ports_1_cache_2_valid <= 1'b0; + MmuPlugin_ports_1_cache_3_valid <= 1'b0; + end + end + end + end + + always @(posedge clk) begin + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready) begin + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; + end + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready) begin + IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit; + end + if(IBusCachedPlugin_iBusRsp_stages_2_input_ready) begin + IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; + end + if(when_Stream_l365) begin + dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_payload_wr; + dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached; + dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_payload_address; + dataCache_1_io_mem_cmd_s2mPipe_rData_data <= dataCache_1_io_mem_cmd_payload_data; + dataCache_1_io_mem_cmd_s2mPipe_rData_mask <= dataCache_1_io_mem_cmd_payload_mask; + dataCache_1_io_mem_cmd_s2mPipe_rData_size <= dataCache_1_io_mem_cmd_payload_size; + dataCache_1_io_mem_cmd_s2mPipe_rData_last <= dataCache_1_io_mem_cmd_payload_last; + end + if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin + dataCache_1_io_mem_cmd_s2mPipe_rData_wr_1 <= dataCache_1_io_mem_cmd_s2mPipe_payload_wr; + dataCache_1_io_mem_cmd_s2mPipe_rData_uncached_1 <= dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; + dataCache_1_io_mem_cmd_s2mPipe_rData_address_1 <= dataCache_1_io_mem_cmd_s2mPipe_payload_address; + dataCache_1_io_mem_cmd_s2mPipe_rData_data_1 <= dataCache_1_io_mem_cmd_s2mPipe_payload_data; + dataCache_1_io_mem_cmd_s2mPipe_rData_mask_1 <= dataCache_1_io_mem_cmd_s2mPipe_payload_mask; + dataCache_1_io_mem_cmd_s2mPipe_rData_size_1 <= dataCache_1_io_mem_cmd_s2mPipe_payload_size; + dataCache_1_io_mem_cmd_s2mPipe_rData_last_1 <= dataCache_1_io_mem_cmd_s2mPipe_payload_last; + end + dBus_rsp_regNext_payload_last <= dBus_rsp_payload_last; + dBus_rsp_regNext_payload_data <= dBus_rsp_payload_data; + dBus_rsp_regNext_payload_error <= dBus_rsp_payload_error; + HazardSimplePlugin_writeBackBuffer_payload_address <= HazardSimplePlugin_writeBackWrites_payload_address; + HazardSimplePlugin_writeBackBuffer_payload_data <= HazardSimplePlugin_writeBackWrites_payload_data; + if(when_MulDivIterativePlugin_l126) begin + memory_MulDivIterativePlugin_div_done <= 1'b1; + end + if(when_MulDivIterativePlugin_l126_1) begin + memory_MulDivIterativePlugin_div_done <= 1'b0; + end + if(when_MulDivIterativePlugin_l128) begin + if(when_MulDivIterativePlugin_l132) begin + memory_MulDivIterativePlugin_rs1[31 : 0] <= memory_MulDivIterativePlugin_div_stage_0_outNumerator; + memory_MulDivIterativePlugin_accumulator[31 : 0] <= memory_MulDivIterativePlugin_div_stage_0_outRemainder; + if(when_MulDivIterativePlugin_l151) begin + memory_MulDivIterativePlugin_div_result <= _zz_memory_MulDivIterativePlugin_div_result_1[31:0]; + end + end + end + if(when_MulDivIterativePlugin_l162) begin + memory_MulDivIterativePlugin_accumulator <= 65'h0; + memory_MulDivIterativePlugin_rs1 <= ((_zz_memory_MulDivIterativePlugin_rs1 ? (~ _zz_memory_MulDivIterativePlugin_rs1_1) : _zz_memory_MulDivIterativePlugin_rs1_1) + _zz_memory_MulDivIterativePlugin_rs1_2); + memory_MulDivIterativePlugin_rs2 <= ((_zz_memory_MulDivIterativePlugin_rs2 ? (~ execute_RS2) : execute_RS2) + _zz_memory_MulDivIterativePlugin_rs2_1); + memory_MulDivIterativePlugin_div_needRevert <= ((_zz_memory_MulDivIterativePlugin_rs1 ^ (_zz_memory_MulDivIterativePlugin_rs2 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + end + CsrPlugin_mip_MEIP <= externalInterrupt; + CsrPlugin_mip_MTIP <= timerInterrupt; + CsrPlugin_mip_MSIP <= softwareInterrupt; + CsrPlugin_sip_SEIP_INPUT <= externalInterruptS; + CsrPlugin_mcycle <= (CsrPlugin_mcycle + 64'h0000000000000001); + if(writeBack_arbitration_isFiring) begin + CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); + end + if(_zz_when) begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); + end + if(CsrPlugin_selfException_valid) begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CsrPlugin_selfException_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CsrPlugin_selfException_payload_badAddr; + end + if(BranchPlugin_branchExceptionPort_valid) begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= BranchPlugin_branchExceptionPort_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= BranchPlugin_branchExceptionPort_payload_badAddr; + end + if(DBusCachedPlugin_exceptionBus_valid) begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr; + end + if(when_CsrPlugin_l946) begin + if(when_CsrPlugin_l952) begin + CsrPlugin_interrupt_code <= 4'b0101; + CsrPlugin_interrupt_targetPrivilege <= 2'b01; + end + if(when_CsrPlugin_l952_1) begin + CsrPlugin_interrupt_code <= 4'b0001; + CsrPlugin_interrupt_targetPrivilege <= 2'b01; + end + if(when_CsrPlugin_l952_2) begin + CsrPlugin_interrupt_code <= 4'b1001; + CsrPlugin_interrupt_targetPrivilege <= 2'b01; + end + end + if(when_CsrPlugin_l946_1) begin + if(when_CsrPlugin_l952_3) begin + CsrPlugin_interrupt_code <= 4'b0101; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + if(when_CsrPlugin_l952_4) begin + CsrPlugin_interrupt_code <= 4'b0001; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + if(when_CsrPlugin_l952_5) begin + CsrPlugin_interrupt_code <= 4'b1001; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + if(when_CsrPlugin_l952_6) begin + CsrPlugin_interrupt_code <= 4'b0111; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + if(when_CsrPlugin_l952_7) begin + CsrPlugin_interrupt_code <= 4'b0011; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + if(when_CsrPlugin_l952_8) begin + CsrPlugin_interrupt_code <= 4'b1011; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + end + if(when_CsrPlugin_l1019) begin + case(CsrPlugin_targetPrivilege) + 2'b01 : begin + CsrPlugin_scause_interrupt <= (! CsrPlugin_hadException); + CsrPlugin_scause_exceptionCode <= CsrPlugin_trapCause; + CsrPlugin_sepc <= writeBack_PC; + if(CsrPlugin_hadException) begin + CsrPlugin_stval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + end + end + 2'b11 : begin + CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); + CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause; + CsrPlugin_mepc <= writeBack_PC; + if(CsrPlugin_hadException) begin + CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + end + end + default : begin + end + endcase + end + MmuPlugin_shared_dBusRspStaged_payload_data <= MmuPlugin_dBusAccess_rsp_payload_data; + MmuPlugin_shared_dBusRspStaged_payload_error <= MmuPlugin_dBusAccess_rsp_payload_error; + MmuPlugin_shared_dBusRspStaged_payload_redo <= MmuPlugin_dBusAccess_rsp_payload_redo; + if(when_MmuPlugin_l205) begin + MmuPlugin_shared_pteBuffer_V <= MmuPlugin_shared_dBusRsp_pte_V; + MmuPlugin_shared_pteBuffer_R <= MmuPlugin_shared_dBusRsp_pte_R; + MmuPlugin_shared_pteBuffer_W <= MmuPlugin_shared_dBusRsp_pte_W; + MmuPlugin_shared_pteBuffer_X <= MmuPlugin_shared_dBusRsp_pte_X; + MmuPlugin_shared_pteBuffer_U <= MmuPlugin_shared_dBusRsp_pte_U; + MmuPlugin_shared_pteBuffer_G <= MmuPlugin_shared_dBusRsp_pte_G; + MmuPlugin_shared_pteBuffer_A <= MmuPlugin_shared_dBusRsp_pte_A; + MmuPlugin_shared_pteBuffer_D <= MmuPlugin_shared_dBusRsp_pte_D; + MmuPlugin_shared_pteBuffer_RSW <= MmuPlugin_shared_dBusRsp_pte_RSW; + MmuPlugin_shared_pteBuffer_PPN0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; + MmuPlugin_shared_pteBuffer_PPN1 <= MmuPlugin_shared_dBusRsp_pte_PPN1; + end + case(MmuPlugin_shared_state_1) + `MmuPlugin_shared_State_defaultEncoding_IDLE : begin + if(when_MmuPlugin_l217) begin + MmuPlugin_shared_portSortedOh <= MmuPlugin_shared_refills; + MmuPlugin_shared_vpn_1 <= _zz_MmuPlugin_shared_vpn_0[31 : 22]; + MmuPlugin_shared_vpn_0 <= _zz_MmuPlugin_shared_vpn_0[21 : 12]; + end + end + `MmuPlugin_shared_State_defaultEncoding_L1_CMD : begin + end + `MmuPlugin_shared_State_defaultEncoding_L1_RSP : begin + end + `MmuPlugin_shared_State_defaultEncoding_L0_CMD : begin + end + default : begin + end + endcase + if(when_MmuPlugin_l272) begin + if(when_MmuPlugin_l274) begin + if(when_MmuPlugin_l280) begin + MmuPlugin_ports_0_cache_0_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); + MmuPlugin_ports_0_cache_0_virtualAddress_0 <= MmuPlugin_shared_vpn_0; + MmuPlugin_ports_0_cache_0_virtualAddress_1 <= MmuPlugin_shared_vpn_1; + MmuPlugin_ports_0_cache_0_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; + MmuPlugin_ports_0_cache_0_physicalAddress_1 <= MmuPlugin_shared_dBusRsp_pte_PPN1[9 : 0]; + MmuPlugin_ports_0_cache_0_allowRead <= MmuPlugin_shared_dBusRsp_pte_R; + MmuPlugin_ports_0_cache_0_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; + MmuPlugin_ports_0_cache_0_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; + MmuPlugin_ports_0_cache_0_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; + MmuPlugin_ports_0_cache_0_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); + end + if(when_MmuPlugin_l280_1) begin + MmuPlugin_ports_0_cache_1_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); + MmuPlugin_ports_0_cache_1_virtualAddress_0 <= MmuPlugin_shared_vpn_0; + MmuPlugin_ports_0_cache_1_virtualAddress_1 <= MmuPlugin_shared_vpn_1; + MmuPlugin_ports_0_cache_1_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; + MmuPlugin_ports_0_cache_1_physicalAddress_1 <= MmuPlugin_shared_dBusRsp_pte_PPN1[9 : 0]; + MmuPlugin_ports_0_cache_1_allowRead <= MmuPlugin_shared_dBusRsp_pte_R; + MmuPlugin_ports_0_cache_1_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; + MmuPlugin_ports_0_cache_1_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; + MmuPlugin_ports_0_cache_1_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; + MmuPlugin_ports_0_cache_1_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); + end + if(when_MmuPlugin_l280_2) begin + MmuPlugin_ports_0_cache_2_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); + MmuPlugin_ports_0_cache_2_virtualAddress_0 <= MmuPlugin_shared_vpn_0; + MmuPlugin_ports_0_cache_2_virtualAddress_1 <= MmuPlugin_shared_vpn_1; + MmuPlugin_ports_0_cache_2_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; + MmuPlugin_ports_0_cache_2_physicalAddress_1 <= MmuPlugin_shared_dBusRsp_pte_PPN1[9 : 0]; + MmuPlugin_ports_0_cache_2_allowRead <= MmuPlugin_shared_dBusRsp_pte_R; + MmuPlugin_ports_0_cache_2_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; + MmuPlugin_ports_0_cache_2_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; + MmuPlugin_ports_0_cache_2_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; + MmuPlugin_ports_0_cache_2_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); + end + if(when_MmuPlugin_l280_3) begin + MmuPlugin_ports_0_cache_3_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); + MmuPlugin_ports_0_cache_3_virtualAddress_0 <= MmuPlugin_shared_vpn_0; + MmuPlugin_ports_0_cache_3_virtualAddress_1 <= MmuPlugin_shared_vpn_1; + MmuPlugin_ports_0_cache_3_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; + MmuPlugin_ports_0_cache_3_physicalAddress_1 <= MmuPlugin_shared_dBusRsp_pte_PPN1[9 : 0]; + MmuPlugin_ports_0_cache_3_allowRead <= MmuPlugin_shared_dBusRsp_pte_R; + MmuPlugin_ports_0_cache_3_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; + MmuPlugin_ports_0_cache_3_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; + MmuPlugin_ports_0_cache_3_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; + MmuPlugin_ports_0_cache_3_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); + end + end + if(when_MmuPlugin_l274_1) begin + if(when_MmuPlugin_l280_4) begin + MmuPlugin_ports_1_cache_0_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); + MmuPlugin_ports_1_cache_0_virtualAddress_0 <= MmuPlugin_shared_vpn_0; + MmuPlugin_ports_1_cache_0_virtualAddress_1 <= MmuPlugin_shared_vpn_1; + MmuPlugin_ports_1_cache_0_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; + MmuPlugin_ports_1_cache_0_physicalAddress_1 <= MmuPlugin_shared_dBusRsp_pte_PPN1[9 : 0]; + MmuPlugin_ports_1_cache_0_allowRead <= MmuPlugin_shared_dBusRsp_pte_R; + MmuPlugin_ports_1_cache_0_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; + MmuPlugin_ports_1_cache_0_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; + MmuPlugin_ports_1_cache_0_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; + MmuPlugin_ports_1_cache_0_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); + end + if(when_MmuPlugin_l280_5) begin + MmuPlugin_ports_1_cache_1_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); + MmuPlugin_ports_1_cache_1_virtualAddress_0 <= MmuPlugin_shared_vpn_0; + MmuPlugin_ports_1_cache_1_virtualAddress_1 <= MmuPlugin_shared_vpn_1; + MmuPlugin_ports_1_cache_1_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; + MmuPlugin_ports_1_cache_1_physicalAddress_1 <= MmuPlugin_shared_dBusRsp_pte_PPN1[9 : 0]; + MmuPlugin_ports_1_cache_1_allowRead <= MmuPlugin_shared_dBusRsp_pte_R; + MmuPlugin_ports_1_cache_1_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; + MmuPlugin_ports_1_cache_1_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; + MmuPlugin_ports_1_cache_1_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; + MmuPlugin_ports_1_cache_1_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); + end + if(when_MmuPlugin_l280_6) begin + MmuPlugin_ports_1_cache_2_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); + MmuPlugin_ports_1_cache_2_virtualAddress_0 <= MmuPlugin_shared_vpn_0; + MmuPlugin_ports_1_cache_2_virtualAddress_1 <= MmuPlugin_shared_vpn_1; + MmuPlugin_ports_1_cache_2_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; + MmuPlugin_ports_1_cache_2_physicalAddress_1 <= MmuPlugin_shared_dBusRsp_pte_PPN1[9 : 0]; + MmuPlugin_ports_1_cache_2_allowRead <= MmuPlugin_shared_dBusRsp_pte_R; + MmuPlugin_ports_1_cache_2_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; + MmuPlugin_ports_1_cache_2_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; + MmuPlugin_ports_1_cache_2_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; + MmuPlugin_ports_1_cache_2_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); + end + if(when_MmuPlugin_l280_7) begin + MmuPlugin_ports_1_cache_3_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); + MmuPlugin_ports_1_cache_3_virtualAddress_0 <= MmuPlugin_shared_vpn_0; + MmuPlugin_ports_1_cache_3_virtualAddress_1 <= MmuPlugin_shared_vpn_1; + MmuPlugin_ports_1_cache_3_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; + MmuPlugin_ports_1_cache_3_physicalAddress_1 <= MmuPlugin_shared_dBusRsp_pte_PPN1[9 : 0]; + MmuPlugin_ports_1_cache_3_allowRead <= MmuPlugin_shared_dBusRsp_pte_R; + MmuPlugin_ports_1_cache_3_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; + MmuPlugin_ports_1_cache_3_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; + MmuPlugin_ports_1_cache_3_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; + MmuPlugin_ports_1_cache_3_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); + end + end + end + if(when_Pipeline_l124) begin + decode_to_execute_PC <= _zz_decode_SRC2; + end + if(when_Pipeline_l124_1) begin + execute_to_memory_PC <= execute_PC; + end + if(when_Pipeline_l124_2) begin + memory_to_writeBack_PC <= memory_PC; + end + if(when_Pipeline_l124_3) begin + decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; + end + if(when_Pipeline_l124_4) begin + execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; + end + if(when_Pipeline_l124_5) begin + memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; + end + if(when_Pipeline_l124_6) begin + decode_to_execute_FORMAL_PC_NEXT <= _zz_decode_to_execute_FORMAL_PC_NEXT; + end + if(when_Pipeline_l124_7) begin + execute_to_memory_FORMAL_PC_NEXT <= _zz_execute_to_memory_FORMAL_PC_NEXT; + end + if(when_Pipeline_l124_8) begin + memory_to_writeBack_FORMAL_PC_NEXT <= _zz_memory_to_writeBack_FORMAL_PC_NEXT; + end + if(when_Pipeline_l124_9) begin + decode_to_execute_MEMORY_FORCE_CONSTISTENCY <= decode_MEMORY_FORCE_CONSTISTENCY; + end + if(when_Pipeline_l124_10) begin + decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; + end + if(when_Pipeline_l124_11) begin + decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; + end + if(when_Pipeline_l124_12) begin + execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; + end + if(when_Pipeline_l124_13) begin + memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; + end + if(when_Pipeline_l124_14) begin + decode_to_execute_ALU_CTRL <= _zz_decode_to_execute_ALU_CTRL; + end + if(when_Pipeline_l124_15) begin + decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; + end + if(when_Pipeline_l124_16) begin + execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; + end + if(when_Pipeline_l124_17) begin + memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; + end + if(when_Pipeline_l124_18) begin + decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; + end + if(when_Pipeline_l124_19) begin + decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; + end + if(when_Pipeline_l124_20) begin + execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; + end + if(when_Pipeline_l124_21) begin + decode_to_execute_MEMORY_WR <= decode_MEMORY_WR; + end + if(when_Pipeline_l124_22) begin + execute_to_memory_MEMORY_WR <= execute_MEMORY_WR; + end + if(when_Pipeline_l124_23) begin + memory_to_writeBack_MEMORY_WR <= memory_MEMORY_WR; + end + if(when_Pipeline_l124_24) begin + decode_to_execute_MEMORY_LRSC <= decode_MEMORY_LRSC; + end + if(when_Pipeline_l124_25) begin + execute_to_memory_MEMORY_LRSC <= execute_MEMORY_LRSC; + end + if(when_Pipeline_l124_26) begin + memory_to_writeBack_MEMORY_LRSC <= memory_MEMORY_LRSC; + end + if(when_Pipeline_l124_27) begin + decode_to_execute_MEMORY_AMO <= decode_MEMORY_AMO; + end + if(when_Pipeline_l124_28) begin + decode_to_execute_MEMORY_MANAGMENT <= decode_MEMORY_MANAGMENT; + end + if(when_Pipeline_l124_29) begin + decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; + end + if(when_Pipeline_l124_30) begin + decode_to_execute_ALU_BITWISE_CTRL <= _zz_decode_to_execute_ALU_BITWISE_CTRL; + end + if(when_Pipeline_l124_31) begin + decode_to_execute_SHIFT_CTRL <= _zz_decode_to_execute_SHIFT_CTRL; + end + if(when_Pipeline_l124_32) begin + execute_to_memory_SHIFT_CTRL <= _zz_execute_to_memory_SHIFT_CTRL; + end + if(when_Pipeline_l124_33) begin + decode_to_execute_IS_MUL <= decode_IS_MUL; + end + if(when_Pipeline_l124_34) begin + execute_to_memory_IS_MUL <= execute_IS_MUL; + end + if(when_Pipeline_l124_35) begin + memory_to_writeBack_IS_MUL <= memory_IS_MUL; + end + if(when_Pipeline_l124_36) begin + decode_to_execute_IS_DIV <= decode_IS_DIV; + end + if(when_Pipeline_l124_37) begin + execute_to_memory_IS_DIV <= execute_IS_DIV; + end + if(when_Pipeline_l124_38) begin + decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED; + end + if(when_Pipeline_l124_39) begin + decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED; + end + if(when_Pipeline_l124_40) begin + decode_to_execute_IS_CSR <= decode_IS_CSR; + end + if(when_Pipeline_l124_41) begin + decode_to_execute_ENV_CTRL <= _zz_decode_to_execute_ENV_CTRL; + end + if(when_Pipeline_l124_42) begin + execute_to_memory_ENV_CTRL <= _zz_execute_to_memory_ENV_CTRL; + end + if(when_Pipeline_l124_43) begin + memory_to_writeBack_ENV_CTRL <= _zz_memory_to_writeBack_ENV_CTRL; + end + if(when_Pipeline_l124_44) begin + decode_to_execute_IS_SFENCE_VMA <= decode_IS_SFENCE_VMA; + end + if(when_Pipeline_l124_45) begin + decode_to_execute_IS_SFENCE_VMA2 <= decode_IS_SFENCE_VMA2; + end + if(when_Pipeline_l124_46) begin + decode_to_execute_BRANCH_CTRL <= _zz_decode_to_execute_BRANCH_CTRL; + end + if(when_Pipeline_l124_47) begin + decode_to_execute_RS1 <= _zz_decode_SRC1; + end + if(when_Pipeline_l124_48) begin + decode_to_execute_RS2 <= _zz_decode_SRC2_1; + end + if(when_Pipeline_l124_49) begin + decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; + end + if(when_Pipeline_l124_50) begin + decode_to_execute_SRC1 <= decode_SRC1; + end + if(when_Pipeline_l124_51) begin + decode_to_execute_SRC2 <= decode_SRC2; + end + if(when_Pipeline_l124_52) begin + decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; + end + if(when_Pipeline_l124_53) begin + decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; + end + if(when_Pipeline_l124_54) begin + decode_to_execute_DO_EBREAK <= decode_DO_EBREAK; + end + if(when_Pipeline_l124_55) begin + decode_to_execute_PREDICTION_HAD_BRANCHED2 <= decode_PREDICTION_HAD_BRANCHED2; + end + if(when_Pipeline_l124_56) begin + execute_to_memory_MEMORY_STORE_DATA_RF <= execute_MEMORY_STORE_DATA_RF; + end + if(when_Pipeline_l124_57) begin + memory_to_writeBack_MEMORY_STORE_DATA_RF <= memory_MEMORY_STORE_DATA_RF; + end + if(when_Pipeline_l124_60) begin + execute_to_memory_REGFILE_WRITE_DATA <= _zz_decode_RS2; + end + if(when_Pipeline_l124_61) begin + memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_decode_RS2_1; + end + if(when_Pipeline_l124_62) begin + execute_to_memory_SHIFT_RIGHT <= execute_SHIFT_RIGHT; + end + if(when_Pipeline_l124_63) begin + execute_to_memory_MUL_LL <= execute_MUL_LL; + end + if(when_Pipeline_l124_64) begin + execute_to_memory_MUL_LH <= execute_MUL_LH; + end + if(when_Pipeline_l124_65) begin + execute_to_memory_MUL_HL <= execute_MUL_HL; + end + if(when_Pipeline_l124_66) begin + execute_to_memory_MUL_HH <= execute_MUL_HH; + end + if(when_Pipeline_l124_67) begin + memory_to_writeBack_MUL_HH <= memory_MUL_HH; + end + if(when_Pipeline_l124_68) begin + execute_to_memory_BRANCH_DO <= execute_BRANCH_DO; + end + if(when_Pipeline_l124_69) begin + execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC; + end + if(when_Pipeline_l124_70) begin + memory_to_writeBack_MUL_LOW <= memory_MUL_LOW; + end + if(when_CsrPlugin_l1264) begin + execute_CsrPlugin_csr_3857 <= (decode_INSTRUCTION[31 : 20] == 12'hf11); + end + if(when_CsrPlugin_l1264_1) begin + execute_CsrPlugin_csr_3858 <= (decode_INSTRUCTION[31 : 20] == 12'hf12); + end + if(when_CsrPlugin_l1264_2) begin + execute_CsrPlugin_csr_3859 <= (decode_INSTRUCTION[31 : 20] == 12'hf13); + end + if(when_CsrPlugin_l1264_3) begin + execute_CsrPlugin_csr_3860 <= (decode_INSTRUCTION[31 : 20] == 12'hf14); + end + if(when_CsrPlugin_l1264_4) begin + execute_CsrPlugin_csr_768 <= (decode_INSTRUCTION[31 : 20] == 12'h300); + end + if(when_CsrPlugin_l1264_5) begin + execute_CsrPlugin_csr_836 <= (decode_INSTRUCTION[31 : 20] == 12'h344); + end + if(when_CsrPlugin_l1264_6) begin + execute_CsrPlugin_csr_772 <= (decode_INSTRUCTION[31 : 20] == 12'h304); + end + if(when_CsrPlugin_l1264_7) begin + execute_CsrPlugin_csr_773 <= (decode_INSTRUCTION[31 : 20] == 12'h305); + end + if(when_CsrPlugin_l1264_8) begin + execute_CsrPlugin_csr_833 <= (decode_INSTRUCTION[31 : 20] == 12'h341); + end + if(when_CsrPlugin_l1264_9) begin + execute_CsrPlugin_csr_832 <= (decode_INSTRUCTION[31 : 20] == 12'h340); + end + if(when_CsrPlugin_l1264_10) begin + execute_CsrPlugin_csr_834 <= (decode_INSTRUCTION[31 : 20] == 12'h342); + end + if(when_CsrPlugin_l1264_11) begin + execute_CsrPlugin_csr_835 <= (decode_INSTRUCTION[31 : 20] == 12'h343); + end + if(when_CsrPlugin_l1264_12) begin + execute_CsrPlugin_csr_770 <= (decode_INSTRUCTION[31 : 20] == 12'h302); + end + if(when_CsrPlugin_l1264_13) begin + execute_CsrPlugin_csr_771 <= (decode_INSTRUCTION[31 : 20] == 12'h303); + end + if(when_CsrPlugin_l1264_14) begin + execute_CsrPlugin_csr_256 <= (decode_INSTRUCTION[31 : 20] == 12'h100); + end + if(when_CsrPlugin_l1264_15) begin + execute_CsrPlugin_csr_324 <= (decode_INSTRUCTION[31 : 20] == 12'h144); + end + if(when_CsrPlugin_l1264_16) begin + execute_CsrPlugin_csr_260 <= (decode_INSTRUCTION[31 : 20] == 12'h104); + end + if(when_CsrPlugin_l1264_17) begin + execute_CsrPlugin_csr_261 <= (decode_INSTRUCTION[31 : 20] == 12'h105); + end + if(when_CsrPlugin_l1264_18) begin + execute_CsrPlugin_csr_321 <= (decode_INSTRUCTION[31 : 20] == 12'h141); + end + if(when_CsrPlugin_l1264_19) begin + execute_CsrPlugin_csr_320 <= (decode_INSTRUCTION[31 : 20] == 12'h140); + end + if(when_CsrPlugin_l1264_20) begin + execute_CsrPlugin_csr_322 <= (decode_INSTRUCTION[31 : 20] == 12'h142); + end + if(when_CsrPlugin_l1264_21) begin + execute_CsrPlugin_csr_323 <= (decode_INSTRUCTION[31 : 20] == 12'h143); + end + if(when_CsrPlugin_l1264_22) begin + execute_CsrPlugin_csr_384 <= (decode_INSTRUCTION[31 : 20] == 12'h180); + end + if(execute_CsrPlugin_csr_836) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mip_MSIP <= CsrPlugin_csrMapping_writeDataSignal[3]; + end + end + if(execute_CsrPlugin_csr_833) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mepc <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; + end + end + if(execute_CsrPlugin_csr_832) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mscratch <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; + end + end + if(execute_CsrPlugin_csr_261) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_stvec_base <= CsrPlugin_csrMapping_writeDataSignal[31 : 2]; + CsrPlugin_stvec_mode <= CsrPlugin_csrMapping_writeDataSignal[1 : 0]; + end + end + if(execute_CsrPlugin_csr_321) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_sepc <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; + end + end + if(execute_CsrPlugin_csr_320) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_sscratch <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; + end + end + if(execute_CsrPlugin_csr_322) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_scause_interrupt <= CsrPlugin_csrMapping_writeDataSignal[31]; + CsrPlugin_scause_exceptionCode <= CsrPlugin_csrMapping_writeDataSignal[3 : 0]; + end + end + if(execute_CsrPlugin_csr_323) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_stval <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; + end + end + if(execute_CsrPlugin_csr_384) begin + if(execute_CsrPlugin_writeEnable) begin + MmuPlugin_satp_asid <= CsrPlugin_csrMapping_writeDataSignal[30 : 22]; + MmuPlugin_satp_ppn <= CsrPlugin_csrMapping_writeDataSignal[19 : 0]; + end + end + end + + always @(posedge clk) begin + DebugPlugin_firstCycle <= 1'b0; + if(debug_bus_cmd_ready) begin + DebugPlugin_firstCycle <= 1'b1; + end + DebugPlugin_secondCycle <= DebugPlugin_firstCycle; + DebugPlugin_isPipBusy <= (({writeBack_arbitration_isValid,{memory_arbitration_isValid,{execute_arbitration_isValid,decode_arbitration_isValid}}} != 4'b0000) || IBusCachedPlugin_incomingInstruction); + if(writeBack_arbitration_isValid) begin + DebugPlugin_busReadDataReg <= _zz_decode_RS2_2; + end + _zz_when_DebugPlugin_l244 <= debug_bus_cmd_payload_address[2]; + if(when_DebugPlugin_l284) begin + DebugPlugin_busReadDataReg <= execute_PC; + end + DebugPlugin_resetIt_regNext <= DebugPlugin_resetIt; + end + + always @(posedge clk or posedge debugReset) begin + if(debugReset) begin + DebugPlugin_resetIt <= 1'b0; + DebugPlugin_haltIt <= 1'b0; + DebugPlugin_stepIt <= 1'b0; + DebugPlugin_godmode <= 1'b0; + DebugPlugin_haltedByBreak <= 1'b0; + DebugPlugin_debugUsed <= 1'b0; + DebugPlugin_disableEbreak <= 1'b0; + end else begin + if(when_DebugPlugin_l225) begin + DebugPlugin_godmode <= 1'b1; + end + if(debug_bus_cmd_valid) begin + DebugPlugin_debugUsed <= 1'b1; + end + if(debug_bus_cmd_valid) begin + case(switch_DebugPlugin_l256) + 6'h0 : begin + if(debug_bus_cmd_payload_wr) begin + DebugPlugin_stepIt <= debug_bus_cmd_payload_data[4]; + if(when_DebugPlugin_l260) begin + DebugPlugin_resetIt <= 1'b1; + end + if(when_DebugPlugin_l260_1) begin + DebugPlugin_resetIt <= 1'b0; + end + if(when_DebugPlugin_l261) begin + DebugPlugin_haltIt <= 1'b1; + end + if(when_DebugPlugin_l261_1) begin + DebugPlugin_haltIt <= 1'b0; + end + if(when_DebugPlugin_l262) begin + DebugPlugin_haltedByBreak <= 1'b0; + end + if(when_DebugPlugin_l263) begin + DebugPlugin_godmode <= 1'b0; + end + if(when_DebugPlugin_l264) begin + DebugPlugin_disableEbreak <= 1'b1; + end + if(when_DebugPlugin_l264_1) begin + DebugPlugin_disableEbreak <= 1'b0; + end + end + end + default : begin + end + endcase + end + if(when_DebugPlugin_l284) begin + if(when_DebugPlugin_l287) begin + DebugPlugin_haltIt <= 1'b1; + DebugPlugin_haltedByBreak <= 1'b1; + end + end + if(when_DebugPlugin_l300) begin + if(decode_arbitration_isValid) begin + DebugPlugin_haltIt <= 1'b1; + end + end + end + end + + +endmodule + +module DataCache ( + input io_cpu_execute_isValid, + input [31:0] io_cpu_execute_address, + output reg io_cpu_execute_haltIt, + input io_cpu_execute_args_wr, + input [1:0] io_cpu_execute_args_size, + input io_cpu_execute_args_isLrsc, + input io_cpu_execute_args_isAmo, + input io_cpu_execute_args_amoCtrl_swap, + input [2:0] io_cpu_execute_args_amoCtrl_alu, + input io_cpu_execute_args_totalyConsistent, + output io_cpu_execute_refilling, + input io_cpu_memory_isValid, + input io_cpu_memory_isStuck, + output io_cpu_memory_isWrite, + input [31:0] io_cpu_memory_address, + input [31:0] io_cpu_memory_mmuRsp_physicalAddress, + input io_cpu_memory_mmuRsp_isIoAccess, + input io_cpu_memory_mmuRsp_isPaging, + input io_cpu_memory_mmuRsp_allowRead, + input io_cpu_memory_mmuRsp_allowWrite, + input io_cpu_memory_mmuRsp_allowExecute, + input io_cpu_memory_mmuRsp_exception, + input io_cpu_memory_mmuRsp_refilling, + input io_cpu_memory_mmuRsp_bypassTranslation, + input io_cpu_memory_mmuRsp_ways_0_sel, + input [31:0] io_cpu_memory_mmuRsp_ways_0_physical, + input io_cpu_memory_mmuRsp_ways_1_sel, + input [31:0] io_cpu_memory_mmuRsp_ways_1_physical, + input io_cpu_memory_mmuRsp_ways_2_sel, + input [31:0] io_cpu_memory_mmuRsp_ways_2_physical, + input io_cpu_memory_mmuRsp_ways_3_sel, + input [31:0] io_cpu_memory_mmuRsp_ways_3_physical, + input io_cpu_writeBack_isValid, + input io_cpu_writeBack_isStuck, + input io_cpu_writeBack_isUser, + output reg io_cpu_writeBack_haltIt, + output io_cpu_writeBack_isWrite, + input [31:0] io_cpu_writeBack_storeData, + output reg [31:0] io_cpu_writeBack_data, + input [31:0] io_cpu_writeBack_address, + output io_cpu_writeBack_mmuException, + output io_cpu_writeBack_unalignedAccess, + output reg io_cpu_writeBack_accessError, + output io_cpu_writeBack_keepMemRspData, + input io_cpu_writeBack_fence_SW, + input io_cpu_writeBack_fence_SR, + input io_cpu_writeBack_fence_SO, + input io_cpu_writeBack_fence_SI, + input io_cpu_writeBack_fence_PW, + input io_cpu_writeBack_fence_PR, + input io_cpu_writeBack_fence_PO, + input io_cpu_writeBack_fence_PI, + input [3:0] io_cpu_writeBack_fence_FM, + output io_cpu_writeBack_exclusiveOk, + output reg io_cpu_redo, + input io_cpu_flush_valid, + output io_cpu_flush_ready, + output reg io_mem_cmd_valid, + input io_mem_cmd_ready, + output reg io_mem_cmd_payload_wr, + output io_mem_cmd_payload_uncached, + output reg [31:0] io_mem_cmd_payload_address, + output [31:0] io_mem_cmd_payload_data, + output [3:0] io_mem_cmd_payload_mask, + output reg [2:0] io_mem_cmd_payload_size, + output io_mem_cmd_payload_last, + input io_mem_rsp_valid, + input io_mem_rsp_payload_last, + input [31:0] io_mem_rsp_payload_data, + input io_mem_rsp_payload_error, + input clk, + input reset +); + reg [21:0] _zz_ways_0_tags_port0; + reg [31:0] _zz_ways_0_data_port0; + wire [21:0] _zz_ways_0_tags_port; + wire [9:0] _zz_stage0_dataColisions; + wire [9:0] _zz__zz_stageA_dataColisions; + wire [31:0] _zz_stageB_amo_addSub; + wire [31:0] _zz_stageB_amo_addSub_1; + wire [31:0] _zz_stageB_amo_addSub_2; + wire [31:0] _zz_stageB_amo_addSub_3; + wire [31:0] _zz_stageB_amo_addSub_4; + wire [1:0] _zz_stageB_amo_addSub_5; + wire [1:0] _zz_stageB_amo_addSub_6; + wire [1:0] _zz_stageB_amo_addSub_7; + wire [0:0] _zz_when; + wire [2:0] _zz_loader_counter_valueNext; + wire [0:0] _zz_loader_counter_valueNext_1; + wire [1:0] _zz_loader_waysAllocator; + reg _zz_1; + reg _zz_2; + wire haltCpu; + reg tagsReadCmd_valid; + reg [6:0] tagsReadCmd_payload; + reg tagsWriteCmd_valid; + reg [0:0] tagsWriteCmd_payload_way; + reg [6:0] tagsWriteCmd_payload_address; + reg tagsWriteCmd_payload_data_valid; + reg tagsWriteCmd_payload_data_error; + reg [19:0] tagsWriteCmd_payload_data_address; + reg tagsWriteLastCmd_valid; + reg [0:0] tagsWriteLastCmd_payload_way; + reg [6:0] tagsWriteLastCmd_payload_address; + reg tagsWriteLastCmd_payload_data_valid; + reg tagsWriteLastCmd_payload_data_error; + reg [19:0] tagsWriteLastCmd_payload_data_address; + reg dataReadCmd_valid; + reg [9:0] dataReadCmd_payload; + reg dataWriteCmd_valid; + reg [0:0] dataWriteCmd_payload_way; + reg [9:0] dataWriteCmd_payload_address; + reg [31:0] dataWriteCmd_payload_data; + reg [3:0] dataWriteCmd_payload_mask; + wire _zz_ways_0_tagsReadRsp_valid; + wire ways_0_tagsReadRsp_valid; + wire ways_0_tagsReadRsp_error; + wire [19:0] ways_0_tagsReadRsp_address; + wire [21:0] _zz_ways_0_tagsReadRsp_valid_1; + wire _zz_ways_0_dataReadRspMem; + wire [31:0] ways_0_dataReadRspMem; + wire [31:0] ways_0_dataReadRsp; + wire when_DataCache_l634; + wire when_DataCache_l637; + wire when_DataCache_l656; + wire rspSync; + wire rspLast; + reg memCmdSent; + wire when_DataCache_l678; + wire when_DataCache_l678_1; + reg [3:0] _zz_stage0_mask; + wire [3:0] stage0_mask; + wire [0:0] stage0_dataColisions; + wire [0:0] stage0_wayInvalidate; + wire when_DataCache_l763; + reg stageA_request_wr; + reg [1:0] stageA_request_size; + reg stageA_request_isLrsc; + reg stageA_request_isAmo; + reg stageA_request_amoCtrl_swap; + reg [2:0] stageA_request_amoCtrl_alu; + reg stageA_request_totalyConsistent; + wire when_DataCache_l763_1; + reg [3:0] stageA_mask; + wire [0:0] stageA_wayHits; + wire when_DataCache_l763_2; + reg [0:0] stageA_wayInvalidate; + wire when_DataCache_l763_3; + reg [0:0] stage0_dataColisions_regNextWhen; + wire [0:0] _zz_stageA_dataColisions; + wire [0:0] stageA_dataColisions; + wire when_DataCache_l814; + reg stageB_request_wr; + reg [1:0] stageB_request_size; + reg stageB_request_isLrsc; + reg stageB_request_isAmo; + reg stageB_request_amoCtrl_swap; + reg [2:0] stageB_request_amoCtrl_alu; + reg stageB_request_totalyConsistent; + reg stageB_mmuRspFreeze; + wire when_DataCache_l816; + reg [31:0] stageB_mmuRsp_physicalAddress; + reg stageB_mmuRsp_isIoAccess; + reg stageB_mmuRsp_isPaging; + reg stageB_mmuRsp_allowRead; + reg stageB_mmuRsp_allowWrite; + reg stageB_mmuRsp_allowExecute; + reg stageB_mmuRsp_exception; + reg stageB_mmuRsp_refilling; + reg stageB_mmuRsp_bypassTranslation; + reg stageB_mmuRsp_ways_0_sel; + reg [31:0] stageB_mmuRsp_ways_0_physical; + reg stageB_mmuRsp_ways_1_sel; + reg [31:0] stageB_mmuRsp_ways_1_physical; + reg stageB_mmuRsp_ways_2_sel; + reg [31:0] stageB_mmuRsp_ways_2_physical; + reg stageB_mmuRsp_ways_3_sel; + reg [31:0] stageB_mmuRsp_ways_3_physical; + wire when_DataCache_l813; + reg stageB_tagsReadRsp_0_valid; + reg stageB_tagsReadRsp_0_error; + reg [19:0] stageB_tagsReadRsp_0_address; + wire when_DataCache_l813_1; + reg [31:0] stageB_dataReadRsp_0; + wire when_DataCache_l812; + reg [0:0] stageB_wayInvalidate; + wire stageB_consistancyHazard; + wire when_DataCache_l812_1; + reg [0:0] stageB_dataColisions; + wire when_DataCache_l812_2; + reg stageB_unaligned; + wire when_DataCache_l812_3; + reg [0:0] stageB_waysHitsBeforeInvalidate; + wire [0:0] stageB_waysHits; + wire stageB_waysHit; + wire [31:0] stageB_dataMux; + wire when_DataCache_l812_4; + reg [3:0] stageB_mask; + reg stageB_loaderValid; + wire [31:0] stageB_ioMemRspMuxed; + reg stageB_flusher_waitDone; + wire stageB_flusher_hold; + reg [7:0] stageB_flusher_counter; + wire when_DataCache_l842; + wire when_DataCache_l848; + reg stageB_flusher_start; + reg stageB_lrSc_reserved; + wire when_DataCache_l866; + wire stageB_isExternalLsrc; + wire stageB_isExternalAmo; + reg [31:0] stageB_requestDataBypass; + wire stageB_amo_compare; + wire stageB_amo_unsigned; + wire [31:0] stageB_amo_addSub; + wire stageB_amo_less; + wire stageB_amo_selectRf; + wire [2:0] switch_Misc_l199; + reg [31:0] stageB_amo_result; + reg [31:0] stageB_amo_resultReg; + reg stageB_amo_internal_resultRegValid; + reg stageB_cpuWriteToCache; + wire when_DataCache_l911; + wire stageB_badPermissions; + wire stageB_loadStoreFault; + wire stageB_bypassCache; + wire when_DataCache_l980; + wire when_DataCache_l984; + wire when_DataCache_l989; + wire when_DataCache_l994; + wire when_DataCache_l997; + wire when_DataCache_l1005; + wire when_DataCache_l1010; + wire when_DataCache_l1017; + wire when_DataCache_l976; + wire when_DataCache_l1051; + wire when_DataCache_l1060; + reg loader_valid; + reg loader_counter_willIncrement; + wire loader_counter_willClear; + reg [2:0] loader_counter_valueNext; + reg [2:0] loader_counter_value; + wire loader_counter_willOverflowIfInc; + wire loader_counter_willOverflow; + reg [0:0] loader_waysAllocator; + reg loader_error; + wire loader_kill; + reg loader_killReg; + wire when_DataCache_l1075; + wire loader_done; + wire when_DataCache_l1103; + reg loader_valid_regNext; + wire when_DataCache_l1107; + wire when_DataCache_l1110; + reg [21:0] ways_0_tags [0:127]; + reg [7:0] ways_0_data_symbol0 [0:1023]; + reg [7:0] ways_0_data_symbol1 [0:1023]; + reg [7:0] ways_0_data_symbol2 [0:1023]; + reg [7:0] ways_0_data_symbol3 [0:1023]; + reg [7:0] _zz_ways_0_datasymbol_read; + reg [7:0] _zz_ways_0_datasymbol_read_1; + reg [7:0] _zz_ways_0_datasymbol_read_2; + reg [7:0] _zz_ways_0_datasymbol_read_3; + + assign _zz_stage0_dataColisions = (io_cpu_execute_address[11 : 2] >>> 0); + assign _zz__zz_stageA_dataColisions = (io_cpu_memory_address[11 : 2] >>> 0); + assign _zz_stageB_amo_addSub = ($signed(_zz_stageB_amo_addSub_1) + $signed(_zz_stageB_amo_addSub_4)); + assign _zz_stageB_amo_addSub_1 = ($signed(_zz_stageB_amo_addSub_2) + $signed(_zz_stageB_amo_addSub_3)); + assign _zz_stageB_amo_addSub_2 = io_cpu_writeBack_storeData[31 : 0]; + assign _zz_stageB_amo_addSub_3 = (stageB_amo_compare ? (~ stageB_dataMux[31 : 0]) : stageB_dataMux[31 : 0]); + assign _zz_stageB_amo_addSub_5 = (stageB_amo_compare ? _zz_stageB_amo_addSub_6 : _zz_stageB_amo_addSub_7); + assign _zz_stageB_amo_addSub_4 = {{30{_zz_stageB_amo_addSub_5[1]}}, _zz_stageB_amo_addSub_5}; + assign _zz_stageB_amo_addSub_6 = 2'b01; + assign _zz_stageB_amo_addSub_7 = 2'b00; + assign _zz_when = 1'b1; + assign _zz_loader_counter_valueNext_1 = loader_counter_willIncrement; + assign _zz_loader_counter_valueNext = {2'd0, _zz_loader_counter_valueNext_1}; + assign _zz_loader_waysAllocator = {loader_waysAllocator,loader_waysAllocator[0]}; + assign _zz_ways_0_tags_port = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; + always @(posedge clk) begin + if(_zz_ways_0_tagsReadRsp_valid) begin + _zz_ways_0_tags_port0 <= ways_0_tags[tagsReadCmd_payload]; + end + end + + always @(posedge clk) begin + if(_zz_2) begin + ways_0_tags[tagsWriteCmd_payload_address] <= _zz_ways_0_tags_port; + end + end + + always @(*) begin + _zz_ways_0_data_port0 = {_zz_ways_0_datasymbol_read_3, _zz_ways_0_datasymbol_read_2, _zz_ways_0_datasymbol_read_1, _zz_ways_0_datasymbol_read}; + end + always @(posedge clk) begin + if(_zz_ways_0_dataReadRspMem) begin + _zz_ways_0_datasymbol_read <= ways_0_data_symbol0[dataReadCmd_payload]; + _zz_ways_0_datasymbol_read_1 <= ways_0_data_symbol1[dataReadCmd_payload]; + _zz_ways_0_datasymbol_read_2 <= ways_0_data_symbol2[dataReadCmd_payload]; + _zz_ways_0_datasymbol_read_3 <= ways_0_data_symbol3[dataReadCmd_payload]; + end + end + + always @(posedge clk) begin + if(dataWriteCmd_payload_mask[0] && _zz_1) begin + ways_0_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0]; + end + if(dataWriteCmd_payload_mask[1] && _zz_1) begin + ways_0_data_symbol1[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[15 : 8]; + end + if(dataWriteCmd_payload_mask[2] && _zz_1) begin + ways_0_data_symbol2[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[23 : 16]; + end + if(dataWriteCmd_payload_mask[3] && _zz_1) begin + ways_0_data_symbol3[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[31 : 24]; + end + end + + always @(*) begin + _zz_1 = 1'b0; + if(when_DataCache_l637) begin + _zz_1 = 1'b1; + end + end + + always @(*) begin + _zz_2 = 1'b0; + if(when_DataCache_l634) begin + _zz_2 = 1'b1; + end + end + + assign haltCpu = 1'b0; + assign _zz_ways_0_tagsReadRsp_valid = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); + assign _zz_ways_0_tagsReadRsp_valid_1 = _zz_ways_0_tags_port0; + assign ways_0_tagsReadRsp_valid = _zz_ways_0_tagsReadRsp_valid_1[0]; + assign ways_0_tagsReadRsp_error = _zz_ways_0_tagsReadRsp_valid_1[1]; + assign ways_0_tagsReadRsp_address = _zz_ways_0_tagsReadRsp_valid_1[21 : 2]; + assign _zz_ways_0_dataReadRspMem = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); + assign ways_0_dataReadRspMem = _zz_ways_0_data_port0; + assign ways_0_dataReadRsp = ways_0_dataReadRspMem[31 : 0]; + assign when_DataCache_l634 = (tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]); + assign when_DataCache_l637 = (dataWriteCmd_valid && dataWriteCmd_payload_way[0]); + always @(*) begin + tagsReadCmd_valid = 1'b0; + if(when_DataCache_l656) begin + tagsReadCmd_valid = 1'b1; + end + end + + always @(*) begin + tagsReadCmd_payload = 7'bxxxxxxx; + if(when_DataCache_l656) begin + tagsReadCmd_payload = io_cpu_execute_address[11 : 5]; + end + end + + always @(*) begin + dataReadCmd_valid = 1'b0; + if(when_DataCache_l656) begin + dataReadCmd_valid = 1'b1; + end + end + + always @(*) begin + dataReadCmd_payload = 10'bxxxxxxxxxx; + if(when_DataCache_l656) begin + dataReadCmd_payload = io_cpu_execute_address[11 : 2]; + end + end + + always @(*) begin + tagsWriteCmd_valid = 1'b0; + if(when_DataCache_l842) begin + tagsWriteCmd_valid = 1'b1; + end + if(when_DataCache_l1051) begin + tagsWriteCmd_valid = 1'b0; + end + if(loader_done) begin + tagsWriteCmd_valid = 1'b1; + end + end + + always @(*) begin + tagsWriteCmd_payload_way = 1'bx; + if(when_DataCache_l842) begin + tagsWriteCmd_payload_way = 1'b1; + end + if(loader_done) begin + tagsWriteCmd_payload_way = loader_waysAllocator; + end + end + + always @(*) begin + tagsWriteCmd_payload_address = 7'bxxxxxxx; + if(when_DataCache_l842) begin + tagsWriteCmd_payload_address = stageB_flusher_counter[6:0]; + end + if(loader_done) begin + tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; + end + end + + always @(*) begin + tagsWriteCmd_payload_data_valid = 1'bx; + if(when_DataCache_l842) begin + tagsWriteCmd_payload_data_valid = 1'b0; + end + if(loader_done) begin + tagsWriteCmd_payload_data_valid = (! (loader_kill || loader_killReg)); + end + end + + always @(*) begin + tagsWriteCmd_payload_data_error = 1'bx; + if(loader_done) begin + tagsWriteCmd_payload_data_error = (loader_error || (io_mem_rsp_valid && io_mem_rsp_payload_error)); + end + end + + always @(*) begin + tagsWriteCmd_payload_data_address = 20'bxxxxxxxxxxxxxxxxxxxx; + if(loader_done) begin + tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 12]; + end + end + + always @(*) begin + dataWriteCmd_valid = 1'b0; + if(stageB_cpuWriteToCache) begin + if(when_DataCache_l911) begin + dataWriteCmd_valid = 1'b1; + end + end + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(when_DataCache_l989) begin + if(stageB_request_isAmo) begin + if(when_DataCache_l997) begin + dataWriteCmd_valid = 1'b0; + end + end + if(when_DataCache_l1010) begin + dataWriteCmd_valid = 1'b0; + end + end + end + end + end + if(when_DataCache_l1051) begin + dataWriteCmd_valid = 1'b0; + end + if(when_DataCache_l1075) begin + dataWriteCmd_valid = 1'b1; + end + end + + always @(*) begin + dataWriteCmd_payload_way = 1'bx; + if(stageB_cpuWriteToCache) begin + dataWriteCmd_payload_way = stageB_waysHits; + end + if(when_DataCache_l1075) begin + dataWriteCmd_payload_way = loader_waysAllocator; + end + end + + always @(*) begin + dataWriteCmd_payload_address = 10'bxxxxxxxxxx; + if(stageB_cpuWriteToCache) begin + dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 2]; + end + if(when_DataCache_l1075) begin + dataWriteCmd_payload_address = {stageB_mmuRsp_physicalAddress[11 : 5],loader_counter_value}; + end + end + + always @(*) begin + dataWriteCmd_payload_data = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + if(stageB_cpuWriteToCache) begin + dataWriteCmd_payload_data[31 : 0] = stageB_requestDataBypass; + end + if(when_DataCache_l1075) begin + dataWriteCmd_payload_data = io_mem_rsp_payload_data; + end + end + + always @(*) begin + dataWriteCmd_payload_mask = 4'bxxxx; + if(stageB_cpuWriteToCache) begin + dataWriteCmd_payload_mask = 4'b0000; + if(_zz_when[0]) begin + dataWriteCmd_payload_mask[3 : 0] = stageB_mask; + end + end + if(when_DataCache_l1075) begin + dataWriteCmd_payload_mask = 4'b1111; + end + end + + assign when_DataCache_l656 = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck)); + always @(*) begin + io_cpu_execute_haltIt = 1'b0; + if(when_DataCache_l842) begin + io_cpu_execute_haltIt = 1'b1; + end + end + + assign rspSync = 1'b1; + assign rspLast = 1'b1; + assign when_DataCache_l678 = (io_mem_cmd_valid && io_mem_cmd_ready); + assign when_DataCache_l678_1 = (! io_cpu_writeBack_isStuck); + always @(*) begin + _zz_stage0_mask = 4'bxxxx; + case(io_cpu_execute_args_size) + 2'b00 : begin + _zz_stage0_mask = 4'b0001; + end + 2'b01 : begin + _zz_stage0_mask = 4'b0011; + end + 2'b10 : begin + _zz_stage0_mask = 4'b1111; + end + default : begin + end + endcase + end + + assign stage0_mask = (_zz_stage0_mask <<< io_cpu_execute_address[1 : 0]); + assign stage0_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_stage0_dataColisions)) && ((stage0_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); + assign stage0_wayInvalidate = 1'b0; + assign when_DataCache_l763 = (! io_cpu_memory_isStuck); + assign when_DataCache_l763_1 = (! io_cpu_memory_isStuck); + assign io_cpu_memory_isWrite = stageA_request_wr; + assign stageA_wayHits = ((io_cpu_memory_mmuRsp_physicalAddress[31 : 12] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid); + assign when_DataCache_l763_2 = (! io_cpu_memory_isStuck); + assign when_DataCache_l763_3 = (! io_cpu_memory_isStuck); + assign _zz_stageA_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz__zz_stageA_dataColisions)) && ((stageA_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); + assign stageA_dataColisions = (stage0_dataColisions_regNextWhen | _zz_stageA_dataColisions); + assign when_DataCache_l814 = (! io_cpu_writeBack_isStuck); + always @(*) begin + stageB_mmuRspFreeze = 1'b0; + if(when_DataCache_l1110) begin + stageB_mmuRspFreeze = 1'b1; + end + end + + assign when_DataCache_l816 = ((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze)); + assign when_DataCache_l813 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l813_1 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l812 = (! io_cpu_writeBack_isStuck); + assign stageB_consistancyHazard = 1'b0; + assign when_DataCache_l812_1 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l812_2 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l812_3 = (! io_cpu_writeBack_isStuck); + assign stageB_waysHits = (stageB_waysHitsBeforeInvalidate & (~ stageB_wayInvalidate)); + assign stageB_waysHit = (stageB_waysHits != 1'b0); + assign stageB_dataMux = stageB_dataReadRsp_0; + assign when_DataCache_l812_4 = (! io_cpu_writeBack_isStuck); + always @(*) begin + stageB_loaderValid = 1'b0; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(!when_DataCache_l989) begin + if(io_mem_cmd_ready) begin + stageB_loaderValid = 1'b1; + end + end + end + end + end + if(when_DataCache_l1051) begin + stageB_loaderValid = 1'b0; + end + end + + assign stageB_ioMemRspMuxed = io_mem_rsp_payload_data[31 : 0]; + always @(*) begin + io_cpu_writeBack_haltIt = 1'b1; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(when_DataCache_l976) begin + if(when_DataCache_l980) begin + io_cpu_writeBack_haltIt = 1'b0; + end + if(when_DataCache_l984) begin + io_cpu_writeBack_haltIt = 1'b0; + end + end else begin + if(when_DataCache_l989) begin + if(when_DataCache_l994) begin + io_cpu_writeBack_haltIt = 1'b0; + end + if(stageB_request_isAmo) begin + if(when_DataCache_l997) begin + io_cpu_writeBack_haltIt = 1'b1; + end + end + if(when_DataCache_l1010) begin + io_cpu_writeBack_haltIt = 1'b0; + end + end + end + end + end + if(when_DataCache_l1051) begin + io_cpu_writeBack_haltIt = 1'b0; + end + end + + assign stageB_flusher_hold = 1'b0; + assign when_DataCache_l842 = (! stageB_flusher_counter[7]); + assign when_DataCache_l848 = (! stageB_flusher_hold); + assign io_cpu_flush_ready = (stageB_flusher_waitDone && stageB_flusher_counter[7]); + assign when_DataCache_l866 = ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_isStuck)) && stageB_request_isLrsc); + assign stageB_isExternalLsrc = 1'b0; + assign stageB_isExternalAmo = 1'b0; + always @(*) begin + stageB_requestDataBypass = io_cpu_writeBack_storeData; + if(stageB_request_isAmo) begin + stageB_requestDataBypass[31 : 0] = stageB_amo_resultReg; + end + end + + assign stageB_amo_compare = stageB_request_amoCtrl_alu[2]; + assign stageB_amo_unsigned = (stageB_request_amoCtrl_alu[2 : 1] == 2'b11); + assign stageB_amo_addSub = _zz_stageB_amo_addSub; + assign stageB_amo_less = ((io_cpu_writeBack_storeData[31] == stageB_dataMux[31]) ? stageB_amo_addSub[31] : (stageB_amo_unsigned ? stageB_dataMux[31] : io_cpu_writeBack_storeData[31])); + assign stageB_amo_selectRf = (stageB_request_amoCtrl_swap ? 1'b1 : (stageB_request_amoCtrl_alu[0] ^ stageB_amo_less)); + assign switch_Misc_l199 = (stageB_request_amoCtrl_alu | {stageB_request_amoCtrl_swap,2'b00}); + always @(*) begin + case(switch_Misc_l199) + 3'b000 : begin + stageB_amo_result = stageB_amo_addSub; + end + 3'b001 : begin + stageB_amo_result = (io_cpu_writeBack_storeData[31 : 0] ^ stageB_dataMux[31 : 0]); + end + 3'b010 : begin + stageB_amo_result = (io_cpu_writeBack_storeData[31 : 0] | stageB_dataMux[31 : 0]); + end + 3'b011 : begin + stageB_amo_result = (io_cpu_writeBack_storeData[31 : 0] & stageB_dataMux[31 : 0]); + end + default : begin + stageB_amo_result = (stageB_amo_selectRf ? io_cpu_writeBack_storeData[31 : 0] : stageB_dataMux[31 : 0]); + end + endcase + end + + always @(*) begin + stageB_cpuWriteToCache = 1'b0; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(when_DataCache_l989) begin + stageB_cpuWriteToCache = 1'b1; + end + end + end + end + end + + assign when_DataCache_l911 = (stageB_request_wr && stageB_waysHit); + assign stageB_badPermissions = (((! stageB_mmuRsp_allowWrite) && stageB_request_wr) || ((! stageB_mmuRsp_allowRead) && ((! stageB_request_wr) || stageB_request_isAmo))); + assign stageB_loadStoreFault = (io_cpu_writeBack_isValid && (stageB_mmuRsp_exception || stageB_badPermissions)); + always @(*) begin + io_cpu_redo = 1'b0; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(when_DataCache_l989) begin + if(when_DataCache_l1005) begin + io_cpu_redo = 1'b1; + end + end + end + end + end + if(when_DataCache_l1060) begin + io_cpu_redo = 1'b1; + end + if(when_DataCache_l1107) begin + io_cpu_redo = 1'b1; + end + end + + always @(*) begin + io_cpu_writeBack_accessError = 1'b0; + if(stageB_bypassCache) begin + io_cpu_writeBack_accessError = ((((! stageB_request_wr) && 1'b1) && io_mem_rsp_valid) && io_mem_rsp_payload_error); + end else begin + io_cpu_writeBack_accessError = (((stageB_waysHits & stageB_tagsReadRsp_0_error) != 1'b0) || (stageB_loadStoreFault && (! stageB_mmuRsp_isPaging))); + end + end + + assign io_cpu_writeBack_mmuException = (stageB_loadStoreFault && stageB_mmuRsp_isPaging); + assign io_cpu_writeBack_unalignedAccess = (io_cpu_writeBack_isValid && stageB_unaligned); + assign io_cpu_writeBack_isWrite = stageB_request_wr; + always @(*) begin + io_mem_cmd_valid = 1'b0; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(when_DataCache_l976) begin + io_mem_cmd_valid = (! memCmdSent); + if(when_DataCache_l984) begin + io_mem_cmd_valid = 1'b0; + end + end else begin + if(when_DataCache_l989) begin + if(stageB_request_wr) begin + io_mem_cmd_valid = 1'b1; + end + if(stageB_request_isAmo) begin + if(when_DataCache_l997) begin + io_mem_cmd_valid = 1'b0; + end + end + if(when_DataCache_l1005) begin + io_mem_cmd_valid = 1'b0; + end + if(when_DataCache_l1010) begin + io_mem_cmd_valid = 1'b0; + end + end else begin + if(when_DataCache_l1017) begin + io_mem_cmd_valid = 1'b1; + end + end + end + end + end + if(when_DataCache_l1051) begin + io_mem_cmd_valid = 1'b0; + end + end + + always @(*) begin + io_mem_cmd_payload_address = stageB_mmuRsp_physicalAddress; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(!when_DataCache_l989) begin + io_mem_cmd_payload_address[4 : 0] = 5'h0; + end + end + end + end + end + + assign io_mem_cmd_payload_last = 1'b1; + always @(*) begin + io_mem_cmd_payload_wr = stageB_request_wr; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(!when_DataCache_l989) begin + io_mem_cmd_payload_wr = 1'b0; + end + end + end + end + end + + assign io_mem_cmd_payload_mask = stageB_mask; + assign io_mem_cmd_payload_data = stageB_requestDataBypass; + assign io_mem_cmd_payload_uncached = stageB_mmuRsp_isIoAccess; + always @(*) begin + io_mem_cmd_payload_size = {1'd0, stageB_request_size}; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(!when_DataCache_l989) begin + io_mem_cmd_payload_size = 3'b101; + end + end + end + end + end + + assign stageB_bypassCache = ((stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc) || stageB_isExternalAmo); + assign io_cpu_writeBack_keepMemRspData = 1'b0; + assign when_DataCache_l980 = ((! stageB_request_wr) ? (io_mem_rsp_valid && rspSync) : io_mem_cmd_ready); + assign when_DataCache_l984 = (stageB_request_isLrsc && (! stageB_lrSc_reserved)); + assign when_DataCache_l989 = (stageB_waysHit || (stageB_request_wr && (! stageB_request_isAmo))); + assign when_DataCache_l994 = ((! stageB_request_wr) || io_mem_cmd_ready); + assign when_DataCache_l997 = (! stageB_amo_internal_resultRegValid); + assign when_DataCache_l1005 = (((! stageB_request_wr) || stageB_request_isAmo) && ((stageB_dataColisions & stageB_waysHits) != 1'b0)); + assign when_DataCache_l1010 = (stageB_request_isLrsc && (! stageB_lrSc_reserved)); + assign when_DataCache_l1017 = (! memCmdSent); + assign when_DataCache_l976 = (stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc); + always @(*) begin + if(stageB_bypassCache) begin + io_cpu_writeBack_data = stageB_ioMemRspMuxed; + end else begin + io_cpu_writeBack_data = stageB_dataMux; + end + end + + assign io_cpu_writeBack_exclusiveOk = stageB_lrSc_reserved; + assign when_DataCache_l1051 = ((((stageB_consistancyHazard || stageB_mmuRsp_refilling) || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess); + assign when_DataCache_l1060 = (io_cpu_writeBack_isValid && (stageB_mmuRsp_refilling || stageB_consistancyHazard)); + always @(*) begin + loader_counter_willIncrement = 1'b0; + if(when_DataCache_l1075) begin + loader_counter_willIncrement = 1'b1; + end + end + + assign loader_counter_willClear = 1'b0; + assign loader_counter_willOverflowIfInc = (loader_counter_value == 3'b111); + assign loader_counter_willOverflow = (loader_counter_willOverflowIfInc && loader_counter_willIncrement); + always @(*) begin + loader_counter_valueNext = (loader_counter_value + _zz_loader_counter_valueNext); + if(loader_counter_willClear) begin + loader_counter_valueNext = 3'b000; + end + end + + assign loader_kill = 1'b0; + assign when_DataCache_l1075 = ((loader_valid && io_mem_rsp_valid) && rspLast); + assign loader_done = loader_counter_willOverflow; + assign when_DataCache_l1103 = (! loader_valid); + assign when_DataCache_l1107 = (loader_valid && (! loader_valid_regNext)); + assign io_cpu_execute_refilling = loader_valid; + assign when_DataCache_l1110 = (stageB_loaderValid || loader_valid); + always @(posedge clk) begin + tagsWriteLastCmd_valid <= tagsWriteCmd_valid; + tagsWriteLastCmd_payload_way <= tagsWriteCmd_payload_way; + tagsWriteLastCmd_payload_address <= tagsWriteCmd_payload_address; + tagsWriteLastCmd_payload_data_valid <= tagsWriteCmd_payload_data_valid; + tagsWriteLastCmd_payload_data_error <= tagsWriteCmd_payload_data_error; + tagsWriteLastCmd_payload_data_address <= tagsWriteCmd_payload_data_address; + if(when_DataCache_l763) begin + stageA_request_wr <= io_cpu_execute_args_wr; + stageA_request_size <= io_cpu_execute_args_size; + stageA_request_isLrsc <= io_cpu_execute_args_isLrsc; + stageA_request_isAmo <= io_cpu_execute_args_isAmo; + stageA_request_amoCtrl_swap <= io_cpu_execute_args_amoCtrl_swap; + stageA_request_amoCtrl_alu <= io_cpu_execute_args_amoCtrl_alu; + stageA_request_totalyConsistent <= io_cpu_execute_args_totalyConsistent; + end + if(when_DataCache_l763_1) begin + stageA_mask <= stage0_mask; + end + if(when_DataCache_l763_2) begin + stageA_wayInvalidate <= stage0_wayInvalidate; + end + if(when_DataCache_l763_3) begin + stage0_dataColisions_regNextWhen <= stage0_dataColisions; + end + if(when_DataCache_l814) begin + stageB_request_wr <= stageA_request_wr; + stageB_request_size <= stageA_request_size; + stageB_request_isLrsc <= stageA_request_isLrsc; + stageB_request_isAmo <= stageA_request_isAmo; + stageB_request_amoCtrl_swap <= stageA_request_amoCtrl_swap; + stageB_request_amoCtrl_alu <= stageA_request_amoCtrl_alu; + stageB_request_totalyConsistent <= stageA_request_totalyConsistent; + end + if(when_DataCache_l816) begin + stageB_mmuRsp_physicalAddress <= io_cpu_memory_mmuRsp_physicalAddress; + stageB_mmuRsp_isIoAccess <= io_cpu_memory_mmuRsp_isIoAccess; + stageB_mmuRsp_isPaging <= io_cpu_memory_mmuRsp_isPaging; + stageB_mmuRsp_allowRead <= io_cpu_memory_mmuRsp_allowRead; + stageB_mmuRsp_allowWrite <= io_cpu_memory_mmuRsp_allowWrite; + stageB_mmuRsp_allowExecute <= io_cpu_memory_mmuRsp_allowExecute; + stageB_mmuRsp_exception <= io_cpu_memory_mmuRsp_exception; + stageB_mmuRsp_refilling <= io_cpu_memory_mmuRsp_refilling; + stageB_mmuRsp_bypassTranslation <= io_cpu_memory_mmuRsp_bypassTranslation; + stageB_mmuRsp_ways_0_sel <= io_cpu_memory_mmuRsp_ways_0_sel; + stageB_mmuRsp_ways_0_physical <= io_cpu_memory_mmuRsp_ways_0_physical; + stageB_mmuRsp_ways_1_sel <= io_cpu_memory_mmuRsp_ways_1_sel; + stageB_mmuRsp_ways_1_physical <= io_cpu_memory_mmuRsp_ways_1_physical; + stageB_mmuRsp_ways_2_sel <= io_cpu_memory_mmuRsp_ways_2_sel; + stageB_mmuRsp_ways_2_physical <= io_cpu_memory_mmuRsp_ways_2_physical; + stageB_mmuRsp_ways_3_sel <= io_cpu_memory_mmuRsp_ways_3_sel; + stageB_mmuRsp_ways_3_physical <= io_cpu_memory_mmuRsp_ways_3_physical; + end + if(when_DataCache_l813) begin + stageB_tagsReadRsp_0_valid <= ways_0_tagsReadRsp_valid; + stageB_tagsReadRsp_0_error <= ways_0_tagsReadRsp_error; + stageB_tagsReadRsp_0_address <= ways_0_tagsReadRsp_address; + end + if(when_DataCache_l813_1) begin + stageB_dataReadRsp_0 <= ways_0_dataReadRsp; + end + if(when_DataCache_l812) begin + stageB_wayInvalidate <= stageA_wayInvalidate; + end + if(when_DataCache_l812_1) begin + stageB_dataColisions <= stageA_dataColisions; + end + if(when_DataCache_l812_2) begin + stageB_unaligned <= ({((stageA_request_size == 2'b10) && (io_cpu_memory_address[1 : 0] != 2'b00)),((stageA_request_size == 2'b01) && (io_cpu_memory_address[0 : 0] != 1'b0))} != 2'b00); + end + if(when_DataCache_l812_3) begin + stageB_waysHitsBeforeInvalidate <= stageA_wayHits; + end + if(when_DataCache_l812_4) begin + stageB_mask <= stageA_mask; + end + stageB_amo_internal_resultRegValid <= io_cpu_writeBack_isStuck; + stageB_amo_resultReg <= stageB_amo_result; + loader_valid_regNext <= loader_valid; + end + + always @(posedge clk or posedge reset) begin + if(reset) begin + memCmdSent <= 1'b0; + stageB_flusher_waitDone <= 1'b0; + stageB_flusher_counter <= 8'h0; + stageB_flusher_start <= 1'b1; + stageB_lrSc_reserved <= 1'b0; + loader_valid <= 1'b0; + loader_counter_value <= 3'b000; + loader_waysAllocator <= 1'b1; + loader_error <= 1'b0; + loader_killReg <= 1'b0; + end else begin + if(when_DataCache_l678) begin + memCmdSent <= 1'b1; + end + if(when_DataCache_l678_1) begin + memCmdSent <= 1'b0; + end + if(io_cpu_flush_ready) begin + stageB_flusher_waitDone <= 1'b0; + end + if(when_DataCache_l842) begin + if(when_DataCache_l848) begin + stageB_flusher_counter <= (stageB_flusher_counter + 8'h01); + end + end + stageB_flusher_start <= (((((((! stageB_flusher_waitDone) && (! stageB_flusher_start)) && io_cpu_flush_valid) && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo)); + if(stageB_flusher_start) begin + stageB_flusher_waitDone <= 1'b1; + stageB_flusher_counter <= 8'h0; + end + if(when_DataCache_l866) begin + stageB_lrSc_reserved <= (! stageB_request_wr); + end + if(when_DataCache_l1051) begin + stageB_lrSc_reserved <= stageB_lrSc_reserved; + end + `ifndef SYNTHESIS + `ifdef FORMAL + assert((! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))); + `else + if(!(! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))) begin + $display("ERROR writeBack stuck by another plugin is not allowed"); + end + `endif + `endif + if(stageB_loaderValid) begin + loader_valid <= 1'b1; + end + loader_counter_value <= loader_counter_valueNext; + if(loader_kill) begin + loader_killReg <= 1'b1; + end + if(when_DataCache_l1075) begin + loader_error <= (loader_error || io_mem_rsp_payload_error); + end + if(loader_done) begin + loader_valid <= 1'b0; + loader_error <= 1'b0; + loader_killReg <= 1'b0; + end + if(when_DataCache_l1103) begin + loader_waysAllocator <= _zz_loader_waysAllocator[0:0]; + end + end + end + + +endmodule + +module InstructionCache ( + input io_flush, + input io_cpu_prefetch_isValid, + output reg io_cpu_prefetch_haltIt, + input [31:0] io_cpu_prefetch_pc, + input io_cpu_fetch_isValid, + input io_cpu_fetch_isStuck, + input io_cpu_fetch_isRemoved, + input [31:0] io_cpu_fetch_pc, + output [31:0] io_cpu_fetch_data, + input [31:0] io_cpu_fetch_mmuRsp_physicalAddress, + input io_cpu_fetch_mmuRsp_isIoAccess, + input io_cpu_fetch_mmuRsp_isPaging, + input io_cpu_fetch_mmuRsp_allowRead, + input io_cpu_fetch_mmuRsp_allowWrite, + input io_cpu_fetch_mmuRsp_allowExecute, + input io_cpu_fetch_mmuRsp_exception, + input io_cpu_fetch_mmuRsp_refilling, + input io_cpu_fetch_mmuRsp_bypassTranslation, + input io_cpu_fetch_mmuRsp_ways_0_sel, + input [31:0] io_cpu_fetch_mmuRsp_ways_0_physical, + input io_cpu_fetch_mmuRsp_ways_1_sel, + input [31:0] io_cpu_fetch_mmuRsp_ways_1_physical, + input io_cpu_fetch_mmuRsp_ways_2_sel, + input [31:0] io_cpu_fetch_mmuRsp_ways_2_physical, + input io_cpu_fetch_mmuRsp_ways_3_sel, + input [31:0] io_cpu_fetch_mmuRsp_ways_3_physical, + output [31:0] io_cpu_fetch_physicalAddress, + input io_cpu_decode_isValid, + input io_cpu_decode_isStuck, + input [31:0] io_cpu_decode_pc, + output [31:0] io_cpu_decode_physicalAddress, + output [31:0] io_cpu_decode_data, + output io_cpu_decode_cacheMiss, + output io_cpu_decode_error, + output io_cpu_decode_mmuRefilling, + output io_cpu_decode_mmuException, + input io_cpu_decode_isUser, + input io_cpu_fill_valid, + input [31:0] io_cpu_fill_payload, + output io_mem_cmd_valid, + input io_mem_cmd_ready, + output [31:0] io_mem_cmd_payload_address, + output [2:0] io_mem_cmd_payload_size, + input io_mem_rsp_valid, + input [31:0] io_mem_rsp_payload_data, + input io_mem_rsp_payload_error, + input [2:0] _zz_when_Fetcher_l398, + input [31:0] _zz_io_cpu_fetch_data_regNextWhen, + input clk, + input reset +); + reg [31:0] _zz_banks_0_port1; + reg [21:0] _zz_ways_0_tags_port1; + wire [21:0] _zz_ways_0_tags_port; + reg _zz_1; + reg _zz_2; + reg lineLoader_fire; + reg lineLoader_valid; + (* keep , syn_keep *) reg [31:0] lineLoader_address /* synthesis syn_keep = 1 */ ; + reg lineLoader_hadError; + reg lineLoader_flushPending; + reg [7:0] lineLoader_flushCounter; + wire when_InstructionCache_l338; + reg _zz_when_InstructionCache_l342; + wire when_InstructionCache_l342; + wire when_InstructionCache_l351; + reg lineLoader_cmdSent; + wire when_InstructionCache_l358; + wire when_Utils_l357; + reg lineLoader_wayToAllocate_willIncrement; + wire lineLoader_wayToAllocate_willClear; + wire lineLoader_wayToAllocate_willOverflowIfInc; + wire lineLoader_wayToAllocate_willOverflow; + (* keep , syn_keep *) reg [2:0] lineLoader_wordIndex /* synthesis syn_keep = 1 */ ; + wire lineLoader_write_tag_0_valid; + wire [6:0] lineLoader_write_tag_0_payload_address; + wire lineLoader_write_tag_0_payload_data_valid; + wire lineLoader_write_tag_0_payload_data_error; + wire [19:0] lineLoader_write_tag_0_payload_data_address; + wire lineLoader_write_data_0_valid; + wire [9:0] lineLoader_write_data_0_payload_address; + wire [31:0] lineLoader_write_data_0_payload_data; + wire when_InstructionCache_l401; + wire [9:0] _zz_fetchStage_read_banksValue_0_dataMem; + wire _zz_fetchStage_read_banksValue_0_dataMem_1; + wire [31:0] fetchStage_read_banksValue_0_dataMem; + wire [31:0] fetchStage_read_banksValue_0_data; + wire [6:0] _zz_fetchStage_read_waysValues_0_tag_valid; + wire _zz_fetchStage_read_waysValues_0_tag_valid_1; + wire fetchStage_read_waysValues_0_tag_valid; + wire fetchStage_read_waysValues_0_tag_error; + wire [19:0] fetchStage_read_waysValues_0_tag_address; + wire [21:0] _zz_fetchStage_read_waysValues_0_tag_valid_2; + wire fetchStage_hit_hits_0; + wire fetchStage_hit_valid; + wire fetchStage_hit_error; + wire [31:0] fetchStage_hit_data; + wire [31:0] fetchStage_hit_word; + wire when_InstructionCache_l435; + reg [31:0] io_cpu_fetch_data_regNextWhen; + wire when_InstructionCache_l459; + reg [31:0] decodeStage_mmuRsp_physicalAddress; + reg decodeStage_mmuRsp_isIoAccess; + reg decodeStage_mmuRsp_isPaging; + reg decodeStage_mmuRsp_allowRead; + reg decodeStage_mmuRsp_allowWrite; + reg decodeStage_mmuRsp_allowExecute; + reg decodeStage_mmuRsp_exception; + reg decodeStage_mmuRsp_refilling; + reg decodeStage_mmuRsp_bypassTranslation; + reg decodeStage_mmuRsp_ways_0_sel; + reg [31:0] decodeStage_mmuRsp_ways_0_physical; + reg decodeStage_mmuRsp_ways_1_sel; + reg [31:0] decodeStage_mmuRsp_ways_1_physical; + reg decodeStage_mmuRsp_ways_2_sel; + reg [31:0] decodeStage_mmuRsp_ways_2_physical; + reg decodeStage_mmuRsp_ways_3_sel; + reg [31:0] decodeStage_mmuRsp_ways_3_physical; + wire when_InstructionCache_l459_1; + reg decodeStage_hit_valid; + wire when_InstructionCache_l459_2; + reg decodeStage_hit_error; + wire when_Fetcher_l398; + reg [31:0] banks_0 [0:1023]; + reg [21:0] ways_0_tags [0:127]; + + assign _zz_ways_0_tags_port = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; + always @(posedge clk) begin + if(_zz_1) begin + banks_0[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data; + end + end + + always @(posedge clk) begin + if(_zz_fetchStage_read_banksValue_0_dataMem_1) begin + _zz_banks_0_port1 <= banks_0[_zz_fetchStage_read_banksValue_0_dataMem]; + end + end + + always @(posedge clk) begin + if(_zz_2) begin + ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_ways_0_tags_port; + end + end + + always @(posedge clk) begin + if(_zz_fetchStage_read_waysValues_0_tag_valid_1) begin + _zz_ways_0_tags_port1 <= ways_0_tags[_zz_fetchStage_read_waysValues_0_tag_valid]; + end + end + + always @(*) begin + _zz_1 = 1'b0; + if(lineLoader_write_data_0_valid) begin + _zz_1 = 1'b1; + end + end + + always @(*) begin + _zz_2 = 1'b0; + if(lineLoader_write_tag_0_valid) begin + _zz_2 = 1'b1; + end + end + + always @(*) begin + lineLoader_fire = 1'b0; + if(io_mem_rsp_valid) begin + if(when_InstructionCache_l401) begin + lineLoader_fire = 1'b1; + end + end + end + + always @(*) begin + io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending); + if(when_InstructionCache_l338) begin + io_cpu_prefetch_haltIt = 1'b1; + end + if(when_InstructionCache_l342) begin + io_cpu_prefetch_haltIt = 1'b1; + end + if(io_flush) begin + io_cpu_prefetch_haltIt = 1'b1; + end + end + + assign when_InstructionCache_l338 = (! lineLoader_flushCounter[7]); + assign when_InstructionCache_l342 = (! _zz_when_InstructionCache_l342); + assign when_InstructionCache_l351 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); + assign when_InstructionCache_l358 = (io_mem_cmd_valid && io_mem_cmd_ready); + assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent)); + assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],5'h0}; + assign io_mem_cmd_payload_size = 3'b101; + assign when_Utils_l357 = (! lineLoader_valid); + always @(*) begin + lineLoader_wayToAllocate_willIncrement = 1'b0; + if(when_Utils_l357) begin + lineLoader_wayToAllocate_willIncrement = 1'b1; + end + end + + assign lineLoader_wayToAllocate_willClear = 1'b0; + assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1; + assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement); + assign lineLoader_write_tag_0_valid = ((1'b1 && lineLoader_fire) || (! lineLoader_flushCounter[7])); + assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[7] ? lineLoader_address[11 : 5] : lineLoader_flushCounter[6 : 0]); + assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[7]; + assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error); + assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 12]; + assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && 1'b1); + assign lineLoader_write_data_0_payload_address = {lineLoader_address[11 : 5],lineLoader_wordIndex}; + assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data; + assign when_InstructionCache_l401 = (lineLoader_wordIndex == 3'b111); + assign _zz_fetchStage_read_banksValue_0_dataMem = io_cpu_prefetch_pc[11 : 2]; + assign _zz_fetchStage_read_banksValue_0_dataMem_1 = (! io_cpu_fetch_isStuck); + assign fetchStage_read_banksValue_0_dataMem = _zz_banks_0_port1; + assign fetchStage_read_banksValue_0_data = fetchStage_read_banksValue_0_dataMem[31 : 0]; + assign _zz_fetchStage_read_waysValues_0_tag_valid = io_cpu_prefetch_pc[11 : 5]; + assign _zz_fetchStage_read_waysValues_0_tag_valid_1 = (! io_cpu_fetch_isStuck); + assign _zz_fetchStage_read_waysValues_0_tag_valid_2 = _zz_ways_0_tags_port1; + assign fetchStage_read_waysValues_0_tag_valid = _zz_fetchStage_read_waysValues_0_tag_valid_2[0]; + assign fetchStage_read_waysValues_0_tag_error = _zz_fetchStage_read_waysValues_0_tag_valid_2[1]; + assign fetchStage_read_waysValues_0_tag_address = _zz_fetchStage_read_waysValues_0_tag_valid_2[21 : 2]; + assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuRsp_physicalAddress[31 : 12])); + assign fetchStage_hit_valid = (fetchStage_hit_hits_0 != 1'b0); + assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error; + assign fetchStage_hit_data = fetchStage_read_banksValue_0_data; + assign fetchStage_hit_word = fetchStage_hit_data; + assign io_cpu_fetch_data = fetchStage_hit_word; + assign when_InstructionCache_l435 = (! io_cpu_decode_isStuck); + assign io_cpu_decode_data = io_cpu_fetch_data_regNextWhen; + assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuRsp_physicalAddress; + assign when_InstructionCache_l459 = (! io_cpu_decode_isStuck); + assign when_InstructionCache_l459_1 = (! io_cpu_decode_isStuck); + assign when_InstructionCache_l459_2 = (! io_cpu_decode_isStuck); + assign io_cpu_decode_cacheMiss = (! decodeStage_hit_valid); + assign io_cpu_decode_error = (decodeStage_hit_error || ((! decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute)))); + assign io_cpu_decode_mmuRefilling = decodeStage_mmuRsp_refilling; + assign io_cpu_decode_mmuException = (((! decodeStage_mmuRsp_refilling) && decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute))); + assign io_cpu_decode_physicalAddress = decodeStage_mmuRsp_physicalAddress; + assign when_Fetcher_l398 = (_zz_when_Fetcher_l398 != 3'b000); + always @(posedge clk or posedge reset) begin + if(reset) begin + lineLoader_valid <= 1'b0; + lineLoader_hadError <= 1'b0; + lineLoader_flushPending <= 1'b1; + lineLoader_cmdSent <= 1'b0; + lineLoader_wordIndex <= 3'b000; + end else begin + if(lineLoader_fire) begin + lineLoader_valid <= 1'b0; + end + if(lineLoader_fire) begin + lineLoader_hadError <= 1'b0; + end + if(io_cpu_fill_valid) begin + lineLoader_valid <= 1'b1; + end + if(io_flush) begin + lineLoader_flushPending <= 1'b1; + end + if(when_InstructionCache_l351) begin + lineLoader_flushPending <= 1'b0; + end + if(when_InstructionCache_l358) begin + lineLoader_cmdSent <= 1'b1; + end + if(lineLoader_fire) begin + lineLoader_cmdSent <= 1'b0; + end + if(io_mem_rsp_valid) begin + lineLoader_wordIndex <= (lineLoader_wordIndex + 3'b001); + if(io_mem_rsp_payload_error) begin + lineLoader_hadError <= 1'b1; + end + end + end + end + + always @(posedge clk) begin + if(io_cpu_fill_valid) begin + lineLoader_address <= io_cpu_fill_payload; + end + if(when_InstructionCache_l338) begin + lineLoader_flushCounter <= (lineLoader_flushCounter + 8'h01); + end + _zz_when_InstructionCache_l342 <= lineLoader_flushCounter[7]; + if(when_InstructionCache_l351) begin + lineLoader_flushCounter <= 8'h0; + end + if(when_InstructionCache_l435) begin + io_cpu_fetch_data_regNextWhen <= io_cpu_fetch_data; + end + if(when_InstructionCache_l459) begin + decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuRsp_physicalAddress; + decodeStage_mmuRsp_isIoAccess <= io_cpu_fetch_mmuRsp_isIoAccess; + decodeStage_mmuRsp_isPaging <= io_cpu_fetch_mmuRsp_isPaging; + decodeStage_mmuRsp_allowRead <= io_cpu_fetch_mmuRsp_allowRead; + decodeStage_mmuRsp_allowWrite <= io_cpu_fetch_mmuRsp_allowWrite; + decodeStage_mmuRsp_allowExecute <= io_cpu_fetch_mmuRsp_allowExecute; + decodeStage_mmuRsp_exception <= io_cpu_fetch_mmuRsp_exception; + decodeStage_mmuRsp_refilling <= io_cpu_fetch_mmuRsp_refilling; + decodeStage_mmuRsp_bypassTranslation <= io_cpu_fetch_mmuRsp_bypassTranslation; + decodeStage_mmuRsp_ways_0_sel <= io_cpu_fetch_mmuRsp_ways_0_sel; + decodeStage_mmuRsp_ways_0_physical <= io_cpu_fetch_mmuRsp_ways_0_physical; + decodeStage_mmuRsp_ways_1_sel <= io_cpu_fetch_mmuRsp_ways_1_sel; + decodeStage_mmuRsp_ways_1_physical <= io_cpu_fetch_mmuRsp_ways_1_physical; + decodeStage_mmuRsp_ways_2_sel <= io_cpu_fetch_mmuRsp_ways_2_sel; + decodeStage_mmuRsp_ways_2_physical <= io_cpu_fetch_mmuRsp_ways_2_physical; + decodeStage_mmuRsp_ways_3_sel <= io_cpu_fetch_mmuRsp_ways_3_sel; + decodeStage_mmuRsp_ways_3_physical <= io_cpu_fetch_mmuRsp_ways_3_physical; + end + if(when_InstructionCache_l459_1) begin + decodeStage_hit_valid <= fetchStage_hit_valid; + end + if(when_InstructionCache_l459_2) begin + decodeStage_hit_error <= fetchStage_hit_error; + end + if(when_Fetcher_l398) begin + io_cpu_fetch_data_regNextWhen <= _zz_io_cpu_fetch_data_regNextWhen; + end + end + + +endmodule diff --git a/openfpga_flow/benchmarks/processor/vexriscv/vexriscv_small.v b/openfpga_flow/benchmarks/processor/vexriscv/vexriscv_small.v new file mode 100644 index 0000000000..2b4f567851 --- /dev/null +++ b/openfpga_flow/benchmarks/processor/vexriscv/vexriscv_small.v @@ -0,0 +1,3127 @@ +// Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 +// Component : VexRiscv +// Git hash : 36b3cd918896c94c4e8a224d97c559ab6dbf3ec9 + + +`define BranchCtrlEnum_defaultEncoding_type [1:0] +`define BranchCtrlEnum_defaultEncoding_INC 2'b00 +`define BranchCtrlEnum_defaultEncoding_B 2'b01 +`define BranchCtrlEnum_defaultEncoding_JAL 2'b10 +`define BranchCtrlEnum_defaultEncoding_JALR 2'b11 + +`define ShiftCtrlEnum_defaultEncoding_type [1:0] +`define ShiftCtrlEnum_defaultEncoding_DISABLE_1 2'b00 +`define ShiftCtrlEnum_defaultEncoding_SLL_1 2'b01 +`define ShiftCtrlEnum_defaultEncoding_SRL_1 2'b10 +`define ShiftCtrlEnum_defaultEncoding_SRA_1 2'b11 + +`define AluBitwiseCtrlEnum_defaultEncoding_type [1:0] +`define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 2'b00 +`define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01 +`define AluBitwiseCtrlEnum_defaultEncoding_AND_1 2'b10 + +`define AluCtrlEnum_defaultEncoding_type [1:0] +`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00 +`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01 +`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10 + +`define EnvCtrlEnum_defaultEncoding_type [0:0] +`define EnvCtrlEnum_defaultEncoding_NONE 1'b0 +`define EnvCtrlEnum_defaultEncoding_XRET 1'b1 + +`define Src2CtrlEnum_defaultEncoding_type [1:0] +`define Src2CtrlEnum_defaultEncoding_RS 2'b00 +`define Src2CtrlEnum_defaultEncoding_IMI 2'b01 +`define Src2CtrlEnum_defaultEncoding_IMS 2'b10 +`define Src2CtrlEnum_defaultEncoding_PC 2'b11 + +`define Src1CtrlEnum_defaultEncoding_type [1:0] +`define Src1CtrlEnum_defaultEncoding_RS 2'b00 +`define Src1CtrlEnum_defaultEncoding_IMU 2'b01 +`define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10 +`define Src1CtrlEnum_defaultEncoding_URS1 2'b11 + + +module VexRiscv ( + output iBus_cmd_valid, + input iBus_cmd_ready, + output [31:0] iBus_cmd_payload_pc, + input iBus_rsp_valid, + input iBus_rsp_payload_error, + input [31:0] iBus_rsp_payload_inst, + input timerInterrupt, + input externalInterrupt, + input softwareInterrupt, + output dBus_cmd_valid, + input dBus_cmd_ready, + output dBus_cmd_payload_wr, + output [31:0] dBus_cmd_payload_address, + output [31:0] dBus_cmd_payload_data, + output [1:0] dBus_cmd_payload_size, + input dBus_rsp_ready, + input dBus_rsp_error, + input [31:0] dBus_rsp_data, + input clk, + input reset +); + wire _zz_107; + wire _zz_108; + reg [31:0] _zz_109; + reg [31:0] _zz_110; + wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_push_ready; + wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid; + wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error; + wire [31:0] IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst; + wire [0:0] IBusSimplePlugin_rspJoin_rspBuffer_c_io_occupancy; + wire _zz_111; + wire _zz_112; + wire _zz_113; + wire _zz_114; + wire [1:0] _zz_115; + wire _zz_116; + wire _zz_117; + wire _zz_118; + wire _zz_119; + wire _zz_120; + wire _zz_121; + wire _zz_122; + wire _zz_123; + wire _zz_124; + wire _zz_125; + wire _zz_126; + wire _zz_127; + wire [1:0] _zz_128; + wire _zz_129; + wire [0:0] _zz_130; + wire [0:0] _zz_131; + wire [0:0] _zz_132; + wire [0:0] _zz_133; + wire [0:0] _zz_134; + wire [0:0] _zz_135; + wire [0:0] _zz_136; + wire [0:0] _zz_137; + wire [0:0] _zz_138; + wire [0:0] _zz_139; + wire [0:0] _zz_140; + wire [1:0] _zz_141; + wire [1:0] _zz_142; + wire [2:0] _zz_143; + wire [31:0] _zz_144; + wire [2:0] _zz_145; + wire [0:0] _zz_146; + wire [2:0] _zz_147; + wire [0:0] _zz_148; + wire [2:0] _zz_149; + wire [0:0] _zz_150; + wire [2:0] _zz_151; + wire [0:0] _zz_152; + wire [2:0] _zz_153; + wire [0:0] _zz_154; + wire [2:0] _zz_155; + wire [4:0] _zz_156; + wire [11:0] _zz_157; + wire [11:0] _zz_158; + wire [31:0] _zz_159; + wire [31:0] _zz_160; + wire [31:0] _zz_161; + wire [31:0] _zz_162; + wire [31:0] _zz_163; + wire [31:0] _zz_164; + wire [31:0] _zz_165; + wire [31:0] _zz_166; + wire [32:0] _zz_167; + wire [19:0] _zz_168; + wire [11:0] _zz_169; + wire [11:0] _zz_170; + wire [0:0] _zz_171; + wire [0:0] _zz_172; + wire [0:0] _zz_173; + wire [0:0] _zz_174; + wire [0:0] _zz_175; + wire [0:0] _zz_176; + wire _zz_177; + wire _zz_178; + wire [31:0] _zz_179; + wire [31:0] _zz_180; + wire [31:0] _zz_181; + wire [31:0] _zz_182; + wire _zz_183; + wire [1:0] _zz_184; + wire [1:0] _zz_185; + wire _zz_186; + wire [0:0] _zz_187; + wire [18:0] _zz_188; + wire [31:0] _zz_189; + wire [31:0] _zz_190; + wire [31:0] _zz_191; + wire [31:0] _zz_192; + wire _zz_193; + wire _zz_194; + wire _zz_195; + wire [0:0] _zz_196; + wire [0:0] _zz_197; + wire _zz_198; + wire [0:0] _zz_199; + wire [15:0] _zz_200; + wire [31:0] _zz_201; + wire _zz_202; + wire _zz_203; + wire [0:0] _zz_204; + wire [0:0] _zz_205; + wire [0:0] _zz_206; + wire [0:0] _zz_207; + wire _zz_208; + wire [0:0] _zz_209; + wire [12:0] _zz_210; + wire [31:0] _zz_211; + wire [31:0] _zz_212; + wire _zz_213; + wire _zz_214; + wire _zz_215; + wire [1:0] _zz_216; + wire [1:0] _zz_217; + wire _zz_218; + wire [0:0] _zz_219; + wire [9:0] _zz_220; + wire [31:0] _zz_221; + wire [31:0] _zz_222; + wire [31:0] _zz_223; + wire [31:0] _zz_224; + wire _zz_225; + wire _zz_226; + wire _zz_227; + wire [0:0] _zz_228; + wire [0:0] _zz_229; + wire _zz_230; + wire [0:0] _zz_231; + wire [6:0] _zz_232; + wire [31:0] _zz_233; + wire [0:0] _zz_234; + wire [4:0] _zz_235; + wire [1:0] _zz_236; + wire [1:0] _zz_237; + wire _zz_238; + wire [0:0] _zz_239; + wire [3:0] _zz_240; + wire [31:0] _zz_241; + wire [31:0] _zz_242; + wire _zz_243; + wire [0:0] _zz_244; + wire [1:0] _zz_245; + wire [31:0] _zz_246; + wire [31:0] _zz_247; + wire _zz_248; + wire [0:0] _zz_249; + wire [2:0] _zz_250; + wire [0:0] _zz_251; + wire [0:0] _zz_252; + wire _zz_253; + wire [0:0] _zz_254; + wire [0:0] _zz_255; + wire [31:0] _zz_256; + wire _zz_257; + wire _zz_258; + wire [31:0] _zz_259; + wire [31:0] _zz_260; + wire [31:0] _zz_261; + wire _zz_262; + wire [0:0] _zz_263; + wire [0:0] _zz_264; + wire [31:0] _zz_265; + wire [31:0] _zz_266; + wire [0:0] _zz_267; + wire [1:0] _zz_268; + wire [1:0] _zz_269; + wire [1:0] _zz_270; + wire [1:0] _zz_271; + wire [1:0] _zz_272; + wire [31:0] _zz_273; + wire [31:0] _zz_274; + wire [31:0] _zz_275; + wire [31:0] _zz_276; + wire [31:0] _zz_277; + wire [31:0] _zz_278; + wire [31:0] _zz_279; + wire [31:0] _zz_280; + wire [31:0] _zz_281; + wire [31:0] _zz_282; + wire [31:0] memory_MEMORY_READ_DATA; + wire [31:0] execute_BRANCH_CALC; + wire execute_BRANCH_DO; + wire [31:0] writeBack_REGFILE_WRITE_DATA; + wire [31:0] execute_REGFILE_WRITE_DATA; + wire [1:0] memory_MEMORY_ADDRESS_LOW; + wire [1:0] execute_MEMORY_ADDRESS_LOW; + wire [31:0] decode_SRC2; + wire [31:0] decode_SRC1; + wire decode_SRC2_FORCE_ZERO; + wire [31:0] decode_RS2; + wire [31:0] decode_RS1; + wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_1; + wire `BranchCtrlEnum_defaultEncoding_type _zz_2; + wire `BranchCtrlEnum_defaultEncoding_type _zz_3; + wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_4; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_5; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_6; + wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_7; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_8; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_9; + wire decode_SRC_LESS_UNSIGNED; + wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_10; + wire `AluCtrlEnum_defaultEncoding_type _zz_11; + wire `AluCtrlEnum_defaultEncoding_type _zz_12; + wire `EnvCtrlEnum_defaultEncoding_type _zz_13; + wire `EnvCtrlEnum_defaultEncoding_type _zz_14; + wire `EnvCtrlEnum_defaultEncoding_type _zz_15; + wire `EnvCtrlEnum_defaultEncoding_type _zz_16; + wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_17; + wire `EnvCtrlEnum_defaultEncoding_type _zz_18; + wire `EnvCtrlEnum_defaultEncoding_type _zz_19; + wire decode_IS_CSR; + wire decode_MEMORY_STORE; + wire execute_BYPASSABLE_MEMORY_STAGE; + wire decode_BYPASSABLE_MEMORY_STAGE; + wire decode_BYPASSABLE_EXECUTE_STAGE; + wire decode_MEMORY_ENABLE; + wire decode_CSR_READ_OPCODE; + wire decode_CSR_WRITE_OPCODE; + wire [31:0] writeBack_FORMAL_PC_NEXT; + wire [31:0] memory_FORMAL_PC_NEXT; + wire [31:0] execute_FORMAL_PC_NEXT; + wire [31:0] decode_FORMAL_PC_NEXT; + wire [31:0] memory_PC; + wire [31:0] memory_BRANCH_CALC; + wire memory_BRANCH_DO; + wire [31:0] execute_PC; + wire [31:0] execute_RS1; + wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_20; + wire decode_RS2_USE; + wire decode_RS1_USE; + wire execute_REGFILE_WRITE_VALID; + wire execute_BYPASSABLE_EXECUTE_STAGE; + wire memory_REGFILE_WRITE_VALID; + wire [31:0] memory_INSTRUCTION; + wire memory_BYPASSABLE_MEMORY_STAGE; + wire writeBack_REGFILE_WRITE_VALID; + wire [31:0] memory_REGFILE_WRITE_DATA; + wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_21; + wire execute_SRC_LESS_UNSIGNED; + wire execute_SRC2_FORCE_ZERO; + wire execute_SRC_USE_SUB_LESS; + wire [31:0] _zz_22; + wire [31:0] _zz_23; + wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; + wire `Src2CtrlEnum_defaultEncoding_type _zz_24; + wire [31:0] _zz_25; + wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; + wire `Src1CtrlEnum_defaultEncoding_type _zz_26; + wire decode_SRC_USE_SUB_LESS; + wire decode_SRC_ADD_ZERO; + wire [31:0] execute_SRC_ADD_SUB; + wire execute_SRC_LESS; + wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_27; + wire [31:0] execute_SRC2; + wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_28; + wire [31:0] _zz_29; + wire _zz_30; + reg _zz_31; + wire [31:0] decode_INSTRUCTION_ANTICIPATED; + reg decode_REGFILE_WRITE_VALID; + wire `BranchCtrlEnum_defaultEncoding_type _zz_32; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_33; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_34; + wire `AluCtrlEnum_defaultEncoding_type _zz_35; + wire `EnvCtrlEnum_defaultEncoding_type _zz_36; + wire `Src2CtrlEnum_defaultEncoding_type _zz_37; + wire `Src1CtrlEnum_defaultEncoding_type _zz_38; + reg [31:0] _zz_39; + wire [31:0] execute_SRC1; + wire execute_CSR_READ_OPCODE; + wire execute_CSR_WRITE_OPCODE; + wire execute_IS_CSR; + wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_40; + wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_41; + wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_42; + wire writeBack_MEMORY_STORE; + reg [31:0] _zz_43; + wire writeBack_MEMORY_ENABLE; + wire [1:0] writeBack_MEMORY_ADDRESS_LOW; + wire [31:0] writeBack_MEMORY_READ_DATA; + wire memory_MEMORY_STORE; + wire memory_MEMORY_ENABLE; + wire [31:0] execute_SRC_ADD; + wire [31:0] execute_RS2; + wire [31:0] execute_INSTRUCTION; + wire execute_MEMORY_STORE; + wire execute_MEMORY_ENABLE; + wire execute_ALIGNEMENT_FAULT; + reg [31:0] _zz_44; + wire [31:0] decode_PC; + wire [31:0] decode_INSTRUCTION; + wire [31:0] writeBack_PC; + wire [31:0] writeBack_INSTRUCTION; + wire decode_arbitration_haltItself; + reg decode_arbitration_haltByOther; + reg decode_arbitration_removeIt; + wire decode_arbitration_flushIt; + wire decode_arbitration_flushNext; + wire decode_arbitration_isValid; + wire decode_arbitration_isStuck; + wire decode_arbitration_isStuckByOthers; + wire decode_arbitration_isFlushed; + wire decode_arbitration_isMoving; + wire decode_arbitration_isFiring; + reg execute_arbitration_haltItself; + wire execute_arbitration_haltByOther; + reg execute_arbitration_removeIt; + wire execute_arbitration_flushIt; + wire execute_arbitration_flushNext; + reg execute_arbitration_isValid; + wire execute_arbitration_isStuck; + wire execute_arbitration_isStuckByOthers; + wire execute_arbitration_isFlushed; + wire execute_arbitration_isMoving; + wire execute_arbitration_isFiring; + reg memory_arbitration_haltItself; + wire memory_arbitration_haltByOther; + reg memory_arbitration_removeIt; + wire memory_arbitration_flushIt; + reg memory_arbitration_flushNext; + reg memory_arbitration_isValid; + wire memory_arbitration_isStuck; + wire memory_arbitration_isStuckByOthers; + wire memory_arbitration_isFlushed; + wire memory_arbitration_isMoving; + wire memory_arbitration_isFiring; + wire writeBack_arbitration_haltItself; + wire writeBack_arbitration_haltByOther; + reg writeBack_arbitration_removeIt; + wire writeBack_arbitration_flushIt; + reg writeBack_arbitration_flushNext; + reg writeBack_arbitration_isValid; + wire writeBack_arbitration_isStuck; + wire writeBack_arbitration_isStuckByOthers; + wire writeBack_arbitration_isFlushed; + wire writeBack_arbitration_isMoving; + wire writeBack_arbitration_isFiring; + wire [31:0] lastStageInstruction /* verilator public */ ; + wire [31:0] lastStagePc /* verilator public */ ; + wire lastStageIsValid /* verilator public */ ; + wire lastStageIsFiring /* verilator public */ ; + reg IBusSimplePlugin_fetcherHalt; + reg IBusSimplePlugin_incomingInstruction; + wire IBusSimplePlugin_pcValids_0; + wire IBusSimplePlugin_pcValids_1; + wire IBusSimplePlugin_pcValids_2; + wire IBusSimplePlugin_pcValids_3; + wire CsrPlugin_inWfi /* verilator public */ ; + wire CsrPlugin_thirdPartyWake; + reg CsrPlugin_jumpInterface_valid; + reg [31:0] CsrPlugin_jumpInterface_payload; + wire CsrPlugin_exceptionPendings_0; + wire CsrPlugin_exceptionPendings_1; + wire CsrPlugin_exceptionPendings_2; + wire CsrPlugin_exceptionPendings_3; + wire contextSwitching; + reg [1:0] CsrPlugin_privilege; + wire CsrPlugin_forceMachineWire; + wire CsrPlugin_allowInterrupts; + wire CsrPlugin_allowException; + wire BranchPlugin_jumpInterface_valid; + wire [31:0] BranchPlugin_jumpInterface_payload; + wire IBusSimplePlugin_externalFlush; + wire IBusSimplePlugin_jump_pcLoad_valid; + wire [31:0] IBusSimplePlugin_jump_pcLoad_payload; + wire [1:0] _zz_45; + wire IBusSimplePlugin_fetchPc_output_valid; + wire IBusSimplePlugin_fetchPc_output_ready; + wire [31:0] IBusSimplePlugin_fetchPc_output_payload; + reg [31:0] IBusSimplePlugin_fetchPc_pcReg /* verilator public */ ; + reg IBusSimplePlugin_fetchPc_correction; + reg IBusSimplePlugin_fetchPc_correctionReg; + wire IBusSimplePlugin_fetchPc_corrected; + reg IBusSimplePlugin_fetchPc_pcRegPropagate; + reg IBusSimplePlugin_fetchPc_booted; + reg IBusSimplePlugin_fetchPc_inc; + reg [31:0] IBusSimplePlugin_fetchPc_pc; + reg IBusSimplePlugin_fetchPc_flushed; + wire IBusSimplePlugin_iBusRsp_redoFetch; + wire IBusSimplePlugin_iBusRsp_stages_0_input_valid; + wire IBusSimplePlugin_iBusRsp_stages_0_input_ready; + wire [31:0] IBusSimplePlugin_iBusRsp_stages_0_input_payload; + wire IBusSimplePlugin_iBusRsp_stages_0_output_valid; + wire IBusSimplePlugin_iBusRsp_stages_0_output_ready; + wire [31:0] IBusSimplePlugin_iBusRsp_stages_0_output_payload; + reg IBusSimplePlugin_iBusRsp_stages_0_halt; + wire IBusSimplePlugin_iBusRsp_stages_1_input_valid; + wire IBusSimplePlugin_iBusRsp_stages_1_input_ready; + wire [31:0] IBusSimplePlugin_iBusRsp_stages_1_input_payload; + wire IBusSimplePlugin_iBusRsp_stages_1_output_valid; + wire IBusSimplePlugin_iBusRsp_stages_1_output_ready; + wire [31:0] IBusSimplePlugin_iBusRsp_stages_1_output_payload; + wire IBusSimplePlugin_iBusRsp_stages_1_halt; + wire _zz_46; + wire _zz_47; + wire IBusSimplePlugin_iBusRsp_flush; + wire _zz_48; + wire _zz_49; + reg _zz_50; + reg IBusSimplePlugin_iBusRsp_readyForError; + wire IBusSimplePlugin_iBusRsp_output_valid; + wire IBusSimplePlugin_iBusRsp_output_ready; + wire [31:0] IBusSimplePlugin_iBusRsp_output_payload_pc; + wire IBusSimplePlugin_iBusRsp_output_payload_rsp_error; + wire [31:0] IBusSimplePlugin_iBusRsp_output_payload_rsp_inst; + wire IBusSimplePlugin_iBusRsp_output_payload_isRvc; + wire IBusSimplePlugin_injector_decodeInput_valid; + wire IBusSimplePlugin_injector_decodeInput_ready; + wire [31:0] IBusSimplePlugin_injector_decodeInput_payload_pc; + wire IBusSimplePlugin_injector_decodeInput_payload_rsp_error; + wire [31:0] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst; + wire IBusSimplePlugin_injector_decodeInput_payload_isRvc; + reg _zz_51; + reg [31:0] _zz_52; + reg _zz_53; + reg [31:0] _zz_54; + reg _zz_55; + reg IBusSimplePlugin_injector_nextPcCalc_valids_0; + reg IBusSimplePlugin_injector_nextPcCalc_valids_1; + reg IBusSimplePlugin_injector_nextPcCalc_valids_2; + reg IBusSimplePlugin_injector_nextPcCalc_valids_3; + reg IBusSimplePlugin_injector_nextPcCalc_valids_4; + reg [31:0] IBusSimplePlugin_injector_formal_rawInDecode; + wire IBusSimplePlugin_cmd_valid; + wire IBusSimplePlugin_cmd_ready; + wire [31:0] IBusSimplePlugin_cmd_payload_pc; + wire IBusSimplePlugin_pending_inc; + wire IBusSimplePlugin_pending_dec; + reg [2:0] IBusSimplePlugin_pending_value; + wire [2:0] IBusSimplePlugin_pending_next; + wire IBusSimplePlugin_cmdFork_canEmit; + wire IBusSimplePlugin_rspJoin_rspBuffer_output_valid; + wire IBusSimplePlugin_rspJoin_rspBuffer_output_ready; + wire IBusSimplePlugin_rspJoin_rspBuffer_output_payload_error; + wire [31:0] IBusSimplePlugin_rspJoin_rspBuffer_output_payload_inst; + reg [2:0] IBusSimplePlugin_rspJoin_rspBuffer_discardCounter; + wire IBusSimplePlugin_rspJoin_rspBuffer_flush; + wire [31:0] IBusSimplePlugin_rspJoin_fetchRsp_pc; + reg IBusSimplePlugin_rspJoin_fetchRsp_rsp_error; + wire [31:0] IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst; + wire IBusSimplePlugin_rspJoin_fetchRsp_isRvc; + wire IBusSimplePlugin_rspJoin_join_valid; + wire IBusSimplePlugin_rspJoin_join_ready; + wire [31:0] IBusSimplePlugin_rspJoin_join_payload_pc; + wire IBusSimplePlugin_rspJoin_join_payload_rsp_error; + wire [31:0] IBusSimplePlugin_rspJoin_join_payload_rsp_inst; + wire IBusSimplePlugin_rspJoin_join_payload_isRvc; + wire IBusSimplePlugin_rspJoin_exceptionDetected; + wire _zz_56; + wire _zz_57; + reg execute_DBusSimplePlugin_skipCmd; + reg [31:0] _zz_58; + reg [3:0] _zz_59; + wire [3:0] execute_DBusSimplePlugin_formalMask; + reg [31:0] writeBack_DBusSimplePlugin_rspShifted; + wire _zz_60; + reg [31:0] _zz_61; + wire _zz_62; + reg [31:0] _zz_63; + reg [31:0] writeBack_DBusSimplePlugin_rspFormated; + wire [1:0] CsrPlugin_misa_base; + wire [25:0] CsrPlugin_misa_extensions; + wire [1:0] CsrPlugin_mtvec_mode; + wire [29:0] CsrPlugin_mtvec_base; + reg [31:0] CsrPlugin_mepc; + reg CsrPlugin_mstatus_MIE; + reg CsrPlugin_mstatus_MPIE; + reg [1:0] CsrPlugin_mstatus_MPP; + reg CsrPlugin_mip_MEIP; + reg CsrPlugin_mip_MTIP; + reg CsrPlugin_mip_MSIP; + reg CsrPlugin_mie_MEIE; + reg CsrPlugin_mie_MTIE; + reg CsrPlugin_mie_MSIE; + reg CsrPlugin_mcause_interrupt; + reg [3:0] CsrPlugin_mcause_exceptionCode; + reg [31:0] CsrPlugin_mtval; + reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; + reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; + wire _zz_64; + wire _zz_65; + wire _zz_66; + reg CsrPlugin_interrupt_valid; + reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; + reg [1:0] CsrPlugin_interrupt_targetPrivilege; + wire CsrPlugin_exception; + wire CsrPlugin_lastStageWasWfi; + reg CsrPlugin_pipelineLiberator_pcValids_0; + reg CsrPlugin_pipelineLiberator_pcValids_1; + reg CsrPlugin_pipelineLiberator_pcValids_2; + wire CsrPlugin_pipelineLiberator_active; + reg CsrPlugin_pipelineLiberator_done; + wire CsrPlugin_interruptJump /* verilator public */ ; + reg CsrPlugin_hadException /* verilator public */ ; + wire [1:0] CsrPlugin_targetPrivilege; + wire [3:0] CsrPlugin_trapCause; + reg [1:0] CsrPlugin_xtvec_mode; + reg [29:0] CsrPlugin_xtvec_base; + reg execute_CsrPlugin_wfiWake; + wire execute_CsrPlugin_blockedBySideEffects; + reg execute_CsrPlugin_illegalAccess; + reg execute_CsrPlugin_illegalInstruction; + wire [31:0] execute_CsrPlugin_readData; + reg execute_CsrPlugin_writeInstruction; + reg execute_CsrPlugin_readInstruction; + wire execute_CsrPlugin_writeEnable; + wire execute_CsrPlugin_readEnable; + wire [31:0] execute_CsrPlugin_readToWriteData; + reg [31:0] execute_CsrPlugin_writeData; + wire [11:0] execute_CsrPlugin_csrAddress; + wire [24:0] _zz_67; + wire _zz_68; + wire _zz_69; + wire _zz_70; + wire _zz_71; + wire _zz_72; + wire `Src1CtrlEnum_defaultEncoding_type _zz_73; + wire `Src2CtrlEnum_defaultEncoding_type _zz_74; + wire `EnvCtrlEnum_defaultEncoding_type _zz_75; + wire `AluCtrlEnum_defaultEncoding_type _zz_76; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_77; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_78; + wire `BranchCtrlEnum_defaultEncoding_type _zz_79; + wire [4:0] decode_RegFilePlugin_regFileReadAddress1; + wire [4:0] decode_RegFilePlugin_regFileReadAddress2; + wire [31:0] decode_RegFilePlugin_rs1Data; + wire [31:0] decode_RegFilePlugin_rs2Data; + reg lastStageRegFileWrite_valid /* verilator public */ ; + reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; + reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; + reg _zz_80; + reg [31:0] execute_IntAluPlugin_bitwise; + reg [31:0] _zz_81; + reg [31:0] _zz_82; + wire _zz_83; + reg [19:0] _zz_84; + wire _zz_85; + reg [19:0] _zz_86; + reg [31:0] _zz_87; + reg [31:0] execute_SrcPlugin_addSub; + wire execute_SrcPlugin_less; + reg execute_LightShifterPlugin_isActive; + wire execute_LightShifterPlugin_isShift; + reg [4:0] execute_LightShifterPlugin_amplitudeReg; + wire [4:0] execute_LightShifterPlugin_amplitude; + wire [31:0] execute_LightShifterPlugin_shiftInput; + wire execute_LightShifterPlugin_done; + reg [31:0] _zz_88; + reg _zz_89; + reg _zz_90; + reg _zz_91; + reg [4:0] _zz_92; + wire execute_BranchPlugin_eq; + wire [2:0] _zz_93; + reg _zz_94; + reg _zz_95; + wire [31:0] execute_BranchPlugin_branch_src1; + wire _zz_96; + reg [10:0] _zz_97; + wire _zz_98; + reg [19:0] _zz_99; + wire _zz_100; + reg [18:0] _zz_101; + reg [31:0] _zz_102; + wire [31:0] execute_BranchPlugin_branch_src2; + wire [31:0] execute_BranchPlugin_branchAdder; + reg [31:0] decode_to_execute_PC; + reg [31:0] execute_to_memory_PC; + reg [31:0] memory_to_writeBack_PC; + reg [31:0] decode_to_execute_INSTRUCTION; + reg [31:0] execute_to_memory_INSTRUCTION; + reg [31:0] memory_to_writeBack_INSTRUCTION; + reg [31:0] decode_to_execute_FORMAL_PC_NEXT; + reg [31:0] execute_to_memory_FORMAL_PC_NEXT; + reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; + reg decode_to_execute_CSR_WRITE_OPCODE; + reg decode_to_execute_CSR_READ_OPCODE; + reg decode_to_execute_SRC_USE_SUB_LESS; + reg decode_to_execute_MEMORY_ENABLE; + reg execute_to_memory_MEMORY_ENABLE; + reg memory_to_writeBack_MEMORY_ENABLE; + reg decode_to_execute_REGFILE_WRITE_VALID; + reg execute_to_memory_REGFILE_WRITE_VALID; + reg memory_to_writeBack_REGFILE_WRITE_VALID; + reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; + reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; + reg decode_to_execute_MEMORY_STORE; + reg execute_to_memory_MEMORY_STORE; + reg memory_to_writeBack_MEMORY_STORE; + reg decode_to_execute_IS_CSR; + reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; + reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL; + reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL; + reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; + reg decode_to_execute_SRC_LESS_UNSIGNED; + reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; + reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; + reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; + reg [31:0] decode_to_execute_RS1; + reg [31:0] decode_to_execute_RS2; + reg decode_to_execute_SRC2_FORCE_ZERO; + reg [31:0] decode_to_execute_SRC1; + reg [31:0] decode_to_execute_SRC2; + reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW; + reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW; + reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; + reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; + reg execute_to_memory_BRANCH_DO; + reg [31:0] execute_to_memory_BRANCH_CALC; + reg [31:0] memory_to_writeBack_MEMORY_READ_DATA; + reg execute_CsrPlugin_csr_768; + reg execute_CsrPlugin_csr_836; + reg execute_CsrPlugin_csr_772; + reg execute_CsrPlugin_csr_834; + reg [31:0] _zz_103; + reg [31:0] _zz_104; + reg [31:0] _zz_105; + reg [31:0] _zz_106; + `ifndef SYNTHESIS + reg [31:0] decode_BRANCH_CTRL_string; + reg [31:0] _zz_1_string; + reg [31:0] _zz_2_string; + reg [31:0] _zz_3_string; + reg [71:0] decode_SHIFT_CTRL_string; + reg [71:0] _zz_4_string; + reg [71:0] _zz_5_string; + reg [71:0] _zz_6_string; + reg [39:0] decode_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_7_string; + reg [39:0] _zz_8_string; + reg [39:0] _zz_9_string; + reg [63:0] decode_ALU_CTRL_string; + reg [63:0] _zz_10_string; + reg [63:0] _zz_11_string; + reg [63:0] _zz_12_string; + reg [31:0] _zz_13_string; + reg [31:0] _zz_14_string; + reg [31:0] _zz_15_string; + reg [31:0] _zz_16_string; + reg [31:0] decode_ENV_CTRL_string; + reg [31:0] _zz_17_string; + reg [31:0] _zz_18_string; + reg [31:0] _zz_19_string; + reg [31:0] execute_BRANCH_CTRL_string; + reg [31:0] _zz_20_string; + reg [71:0] execute_SHIFT_CTRL_string; + reg [71:0] _zz_21_string; + reg [23:0] decode_SRC2_CTRL_string; + reg [23:0] _zz_24_string; + reg [95:0] decode_SRC1_CTRL_string; + reg [95:0] _zz_26_string; + reg [63:0] execute_ALU_CTRL_string; + reg [63:0] _zz_27_string; + reg [39:0] execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_28_string; + reg [31:0] _zz_32_string; + reg [71:0] _zz_33_string; + reg [39:0] _zz_34_string; + reg [63:0] _zz_35_string; + reg [31:0] _zz_36_string; + reg [23:0] _zz_37_string; + reg [95:0] _zz_38_string; + reg [31:0] memory_ENV_CTRL_string; + reg [31:0] _zz_40_string; + reg [31:0] execute_ENV_CTRL_string; + reg [31:0] _zz_41_string; + reg [31:0] writeBack_ENV_CTRL_string; + reg [31:0] _zz_42_string; + reg [95:0] _zz_73_string; + reg [23:0] _zz_74_string; + reg [31:0] _zz_75_string; + reg [63:0] _zz_76_string; + reg [39:0] _zz_77_string; + reg [71:0] _zz_78_string; + reg [31:0] _zz_79_string; + reg [31:0] decode_to_execute_ENV_CTRL_string; + reg [31:0] execute_to_memory_ENV_CTRL_string; + reg [31:0] memory_to_writeBack_ENV_CTRL_string; + reg [63:0] decode_to_execute_ALU_CTRL_string; + reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string; + reg [71:0] decode_to_execute_SHIFT_CTRL_string; + reg [31:0] decode_to_execute_BRANCH_CTRL_string; + `endif + + reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; + + assign _zz_111 = (execute_arbitration_isValid && execute_IS_CSR); + assign _zz_112 = ((execute_arbitration_isValid && execute_LightShifterPlugin_isShift) && (execute_SRC2[4 : 0] != 5'h0)); + assign _zz_113 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign _zz_114 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); + assign _zz_115 = writeBack_INSTRUCTION[29 : 28]; + assign _zz_116 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign _zz_117 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_118 = (1'b1 || (! 1'b1)); + assign _zz_119 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_120 = (1'b1 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign _zz_121 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_122 = (1'b1 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign _zz_123 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign _zz_124 = ((_zz_64 && 1'b1) && (! 1'b0)); + assign _zz_125 = ((_zz_65 && 1'b1) && (! 1'b0)); + assign _zz_126 = ((_zz_66 && 1'b1) && (! 1'b0)); + assign _zz_127 = (! execute_arbitration_isStuckByOthers); + assign _zz_128 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_129 = execute_INSTRUCTION[13]; + assign _zz_130 = _zz_67[17 : 17]; + assign _zz_131 = _zz_67[12 : 12]; + assign _zz_132 = _zz_67[10 : 10]; + assign _zz_133 = _zz_67[9 : 9]; + assign _zz_134 = _zz_67[8 : 8]; + assign _zz_135 = _zz_67[3 : 3]; + assign _zz_136 = _zz_67[11 : 11]; + assign _zz_137 = _zz_67[4 : 4]; + assign _zz_138 = _zz_67[2 : 2]; + assign _zz_139 = _zz_67[20 : 20]; + assign _zz_140 = _zz_67[7 : 7]; + assign _zz_141 = (_zz_45 & (~ _zz_142)); + assign _zz_142 = (_zz_45 - 2'b01); + assign _zz_143 = {IBusSimplePlugin_fetchPc_inc,2'b00}; + assign _zz_144 = {29'd0, _zz_143}; + assign _zz_145 = (IBusSimplePlugin_pending_value + _zz_147); + assign _zz_146 = IBusSimplePlugin_pending_inc; + assign _zz_147 = {2'd0, _zz_146}; + assign _zz_148 = IBusSimplePlugin_pending_dec; + assign _zz_149 = {2'd0, _zz_148}; + assign _zz_150 = (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid && (IBusSimplePlugin_rspJoin_rspBuffer_discardCounter != 3'b000)); + assign _zz_151 = {2'd0, _zz_150}; + assign _zz_152 = IBusSimplePlugin_pending_dec; + assign _zz_153 = {2'd0, _zz_152}; + assign _zz_154 = execute_SRC_LESS; + assign _zz_155 = 3'b100; + assign _zz_156 = decode_INSTRUCTION[19 : 15]; + assign _zz_157 = decode_INSTRUCTION[31 : 20]; + assign _zz_158 = {decode_INSTRUCTION[31 : 25],decode_INSTRUCTION[11 : 7]}; + assign _zz_159 = ($signed(_zz_160) + $signed(_zz_163)); + assign _zz_160 = ($signed(_zz_161) + $signed(_zz_162)); + assign _zz_161 = execute_SRC1; + assign _zz_162 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_163 = (execute_SRC_USE_SUB_LESS ? _zz_164 : _zz_165); + assign _zz_164 = 32'h00000001; + assign _zz_165 = 32'h0; + assign _zz_166 = (_zz_167 >>> 1); + assign _zz_167 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_LightShifterPlugin_shiftInput[31]),execute_LightShifterPlugin_shiftInput}; + assign _zz_168 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_169 = execute_INSTRUCTION[31 : 20]; + assign _zz_170 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_171 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_172 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_173 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_174 = execute_CsrPlugin_writeData[11 : 11]; + assign _zz_175 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_176 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_177 = 1'b1; + assign _zz_178 = 1'b1; + assign _zz_179 = (decode_INSTRUCTION & 32'h0000001c); + assign _zz_180 = 32'h00000004; + assign _zz_181 = (decode_INSTRUCTION & 32'h00000058); + assign _zz_182 = 32'h00000040; + assign _zz_183 = ((decode_INSTRUCTION & 32'h00007054) == 32'h00005010); + assign _zz_184 = {(_zz_189 == _zz_190),(_zz_191 == _zz_192)}; + assign _zz_185 = 2'b00; + assign _zz_186 = ({_zz_193,_zz_194} != 2'b00); + assign _zz_187 = (_zz_195 != 1'b0); + assign _zz_188 = {(_zz_196 != _zz_197),{_zz_198,{_zz_199,_zz_200}}}; + assign _zz_189 = (decode_INSTRUCTION & 32'h40003054); + assign _zz_190 = 32'h40001010; + assign _zz_191 = (decode_INSTRUCTION & 32'h00007054); + assign _zz_192 = 32'h00001010; + assign _zz_193 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000024); + assign _zz_194 = ((decode_INSTRUCTION & 32'h00003054) == 32'h00001010); + assign _zz_195 = ((decode_INSTRUCTION & 32'h00001000) == 32'h00001000); + assign _zz_196 = ((decode_INSTRUCTION & _zz_201) == 32'h00002000); + assign _zz_197 = 1'b0; + assign _zz_198 = ({_zz_202,_zz_203} != 2'b00); + assign _zz_199 = ({_zz_204,_zz_205} != 2'b00); + assign _zz_200 = {(_zz_206 != _zz_207),{_zz_208,{_zz_209,_zz_210}}}; + assign _zz_201 = 32'h00003000; + assign _zz_202 = ((decode_INSTRUCTION & 32'h00002010) == 32'h00002000); + assign _zz_203 = ((decode_INSTRUCTION & 32'h00005000) == 32'h00001000); + assign _zz_204 = ((decode_INSTRUCTION & _zz_211) == 32'h00006000); + assign _zz_205 = ((decode_INSTRUCTION & _zz_212) == 32'h00004000); + assign _zz_206 = _zz_69; + assign _zz_207 = 1'b0; + assign _zz_208 = ({_zz_213,_zz_214} != 2'b00); + assign _zz_209 = (_zz_215 != 1'b0); + assign _zz_210 = {(_zz_216 != _zz_217),{_zz_218,{_zz_219,_zz_220}}}; + assign _zz_211 = 32'h00006004; + assign _zz_212 = 32'h00005004; + assign _zz_213 = ((decode_INSTRUCTION & 32'h00000050) == 32'h00000040); + assign _zz_214 = ((decode_INSTRUCTION & 32'h00003040) == 32'h00000040); + assign _zz_215 = ((decode_INSTRUCTION & 32'h00003050) == 32'h00000050); + assign _zz_216 = {(_zz_221 == _zz_222),(_zz_223 == _zz_224)}; + assign _zz_217 = 2'b00; + assign _zz_218 = ({_zz_225,_zz_226} != 2'b00); + assign _zz_219 = (_zz_227 != 1'b0); + assign _zz_220 = {(_zz_228 != _zz_229),{_zz_230,{_zz_231,_zz_232}}}; + assign _zz_221 = (decode_INSTRUCTION & 32'h00001050); + assign _zz_222 = 32'h00001050; + assign _zz_223 = (decode_INSTRUCTION & 32'h00002050); + assign _zz_224 = 32'h00002050; + assign _zz_225 = ((decode_INSTRUCTION & 32'h00000034) == 32'h00000020); + assign _zz_226 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000020); + assign _zz_227 = ((decode_INSTRUCTION & 32'h00000020) == 32'h00000020); + assign _zz_228 = ((decode_INSTRUCTION & _zz_233) == 32'h00000010); + assign _zz_229 = 1'b0; + assign _zz_230 = (_zz_71 != 1'b0); + assign _zz_231 = ({_zz_234,_zz_235} != 6'h0); + assign _zz_232 = {(_zz_236 != _zz_237),{_zz_238,{_zz_239,_zz_240}}}; + assign _zz_233 = 32'h00000010; + assign _zz_234 = _zz_72; + assign _zz_235 = {(_zz_241 == _zz_242),{_zz_243,{_zz_244,_zz_245}}}; + assign _zz_236 = {_zz_70,(_zz_246 == _zz_247)}; + assign _zz_237 = 2'b00; + assign _zz_238 = ({_zz_70,_zz_248} != 2'b00); + assign _zz_239 = ({_zz_249,_zz_250} != 4'b0000); + assign _zz_240 = {(_zz_251 != _zz_252),{_zz_253,{_zz_254,_zz_255}}}; + assign _zz_241 = (decode_INSTRUCTION & 32'h00001010); + assign _zz_242 = 32'h00001010; + assign _zz_243 = ((decode_INSTRUCTION & _zz_256) == 32'h00002010); + assign _zz_244 = _zz_71; + assign _zz_245 = {_zz_257,_zz_258}; + assign _zz_246 = (decode_INSTRUCTION & 32'h00000070); + assign _zz_247 = 32'h00000020; + assign _zz_248 = ((decode_INSTRUCTION & _zz_259) == 32'h0); + assign _zz_249 = (_zz_260 == _zz_261); + assign _zz_250 = {_zz_262,{_zz_263,_zz_264}}; + assign _zz_251 = (_zz_265 == _zz_266); + assign _zz_252 = 1'b0; + assign _zz_253 = ({_zz_267,_zz_268} != 3'b000); + assign _zz_254 = (_zz_269 != _zz_270); + assign _zz_255 = (_zz_271 != _zz_272); + assign _zz_256 = 32'h00002010; + assign _zz_257 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000004); + assign _zz_258 = ((decode_INSTRUCTION & 32'h00000028) == 32'h0); + assign _zz_259 = 32'h00000020; + assign _zz_260 = (decode_INSTRUCTION & 32'h00000044); + assign _zz_261 = 32'h0; + assign _zz_262 = ((decode_INSTRUCTION & 32'h00000018) == 32'h0); + assign _zz_263 = _zz_69; + assign _zz_264 = ((decode_INSTRUCTION & _zz_273) == 32'h00001000); + assign _zz_265 = (decode_INSTRUCTION & 32'h00000058); + assign _zz_266 = 32'h0; + assign _zz_267 = ((decode_INSTRUCTION & _zz_274) == 32'h00000040); + assign _zz_268 = {(_zz_275 == _zz_276),(_zz_277 == _zz_278)}; + assign _zz_269 = {(_zz_279 == _zz_280),_zz_68}; + assign _zz_270 = 2'b00; + assign _zz_271 = {(_zz_281 == _zz_282),_zz_68}; + assign _zz_272 = 2'b00; + assign _zz_273 = 32'h00005004; + assign _zz_274 = 32'h00000044; + assign _zz_275 = (decode_INSTRUCTION & 32'h00002014); + assign _zz_276 = 32'h00002010; + assign _zz_277 = (decode_INSTRUCTION & 32'h40004034); + assign _zz_278 = 32'h40000030; + assign _zz_279 = (decode_INSTRUCTION & 32'h00000014); + assign _zz_280 = 32'h00000004; + assign _zz_281 = (decode_INSTRUCTION & 32'h00000044); + assign _zz_282 = 32'h00000004; + always @ (posedge clk) begin + if(_zz_177) begin + _zz_109 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + end + end + + always @ (posedge clk) begin + if(_zz_178) begin + _zz_110 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + end + end + + always @ (posedge clk) begin + if(_zz_31) begin + RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; + end + end + + StreamFifoLowLatency IBusSimplePlugin_rspJoin_rspBuffer_c ( + .io_push_valid (iBus_rsp_valid ), //i + .io_push_ready (IBusSimplePlugin_rspJoin_rspBuffer_c_io_push_ready ), //o + .io_push_payload_error (iBus_rsp_payload_error ), //i + .io_push_payload_inst (iBus_rsp_payload_inst[31:0] ), //i + .io_pop_valid (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid ), //o + .io_pop_ready (_zz_107 ), //i + .io_pop_payload_error (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error ), //o + .io_pop_payload_inst (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst[31:0] ), //o + .io_flush (_zz_108 ), //i + .io_occupancy (IBusSimplePlugin_rspJoin_rspBuffer_c_io_occupancy ), //o + .clk (clk ), //i + .reset (reset ) //i + ); + `ifndef SYNTHESIS + always @(*) begin + case(decode_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR"; + default : decode_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_1) + `BranchCtrlEnum_defaultEncoding_INC : _zz_1_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_1_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_1_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_1_string = "JALR"; + default : _zz_1_string = "????"; + endcase + end + always @(*) begin + case(_zz_2) + `BranchCtrlEnum_defaultEncoding_INC : _zz_2_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_2_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_2_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_2_string = "JALR"; + default : _zz_2_string = "????"; + endcase + end + always @(*) begin + case(_zz_3) + `BranchCtrlEnum_defaultEncoding_INC : _zz_3_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_3_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_3_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_3_string = "JALR"; + default : _zz_3_string = "????"; + endcase + end + always @(*) begin + case(decode_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; + default : decode_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_4) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_4_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_4_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_4_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_4_string = "SRA_1 "; + default : _zz_4_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_5) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_5_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_5_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_5_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_5_string = "SRA_1 "; + default : _zz_5_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_6) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_6_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_6_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_6_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_6_string = "SRA_1 "; + default : _zz_6_string = "?????????"; + endcase + end + always @(*) begin + case(decode_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_7) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_7_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_7_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_7_string = "AND_1"; + default : _zz_7_string = "?????"; + endcase + end + always @(*) begin + case(_zz_8) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_8_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_8_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_8_string = "AND_1"; + default : _zz_8_string = "?????"; + endcase + end + always @(*) begin + case(_zz_9) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_9_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_9_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_9_string = "AND_1"; + default : _zz_9_string = "?????"; + endcase + end + always @(*) begin + case(decode_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; + default : decode_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_10) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_10_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_10_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_10_string = "BITWISE "; + default : _zz_10_string = "????????"; + endcase + end + always @(*) begin + case(_zz_11) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_11_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_11_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_11_string = "BITWISE "; + default : _zz_11_string = "????????"; + endcase + end + always @(*) begin + case(_zz_12) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_12_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_12_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_12_string = "BITWISE "; + default : _zz_12_string = "????????"; + endcase + end + always @(*) begin + case(_zz_13) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_13_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_13_string = "XRET"; + default : _zz_13_string = "????"; + endcase + end + always @(*) begin + case(_zz_14) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_14_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_14_string = "XRET"; + default : _zz_14_string = "????"; + endcase + end + always @(*) begin + case(_zz_15) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_15_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_15_string = "XRET"; + default : _zz_15_string = "????"; + endcase + end + always @(*) begin + case(_zz_16) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_16_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_16_string = "XRET"; + default : _zz_16_string = "????"; + endcase + end + always @(*) begin + case(decode_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET"; + default : decode_ENV_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_17) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_17_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_17_string = "XRET"; + default : _zz_17_string = "????"; + endcase + end + always @(*) begin + case(_zz_18) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_18_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_18_string = "XRET"; + default : _zz_18_string = "????"; + endcase + end + always @(*) begin + case(_zz_19) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_19_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_19_string = "XRET"; + default : _zz_19_string = "????"; + endcase + end + always @(*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : execute_BRANCH_CTRL_string = "JALR"; + default : execute_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_20) + `BranchCtrlEnum_defaultEncoding_INC : _zz_20_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_20_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_20_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_20_string = "JALR"; + default : _zz_20_string = "????"; + endcase + end + always @(*) begin + case(execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; + default : execute_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_21) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_21_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_21_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_21_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_21_string = "SRA_1 "; + default : _zz_21_string = "?????????"; + endcase + end + always @(*) begin + case(decode_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; + default : decode_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(_zz_24) + `Src2CtrlEnum_defaultEncoding_RS : _zz_24_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_24_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_24_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_24_string = "PC "; + default : _zz_24_string = "???"; + endcase + end + always @(*) begin + case(decode_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; + default : decode_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_26) + `Src1CtrlEnum_defaultEncoding_RS : _zz_26_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_26_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_26_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_26_string = "URS1 "; + default : _zz_26_string = "????????????"; + endcase + end + always @(*) begin + case(execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : execute_ALU_CTRL_string = "BITWISE "; + default : execute_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_27) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_27_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_27_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_27_string = "BITWISE "; + default : _zz_27_string = "????????"; + endcase + end + always @(*) begin + case(execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : execute_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_28) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_28_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_28_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_28_string = "AND_1"; + default : _zz_28_string = "?????"; + endcase + end + always @(*) begin + case(_zz_32) + `BranchCtrlEnum_defaultEncoding_INC : _zz_32_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_32_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_32_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_32_string = "JALR"; + default : _zz_32_string = "????"; + endcase + end + always @(*) begin + case(_zz_33) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_33_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_33_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_33_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_33_string = "SRA_1 "; + default : _zz_33_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_34) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_34_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_34_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_34_string = "AND_1"; + default : _zz_34_string = "?????"; + endcase + end + always @(*) begin + case(_zz_35) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_35_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_35_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_35_string = "BITWISE "; + default : _zz_35_string = "????????"; + endcase + end + always @(*) begin + case(_zz_36) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_36_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_36_string = "XRET"; + default : _zz_36_string = "????"; + endcase + end + always @(*) begin + case(_zz_37) + `Src2CtrlEnum_defaultEncoding_RS : _zz_37_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_37_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_37_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_37_string = "PC "; + default : _zz_37_string = "???"; + endcase + end + always @(*) begin + case(_zz_38) + `Src1CtrlEnum_defaultEncoding_RS : _zz_38_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_38_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_38_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_38_string = "URS1 "; + default : _zz_38_string = "????????????"; + endcase + end + always @(*) begin + case(memory_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : memory_ENV_CTRL_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : memory_ENV_CTRL_string = "XRET"; + default : memory_ENV_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_40) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_40_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_40_string = "XRET"; + default : _zz_40_string = "????"; + endcase + end + always @(*) begin + case(execute_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : execute_ENV_CTRL_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : execute_ENV_CTRL_string = "XRET"; + default : execute_ENV_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_41) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_41_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_41_string = "XRET"; + default : _zz_41_string = "????"; + endcase + end + always @(*) begin + case(writeBack_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : writeBack_ENV_CTRL_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : writeBack_ENV_CTRL_string = "XRET"; + default : writeBack_ENV_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_42) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_42_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_42_string = "XRET"; + default : _zz_42_string = "????"; + endcase + end + always @(*) begin + case(_zz_73) + `Src1CtrlEnum_defaultEncoding_RS : _zz_73_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_73_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_73_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_73_string = "URS1 "; + default : _zz_73_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_74) + `Src2CtrlEnum_defaultEncoding_RS : _zz_74_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_74_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_74_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_74_string = "PC "; + default : _zz_74_string = "???"; + endcase + end + always @(*) begin + case(_zz_75) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_75_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_75_string = "XRET"; + default : _zz_75_string = "????"; + endcase + end + always @(*) begin + case(_zz_76) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_76_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_76_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_76_string = "BITWISE "; + default : _zz_76_string = "????????"; + endcase + end + always @(*) begin + case(_zz_77) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_77_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_77_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_77_string = "AND_1"; + default : _zz_77_string = "?????"; + endcase + end + always @(*) begin + case(_zz_78) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_78_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_78_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_78_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_78_string = "SRA_1 "; + default : _zz_78_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_79) + `BranchCtrlEnum_defaultEncoding_INC : _zz_79_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_79_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_79_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_79_string = "JALR"; + default : _zz_79_string = "????"; + endcase + end + always @(*) begin + case(decode_to_execute_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : decode_to_execute_ENV_CTRL_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : decode_to_execute_ENV_CTRL_string = "XRET"; + default : decode_to_execute_ENV_CTRL_string = "????"; + endcase + end + always @(*) begin + case(execute_to_memory_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : execute_to_memory_ENV_CTRL_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : execute_to_memory_ENV_CTRL_string = "XRET"; + default : execute_to_memory_ENV_CTRL_string = "????"; + endcase + end + always @(*) begin + case(memory_to_writeBack_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET"; + default : memory_to_writeBack_ENV_CTRL_string = "????"; + endcase + end + always @(*) begin + case(decode_to_execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; + default : decode_to_execute_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(decode_to_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(decode_to_execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + default : decode_to_execute_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(decode_to_execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; + default : decode_to_execute_BRANCH_CTRL_string = "????"; + endcase + end + `endif + + assign memory_MEMORY_READ_DATA = dBus_rsp_data; + assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; + assign execute_BRANCH_DO = _zz_95; + assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA; + assign execute_REGFILE_WRITE_DATA = _zz_81; + assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; + assign execute_MEMORY_ADDRESS_LOW = dBus_cmd_payload_address[1 : 0]; + assign decode_SRC2 = _zz_87; + assign decode_SRC1 = _zz_82; + assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); + assign decode_RS2 = decode_RegFilePlugin_rs2Data; + assign decode_RS1 = decode_RegFilePlugin_rs1Data; + assign decode_BRANCH_CTRL = _zz_1; + assign _zz_2 = _zz_3; + assign decode_SHIFT_CTRL = _zz_4; + assign _zz_5 = _zz_6; + assign decode_ALU_BITWISE_CTRL = _zz_7; + assign _zz_8 = _zz_9; + assign decode_SRC_LESS_UNSIGNED = _zz_130[0]; + assign decode_ALU_CTRL = _zz_10; + assign _zz_11 = _zz_12; + assign _zz_13 = _zz_14; + assign _zz_15 = _zz_16; + assign decode_ENV_CTRL = _zz_17; + assign _zz_18 = _zz_19; + assign decode_IS_CSR = _zz_131[0]; + assign decode_MEMORY_STORE = _zz_132[0]; + assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_133[0]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_134[0]; + assign decode_MEMORY_ENABLE = _zz_135[0]; + assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); + assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); + assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; + assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; + assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; + assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004); + assign memory_PC = execute_to_memory_PC; + assign memory_BRANCH_CALC = execute_to_memory_BRANCH_CALC; + assign memory_BRANCH_DO = execute_to_memory_BRANCH_DO; + assign execute_PC = decode_to_execute_PC; + assign execute_RS1 = decode_to_execute_RS1; + assign execute_BRANCH_CTRL = _zz_20; + assign decode_RS2_USE = _zz_136[0]; + assign decode_RS1_USE = _zz_137[0]; + assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID; + assign execute_BYPASSABLE_EXECUTE_STAGE = decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + assign memory_REGFILE_WRITE_VALID = execute_to_memory_REGFILE_WRITE_VALID; + assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION; + assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE; + assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; + assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA; + assign execute_SHIFT_CTRL = _zz_21; + assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; + assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; + assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; + assign _zz_22 = decode_PC; + assign _zz_23 = decode_RS2; + assign decode_SRC2_CTRL = _zz_24; + assign _zz_25 = decode_RS1; + assign decode_SRC1_CTRL = _zz_26; + assign decode_SRC_USE_SUB_LESS = _zz_138[0]; + assign decode_SRC_ADD_ZERO = _zz_139[0]; + assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; + assign execute_SRC_LESS = execute_SrcPlugin_less; + assign execute_ALU_CTRL = _zz_27; + assign execute_SRC2 = decode_to_execute_SRC2; + assign execute_ALU_BITWISE_CTRL = _zz_28; + assign _zz_29 = writeBack_INSTRUCTION; + assign _zz_30 = writeBack_REGFILE_WRITE_VALID; + always @ (*) begin + _zz_31 = 1'b0; + if(lastStageRegFileWrite_valid)begin + _zz_31 = 1'b1; + end + end + + assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusSimplePlugin_iBusRsp_output_payload_rsp_inst); + always @ (*) begin + decode_REGFILE_WRITE_VALID = _zz_140[0]; + if((decode_INSTRUCTION[11 : 7] == 5'h0))begin + decode_REGFILE_WRITE_VALID = 1'b0; + end + end + + always @ (*) begin + _zz_39 = execute_REGFILE_WRITE_DATA; + if(_zz_111)begin + _zz_39 = execute_CsrPlugin_readData; + end + if(_zz_112)begin + _zz_39 = _zz_88; + end + end + + assign execute_SRC1 = decode_to_execute_SRC1; + assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; + assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; + assign execute_IS_CSR = decode_to_execute_IS_CSR; + assign memory_ENV_CTRL = _zz_40; + assign execute_ENV_CTRL = _zz_41; + assign writeBack_ENV_CTRL = _zz_42; + assign writeBack_MEMORY_STORE = memory_to_writeBack_MEMORY_STORE; + always @ (*) begin + _zz_43 = writeBack_REGFILE_WRITE_DATA; + if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin + _zz_43 = writeBack_DBusSimplePlugin_rspFormated; + end + end + + assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE; + assign writeBack_MEMORY_ADDRESS_LOW = memory_to_writeBack_MEMORY_ADDRESS_LOW; + assign writeBack_MEMORY_READ_DATA = memory_to_writeBack_MEMORY_READ_DATA; + assign memory_MEMORY_STORE = execute_to_memory_MEMORY_STORE; + assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE; + assign execute_SRC_ADD = execute_SrcPlugin_addSub; + assign execute_RS2 = decode_to_execute_RS2; + assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; + assign execute_MEMORY_STORE = decode_to_execute_MEMORY_STORE; + assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; + assign execute_ALIGNEMENT_FAULT = 1'b0; + always @ (*) begin + _zz_44 = memory_FORMAL_PC_NEXT; + if(BranchPlugin_jumpInterface_valid)begin + _zz_44 = BranchPlugin_jumpInterface_payload; + end + end + + assign decode_PC = IBusSimplePlugin_injector_decodeInput_payload_pc; + assign decode_INSTRUCTION = IBusSimplePlugin_injector_decodeInput_payload_rsp_inst; + assign writeBack_PC = memory_to_writeBack_PC; + assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION; + assign decode_arbitration_haltItself = 1'b0; + always @ (*) begin + decode_arbitration_haltByOther = 1'b0; + if(CsrPlugin_pipelineLiberator_active)begin + decode_arbitration_haltByOther = 1'b1; + end + if(({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET))}} != 3'b000))begin + decode_arbitration_haltByOther = 1'b1; + end + if((decode_arbitration_isValid && (_zz_89 || _zz_90)))begin + decode_arbitration_haltByOther = 1'b1; + end + end + + always @ (*) begin + decode_arbitration_removeIt = 1'b0; + if(decode_arbitration_isFlushed)begin + decode_arbitration_removeIt = 1'b1; + end + end + + assign decode_arbitration_flushIt = 1'b0; + assign decode_arbitration_flushNext = 1'b0; + always @ (*) begin + execute_arbitration_haltItself = 1'b0; + if(((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! dBus_cmd_ready)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_57)))begin + execute_arbitration_haltItself = 1'b1; + end + if(_zz_111)begin + if(execute_CsrPlugin_blockedBySideEffects)begin + execute_arbitration_haltItself = 1'b1; + end + end + if(_zz_112)begin + if((! execute_LightShifterPlugin_done))begin + execute_arbitration_haltItself = 1'b1; + end + end + end + + assign execute_arbitration_haltByOther = 1'b0; + always @ (*) begin + execute_arbitration_removeIt = 1'b0; + if(execute_arbitration_isFlushed)begin + execute_arbitration_removeIt = 1'b1; + end + end + + assign execute_arbitration_flushIt = 1'b0; + assign execute_arbitration_flushNext = 1'b0; + always @ (*) begin + memory_arbitration_haltItself = 1'b0; + if((((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (! memory_MEMORY_STORE)) && ((! dBus_rsp_ready) || 1'b0)))begin + memory_arbitration_haltItself = 1'b1; + end + end + + assign memory_arbitration_haltByOther = 1'b0; + always @ (*) begin + memory_arbitration_removeIt = 1'b0; + if(memory_arbitration_isFlushed)begin + memory_arbitration_removeIt = 1'b1; + end + end + + assign memory_arbitration_flushIt = 1'b0; + always @ (*) begin + memory_arbitration_flushNext = 1'b0; + if(BranchPlugin_jumpInterface_valid)begin + memory_arbitration_flushNext = 1'b1; + end + end + + assign writeBack_arbitration_haltItself = 1'b0; + assign writeBack_arbitration_haltByOther = 1'b0; + always @ (*) begin + writeBack_arbitration_removeIt = 1'b0; + if(writeBack_arbitration_isFlushed)begin + writeBack_arbitration_removeIt = 1'b1; + end + end + + assign writeBack_arbitration_flushIt = 1'b0; + always @ (*) begin + writeBack_arbitration_flushNext = 1'b0; + if(_zz_113)begin + writeBack_arbitration_flushNext = 1'b1; + end + if(_zz_114)begin + writeBack_arbitration_flushNext = 1'b1; + end + end + + assign lastStageInstruction = writeBack_INSTRUCTION; + assign lastStagePc = writeBack_PC; + assign lastStageIsValid = writeBack_arbitration_isValid; + assign lastStageIsFiring = writeBack_arbitration_isFiring; + always @ (*) begin + IBusSimplePlugin_fetcherHalt = 1'b0; + if(_zz_113)begin + IBusSimplePlugin_fetcherHalt = 1'b1; + end + if(_zz_114)begin + IBusSimplePlugin_fetcherHalt = 1'b1; + end + end + + always @ (*) begin + IBusSimplePlugin_incomingInstruction = 1'b0; + if(IBusSimplePlugin_iBusRsp_stages_1_input_valid)begin + IBusSimplePlugin_incomingInstruction = 1'b1; + end + if(IBusSimplePlugin_injector_decodeInput_valid)begin + IBusSimplePlugin_incomingInstruction = 1'b1; + end + end + + assign CsrPlugin_inWfi = 1'b0; + assign CsrPlugin_thirdPartyWake = 1'b0; + always @ (*) begin + CsrPlugin_jumpInterface_valid = 1'b0; + if(_zz_113)begin + CsrPlugin_jumpInterface_valid = 1'b1; + end + if(_zz_114)begin + CsrPlugin_jumpInterface_valid = 1'b1; + end + end + + always @ (*) begin + CsrPlugin_jumpInterface_payload = 32'h0; + if(_zz_113)begin + CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; + end + if(_zz_114)begin + case(_zz_115) + 2'b11 : begin + CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; + end + default : begin + end + endcase + end + end + + assign CsrPlugin_forceMachineWire = 1'b0; + assign CsrPlugin_allowInterrupts = 1'b1; + assign CsrPlugin_allowException = 1'b1; + assign IBusSimplePlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); + assign IBusSimplePlugin_jump_pcLoad_valid = ({BranchPlugin_jumpInterface_valid,CsrPlugin_jumpInterface_valid} != 2'b00); + assign _zz_45 = {BranchPlugin_jumpInterface_valid,CsrPlugin_jumpInterface_valid}; + assign IBusSimplePlugin_jump_pcLoad_payload = (_zz_141[0] ? CsrPlugin_jumpInterface_payload : BranchPlugin_jumpInterface_payload); + always @ (*) begin + IBusSimplePlugin_fetchPc_correction = 1'b0; + if(IBusSimplePlugin_jump_pcLoad_valid)begin + IBusSimplePlugin_fetchPc_correction = 1'b1; + end + end + + assign IBusSimplePlugin_fetchPc_corrected = (IBusSimplePlugin_fetchPc_correction || IBusSimplePlugin_fetchPc_correctionReg); + always @ (*) begin + IBusSimplePlugin_fetchPc_pcRegPropagate = 1'b0; + if(IBusSimplePlugin_iBusRsp_stages_1_input_ready)begin + IBusSimplePlugin_fetchPc_pcRegPropagate = 1'b1; + end + end + + always @ (*) begin + IBusSimplePlugin_fetchPc_pc = (IBusSimplePlugin_fetchPc_pcReg + _zz_144); + if(IBusSimplePlugin_jump_pcLoad_valid)begin + IBusSimplePlugin_fetchPc_pc = IBusSimplePlugin_jump_pcLoad_payload; + end + IBusSimplePlugin_fetchPc_pc[0] = 1'b0; + IBusSimplePlugin_fetchPc_pc[1] = 1'b0; + end + + always @ (*) begin + IBusSimplePlugin_fetchPc_flushed = 1'b0; + if(IBusSimplePlugin_jump_pcLoad_valid)begin + IBusSimplePlugin_fetchPc_flushed = 1'b1; + end + end + + assign IBusSimplePlugin_fetchPc_output_valid = ((! IBusSimplePlugin_fetcherHalt) && IBusSimplePlugin_fetchPc_booted); + assign IBusSimplePlugin_fetchPc_output_payload = IBusSimplePlugin_fetchPc_pc; + assign IBusSimplePlugin_iBusRsp_redoFetch = 1'b0; + assign IBusSimplePlugin_iBusRsp_stages_0_input_valid = IBusSimplePlugin_fetchPc_output_valid; + assign IBusSimplePlugin_fetchPc_output_ready = IBusSimplePlugin_iBusRsp_stages_0_input_ready; + assign IBusSimplePlugin_iBusRsp_stages_0_input_payload = IBusSimplePlugin_fetchPc_output_payload; + always @ (*) begin + IBusSimplePlugin_iBusRsp_stages_0_halt = 1'b0; + if((IBusSimplePlugin_iBusRsp_stages_0_input_valid && ((! IBusSimplePlugin_cmdFork_canEmit) || (! IBusSimplePlugin_cmd_ready))))begin + IBusSimplePlugin_iBusRsp_stages_0_halt = 1'b1; + end + end + + assign _zz_46 = (! IBusSimplePlugin_iBusRsp_stages_0_halt); + assign IBusSimplePlugin_iBusRsp_stages_0_input_ready = (IBusSimplePlugin_iBusRsp_stages_0_output_ready && _zz_46); + assign IBusSimplePlugin_iBusRsp_stages_0_output_valid = (IBusSimplePlugin_iBusRsp_stages_0_input_valid && _zz_46); + assign IBusSimplePlugin_iBusRsp_stages_0_output_payload = IBusSimplePlugin_iBusRsp_stages_0_input_payload; + assign IBusSimplePlugin_iBusRsp_stages_1_halt = 1'b0; + assign _zz_47 = (! IBusSimplePlugin_iBusRsp_stages_1_halt); + assign IBusSimplePlugin_iBusRsp_stages_1_input_ready = (IBusSimplePlugin_iBusRsp_stages_1_output_ready && _zz_47); + assign IBusSimplePlugin_iBusRsp_stages_1_output_valid = (IBusSimplePlugin_iBusRsp_stages_1_input_valid && _zz_47); + assign IBusSimplePlugin_iBusRsp_stages_1_output_payload = IBusSimplePlugin_iBusRsp_stages_1_input_payload; + assign IBusSimplePlugin_iBusRsp_flush = (IBusSimplePlugin_externalFlush || IBusSimplePlugin_iBusRsp_redoFetch); + assign IBusSimplePlugin_iBusRsp_stages_0_output_ready = _zz_48; + assign _zz_48 = ((1'b0 && (! _zz_49)) || IBusSimplePlugin_iBusRsp_stages_1_input_ready); + assign _zz_49 = _zz_50; + assign IBusSimplePlugin_iBusRsp_stages_1_input_valid = _zz_49; + assign IBusSimplePlugin_iBusRsp_stages_1_input_payload = IBusSimplePlugin_fetchPc_pcReg; + always @ (*) begin + IBusSimplePlugin_iBusRsp_readyForError = 1'b1; + if(IBusSimplePlugin_injector_decodeInput_valid)begin + IBusSimplePlugin_iBusRsp_readyForError = 1'b0; + end + if((! IBusSimplePlugin_pcValids_0))begin + IBusSimplePlugin_iBusRsp_readyForError = 1'b0; + end + end + + assign IBusSimplePlugin_iBusRsp_output_ready = ((1'b0 && (! IBusSimplePlugin_injector_decodeInput_valid)) || IBusSimplePlugin_injector_decodeInput_ready); + assign IBusSimplePlugin_injector_decodeInput_valid = _zz_51; + assign IBusSimplePlugin_injector_decodeInput_payload_pc = _zz_52; + assign IBusSimplePlugin_injector_decodeInput_payload_rsp_error = _zz_53; + assign IBusSimplePlugin_injector_decodeInput_payload_rsp_inst = _zz_54; + assign IBusSimplePlugin_injector_decodeInput_payload_isRvc = _zz_55; + assign IBusSimplePlugin_pcValids_0 = IBusSimplePlugin_injector_nextPcCalc_valids_1; + assign IBusSimplePlugin_pcValids_1 = IBusSimplePlugin_injector_nextPcCalc_valids_2; + assign IBusSimplePlugin_pcValids_2 = IBusSimplePlugin_injector_nextPcCalc_valids_3; + assign IBusSimplePlugin_pcValids_3 = IBusSimplePlugin_injector_nextPcCalc_valids_4; + assign IBusSimplePlugin_injector_decodeInput_ready = (! decode_arbitration_isStuck); + assign decode_arbitration_isValid = IBusSimplePlugin_injector_decodeInput_valid; + assign iBus_cmd_valid = IBusSimplePlugin_cmd_valid; + assign IBusSimplePlugin_cmd_ready = iBus_cmd_ready; + assign iBus_cmd_payload_pc = IBusSimplePlugin_cmd_payload_pc; + assign IBusSimplePlugin_pending_next = (_zz_145 - _zz_149); + assign IBusSimplePlugin_cmdFork_canEmit = (IBusSimplePlugin_iBusRsp_stages_0_output_ready && (IBusSimplePlugin_pending_value != 3'b111)); + assign IBusSimplePlugin_cmd_valid = (IBusSimplePlugin_iBusRsp_stages_0_input_valid && IBusSimplePlugin_cmdFork_canEmit); + assign IBusSimplePlugin_pending_inc = (IBusSimplePlugin_cmd_valid && IBusSimplePlugin_cmd_ready); + assign IBusSimplePlugin_cmd_payload_pc = {IBusSimplePlugin_iBusRsp_stages_0_input_payload[31 : 2],2'b00}; + assign IBusSimplePlugin_rspJoin_rspBuffer_flush = ((IBusSimplePlugin_rspJoin_rspBuffer_discardCounter != 3'b000) || IBusSimplePlugin_iBusRsp_flush); + assign IBusSimplePlugin_rspJoin_rspBuffer_output_valid = (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid && (IBusSimplePlugin_rspJoin_rspBuffer_discardCounter == 3'b000)); + assign IBusSimplePlugin_rspJoin_rspBuffer_output_payload_error = IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error; + assign IBusSimplePlugin_rspJoin_rspBuffer_output_payload_inst = IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst; + assign _zz_107 = (IBusSimplePlugin_rspJoin_rspBuffer_output_ready || IBusSimplePlugin_rspJoin_rspBuffer_flush); + assign IBusSimplePlugin_pending_dec = (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid && _zz_107); + assign IBusSimplePlugin_rspJoin_fetchRsp_pc = IBusSimplePlugin_iBusRsp_stages_1_output_payload; + always @ (*) begin + IBusSimplePlugin_rspJoin_fetchRsp_rsp_error = IBusSimplePlugin_rspJoin_rspBuffer_output_payload_error; + if((! IBusSimplePlugin_rspJoin_rspBuffer_output_valid))begin + IBusSimplePlugin_rspJoin_fetchRsp_rsp_error = 1'b0; + end + end + + assign IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst = IBusSimplePlugin_rspJoin_rspBuffer_output_payload_inst; + assign IBusSimplePlugin_rspJoin_exceptionDetected = 1'b0; + assign IBusSimplePlugin_rspJoin_join_valid = (IBusSimplePlugin_iBusRsp_stages_1_output_valid && IBusSimplePlugin_rspJoin_rspBuffer_output_valid); + assign IBusSimplePlugin_rspJoin_join_payload_pc = IBusSimplePlugin_rspJoin_fetchRsp_pc; + assign IBusSimplePlugin_rspJoin_join_payload_rsp_error = IBusSimplePlugin_rspJoin_fetchRsp_rsp_error; + assign IBusSimplePlugin_rspJoin_join_payload_rsp_inst = IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst; + assign IBusSimplePlugin_rspJoin_join_payload_isRvc = IBusSimplePlugin_rspJoin_fetchRsp_isRvc; + assign IBusSimplePlugin_iBusRsp_stages_1_output_ready = (IBusSimplePlugin_iBusRsp_stages_1_output_valid ? (IBusSimplePlugin_rspJoin_join_valid && IBusSimplePlugin_rspJoin_join_ready) : IBusSimplePlugin_rspJoin_join_ready); + assign IBusSimplePlugin_rspJoin_rspBuffer_output_ready = (IBusSimplePlugin_rspJoin_join_valid && IBusSimplePlugin_rspJoin_join_ready); + assign _zz_56 = (! IBusSimplePlugin_rspJoin_exceptionDetected); + assign IBusSimplePlugin_rspJoin_join_ready = (IBusSimplePlugin_iBusRsp_output_ready && _zz_56); + assign IBusSimplePlugin_iBusRsp_output_valid = (IBusSimplePlugin_rspJoin_join_valid && _zz_56); + assign IBusSimplePlugin_iBusRsp_output_payload_pc = IBusSimplePlugin_rspJoin_join_payload_pc; + assign IBusSimplePlugin_iBusRsp_output_payload_rsp_error = IBusSimplePlugin_rspJoin_join_payload_rsp_error; + assign IBusSimplePlugin_iBusRsp_output_payload_rsp_inst = IBusSimplePlugin_rspJoin_join_payload_rsp_inst; + assign IBusSimplePlugin_iBusRsp_output_payload_isRvc = IBusSimplePlugin_rspJoin_join_payload_isRvc; + assign _zz_57 = 1'b0; + always @ (*) begin + execute_DBusSimplePlugin_skipCmd = 1'b0; + if(execute_ALIGNEMENT_FAULT)begin + execute_DBusSimplePlugin_skipCmd = 1'b1; + end + end + + assign dBus_cmd_valid = (((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_arbitration_isStuckByOthers)) && (! execute_arbitration_isFlushed)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_57)); + assign dBus_cmd_payload_wr = execute_MEMORY_STORE; + assign dBus_cmd_payload_size = execute_INSTRUCTION[13 : 12]; + always @ (*) begin + case(dBus_cmd_payload_size) + 2'b00 : begin + _zz_58 = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; + end + 2'b01 : begin + _zz_58 = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; + end + default : begin + _zz_58 = execute_RS2[31 : 0]; + end + endcase + end + + assign dBus_cmd_payload_data = _zz_58; + always @ (*) begin + case(dBus_cmd_payload_size) + 2'b00 : begin + _zz_59 = 4'b0001; + end + 2'b01 : begin + _zz_59 = 4'b0011; + end + default : begin + _zz_59 = 4'b1111; + end + endcase + end + + assign execute_DBusSimplePlugin_formalMask = (_zz_59 <<< dBus_cmd_payload_address[1 : 0]); + assign dBus_cmd_payload_address = execute_SRC_ADD; + always @ (*) begin + writeBack_DBusSimplePlugin_rspShifted = writeBack_MEMORY_READ_DATA; + case(writeBack_MEMORY_ADDRESS_LOW) + 2'b01 : begin + writeBack_DBusSimplePlugin_rspShifted[7 : 0] = writeBack_MEMORY_READ_DATA[15 : 8]; + end + 2'b10 : begin + writeBack_DBusSimplePlugin_rspShifted[15 : 0] = writeBack_MEMORY_READ_DATA[31 : 16]; + end + 2'b11 : begin + writeBack_DBusSimplePlugin_rspShifted[7 : 0] = writeBack_MEMORY_READ_DATA[31 : 24]; + end + default : begin + end + endcase + end + + assign _zz_60 = (writeBack_DBusSimplePlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); + always @ (*) begin + _zz_61[31] = _zz_60; + _zz_61[30] = _zz_60; + _zz_61[29] = _zz_60; + _zz_61[28] = _zz_60; + _zz_61[27] = _zz_60; + _zz_61[26] = _zz_60; + _zz_61[25] = _zz_60; + _zz_61[24] = _zz_60; + _zz_61[23] = _zz_60; + _zz_61[22] = _zz_60; + _zz_61[21] = _zz_60; + _zz_61[20] = _zz_60; + _zz_61[19] = _zz_60; + _zz_61[18] = _zz_60; + _zz_61[17] = _zz_60; + _zz_61[16] = _zz_60; + _zz_61[15] = _zz_60; + _zz_61[14] = _zz_60; + _zz_61[13] = _zz_60; + _zz_61[12] = _zz_60; + _zz_61[11] = _zz_60; + _zz_61[10] = _zz_60; + _zz_61[9] = _zz_60; + _zz_61[8] = _zz_60; + _zz_61[7 : 0] = writeBack_DBusSimplePlugin_rspShifted[7 : 0]; + end + + assign _zz_62 = (writeBack_DBusSimplePlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); + always @ (*) begin + _zz_63[31] = _zz_62; + _zz_63[30] = _zz_62; + _zz_63[29] = _zz_62; + _zz_63[28] = _zz_62; + _zz_63[27] = _zz_62; + _zz_63[26] = _zz_62; + _zz_63[25] = _zz_62; + _zz_63[24] = _zz_62; + _zz_63[23] = _zz_62; + _zz_63[22] = _zz_62; + _zz_63[21] = _zz_62; + _zz_63[20] = _zz_62; + _zz_63[19] = _zz_62; + _zz_63[18] = _zz_62; + _zz_63[17] = _zz_62; + _zz_63[16] = _zz_62; + _zz_63[15 : 0] = writeBack_DBusSimplePlugin_rspShifted[15 : 0]; + end + + always @ (*) begin + case(_zz_128) + 2'b00 : begin + writeBack_DBusSimplePlugin_rspFormated = _zz_61; + end + 2'b01 : begin + writeBack_DBusSimplePlugin_rspFormated = _zz_63; + end + default : begin + writeBack_DBusSimplePlugin_rspFormated = writeBack_DBusSimplePlugin_rspShifted; + end + endcase + end + + always @ (*) begin + CsrPlugin_privilege = 2'b11; + if(CsrPlugin_forceMachineWire)begin + CsrPlugin_privilege = 2'b11; + end + end + + assign CsrPlugin_misa_base = 2'b01; + assign CsrPlugin_misa_extensions = 26'h0000042; + assign CsrPlugin_mtvec_mode = 2'b00; + assign CsrPlugin_mtvec_base = 30'h00000008; + assign _zz_64 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_65 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_66 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign CsrPlugin_exception = 1'b0; + assign CsrPlugin_lastStageWasWfi = 1'b0; + assign CsrPlugin_pipelineLiberator_active = ((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts) && decode_arbitration_isValid); + always @ (*) begin + CsrPlugin_pipelineLiberator_done = CsrPlugin_pipelineLiberator_pcValids_2; + if(CsrPlugin_hadException)begin + CsrPlugin_pipelineLiberator_done = 1'b0; + end + end + + assign CsrPlugin_interruptJump = ((CsrPlugin_interrupt_valid && CsrPlugin_pipelineLiberator_done) && CsrPlugin_allowInterrupts); + assign CsrPlugin_targetPrivilege = CsrPlugin_interrupt_targetPrivilege; + assign CsrPlugin_trapCause = CsrPlugin_interrupt_code; + always @ (*) begin + CsrPlugin_xtvec_mode = 2'bxx; + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_xtvec_mode = CsrPlugin_mtvec_mode; + end + default : begin + end + endcase + end + + always @ (*) begin + CsrPlugin_xtvec_base = 30'h0; + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_xtvec_base = CsrPlugin_mtvec_base; + end + default : begin + end + endcase + end + + assign contextSwitching = CsrPlugin_jumpInterface_valid; + assign execute_CsrPlugin_blockedBySideEffects = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) || 1'b0); + always @ (*) begin + execute_CsrPlugin_illegalAccess = 1'b1; + if(execute_CsrPlugin_csr_768)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_836)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_772)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_834)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(_zz_116)begin + execute_CsrPlugin_illegalAccess = 1'b1; + end + if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + + always @ (*) begin + execute_CsrPlugin_illegalInstruction = 1'b0; + if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)))begin + if((CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]))begin + execute_CsrPlugin_illegalInstruction = 1'b1; + end + end + end + + always @ (*) begin + execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); + if(_zz_116)begin + execute_CsrPlugin_writeInstruction = 1'b0; + end + end + + always @ (*) begin + execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); + if(_zz_116)begin + execute_CsrPlugin_readInstruction = 1'b0; + end + end + + assign execute_CsrPlugin_writeEnable = (execute_CsrPlugin_writeInstruction && (! execute_arbitration_isStuck)); + assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); + assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; + always @ (*) begin + case(_zz_129) + 1'b0 : begin + execute_CsrPlugin_writeData = execute_SRC1; + end + default : begin + execute_CsrPlugin_writeData = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); + end + endcase + end + + assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; + assign _zz_68 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); + assign _zz_69 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); + assign _zz_70 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); + assign _zz_71 = ((decode_INSTRUCTION & 32'h00000050) == 32'h00000010); + assign _zz_72 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); + assign _zz_67 = {({_zz_72,(_zz_179 == _zz_180)} != 2'b00),{((_zz_181 == _zz_182) != 1'b0),{(_zz_183 != 1'b0),{(_zz_184 != _zz_185),{_zz_186,{_zz_187,_zz_188}}}}}}; + assign _zz_73 = _zz_67[1 : 0]; + assign _zz_38 = _zz_73; + assign _zz_74 = _zz_67[6 : 5]; + assign _zz_37 = _zz_74; + assign _zz_75 = _zz_67[13 : 13]; + assign _zz_36 = _zz_75; + assign _zz_76 = _zz_67[16 : 15]; + assign _zz_35 = _zz_76; + assign _zz_77 = _zz_67[19 : 18]; + assign _zz_34 = _zz_77; + assign _zz_78 = _zz_67[22 : 21]; + assign _zz_33 = _zz_78; + assign _zz_79 = _zz_67[24 : 23]; + assign _zz_32 = _zz_79; + assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; + assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; + assign decode_RegFilePlugin_rs1Data = _zz_109; + assign decode_RegFilePlugin_rs2Data = _zz_110; + always @ (*) begin + lastStageRegFileWrite_valid = (_zz_30 && writeBack_arbitration_isFiring); + if(_zz_80)begin + lastStageRegFileWrite_valid = 1'b1; + end + end + + always @ (*) begin + lastStageRegFileWrite_payload_address = _zz_29[11 : 7]; + if(_zz_80)begin + lastStageRegFileWrite_payload_address = 5'h0; + end + end + + always @ (*) begin + lastStageRegFileWrite_payload_data = _zz_43; + if(_zz_80)begin + lastStageRegFileWrite_payload_data = 32'h0; + end + end + + always @ (*) begin + case(execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2); + end + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2); + end + default : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 ^ execute_SRC2); + end + endcase + end + + always @ (*) begin + case(execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_BITWISE : begin + _zz_81 = execute_IntAluPlugin_bitwise; + end + `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin + _zz_81 = {31'd0, _zz_154}; + end + default : begin + _zz_81 = execute_SRC_ADD_SUB; + end + endcase + end + + always @ (*) begin + case(decode_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : begin + _zz_82 = _zz_25; + end + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin + _zz_82 = {29'd0, _zz_155}; + end + `Src1CtrlEnum_defaultEncoding_IMU : begin + _zz_82 = {decode_INSTRUCTION[31 : 12],12'h0}; + end + default : begin + _zz_82 = {27'd0, _zz_156}; + end + endcase + end + + assign _zz_83 = _zz_157[11]; + always @ (*) begin + _zz_84[19] = _zz_83; + _zz_84[18] = _zz_83; + _zz_84[17] = _zz_83; + _zz_84[16] = _zz_83; + _zz_84[15] = _zz_83; + _zz_84[14] = _zz_83; + _zz_84[13] = _zz_83; + _zz_84[12] = _zz_83; + _zz_84[11] = _zz_83; + _zz_84[10] = _zz_83; + _zz_84[9] = _zz_83; + _zz_84[8] = _zz_83; + _zz_84[7] = _zz_83; + _zz_84[6] = _zz_83; + _zz_84[5] = _zz_83; + _zz_84[4] = _zz_83; + _zz_84[3] = _zz_83; + _zz_84[2] = _zz_83; + _zz_84[1] = _zz_83; + _zz_84[0] = _zz_83; + end + + assign _zz_85 = _zz_158[11]; + always @ (*) begin + _zz_86[19] = _zz_85; + _zz_86[18] = _zz_85; + _zz_86[17] = _zz_85; + _zz_86[16] = _zz_85; + _zz_86[15] = _zz_85; + _zz_86[14] = _zz_85; + _zz_86[13] = _zz_85; + _zz_86[12] = _zz_85; + _zz_86[11] = _zz_85; + _zz_86[10] = _zz_85; + _zz_86[9] = _zz_85; + _zz_86[8] = _zz_85; + _zz_86[7] = _zz_85; + _zz_86[6] = _zz_85; + _zz_86[5] = _zz_85; + _zz_86[4] = _zz_85; + _zz_86[3] = _zz_85; + _zz_86[2] = _zz_85; + _zz_86[1] = _zz_85; + _zz_86[0] = _zz_85; + end + + always @ (*) begin + case(decode_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : begin + _zz_87 = _zz_23; + end + `Src2CtrlEnum_defaultEncoding_IMI : begin + _zz_87 = {_zz_84,decode_INSTRUCTION[31 : 20]}; + end + `Src2CtrlEnum_defaultEncoding_IMS : begin + _zz_87 = {_zz_86,{decode_INSTRUCTION[31 : 25],decode_INSTRUCTION[11 : 7]}}; + end + default : begin + _zz_87 = _zz_22; + end + endcase + end + + always @ (*) begin + execute_SrcPlugin_addSub = _zz_159; + if(execute_SRC2_FORCE_ZERO)begin + execute_SrcPlugin_addSub = execute_SRC1; + end + end + + assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); + assign execute_LightShifterPlugin_isShift = (execute_SHIFT_CTRL != `ShiftCtrlEnum_defaultEncoding_DISABLE_1); + assign execute_LightShifterPlugin_amplitude = (execute_LightShifterPlugin_isActive ? execute_LightShifterPlugin_amplitudeReg : execute_SRC2[4 : 0]); + assign execute_LightShifterPlugin_shiftInput = (execute_LightShifterPlugin_isActive ? memory_REGFILE_WRITE_DATA : execute_SRC1); + assign execute_LightShifterPlugin_done = (execute_LightShifterPlugin_amplitude[4 : 1] == 4'b0000); + always @ (*) begin + case(execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin + _zz_88 = (execute_LightShifterPlugin_shiftInput <<< 1); + end + default : begin + _zz_88 = _zz_166; + end + endcase + end + + always @ (*) begin + _zz_89 = 1'b0; + if(_zz_91)begin + if((_zz_92 == decode_INSTRUCTION[19 : 15]))begin + _zz_89 = 1'b1; + end + end + if(_zz_117)begin + if(_zz_118)begin + if((writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin + _zz_89 = 1'b1; + end + end + end + if(_zz_119)begin + if(_zz_120)begin + if((memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin + _zz_89 = 1'b1; + end + end + end + if(_zz_121)begin + if(_zz_122)begin + if((execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin + _zz_89 = 1'b1; + end + end + end + if((! decode_RS1_USE))begin + _zz_89 = 1'b0; + end + end + + always @ (*) begin + _zz_90 = 1'b0; + if(_zz_91)begin + if((_zz_92 == decode_INSTRUCTION[24 : 20]))begin + _zz_90 = 1'b1; + end + end + if(_zz_117)begin + if(_zz_118)begin + if((writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin + _zz_90 = 1'b1; + end + end + end + if(_zz_119)begin + if(_zz_120)begin + if((memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin + _zz_90 = 1'b1; + end + end + end + if(_zz_121)begin + if(_zz_122)begin + if((execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin + _zz_90 = 1'b1; + end + end + end + if((! decode_RS2_USE))begin + _zz_90 = 1'b0; + end + end + + assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); + assign _zz_93 = execute_INSTRUCTION[14 : 12]; + always @ (*) begin + if((_zz_93 == 3'b000)) begin + _zz_94 = execute_BranchPlugin_eq; + end else if((_zz_93 == 3'b001)) begin + _zz_94 = (! execute_BranchPlugin_eq); + end else if((((_zz_93 & 3'b101) == 3'b101))) begin + _zz_94 = (! execute_SRC_LESS); + end else begin + _zz_94 = execute_SRC_LESS; + end + end + + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : begin + _zz_95 = 1'b0; + end + `BranchCtrlEnum_defaultEncoding_JAL : begin + _zz_95 = 1'b1; + end + `BranchCtrlEnum_defaultEncoding_JALR : begin + _zz_95 = 1'b1; + end + default : begin + _zz_95 = _zz_94; + end + endcase + end + + assign execute_BranchPlugin_branch_src1 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JALR) ? execute_RS1 : execute_PC); + assign _zz_96 = _zz_168[19]; + always @ (*) begin + _zz_97[10] = _zz_96; + _zz_97[9] = _zz_96; + _zz_97[8] = _zz_96; + _zz_97[7] = _zz_96; + _zz_97[6] = _zz_96; + _zz_97[5] = _zz_96; + _zz_97[4] = _zz_96; + _zz_97[3] = _zz_96; + _zz_97[2] = _zz_96; + _zz_97[1] = _zz_96; + _zz_97[0] = _zz_96; + end + + assign _zz_98 = _zz_169[11]; + always @ (*) begin + _zz_99[19] = _zz_98; + _zz_99[18] = _zz_98; + _zz_99[17] = _zz_98; + _zz_99[16] = _zz_98; + _zz_99[15] = _zz_98; + _zz_99[14] = _zz_98; + _zz_99[13] = _zz_98; + _zz_99[12] = _zz_98; + _zz_99[11] = _zz_98; + _zz_99[10] = _zz_98; + _zz_99[9] = _zz_98; + _zz_99[8] = _zz_98; + _zz_99[7] = _zz_98; + _zz_99[6] = _zz_98; + _zz_99[5] = _zz_98; + _zz_99[4] = _zz_98; + _zz_99[3] = _zz_98; + _zz_99[2] = _zz_98; + _zz_99[1] = _zz_98; + _zz_99[0] = _zz_98; + end + + assign _zz_100 = _zz_170[11]; + always @ (*) begin + _zz_101[18] = _zz_100; + _zz_101[17] = _zz_100; + _zz_101[16] = _zz_100; + _zz_101[15] = _zz_100; + _zz_101[14] = _zz_100; + _zz_101[13] = _zz_100; + _zz_101[12] = _zz_100; + _zz_101[11] = _zz_100; + _zz_101[10] = _zz_100; + _zz_101[9] = _zz_100; + _zz_101[8] = _zz_100; + _zz_101[7] = _zz_100; + _zz_101[6] = _zz_100; + _zz_101[5] = _zz_100; + _zz_101[4] = _zz_100; + _zz_101[3] = _zz_100; + _zz_101[2] = _zz_100; + _zz_101[1] = _zz_100; + _zz_101[0] = _zz_100; + end + + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JAL : begin + _zz_102 = {{_zz_97,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + end + `BranchCtrlEnum_defaultEncoding_JALR : begin + _zz_102 = {_zz_99,execute_INSTRUCTION[31 : 20]}; + end + default : begin + _zz_102 = {{_zz_101,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + end + endcase + end + + assign execute_BranchPlugin_branch_src2 = _zz_102; + assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); + assign BranchPlugin_jumpInterface_valid = ((memory_arbitration_isValid && memory_BRANCH_DO) && (! 1'b0)); + assign BranchPlugin_jumpInterface_payload = memory_BRANCH_CALC; + assign _zz_26 = _zz_38; + assign _zz_24 = _zz_37; + assign _zz_19 = decode_ENV_CTRL; + assign _zz_16 = execute_ENV_CTRL; + assign _zz_14 = memory_ENV_CTRL; + assign _zz_17 = _zz_36; + assign _zz_41 = decode_to_execute_ENV_CTRL; + assign _zz_40 = execute_to_memory_ENV_CTRL; + assign _zz_42 = memory_to_writeBack_ENV_CTRL; + assign _zz_12 = decode_ALU_CTRL; + assign _zz_10 = _zz_35; + assign _zz_27 = decode_to_execute_ALU_CTRL; + assign _zz_9 = decode_ALU_BITWISE_CTRL; + assign _zz_7 = _zz_34; + assign _zz_28 = decode_to_execute_ALU_BITWISE_CTRL; + assign _zz_6 = decode_SHIFT_CTRL; + assign _zz_4 = _zz_33; + assign _zz_21 = decode_to_execute_SHIFT_CTRL; + assign _zz_3 = decode_BRANCH_CTRL; + assign _zz_1 = _zz_32; + assign _zz_20 = decode_to_execute_BRANCH_CTRL; + assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != 3'b000) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != 4'b0000)); + assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != 2'b00) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != 3'b000)); + assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != 1'b0) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != 2'b00)); + assign writeBack_arbitration_isFlushed = (1'b0 || (writeBack_arbitration_flushIt != 1'b0)); + assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (((1'b0 || execute_arbitration_isStuck) || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); + assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers); + assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); + assign decode_arbitration_isFiring = ((decode_arbitration_isValid && (! decode_arbitration_isStuck)) && (! decode_arbitration_removeIt)); + assign execute_arbitration_isStuckByOthers = (execute_arbitration_haltByOther || ((1'b0 || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); + assign execute_arbitration_isStuck = (execute_arbitration_haltItself || execute_arbitration_isStuckByOthers); + assign execute_arbitration_isMoving = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); + assign execute_arbitration_isFiring = ((execute_arbitration_isValid && (! execute_arbitration_isStuck)) && (! execute_arbitration_removeIt)); + assign memory_arbitration_isStuckByOthers = (memory_arbitration_haltByOther || (1'b0 || writeBack_arbitration_isStuck)); + assign memory_arbitration_isStuck = (memory_arbitration_haltItself || memory_arbitration_isStuckByOthers); + assign memory_arbitration_isMoving = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)); + assign memory_arbitration_isFiring = ((memory_arbitration_isValid && (! memory_arbitration_isStuck)) && (! memory_arbitration_removeIt)); + assign writeBack_arbitration_isStuckByOthers = (writeBack_arbitration_haltByOther || 1'b0); + assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers); + assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); + assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); + always @ (*) begin + _zz_103 = 32'h0; + if(execute_CsrPlugin_csr_768)begin + _zz_103[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_103[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_103[3 : 3] = CsrPlugin_mstatus_MIE; + end + end + + always @ (*) begin + _zz_104 = 32'h0; + if(execute_CsrPlugin_csr_836)begin + _zz_104[11 : 11] = CsrPlugin_mip_MEIP; + _zz_104[7 : 7] = CsrPlugin_mip_MTIP; + _zz_104[3 : 3] = CsrPlugin_mip_MSIP; + end + end + + always @ (*) begin + _zz_105 = 32'h0; + if(execute_CsrPlugin_csr_772)begin + _zz_105[11 : 11] = CsrPlugin_mie_MEIE; + _zz_105[7 : 7] = CsrPlugin_mie_MTIE; + _zz_105[3 : 3] = CsrPlugin_mie_MSIE; + end + end + + always @ (*) begin + _zz_106 = 32'h0; + if(execute_CsrPlugin_csr_834)begin + _zz_106[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_106[3 : 0] = CsrPlugin_mcause_exceptionCode; + end + end + + assign execute_CsrPlugin_readData = ((_zz_103 | _zz_104) | (_zz_105 | _zz_106)); + assign _zz_108 = 1'b0; + always @ (posedge clk or posedge reset) begin + if (reset) begin + IBusSimplePlugin_fetchPc_pcReg <= 32'h80000000; + IBusSimplePlugin_fetchPc_correctionReg <= 1'b0; + IBusSimplePlugin_fetchPc_booted <= 1'b0; + IBusSimplePlugin_fetchPc_inc <= 1'b0; + _zz_50 <= 1'b0; + _zz_51 <= 1'b0; + IBusSimplePlugin_injector_nextPcCalc_valids_0 <= 1'b0; + IBusSimplePlugin_injector_nextPcCalc_valids_1 <= 1'b0; + IBusSimplePlugin_injector_nextPcCalc_valids_2 <= 1'b0; + IBusSimplePlugin_injector_nextPcCalc_valids_3 <= 1'b0; + IBusSimplePlugin_injector_nextPcCalc_valids_4 <= 1'b0; + IBusSimplePlugin_pending_value <= 3'b000; + IBusSimplePlugin_rspJoin_rspBuffer_discardCounter <= 3'b000; + CsrPlugin_mstatus_MIE <= 1'b0; + CsrPlugin_mstatus_MPIE <= 1'b0; + CsrPlugin_mstatus_MPP <= 2'b11; + CsrPlugin_mie_MEIE <= 1'b0; + CsrPlugin_mie_MTIE <= 1'b0; + CsrPlugin_mie_MSIE <= 1'b0; + CsrPlugin_interrupt_valid <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; + CsrPlugin_hadException <= 1'b0; + execute_CsrPlugin_wfiWake <= 1'b0; + _zz_80 <= 1'b1; + execute_LightShifterPlugin_isActive <= 1'b0; + _zz_91 <= 1'b0; + execute_arbitration_isValid <= 1'b0; + memory_arbitration_isValid <= 1'b0; + writeBack_arbitration_isValid <= 1'b0; + end else begin + if(IBusSimplePlugin_fetchPc_correction)begin + IBusSimplePlugin_fetchPc_correctionReg <= 1'b1; + end + if((IBusSimplePlugin_fetchPc_output_valid && IBusSimplePlugin_fetchPc_output_ready))begin + IBusSimplePlugin_fetchPc_correctionReg <= 1'b0; + end + IBusSimplePlugin_fetchPc_booted <= 1'b1; + if((IBusSimplePlugin_fetchPc_correction || IBusSimplePlugin_fetchPc_pcRegPropagate))begin + IBusSimplePlugin_fetchPc_inc <= 1'b0; + end + if((IBusSimplePlugin_fetchPc_output_valid && IBusSimplePlugin_fetchPc_output_ready))begin + IBusSimplePlugin_fetchPc_inc <= 1'b1; + end + if(((! IBusSimplePlugin_fetchPc_output_valid) && IBusSimplePlugin_fetchPc_output_ready))begin + IBusSimplePlugin_fetchPc_inc <= 1'b0; + end + if((IBusSimplePlugin_fetchPc_booted && ((IBusSimplePlugin_fetchPc_output_ready || IBusSimplePlugin_fetchPc_correction) || IBusSimplePlugin_fetchPc_pcRegPropagate)))begin + IBusSimplePlugin_fetchPc_pcReg <= IBusSimplePlugin_fetchPc_pc; + end + if(IBusSimplePlugin_iBusRsp_flush)begin + _zz_50 <= 1'b0; + end + if(_zz_48)begin + _zz_50 <= (IBusSimplePlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); + end + if(decode_arbitration_removeIt)begin + _zz_51 <= 1'b0; + end + if(IBusSimplePlugin_iBusRsp_output_ready)begin + _zz_51 <= (IBusSimplePlugin_iBusRsp_output_valid && (! IBusSimplePlugin_externalFlush)); + end + if(IBusSimplePlugin_fetchPc_flushed)begin + IBusSimplePlugin_injector_nextPcCalc_valids_0 <= 1'b0; + end + if((! (! IBusSimplePlugin_iBusRsp_stages_1_input_ready)))begin + IBusSimplePlugin_injector_nextPcCalc_valids_0 <= 1'b1; + end + if(IBusSimplePlugin_fetchPc_flushed)begin + IBusSimplePlugin_injector_nextPcCalc_valids_1 <= 1'b0; + end + if((! (! IBusSimplePlugin_injector_decodeInput_ready)))begin + IBusSimplePlugin_injector_nextPcCalc_valids_1 <= IBusSimplePlugin_injector_nextPcCalc_valids_0; + end + if(IBusSimplePlugin_fetchPc_flushed)begin + IBusSimplePlugin_injector_nextPcCalc_valids_1 <= 1'b0; + end + if(IBusSimplePlugin_fetchPc_flushed)begin + IBusSimplePlugin_injector_nextPcCalc_valids_2 <= 1'b0; + end + if((! execute_arbitration_isStuck))begin + IBusSimplePlugin_injector_nextPcCalc_valids_2 <= IBusSimplePlugin_injector_nextPcCalc_valids_1; + end + if(IBusSimplePlugin_fetchPc_flushed)begin + IBusSimplePlugin_injector_nextPcCalc_valids_2 <= 1'b0; + end + if(IBusSimplePlugin_fetchPc_flushed)begin + IBusSimplePlugin_injector_nextPcCalc_valids_3 <= 1'b0; + end + if((! memory_arbitration_isStuck))begin + IBusSimplePlugin_injector_nextPcCalc_valids_3 <= IBusSimplePlugin_injector_nextPcCalc_valids_2; + end + if(IBusSimplePlugin_fetchPc_flushed)begin + IBusSimplePlugin_injector_nextPcCalc_valids_3 <= 1'b0; + end + if(IBusSimplePlugin_fetchPc_flushed)begin + IBusSimplePlugin_injector_nextPcCalc_valids_4 <= 1'b0; + end + if((! writeBack_arbitration_isStuck))begin + IBusSimplePlugin_injector_nextPcCalc_valids_4 <= IBusSimplePlugin_injector_nextPcCalc_valids_3; + end + if(IBusSimplePlugin_fetchPc_flushed)begin + IBusSimplePlugin_injector_nextPcCalc_valids_4 <= 1'b0; + end + IBusSimplePlugin_pending_value <= IBusSimplePlugin_pending_next; + IBusSimplePlugin_rspJoin_rspBuffer_discardCounter <= (IBusSimplePlugin_rspJoin_rspBuffer_discardCounter - _zz_151); + if(IBusSimplePlugin_iBusRsp_flush)begin + IBusSimplePlugin_rspJoin_rspBuffer_discardCounter <= (IBusSimplePlugin_pending_value - _zz_153); + end + `ifndef SYNTHESIS + `ifdef FORMAL + assert((! (((dBus_rsp_ready && memory_MEMORY_ENABLE) && memory_arbitration_isValid) && memory_arbitration_isStuck))); + `else + if(!(! (((dBus_rsp_ready && memory_MEMORY_ENABLE) && memory_arbitration_isValid) && memory_arbitration_isStuck))) begin + $display("FAILURE DBusSimplePlugin doesn't allow memory stage stall when read happend"); + $finish; + end + `endif + `endif + `ifndef SYNTHESIS + `ifdef FORMAL + assert((! (((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE) && (! writeBack_MEMORY_STORE)) && writeBack_arbitration_isStuck))); + `else + if(!(! (((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE) && (! writeBack_MEMORY_STORE)) && writeBack_arbitration_isStuck))) begin + $display("FAILURE DBusSimplePlugin doesn't allow writeback stage stall when read happend"); + $finish; + end + `endif + `endif + CsrPlugin_interrupt_valid <= 1'b0; + if(_zz_123)begin + if(_zz_124)begin + CsrPlugin_interrupt_valid <= 1'b1; + end + if(_zz_125)begin + CsrPlugin_interrupt_valid <= 1'b1; + end + if(_zz_126)begin + CsrPlugin_interrupt_valid <= 1'b1; + end + end + if(CsrPlugin_pipelineLiberator_active)begin + if((! execute_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b1; + end + if((! memory_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_1 <= CsrPlugin_pipelineLiberator_pcValids_0; + end + if((! writeBack_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_2 <= CsrPlugin_pipelineLiberator_pcValids_1; + end + end + if(((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt))begin + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; + end + if(CsrPlugin_interruptJump)begin + CsrPlugin_interrupt_valid <= 1'b0; + end + CsrPlugin_hadException <= CsrPlugin_exception; + if(_zz_113)begin + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_mstatus_MIE <= 1'b0; + CsrPlugin_mstatus_MPIE <= CsrPlugin_mstatus_MIE; + CsrPlugin_mstatus_MPP <= CsrPlugin_privilege; + end + default : begin + end + endcase + end + if(_zz_114)begin + case(_zz_115) + 2'b11 : begin + CsrPlugin_mstatus_MPP <= 2'b00; + CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; + CsrPlugin_mstatus_MPIE <= 1'b1; + end + default : begin + end + endcase + end + execute_CsrPlugin_wfiWake <= (({_zz_66,{_zz_65,_zz_64}} != 3'b000) || CsrPlugin_thirdPartyWake); + _zz_80 <= 1'b0; + if(_zz_112)begin + if(_zz_127)begin + execute_LightShifterPlugin_isActive <= 1'b1; + if(execute_LightShifterPlugin_done)begin + execute_LightShifterPlugin_isActive <= 1'b0; + end + end + end + if(execute_arbitration_removeIt)begin + execute_LightShifterPlugin_isActive <= 1'b0; + end + _zz_91 <= (_zz_30 && writeBack_arbitration_isFiring); + if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin + execute_arbitration_isValid <= 1'b0; + end + if(((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)))begin + execute_arbitration_isValid <= decode_arbitration_isValid; + end + if(((! memory_arbitration_isStuck) || memory_arbitration_removeIt))begin + memory_arbitration_isValid <= 1'b0; + end + if(((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)))begin + memory_arbitration_isValid <= execute_arbitration_isValid; + end + if(((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt))begin + writeBack_arbitration_isValid <= 1'b0; + end + if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin + writeBack_arbitration_isValid <= memory_arbitration_isValid; + end + if(execute_CsrPlugin_csr_768)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; + CsrPlugin_mstatus_MPIE <= _zz_171[0]; + CsrPlugin_mstatus_MIE <= _zz_172[0]; + end + end + if(execute_CsrPlugin_csr_772)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mie_MEIE <= _zz_174[0]; + CsrPlugin_mie_MTIE <= _zz_175[0]; + CsrPlugin_mie_MSIE <= _zz_176[0]; + end + end + end + end + + always @ (posedge clk) begin + if(IBusSimplePlugin_iBusRsp_output_ready)begin + _zz_52 <= IBusSimplePlugin_iBusRsp_output_payload_pc; + _zz_53 <= IBusSimplePlugin_iBusRsp_output_payload_rsp_error; + _zz_54 <= IBusSimplePlugin_iBusRsp_output_payload_rsp_inst; + _zz_55 <= IBusSimplePlugin_iBusRsp_output_payload_isRvc; + end + if(IBusSimplePlugin_injector_decodeInput_ready)begin + IBusSimplePlugin_injector_formal_rawInDecode <= IBusSimplePlugin_iBusRsp_output_payload_rsp_inst; + end + CsrPlugin_mip_MEIP <= externalInterrupt; + CsrPlugin_mip_MTIP <= timerInterrupt; + CsrPlugin_mip_MSIP <= softwareInterrupt; + CsrPlugin_mcycle <= (CsrPlugin_mcycle + 64'h0000000000000001); + if(writeBack_arbitration_isFiring)begin + CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); + end + if(_zz_123)begin + if(_zz_124)begin + CsrPlugin_interrupt_code <= 4'b0111; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + if(_zz_125)begin + CsrPlugin_interrupt_code <= 4'b0011; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + if(_zz_126)begin + CsrPlugin_interrupt_code <= 4'b1011; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + end + if(_zz_113)begin + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); + CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause; + CsrPlugin_mepc <= decode_PC; + end + default : begin + end + endcase + end + if(_zz_112)begin + if(_zz_127)begin + execute_LightShifterPlugin_amplitudeReg <= (execute_LightShifterPlugin_amplitude - 5'h01); + end + end + _zz_92 <= _zz_29[11 : 7]; + if((! execute_arbitration_isStuck))begin + decode_to_execute_PC <= _zz_22; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_PC <= execute_PC; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_PC <= memory_PC; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_FORMAL_PC_NEXT <= decode_FORMAL_PC_NEXT; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_FORMAL_PC_NEXT <= execute_FORMAL_PC_NEXT; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_FORMAL_PC_NEXT <= _zz_44; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_STORE <= decode_MEMORY_STORE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_STORE <= execute_MEMORY_STORE; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_STORE <= memory_MEMORY_STORE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_CSR <= decode_IS_CSR; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ENV_CTRL <= _zz_18; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_ENV_CTRL <= _zz_15; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_ENV_CTRL <= _zz_13; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ALU_CTRL <= _zz_11; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ALU_BITWISE_CTRL <= _zz_8; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SHIFT_CTRL <= _zz_5; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BRANCH_CTRL <= _zz_2; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_RS1 <= _zz_25; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_RS2 <= _zz_23; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC1 <= decode_SRC1; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC2 <= decode_SRC2; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW; + end + if(((! memory_arbitration_isStuck) && (! execute_arbitration_isStuckByOthers)))begin + execute_to_memory_REGFILE_WRITE_DATA <= _zz_39; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_REGFILE_WRITE_DATA <= memory_REGFILE_WRITE_DATA; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BRANCH_DO <= execute_BRANCH_DO; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_READ_DATA <= memory_MEMORY_READ_DATA; + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_768 <= (decode_INSTRUCTION[31 : 20] == 12'h300); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_836 <= (decode_INSTRUCTION[31 : 20] == 12'h344); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_772 <= (decode_INSTRUCTION[31 : 20] == 12'h304); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_834 <= (decode_INSTRUCTION[31 : 20] == 12'h342); + end + if(execute_CsrPlugin_csr_836)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mip_MSIP <= _zz_173[0]; + end + end + end + + +endmodule + +module StreamFifoLowLatency ( + input io_push_valid, + output io_push_ready, + input io_push_payload_error, + input [31:0] io_push_payload_inst, + output reg io_pop_valid, + input io_pop_ready, + output reg io_pop_payload_error, + output reg [31:0] io_pop_payload_inst, + input io_flush, + output [0:0] io_occupancy, + input clk, + input reset +); + wire _zz_4; + wire [0:0] _zz_5; + reg _zz_1; + reg pushPtr_willIncrement; + reg pushPtr_willClear; + wire pushPtr_willOverflowIfInc; + wire pushPtr_willOverflow; + reg popPtr_willIncrement; + reg popPtr_willClear; + wire popPtr_willOverflowIfInc; + wire popPtr_willOverflow; + wire ptrMatch; + reg risingOccupancy; + wire empty; + wire full; + wire pushing; + wire popping; + wire [32:0] _zz_2; + reg [32:0] _zz_3; + + assign _zz_4 = (! empty); + assign _zz_5 = _zz_2[0 : 0]; + always @ (*) begin + _zz_1 = 1'b0; + if(pushing)begin + _zz_1 = 1'b1; + end + end + + always @ (*) begin + pushPtr_willIncrement = 1'b0; + if(pushing)begin + pushPtr_willIncrement = 1'b1; + end + end + + always @ (*) begin + pushPtr_willClear = 1'b0; + if(io_flush)begin + pushPtr_willClear = 1'b1; + end + end + + assign pushPtr_willOverflowIfInc = 1'b1; + assign pushPtr_willOverflow = (pushPtr_willOverflowIfInc && pushPtr_willIncrement); + always @ (*) begin + popPtr_willIncrement = 1'b0; + if(popping)begin + popPtr_willIncrement = 1'b1; + end + end + + always @ (*) begin + popPtr_willClear = 1'b0; + if(io_flush)begin + popPtr_willClear = 1'b1; + end + end + + assign popPtr_willOverflowIfInc = 1'b1; + assign popPtr_willOverflow = (popPtr_willOverflowIfInc && popPtr_willIncrement); + assign ptrMatch = 1'b1; + assign empty = (ptrMatch && (! risingOccupancy)); + assign full = (ptrMatch && risingOccupancy); + assign pushing = (io_push_valid && io_push_ready); + assign popping = (io_pop_valid && io_pop_ready); + assign io_push_ready = (! full); + always @ (*) begin + if(_zz_4)begin + io_pop_valid = 1'b1; + end else begin + io_pop_valid = io_push_valid; + end + end + + assign _zz_2 = _zz_3; + always @ (*) begin + if(_zz_4)begin + io_pop_payload_error = _zz_5[0]; + end else begin + io_pop_payload_error = io_push_payload_error; + end + end + + always @ (*) begin + if(_zz_4)begin + io_pop_payload_inst = _zz_2[32 : 1]; + end else begin + io_pop_payload_inst = io_push_payload_inst; + end + end + + assign io_occupancy = (risingOccupancy && ptrMatch); + always @ (posedge clk or posedge reset) begin + if (reset) begin + risingOccupancy <= 1'b0; + end else begin + if((pushing != popping))begin + risingOccupancy <= pushing; + end + if(io_flush)begin + risingOccupancy <= 1'b0; + end + end + end + + always @ (posedge clk) begin + if(_zz_1)begin + _zz_3 <= {io_push_payload_inst,io_push_payload_error}; + end + end + + +endmodule diff --git a/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_dff_flow.ys b/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_dff_flow.ys index 7244532e5b..695ad4190c 100644 --- a/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_dff_flow.ys +++ b/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_dff_flow.ys @@ -75,6 +75,11 @@ opt -fast -mux_undef -undriven -fine memory_map opt -undriven -fine +######################### +# Map muxes to pmuxes +######################### +techmap -map pmux2mux.v + ######################### # Map flip-flops ######################### diff --git a/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_flow.ys b/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_flow.ys index a81474999e..6b4830235c 100644 --- a/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_flow.ys +++ b/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_flow.ys @@ -75,6 +75,11 @@ opt -fast -mux_undef -undriven -fine memory_map opt -undriven -fine +######################### +# Map muxes to pmuxes +######################### +techmap -map pmux2mux.v + ######################### # Map flip-flops ######################### diff --git a/openfpga_flow/openfpga_yosys_techlib/dsp18_map.v b/openfpga_flow/openfpga_yosys_techlib/dsp18_map.v new file mode 100644 index 0000000000..e44a983345 --- /dev/null +++ b/openfpga_flow/openfpga_yosys_techlib/dsp18_map.v @@ -0,0 +1,17 @@ +module mult_18x18 ( + input [0:17] A, + input [0:17] B, + output [0:35] Y +); + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + parameter A_WIDTH = 0; + parameter B_WIDTH = 0; + parameter Y_WIDTH = 0; + + mult_18 #() _TECHMAP_REPLACE_ ( + .A (A), + .B (B), + .Y (Y) ); + +endmodule diff --git a/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_40nm_cell_sim.v b/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_40nm_cell_sim.v new file mode 100644 index 0000000000..9a5dfd26e6 --- /dev/null +++ b/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_40nm_cell_sim.v @@ -0,0 +1,220 @@ +//----------------------------- +// Dual-port RAM 128x8 bit (1Kbit) +// Core logic +//----------------------------- +module dpram_128x8_core ( + input wclk, + input wen, + input [0:6] waddr, + input [0:7] data_in, + input rclk, + input ren, + input [0:6] raddr, + output [0:7] data_out ); + + reg [0:7] ram[0:127]; + reg [0:7] internal; + + assign data_out = internal; + + always @(posedge wclk) begin + if(wen) begin + ram[waddr] <= data_in; + end + end + + always @(posedge rclk) begin + if(ren) begin + internal <= ram[raddr]; + end + end + +endmodule + +//----------------------------- +// Dual-port RAM 128x8 bit (1Kbit) wrapper +// where the read clock and write clock +// are combined to a unified clock +//----------------------------- +module dpram_128x8 ( + input clk, + input wen, + input ren, + input [0:6] waddr, + input [0:6] raddr, + input [0:7] data_in, + output [0:7] data_out ); + + dpram_128x8_core memory_0 ( + .wclk (clk), + .wen (wen), + .waddr (waddr), + .data_in (data_in), + .rclk (clk), + .ren (ren), + .raddr (raddr), + .data_out (data_out) ); + +endmodule + +//----------------------------- +// 18-bit multiplier +//----------------------------- +module mult_18( + input [0:17] A, + input [0:17] B, + output [0:35] Y +); + +assign Y = A * B; + +endmodule + +//----------------------------- +// Native D-type flip-flop +//----------------------------- +(* abc9_flop, lib_whitebox *) +module dff( + output reg Q, + input D, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C) + Q <= D; + 1'b1: + always @(negedge C) + Q <= D; + endcase +endmodule + +//----------------------------- +// D-type flip-flop with active-high asynchronous reset +//----------------------------- +(* abc9_flop, lib_whitebox *) +module dffr( + output reg Q, + input D, + input R, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C or posedge R) + if (R == 1'b1) + Q <= 1'b0; + else + Q <= D; + 1'b1: + always @(negedge C or posedge R) + if (R == 1'b1) + Q <= 1'b0; + else + Q <= D; + endcase +endmodule + +//----------------------------- +// D-type flip-flop with active-high asynchronous set +//----------------------------- +(* abc9_flop, lib_whitebox *) +module dffs( + output reg Q, + input D, + input S, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C or posedge S) + if (S == 1'b1) + Q <= 1'b1; + else + Q <= D; + 1'b1: + always @(negedge C or posedge S) + if (S == 1'b1) + Q <= 1'b1; + else + Q <= D; + endcase +endmodule + +//----------------------------- +// D-type flip-flop with active-low asynchronous reset +//----------------------------- +(* abc9_flop, lib_whitebox *) +module dffrn( + output reg Q, + input D, + input RN, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C or negedge RN) + if (RN == 1'b0) + Q <= 1'b0; + else + Q <= D; + 1'b1: + always @(negedge C or negedge RN) + if (RN == 1'b0) + Q <= 1'b0; + else + Q <= D; + endcase +endmodule + +//----------------------------- +// D-type flip-flop with active-low asynchronous set +//----------------------------- +(* abc9_flop, lib_whitebox *) +module dffsn( + output reg Q, + input D, + input SN, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C or negedge SN) + if (SN == 1'b0) + Q <= 1'b1; + else + Q <= D; + 1'b1: + always @(negedge C or negedge SN) + if (SN == 1'b0) + Q <= 1'b1; + else + Q <= D; + endcase +endmodule + diff --git a/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_40nm_dff_map.v b/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_40nm_dff_map.v new file mode 100644 index 0000000000..f8eed8db05 --- /dev/null +++ b/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_40nm_dff_map.v @@ -0,0 +1,48 @@ +// Basic DFF +module \$_DFF_P_ (D, C, Q); + input D; + input C; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + dff _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C)); +endmodule + +// Async active-high reset +module \$_DFF_PP0_ (D, C, R, Q); + input D; + input C; + input R; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + dffr _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .R(R)); +endmodule + +// Async active-high set +module \$_DFF_PP1_ (D, C, R, Q); + input D; + input C; + input R; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + dffs _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .S(R)); +endmodule + +// Async active-low reset +module \$_DFF_PN0_ (D, C, R, Q); + input D; + input C; + input R; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + dffrn _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .RN(R)); +endmodule + +// Async active-low set +module \$_DFF_PN1_ (D, C, R, Q); + input D; + input C; + input R; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + dffsn _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .SN(R)); +endmodule diff --git a/openfpga_flow/tasks/skywater_openfpga_task b/openfpga_flow/tasks/skywater_openfpga_task new file mode 120000 index 0000000000..4fd3973876 --- /dev/null +++ b/openfpga_flow/tasks/skywater_openfpga_task @@ -0,0 +1 @@ +/home/apond/sofa/SCRIPT/skywater_openfpga_task \ No newline at end of file From 1409b3e855bee2d05479b3bbeade4f1df3efc917 Mon Sep 17 00:00:00 2001 From: Andrew Pond Date: Tue, 6 Jul 2021 12:25:51 -0600 Subject: [PATCH 02/22] pmux2mux.v path change --- openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_dff_flow.ys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_dff_flow.ys b/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_dff_flow.ys index 695ad4190c..81b1e21ffa 100644 --- a/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_dff_flow.ys +++ b/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_dff_flow.ys @@ -78,7 +78,7 @@ opt -undriven -fine ######################### # Map muxes to pmuxes ######################### -techmap -map pmux2mux.v +techmap -map +/pmux2mux.v ######################### # Map flip-flops From 6445507ddf50c345945b42ce1999f60c523c851a Mon Sep 17 00:00:00 2001 From: Andrew Pond Date: Tue, 6 Jul 2021 14:19:28 -0600 Subject: [PATCH 03/22] pmux2mux yosys script change --- openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_flow.ys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_flow.ys b/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_flow.ys index 6b4830235c..d0ff395b63 100644 --- a/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_flow.ys +++ b/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_flow.ys @@ -78,7 +78,7 @@ opt -undriven -fine ######################### # Map muxes to pmuxes ######################### -techmap -map pmux2mux.v +techmap -map +/pmux2mux.v ######################### # Map flip-flops From a9755c4dec37c3d41cf364a70bdff44b34c74569 Mon Sep 17 00:00:00 2001 From: Andrew Pond Date: Fri, 16 Jul 2021 09:09:25 -0600 Subject: [PATCH 04/22] started modifying arch files --- ...rac_N4_adder_mem1K_dsp18_40nm_openfpga.xml | 253 ++++ ...1K_dsp18_fracff_skywater130nm_openfpga.xml | 333 +++++ ...ite_full_testbench_example_script.openfpga | 4 +- ...chain_dpram1K_dsp18_fracff_40nm_cell_sim.v | 14 +- ...rac_N4_tileable_adder_mem1K_dsp18_40nm.xml | 620 +++++++++ ...ain_dpram1K_dsp18_fracff_skywater130nm.xml | 1223 +++++++++++++++++ 6 files changed, 2438 insertions(+), 9 deletions(-) create mode 100644 openfpga_flow/openfpga_arch/k4_frac_N4_adder_mem1K_dsp18_40nm_openfpga.xml create mode 100644 openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dpram1K_dsp18_fracff_skywater130nm_openfpga.xml create mode 100644 openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_mem1K_dsp18_40nm.xml create mode 100644 openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm.xml diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_mem1K_dsp18_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_mem1K_dsp18_40nm_openfpga.xml new file mode 100644 index 0000000000..cd12856c52 --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_mem1K_dsp18_40nm_openfpga.xml @@ -0,0 +1,253 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + 10e-12 5e-12 + + + 10e-12 5e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dpram1K_dsp18_fracff_skywater130nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dpram1K_dsp18_fracff_skywater130nm_openfpga.xml new file mode 100644 index 0000000000..e9a81bfd87 --- /dev/null +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dpram1K_dsp18_fracff_skywater130nm_openfpga.xml @@ -0,0 +1,333 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + 10e-12 5e-12 + + + 10e-12 5e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga index 612249a156..5c155b5b95 100644 --- a/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga @@ -1,6 +1,6 @@ # Run VPR for the 'and' design #--write_rr_graph example_rr_graph.xml -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route ${OPENFPGA_VPR_DEVICE_LAYOUT} +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --device ${OPENFPGA_VPR_DEVICE_LAYOUT} # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} @@ -10,7 +10,7 @@ read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} # Annotate the OpenFPGA architecture to VPR data base # to debug use --verbose options -link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges +link_openfpga_arch --sort_gsb_chan_node_in_edges # Check and correct any naming conflicts in the BLIF netlist check_netlist_naming_conflict --fix --report ./netlist_renaming.xml diff --git a/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_40nm_cell_sim.v b/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_40nm_cell_sim.v index 9a5dfd26e6..6491d7870f 100644 --- a/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_40nm_cell_sim.v +++ b/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_40nm_cell_sim.v @@ -60,15 +60,15 @@ endmodule //----------------------------- // 18-bit multiplier //----------------------------- -module mult_18( - input [0:17] A, - input [0:17] B, - output [0:35] Y -); +// module mult_18( +// input [0:17] A, +// input [0:17] B, +// output [0:35] Y +// ); -assign Y = A * B; +// assign Y = A * B; -endmodule +// endmodule //----------------------------- // Native D-type flip-flop diff --git a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_mem1K_dsp18_40nm.xml b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_mem1K_dsp18_40nm.xml new file mode 100644 index 0000000000..5351486bcf --- /dev/null +++ b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_mem1K_dsp18_40nm.xml @@ -0,0 +1,620 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 1 1 1 + 1 1 1 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 235e-12 + 235e-12 + 235e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 261e-12 + 261e-12 + 261e-12 + 261e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm.xml new file mode 100644 index 0000000000..0816800260 --- /dev/null +++ b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm.xml @@ -0,0 +1,1223 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + + + + + + + + + + + + + + + + + + + + + + + + clb.clk clb.reset clb.set + clb.cin + clb.O[9:0] clb.I[19:0] + clb.cout clb.O[19:10] clb.I[39:20] + + + + + + + + + + + + + + + + + + + memory.clk + + memory.waddr[4:0] memory.raddr[4:0] memory.data_in[3:0] memory.wen memory.data_out[3:0] + memory.waddr[9:5] memory.raddr[9:5] memory.data_in[7:4] memory.ren memory.data_out[7:4] + + + + + + + + + + + + + + mult_18.b[0:4] mult_18.b[5:17] mult_18.out[18:35] + + mult_18.a[0:4] mult_18.a[5:17] mult_18.out[0:17] + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 1 1 1 + 1 1 1 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 235e-12 + 235e-12 + 235e-12 + 235e-12 + 235e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 195e-12 + 195e-12 + 195e-12 + 195e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 261e-12 + 261e-12 + 261e-12 + 261e-12 + 261e-12 + 261e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + From afea5bb44ca33817515d8d6bba2162f72a87b3a1 Mon Sep 17 00:00:00 2001 From: Andrew Pond Date: Mon, 19 Jul 2021 10:48:55 -0600 Subject: [PATCH 05/22] started updating timings --- .../ys_tmpl_yosys_vpr_dsp_dff_flow - Copy.ys | 96 ++ ...in_dsp18_fracff_skywater130nm_openfpga.xml | 317 +++++ ...1K_dsp18_fracff_skywater130nm_openfpga.xml | 300 +++++ .../skywater130nm.yml | 26 + ..._sim.v => dpram1K_dsp18_fracff_cell_sim.v} | 14 +- .../openfpga_yosys_techlib/dsp18_map.v | 17 - .../openfpga_yosys_techlib/dsp_map.v | 41 + ...am1K_dsp18_fracff_skywater130nm_dff_map.v} | 0 ...able_adder_chain_skywater130nm_cell_sim.v} | 0 ...ain_mem1K_40nm_bram.txt => mem1K_bram.txt} | 0 ...mem1K_40nm_bram_map.v => mem1K_bram_map.v} | 0 ...adder_chain_dsp18_fracff_skywater130nm.xml | 1123 +++++++++++++++++ ...ain_dpram1K_dsp18_fracff_skywater130nm.xml | 975 ++++++++++++++ 13 files changed, 2885 insertions(+), 24 deletions(-) create mode 100644 openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_dff_flow - Copy.ys create mode 100644 openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dsp18_fracff_skywater130nm_openfpga.xml create mode 100644 openfpga_flow/openfpga_arch/k6_frac_N10_chain_dpram1K_dsp18_fracff_skywater130nm_openfpga.xml create mode 100644 openfpga_flow/openfpga_timing_annotation/skywater130nm.yml rename openfpga_flow/openfpga_yosys_techlib/{k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_40nm_cell_sim.v => dpram1K_dsp18_fracff_cell_sim.v} (97%) delete mode 100644 openfpga_flow/openfpga_yosys_techlib/dsp18_map.v create mode 100644 openfpga_flow/openfpga_yosys_techlib/dsp_map.v rename openfpga_flow/openfpga_yosys_techlib/{k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_40nm_dff_map.v => k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm_dff_map.v} (100%) rename openfpga_flow/openfpga_yosys_techlib/{k6_frac_N10_tileable_adder_chain_mem1K_40nm_cell_sim.v => k6_frac_N10_tileable_adder_chain_skywater130nm_cell_sim.v} (100%) rename openfpga_flow/openfpga_yosys_techlib/{k6_frac_N10_tileable_adder_chain_mem1K_40nm_bram.txt => mem1K_bram.txt} (100%) rename openfpga_flow/openfpga_yosys_techlib/{k6_frac_N10_tileable_adder_chain_mem1K_40nm_bram_map.v => mem1K_bram_map.v} (100%) create mode 100644 openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dsp18_fracff_skywater130nm.xml create mode 100644 openfpga_flow/vpr_arch/k6_frac_N10_tileable_chain_dpram1K_dsp18_fracff_skywater130nm.xml diff --git a/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_dff_flow - Copy.ys b/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_dff_flow - Copy.ys new file mode 100644 index 0000000000..5697352c8f --- /dev/null +++ b/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_dff_flow - Copy.ys @@ -0,0 +1,96 @@ +# Yosys synthesis script for ${TOP_MODULE} + +######################### +# Parse input files +######################### +# Read verilog files +${READ_VERILOG_FILE} +# Read technology library +read_verilog -lib -specify ${YOSYS_CELL_SIM_VERILOG} + +######################### +# Prepare for synthesis +######################### +# Identify top module from hierarchy +hierarchy -check -top ${TOP_MODULE} +# - Convert process blocks to AST +proc +# Flatten all the gates/primitives +flatten +# Identify tri-state buffers from 'z' signal in AST +# with follow-up optimizations to clean up AST +tribuf -logic +opt_expr +opt_clean +# demote inout ports to input or output port +# with follow-up optimizations to clean up AST +deminout +opt + +opt_expr +opt_clean +check +opt +wreduce -keepdc +peepopt +pmuxtree +opt_clean + +######################## +# Map multipliers +# Inspired from synth_xilinx.cc +######################### +# Avoid merging any registers into DSP, reserve memory port registers first +memory_dff +wreduce t:$mul +techmap -map +/mul2dsp.v -map ${YOSYS_DSP_MAP_VERILOG} ${YOSYS_DSP_MAP_PARAMETERS} +select a:mul2dsp +setattr -unset mul2dsp +opt_expr -fine +wreduce +select -clear +chtype -set $mul t:$__soft_mul# Extract arithmetic functions + +######################### +# Run coarse synthesis +######################### +# Run a tech map with default library +techmap +alumacc +share +opt +fsm +# Run a quick follow-up optimization to sweep out unused nets/signals +opt -fast +# Optimize any memory cells by merging share-able ports and collecting all the ports belonging to memorcy cells +memory -nomap +opt_clean + +######################### +# Map flip-flops +######################### +techmap -map ${YOSYS_DFF_MAP_VERILOG} +opt_expr -mux_undef +simplemap +opt_expr +opt_merge +opt_rmdff +opt_clean +opt + +######################### +# Map LUTs +######################### +abc -lut ${LUT_SIZE} + +######################### +# Check and show statisitics +######################### +hierarchy -check +stat + +######################### +# Output netlists +######################### +opt_clean -purge +write_blif ${OUTPUT_BLIF} diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dsp18_fracff_skywater130nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dsp18_fracff_skywater130nm_openfpga.xml new file mode 100644 index 0000000000..97fdacb1ad --- /dev/null +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_dsp18_fracff_skywater130nm_openfpga.xml @@ -0,0 +1,317 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + 10e-12 5e-12 + + + 10e-12 5e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_chain_dpram1K_dsp18_fracff_skywater130nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_chain_dpram1K_dsp18_fracff_skywater130nm_openfpga.xml new file mode 100644 index 0000000000..e2ec2a3a2f --- /dev/null +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_chain_dpram1K_dsp18_fracff_skywater130nm_openfpga.xml @@ -0,0 +1,300 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + 10e-12 5e-12 + + + 10e-12 5e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/openfpga_timing_annotation/skywater130nm.yml b/openfpga_flow/openfpga_timing_annotation/skywater130nm.yml new file mode 100644 index 0000000000..ab976c6bbe --- /dev/null +++ b/openfpga_flow/openfpga_timing_annotation/skywater130nm.yml @@ -0,0 +1,26 @@ +L1_SB_MUX_DELAY: 1.44e-9 +L2_SB_MUX_DELAY: 1.44e-9 +L4_SB_MUX_DELAY: 1.44e-9 +CB_MUX_DELAY: 1.38e-9 +L1_WIRE_R: 100 +L1_WIRE_C: 1e-12 +L2_WIRE_R: 100 +L2_WIRE_C: 1e-12 +L4_WIRE_R: 100 +L4_WIRE_C: 1e-12 +INPAD_DELAY: 0.11e-9 +OUTPAD_DELAY: 0.11e-9 +FF_T_SETUP: 0.39e-9 +FF_T_CLK2Q: 0.43e-9 +LUT_OUT0_TO_FF_D_DELAY: 1.14e-9 +LUT_OUT1_TO_FF_D_DELAY: 0.56e-9 +LUT_OUT0_TO_FLE_OUT_DELAY: 0.89e-9 +FF0_Q_TO_FLE_OUT_DELAY: 0.88e-9 +LUT_OUT1_TO_FLE_OUT_DELAY: 0.78e-9 +FF1_Q_TO_FLE_OUT_DELAY: 0.89e-9 +LUT3_DELAY: 0.92e-9 +LUT3_OUT_TO_FLE_OUT_DELAY: 1.44e-9 +LUT4_DELAY: 1.21e-9 +LUT4_OUT_TO_FLE_OUT_DELAY: 1.46e-9 +REGIN_TO_FF0_DELAY: 1.12e-9 +FF0_TO_FF1_DELAY: 0.56e-9 \ No newline at end of file diff --git a/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_40nm_cell_sim.v b/openfpga_flow/openfpga_yosys_techlib/dpram1K_dsp18_fracff_cell_sim.v similarity index 97% rename from openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_40nm_cell_sim.v rename to openfpga_flow/openfpga_yosys_techlib/dpram1K_dsp18_fracff_cell_sim.v index 6491d7870f..9a5dfd26e6 100644 --- a/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_40nm_cell_sim.v +++ b/openfpga_flow/openfpga_yosys_techlib/dpram1K_dsp18_fracff_cell_sim.v @@ -60,15 +60,15 @@ endmodule //----------------------------- // 18-bit multiplier //----------------------------- -// module mult_18( -// input [0:17] A, -// input [0:17] B, -// output [0:35] Y -// ); +module mult_18( + input [0:17] A, + input [0:17] B, + output [0:35] Y +); -// assign Y = A * B; +assign Y = A * B; -// endmodule +endmodule //----------------------------- // Native D-type flip-flop diff --git a/openfpga_flow/openfpga_yosys_techlib/dsp18_map.v b/openfpga_flow/openfpga_yosys_techlib/dsp18_map.v deleted file mode 100644 index e44a983345..0000000000 --- a/openfpga_flow/openfpga_yosys_techlib/dsp18_map.v +++ /dev/null @@ -1,17 +0,0 @@ -module mult_18x18 ( - input [0:17] A, - input [0:17] B, - output [0:35] Y -); - parameter A_SIGNED = 0; - parameter B_SIGNED = 0; - parameter A_WIDTH = 0; - parameter B_WIDTH = 0; - parameter Y_WIDTH = 0; - - mult_18 #() _TECHMAP_REPLACE_ ( - .A (A), - .B (B), - .Y (Y) ); - -endmodule diff --git a/openfpga_flow/openfpga_yosys_techlib/dsp_map.v b/openfpga_flow/openfpga_yosys_techlib/dsp_map.v new file mode 100644 index 0000000000..2ec30fccc5 --- /dev/null +++ b/openfpga_flow/openfpga_yosys_techlib/dsp_map.v @@ -0,0 +1,41 @@ +//----------------------------- +// 9-bit multiplier +//----------------------------- +module mult_9x9 ( + input [0:8] A, + input [0:8] B, + output [0:17] Y +); + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + parameter A_WIDTH = 0; + parameter B_WIDTH = 0; + parameter Y_WIDTH = 0; + + mult_9 #() _TECHMAP_REPLACE_ ( + .A (A), + .B (B), + .Y (Y) ); + +endmodule + +//----------------------------- +// 18-bit multiplier +//----------------------------- +module mult_18x18 ( + input [0:17] A, + input [0:17] B, + output [0:35] Y +); + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + parameter A_WIDTH = 0; + parameter B_WIDTH = 0; + parameter Y_WIDTH = 0; + + mult_18 #() _TECHMAP_REPLACE_ ( + .A (A), + .B (B), + .Y (Y) ); + +endmodule diff --git a/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_40nm_dff_map.v b/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm_dff_map.v similarity index 100% rename from openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_40nm_dff_map.v rename to openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm_dff_map.v diff --git a/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem1K_40nm_cell_sim.v b/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_skywater130nm_cell_sim.v similarity index 100% rename from openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem1K_40nm_cell_sim.v rename to openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_skywater130nm_cell_sim.v diff --git a/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem1K_40nm_bram.txt b/openfpga_flow/openfpga_yosys_techlib/mem1K_bram.txt similarity index 100% rename from openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem1K_40nm_bram.txt rename to openfpga_flow/openfpga_yosys_techlib/mem1K_bram.txt diff --git a/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem1K_40nm_bram_map.v b/openfpga_flow/openfpga_yosys_techlib/mem1K_bram_map.v similarity index 100% rename from openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem1K_40nm_bram_map.v rename to openfpga_flow/openfpga_yosys_techlib/mem1K_bram_map.v diff --git a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dsp18_fracff_skywater130nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dsp18_fracff_skywater130nm.xml new file mode 100644 index 0000000000..8f70260b00 --- /dev/null +++ b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dsp18_fracff_skywater130nm.xml @@ -0,0 +1,1123 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + + + + + + + + + + + + + + + + + + + + + + + + clb.clk clb.reset clb.set + clb.cin + clb.O[9:0] clb.I[19:0] + clb.cout clb.O[19:10] clb.I[39:20] + + + + + + + + + + + + + + mult_18.b[0:4] mult_18.b[5:17] mult_18.out[18:35] + + mult_18.a[0:4] mult_18.a[5:17] mult_18.out[0:17] + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 1 1 1 + 1 1 1 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 235e-12 + 235e-12 + 235e-12 + 235e-12 + 235e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 195e-12 + 195e-12 + 195e-12 + 195e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 261e-12 + 261e-12 + 261e-12 + 261e-12 + 261e-12 + 261e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_chain_dpram1K_dsp18_fracff_skywater130nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_chain_dpram1K_dsp18_fracff_skywater130nm.xml new file mode 100644 index 0000000000..0009de0c31 --- /dev/null +++ b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_chain_dpram1K_dsp18_fracff_skywater130nm.xml @@ -0,0 +1,975 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + + + + + + + + + + + + + + + + + + + + clb.clk clb.reset clb.set + clb.O[9:0] clb.I[19:0] + clb.O[19:10] clb.I[39:20] + + + + + + + + + + + + + + + + + + + memory.clk + + memory.waddr[4:0] memory.raddr[4:0] memory.data_in[3:0] memory.wen memory.data_out[3:0] + memory.waddr[9:5] memory.raddr[9:5] memory.data_in[7:4] memory.ren memory.data_out[7:4] + + + + + + + + + + + + + + mult_18.b[0:4] mult_18.b[5:17] mult_18.out[18:35] + + mult_18.a[0:4] mult_18.a[5:17] mult_18.out[0:17] + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 1 1 1 + 1 1 1 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 235e-12 + 235e-12 + 235e-12 + 235e-12 + 235e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 261e-12 + 261e-12 + 261e-12 + 261e-12 + 261e-12 + 261e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + From 805053f4be65816049c523cae3a70c6c5a2e965e Mon Sep 17 00:00:00 2001 From: Andrew Pond Date: Tue, 20 Jul 2021 11:45:35 -0600 Subject: [PATCH 06/22] created timing annotation file --- .../skywater130nm.yml | 65 ++++- ...ain_dpram1K_dsp18_fracff_skywater130nm.xml | 226 +++++++++--------- ...ain_dpram1K_dsp18_fracff_skywater130nm.xml | 156 ++++++------ 3 files changed, 255 insertions(+), 192 deletions(-) diff --git a/openfpga_flow/openfpga_timing_annotation/skywater130nm.yml b/openfpga_flow/openfpga_timing_annotation/skywater130nm.yml index ab976c6bbe..31061e930c 100644 --- a/openfpga_flow/openfpga_timing_annotation/skywater130nm.yml +++ b/openfpga_flow/openfpga_timing_annotation/skywater130nm.yml @@ -22,5 +22,68 @@ LUT3_DELAY: 0.92e-9 LUT3_OUT_TO_FLE_OUT_DELAY: 1.44e-9 LUT4_DELAY: 1.21e-9 LUT4_OUT_TO_FLE_OUT_DELAY: 1.46e-9 +LUT5_DELAY: 235e-12 # LUT5_DELAY NOT ACCURATE +LUT5_OUT_TO_FLE_OUT_DELAY: 25e-12 # LUT5_OUT_TO_FLE_OUT_DELAY NOT ACCURATE +LUT6_DELAY: 235e-12 # LUT6_DELAY NOT ACCURATE +LUT6_OUT_TO_FLE_OUT_DELAY: 25e-12 # LUT6_OUT_TO_FLE_OUT_DELAY NOT ACCURATE REGIN_TO_FF0_DELAY: 1.12e-9 -FF0_TO_FF1_DELAY: 0.56e-9 \ No newline at end of file +FF0_TO_FF1_DELAY: 0.56e-9 + +CROSSBAR_I_TO_FLE_IN_DELAY: 95e-12 # CROSSBAR_I_TO_FLE_IN_DELAY NOT ACCURATE +CROSSBAR_FLE_OUT_TO_FLE_IN_DELAY: 95e-12 # FLE_OUT_TO_FLE_IN_DELAY NOT ACCURATE + +CLB_CIN_TO_FLE_CIN: 0.16e-9 # CLB_CIN_TO_FLE_CIN NOT ACCURATE + + + +################# Adder Delays ################# + +ADDER_LUT4_CIN2OUT_DELAY: 1.21e-9 +ADDER_LUT4_CIN2COUT_DELAY: 1.21e-9 +ADDER_LUT4_IN2OUT_DELAY: 1.21e-9 +ADDER_LUT4_IN2COUT_DELAY: 1.21e-9 + +ARITHMETIC_ADDER_OUT_TO_ARITHMETIC_OUT: 25e-12 +ARITHMETIC_FF_OUT_TO_ARITHMETIC_OUT: 45e-12 + + + +################# MULT9 Delays ################# + +MULT9_A2Y_DELAY_MAX: 1.523e-9 +MULT9_A2Y_DELAY_MIN: 0.776e-9 +MULT9_B2Y_DELAY_MAX: 1.523e-9 +MULT9_B2Y_DELAY_MIN: 0.776e-9 + + + +################# MULT18 Delays ################# + +MULT18_A2Y_DELAY_MAX: 1.523e-9 +MULT18_A2Y_DELAY_MIN: 0.776e-9 +MULT18_B2Y_DELAY_MAX: 1.523e-9 +MULT18_B2Y_DELAY_MIN: 0.776e-9 +MULT18_SLICE_A2A_DELAY_MAX: 134e-12 # MULT18_SLICE_A2A_DELAY_MAX NOT ACCURATE +MULT18_SLICE_A2A_DELAY_MIN: 74e-12 # MULT18_SLICE_A2A_DELAY_MIN NOT ACCURATE +MULT18_SLICE_B2B_DELAY_MAX: 134e-12 # MULT18_SLICE_B2B_DELAY_MAX NOT ACCURATE +MULT18_SLICE_B2B_DELAY_MIN: 74e-12 # MULT18_SLICE_B2B_DELAY_MIN NOT ACCURATE +MULT18_SLICE_OUT2OUT_DELAY_MAX: 1.93e-9 # MULT18_SLICE_OUT2OUT_DELAY_MAX NOT ACCURATE +MULT18_SLICE_OUT2OUT_DELAY_MIN: 74e-12 # MULT18_SLICE_OUT2OUT_DELAY_MIN NOT ACCURATE + + + +################# BRAM Delays ################# + +DPRAM_128x8_CLK_TO_WADDR_DELAY: 509e-12 +DPRAM_128x8_CLK_TO_RADDR_DELAY: 509e-12 +DPRAM_128x8_CLK_TO_DATA_IN_DELAY: 509e-12 +DPRAM_128x8_CLK_TO_WEN_DELAY: 509e-12 +DPRAM_128x8_CLK_TO_REN_DELAY: 509e-12 +DPRAM_128x8_CLK_TO_DATA_OUT_DELAY: 1.234e-9 + +MEMORY_WADDR_TO_BRAM_WADDR_DELAY: 132e-12 +MEMORY_RADDR_TO_BRAM_RADDR_DELAY: 132e-12 +MEMORY_DATA_IN_TO_BRAM_DATA_IN_DELAY: 132e-12 +MEMORY_WEN_TO_BRAM_WEN_DELAY: 132e-12 +MEMORY_REN_TO_BRAM_REN_DELAY: 132e-12 +BRAM_DATA_OUT_TO_MEMORY_DATA_OUT_DELAY: 40e-12 \ No newline at end of file diff --git a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm.xml index 0816800260..a967f67a31 100644 --- a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm.xml +++ b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm.xml @@ -399,10 +399,10 @@ - + - + @@ -418,7 +418,7 @@ - + @@ -428,7 +428,7 @@ - + @@ -507,10 +507,10 @@ - - - - + + + + @@ -519,12 +519,12 @@ - - - - - - + + + + + + @@ -541,13 +541,13 @@ - - + + - - + + @@ -584,11 +584,11 @@ 398e-12 --> - 235e-12 - 235e-12 - 235e-12 - 235e-12 - 235e-12 + ${LUT5_DELAY} + ${LUT5_DELAY} + ${LUT5_DELAY} + ${LUT5_DELAY} + ${LUT5_DELAY} @@ -603,8 +603,8 @@ - - + + @@ -617,8 +617,8 @@ - - + + @@ -632,9 +632,9 @@ - - - + + + @@ -649,9 +649,9 @@ - - - + + + @@ -666,9 +666,9 @@ - - - + + + @@ -683,9 +683,9 @@ - - - + + + @@ -704,8 +704,8 @@ - - + + @@ -742,10 +742,10 @@ 263e-12 --> - 195e-12 - 195e-12 - 195e-12 - 195e-12 + ${LUT4_DELAY} + ${LUT4_DELAY} + ${LUT4_DELAY} + ${LUT4_DELAY} @@ -754,12 +754,12 @@ - - - - - - + + + + + + @@ -773,8 +773,8 @@ - - + + @@ -787,8 +787,8 @@ - - + + @@ -802,9 +802,9 @@ - - - + + + @@ -819,9 +819,9 @@ - - - + + + @@ -836,9 +836,9 @@ - - - + + + @@ -853,9 +853,9 @@ - - - + + + @@ -885,8 +885,8 @@ - - + + @@ -930,12 +930,12 @@ 397e-12 --> - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 + ${LUT6_DELAY} + ${LUT6_DELAY} + ${LUT6_DELAY} + ${LUT6_DELAY} + ${LUT6_DELAY} + ${LUT6_DELAY} @@ -950,8 +950,8 @@ - - + + @@ -964,8 +964,8 @@ - - + + @@ -979,9 +979,9 @@ - - - + + + @@ -996,9 +996,9 @@ - - - + + + @@ -1013,9 +1013,9 @@ - - - + + + @@ -1030,9 +1030,9 @@ - - - + + + @@ -1051,8 +1051,8 @@ - - + + @@ -1077,8 +1077,8 @@ 25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback to get the part that should be marked on the crossbar. --> - - + + @@ -1097,7 +1097,7 @@ - + @@ -1123,8 +1123,8 @@ - - + + @@ -1147,13 +1147,13 @@ The interconnect difference for DSP blocks is 0.5523, which leads to a minimum delay of 74 ps --> - + - + - + @@ -1183,12 +1183,12 @@ - - - - - - + + + + + + @@ -1196,22 +1196,22 @@ - + - + - + - + - + - + diff --git a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_chain_dpram1K_dsp18_fracff_skywater130nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_chain_dpram1K_dsp18_fracff_skywater130nm.xml index 0009de0c31..cdec844f13 100644 --- a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_chain_dpram1K_dsp18_fracff_skywater130nm.xml +++ b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_chain_dpram1K_dsp18_fracff_skywater130nm.xml @@ -380,10 +380,10 @@ - + - + @@ -399,7 +399,7 @@ - + @@ -409,7 +409,7 @@ - + @@ -482,10 +482,10 @@ - - - - + + + + @@ -495,13 +495,13 @@ - - + + - - + + @@ -536,11 +536,11 @@ 398e-12 --> - 235e-12 - 235e-12 - 235e-12 - 235e-12 - 235e-12 + ${LUT5_DELAY} + ${LUT5_DELAY} + ${LUT5_DELAY} + ${LUT5_DELAY} + ${LUT5_DELAY} @@ -555,8 +555,8 @@ - - + + @@ -569,8 +569,8 @@ - - + + @@ -584,9 +584,9 @@ - - - + + + @@ -601,9 +601,9 @@ - - - + + + @@ -618,9 +618,9 @@ - - - + + + @@ -635,9 +635,9 @@ - - - + + + @@ -656,8 +656,8 @@ - - + + @@ -694,12 +694,12 @@ 397e-12 --> - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 + ${LUT6_DELAY} + ${LUT6_DELAY} + ${LUT6_DELAY} + ${LUT6_DELAY} + ${LUT6_DELAY} + ${LUT6_DELAY} @@ -714,8 +714,8 @@ - - + + @@ -728,8 +728,8 @@ - - + + @@ -743,9 +743,9 @@ - - - + + + @@ -760,9 +760,9 @@ - - - + + + @@ -777,9 +777,9 @@ - - - + + + @@ -794,9 +794,9 @@ - - - + + + @@ -815,8 +815,8 @@ - - + + @@ -841,8 +841,8 @@ 25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback to get the part that should be marked on the crossbar. --> - - + + @@ -875,8 +875,8 @@ - - + + @@ -899,13 +899,13 @@ The interconnect difference for DSP blocks is 0.5523, which leads to a minimum delay of 74 ps --> - + - + - + @@ -935,12 +935,12 @@ - - - - - - + + + + + + @@ -948,22 +948,22 @@ - + - + - + - + - + - + From 60ac09d315e6f47c79a1776be031fb91e9b83acb Mon Sep 17 00:00:00 2001 From: Andrew Pond Date: Wed, 21 Jul 2021 08:09:20 -0600 Subject: [PATCH 07/22] removed duplicate yosys script --- ...dff_flow - Copy.ys => ys_tmpl_yosys_vpr_dsp_dff_flow.ys} | 6 ++++++ 1 file changed, 6 insertions(+) rename openfpga_flow/misc/{ys_tmpl_yosys_vpr_dsp_dff_flow - Copy.ys => ys_tmpl_yosys_vpr_dsp_dff_flow.ys} (95%) diff --git a/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_dff_flow - Copy.ys b/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_dff_flow.ys similarity index 95% rename from openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_dff_flow - Copy.ys rename to openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_dff_flow.ys index 5697352c8f..e414466053 100644 --- a/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_dff_flow - Copy.ys +++ b/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_dff_flow.ys @@ -66,6 +66,12 @@ opt -fast memory -nomap opt_clean + +######################### +# Map muxes to pmuxes +######################### +techmap -map +/pmux2mux.v + ######################### # Map flip-flops ######################### From 6cb51d1e7d2fdd5446ea43668bc83aa8ce10ec45 Mon Sep 17 00:00:00 2001 From: Andrew Pond Date: Wed, 21 Jul 2021 14:12:32 -0600 Subject: [PATCH 08/22] timing files renamed --- .../misc/ys_tmpl_yosys_vpr_bram_dff_flow.ys | 102 +++ ...ain_dpram1K_dsp18_fracff_skywater130nm.yml | 62 ++ ...der_chain_dpram1K_fracff_skywater130nm.yml | 47 ++ ...adder_chain_dsp18_fracff_skywater130nm.yml | 44 ++ .../skywater130nm.yml | 8 +- ...ac_N4_tileable_adder_chain_mem1K_130nm.xml | 702 ++++++++++++++++++ ...ain_dpram1K_dsp18_fracff_skywater130nm.xml | 24 +- 7 files changed, 973 insertions(+), 16 deletions(-) create mode 100644 openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dff_flow.ys create mode 100644 openfpga_flow/openfpga_timing_annotation/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm.yml create mode 100644 openfpga_flow/openfpga_timing_annotation/k6_frac_N10_tileable_adder_chain_dpram1K_fracff_skywater130nm.yml create mode 100644 openfpga_flow/openfpga_timing_annotation/k6_frac_N10_tileable_adder_chain_dsp18_fracff_skywater130nm.yml create mode 100644 openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_mem1K_130nm.xml diff --git a/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dff_flow.ys b/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dff_flow.ys new file mode 100644 index 0000000000..cd7ff02b54 --- /dev/null +++ b/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dff_flow.ys @@ -0,0 +1,102 @@ +# Yosys synthesis script for ${TOP_MODULE} + +######################### +# Parse input files +######################### +# Read verilog files +${READ_VERILOG_FILE} +# Read technology library +read_verilog -lib -specify ${YOSYS_CELL_SIM_VERILOG} + +######################### +# Prepare for synthesis +######################### +# Identify top module from hierarchy +hierarchy -check -top ${TOP_MODULE} +# - Convert process blocks to AST +proc +# Flatten all the gates/primitives +flatten +# Identify tri-state buffers from 'z' signal in AST +# with follow-up optimizations to clean up AST +tribuf -logic +opt_expr +opt_clean +# demote inout ports to input or output port +# with follow-up optimizations to clean up AST +deminout +opt + +opt_expr +opt_clean +check +opt +wreduce -keepdc +peepopt +pmuxtree +opt_clean + +######################## +# Map multipliers +# Inspired from synth_xilinx.cc +######################### +# Avoid merging any registers into DSP, reserve memory port registers first +memory_dff + +######################### +# Run coarse synthesis +######################### +# Run a tech map with default library +techmap +alumacc +share +opt +fsm +# Run a quick follow-up optimization to sweep out unused nets/signals +opt -fast +# Optimize any memory cells by merging share-able ports and collecting all the ports belonging to memorcy cells +memory -nomap +opt_clean + +######################### +# Map logics to BRAMs +######################### +memory_bram -rules ${YOSYS_BRAM_MAP_RULES} +techmap -map ${YOSYS_BRAM_MAP_VERILOG} +opt -fast -mux_undef -undriven -fine +memory_map +opt -undriven -fine + +######################### +# Map pmuxes to muxes +######################### +techmap -map +/pmux2mux.v + +######################### +# Map flip-flops +######################### +techmap -map ${YOSYS_DFF_MAP_VERILOG} +opt_expr -mux_undef +simplemap +opt_expr +opt_merge +opt_rmdff +opt_clean +opt + +######################### +# Map LUTs +######################### +abc -lut ${LUT_SIZE} + +######################### +# Check and show statisitics +######################### +hierarchy -check +stat + +######################### +# Output netlists +######################### +opt_clean -purge +write_blif ${OUTPUT_BLIF} diff --git a/openfpga_flow/openfpga_timing_annotation/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm.yml b/openfpga_flow/openfpga_timing_annotation/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm.yml new file mode 100644 index 0000000000..95b36d41db --- /dev/null +++ b/openfpga_flow/openfpga_timing_annotation/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm.yml @@ -0,0 +1,62 @@ +INPAD_DELAY: 0.11e-9 +OUTPAD_DELAY: 0.11e-9 +FF_T_SETUP: 0.39e-9 +FF_T_CLK2Q: 0.43e-9 +LUT_OUT0_TO_FLE_OUT_DELAY: 0.89e-9 +FF0_Q_TO_FLE_OUT_DELAY: 0.88e-9 +LUT_OUT1_TO_FLE_OUT_DELAY: 0.78e-9 +FF1_Q_TO_FLE_OUT_DELAY: 0.89e-9 +LUT5_DELAY: 235e-12 # LUT5_DELAY NOT ACCURATE +LUT5_OUT_TO_FLE_OUT_DELAY: 25e-12 # LUT5_OUT_TO_FLE_OUT_DELAY NOT ACCURATE +LUT6_DELAY: 235e-12 # LUT6_DELAY NOT ACCURATE +LUT6_OUT_TO_FLE_OUT_DELAY: 25e-12 # LUT6_OUT_TO_FLE_OUT_DELAY NOT ACCURATE + +CROSSBAR_I_TO_FLE_IN_DELAY: 95e-12 # CROSSBAR_I_TO_FLE_IN_DELAY NOT ACCURATE +CROSSBAR_FLE_OUT_TO_FLE_IN_DELAY: 95e-12 # FLE_OUT_TO_FLE_IN_DELAY NOT ACCURATE + +CLB_CIN_TO_FLE_CIN: 0.16e-9 # CLB_CIN_TO_FLE_CIN NOT ACCURATE + + + +################# Adder Delays ################# + +ADDER_CIN2OUT_DELAY: 1.21e-9 +ADDER_CIN2COUT_DELAY: 1.21e-9 +ADDER_IN2OUT_DELAY: 1.21e-9 +ADDER_IN2COUT_DELAY: 1.21e-9 + +ARITHMETIC_ADDER_OUT_TO_ARITHMETIC_OUT: 25e-12 +ARITHMETIC_FF_OUT_TO_ARITHMETIC_OUT: 45e-12 + + + +################# MULT18 Delays ################# + +MULT18_A2Y_DELAY_MAX: 1.523e-9 +MULT18_A2Y_DELAY_MIN: 0.776e-9 +MULT18_B2Y_DELAY_MAX: 1.523e-9 +MULT18_B2Y_DELAY_MIN: 0.776e-9 +MULT18_SLICE_A2A_DELAY_MAX: 134e-12 # MULT18_SLICE_A2A_DELAY_MAX NOT ACCURATE +MULT18_SLICE_A2A_DELAY_MIN: 74e-12 # MULT18_SLICE_A2A_DELAY_MIN NOT ACCURATE +MULT18_SLICE_B2B_DELAY_MAX: 134e-12 # MULT18_SLICE_B2B_DELAY_MAX NOT ACCURATE +MULT18_SLICE_B2B_DELAY_MIN: 74e-12 # MULT18_SLICE_B2B_DELAY_MIN NOT ACCURATE +MULT18_SLICE_OUT2OUT_DELAY_MAX: 1.93e-9 # MULT18_SLICE_OUT2OUT_DELAY_MAX NOT ACCURATE +MULT18_SLICE_OUT2OUT_DELAY_MIN: 74e-12 # MULT18_SLICE_OUT2OUT_DELAY_MIN NOT ACCURATE + + + +################# BRAM Delays ################# + +DPRAM_128x8_CLK_TO_WADDR_DELAY: 509e-12 +DPRAM_128x8_CLK_TO_RADDR_DELAY: 509e-12 +DPRAM_128x8_CLK_TO_DATA_IN_DELAY: 509e-12 +DPRAM_128x8_CLK_TO_WEN_DELAY: 509e-12 +DPRAM_128x8_CLK_TO_REN_DELAY: 509e-12 +DPRAM_128x8_CLK_TO_DATA_OUT_DELAY: 1.234e-9 + +MEMORY_WADDR_TO_BRAM_WADDR_DELAY: 132e-12 +MEMORY_RADDR_TO_BRAM_RADDR_DELAY: 132e-12 +MEMORY_DATA_IN_TO_BRAM_DATA_IN_DELAY: 132e-12 +MEMORY_WEN_TO_BRAM_WEN_DELAY: 132e-12 +MEMORY_REN_TO_BRAM_REN_DELAY: 132e-12 +BRAM_DATA_OUT_TO_MEMORY_DATA_OUT_DELAY: 40e-12 \ No newline at end of file diff --git a/openfpga_flow/openfpga_timing_annotation/k6_frac_N10_tileable_adder_chain_dpram1K_fracff_skywater130nm.yml b/openfpga_flow/openfpga_timing_annotation/k6_frac_N10_tileable_adder_chain_dpram1K_fracff_skywater130nm.yml new file mode 100644 index 0000000000..4d1136b15d --- /dev/null +++ b/openfpga_flow/openfpga_timing_annotation/k6_frac_N10_tileable_adder_chain_dpram1K_fracff_skywater130nm.yml @@ -0,0 +1,47 @@ +INPAD_DELAY: 0.11e-9 +OUTPAD_DELAY: 0.11e-9 +FF_T_SETUP: 0.39e-9 +FF_T_CLK2Q: 0.43e-9 +LUT_OUT0_TO_FLE_OUT_DELAY: 0.89e-9 +FF0_Q_TO_FLE_OUT_DELAY: 0.88e-9 +LUT_OUT1_TO_FLE_OUT_DELAY: 0.78e-9 +FF1_Q_TO_FLE_OUT_DELAY: 0.89e-9 +LUT5_DELAY: 235e-12 # LUT5_DELAY NOT ACCURATE +LUT5_OUT_TO_FLE_OUT_DELAY: 25e-12 # LUT5_OUT_TO_FLE_OUT_DELAY NOT ACCURATE +LUT6_DELAY: 235e-12 # LUT6_DELAY NOT ACCURATE +LUT6_OUT_TO_FLE_OUT_DELAY: 25e-12 # LUT6_OUT_TO_FLE_OUT_DELAY NOT ACCURATE + +CROSSBAR_I_TO_FLE_IN_DELAY: 95e-12 # CROSSBAR_I_TO_FLE_IN_DELAY NOT ACCURATE +CROSSBAR_FLE_OUT_TO_FLE_IN_DELAY: 95e-12 # FLE_OUT_TO_FLE_IN_DELAY NOT ACCURATE + +CLB_CIN_TO_FLE_CIN: 0.16e-9 # CLB_CIN_TO_FLE_CIN NOT ACCURATE + + + +################# Adder Delays ################# + +ADDER_CIN2OUT_DELAY: 1.21e-9 +ADDER_CIN2COUT_DELAY: 1.21e-9 +ADDER_IN2OUT_DELAY: 1.21e-9 +ADDER_IN2COUT_DELAY: 1.21e-9 + +ARITHMETIC_ADDER_OUT_TO_ARITHMETIC_OUT: 25e-12 +ARITHMETIC_FF_OUT_TO_ARITHMETIC_OUT: 45e-12 + + + +################# BRAM Delays ################# + +DPRAM_128x8_CLK_TO_WADDR_DELAY: 509e-12 +DPRAM_128x8_CLK_TO_RADDR_DELAY: 509e-12 +DPRAM_128x8_CLK_TO_DATA_IN_DELAY: 509e-12 +DPRAM_128x8_CLK_TO_WEN_DELAY: 509e-12 +DPRAM_128x8_CLK_TO_REN_DELAY: 509e-12 +DPRAM_128x8_CLK_TO_DATA_OUT_DELAY: 1.234e-9 + +MEMORY_WADDR_TO_BRAM_WADDR_DELAY: 132e-12 +MEMORY_RADDR_TO_BRAM_RADDR_DELAY: 132e-12 +MEMORY_DATA_IN_TO_BRAM_DATA_IN_DELAY: 132e-12 +MEMORY_WEN_TO_BRAM_WEN_DELAY: 132e-12 +MEMORY_REN_TO_BRAM_REN_DELAY: 132e-12 +BRAM_DATA_OUT_TO_MEMORY_DATA_OUT_DELAY: 40e-12 \ No newline at end of file diff --git a/openfpga_flow/openfpga_timing_annotation/k6_frac_N10_tileable_adder_chain_dsp18_fracff_skywater130nm.yml b/openfpga_flow/openfpga_timing_annotation/k6_frac_N10_tileable_adder_chain_dsp18_fracff_skywater130nm.yml new file mode 100644 index 0000000000..a2af36f56a --- /dev/null +++ b/openfpga_flow/openfpga_timing_annotation/k6_frac_N10_tileable_adder_chain_dsp18_fracff_skywater130nm.yml @@ -0,0 +1,44 @@ +INPAD_DELAY: 0.11e-9 +OUTPAD_DELAY: 0.11e-9 +FF_T_SETUP: 0.39e-9 +FF_T_CLK2Q: 0.43e-9 +LUT_OUT0_TO_FLE_OUT_DELAY: 0.89e-9 +FF0_Q_TO_FLE_OUT_DELAY: 0.88e-9 +LUT_OUT1_TO_FLE_OUT_DELAY: 0.78e-9 +FF1_Q_TO_FLE_OUT_DELAY: 0.89e-9 +LUT5_DELAY: 235e-12 # LUT5_DELAY NOT ACCURATE +LUT5_OUT_TO_FLE_OUT_DELAY: 25e-12 # LUT5_OUT_TO_FLE_OUT_DELAY NOT ACCURATE +LUT6_DELAY: 235e-12 # LUT6_DELAY NOT ACCURATE +LUT6_OUT_TO_FLE_OUT_DELAY: 25e-12 # LUT6_OUT_TO_FLE_OUT_DELAY NOT ACCURATE + +CROSSBAR_I_TO_FLE_IN_DELAY: 95e-12 # CROSSBAR_I_TO_FLE_IN_DELAY NOT ACCURATE +CROSSBAR_FLE_OUT_TO_FLE_IN_DELAY: 95e-12 # FLE_OUT_TO_FLE_IN_DELAY NOT ACCURATE + +CLB_CIN_TO_FLE_CIN: 0.16e-9 # CLB_CIN_TO_FLE_CIN NOT ACCURATE + + + +################# Adder Delays ################# + +ADDER_CIN2OUT_DELAY: 1.21e-9 +ADDER_CIN2COUT_DELAY: 1.21e-9 +ADDER_IN2OUT_DELAY: 1.21e-9 +ADDER_IN2COUT_DELAY: 1.21e-9 + +ARITHMETIC_ADDER_OUT_TO_ARITHMETIC_OUT: 25e-12 +ARITHMETIC_FF_OUT_TO_ARITHMETIC_OUT: 45e-12 + + + +################# MULT18 Delays ################# + +MULT18_A2Y_DELAY_MAX: 1.523e-9 +MULT18_A2Y_DELAY_MIN: 0.776e-9 +MULT18_B2Y_DELAY_MAX: 1.523e-9 +MULT18_B2Y_DELAY_MIN: 0.776e-9 +MULT18_SLICE_A2A_DELAY_MAX: 134e-12 # MULT18_SLICE_A2A_DELAY_MAX NOT ACCURATE +MULT18_SLICE_A2A_DELAY_MIN: 74e-12 # MULT18_SLICE_A2A_DELAY_MIN NOT ACCURATE +MULT18_SLICE_B2B_DELAY_MAX: 134e-12 # MULT18_SLICE_B2B_DELAY_MAX NOT ACCURATE +MULT18_SLICE_B2B_DELAY_MIN: 74e-12 # MULT18_SLICE_B2B_DELAY_MIN NOT ACCURATE +MULT18_SLICE_OUT2OUT_DELAY_MAX: 1.93e-9 # MULT18_SLICE_OUT2OUT_DELAY_MAX NOT ACCURATE +MULT18_SLICE_OUT2OUT_DELAY_MIN: 74e-12 # MULT18_SLICE_OUT2OUT_DELAY_MIN NOT ACCURATE \ No newline at end of file diff --git a/openfpga_flow/openfpga_timing_annotation/skywater130nm.yml b/openfpga_flow/openfpga_timing_annotation/skywater130nm.yml index 31061e930c..dd08b1e630 100644 --- a/openfpga_flow/openfpga_timing_annotation/skywater130nm.yml +++ b/openfpga_flow/openfpga_timing_annotation/skywater130nm.yml @@ -38,10 +38,10 @@ CLB_CIN_TO_FLE_CIN: 0.16e-9 # CLB_CIN_TO_FLE_CIN NOT ACCURATE ################# Adder Delays ################# -ADDER_LUT4_CIN2OUT_DELAY: 1.21e-9 -ADDER_LUT4_CIN2COUT_DELAY: 1.21e-9 -ADDER_LUT4_IN2OUT_DELAY: 1.21e-9 -ADDER_LUT4_IN2COUT_DELAY: 1.21e-9 +ADDER_CIN2OUT_DELAY: 1.21e-9 +ADDER_CIN2COUT_DELAY: 1.21e-9 +ADDER_IN2OUT_DELAY: 1.21e-9 +ADDER_IN2COUT_DELAY: 1.21e-9 ARITHMETIC_ADDER_OUT_TO_ARITHMETIC_OUT: 25e-12 ARITHMETIC_FF_OUT_TO_ARITHMETIC_OUT: 45e-12 diff --git a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_mem1K_130nm.xml b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_mem1K_130nm.xml new file mode 100644 index 0000000000..e989e9341e --- /dev/null +++ b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_mem1K_130nm.xml @@ -0,0 +1,702 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + + + + + + + + + + + + + + + + + + clb.clk + clb.cin + clb.O[3:0] clb.I[5:0] + clb.cout clb.O[7:4] clb.I[11:6] + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 1 1 1 + 1 1 1 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 235e-12 + 235e-12 + 235e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 195e-12 + 195e-12 + 195e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 261e-12 + 261e-12 + 261e-12 + 261e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm.xml index a967f67a31..2ff83dc494 100644 --- a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm.xml +++ b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm.xml @@ -519,12 +519,12 @@ - - - - - - + + + + + + @@ -754,12 +754,12 @@ - - - - - - + + + + + + From 29f67479ccc4cfef8b91d0a9a7e767bd7db68629 Mon Sep 17 00:00:00 2001 From: Andrew Pond Date: Thu, 22 Jul 2021 15:14:14 -0600 Subject: [PATCH 09/22] yosys techlib directory restructure --- .../openfpga_timing_annotation/README.md | 27 +++++++++++ ...dpram1K_dsp18_fracff_skywater130nm_tt.yml} | 33 ++----------- ..._chain_dpram1K_fracff_skywater130nm_tt.yml | 47 +++++++++++++++++++ ...er_chain_dsp18_fracff_skywater130nm_tt.yml | 44 +++++++++++++++++ .../dpram_1K_bram.txt} | 0 .../dpram_1K_bram_map.v} | 0 .../{ => common}/dsp_map.v | 0 .../{ => common}/openfpga_adders_sim.v | 0 .../{ => common}/openfpga_arith_map.v | 0 .../{ => common}/openfpga_brams.txt | 0 .../{ => common}/openfpga_brams_map.v | 0 .../{ => common}/openfpga_brams_sim.v | 0 .../{ => common}/openfpga_dff_map.v | 0 .../{ => common}/openfpga_dff_sim.v | 0 ...m1K_dsp18_fracff_skywater130nm_cell_sim.v} | 0 15 files changed, 122 insertions(+), 29 deletions(-) create mode 100644 openfpga_flow/openfpga_timing_annotation/README.md rename openfpga_flow/openfpga_timing_annotation/{skywater130nm.yml => k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm_tt.yml} (73%) create mode 100644 openfpga_flow/openfpga_timing_annotation/k6_frac_N10_tileable_adder_chain_dpram1K_fracff_skywater130nm_tt.yml create mode 100644 openfpga_flow/openfpga_timing_annotation/k6_frac_N10_tileable_adder_chain_dsp18_fracff_skywater130nm_tt.yml rename openfpga_flow/openfpga_yosys_techlib/{mem1K_bram.txt => common/dpram_1K_bram.txt} (100%) rename openfpga_flow/openfpga_yosys_techlib/{mem1K_bram_map.v => common/dpram_1K_bram_map.v} (100%) rename openfpga_flow/openfpga_yosys_techlib/{ => common}/dsp_map.v (100%) rename openfpga_flow/openfpga_yosys_techlib/{ => common}/openfpga_adders_sim.v (100%) rename openfpga_flow/openfpga_yosys_techlib/{ => common}/openfpga_arith_map.v (100%) rename openfpga_flow/openfpga_yosys_techlib/{ => common}/openfpga_brams.txt (100%) rename openfpga_flow/openfpga_yosys_techlib/{ => common}/openfpga_brams_map.v (100%) rename openfpga_flow/openfpga_yosys_techlib/{ => common}/openfpga_brams_sim.v (100%) rename openfpga_flow/openfpga_yosys_techlib/{ => common}/openfpga_dff_map.v (100%) rename openfpga_flow/openfpga_yosys_techlib/{ => common}/openfpga_dff_sim.v (100%) rename openfpga_flow/openfpga_yosys_techlib/{dpram1K_dsp18_fracff_cell_sim.v => k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm_cell_sim.v} (100%) diff --git a/openfpga_flow/openfpga_timing_annotation/README.md b/openfpga_flow/openfpga_timing_annotation/README.md new file mode 100644 index 0000000000..29bce8fb49 --- /dev/null +++ b/openfpga_flow/openfpga_timing_annotation/README.md @@ -0,0 +1,27 @@ +Naming convention for timing annotation files +Convention follows the VPR architecture file naming convention, with some extra detail appended to the end. + +k: Look-Up Table (LUT) size of FPGA. If you have fracturable LUTs or multiple LUT circuits, this should be largest input size. +The keyword 'frac' is to specify if fracturable LUT is used or not. +The keyword 'Native' is to specify if fracturable LUT design is a native one (without mode switch) or a standard one (with mode switch). +N: Number of logic elements for a CLB. If you have multiple CLB architectures, this should be largest number. +tileable: If the routing architecture is tileable or not. +The keyword 'IO' specifies if the I/O tile is tileable or not +fracdff: Use multi-mode DFF model, where reset/set/clock polarity is configurable +adder_chain: If hard adder/carry chain is used inside CLBs +register_chain: If shift register chain is used inside CLBs +scan_chain: If scan chain testing infrastructure is used inside CLBs +__mem: If block RAM (BRAM) is used or not. If used, the memory size should be clarified here. The keyword 'wide' is to specify if the BRAM spans more than 1 column. The keyword 'frac' is to specify if the BRAM is fracturable to operate in different modes. +__dsp: If Digital Signal Processor (DSP) is used or not. If used, the input size should be clarified here. The keyword 'wide' is to specify if the DSP spans more than 1 column. The keyword 'frac' is to specify if the DSP is fracturable to operate in different modes. +aib: If the Advanced Interface Bus (AIB) is used in place of some I/Os. +multi_io_capacity: If I/O capacity is different on each side of FPGAs. +reduced_io: If I/Os only appear a certain or multiple sides of FPGAs +registerable_io: If I/Os are registerable (can be either combinational or sequential) +: The technology node which the delay numbers are extracted from. +TileOrgz: How tile is organized. +Top-left (Tl): the pins of a tile are placed on the top side and left side only +Top-right (Tr): the pins of a tile are placed on the top side and right side only +Bottom-right (Br): the pins of a tile are placed on the bottom side and right side only +GlobalTileClk: How many clocks are defined through global ports from physical tiles. is the number of clocks +Other features are used in naming should be listed here. + diff --git a/openfpga_flow/openfpga_timing_annotation/skywater130nm.yml b/openfpga_flow/openfpga_timing_annotation/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm_tt.yml similarity index 73% rename from openfpga_flow/openfpga_timing_annotation/skywater130nm.yml rename to openfpga_flow/openfpga_timing_annotation/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm_tt.yml index 31061e930c..d015287fbb 100644 --- a/openfpga_flow/openfpga_timing_annotation/skywater130nm.yml +++ b/openfpga_flow/openfpga_timing_annotation/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm_tt.yml @@ -1,33 +1,17 @@ -L1_SB_MUX_DELAY: 1.44e-9 -L2_SB_MUX_DELAY: 1.44e-9 -L4_SB_MUX_DELAY: 1.44e-9 -CB_MUX_DELAY: 1.38e-9 -L1_WIRE_R: 100 -L1_WIRE_C: 1e-12 -L2_WIRE_R: 100 -L2_WIRE_C: 1e-12 -L4_WIRE_R: 100 -L4_WIRE_C: 1e-12 INPAD_DELAY: 0.11e-9 OUTPAD_DELAY: 0.11e-9 FF_T_SETUP: 0.39e-9 FF_T_CLK2Q: 0.43e-9 -LUT_OUT0_TO_FF_D_DELAY: 1.14e-9 -LUT_OUT1_TO_FF_D_DELAY: 0.56e-9 LUT_OUT0_TO_FLE_OUT_DELAY: 0.89e-9 FF0_Q_TO_FLE_OUT_DELAY: 0.88e-9 LUT_OUT1_TO_FLE_OUT_DELAY: 0.78e-9 FF1_Q_TO_FLE_OUT_DELAY: 0.89e-9 -LUT3_DELAY: 0.92e-9 -LUT3_OUT_TO_FLE_OUT_DELAY: 1.44e-9 LUT4_DELAY: 1.21e-9 LUT4_OUT_TO_FLE_OUT_DELAY: 1.46e-9 LUT5_DELAY: 235e-12 # LUT5_DELAY NOT ACCURATE LUT5_OUT_TO_FLE_OUT_DELAY: 25e-12 # LUT5_OUT_TO_FLE_OUT_DELAY NOT ACCURATE LUT6_DELAY: 235e-12 # LUT6_DELAY NOT ACCURATE LUT6_OUT_TO_FLE_OUT_DELAY: 25e-12 # LUT6_OUT_TO_FLE_OUT_DELAY NOT ACCURATE -REGIN_TO_FF0_DELAY: 1.12e-9 -FF0_TO_FF1_DELAY: 0.56e-9 CROSSBAR_I_TO_FLE_IN_DELAY: 95e-12 # CROSSBAR_I_TO_FLE_IN_DELAY NOT ACCURATE CROSSBAR_FLE_OUT_TO_FLE_IN_DELAY: 95e-12 # FLE_OUT_TO_FLE_IN_DELAY NOT ACCURATE @@ -38,25 +22,16 @@ CLB_CIN_TO_FLE_CIN: 0.16e-9 # CLB_CIN_TO_FLE_CIN NOT ACCURATE ################# Adder Delays ################# -ADDER_LUT4_CIN2OUT_DELAY: 1.21e-9 -ADDER_LUT4_CIN2COUT_DELAY: 1.21e-9 -ADDER_LUT4_IN2OUT_DELAY: 1.21e-9 -ADDER_LUT4_IN2COUT_DELAY: 1.21e-9 +ADDER_CIN2OUT_DELAY: 1.21e-9 +ADDER_CIN2COUT_DELAY: 1.21e-9 +ADDER_IN2OUT_DELAY: 1.21e-9 +ADDER_IN2COUT_DELAY: 1.21e-9 ARITHMETIC_ADDER_OUT_TO_ARITHMETIC_OUT: 25e-12 ARITHMETIC_FF_OUT_TO_ARITHMETIC_OUT: 45e-12 -################# MULT9 Delays ################# - -MULT9_A2Y_DELAY_MAX: 1.523e-9 -MULT9_A2Y_DELAY_MIN: 0.776e-9 -MULT9_B2Y_DELAY_MAX: 1.523e-9 -MULT9_B2Y_DELAY_MIN: 0.776e-9 - - - ################# MULT18 Delays ################# MULT18_A2Y_DELAY_MAX: 1.523e-9 diff --git a/openfpga_flow/openfpga_timing_annotation/k6_frac_N10_tileable_adder_chain_dpram1K_fracff_skywater130nm_tt.yml b/openfpga_flow/openfpga_timing_annotation/k6_frac_N10_tileable_adder_chain_dpram1K_fracff_skywater130nm_tt.yml new file mode 100644 index 0000000000..4d1136b15d --- /dev/null +++ b/openfpga_flow/openfpga_timing_annotation/k6_frac_N10_tileable_adder_chain_dpram1K_fracff_skywater130nm_tt.yml @@ -0,0 +1,47 @@ +INPAD_DELAY: 0.11e-9 +OUTPAD_DELAY: 0.11e-9 +FF_T_SETUP: 0.39e-9 +FF_T_CLK2Q: 0.43e-9 +LUT_OUT0_TO_FLE_OUT_DELAY: 0.89e-9 +FF0_Q_TO_FLE_OUT_DELAY: 0.88e-9 +LUT_OUT1_TO_FLE_OUT_DELAY: 0.78e-9 +FF1_Q_TO_FLE_OUT_DELAY: 0.89e-9 +LUT5_DELAY: 235e-12 # LUT5_DELAY NOT ACCURATE +LUT5_OUT_TO_FLE_OUT_DELAY: 25e-12 # LUT5_OUT_TO_FLE_OUT_DELAY NOT ACCURATE +LUT6_DELAY: 235e-12 # LUT6_DELAY NOT ACCURATE +LUT6_OUT_TO_FLE_OUT_DELAY: 25e-12 # LUT6_OUT_TO_FLE_OUT_DELAY NOT ACCURATE + +CROSSBAR_I_TO_FLE_IN_DELAY: 95e-12 # CROSSBAR_I_TO_FLE_IN_DELAY NOT ACCURATE +CROSSBAR_FLE_OUT_TO_FLE_IN_DELAY: 95e-12 # FLE_OUT_TO_FLE_IN_DELAY NOT ACCURATE + +CLB_CIN_TO_FLE_CIN: 0.16e-9 # CLB_CIN_TO_FLE_CIN NOT ACCURATE + + + +################# Adder Delays ################# + +ADDER_CIN2OUT_DELAY: 1.21e-9 +ADDER_CIN2COUT_DELAY: 1.21e-9 +ADDER_IN2OUT_DELAY: 1.21e-9 +ADDER_IN2COUT_DELAY: 1.21e-9 + +ARITHMETIC_ADDER_OUT_TO_ARITHMETIC_OUT: 25e-12 +ARITHMETIC_FF_OUT_TO_ARITHMETIC_OUT: 45e-12 + + + +################# BRAM Delays ################# + +DPRAM_128x8_CLK_TO_WADDR_DELAY: 509e-12 +DPRAM_128x8_CLK_TO_RADDR_DELAY: 509e-12 +DPRAM_128x8_CLK_TO_DATA_IN_DELAY: 509e-12 +DPRAM_128x8_CLK_TO_WEN_DELAY: 509e-12 +DPRAM_128x8_CLK_TO_REN_DELAY: 509e-12 +DPRAM_128x8_CLK_TO_DATA_OUT_DELAY: 1.234e-9 + +MEMORY_WADDR_TO_BRAM_WADDR_DELAY: 132e-12 +MEMORY_RADDR_TO_BRAM_RADDR_DELAY: 132e-12 +MEMORY_DATA_IN_TO_BRAM_DATA_IN_DELAY: 132e-12 +MEMORY_WEN_TO_BRAM_WEN_DELAY: 132e-12 +MEMORY_REN_TO_BRAM_REN_DELAY: 132e-12 +BRAM_DATA_OUT_TO_MEMORY_DATA_OUT_DELAY: 40e-12 \ No newline at end of file diff --git a/openfpga_flow/openfpga_timing_annotation/k6_frac_N10_tileable_adder_chain_dsp18_fracff_skywater130nm_tt.yml b/openfpga_flow/openfpga_timing_annotation/k6_frac_N10_tileable_adder_chain_dsp18_fracff_skywater130nm_tt.yml new file mode 100644 index 0000000000..a2af36f56a --- /dev/null +++ b/openfpga_flow/openfpga_timing_annotation/k6_frac_N10_tileable_adder_chain_dsp18_fracff_skywater130nm_tt.yml @@ -0,0 +1,44 @@ +INPAD_DELAY: 0.11e-9 +OUTPAD_DELAY: 0.11e-9 +FF_T_SETUP: 0.39e-9 +FF_T_CLK2Q: 0.43e-9 +LUT_OUT0_TO_FLE_OUT_DELAY: 0.89e-9 +FF0_Q_TO_FLE_OUT_DELAY: 0.88e-9 +LUT_OUT1_TO_FLE_OUT_DELAY: 0.78e-9 +FF1_Q_TO_FLE_OUT_DELAY: 0.89e-9 +LUT5_DELAY: 235e-12 # LUT5_DELAY NOT ACCURATE +LUT5_OUT_TO_FLE_OUT_DELAY: 25e-12 # LUT5_OUT_TO_FLE_OUT_DELAY NOT ACCURATE +LUT6_DELAY: 235e-12 # LUT6_DELAY NOT ACCURATE +LUT6_OUT_TO_FLE_OUT_DELAY: 25e-12 # LUT6_OUT_TO_FLE_OUT_DELAY NOT ACCURATE + +CROSSBAR_I_TO_FLE_IN_DELAY: 95e-12 # CROSSBAR_I_TO_FLE_IN_DELAY NOT ACCURATE +CROSSBAR_FLE_OUT_TO_FLE_IN_DELAY: 95e-12 # FLE_OUT_TO_FLE_IN_DELAY NOT ACCURATE + +CLB_CIN_TO_FLE_CIN: 0.16e-9 # CLB_CIN_TO_FLE_CIN NOT ACCURATE + + + +################# Adder Delays ################# + +ADDER_CIN2OUT_DELAY: 1.21e-9 +ADDER_CIN2COUT_DELAY: 1.21e-9 +ADDER_IN2OUT_DELAY: 1.21e-9 +ADDER_IN2COUT_DELAY: 1.21e-9 + +ARITHMETIC_ADDER_OUT_TO_ARITHMETIC_OUT: 25e-12 +ARITHMETIC_FF_OUT_TO_ARITHMETIC_OUT: 45e-12 + + + +################# MULT18 Delays ################# + +MULT18_A2Y_DELAY_MAX: 1.523e-9 +MULT18_A2Y_DELAY_MIN: 0.776e-9 +MULT18_B2Y_DELAY_MAX: 1.523e-9 +MULT18_B2Y_DELAY_MIN: 0.776e-9 +MULT18_SLICE_A2A_DELAY_MAX: 134e-12 # MULT18_SLICE_A2A_DELAY_MAX NOT ACCURATE +MULT18_SLICE_A2A_DELAY_MIN: 74e-12 # MULT18_SLICE_A2A_DELAY_MIN NOT ACCURATE +MULT18_SLICE_B2B_DELAY_MAX: 134e-12 # MULT18_SLICE_B2B_DELAY_MAX NOT ACCURATE +MULT18_SLICE_B2B_DELAY_MIN: 74e-12 # MULT18_SLICE_B2B_DELAY_MIN NOT ACCURATE +MULT18_SLICE_OUT2OUT_DELAY_MAX: 1.93e-9 # MULT18_SLICE_OUT2OUT_DELAY_MAX NOT ACCURATE +MULT18_SLICE_OUT2OUT_DELAY_MIN: 74e-12 # MULT18_SLICE_OUT2OUT_DELAY_MIN NOT ACCURATE \ No newline at end of file diff --git a/openfpga_flow/openfpga_yosys_techlib/mem1K_bram.txt b/openfpga_flow/openfpga_yosys_techlib/common/dpram_1K_bram.txt similarity index 100% rename from openfpga_flow/openfpga_yosys_techlib/mem1K_bram.txt rename to openfpga_flow/openfpga_yosys_techlib/common/dpram_1K_bram.txt diff --git a/openfpga_flow/openfpga_yosys_techlib/mem1K_bram_map.v b/openfpga_flow/openfpga_yosys_techlib/common/dpram_1K_bram_map.v similarity index 100% rename from openfpga_flow/openfpga_yosys_techlib/mem1K_bram_map.v rename to openfpga_flow/openfpga_yosys_techlib/common/dpram_1K_bram_map.v diff --git a/openfpga_flow/openfpga_yosys_techlib/dsp_map.v b/openfpga_flow/openfpga_yosys_techlib/common/dsp_map.v similarity index 100% rename from openfpga_flow/openfpga_yosys_techlib/dsp_map.v rename to openfpga_flow/openfpga_yosys_techlib/common/dsp_map.v diff --git a/openfpga_flow/openfpga_yosys_techlib/openfpga_adders_sim.v b/openfpga_flow/openfpga_yosys_techlib/common/openfpga_adders_sim.v similarity index 100% rename from openfpga_flow/openfpga_yosys_techlib/openfpga_adders_sim.v rename to openfpga_flow/openfpga_yosys_techlib/common/openfpga_adders_sim.v diff --git a/openfpga_flow/openfpga_yosys_techlib/openfpga_arith_map.v b/openfpga_flow/openfpga_yosys_techlib/common/openfpga_arith_map.v similarity index 100% rename from openfpga_flow/openfpga_yosys_techlib/openfpga_arith_map.v rename to openfpga_flow/openfpga_yosys_techlib/common/openfpga_arith_map.v diff --git a/openfpga_flow/openfpga_yosys_techlib/openfpga_brams.txt b/openfpga_flow/openfpga_yosys_techlib/common/openfpga_brams.txt similarity index 100% rename from openfpga_flow/openfpga_yosys_techlib/openfpga_brams.txt rename to openfpga_flow/openfpga_yosys_techlib/common/openfpga_brams.txt diff --git a/openfpga_flow/openfpga_yosys_techlib/openfpga_brams_map.v b/openfpga_flow/openfpga_yosys_techlib/common/openfpga_brams_map.v similarity index 100% rename from openfpga_flow/openfpga_yosys_techlib/openfpga_brams_map.v rename to openfpga_flow/openfpga_yosys_techlib/common/openfpga_brams_map.v diff --git a/openfpga_flow/openfpga_yosys_techlib/openfpga_brams_sim.v b/openfpga_flow/openfpga_yosys_techlib/common/openfpga_brams_sim.v similarity index 100% rename from openfpga_flow/openfpga_yosys_techlib/openfpga_brams_sim.v rename to openfpga_flow/openfpga_yosys_techlib/common/openfpga_brams_sim.v diff --git a/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v b/openfpga_flow/openfpga_yosys_techlib/common/openfpga_dff_map.v similarity index 100% rename from openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v rename to openfpga_flow/openfpga_yosys_techlib/common/openfpga_dff_map.v diff --git a/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v b/openfpga_flow/openfpga_yosys_techlib/common/openfpga_dff_sim.v similarity index 100% rename from openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v rename to openfpga_flow/openfpga_yosys_techlib/common/openfpga_dff_sim.v diff --git a/openfpga_flow/openfpga_yosys_techlib/dpram1K_dsp18_fracff_cell_sim.v b/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm_cell_sim.v similarity index 100% rename from openfpga_flow/openfpga_yosys_techlib/dpram1K_dsp18_fracff_cell_sim.v rename to openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm_cell_sim.v From 05c4a253cc4d276b1ec9ff5ecdface9cae93457f Mon Sep 17 00:00:00 2001 From: Andrew Pond Date: Thu, 22 Jul 2021 16:39:44 -0600 Subject: [PATCH 10/22] fixed CI errors --- ...ite_full_testbench_example_script.openfpga | 5 +- ...ch_no_clk_modeling_example_script.openfpga | 75 +++++++++++++++++++ ...ram1K_dsp18_fracff_skywater130nm_dff_map.v | 48 ++++++++++++ .../k4_series/k4n4_bram/config/task.conf | 6 +- .../k4_series/k4n4_fracff/config/task.conf | 4 +- ...ain_dpram1K_dsp18_fracff_skywater130nm.xml | 24 +++--- 6 files changed, 143 insertions(+), 19 deletions(-) create mode 100644 openfpga_flow/openfpga_shell_scripts/write_full_testbench_no_clk_modeling_example_script.openfpga create mode 100644 openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm_dff_map.v diff --git a/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga index 5c155b5b95..c8f8105fbb 100644 --- a/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga @@ -1,6 +1,6 @@ # Run VPR for the 'and' design #--write_rr_graph example_rr_graph.xml -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --device ${OPENFPGA_VPR_DEVICE_LAYOUT} +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route ${OPENFPGA_VPR_DEVICE_LAYOUT} # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} @@ -10,7 +10,7 @@ read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} # Annotate the OpenFPGA architecture to VPR data base # to debug use --verbose options -link_openfpga_arch --sort_gsb_chan_node_in_edges +link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges # Check and correct any naming conflicts in the BLIF netlist check_netlist_naming_conflict --fix --report ./netlist_renaming.xml @@ -72,3 +72,4 @@ exit # Note : # To run verification at the end of the flow maintain source in ./SRC directory +{"mode":"full","isActive":false} \ No newline at end of file diff --git a/openfpga_flow/openfpga_shell_scripts/write_full_testbench_no_clk_modeling_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/write_full_testbench_no_clk_modeling_example_script.openfpga new file mode 100644 index 0000000000..506364e308 --- /dev/null +++ b/openfpga_flow/openfpga_shell_scripts/write_full_testbench_no_clk_modeling_example_script.openfpga @@ -0,0 +1,75 @@ +# Run VPR for the 'and' design +#--write_rr_graph example_rr_graph.xml +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --device ${OPENFPGA_VPR_DEVICE_LAYOUT} + +# Read OpenFPGA architecture definition +read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} + +# Read OpenFPGA simulation settings +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} + +# Annotate the OpenFPGA architecture to VPR data base +# to debug use --verbose options +link_openfpga_arch --sort_gsb_chan_node_in_edges + +# Check and correct any naming conflicts in the BLIF netlist +check_netlist_naming_conflict --fix --report ./netlist_renaming.xml + +# Apply fix-up to clustering nets based on routing results +pb_pin_fixup --verbose + +# Apply fix-up to Look-Up Table truth tables based on packing results +lut_truth_table_fixup + +# Build the module graph +# - Enabled compression on routing architecture modules +# - Enable pin duplication on grid modules +build_fabric --compress_routing #--verbose + +# Write the fabric hierarchy of module graph to a file +# This is used by hierarchical PnR flows +write_fabric_hierarchy --file ./fabric_hierarchy.txt + +# Repack the netlist to physical pbs +# This must be done before bitstream generator and testbench generation +# Strongly recommend it is done after all the fix-up have been applied +repack #--verbose + +# Build the bitstream +# - Output the fabric-independent bitstream to a file +build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml + +# Build fabric-dependent bitstream +build_fabric_bitstream --verbose + +# Write fabric-dependent bitstream +write_fabric_bitstream --file fabric_bitstream.bit --format plain_text ${OPENFPGA_FAST_CONFIGURATION} + +# Write the Verilog netlist for FPGA fabric +# - Enable the use of explicit port mapping in Verilog netlist +write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose + +# Write the Verilog testbench for FPGA fabric +# - We suggest the use of same output directory as fabric Verilog netlists +# - Must specify the reference benchmark file if you want to output any testbenches +# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA +# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase +# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts +write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --include_signal_init --explicit_port_mapping --bitstream fabric_bitstream.bit ${OPENFPGA_FAST_CONFIGURATION} + +# Write the SDC files for PnR backend +# - Turn on every options here +write_pnr_sdc --file ./SDC + +# Write SDC to disable timing for configure ports +write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc + +# Write the SDC to run timing analysis for a mapped FPGA fabric +write_analysis_sdc --file ./SDC_analysis + +# Finish and exit OpenFPGA +exit + +# Note : +# To run verification at the end of the flow maintain source in ./SRC directory +{"mode":"full","isActive":false} \ No newline at end of file diff --git a/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm_dff_map.v b/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm_dff_map.v new file mode 100644 index 0000000000..f8eed8db05 --- /dev/null +++ b/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm_dff_map.v @@ -0,0 +1,48 @@ +// Basic DFF +module \$_DFF_P_ (D, C, Q); + input D; + input C; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + dff _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C)); +endmodule + +// Async active-high reset +module \$_DFF_PP0_ (D, C, R, Q); + input D; + input C; + input R; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + dffr _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .R(R)); +endmodule + +// Async active-high set +module \$_DFF_PP1_ (D, C, R, Q); + input D; + input C; + input R; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + dffs _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .S(R)); +endmodule + +// Async active-low reset +module \$_DFF_PN0_ (D, C, R, Q); + input D; + input C; + input R; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + dffrn _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .RN(R)); +endmodule + +// Async active-low set +module \$_DFF_PN1_ (D, C, R, Q); + input D; + input C; + input R; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + dffsn _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .SN(R)); +endmodule diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_bram/config/task.conf b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_bram/config/task.conf index 6caa13456a..91c1237fc0 100644 --- a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_bram/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_bram/config/task.conf @@ -21,9 +21,9 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml openfpga_vpr_device_layout=3x2 # Yosys script parameters -yosys_cell_sim_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_brams_sim.v -yosys_bram_map_rules=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_brams.txt -yosys_bram_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_brams_map.v +yosys_cell_sim_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/common/openfpga_dff_map.v +yosys_bram_map_rules=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/common/openfpga_brams.txt +yosys_bram_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/common/openfpga_dff_map.v [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_mem1K_40nm.xml diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/task.conf b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/task.conf index 2408323ed4..bdbb241e77 100644 --- a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/task.conf @@ -20,8 +20,8 @@ openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scrip openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml # Yosys script parameters -yosys_cell_sim_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v -yosys_dff_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v +yosys_cell_sim_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/common/openfpga_dff_sim.v +yosys_dff_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/common/openfpga_dff_map.v [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_fracff_40nm.xml diff --git a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm.xml index a967f67a31..2ff83dc494 100644 --- a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm.xml +++ b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm.xml @@ -519,12 +519,12 @@ - - - - - - + + + + + + @@ -754,12 +754,12 @@ - - - - - - + + + + + + From ce71466b3238ca08a8f22b03fd7f989b3339cd10 Mon Sep 17 00:00:00 2001 From: Andrew Pond Date: Fri, 23 Jul 2021 11:16:26 -0600 Subject: [PATCH 11/22] fixed bram CI error --- ...0_tileable_adder_chain_mem1K_40nm_bram.txt | 18 ++ ...tileable_adder_chain_mem1K_40nm_bram_map.v | 21 ++ ...tileable_adder_chain_mem1K_40nm_cell_sim.v | 207 ++++++++++++++++++ 3 files changed, 246 insertions(+) create mode 100644 openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem1K_40nm_bram.txt create mode 100644 openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem1K_40nm_bram_map.v create mode 100644 openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem1K_40nm_cell_sim.v diff --git a/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem1K_40nm_bram.txt b/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem1K_40nm_bram.txt new file mode 100644 index 0000000000..51617f2719 --- /dev/null +++ b/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem1K_40nm_bram.txt @@ -0,0 +1,18 @@ +bram $__MY_DPRAM_128x8 + init 0 + abits 7 + dbits 8 + groups 2 + ports 1 1 + wrmode 1 0 + enable 1 1 + transp 0 0 + clocks 1 1 + clkpol 1 1 +endbram + +match $__MY_DPRAM_128x8 + min efficiency 0 + make_transp +endmatch + diff --git a/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem1K_40nm_bram_map.v b/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem1K_40nm_bram_map.v new file mode 100644 index 0000000000..8cf462c1a7 --- /dev/null +++ b/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem1K_40nm_bram_map.v @@ -0,0 +1,21 @@ +module $__MY_DPRAM_128x8 ( + output [0:7] B1DATA, + input CLK1, + input [0:6] B1ADDR, + input [0:6] A1ADDR, + input [0:7] A1DATA, + input A1EN, + input B1EN ); + + generate + dpram_128x8 #() _TECHMAP_REPLACE_ ( + .clk (CLK1), + .wen (A1EN), + .waddr (A1ADDR), + .data_in (A1DATA), + .ren (B1EN), + .raddr (B1ADDR), + .data_out (B1DATA) ); + endgenerate + +endmodule diff --git a/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem1K_40nm_cell_sim.v b/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem1K_40nm_cell_sim.v new file mode 100644 index 0000000000..bef1c4b116 --- /dev/null +++ b/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem1K_40nm_cell_sim.v @@ -0,0 +1,207 @@ +//----------------------------- +// Dual-port RAM 128x8 bit (1Kbit) +// Core logic +//----------------------------- +module dpram_128x8_core ( + input wclk, + input wen, + input [0:6] waddr, + input [0:7] data_in, + input rclk, + input ren, + input [0:6] raddr, + output [0:7] data_out ); + + reg [0:7] ram[0:127]; + reg [0:7] internal; + + assign data_out = internal; + + always @(posedge wclk) begin + if(wen) begin + ram[waddr] <= data_in; + end + end + + always @(posedge rclk) begin + if(ren) begin + internal <= ram[raddr]; + end + end + +endmodule + +//----------------------------- +// Dual-port RAM 128x8 bit (1Kbit) wrapper +// where the read clock and write clock +// are combined to a unified clock +//----------------------------- +module dpram_128x8 ( + input clk, + input wen, + input ren, + input [0:6] waddr, + input [0:6] raddr, + input [0:7] data_in, + output [0:7] data_out ); + + dpram_128x8_core memory_0 ( + .wclk (clk), + .wen (wen), + .waddr (waddr), + .data_in (data_in), + .rclk (clk), + .ren (ren), + .raddr (raddr), + .data_out (data_out) ); + +endmodule + +//----------------------------- +// Native D-type flip-flop +//----------------------------- +(* abc9_flop, lib_whitebox *) +module dff( + output reg Q, + input D, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C) + Q <= D; + 1'b1: + always @(negedge C) + Q <= D; + endcase +endmodule + +//----------------------------- +// D-type flip-flop with active-high asynchronous reset +//----------------------------- +(* abc9_flop, lib_whitebox *) +module dffr( + output reg Q, + input D, + input R, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C or posedge R) + if (R == 1'b1) + Q <= 1'b0; + else + Q <= D; + 1'b1: + always @(negedge C or posedge R) + if (R == 1'b1) + Q <= 1'b0; + else + Q <= D; + endcase +endmodule + +//----------------------------- +// D-type flip-flop with active-high asynchronous set +//----------------------------- +(* abc9_flop, lib_whitebox *) +module dffs( + output reg Q, + input D, + input S, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C or posedge S) + if (S == 1'b1) + Q <= 1'b1; + else + Q <= D; + 1'b1: + always @(negedge C or posedge S) + if (S == 1'b1) + Q <= 1'b1; + else + Q <= D; + endcase +endmodule + +//----------------------------- +// D-type flip-flop with active-low asynchronous reset +//----------------------------- +(* abc9_flop, lib_whitebox *) +module dffrn( + output reg Q, + input D, + input RN, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C or negedge RN) + if (RN == 1'b0) + Q <= 1'b0; + else + Q <= D; + 1'b1: + always @(negedge C or negedge RN) + if (RN == 1'b0) + Q <= 1'b0; + else + Q <= D; + endcase +endmodule + +//----------------------------- +// D-type flip-flop with active-low asynchronous set +//----------------------------- +(* abc9_flop, lib_whitebox *) +module dffsn( + output reg Q, + input D, + input SN, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C or negedge SN) + if (SN == 1'b0) + Q <= 1'b1; + else + Q <= D; + 1'b1: + always @(negedge C or negedge SN) + if (SN == 1'b0) + Q <= 1'b1; + else + Q <= D; + endcase +endmodule + From e39e9b8c26b3b21ddd6f3e8109b792e70c7d1773 Mon Sep 17 00:00:00 2001 From: Andrew Pond Date: Fri, 23 Jul 2021 12:08:32 -0600 Subject: [PATCH 12/22] finishing touches for PR --- .../misc/ys_tmpl_yosys_vpr_dsp_dff_flow.ys | 102 ------------ ...ite_full_testbench_example_script.openfpga | 3 +- .../openfpga_timing_annotation/README.md | 1 + ...tileable_adder_chain_mem1K_40nm_cell_sim.v | 151 +----------------- ...eable_adder_chain_skywater130nm_cell_sim.v | 58 ------- 5 files changed, 3 insertions(+), 312 deletions(-) delete mode 100644 openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_dff_flow.ys delete mode 100644 openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_skywater130nm_cell_sim.v diff --git a/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_dff_flow.ys b/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_dff_flow.ys deleted file mode 100644 index e414466053..0000000000 --- a/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_dff_flow.ys +++ /dev/null @@ -1,102 +0,0 @@ -# Yosys synthesis script for ${TOP_MODULE} - -######################### -# Parse input files -######################### -# Read verilog files -${READ_VERILOG_FILE} -# Read technology library -read_verilog -lib -specify ${YOSYS_CELL_SIM_VERILOG} - -######################### -# Prepare for synthesis -######################### -# Identify top module from hierarchy -hierarchy -check -top ${TOP_MODULE} -# - Convert process blocks to AST -proc -# Flatten all the gates/primitives -flatten -# Identify tri-state buffers from 'z' signal in AST -# with follow-up optimizations to clean up AST -tribuf -logic -opt_expr -opt_clean -# demote inout ports to input or output port -# with follow-up optimizations to clean up AST -deminout -opt - -opt_expr -opt_clean -check -opt -wreduce -keepdc -peepopt -pmuxtree -opt_clean - -######################## -# Map multipliers -# Inspired from synth_xilinx.cc -######################### -# Avoid merging any registers into DSP, reserve memory port registers first -memory_dff -wreduce t:$mul -techmap -map +/mul2dsp.v -map ${YOSYS_DSP_MAP_VERILOG} ${YOSYS_DSP_MAP_PARAMETERS} -select a:mul2dsp -setattr -unset mul2dsp -opt_expr -fine -wreduce -select -clear -chtype -set $mul t:$__soft_mul# Extract arithmetic functions - -######################### -# Run coarse synthesis -######################### -# Run a tech map with default library -techmap -alumacc -share -opt -fsm -# Run a quick follow-up optimization to sweep out unused nets/signals -opt -fast -# Optimize any memory cells by merging share-able ports and collecting all the ports belonging to memorcy cells -memory -nomap -opt_clean - - -######################### -# Map muxes to pmuxes -######################### -techmap -map +/pmux2mux.v - -######################### -# Map flip-flops -######################### -techmap -map ${YOSYS_DFF_MAP_VERILOG} -opt_expr -mux_undef -simplemap -opt_expr -opt_merge -opt_rmdff -opt_clean -opt - -######################### -# Map LUTs -######################### -abc -lut ${LUT_SIZE} - -######################### -# Check and show statisitics -######################### -hierarchy -check -stat - -######################### -# Output netlists -######################### -opt_clean -purge -write_blif ${OUTPUT_BLIF} diff --git a/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga index c8f8105fbb..e3e74a4091 100644 --- a/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga @@ -71,5 +71,4 @@ write_analysis_sdc --file ./SDC_analysis exit # Note : -# To run verification at the end of the flow maintain source in ./SRC directory -{"mode":"full","isActive":false} \ No newline at end of file +# To run verification at the end of the flow maintain source in ./SRC directory \ No newline at end of file diff --git a/openfpga_flow/openfpga_timing_annotation/README.md b/openfpga_flow/openfpga_timing_annotation/README.md index 29bce8fb49..ae75506dba 100644 --- a/openfpga_flow/openfpga_timing_annotation/README.md +++ b/openfpga_flow/openfpga_timing_annotation/README.md @@ -25,3 +25,4 @@ Bottom-right (Br): the pins of a tile are placed on the bottom side and right si GlobalTileClk: How many clocks are defined through global ports from physical tiles. is the number of clocks Other features are used in naming should be listed here. +tt/ff/ss: timing coners specified at the end of the file name. Each file under the specific architecture is tied to a certain corner, as the timing values will change with the corner. \ No newline at end of file diff --git a/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem1K_40nm_cell_sim.v b/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem1K_40nm_cell_sim.v index bef1c4b116..83b44875c3 100644 --- a/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem1K_40nm_cell_sim.v +++ b/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem1K_40nm_cell_sim.v @@ -55,153 +55,4 @@ module dpram_128x8 ( .raddr (raddr), .data_out (data_out) ); -endmodule - -//----------------------------- -// Native D-type flip-flop -//----------------------------- -(* abc9_flop, lib_whitebox *) -module dff( - output reg Q, - input D, - (* clkbuf_sink *) - (* invertible_pin = "IS_C_INVERTED" *) - input C -); - parameter [0:0] INIT = 1'b0; - parameter [0:0] IS_C_INVERTED = 1'b0; - initial Q = INIT; - case(|IS_C_INVERTED) - 1'b0: - always @(posedge C) - Q <= D; - 1'b1: - always @(negedge C) - Q <= D; - endcase -endmodule - -//----------------------------- -// D-type flip-flop with active-high asynchronous reset -//----------------------------- -(* abc9_flop, lib_whitebox *) -module dffr( - output reg Q, - input D, - input R, - (* clkbuf_sink *) - (* invertible_pin = "IS_C_INVERTED" *) - input C -); - parameter [0:0] INIT = 1'b0; - parameter [0:0] IS_C_INVERTED = 1'b0; - initial Q = INIT; - case(|IS_C_INVERTED) - 1'b0: - always @(posedge C or posedge R) - if (R == 1'b1) - Q <= 1'b0; - else - Q <= D; - 1'b1: - always @(negedge C or posedge R) - if (R == 1'b1) - Q <= 1'b0; - else - Q <= D; - endcase -endmodule - -//----------------------------- -// D-type flip-flop with active-high asynchronous set -//----------------------------- -(* abc9_flop, lib_whitebox *) -module dffs( - output reg Q, - input D, - input S, - (* clkbuf_sink *) - (* invertible_pin = "IS_C_INVERTED" *) - input C -); - parameter [0:0] INIT = 1'b0; - parameter [0:0] IS_C_INVERTED = 1'b0; - initial Q = INIT; - case(|IS_C_INVERTED) - 1'b0: - always @(posedge C or posedge S) - if (S == 1'b1) - Q <= 1'b1; - else - Q <= D; - 1'b1: - always @(negedge C or posedge S) - if (S == 1'b1) - Q <= 1'b1; - else - Q <= D; - endcase -endmodule - -//----------------------------- -// D-type flip-flop with active-low asynchronous reset -//----------------------------- -(* abc9_flop, lib_whitebox *) -module dffrn( - output reg Q, - input D, - input RN, - (* clkbuf_sink *) - (* invertible_pin = "IS_C_INVERTED" *) - input C -); - parameter [0:0] INIT = 1'b0; - parameter [0:0] IS_C_INVERTED = 1'b0; - initial Q = INIT; - case(|IS_C_INVERTED) - 1'b0: - always @(posedge C or negedge RN) - if (RN == 1'b0) - Q <= 1'b0; - else - Q <= D; - 1'b1: - always @(negedge C or negedge RN) - if (RN == 1'b0) - Q <= 1'b0; - else - Q <= D; - endcase -endmodule - -//----------------------------- -// D-type flip-flop with active-low asynchronous set -//----------------------------- -(* abc9_flop, lib_whitebox *) -module dffsn( - output reg Q, - input D, - input SN, - (* clkbuf_sink *) - (* invertible_pin = "IS_C_INVERTED" *) - input C -); - parameter [0:0] INIT = 1'b0; - parameter [0:0] IS_C_INVERTED = 1'b0; - initial Q = INIT; - case(|IS_C_INVERTED) - 1'b0: - always @(posedge C or negedge SN) - if (SN == 1'b0) - Q <= 1'b1; - else - Q <= D; - 1'b1: - always @(negedge C or negedge SN) - if (SN == 1'b0) - Q <= 1'b1; - else - Q <= D; - endcase -endmodule - +endmodule \ No newline at end of file diff --git a/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_skywater130nm_cell_sim.v b/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_skywater130nm_cell_sim.v deleted file mode 100644 index 9ec66e6eed..0000000000 --- a/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_skywater130nm_cell_sim.v +++ /dev/null @@ -1,58 +0,0 @@ -//----------------------------- -// Dual-port RAM 128x8 bit (1Kbit) -// Core logic -//----------------------------- -module dpram_128x8_core ( - input wclk, - input wen, - input [0:6] waddr, - input [0:7] data_in, - input rclk, - input ren, - input [0:6] raddr, - output [0:7] data_out ); - - reg [0:7] ram[0:127]; - reg [0:7] internal; - - assign data_out = internal; - - always @(posedge wclk) begin - if(wen) begin - ram[waddr] <= data_in; - end - end - - always @(posedge rclk) begin - if(ren) begin - internal <= ram[raddr]; - end - end - -endmodule - -//----------------------------- -// Dual-port RAM 128x8 bit (1Kbit) wrapper -// where the read clock and write clock -// are combined to a unified clock -//----------------------------- -module dpram_128x8 ( - input clk, - input wen, - input ren, - input [0:6] waddr, - input [0:6] raddr, - input [0:7] data_in, - output [0:7] data_out ); - - dpram_128x8_core memory_0 ( - .wclk (clk), - .wen (wen), - .waddr (waddr), - .data_in (data_in), - .rclk (clk), - .ren (ren), - .raddr (raddr), - .data_out (data_out) ); - -endmodule From cb0dbd6f2ff61ca2582ffadb508ee77b720541ed Mon Sep 17 00:00:00 2001 From: Andrew Pond Date: Mon, 26 Jul 2021 17:40:34 -0600 Subject: [PATCH 13/22] responding to Xifan's comments in PR --- openfpga_flow/scripts/run_fpga_task.py | 0 .../processor/config/task.conf | 36 + openfpga_flow/tasks/skywater_openfpga_task | 1 - ...rac_N4_tileable_adder_mem1K_dsp18_40nm.xml | 620 ------------------ ...ain_dpram1K_dsp18_fracff_skywater130nm.xml | 4 +- 5 files changed, 38 insertions(+), 623 deletions(-) mode change 100644 => 100755 openfpga_flow/scripts/run_fpga_task.py create mode 100644 openfpga_flow/tasks/benchmark_sweep/processor/config/task.conf delete mode 120000 openfpga_flow/tasks/skywater_openfpga_task delete mode 100644 openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_mem1K_dsp18_40nm.xml diff --git a/openfpga_flow/scripts/run_fpga_task.py b/openfpga_flow/scripts/run_fpga_task.py old mode 100644 new mode 100755 diff --git a/openfpga_flow/tasks/benchmark_sweep/processor/config/task.conf b/openfpga_flow/tasks/benchmark_sweep/processor/config/task.conf new file mode 100644 index 0000000000..bf24a2cf6d --- /dev/null +++ b/openfpga_flow/tasks/benchmark_sweep/processor/config/task.conf @@ -0,0 +1,36 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/generate_bitstream_global_tile_multiclock_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +openfpga_vpr_device_layout=auto +openfpga_fast_configuration= + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/processor/picorv32/picorv32.v + +[SYNTHESIS_PARAM] +bench0_top = picorv32 +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= diff --git a/openfpga_flow/tasks/skywater_openfpga_task b/openfpga_flow/tasks/skywater_openfpga_task deleted file mode 120000 index 4fd3973876..0000000000 --- a/openfpga_flow/tasks/skywater_openfpga_task +++ /dev/null @@ -1 +0,0 @@ -/home/apond/sofa/SCRIPT/skywater_openfpga_task \ No newline at end of file diff --git a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_mem1K_dsp18_40nm.xml b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_mem1K_dsp18_40nm.xml deleted file mode 100644 index 5351486bcf..0000000000 --- a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_mem1K_dsp18_40nm.xml +++ /dev/null @@ -1,620 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 - 1 1 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 235e-12 - 235e-12 - 235e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 261e-12 - 261e-12 - 261e-12 - 261e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm.xml index 2ff83dc494..44907b68f3 100644 --- a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm.xml +++ b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm.xml @@ -246,8 +246,8 @@ clb.clk clb.reset clb.set - clb.cin - clb.O[9:0] clb.I[19:0] + clb.cin clb.O[9:0] + clb.I[19:0] clb.cout clb.O[19:10] clb.I[39:20] From 73854bbe6613aaaf8050a2e135f9ef8485e8ced5 Mon Sep 17 00:00:00 2001 From: Andrew Pond Date: Thu, 29 Jul 2021 12:32:52 -0600 Subject: [PATCH 14/22] bram timing update --- .../write_full_testbench_example_script.openfpga | 2 +- ...leable_adder_chain_dpram1K_dsp18_fracff_skywater130nm_tt.yml | 2 +- ...N10_tileable_adder_chain_dpram1K_fracff_skywater130nm_tt.yml | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga index e3e74a4091..347359d53e 100644 --- a/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga @@ -1,6 +1,6 @@ # Run VPR for the 'and' design #--write_rr_graph example_rr_graph.xml -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route ${OPENFPGA_VPR_DEVICE_LAYOUT} +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ${OPENFPGA_CLOCK_MODELING} ${OPENFPGA_VPR_DEVICE_LAYOUT} # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} diff --git a/openfpga_flow/openfpga_timing_annotation/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm_tt.yml b/openfpga_flow/openfpga_timing_annotation/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm_tt.yml index d015287fbb..b02721d7aa 100644 --- a/openfpga_flow/openfpga_timing_annotation/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm_tt.yml +++ b/openfpga_flow/openfpga_timing_annotation/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm_tt.yml @@ -54,7 +54,7 @@ DPRAM_128x8_CLK_TO_RADDR_DELAY: 509e-12 DPRAM_128x8_CLK_TO_DATA_IN_DELAY: 509e-12 DPRAM_128x8_CLK_TO_WEN_DELAY: 509e-12 DPRAM_128x8_CLK_TO_REN_DELAY: 509e-12 -DPRAM_128x8_CLK_TO_DATA_OUT_DELAY: 1.234e-9 +DPRAM_128x8_CLK_TO_DATA_OUT_DELAY: 6.73e-9 MEMORY_WADDR_TO_BRAM_WADDR_DELAY: 132e-12 MEMORY_RADDR_TO_BRAM_RADDR_DELAY: 132e-12 diff --git a/openfpga_flow/openfpga_timing_annotation/k6_frac_N10_tileable_adder_chain_dpram1K_fracff_skywater130nm_tt.yml b/openfpga_flow/openfpga_timing_annotation/k6_frac_N10_tileable_adder_chain_dpram1K_fracff_skywater130nm_tt.yml index 4d1136b15d..985f9eb5bc 100644 --- a/openfpga_flow/openfpga_timing_annotation/k6_frac_N10_tileable_adder_chain_dpram1K_fracff_skywater130nm_tt.yml +++ b/openfpga_flow/openfpga_timing_annotation/k6_frac_N10_tileable_adder_chain_dpram1K_fracff_skywater130nm_tt.yml @@ -37,7 +37,7 @@ DPRAM_128x8_CLK_TO_RADDR_DELAY: 509e-12 DPRAM_128x8_CLK_TO_DATA_IN_DELAY: 509e-12 DPRAM_128x8_CLK_TO_WEN_DELAY: 509e-12 DPRAM_128x8_CLK_TO_REN_DELAY: 509e-12 -DPRAM_128x8_CLK_TO_DATA_OUT_DELAY: 1.234e-9 +DPRAM_128x8_CLK_TO_DATA_OUT_DELAY: 6.73e-9 MEMORY_WADDR_TO_BRAM_WADDR_DELAY: 132e-12 MEMORY_RADDR_TO_BRAM_RADDR_DELAY: 132e-12 From 0783072be78a1df14b407ba367d6dc0bfc7d7c8b Mon Sep 17 00:00:00 2001 From: Andrew Pond Date: Mon, 16 Aug 2021 16:12:51 -0600 Subject: [PATCH 15/22] fixed errors --- .../micro_benchmark_reg_test.sh | 13 +++++++------ .../benchmark_sweep/processor/config/task.conf | 3 +++ .../benchmark_sweep/signal_gen/config/task.conf | 1 + ...der_chain_dpram1K_dsp18_fracff_skywater130nm.xml | 4 ++-- 4 files changed, 13 insertions(+), 8 deletions(-) diff --git a/openfpga_flow/regression_test_scripts/micro_benchmark_reg_test.sh b/openfpga_flow/regression_test_scripts/micro_benchmark_reg_test.sh index 5f958e2617..57fae9f46f 100755 --- a/openfpga_flow/regression_test_scripts/micro_benchmark_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/micro_benchmark_reg_test.sh @@ -7,13 +7,14 @@ PYTHON_EXEC=python3.8 # OpenFPGA Shell with VPR8 ############################################## echo -e "Micro benchmark regression tests"; -run-task benchmark_sweep/counter --debug --show_thread_logs -run-task benchmark_sweep/mac_units --debug --show_thread_logs +# run-task benchmark_sweep/counter --debug --show_thread_logs +# run-task benchmark_sweep/mac_units --debug --show_thread_logs -# Verify MCNC big20 benchmark suite with ModelSim -# Please make sure you have ModelSim installed in the environment -# Otherwise, it will fail -run-task benchmark_sweep/mcnc_big20 --debug --show_thread_logs +# # Verify MCNC big20 benchmark suite with ModelSim +# # Please make sure you have ModelSim installed in the environment +# # Otherwise, it will fail +# run-task benchmark_sweep/mcnc_big20 --debug --show_thread_logs #python3 openfpga_flow/scripts/run_modelsim.py mcnc_big20 --run_sim run-task benchmark_sweep/signal_gen --debug --show_thread_logs +run-task benchmark_sweep/processor --debug --show_thread_logs diff --git a/openfpga_flow/tasks/benchmark_sweep/processor/config/task.conf b/openfpga_flow/tasks/benchmark_sweep/processor/config/task.conf index bf24a2cf6d..ea252027f9 100644 --- a/openfpga_flow/tasks/benchmark_sweep/processor/config/task.conf +++ b/openfpga_flow/tasks/benchmark_sweep/processor/config/task.conf @@ -27,10 +27,13 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_cha [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/processor/picorv32/picorv32.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/processor/vexriscv/vexriscv_small.v [SYNTHESIS_PARAM] bench0_top = picorv32 bench0_chan_width = 300 +bench1_top = VexRiscv +bench1_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] end_flow_with_test= diff --git a/openfpga_flow/tasks/benchmark_sweep/signal_gen/config/task.conf b/openfpga_flow/tasks/benchmark_sweep/signal_gen/config/task.conf index 9ada9e960c..f246a8cf17 100644 --- a/openfpga_flow/tasks/benchmark_sweep/signal_gen/config/task.conf +++ b/openfpga_flow/tasks/benchmark_sweep/signal_gen/config/task.conf @@ -20,6 +20,7 @@ openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scrip openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml openfpga_vpr_device_layout= +openfpga_clock_modeling=ideal openfpga_fast_configuration= [ARCHITECTURES] diff --git a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm.xml index 44907b68f3..345be7c8ed 100644 --- a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm.xml +++ b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm.xml @@ -269,8 +269,8 @@ memory.clk - memory.waddr[4:0] memory.raddr[4:0] memory.data_in[3:0] memory.wen memory.data_out[3:0] - memory.waddr[9:5] memory.raddr[9:5] memory.data_in[7:4] memory.ren memory.data_out[7:4] + memory.waddr[2:0] memory.raddr[3:0] memory.data_in[3:0] memory.wen memory.data_out[3:0] + memory.waddr[6:3] memory.raddr[6:4] memory.data_in[7:4] memory.ren memory.data_out[7:4] From cebcdba4d448876e8eb611d65a04347dbf0a3446 Mon Sep 17 00:00:00 2001 From: Andrew Pond Date: Tue, 28 Sep 2021 13:32:41 -0600 Subject: [PATCH 16/22] added fpgatoolperf vexriscv src --- .../benchmarks/processor/vexriscv/VexRiscv.v | 5760 +++++++++++++++++ .../vexriscv/vexriscv-verilog_wrap.v | 64 + .../processor/{vexriscv => }/vexriscv_large.v | 0 .../processor/{vexriscv => }/vexriscv_linux.v | 0 .../processor/{vexriscv => }/vexriscv_small.v | 0 .../misc/fpgaflow_default_tool_path.conf | 23 +- .../iwls_benchmark_example_script.openfpga | 2 +- .../common/dpram_8K_bram.txt | 18 + .../common/dpram_8K_bram_map.v | 21 + ...am1K_dsp18_fracff_skywater130nm_cell_sim.v | 220 + ...ram1K_dsp18_fracff_skywater130nm_dff_map.v | 48 + ...am8K_dsp18_fracff_skywater130nm_cell_sim.v | 220 + ...ram8K_dsp18_fracff_skywater130nm_dff_map.v | 48 + 13 files changed, 6415 insertions(+), 9 deletions(-) create mode 100644 openfpga_flow/benchmarks/processor/vexriscv/VexRiscv.v create mode 100644 openfpga_flow/benchmarks/processor/vexriscv/vexriscv-verilog_wrap.v rename openfpga_flow/benchmarks/processor/{vexriscv => }/vexriscv_large.v (100%) rename openfpga_flow/benchmarks/processor/{vexriscv => }/vexriscv_linux.v (100%) rename openfpga_flow/benchmarks/processor/{vexriscv => }/vexriscv_small.v (100%) create mode 100644 openfpga_flow/openfpga_yosys_techlib/common/dpram_8K_bram.txt create mode 100644 openfpga_flow/openfpga_yosys_techlib/common/dpram_8K_bram_map.v create mode 100644 openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm/k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm_cell_sim.v create mode 100644 openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm/k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm_dff_map.v create mode 100644 openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_adder_chain_dpram8K_dsp18_fracff_skywater130nm/k4_frac_N8_tileable_adder_chain_dpram8K_dsp18_fracff_skywater130nm_cell_sim.v create mode 100644 openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_adder_chain_dpram8K_dsp18_fracff_skywater130nm/k4_frac_N8_tileable_adder_chain_dpram8K_dsp18_fracff_skywater130nm_dff_map.v diff --git a/openfpga_flow/benchmarks/processor/vexriscv/VexRiscv.v b/openfpga_flow/benchmarks/processor/vexriscv/VexRiscv.v new file mode 100644 index 0000000000..596468d91d --- /dev/null +++ b/openfpga_flow/benchmarks/processor/vexriscv/VexRiscv.v @@ -0,0 +1,5760 @@ +// Generator : SpinalHDL v1.3.5 git head : f0505d24810c8661a24530409359554b7cfa271a +// Date : 09/06/2019, 12:33:14 +// Component : VexRiscv + + +`define Src1CtrlEnum_defaultEncoding_type [1:0] +`define Src1CtrlEnum_defaultEncoding_RS 2'b00 +`define Src1CtrlEnum_defaultEncoding_IMU 2'b01 +`define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10 +`define Src1CtrlEnum_defaultEncoding_URS1 2'b11 + +`define AluBitwiseCtrlEnum_defaultEncoding_type [1:0] +`define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 2'b00 +`define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01 +`define AluBitwiseCtrlEnum_defaultEncoding_AND_1 2'b10 + +`define EnvCtrlEnum_defaultEncoding_type [0:0] +`define EnvCtrlEnum_defaultEncoding_NONE 1'b0 +`define EnvCtrlEnum_defaultEncoding_XRET 1'b1 + +`define BranchCtrlEnum_defaultEncoding_type [1:0] +`define BranchCtrlEnum_defaultEncoding_INC 2'b00 +`define BranchCtrlEnum_defaultEncoding_B 2'b01 +`define BranchCtrlEnum_defaultEncoding_JAL 2'b10 +`define BranchCtrlEnum_defaultEncoding_JALR 2'b11 + +`define Src2CtrlEnum_defaultEncoding_type [1:0] +`define Src2CtrlEnum_defaultEncoding_RS 2'b00 +`define Src2CtrlEnum_defaultEncoding_IMI 2'b01 +`define Src2CtrlEnum_defaultEncoding_IMS 2'b10 +`define Src2CtrlEnum_defaultEncoding_PC 2'b11 + +`define AluCtrlEnum_defaultEncoding_type [1:0] +`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00 +`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01 +`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10 + +`define ShiftCtrlEnum_defaultEncoding_type [1:0] +`define ShiftCtrlEnum_defaultEncoding_DISABLE_1 2'b00 +`define ShiftCtrlEnum_defaultEncoding_SLL_1 2'b01 +`define ShiftCtrlEnum_defaultEncoding_SRL_1 2'b10 +`define ShiftCtrlEnum_defaultEncoding_SRA_1 2'b11 + +module InstructionCache ( + input io_flush, + input io_cpu_prefetch_isValid, + output reg io_cpu_prefetch_haltIt, + input [31:0] io_cpu_prefetch_pc, + input io_cpu_fetch_isValid, + input io_cpu_fetch_isStuck, + input io_cpu_fetch_isRemoved, + input [31:0] io_cpu_fetch_pc, + output [31:0] io_cpu_fetch_data, + input io_cpu_fetch_dataBypassValid, + input [31:0] io_cpu_fetch_dataBypass, + output io_cpu_fetch_mmuBus_cmd_isValid, + output [31:0] io_cpu_fetch_mmuBus_cmd_virtualAddress, + output io_cpu_fetch_mmuBus_cmd_bypassTranslation, + input [31:0] io_cpu_fetch_mmuBus_rsp_physicalAddress, + input io_cpu_fetch_mmuBus_rsp_isIoAccess, + input io_cpu_fetch_mmuBus_rsp_allowRead, + input io_cpu_fetch_mmuBus_rsp_allowWrite, + input io_cpu_fetch_mmuBus_rsp_allowExecute, + input io_cpu_fetch_mmuBus_rsp_exception, + input io_cpu_fetch_mmuBus_rsp_refilling, + output io_cpu_fetch_mmuBus_end, + input io_cpu_fetch_mmuBus_busy, + output [31:0] io_cpu_fetch_physicalAddress, + output io_cpu_fetch_haltIt, + input io_cpu_decode_isValid, + input io_cpu_decode_isStuck, + input [31:0] io_cpu_decode_pc, + output [31:0] io_cpu_decode_physicalAddress, + output [31:0] io_cpu_decode_data, + output io_cpu_decode_cacheMiss, + output io_cpu_decode_error, + output io_cpu_decode_mmuRefilling, + output io_cpu_decode_mmuException, + input io_cpu_decode_isUser, + input io_cpu_fill_valid, + input [31:0] io_cpu_fill_payload, + output io_mem_cmd_valid, + input io_mem_cmd_ready, + output [31:0] io_mem_cmd_payload_address, + output [2:0] io_mem_cmd_payload_size, + input io_mem_rsp_valid, + input [31:0] io_mem_rsp_payload_data, + input io_mem_rsp_payload_error, + input clk, + input reset); + reg [21:0] _zz_10_; + reg [31:0] _zz_11_; + wire _zz_12_; + wire _zz_13_; + wire [0:0] _zz_14_; + wire [0:0] _zz_15_; + wire [21:0] _zz_16_; + reg _zz_1_; + reg _zz_2_; + reg lineLoader_fire; + reg lineLoader_valid; + reg [31:0] lineLoader_address; + reg lineLoader_hadError; + reg lineLoader_flushPending; + reg [7:0] lineLoader_flushCounter; + reg _zz_3_; + reg lineLoader_cmdSent; + reg lineLoader_wayToAllocate_willIncrement; + wire lineLoader_wayToAllocate_willClear; + wire lineLoader_wayToAllocate_willOverflowIfInc; + wire lineLoader_wayToAllocate_willOverflow; + reg [2:0] lineLoader_wordIndex; + wire lineLoader_write_tag_0_valid; + wire [6:0] lineLoader_write_tag_0_payload_address; + wire lineLoader_write_tag_0_payload_data_valid; + wire lineLoader_write_tag_0_payload_data_error; + wire [19:0] lineLoader_write_tag_0_payload_data_address; + wire lineLoader_write_data_0_valid; + wire [9:0] lineLoader_write_data_0_payload_address; + wire [31:0] lineLoader_write_data_0_payload_data; + wire _zz_4_; + wire [6:0] _zz_5_; + wire _zz_6_; + wire fetchStage_read_waysValues_0_tag_valid; + wire fetchStage_read_waysValues_0_tag_error; + wire [19:0] fetchStage_read_waysValues_0_tag_address; + wire [21:0] _zz_7_; + wire [9:0] _zz_8_; + wire _zz_9_; + wire [31:0] fetchStage_read_waysValues_0_data; + wire fetchStage_hit_hits_0; + wire fetchStage_hit_valid; + wire fetchStage_hit_error; + wire [31:0] fetchStage_hit_data; + wire [31:0] fetchStage_hit_word; + reg [31:0] io_cpu_fetch_data_regNextWhen; + reg [31:0] decodeStage_mmuRsp_physicalAddress; + reg decodeStage_mmuRsp_isIoAccess; + reg decodeStage_mmuRsp_allowRead; + reg decodeStage_mmuRsp_allowWrite; + reg decodeStage_mmuRsp_allowExecute; + reg decodeStage_mmuRsp_exception; + reg decodeStage_mmuRsp_refilling; + reg decodeStage_hit_valid; + reg decodeStage_hit_error; + (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127]; + (* ram_style = "block" *) reg [31:0] ways_0_datas [0:1023]; + assign _zz_12_ = (! lineLoader_flushCounter[7]); + assign _zz_13_ = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); + assign _zz_14_ = _zz_7_[0 : 0]; + assign _zz_15_ = _zz_7_[1 : 1]; + assign _zz_16_ = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; + always @ (posedge clk) begin + if(_zz_2_) begin + ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_16_; + end + end + + always @ (posedge clk) begin + if(_zz_6_) begin + _zz_10_ <= ways_0_tags[_zz_5_]; + end + end + + always @ (posedge clk) begin + if(_zz_1_) begin + ways_0_datas[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data; + end + end + + always @ (posedge clk) begin + if(_zz_9_) begin + _zz_11_ <= ways_0_datas[_zz_8_]; + end + end + + always @ (*) begin + _zz_1_ = 1'b0; + if(lineLoader_write_data_0_valid)begin + _zz_1_ = 1'b1; + end + end + + always @ (*) begin + _zz_2_ = 1'b0; + if(lineLoader_write_tag_0_valid)begin + _zz_2_ = 1'b1; + end + end + + assign io_cpu_fetch_haltIt = io_cpu_fetch_mmuBus_busy; + always @ (*) begin + lineLoader_fire = 1'b0; + if(io_mem_rsp_valid)begin + if((lineLoader_wordIndex == (3'b111)))begin + lineLoader_fire = 1'b1; + end + end + end + + always @ (*) begin + io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending); + if(_zz_12_)begin + io_cpu_prefetch_haltIt = 1'b1; + end + if((! _zz_3_))begin + io_cpu_prefetch_haltIt = 1'b1; + end + if(io_flush)begin + io_cpu_prefetch_haltIt = 1'b1; + end + end + + assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent)); + assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],(5'b00000)}; + assign io_mem_cmd_payload_size = (3'b101); + always @ (*) begin + lineLoader_wayToAllocate_willIncrement = 1'b0; + if(lineLoader_fire)begin + lineLoader_wayToAllocate_willIncrement = 1'b1; + end + end + + assign lineLoader_wayToAllocate_willClear = 1'b0; + assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1; + assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement); + assign _zz_4_ = 1'b1; + assign lineLoader_write_tag_0_valid = ((_zz_4_ && lineLoader_fire) || (! lineLoader_flushCounter[7])); + assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[7] ? lineLoader_address[11 : 5] : lineLoader_flushCounter[6 : 0]); + assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[7]; + assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error); + assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 12]; + assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && _zz_4_); + assign lineLoader_write_data_0_payload_address = {lineLoader_address[11 : 5],lineLoader_wordIndex}; + assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data; + assign _zz_5_ = io_cpu_prefetch_pc[11 : 5]; + assign _zz_6_ = (! io_cpu_fetch_isStuck); + assign _zz_7_ = _zz_10_; + assign fetchStage_read_waysValues_0_tag_valid = _zz_14_[0]; + assign fetchStage_read_waysValues_0_tag_error = _zz_15_[0]; + assign fetchStage_read_waysValues_0_tag_address = _zz_7_[21 : 2]; + assign _zz_8_ = io_cpu_prefetch_pc[11 : 2]; + assign _zz_9_ = (! io_cpu_fetch_isStuck); + assign fetchStage_read_waysValues_0_data = _zz_11_; + assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuBus_rsp_physicalAddress[31 : 12])); + assign fetchStage_hit_valid = (fetchStage_hit_hits_0 != (1'b0)); + assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error; + assign fetchStage_hit_data = fetchStage_read_waysValues_0_data; + assign fetchStage_hit_word = fetchStage_hit_data[31 : 0]; + assign io_cpu_fetch_data = (io_cpu_fetch_dataBypassValid ? io_cpu_fetch_dataBypass : fetchStage_hit_word); + assign io_cpu_decode_data = io_cpu_fetch_data_regNextWhen; + assign io_cpu_fetch_mmuBus_cmd_isValid = io_cpu_fetch_isValid; + assign io_cpu_fetch_mmuBus_cmd_virtualAddress = io_cpu_fetch_pc; + assign io_cpu_fetch_mmuBus_cmd_bypassTranslation = 1'b0; + assign io_cpu_fetch_mmuBus_end = ((! io_cpu_fetch_isStuck) || io_cpu_fetch_isRemoved); + assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuBus_rsp_physicalAddress; + assign io_cpu_decode_cacheMiss = (! decodeStage_hit_valid); + assign io_cpu_decode_error = decodeStage_hit_error; + assign io_cpu_decode_mmuRefilling = decodeStage_mmuRsp_refilling; + assign io_cpu_decode_mmuException = ((! decodeStage_mmuRsp_refilling) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute))); + assign io_cpu_decode_physicalAddress = decodeStage_mmuRsp_physicalAddress; + always @ (posedge clk) begin + if(reset) begin + lineLoader_valid <= 1'b0; + lineLoader_hadError <= 1'b0; + lineLoader_flushPending <= 1'b1; + lineLoader_cmdSent <= 1'b0; + lineLoader_wordIndex <= (3'b000); + end else begin + if(lineLoader_fire)begin + lineLoader_valid <= 1'b0; + end + if(lineLoader_fire)begin + lineLoader_hadError <= 1'b0; + end + if(io_cpu_fill_valid)begin + lineLoader_valid <= 1'b1; + end + if(io_flush)begin + lineLoader_flushPending <= 1'b1; + end + if(_zz_13_)begin + lineLoader_flushPending <= 1'b0; + end + if((io_mem_cmd_valid && io_mem_cmd_ready))begin + lineLoader_cmdSent <= 1'b1; + end + if(lineLoader_fire)begin + lineLoader_cmdSent <= 1'b0; + end + if(io_mem_rsp_valid)begin + lineLoader_wordIndex <= (lineLoader_wordIndex + (3'b001)); + if(io_mem_rsp_payload_error)begin + lineLoader_hadError <= 1'b1; + end + end + end + end + + always @ (posedge clk) begin + if(io_cpu_fill_valid)begin + lineLoader_address <= io_cpu_fill_payload; + end + if(_zz_12_)begin + lineLoader_flushCounter <= (lineLoader_flushCounter + (8'b00000001)); + end + _zz_3_ <= lineLoader_flushCounter[7]; + if(_zz_13_)begin + lineLoader_flushCounter <= (8'b00000000); + end + if((! io_cpu_decode_isStuck))begin + io_cpu_fetch_data_regNextWhen <= io_cpu_fetch_data; + end + if((! io_cpu_decode_isStuck))begin + decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuBus_rsp_physicalAddress; + decodeStage_mmuRsp_isIoAccess <= io_cpu_fetch_mmuBus_rsp_isIoAccess; + decodeStage_mmuRsp_allowRead <= io_cpu_fetch_mmuBus_rsp_allowRead; + decodeStage_mmuRsp_allowWrite <= io_cpu_fetch_mmuBus_rsp_allowWrite; + decodeStage_mmuRsp_allowExecute <= io_cpu_fetch_mmuBus_rsp_allowExecute; + decodeStage_mmuRsp_exception <= io_cpu_fetch_mmuBus_rsp_exception; + decodeStage_mmuRsp_refilling <= io_cpu_fetch_mmuBus_rsp_refilling; + end + if((! io_cpu_decode_isStuck))begin + decodeStage_hit_valid <= fetchStage_hit_valid; + end + if((! io_cpu_decode_isStuck))begin + decodeStage_hit_error <= fetchStage_hit_error; + end + end + +endmodule + +module DataCache ( + input io_cpu_execute_isValid, + input [31:0] io_cpu_execute_address, + input io_cpu_execute_args_wr, + input [31:0] io_cpu_execute_args_data, + input [1:0] io_cpu_execute_args_size, + input io_cpu_memory_isValid, + input io_cpu_memory_isStuck, + input io_cpu_memory_isRemoved, + output io_cpu_memory_isWrite, + input [31:0] io_cpu_memory_address, + output io_cpu_memory_mmuBus_cmd_isValid, + output [31:0] io_cpu_memory_mmuBus_cmd_virtualAddress, + output io_cpu_memory_mmuBus_cmd_bypassTranslation, + input [31:0] io_cpu_memory_mmuBus_rsp_physicalAddress, + input io_cpu_memory_mmuBus_rsp_isIoAccess, + input io_cpu_memory_mmuBus_rsp_allowRead, + input io_cpu_memory_mmuBus_rsp_allowWrite, + input io_cpu_memory_mmuBus_rsp_allowExecute, + input io_cpu_memory_mmuBus_rsp_exception, + input io_cpu_memory_mmuBus_rsp_refilling, + output io_cpu_memory_mmuBus_end, + input io_cpu_memory_mmuBus_busy, + input io_cpu_writeBack_isValid, + input io_cpu_writeBack_isStuck, + input io_cpu_writeBack_isUser, + output reg io_cpu_writeBack_haltIt, + output io_cpu_writeBack_isWrite, + output reg [31:0] io_cpu_writeBack_data, + input [31:0] io_cpu_writeBack_address, + output io_cpu_writeBack_mmuException, + output io_cpu_writeBack_unalignedAccess, + output reg io_cpu_writeBack_accessError, + output reg io_cpu_redo, + input io_cpu_flush_valid, + output reg io_cpu_flush_ready, + output reg io_mem_cmd_valid, + input io_mem_cmd_ready, + output reg io_mem_cmd_payload_wr, + output reg [31:0] io_mem_cmd_payload_address, + output [31:0] io_mem_cmd_payload_data, + output [3:0] io_mem_cmd_payload_mask, + output reg [2:0] io_mem_cmd_payload_length, + output reg io_mem_cmd_payload_last, + input io_mem_rsp_valid, + input [31:0] io_mem_rsp_payload_data, + input io_mem_rsp_payload_error, + input clk, + input reset); + reg [21:0] _zz_10_; + reg [31:0] _zz_11_; + wire _zz_12_; + wire _zz_13_; + wire _zz_14_; + wire _zz_15_; + wire _zz_16_; + wire _zz_17_; + wire [0:0] _zz_18_; + wire [0:0] _zz_19_; + wire [0:0] _zz_20_; + wire [2:0] _zz_21_; + wire [1:0] _zz_22_; + wire [21:0] _zz_23_; + reg _zz_1_; + reg _zz_2_; + wire haltCpu; + reg tagsReadCmd_valid; + reg [6:0] tagsReadCmd_payload; + reg tagsWriteCmd_valid; + reg [0:0] tagsWriteCmd_payload_way; + reg [6:0] tagsWriteCmd_payload_address; + reg tagsWriteCmd_payload_data_valid; + reg tagsWriteCmd_payload_data_error; + reg [19:0] tagsWriteCmd_payload_data_address; + reg tagsWriteLastCmd_valid; + reg [0:0] tagsWriteLastCmd_payload_way; + reg [6:0] tagsWriteLastCmd_payload_address; + reg tagsWriteLastCmd_payload_data_valid; + reg tagsWriteLastCmd_payload_data_error; + reg [19:0] tagsWriteLastCmd_payload_data_address; + reg dataReadCmd_valid; + reg [9:0] dataReadCmd_payload; + reg dataWriteCmd_valid; + reg [0:0] dataWriteCmd_payload_way; + reg [9:0] dataWriteCmd_payload_address; + reg [31:0] dataWriteCmd_payload_data; + reg [3:0] dataWriteCmd_payload_mask; + wire _zz_3_; + wire ways_0_tagsReadRsp_valid; + wire ways_0_tagsReadRsp_error; + wire [19:0] ways_0_tagsReadRsp_address; + wire [21:0] _zz_4_; + wire _zz_5_; + wire [31:0] ways_0_dataReadRsp; + reg [3:0] _zz_6_; + wire [3:0] stage0_mask; + wire [0:0] stage0_colisions; + reg stageA_request_wr; + reg [31:0] stageA_request_data; + reg [1:0] stageA_request_size; + reg [3:0] stageA_mask; + wire stageA_wayHits_0; + reg [0:0] stage0_colisions_regNextWhen; + wire [0:0] _zz_7_; + wire [0:0] stageA_colisions; + reg stageB_request_wr; + reg [31:0] stageB_request_data; + reg [1:0] stageB_request_size; + reg stageB_mmuRspFreeze; + reg [31:0] stageB_mmuRsp_physicalAddress; + reg stageB_mmuRsp_isIoAccess; + reg stageB_mmuRsp_allowRead; + reg stageB_mmuRsp_allowWrite; + reg stageB_mmuRsp_allowExecute; + reg stageB_mmuRsp_exception; + reg stageB_mmuRsp_refilling; + reg stageB_tagsReadRsp_0_valid; + reg stageB_tagsReadRsp_0_error; + reg [19:0] stageB_tagsReadRsp_0_address; + reg [31:0] stageB_dataReadRsp_0; + wire [0:0] _zz_8_; + reg [0:0] stageB_waysHits; + wire stageB_waysHit; + wire [31:0] stageB_dataMux; + reg [3:0] stageB_mask; + reg [0:0] stageB_colisions; + reg stageB_loaderValid; + reg stageB_flusher_valid; + wire [31:0] stageB_requestDataBypass; + wire stageB_isAmo; + reg stageB_memCmdSent; + wire [0:0] _zz_9_; + reg loader_valid; + reg loader_counter_willIncrement; + wire loader_counter_willClear; + reg [2:0] loader_counter_valueNext; + reg [2:0] loader_counter_value; + wire loader_counter_willOverflowIfInc; + wire loader_counter_willOverflow; + reg [0:0] loader_waysAllocator; + reg loader_error; + (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol0 [0:1023]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol1 [0:1023]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol2 [0:1023]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol3 [0:1023]; + reg [7:0] _zz_24_; + reg [7:0] _zz_25_; + reg [7:0] _zz_26_; + reg [7:0] _zz_27_; + assign _zz_12_ = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck)); + assign _zz_13_ = (((stageB_mmuRsp_refilling || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess); + assign _zz_14_ = (stageB_waysHit || (stageB_request_wr && (! stageB_isAmo))); + assign _zz_15_ = (loader_valid && io_mem_rsp_valid); + assign _zz_16_ = ((((io_cpu_flush_valid && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo)); + assign _zz_17_ = ((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze)); + assign _zz_18_ = _zz_4_[0 : 0]; + assign _zz_19_ = _zz_4_[1 : 1]; + assign _zz_20_ = loader_counter_willIncrement; + assign _zz_21_ = {2'd0, _zz_20_}; + assign _zz_22_ = {loader_waysAllocator,loader_waysAllocator[0]}; + assign _zz_23_ = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; + always @ (posedge clk) begin + if(_zz_2_) begin + ways_0_tags[tagsWriteCmd_payload_address] <= _zz_23_; + end + end + + always @ (posedge clk) begin + if(_zz_3_) begin + _zz_10_ <= ways_0_tags[tagsReadCmd_payload]; + end + end + + always @ (*) begin + _zz_11_ = {_zz_27_, _zz_26_, _zz_25_, _zz_24_}; + end + always @ (posedge clk) begin + if(dataWriteCmd_payload_mask[0] && _zz_1_) begin + ways_0_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0]; + end + if(dataWriteCmd_payload_mask[1] && _zz_1_) begin + ways_0_data_symbol1[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[15 : 8]; + end + if(dataWriteCmd_payload_mask[2] && _zz_1_) begin + ways_0_data_symbol2[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[23 : 16]; + end + if(dataWriteCmd_payload_mask[3] && _zz_1_) begin + ways_0_data_symbol3[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[31 : 24]; + end + end + + always @ (posedge clk) begin + if(_zz_5_) begin + _zz_24_ <= ways_0_data_symbol0[dataReadCmd_payload]; + _zz_25_ <= ways_0_data_symbol1[dataReadCmd_payload]; + _zz_26_ <= ways_0_data_symbol2[dataReadCmd_payload]; + _zz_27_ <= ways_0_data_symbol3[dataReadCmd_payload]; + end + end + + always @ (*) begin + _zz_1_ = 1'b0; + if((dataWriteCmd_valid && dataWriteCmd_payload_way[0]))begin + _zz_1_ = 1'b1; + end + end + + always @ (*) begin + _zz_2_ = 1'b0; + if((tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]))begin + _zz_2_ = 1'b1; + end + end + + assign haltCpu = 1'b0; + assign _zz_3_ = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); + assign _zz_4_ = _zz_10_; + assign ways_0_tagsReadRsp_valid = _zz_18_[0]; + assign ways_0_tagsReadRsp_error = _zz_19_[0]; + assign ways_0_tagsReadRsp_address = _zz_4_[21 : 2]; + assign _zz_5_ = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); + assign ways_0_dataReadRsp = _zz_11_; + always @ (*) begin + tagsReadCmd_valid = 1'b0; + if(_zz_12_)begin + tagsReadCmd_valid = 1'b1; + end + end + + always @ (*) begin + tagsReadCmd_payload = (7'bxxxxxxx); + if(_zz_12_)begin + tagsReadCmd_payload = io_cpu_execute_address[11 : 5]; + end + end + + always @ (*) begin + dataReadCmd_valid = 1'b0; + if(_zz_12_)begin + dataReadCmd_valid = 1'b1; + end + end + + always @ (*) begin + dataReadCmd_payload = (10'bxxxxxxxxxx); + if(_zz_12_)begin + dataReadCmd_payload = io_cpu_execute_address[11 : 2]; + end + end + + always @ (*) begin + tagsWriteCmd_valid = 1'b0; + if(stageB_flusher_valid)begin + tagsWriteCmd_valid = stageB_flusher_valid; + end + if(_zz_13_)begin + tagsWriteCmd_valid = 1'b0; + end + if(loader_counter_willOverflow)begin + tagsWriteCmd_valid = 1'b1; + end + end + + always @ (*) begin + tagsWriteCmd_payload_way = (1'bx); + if(stageB_flusher_valid)begin + tagsWriteCmd_payload_way = (1'b1); + end + if(loader_counter_willOverflow)begin + tagsWriteCmd_payload_way = loader_waysAllocator; + end + end + + always @ (*) begin + tagsWriteCmd_payload_address = (7'bxxxxxxx); + if(stageB_flusher_valid)begin + tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; + end + if(loader_counter_willOverflow)begin + tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; + end + end + + always @ (*) begin + tagsWriteCmd_payload_data_valid = 1'bx; + if(stageB_flusher_valid)begin + tagsWriteCmd_payload_data_valid = 1'b0; + end + if(loader_counter_willOverflow)begin + tagsWriteCmd_payload_data_valid = 1'b1; + end + end + + always @ (*) begin + tagsWriteCmd_payload_data_error = 1'bx; + if(loader_counter_willOverflow)begin + tagsWriteCmd_payload_data_error = (loader_error || io_mem_rsp_payload_error); + end + end + + always @ (*) begin + tagsWriteCmd_payload_data_address = (20'bxxxxxxxxxxxxxxxxxxxx); + if(loader_counter_willOverflow)begin + tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 12]; + end + end + + always @ (*) begin + dataWriteCmd_valid = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_mmuRsp_isIoAccess) begin + if(_zz_14_)begin + if((stageB_request_wr && stageB_waysHit))begin + dataWriteCmd_valid = 1'b1; + end + end + end + end + if(_zz_13_)begin + dataWriteCmd_valid = 1'b0; + end + if(_zz_15_)begin + dataWriteCmd_valid = 1'b1; + end + end + + always @ (*) begin + dataWriteCmd_payload_way = (1'bx); + if(io_cpu_writeBack_isValid)begin + if(! stageB_mmuRsp_isIoAccess) begin + if(_zz_14_)begin + dataWriteCmd_payload_way = stageB_waysHits; + end + end + end + if(_zz_15_)begin + dataWriteCmd_payload_way = loader_waysAllocator; + end + end + + always @ (*) begin + dataWriteCmd_payload_address = (10'bxxxxxxxxxx); + if(io_cpu_writeBack_isValid)begin + if(! stageB_mmuRsp_isIoAccess) begin + if(_zz_14_)begin + dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 2]; + end + end + end + if(_zz_15_)begin + dataWriteCmd_payload_address = {stageB_mmuRsp_physicalAddress[11 : 5],loader_counter_value}; + end + end + + always @ (*) begin + dataWriteCmd_payload_data = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); + if(io_cpu_writeBack_isValid)begin + if(! stageB_mmuRsp_isIoAccess) begin + if(_zz_14_)begin + dataWriteCmd_payload_data = stageB_requestDataBypass; + end + end + end + if(_zz_15_)begin + dataWriteCmd_payload_data = io_mem_rsp_payload_data; + end + end + + always @ (*) begin + dataWriteCmd_payload_mask = (4'bxxxx); + if(io_cpu_writeBack_isValid)begin + if(! stageB_mmuRsp_isIoAccess) begin + if(_zz_14_)begin + dataWriteCmd_payload_mask = stageB_mask; + end + end + end + if(_zz_15_)begin + dataWriteCmd_payload_mask = (4'b1111); + end + end + + always @ (*) begin + case(io_cpu_execute_args_size) + 2'b00 : begin + _zz_6_ = (4'b0001); + end + 2'b01 : begin + _zz_6_ = (4'b0011); + end + default : begin + _zz_6_ = (4'b1111); + end + endcase + end + + assign stage0_mask = (_zz_6_ <<< io_cpu_execute_address[1 : 0]); + assign stage0_colisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == io_cpu_execute_address[11 : 2])) && ((stage0_mask & dataWriteCmd_payload_mask) != (4'b0000))); + assign io_cpu_memory_mmuBus_cmd_isValid = io_cpu_memory_isValid; + assign io_cpu_memory_mmuBus_cmd_virtualAddress = io_cpu_memory_address; + assign io_cpu_memory_mmuBus_cmd_bypassTranslation = 1'b0; + assign io_cpu_memory_mmuBus_end = ((! io_cpu_memory_isStuck) || io_cpu_memory_isRemoved); + assign io_cpu_memory_isWrite = stageA_request_wr; + assign stageA_wayHits_0 = ((io_cpu_memory_mmuBus_rsp_physicalAddress[31 : 12] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid); + assign _zz_7_[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == io_cpu_memory_address[11 : 2])) && ((stageA_mask & dataWriteCmd_payload_mask) != (4'b0000))); + assign stageA_colisions = (stage0_colisions_regNextWhen | _zz_7_); + always @ (*) begin + stageB_mmuRspFreeze = 1'b0; + if((stageB_loaderValid || loader_valid))begin + stageB_mmuRspFreeze = 1'b1; + end + end + + assign _zz_8_[0] = stageA_wayHits_0; + assign stageB_waysHit = (stageB_waysHits != (1'b0)); + assign stageB_dataMux = stageB_dataReadRsp_0; + always @ (*) begin + stageB_loaderValid = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_mmuRsp_isIoAccess) begin + if(! _zz_14_) begin + if(io_mem_cmd_ready)begin + stageB_loaderValid = 1'b1; + end + end + end + end + if(_zz_13_)begin + stageB_loaderValid = 1'b0; + end + end + + always @ (*) begin + io_cpu_writeBack_haltIt = io_cpu_writeBack_isValid; + if(stageB_flusher_valid)begin + io_cpu_writeBack_haltIt = 1'b1; + end + if(io_cpu_writeBack_isValid)begin + if(stageB_mmuRsp_isIoAccess)begin + if((stageB_request_wr ? io_mem_cmd_ready : io_mem_rsp_valid))begin + io_cpu_writeBack_haltIt = 1'b0; + end + end else begin + if(_zz_14_)begin + if(((! stageB_request_wr) || io_mem_cmd_ready))begin + io_cpu_writeBack_haltIt = 1'b0; + end + end + end + end + if(_zz_13_)begin + io_cpu_writeBack_haltIt = 1'b0; + end + end + + always @ (*) begin + io_cpu_flush_ready = 1'b0; + if(_zz_16_)begin + io_cpu_flush_ready = 1'b1; + end + end + + assign stageB_requestDataBypass = stageB_request_data; + assign stageB_isAmo = 1'b0; + always @ (*) begin + io_cpu_redo = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_mmuRsp_isIoAccess) begin + if(_zz_14_)begin + if((((! stageB_request_wr) || stageB_isAmo) && ((stageB_colisions & stageB_waysHits) != (1'b0))))begin + io_cpu_redo = 1'b1; + end + end + end + end + if((io_cpu_writeBack_isValid && stageB_mmuRsp_refilling))begin + io_cpu_redo = 1'b1; + end + if(loader_valid)begin + io_cpu_redo = 1'b1; + end + end + + always @ (*) begin + io_cpu_writeBack_accessError = 1'b0; + if(stageB_mmuRsp_isIoAccess)begin + io_cpu_writeBack_accessError = (io_mem_rsp_valid && io_mem_rsp_payload_error); + end else begin + io_cpu_writeBack_accessError = ((stageB_waysHits & _zz_9_) != (1'b0)); + end + end + + assign io_cpu_writeBack_mmuException = (io_cpu_writeBack_isValid && ((stageB_mmuRsp_exception || ((! stageB_mmuRsp_allowWrite) && stageB_request_wr)) || ((! stageB_mmuRsp_allowRead) && ((! stageB_request_wr) || stageB_isAmo)))); + assign io_cpu_writeBack_unalignedAccess = (io_cpu_writeBack_isValid && (((stageB_request_size == (2'b10)) && (stageB_mmuRsp_physicalAddress[1 : 0] != (2'b00))) || ((stageB_request_size == (2'b01)) && (stageB_mmuRsp_physicalAddress[0 : 0] != (1'b0))))); + assign io_cpu_writeBack_isWrite = stageB_request_wr; + always @ (*) begin + io_mem_cmd_valid = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(stageB_mmuRsp_isIoAccess)begin + io_mem_cmd_valid = (! stageB_memCmdSent); + end else begin + if(_zz_14_)begin + if(stageB_request_wr)begin + io_mem_cmd_valid = 1'b1; + end + end else begin + if((! stageB_memCmdSent))begin + io_mem_cmd_valid = 1'b1; + end + end + end + end + if(_zz_13_)begin + io_mem_cmd_valid = 1'b0; + end + end + + always @ (*) begin + io_mem_cmd_payload_address = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); + if(io_cpu_writeBack_isValid)begin + if(stageB_mmuRsp_isIoAccess)begin + io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],(2'b00)}; + end else begin + if(_zz_14_)begin + io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],(2'b00)}; + end else begin + io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 5],(5'b00000)}; + end + end + end + end + + always @ (*) begin + io_mem_cmd_payload_length = (3'bxxx); + if(io_cpu_writeBack_isValid)begin + if(stageB_mmuRsp_isIoAccess)begin + io_mem_cmd_payload_length = (3'b000); + end else begin + if(_zz_14_)begin + io_mem_cmd_payload_length = (3'b000); + end else begin + io_mem_cmd_payload_length = (3'b111); + end + end + end + end + + always @ (*) begin + io_mem_cmd_payload_last = 1'bx; + if(io_cpu_writeBack_isValid)begin + if(stageB_mmuRsp_isIoAccess)begin + io_mem_cmd_payload_last = 1'b1; + end else begin + if(_zz_14_)begin + io_mem_cmd_payload_last = 1'b1; + end else begin + io_mem_cmd_payload_last = 1'b1; + end + end + end + end + + always @ (*) begin + io_mem_cmd_payload_wr = stageB_request_wr; + if(io_cpu_writeBack_isValid)begin + if(! stageB_mmuRsp_isIoAccess) begin + if(! _zz_14_) begin + io_mem_cmd_payload_wr = 1'b0; + end + end + end + end + + assign io_mem_cmd_payload_mask = stageB_mask; + assign io_mem_cmd_payload_data = stageB_requestDataBypass; + always @ (*) begin + if(stageB_mmuRsp_isIoAccess)begin + io_cpu_writeBack_data = io_mem_rsp_payload_data; + end else begin + io_cpu_writeBack_data = stageB_dataMux; + end + end + + assign _zz_9_[0] = stageB_tagsReadRsp_0_error; + always @ (*) begin + loader_counter_willIncrement = 1'b0; + if(_zz_15_)begin + loader_counter_willIncrement = 1'b1; + end + end + + assign loader_counter_willClear = 1'b0; + assign loader_counter_willOverflowIfInc = (loader_counter_value == (3'b111)); + assign loader_counter_willOverflow = (loader_counter_willOverflowIfInc && loader_counter_willIncrement); + always @ (*) begin + loader_counter_valueNext = (loader_counter_value + _zz_21_); + if(loader_counter_willClear)begin + loader_counter_valueNext = (3'b000); + end + end + + always @ (posedge clk) begin + tagsWriteLastCmd_valid <= tagsWriteCmd_valid; + tagsWriteLastCmd_payload_way <= tagsWriteCmd_payload_way; + tagsWriteLastCmd_payload_address <= tagsWriteCmd_payload_address; + tagsWriteLastCmd_payload_data_valid <= tagsWriteCmd_payload_data_valid; + tagsWriteLastCmd_payload_data_error <= tagsWriteCmd_payload_data_error; + tagsWriteLastCmd_payload_data_address <= tagsWriteCmd_payload_data_address; + if((! io_cpu_memory_isStuck))begin + stageA_request_wr <= io_cpu_execute_args_wr; + stageA_request_data <= io_cpu_execute_args_data; + stageA_request_size <= io_cpu_execute_args_size; + end + if((! io_cpu_memory_isStuck))begin + stageA_mask <= stage0_mask; + end + if((! io_cpu_memory_isStuck))begin + stage0_colisions_regNextWhen <= stage0_colisions; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_request_wr <= stageA_request_wr; + stageB_request_data <= stageA_request_data; + stageB_request_size <= stageA_request_size; + end + if(_zz_17_)begin + stageB_mmuRsp_isIoAccess <= io_cpu_memory_mmuBus_rsp_isIoAccess; + stageB_mmuRsp_allowRead <= io_cpu_memory_mmuBus_rsp_allowRead; + stageB_mmuRsp_allowWrite <= io_cpu_memory_mmuBus_rsp_allowWrite; + stageB_mmuRsp_allowExecute <= io_cpu_memory_mmuBus_rsp_allowExecute; + stageB_mmuRsp_exception <= io_cpu_memory_mmuBus_rsp_exception; + stageB_mmuRsp_refilling <= io_cpu_memory_mmuBus_rsp_refilling; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_tagsReadRsp_0_valid <= ways_0_tagsReadRsp_valid; + stageB_tagsReadRsp_0_error <= ways_0_tagsReadRsp_error; + stageB_tagsReadRsp_0_address <= ways_0_tagsReadRsp_address; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_dataReadRsp_0 <= ways_0_dataReadRsp; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_waysHits <= _zz_8_; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_mask <= stageA_mask; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_colisions <= stageA_colisions; + end + if(!(! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))) begin + $display("ERROR writeBack stuck by another plugin is not allowed"); + end + end + + always @ (posedge clk) begin + if(reset) begin + stageB_flusher_valid <= 1'b1; + stageB_mmuRsp_physicalAddress <= (32'b00000000000000000000000000000000); + stageB_memCmdSent <= 1'b0; + loader_valid <= 1'b0; + loader_counter_value <= (3'b000); + loader_waysAllocator <= (1'b1); + loader_error <= 1'b0; + end else begin + if(_zz_17_)begin + stageB_mmuRsp_physicalAddress <= io_cpu_memory_mmuBus_rsp_physicalAddress; + end + if(stageB_flusher_valid)begin + if((stageB_mmuRsp_physicalAddress[11 : 5] != (7'b1111111)))begin + stageB_mmuRsp_physicalAddress[11 : 5] <= (stageB_mmuRsp_physicalAddress[11 : 5] + (7'b0000001)); + end else begin + stageB_flusher_valid <= 1'b0; + end + end + if(_zz_16_)begin + stageB_mmuRsp_physicalAddress[11 : 5] <= (7'b0000000); + stageB_flusher_valid <= 1'b1; + end + if(io_mem_cmd_ready)begin + stageB_memCmdSent <= 1'b1; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_memCmdSent <= 1'b0; + end + if(stageB_loaderValid)begin + loader_valid <= 1'b1; + end + loader_counter_value <= loader_counter_valueNext; + if(_zz_15_)begin + loader_error <= (loader_error || io_mem_rsp_payload_error); + end + if(loader_counter_willOverflow)begin + loader_valid <= 1'b0; + loader_waysAllocator <= _zz_22_[0:0]; + loader_error <= 1'b0; + end + end + end + +endmodule + +module VexRiscv ( + input [31:0] externalResetVector, + input timerInterrupt, + input softwareInterrupt, + input [31:0] externalInterruptArray, + output reg iBusWishbone_CYC, + output reg iBusWishbone_STB, + input iBusWishbone_ACK, + output iBusWishbone_WE, + output [29:0] iBusWishbone_ADR, + input [31:0] iBusWishbone_DAT_MISO, + output [31:0] iBusWishbone_DAT_MOSI, + output [3:0] iBusWishbone_SEL, + input iBusWishbone_ERR, + output [1:0] iBusWishbone_BTE, + output [2:0] iBusWishbone_CTI, + output dBusWishbone_CYC, + output dBusWishbone_STB, + input dBusWishbone_ACK, + output dBusWishbone_WE, + output [29:0] dBusWishbone_ADR, + input [31:0] dBusWishbone_DAT_MISO, + output [31:0] dBusWishbone_DAT_MOSI, + output [3:0] dBusWishbone_SEL, + input dBusWishbone_ERR, + output [1:0] dBusWishbone_BTE, + output [2:0] dBusWishbone_CTI, + input clk, + input reset); + wire _zz_221_; + wire _zz_222_; + wire _zz_223_; + wire _zz_224_; + wire _zz_225_; + wire [31:0] _zz_226_; + wire _zz_227_; + wire _zz_228_; + wire _zz_229_; + reg _zz_230_; + wire _zz_231_; + wire [31:0] _zz_232_; + wire _zz_233_; + wire [31:0] _zz_234_; + reg _zz_235_; + wire _zz_236_; + wire _zz_237_; + wire [31:0] _zz_238_; + wire _zz_239_; + wire _zz_240_; + reg [31:0] _zz_241_; + reg [31:0] _zz_242_; + reg [31:0] _zz_243_; + wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; + wire IBusCachedPlugin_cache_io_cpu_fetch_haltIt; + wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress; + wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_bypassTranslation; + wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_end; + wire IBusCachedPlugin_cache_io_cpu_decode_error; + wire IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling; + wire IBusCachedPlugin_cache_io_cpu_decode_mmuException; + wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_data; + wire IBusCachedPlugin_cache_io_cpu_decode_cacheMiss; + wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_physicalAddress; + wire IBusCachedPlugin_cache_io_mem_cmd_valid; + wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address; + wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size; + wire dataCache_1__io_cpu_memory_isWrite; + wire dataCache_1__io_cpu_memory_mmuBus_cmd_isValid; + wire [31:0] dataCache_1__io_cpu_memory_mmuBus_cmd_virtualAddress; + wire dataCache_1__io_cpu_memory_mmuBus_cmd_bypassTranslation; + wire dataCache_1__io_cpu_memory_mmuBus_end; + wire dataCache_1__io_cpu_writeBack_haltIt; + wire [31:0] dataCache_1__io_cpu_writeBack_data; + wire dataCache_1__io_cpu_writeBack_mmuException; + wire dataCache_1__io_cpu_writeBack_unalignedAccess; + wire dataCache_1__io_cpu_writeBack_accessError; + wire dataCache_1__io_cpu_writeBack_isWrite; + wire dataCache_1__io_cpu_flush_ready; + wire dataCache_1__io_cpu_redo; + wire dataCache_1__io_mem_cmd_valid; + wire dataCache_1__io_mem_cmd_payload_wr; + wire [31:0] dataCache_1__io_mem_cmd_payload_address; + wire [31:0] dataCache_1__io_mem_cmd_payload_data; + wire [3:0] dataCache_1__io_mem_cmd_payload_mask; + wire [2:0] dataCache_1__io_mem_cmd_payload_length; + wire dataCache_1__io_mem_cmd_payload_last; + wire _zz_244_; + wire _zz_245_; + wire _zz_246_; + wire _zz_247_; + wire _zz_248_; + wire _zz_249_; + wire _zz_250_; + wire _zz_251_; + wire _zz_252_; + wire _zz_253_; + wire _zz_254_; + wire _zz_255_; + wire _zz_256_; + wire _zz_257_; + wire [1:0] _zz_258_; + wire _zz_259_; + wire _zz_260_; + wire _zz_261_; + wire _zz_262_; + wire _zz_263_; + wire _zz_264_; + wire _zz_265_; + wire _zz_266_; + wire [1:0] _zz_267_; + wire _zz_268_; + wire _zz_269_; + wire _zz_270_; + wire _zz_271_; + wire _zz_272_; + wire _zz_273_; + wire _zz_274_; + wire [1:0] _zz_275_; + wire _zz_276_; + wire [1:0] _zz_277_; + wire [4:0] _zz_278_; + wire [2:0] _zz_279_; + wire [31:0] _zz_280_; + wire [11:0] _zz_281_; + wire [31:0] _zz_282_; + wire [19:0] _zz_283_; + wire [11:0] _zz_284_; + wire [31:0] _zz_285_; + wire [31:0] _zz_286_; + wire [19:0] _zz_287_; + wire [11:0] _zz_288_; + wire [2:0] _zz_289_; + wire [2:0] _zz_290_; + wire [0:0] _zz_291_; + wire [0:0] _zz_292_; + wire [0:0] _zz_293_; + wire [0:0] _zz_294_; + wire [0:0] _zz_295_; + wire [0:0] _zz_296_; + wire [0:0] _zz_297_; + wire [0:0] _zz_298_; + wire [0:0] _zz_299_; + wire [0:0] _zz_300_; + wire [0:0] _zz_301_; + wire [0:0] _zz_302_; + wire [0:0] _zz_303_; + wire [0:0] _zz_304_; + wire [0:0] _zz_305_; + wire [0:0] _zz_306_; + wire [0:0] _zz_307_; + wire [0:0] _zz_308_; + wire [2:0] _zz_309_; + wire [4:0] _zz_310_; + wire [11:0] _zz_311_; + wire [11:0] _zz_312_; + wire [31:0] _zz_313_; + wire [31:0] _zz_314_; + wire [31:0] _zz_315_; + wire [31:0] _zz_316_; + wire [31:0] _zz_317_; + wire [31:0] _zz_318_; + wire [31:0] _zz_319_; + wire [32:0] _zz_320_; + wire [31:0] _zz_321_; + wire [32:0] _zz_322_; + wire [11:0] _zz_323_; + wire [19:0] _zz_324_; + wire [11:0] _zz_325_; + wire [31:0] _zz_326_; + wire [31:0] _zz_327_; + wire [31:0] _zz_328_; + wire [11:0] _zz_329_; + wire [19:0] _zz_330_; + wire [11:0] _zz_331_; + wire [2:0] _zz_332_; + wire [1:0] _zz_333_; + wire [1:0] _zz_334_; + wire [51:0] _zz_335_; + wire [51:0] _zz_336_; + wire [51:0] _zz_337_; + wire [32:0] _zz_338_; + wire [51:0] _zz_339_; + wire [49:0] _zz_340_; + wire [51:0] _zz_341_; + wire [49:0] _zz_342_; + wire [51:0] _zz_343_; + wire [65:0] _zz_344_; + wire [65:0] _zz_345_; + wire [31:0] _zz_346_; + wire [31:0] _zz_347_; + wire [0:0] _zz_348_; + wire [5:0] _zz_349_; + wire [32:0] _zz_350_; + wire [32:0] _zz_351_; + wire [31:0] _zz_352_; + wire [31:0] _zz_353_; + wire [32:0] _zz_354_; + wire [32:0] _zz_355_; + wire [32:0] _zz_356_; + wire [0:0] _zz_357_; + wire [32:0] _zz_358_; + wire [0:0] _zz_359_; + wire [32:0] _zz_360_; + wire [0:0] _zz_361_; + wire [31:0] _zz_362_; + wire [0:0] _zz_363_; + wire [0:0] _zz_364_; + wire [0:0] _zz_365_; + wire [0:0] _zz_366_; + wire [0:0] _zz_367_; + wire [0:0] _zz_368_; + wire [26:0] _zz_369_; + wire _zz_370_; + wire _zz_371_; + wire [2:0] _zz_372_; + wire _zz_373_; + wire _zz_374_; + wire _zz_375_; + wire [31:0] _zz_376_; + wire [31:0] _zz_377_; + wire _zz_378_; + wire [0:0] _zz_379_; + wire [0:0] _zz_380_; + wire [31:0] _zz_381_; + wire [31:0] _zz_382_; + wire [0:0] _zz_383_; + wire [1:0] _zz_384_; + wire [0:0] _zz_385_; + wire [0:0] _zz_386_; + wire _zz_387_; + wire [0:0] _zz_388_; + wire [24:0] _zz_389_; + wire [31:0] _zz_390_; + wire [31:0] _zz_391_; + wire [31:0] _zz_392_; + wire [31:0] _zz_393_; + wire [31:0] _zz_394_; + wire [31:0] _zz_395_; + wire [31:0] _zz_396_; + wire _zz_397_; + wire _zz_398_; + wire [31:0] _zz_399_; + wire [31:0] _zz_400_; + wire [0:0] _zz_401_; + wire [0:0] _zz_402_; + wire [0:0] _zz_403_; + wire [0:0] _zz_404_; + wire _zz_405_; + wire [0:0] _zz_406_; + wire [22:0] _zz_407_; + wire [31:0] _zz_408_; + wire [31:0] _zz_409_; + wire [0:0] _zz_410_; + wire [3:0] _zz_411_; + wire [0:0] _zz_412_; + wire [0:0] _zz_413_; + wire [1:0] _zz_414_; + wire [1:0] _zz_415_; + wire _zz_416_; + wire [0:0] _zz_417_; + wire [19:0] _zz_418_; + wire [31:0] _zz_419_; + wire [31:0] _zz_420_; + wire [31:0] _zz_421_; + wire _zz_422_; + wire [0:0] _zz_423_; + wire [0:0] _zz_424_; + wire [31:0] _zz_425_; + wire [31:0] _zz_426_; + wire [31:0] _zz_427_; + wire [31:0] _zz_428_; + wire [31:0] _zz_429_; + wire [31:0] _zz_430_; + wire _zz_431_; + wire _zz_432_; + wire [0:0] _zz_433_; + wire [0:0] _zz_434_; + wire [2:0] _zz_435_; + wire [2:0] _zz_436_; + wire _zz_437_; + wire [0:0] _zz_438_; + wire [16:0] _zz_439_; + wire [31:0] _zz_440_; + wire [31:0] _zz_441_; + wire [31:0] _zz_442_; + wire [31:0] _zz_443_; + wire [31:0] _zz_444_; + wire [31:0] _zz_445_; + wire [31:0] _zz_446_; + wire [31:0] _zz_447_; + wire [31:0] _zz_448_; + wire [31:0] _zz_449_; + wire [31:0] _zz_450_; + wire _zz_451_; + wire [0:0] _zz_452_; + wire [0:0] _zz_453_; + wire [0:0] _zz_454_; + wire [0:0] _zz_455_; + wire [1:0] _zz_456_; + wire [1:0] _zz_457_; + wire _zz_458_; + wire [0:0] _zz_459_; + wire [14:0] _zz_460_; + wire [31:0] _zz_461_; + wire [31:0] _zz_462_; + wire [31:0] _zz_463_; + wire [31:0] _zz_464_; + wire [31:0] _zz_465_; + wire [31:0] _zz_466_; + wire [31:0] _zz_467_; + wire _zz_468_; + wire [0:0] _zz_469_; + wire [0:0] _zz_470_; + wire _zz_471_; + wire [0:0] _zz_472_; + wire [12:0] _zz_473_; + wire _zz_474_; + wire [0:0] _zz_475_; + wire [1:0] _zz_476_; + wire [31:0] _zz_477_; + wire [31:0] _zz_478_; + wire _zz_479_; + wire [0:0] _zz_480_; + wire [0:0] _zz_481_; + wire _zz_482_; + wire [0:0] _zz_483_; + wire [8:0] _zz_484_; + wire [31:0] _zz_485_; + wire [31:0] _zz_486_; + wire [31:0] _zz_487_; + wire [31:0] _zz_488_; + wire [31:0] _zz_489_; + wire [31:0] _zz_490_; + wire [31:0] _zz_491_; + wire [31:0] _zz_492_; + wire _zz_493_; + wire [0:0] _zz_494_; + wire [0:0] _zz_495_; + wire _zz_496_; + wire [0:0] _zz_497_; + wire [5:0] _zz_498_; + wire [31:0] _zz_499_; + wire [31:0] _zz_500_; + wire _zz_501_; + wire [0:0] _zz_502_; + wire [3:0] _zz_503_; + wire [0:0] _zz_504_; + wire [0:0] _zz_505_; + wire _zz_506_; + wire [0:0] _zz_507_; + wire [1:0] _zz_508_; + wire [31:0] _zz_509_; + wire _zz_510_; + wire [0:0] _zz_511_; + wire [0:0] _zz_512_; + wire [31:0] _zz_513_; + wire _zz_514_; + wire [0:0] _zz_515_; + wire [0:0] _zz_516_; + wire _zz_517_; + wire [0:0] _zz_518_; + wire [0:0] _zz_519_; + wire [0:0] _zz_520_; + wire [0:0] _zz_521_; + wire [31:0] _zz_522_; + wire [31:0] _zz_523_; + wire [31:0] _zz_524_; + wire [31:0] _zz_525_; + wire [31:0] _zz_526_; + wire [31:0] _zz_527_; + wire [31:0] _zz_528_; + wire [31:0] _zz_529_; + wire [31:0] _zz_530_; + wire _zz_531_; + wire [0:0] _zz_532_; + wire [11:0] _zz_533_; + wire [31:0] _zz_534_; + wire [31:0] _zz_535_; + wire [31:0] _zz_536_; + wire _zz_537_; + wire [0:0] _zz_538_; + wire [5:0] _zz_539_; + wire [31:0] _zz_540_; + wire [31:0] _zz_541_; + wire [31:0] _zz_542_; + wire _zz_543_; + wire _zz_544_; + wire _zz_545_; + wire _zz_546_; + wire _zz_547_; + wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; + wire `Src1CtrlEnum_defaultEncoding_type _zz_1_; + wire `Src1CtrlEnum_defaultEncoding_type _zz_2_; + wire `Src1CtrlEnum_defaultEncoding_type _zz_3_; + wire decode_MEMORY_MANAGMENT; + wire decode_CSR_READ_OPCODE; + wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_4_; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_5_; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_6_; + wire decode_CSR_WRITE_OPCODE; + wire decode_SRC2_FORCE_ZERO; + wire execute_BRANCH_DO; + wire [31:0] execute_SHIFT_RIGHT; + wire `EnvCtrlEnum_defaultEncoding_type _zz_7_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_8_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_9_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_10_; + wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_11_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_12_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_13_; + wire `BranchCtrlEnum_defaultEncoding_type _zz_14_; + wire `BranchCtrlEnum_defaultEncoding_type _zz_15_; + wire decode_IS_DIV; + wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; + wire `Src2CtrlEnum_defaultEncoding_type _zz_16_; + wire `Src2CtrlEnum_defaultEncoding_type _zz_17_; + wire `Src2CtrlEnum_defaultEncoding_type _zz_18_; + wire decode_IS_RS1_SIGNED; + wire decode_SRC_LESS_UNSIGNED; + wire memory_MEMORY_WR; + wire decode_MEMORY_WR; + wire decode_PREDICTION_HAD_BRANCHED2; + wire decode_IS_RS2_SIGNED; + wire [33:0] memory_MUL_HH; + wire [33:0] execute_MUL_HH; + wire [33:0] execute_MUL_HL; + wire decode_BYPASSABLE_EXECUTE_STAGE; + wire [1:0] memory_MEMORY_ADDRESS_LOW; + wire [1:0] execute_MEMORY_ADDRESS_LOW; + wire [31:0] execute_REGFILE_WRITE_DATA; + wire [51:0] memory_MUL_LOW; + wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_19_; + wire `AluCtrlEnum_defaultEncoding_type _zz_20_; + wire `AluCtrlEnum_defaultEncoding_type _zz_21_; + wire [31:0] execute_BRANCH_CALC; + wire [31:0] execute_MUL_LL; + wire decode_IS_CSR; + wire [31:0] memory_PC; + wire execute_BYPASSABLE_MEMORY_STAGE; + wire decode_BYPASSABLE_MEMORY_STAGE; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_22_; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_23_; + wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_24_; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_25_; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_26_; + wire [33:0] execute_MUL_LH; + wire [31:0] writeBack_FORMAL_PC_NEXT; + wire [31:0] memory_FORMAL_PC_NEXT; + wire [31:0] execute_FORMAL_PC_NEXT; + wire [31:0] decode_FORMAL_PC_NEXT; + wire memory_IS_MUL; + wire execute_IS_MUL; + wire decode_IS_MUL; + wire execute_IS_RS1_SIGNED; + wire execute_IS_DIV; + wire execute_IS_RS2_SIGNED; + wire memory_IS_DIV; + wire writeBack_IS_MUL; + wire [33:0] writeBack_MUL_HH; + wire [51:0] writeBack_MUL_LOW; + wire [33:0] memory_MUL_HL; + wire [33:0] memory_MUL_LH; + wire [31:0] memory_MUL_LL; + wire [51:0] _zz_27_; + wire [33:0] _zz_28_; + wire [33:0] _zz_29_; + wire [33:0] _zz_30_; + wire [31:0] _zz_31_; + wire execute_CSR_READ_OPCODE; + wire execute_CSR_WRITE_OPCODE; + wire execute_IS_CSR; + wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_32_; + wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_33_; + wire _zz_34_; + wire _zz_35_; + wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_36_; + wire [31:0] memory_BRANCH_CALC; + wire memory_BRANCH_DO; + wire [31:0] _zz_37_; + wire [31:0] execute_PC; + wire execute_PREDICTION_HAD_BRANCHED2; + wire _zz_38_; + wire [31:0] execute_RS1; + wire execute_BRANCH_COND_RESULT; + wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_39_; + wire _zz_40_; + wire _zz_41_; + wire decode_RS2_USE; + wire decode_RS1_USE; + reg [31:0] _zz_42_; + wire execute_REGFILE_WRITE_VALID; + wire execute_BYPASSABLE_EXECUTE_STAGE; + wire memory_REGFILE_WRITE_VALID; + wire [31:0] memory_INSTRUCTION; + wire memory_BYPASSABLE_MEMORY_STAGE; + wire writeBack_REGFILE_WRITE_VALID; + reg [31:0] decode_RS2; + reg [31:0] decode_RS1; + wire [31:0] memory_SHIFT_RIGHT; + reg [31:0] _zz_43_; + wire `ShiftCtrlEnum_defaultEncoding_type memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_44_; + wire [31:0] _zz_45_; + wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_46_; + wire _zz_47_; + wire [31:0] _zz_48_; + wire [31:0] _zz_49_; + wire execute_SRC_LESS_UNSIGNED; + wire execute_SRC2_FORCE_ZERO; + wire execute_SRC_USE_SUB_LESS; + wire [31:0] _zz_50_; + wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL; + wire `Src2CtrlEnum_defaultEncoding_type _zz_51_; + wire [31:0] _zz_52_; + wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL; + wire `Src1CtrlEnum_defaultEncoding_type _zz_53_; + wire [31:0] _zz_54_; + wire decode_SRC_USE_SUB_LESS; + wire decode_SRC_ADD_ZERO; + wire _zz_55_; + wire [31:0] execute_SRC_ADD_SUB; + wire execute_SRC_LESS; + wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_56_; + wire [31:0] _zz_57_; + wire [31:0] execute_SRC2; + wire [31:0] execute_SRC1; + wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_58_; + wire [31:0] _zz_59_; + wire _zz_60_; + reg _zz_61_; + wire [31:0] _zz_62_; + wire [31:0] _zz_63_; + wire [31:0] decode_INSTRUCTION_ANTICIPATED; + reg decode_REGFILE_WRITE_VALID; + wire decode_LEGAL_INSTRUCTION; + wire decode_INSTRUCTION_READY; + wire _zz_64_; + wire _zz_65_; + wire _zz_66_; + wire _zz_67_; + wire `BranchCtrlEnum_defaultEncoding_type _zz_68_; + wire _zz_69_; + wire _zz_70_; + wire _zz_71_; + wire _zz_72_; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_73_; + wire `Src2CtrlEnum_defaultEncoding_type _zz_74_; + wire _zz_75_; + wire _zz_76_; + wire _zz_77_; + wire _zz_78_; + wire _zz_79_; + wire _zz_80_; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_81_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_82_; + wire `Src1CtrlEnum_defaultEncoding_type _zz_83_; + wire _zz_84_; + wire _zz_85_; + wire _zz_86_; + wire `AluCtrlEnum_defaultEncoding_type _zz_87_; + wire _zz_88_; + reg [31:0] _zz_89_; + wire [1:0] writeBack_MEMORY_ADDRESS_LOW; + wire writeBack_MEMORY_WR; + wire [31:0] writeBack_REGFILE_WRITE_DATA; + wire writeBack_MEMORY_ENABLE; + wire [31:0] memory_REGFILE_WRITE_DATA; + wire memory_MEMORY_ENABLE; + wire [1:0] _zz_90_; + wire execute_MEMORY_MANAGMENT; + wire [31:0] execute_RS2; + wire execute_MEMORY_WR; + wire [31:0] execute_SRC_ADD; + wire execute_MEMORY_ENABLE; + wire [31:0] execute_INSTRUCTION; + wire decode_MEMORY_ENABLE; + wire decode_FLUSH_ALL; + reg IBusCachedPlugin_rsp_issueDetected; + reg _zz_91_; + reg _zz_92_; + reg _zz_93_; + wire [31:0] _zz_94_; + wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_95_; + wire [31:0] decode_INSTRUCTION; + reg [31:0] _zz_96_; + reg [31:0] _zz_97_; + wire [31:0] decode_PC; + wire [31:0] _zz_98_; + wire [31:0] _zz_99_; + wire [31:0] _zz_100_; + wire [31:0] writeBack_PC; + wire [31:0] writeBack_INSTRUCTION; + reg decode_arbitration_haltItself; + reg decode_arbitration_haltByOther; + reg decode_arbitration_removeIt; + wire decode_arbitration_flushAll; + wire decode_arbitration_isValid; + wire decode_arbitration_isStuck; + wire decode_arbitration_isStuckByOthers; + wire decode_arbitration_isFlushed; + wire decode_arbitration_isMoving; + wire decode_arbitration_isFiring; + reg execute_arbitration_haltItself; + wire execute_arbitration_haltByOther; + reg execute_arbitration_removeIt; + reg execute_arbitration_flushAll; + reg execute_arbitration_isValid; + wire execute_arbitration_isStuck; + wire execute_arbitration_isStuckByOthers; + wire execute_arbitration_isFlushed; + wire execute_arbitration_isMoving; + wire execute_arbitration_isFiring; + reg memory_arbitration_haltItself; + wire memory_arbitration_haltByOther; + reg memory_arbitration_removeIt; + reg memory_arbitration_flushAll; + reg memory_arbitration_isValid; + wire memory_arbitration_isStuck; + wire memory_arbitration_isStuckByOthers; + wire memory_arbitration_isFlushed; + wire memory_arbitration_isMoving; + wire memory_arbitration_isFiring; + reg writeBack_arbitration_haltItself; + wire writeBack_arbitration_haltByOther; + reg writeBack_arbitration_removeIt; + reg writeBack_arbitration_flushAll; + reg writeBack_arbitration_isValid; + wire writeBack_arbitration_isStuck; + wire writeBack_arbitration_isStuckByOthers; + wire writeBack_arbitration_isFlushed; + wire writeBack_arbitration_isMoving; + wire writeBack_arbitration_isFiring; + wire [31:0] lastStageInstruction /* verilator public */ ; + wire [31:0] lastStagePc /* verilator public */ ; + wire lastStageIsValid /* verilator public */ ; + wire lastStageIsFiring /* verilator public */ ; + reg IBusCachedPlugin_fetcherHalt; + wire IBusCachedPlugin_fetcherflushIt; + reg IBusCachedPlugin_incomingInstruction; + wire IBusCachedPlugin_predictionJumpInterface_valid; + (* keep , syn_keep *) wire [31:0] IBusCachedPlugin_pcs_4 /* synthesis syn_keep = 1 */ ; + reg IBusCachedPlugin_decodePrediction_cmd_hadBranch; + wire IBusCachedPlugin_decodePrediction_rsp_wasWrong; + wire IBusCachedPlugin_pcValids_0; + wire IBusCachedPlugin_pcValids_1; + wire IBusCachedPlugin_pcValids_2; + wire IBusCachedPlugin_pcValids_3; + wire IBusCachedPlugin_redoBranch_valid; + wire [31:0] IBusCachedPlugin_redoBranch_payload; + reg IBusCachedPlugin_decodeExceptionPort_valid; + reg [3:0] IBusCachedPlugin_decodeExceptionPort_payload_code; + wire [31:0] IBusCachedPlugin_decodeExceptionPort_payload_badAddr; + wire IBusCachedPlugin_mmuBus_cmd_isValid; + wire [31:0] IBusCachedPlugin_mmuBus_cmd_virtualAddress; + wire IBusCachedPlugin_mmuBus_cmd_bypassTranslation; + wire [31:0] IBusCachedPlugin_mmuBus_rsp_physicalAddress; + wire IBusCachedPlugin_mmuBus_rsp_isIoAccess; + wire IBusCachedPlugin_mmuBus_rsp_allowRead; + wire IBusCachedPlugin_mmuBus_rsp_allowWrite; + wire IBusCachedPlugin_mmuBus_rsp_allowExecute; + wire IBusCachedPlugin_mmuBus_rsp_exception; + wire IBusCachedPlugin_mmuBus_rsp_refilling; + wire IBusCachedPlugin_mmuBus_end; + wire IBusCachedPlugin_mmuBus_busy; + wire DBusCachedPlugin_mmuBus_cmd_isValid; + wire [31:0] DBusCachedPlugin_mmuBus_cmd_virtualAddress; + wire DBusCachedPlugin_mmuBus_cmd_bypassTranslation; + wire [31:0] DBusCachedPlugin_mmuBus_rsp_physicalAddress; + wire DBusCachedPlugin_mmuBus_rsp_isIoAccess; + wire DBusCachedPlugin_mmuBus_rsp_allowRead; + wire DBusCachedPlugin_mmuBus_rsp_allowWrite; + wire DBusCachedPlugin_mmuBus_rsp_allowExecute; + wire DBusCachedPlugin_mmuBus_rsp_exception; + wire DBusCachedPlugin_mmuBus_rsp_refilling; + wire DBusCachedPlugin_mmuBus_end; + wire DBusCachedPlugin_mmuBus_busy; + reg DBusCachedPlugin_redoBranch_valid; + wire [31:0] DBusCachedPlugin_redoBranch_payload; + reg DBusCachedPlugin_exceptionBus_valid; + reg [3:0] DBusCachedPlugin_exceptionBus_payload_code; + wire [31:0] DBusCachedPlugin_exceptionBus_payload_badAddr; + wire decodeExceptionPort_valid; + wire [3:0] decodeExceptionPort_payload_code; + wire [31:0] decodeExceptionPort_payload_badAddr; + wire BranchPlugin_jumpInterface_valid; + wire [31:0] BranchPlugin_jumpInterface_payload; + wire BranchPlugin_branchExceptionPort_valid; + wire [3:0] BranchPlugin_branchExceptionPort_payload_code; + wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr; + reg CsrPlugin_jumpInterface_valid; + reg [31:0] CsrPlugin_jumpInterface_payload; + wire CsrPlugin_exceptionPendings_0; + wire CsrPlugin_exceptionPendings_1; + wire CsrPlugin_exceptionPendings_2; + wire CsrPlugin_exceptionPendings_3; + wire externalInterrupt; + wire contextSwitching; + reg [1:0] CsrPlugin_privilege; + wire CsrPlugin_forceMachineWire; + wire CsrPlugin_allowInterrupts; + wire CsrPlugin_allowException; + wire IBusCachedPlugin_jump_pcLoad_valid; + wire [31:0] IBusCachedPlugin_jump_pcLoad_payload; + wire [4:0] _zz_101_; + wire [4:0] _zz_102_; + wire _zz_103_; + wire _zz_104_; + wire _zz_105_; + wire _zz_106_; + wire IBusCachedPlugin_fetchPc_preOutput_valid; + wire IBusCachedPlugin_fetchPc_preOutput_ready; + wire [31:0] IBusCachedPlugin_fetchPc_preOutput_payload; + wire _zz_107_; + wire IBusCachedPlugin_fetchPc_output_valid; + wire IBusCachedPlugin_fetchPc_output_ready; + wire [31:0] IBusCachedPlugin_fetchPc_output_payload; + reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ; + reg IBusCachedPlugin_fetchPc_inc; + reg IBusCachedPlugin_fetchPc_propagatePc; + reg [31:0] IBusCachedPlugin_fetchPc_pc; + reg IBusCachedPlugin_fetchPc_samplePcNext; + reg _zz_108_; + wire IBusCachedPlugin_iBusRsp_stages_0_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_0_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_0_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_0_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_0_halt; + wire IBusCachedPlugin_iBusRsp_stages_0_inputSample; + wire IBusCachedPlugin_iBusRsp_stages_1_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_1_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_1_halt; + wire IBusCachedPlugin_iBusRsp_stages_1_inputSample; + wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid; + wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload; + wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid; + wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload; + reg IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt; + wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_inputSample; + wire _zz_109_; + wire _zz_110_; + wire _zz_111_; + wire _zz_112_; + wire _zz_113_; + reg _zz_114_; + wire _zz_115_; + reg _zz_116_; + reg [31:0] _zz_117_; + reg IBusCachedPlugin_iBusRsp_readyForError; + wire IBusCachedPlugin_iBusRsp_decodeInput_valid; + wire IBusCachedPlugin_iBusRsp_decodeInput_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_decodeInput_payload_pc; + wire IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_error; + wire [31:0] IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_inst; + wire IBusCachedPlugin_iBusRsp_decodeInput_payload_isRvc; + reg IBusCachedPlugin_injector_nextPcCalc_valids_0; + reg IBusCachedPlugin_injector_nextPcCalc_valids_1; + reg IBusCachedPlugin_injector_nextPcCalc_valids_2; + reg IBusCachedPlugin_injector_nextPcCalc_valids_3; + reg IBusCachedPlugin_injector_nextPcCalc_valids_4; + reg IBusCachedPlugin_injector_decodeRemoved; + wire _zz_118_; + reg [18:0] _zz_119_; + wire _zz_120_; + reg [10:0] _zz_121_; + wire _zz_122_; + reg [18:0] _zz_123_; + reg _zz_124_; + wire _zz_125_; + reg [10:0] _zz_126_; + wire _zz_127_; + reg [18:0] _zz_128_; + wire iBus_cmd_valid; + wire iBus_cmd_ready; + reg [31:0] iBus_cmd_payload_address; + wire [2:0] iBus_cmd_payload_size; + wire iBus_rsp_valid; + wire [31:0] iBus_rsp_payload_data; + wire iBus_rsp_payload_error; + wire IBusCachedPlugin_s0_tightlyCoupledHit; + reg IBusCachedPlugin_s1_tightlyCoupledHit; + reg IBusCachedPlugin_s2_tightlyCoupledHit; + wire IBusCachedPlugin_rsp_iBusRspOutputHalt; + reg IBusCachedPlugin_rsp_redoFetch; + wire dBus_cmd_valid; + wire dBus_cmd_ready; + wire dBus_cmd_payload_wr; + wire [31:0] dBus_cmd_payload_address; + wire [31:0] dBus_cmd_payload_data; + wire [3:0] dBus_cmd_payload_mask; + wire [2:0] dBus_cmd_payload_length; + wire dBus_cmd_payload_last; + wire dBus_rsp_valid; + wire [31:0] dBus_rsp_payload_data; + wire dBus_rsp_payload_error; + wire dataCache_1__io_mem_cmd_s2mPipe_valid; + wire dataCache_1__io_mem_cmd_s2mPipe_ready; + wire dataCache_1__io_mem_cmd_s2mPipe_payload_wr; + wire [31:0] dataCache_1__io_mem_cmd_s2mPipe_payload_address; + wire [31:0] dataCache_1__io_mem_cmd_s2mPipe_payload_data; + wire [3:0] dataCache_1__io_mem_cmd_s2mPipe_payload_mask; + wire [2:0] dataCache_1__io_mem_cmd_s2mPipe_payload_length; + wire dataCache_1__io_mem_cmd_s2mPipe_payload_last; + reg _zz_129_; + reg _zz_130_; + reg [31:0] _zz_131_; + reg [31:0] _zz_132_; + reg [3:0] _zz_133_; + reg [2:0] _zz_134_; + reg _zz_135_; + wire dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_valid; + wire dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_ready; + wire dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_wr; + wire [31:0] dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_address; + wire [31:0] dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_data; + wire [3:0] dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_mask; + wire [2:0] dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_length; + wire dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_last; + reg _zz_136_; + reg _zz_137_; + reg [31:0] _zz_138_; + reg [31:0] _zz_139_; + reg [3:0] _zz_140_; + reg [2:0] _zz_141_; + reg _zz_142_; + wire [1:0] execute_DBusCachedPlugin_size; + reg [31:0] _zz_143_; + reg [31:0] writeBack_DBusCachedPlugin_rspShifted; + wire _zz_144_; + reg [31:0] _zz_145_; + wire _zz_146_; + reg [31:0] _zz_147_; + reg [31:0] writeBack_DBusCachedPlugin_rspFormated; + wire [30:0] _zz_148_; + wire _zz_149_; + wire _zz_150_; + wire _zz_151_; + wire _zz_152_; + wire `AluCtrlEnum_defaultEncoding_type _zz_153_; + wire `Src1CtrlEnum_defaultEncoding_type _zz_154_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_155_; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_156_; + wire `Src2CtrlEnum_defaultEncoding_type _zz_157_; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_158_; + wire `BranchCtrlEnum_defaultEncoding_type _zz_159_; + wire [4:0] decode_RegFilePlugin_regFileReadAddress1; + wire [4:0] decode_RegFilePlugin_regFileReadAddress2; + wire [31:0] decode_RegFilePlugin_rs1Data; + wire [31:0] decode_RegFilePlugin_rs2Data; + reg lastStageRegFileWrite_valid /* verilator public */ ; + wire [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; + wire [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; + reg _zz_160_; + reg [31:0] execute_IntAluPlugin_bitwise; + reg [31:0] _zz_161_; + reg [31:0] _zz_162_; + wire _zz_163_; + reg [19:0] _zz_164_; + wire _zz_165_; + reg [19:0] _zz_166_; + reg [31:0] _zz_167_; + reg [31:0] execute_SrcPlugin_addSub; + wire execute_SrcPlugin_less; + wire [4:0] execute_FullBarrelShifterPlugin_amplitude; + reg [31:0] _zz_168_; + wire [31:0] execute_FullBarrelShifterPlugin_reversed; + reg [31:0] _zz_169_; + reg _zz_170_; + reg _zz_171_; + wire _zz_172_; + reg _zz_173_; + reg [4:0] _zz_174_; + reg [31:0] _zz_175_; + wire _zz_176_; + wire _zz_177_; + wire _zz_178_; + wire _zz_179_; + wire _zz_180_; + wire _zz_181_; + wire execute_BranchPlugin_eq; + wire [2:0] _zz_182_; + reg _zz_183_; + reg _zz_184_; + wire _zz_185_; + reg [19:0] _zz_186_; + wire _zz_187_; + reg [10:0] _zz_188_; + wire _zz_189_; + reg [18:0] _zz_190_; + reg _zz_191_; + wire execute_BranchPlugin_missAlignedTarget; + reg [31:0] execute_BranchPlugin_branch_src1; + reg [31:0] execute_BranchPlugin_branch_src2; + wire _zz_192_; + reg [19:0] _zz_193_; + wire _zz_194_; + reg [10:0] _zz_195_; + wire _zz_196_; + reg [18:0] _zz_197_; + wire [31:0] execute_BranchPlugin_branchAdder; + wire [1:0] CsrPlugin_misa_base; + wire [25:0] CsrPlugin_misa_extensions; + reg [1:0] CsrPlugin_mtvec_mode; + reg [29:0] CsrPlugin_mtvec_base; + reg [31:0] CsrPlugin_mepc; + reg CsrPlugin_mstatus_MIE; + reg CsrPlugin_mstatus_MPIE; + reg [1:0] CsrPlugin_mstatus_MPP; + reg CsrPlugin_mip_MEIP; + reg CsrPlugin_mip_MTIP; + reg CsrPlugin_mip_MSIP; + reg CsrPlugin_mie_MEIE; + reg CsrPlugin_mie_MTIE; + reg CsrPlugin_mie_MSIE; + reg CsrPlugin_mcause_interrupt; + reg [3:0] CsrPlugin_mcause_exceptionCode; + reg [31:0] CsrPlugin_mtval; + reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; + reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; + wire _zz_198_; + wire _zz_199_; + wire _zz_200_; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code; + reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; + wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; + wire [1:0] _zz_201_; + wire _zz_202_; + reg CsrPlugin_interrupt_valid; + reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; + reg [1:0] CsrPlugin_interrupt_targetPrivilege; + wire CsrPlugin_exception; + wire CsrPlugin_lastStageWasWfi; + reg CsrPlugin_pipelineLiberator_done; + wire CsrPlugin_interruptJump /* verilator public */ ; + reg CsrPlugin_hadException; + reg [1:0] CsrPlugin_targetPrivilege; + reg [3:0] CsrPlugin_trapCause; + reg [1:0] CsrPlugin_xtvec_mode; + reg [29:0] CsrPlugin_xtvec_base; + wire execute_CsrPlugin_inWfi /* verilator public */ ; + reg execute_CsrPlugin_wfiWake; + wire execute_CsrPlugin_blockedBySideEffects; + reg execute_CsrPlugin_illegalAccess; + reg execute_CsrPlugin_illegalInstruction; + reg [31:0] execute_CsrPlugin_readData; + wire execute_CsrPlugin_writeInstruction; + wire execute_CsrPlugin_readInstruction; + wire execute_CsrPlugin_writeEnable; + wire execute_CsrPlugin_readEnable; + wire [31:0] execute_CsrPlugin_readToWriteData; + reg [31:0] execute_CsrPlugin_writeData; + wire [11:0] execute_CsrPlugin_csrAddress; + reg execute_MulPlugin_aSigned; + reg execute_MulPlugin_bSigned; + wire [31:0] execute_MulPlugin_a; + wire [31:0] execute_MulPlugin_b; + wire [15:0] execute_MulPlugin_aULow; + wire [15:0] execute_MulPlugin_bULow; + wire [16:0] execute_MulPlugin_aSLow; + wire [16:0] execute_MulPlugin_bSLow; + wire [16:0] execute_MulPlugin_aHigh; + wire [16:0] execute_MulPlugin_bHigh; + wire [65:0] writeBack_MulPlugin_result; + reg [32:0] memory_DivPlugin_rs1; + reg [31:0] memory_DivPlugin_rs2; + reg [64:0] memory_DivPlugin_accumulator; + reg memory_DivPlugin_div_needRevert; + reg memory_DivPlugin_div_counter_willIncrement; + reg memory_DivPlugin_div_counter_willClear; + reg [5:0] memory_DivPlugin_div_counter_valueNext; + reg [5:0] memory_DivPlugin_div_counter_value; + wire memory_DivPlugin_div_counter_willOverflowIfInc; + wire memory_DivPlugin_div_counter_willOverflow; + reg memory_DivPlugin_div_done; + reg [31:0] memory_DivPlugin_div_result; + wire [31:0] _zz_203_; + wire [32:0] _zz_204_; + wire [32:0] _zz_205_; + wire [31:0] _zz_206_; + wire _zz_207_; + wire _zz_208_; + reg [32:0] _zz_209_; + reg [31:0] externalInterruptArray_regNext; + reg [31:0] _zz_210_; + wire [31:0] _zz_211_; + reg decode_to_execute_IS_MUL; + reg execute_to_memory_IS_MUL; + reg memory_to_writeBack_IS_MUL; + reg [31:0] decode_to_execute_FORMAL_PC_NEXT; + reg [31:0] execute_to_memory_FORMAL_PC_NEXT; + reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; + reg [33:0] execute_to_memory_MUL_LH; + reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; + reg `ShiftCtrlEnum_defaultEncoding_type execute_to_memory_SHIFT_CTRL; + reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; + reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; + reg [31:0] decode_to_execute_PC; + reg [31:0] execute_to_memory_PC; + reg [31:0] memory_to_writeBack_PC; + reg decode_to_execute_IS_CSR; + reg decode_to_execute_MEMORY_ENABLE; + reg execute_to_memory_MEMORY_ENABLE; + reg memory_to_writeBack_MEMORY_ENABLE; + reg [31:0] execute_to_memory_MUL_LL; + reg [31:0] execute_to_memory_BRANCH_CALC; + reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; + reg [51:0] memory_to_writeBack_MUL_LOW; + reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; + reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; + reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW; + reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW; + reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + reg [33:0] execute_to_memory_MUL_HL; + reg [33:0] execute_to_memory_MUL_HH; + reg [33:0] memory_to_writeBack_MUL_HH; + reg decode_to_execute_IS_RS2_SIGNED; + reg [31:0] decode_to_execute_RS2; + reg decode_to_execute_PREDICTION_HAD_BRANCHED2; + reg decode_to_execute_MEMORY_WR; + reg execute_to_memory_MEMORY_WR; + reg memory_to_writeBack_MEMORY_WR; + reg decode_to_execute_SRC_LESS_UNSIGNED; + reg decode_to_execute_REGFILE_WRITE_VALID; + reg execute_to_memory_REGFILE_WRITE_VALID; + reg memory_to_writeBack_REGFILE_WRITE_VALID; + reg decode_to_execute_IS_RS1_SIGNED; + reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL; + reg decode_to_execute_IS_DIV; + reg execute_to_memory_IS_DIV; + reg [31:0] decode_to_execute_RS1; + reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; + reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; + reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL; + reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL; + reg [31:0] execute_to_memory_SHIFT_RIGHT; + reg [31:0] decode_to_execute_INSTRUCTION; + reg [31:0] execute_to_memory_INSTRUCTION; + reg [31:0] memory_to_writeBack_INSTRUCTION; + reg execute_to_memory_BRANCH_DO; + reg decode_to_execute_SRC2_FORCE_ZERO; + reg decode_to_execute_CSR_WRITE_OPCODE; + reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; + reg decode_to_execute_CSR_READ_OPCODE; + reg decode_to_execute_SRC_USE_SUB_LESS; + reg decode_to_execute_MEMORY_MANAGMENT; + reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL; + reg [2:0] _zz_212_; + reg _zz_213_; + reg [31:0] iBusWishbone_DAT_MISO_regNext; + reg [2:0] _zz_214_; + wire _zz_215_; + wire _zz_216_; + wire _zz_217_; + wire _zz_218_; + wire _zz_219_; + reg _zz_220_; + reg [31:0] dBusWishbone_DAT_MISO_regNext; + `ifndef SYNTHESIS + reg [95:0] decode_SRC1_CTRL_string; + reg [95:0] _zz_1__string; + reg [95:0] _zz_2__string; + reg [95:0] _zz_3__string; + reg [39:0] decode_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_4__string; + reg [39:0] _zz_5__string; + reg [39:0] _zz_6__string; + reg [31:0] _zz_7__string; + reg [31:0] _zz_8__string; + reg [31:0] _zz_9__string; + reg [31:0] _zz_10__string; + reg [31:0] decode_ENV_CTRL_string; + reg [31:0] _zz_11__string; + reg [31:0] _zz_12__string; + reg [31:0] _zz_13__string; + reg [31:0] _zz_14__string; + reg [31:0] _zz_15__string; + reg [23:0] decode_SRC2_CTRL_string; + reg [23:0] _zz_16__string; + reg [23:0] _zz_17__string; + reg [23:0] _zz_18__string; + reg [63:0] decode_ALU_CTRL_string; + reg [63:0] _zz_19__string; + reg [63:0] _zz_20__string; + reg [63:0] _zz_21__string; + reg [71:0] _zz_22__string; + reg [71:0] _zz_23__string; + reg [71:0] decode_SHIFT_CTRL_string; + reg [71:0] _zz_24__string; + reg [71:0] _zz_25__string; + reg [71:0] _zz_26__string; + reg [31:0] memory_ENV_CTRL_string; + reg [31:0] _zz_32__string; + reg [31:0] execute_ENV_CTRL_string; + reg [31:0] _zz_33__string; + reg [31:0] writeBack_ENV_CTRL_string; + reg [31:0] _zz_36__string; + reg [31:0] execute_BRANCH_CTRL_string; + reg [31:0] _zz_39__string; + reg [71:0] memory_SHIFT_CTRL_string; + reg [71:0] _zz_44__string; + reg [71:0] execute_SHIFT_CTRL_string; + reg [71:0] _zz_46__string; + reg [23:0] execute_SRC2_CTRL_string; + reg [23:0] _zz_51__string; + reg [95:0] execute_SRC1_CTRL_string; + reg [95:0] _zz_53__string; + reg [63:0] execute_ALU_CTRL_string; + reg [63:0] _zz_56__string; + reg [39:0] execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_58__string; + reg [31:0] _zz_68__string; + reg [71:0] _zz_73__string; + reg [23:0] _zz_74__string; + reg [39:0] _zz_81__string; + reg [31:0] _zz_82__string; + reg [95:0] _zz_83__string; + reg [63:0] _zz_87__string; + reg [31:0] decode_BRANCH_CTRL_string; + reg [31:0] _zz_95__string; + reg [63:0] _zz_153__string; + reg [95:0] _zz_154__string; + reg [31:0] _zz_155__string; + reg [39:0] _zz_156__string; + reg [23:0] _zz_157__string; + reg [71:0] _zz_158__string; + reg [31:0] _zz_159__string; + reg [71:0] decode_to_execute_SHIFT_CTRL_string; + reg [71:0] execute_to_memory_SHIFT_CTRL_string; + reg [63:0] decode_to_execute_ALU_CTRL_string; + reg [23:0] decode_to_execute_SRC2_CTRL_string; + reg [31:0] decode_to_execute_BRANCH_CTRL_string; + reg [31:0] decode_to_execute_ENV_CTRL_string; + reg [31:0] execute_to_memory_ENV_CTRL_string; + reg [31:0] memory_to_writeBack_ENV_CTRL_string; + reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string; + reg [95:0] decode_to_execute_SRC1_CTRL_string; + `endif + + (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; + assign _zz_244_ = (execute_arbitration_isValid && execute_IS_CSR); + assign _zz_245_ = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_246_ = 1'b1; + assign _zz_247_ = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_248_ = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_249_ = (memory_arbitration_isValid && memory_IS_DIV); + assign _zz_250_ = ((_zz_227_ && IBusCachedPlugin_cache_io_cpu_decode_error) && (! _zz_91_)); + assign _zz_251_ = ((_zz_227_ && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! _zz_92_)); + assign _zz_252_ = ((_zz_227_ && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! _zz_93_)); + assign _zz_253_ = ((_zz_227_ && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! 1'b0)); + assign _zz_254_ = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != (2'b00)); + assign _zz_255_ = (! memory_DivPlugin_div_done); + assign _zz_256_ = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign _zz_257_ = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); + assign _zz_258_ = writeBack_INSTRUCTION[29 : 28]; + assign _zz_259_ = (IBusCachedPlugin_fetchPc_preOutput_valid && IBusCachedPlugin_fetchPc_preOutput_ready); + assign _zz_260_ = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_261_ = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_262_ = (1'b0 || (! 1'b1)); + assign _zz_263_ = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_264_ = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign _zz_265_ = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_266_ = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign _zz_267_ = execute_INSTRUCTION[13 : 12]; + assign _zz_268_ = (! memory_arbitration_isStuck); + assign _zz_269_ = (iBus_cmd_valid || (_zz_212_ != (3'b000))); + assign _zz_270_ = (_zz_240_ && (! dataCache_1__io_mem_cmd_s2mPipe_ready)); + assign _zz_271_ = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < (2'b11))); + assign _zz_272_ = ((_zz_198_ && 1'b1) && (! 1'b0)); + assign _zz_273_ = ((_zz_199_ && 1'b1) && (! 1'b0)); + assign _zz_274_ = ((_zz_200_ && 1'b1) && (! 1'b0)); + assign _zz_275_ = writeBack_INSTRUCTION[13 : 12]; + assign _zz_276_ = execute_INSTRUCTION[13]; + assign _zz_277_ = writeBack_INSTRUCTION[13 : 12]; + assign _zz_278_ = (_zz_101_ - (5'b00001)); + assign _zz_279_ = {IBusCachedPlugin_fetchPc_inc,(2'b00)}; + assign _zz_280_ = {29'd0, _zz_279_}; + assign _zz_281_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_282_ = {{_zz_119_,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_283_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_284_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_285_ = {{_zz_121_,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_286_ = {{_zz_123_,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_287_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_288_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_289_ = (writeBack_MEMORY_WR ? (3'b111) : (3'b101)); + assign _zz_290_ = (writeBack_MEMORY_WR ? (3'b110) : (3'b100)); + assign _zz_291_ = _zz_148_[2 : 2]; + assign _zz_292_ = _zz_148_[4 : 4]; + assign _zz_293_ = _zz_148_[5 : 5]; + assign _zz_294_ = _zz_148_[11 : 11]; + assign _zz_295_ = _zz_148_[12 : 12]; + assign _zz_296_ = _zz_148_[13 : 13]; + assign _zz_297_ = _zz_148_[14 : 14]; + assign _zz_298_ = _zz_148_[15 : 15]; + assign _zz_299_ = _zz_148_[16 : 16]; + assign _zz_300_ = _zz_148_[21 : 21]; + assign _zz_301_ = _zz_148_[22 : 22]; + assign _zz_302_ = _zz_148_[23 : 23]; + assign _zz_303_ = _zz_148_[24 : 24]; + assign _zz_304_ = _zz_148_[27 : 27]; + assign _zz_305_ = _zz_148_[28 : 28]; + assign _zz_306_ = _zz_148_[29 : 29]; + assign _zz_307_ = _zz_148_[30 : 30]; + assign _zz_308_ = execute_SRC_LESS; + assign _zz_309_ = (3'b100); + assign _zz_310_ = execute_INSTRUCTION[19 : 15]; + assign _zz_311_ = execute_INSTRUCTION[31 : 20]; + assign _zz_312_ = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_313_ = ($signed(_zz_314_) + $signed(_zz_317_)); + assign _zz_314_ = ($signed(_zz_315_) + $signed(_zz_316_)); + assign _zz_315_ = execute_SRC1; + assign _zz_316_ = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_317_ = (execute_SRC_USE_SUB_LESS ? _zz_318_ : _zz_319_); + assign _zz_318_ = (32'b00000000000000000000000000000001); + assign _zz_319_ = (32'b00000000000000000000000000000000); + assign _zz_320_ = ($signed(_zz_322_) >>> execute_FullBarrelShifterPlugin_amplitude); + assign _zz_321_ = _zz_320_[31 : 0]; + assign _zz_322_ = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; + assign _zz_323_ = execute_INSTRUCTION[31 : 20]; + assign _zz_324_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_325_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_326_ = {_zz_186_,execute_INSTRUCTION[31 : 20]}; + assign _zz_327_ = {{_zz_188_,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_328_ = {{_zz_190_,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_329_ = execute_INSTRUCTION[31 : 20]; + assign _zz_330_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_331_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_332_ = (3'b100); + assign _zz_333_ = (_zz_201_ & (~ _zz_334_)); + assign _zz_334_ = (_zz_201_ - (2'b01)); + assign _zz_335_ = ($signed(_zz_336_) + $signed(_zz_341_)); + assign _zz_336_ = ($signed(_zz_337_) + $signed(_zz_339_)); + assign _zz_337_ = (52'b0000000000000000000000000000000000000000000000000000); + assign _zz_338_ = {1'b0,memory_MUL_LL}; + assign _zz_339_ = {{19{_zz_338_[32]}}, _zz_338_}; + assign _zz_340_ = ({16'd0,memory_MUL_LH} <<< 16); + assign _zz_341_ = {{2{_zz_340_[49]}}, _zz_340_}; + assign _zz_342_ = ({16'd0,memory_MUL_HL} <<< 16); + assign _zz_343_ = {{2{_zz_342_[49]}}, _zz_342_}; + assign _zz_344_ = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; + assign _zz_345_ = ({32'd0,writeBack_MUL_HH} <<< 32); + assign _zz_346_ = writeBack_MUL_LOW[31 : 0]; + assign _zz_347_ = writeBack_MulPlugin_result[63 : 32]; + assign _zz_348_ = memory_DivPlugin_div_counter_willIncrement; + assign _zz_349_ = {5'd0, _zz_348_}; + assign _zz_350_ = {1'd0, memory_DivPlugin_rs2}; + assign _zz_351_ = {_zz_203_,(! _zz_205_[32])}; + assign _zz_352_ = _zz_205_[31:0]; + assign _zz_353_ = _zz_204_[31:0]; + assign _zz_354_ = _zz_355_; + assign _zz_355_ = _zz_356_; + assign _zz_356_ = ({1'b0,(memory_DivPlugin_div_needRevert ? (~ _zz_206_) : _zz_206_)} + _zz_358_); + assign _zz_357_ = memory_DivPlugin_div_needRevert; + assign _zz_358_ = {32'd0, _zz_357_}; + assign _zz_359_ = _zz_208_; + assign _zz_360_ = {32'd0, _zz_359_}; + assign _zz_361_ = _zz_207_; + assign _zz_362_ = {31'd0, _zz_361_}; + assign _zz_363_ = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_364_ = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_365_ = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_366_ = execute_CsrPlugin_writeData[11 : 11]; + assign _zz_367_ = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_368_ = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_369_ = (iBus_cmd_payload_address >>> 5); + assign _zz_370_ = 1'b1; + assign _zz_371_ = 1'b1; + assign _zz_372_ = {_zz_104_,{_zz_106_,_zz_105_}}; + assign _zz_373_ = decode_INSTRUCTION[31]; + assign _zz_374_ = decode_INSTRUCTION[31]; + assign _zz_375_ = decode_INSTRUCTION[7]; + assign _zz_376_ = (decode_INSTRUCTION & (32'b00000000000000000000000001000100)); + assign _zz_377_ = (32'b00000000000000000000000000000000); + assign _zz_378_ = ((decode_INSTRUCTION & _zz_390_) == (32'b00000000000000000000000000000000)); + assign _zz_379_ = (_zz_391_ == _zz_392_); + assign _zz_380_ = (_zz_393_ == _zz_394_); + assign _zz_381_ = (decode_INSTRUCTION & (32'b00000000000000000000000001011000)); + assign _zz_382_ = (32'b00000000000000000000000000000000); + assign _zz_383_ = (_zz_395_ == _zz_396_); + assign _zz_384_ = {_zz_397_,_zz_398_}; + assign _zz_385_ = (_zz_399_ == _zz_400_); + assign _zz_386_ = (1'b0); + assign _zz_387_ = ({_zz_401_,_zz_402_} != (2'b00)); + assign _zz_388_ = (_zz_403_ != _zz_404_); + assign _zz_389_ = {_zz_405_,{_zz_406_,_zz_407_}}; + assign _zz_390_ = (32'b00000000000000000000000000011000); + assign _zz_391_ = (decode_INSTRUCTION & (32'b00000000000000000110000000000100)); + assign _zz_392_ = (32'b00000000000000000010000000000000); + assign _zz_393_ = (decode_INSTRUCTION & (32'b00000000000000000101000000000100)); + assign _zz_394_ = (32'b00000000000000000001000000000000); + assign _zz_395_ = (decode_INSTRUCTION & (32'b00000000000000000000000001000100)); + assign _zz_396_ = (32'b00000000000000000000000001000000); + assign _zz_397_ = ((decode_INSTRUCTION & (32'b00000000000000000010000000010100)) == (32'b00000000000000000010000000010000)); + assign _zz_398_ = ((decode_INSTRUCTION & (32'b01000000000000000000000000110100)) == (32'b01000000000000000000000000110000)); + assign _zz_399_ = (decode_INSTRUCTION & (32'b00000000000000000000000001100100)); + assign _zz_400_ = (32'b00000000000000000000000000100100); + assign _zz_401_ = _zz_152_; + assign _zz_402_ = ((decode_INSTRUCTION & _zz_408_) == (32'b00000000000000000000000000000100)); + assign _zz_403_ = ((decode_INSTRUCTION & _zz_409_) == (32'b00000000000000000000000001000000)); + assign _zz_404_ = (1'b0); + assign _zz_405_ = ({_zz_152_,{_zz_410_,_zz_411_}} != (6'b000000)); + assign _zz_406_ = ({_zz_412_,_zz_413_} != (2'b00)); + assign _zz_407_ = {(_zz_414_ != _zz_415_),{_zz_416_,{_zz_417_,_zz_418_}}}; + assign _zz_408_ = (32'b00000000000000000000000000011100); + assign _zz_409_ = (32'b00000000000000000000000001011000); + assign _zz_410_ = ((decode_INSTRUCTION & _zz_419_) == (32'b00000000000000000001000000010000)); + assign _zz_411_ = {(_zz_420_ == _zz_421_),{_zz_422_,{_zz_423_,_zz_424_}}}; + assign _zz_412_ = ((decode_INSTRUCTION & _zz_425_) == (32'b00000000000000000010000000000000)); + assign _zz_413_ = ((decode_INSTRUCTION & _zz_426_) == (32'b00000000000000000001000000000000)); + assign _zz_414_ = {(_zz_427_ == _zz_428_),(_zz_429_ == _zz_430_)}; + assign _zz_415_ = (2'b00); + assign _zz_416_ = ({_zz_431_,_zz_432_} != (2'b00)); + assign _zz_417_ = ({_zz_433_,_zz_434_} != (2'b00)); + assign _zz_418_ = {(_zz_435_ != _zz_436_),{_zz_437_,{_zz_438_,_zz_439_}}}; + assign _zz_419_ = (32'b00000000000000000001000000010000); + assign _zz_420_ = (decode_INSTRUCTION & (32'b00000000000000000010000000010000)); + assign _zz_421_ = (32'b00000000000000000010000000010000); + assign _zz_422_ = ((decode_INSTRUCTION & _zz_440_) == (32'b00000000000000000000000000010000)); + assign _zz_423_ = (_zz_441_ == _zz_442_); + assign _zz_424_ = (_zz_443_ == _zz_444_); + assign _zz_425_ = (32'b00000000000000000010000000010000); + assign _zz_426_ = (32'b00000000000000000101000000000000); + assign _zz_427_ = (decode_INSTRUCTION & (32'b00000000000000000000000000110100)); + assign _zz_428_ = (32'b00000000000000000000000000100000); + assign _zz_429_ = (decode_INSTRUCTION & (32'b00000000000000000000000001100100)); + assign _zz_430_ = (32'b00000000000000000000000000100000); + assign _zz_431_ = ((decode_INSTRUCTION & _zz_445_) == (32'b00000000000000000001000001010000)); + assign _zz_432_ = ((decode_INSTRUCTION & _zz_446_) == (32'b00000000000000000010000001010000)); + assign _zz_433_ = (_zz_447_ == _zz_448_); + assign _zz_434_ = (_zz_449_ == _zz_450_); + assign _zz_435_ = {_zz_451_,{_zz_452_,_zz_453_}}; + assign _zz_436_ = (3'b000); + assign _zz_437_ = ({_zz_454_,_zz_455_} != (2'b00)); + assign _zz_438_ = (_zz_456_ != _zz_457_); + assign _zz_439_ = {_zz_458_,{_zz_459_,_zz_460_}}; + assign _zz_440_ = (32'b00000000000000000000000001010000); + assign _zz_441_ = (decode_INSTRUCTION & (32'b00000000000000000000000000001100)); + assign _zz_442_ = (32'b00000000000000000000000000000100); + assign _zz_443_ = (decode_INSTRUCTION & (32'b00000000000000000000000000101000)); + assign _zz_444_ = (32'b00000000000000000000000000000000); + assign _zz_445_ = (32'b00000000000000000001000001010000); + assign _zz_446_ = (32'b00000000000000000010000001010000); + assign _zz_447_ = (decode_INSTRUCTION & (32'b00000000000000000111000000110100)); + assign _zz_448_ = (32'b00000000000000000101000000010000); + assign _zz_449_ = (decode_INSTRUCTION & (32'b00000010000000000111000001100100)); + assign _zz_450_ = (32'b00000000000000000101000000100000); + assign _zz_451_ = ((decode_INSTRUCTION & _zz_461_) == (32'b01000000000000000001000000010000)); + assign _zz_452_ = (_zz_462_ == _zz_463_); + assign _zz_453_ = (_zz_464_ == _zz_465_); + assign _zz_454_ = _zz_149_; + assign _zz_455_ = (_zz_466_ == _zz_467_); + assign _zz_456_ = {_zz_149_,_zz_468_}; + assign _zz_457_ = (2'b00); + assign _zz_458_ = (_zz_151_ != (1'b0)); + assign _zz_459_ = (_zz_469_ != _zz_470_); + assign _zz_460_ = {_zz_471_,{_zz_472_,_zz_473_}}; + assign _zz_461_ = (32'b01000000000000000011000001010100); + assign _zz_462_ = (decode_INSTRUCTION & (32'b00000000000000000111000000110100)); + assign _zz_463_ = (32'b00000000000000000001000000010000); + assign _zz_464_ = (decode_INSTRUCTION & (32'b00000010000000000111000001010100)); + assign _zz_465_ = (32'b00000000000000000001000000010000); + assign _zz_466_ = (decode_INSTRUCTION & (32'b00000000000000000000000001110000)); + assign _zz_467_ = (32'b00000000000000000000000000100000); + assign _zz_468_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000100000)) == (32'b00000000000000000000000000000000)); + assign _zz_469_ = _zz_151_; + assign _zz_470_ = (1'b0); + assign _zz_471_ = ({_zz_149_,{_zz_474_,{_zz_475_,_zz_476_}}} != (5'b00000)); + assign _zz_472_ = ((_zz_477_ == _zz_478_) != (1'b0)); + assign _zz_473_ = {(_zz_479_ != (1'b0)),{(_zz_480_ != _zz_481_),{_zz_482_,{_zz_483_,_zz_484_}}}}; + assign _zz_474_ = ((decode_INSTRUCTION & (32'b00000000000000000010000000110000)) == (32'b00000000000000000010000000010000)); + assign _zz_475_ = ((decode_INSTRUCTION & _zz_485_) == (32'b00000000000000000000000000010000)); + assign _zz_476_ = {(_zz_486_ == _zz_487_),(_zz_488_ == _zz_489_)}; + assign _zz_477_ = (decode_INSTRUCTION & (32'b00000000000000000100000001001000)); + assign _zz_478_ = (32'b00000000000000000100000000001000); + assign _zz_479_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000100000)) == (32'b00000000000000000000000000100000)); + assign _zz_480_ = ((decode_INSTRUCTION & _zz_490_) == (32'b00000010000000000000000000110000)); + assign _zz_481_ = (1'b0); + assign _zz_482_ = ((_zz_491_ == _zz_492_) != (1'b0)); + assign _zz_483_ = (_zz_493_ != (1'b0)); + assign _zz_484_ = {(_zz_494_ != _zz_495_),{_zz_496_,{_zz_497_,_zz_498_}}}; + assign _zz_485_ = (32'b00000000000000000001000000110000); + assign _zz_486_ = (decode_INSTRUCTION & (32'b00000010000000000010000001100000)); + assign _zz_487_ = (32'b00000000000000000010000000100000); + assign _zz_488_ = (decode_INSTRUCTION & (32'b00000010000000000011000000100000)); + assign _zz_489_ = (32'b00000000000000000000000000100000); + assign _zz_490_ = (32'b00000010000000000100000001110100); + assign _zz_491_ = (decode_INSTRUCTION & (32'b00000000000000000001000000000000)); + assign _zz_492_ = (32'b00000000000000000001000000000000); + assign _zz_493_ = ((decode_INSTRUCTION & (32'b00000000000000000011000000000000)) == (32'b00000000000000000010000000000000)); + assign _zz_494_ = ((decode_INSTRUCTION & (32'b00000000000000000011000001010000)) == (32'b00000000000000000000000001010000)); + assign _zz_495_ = (1'b0); + assign _zz_496_ = ({(_zz_499_ == _zz_500_),_zz_150_} != (2'b00)); + assign _zz_497_ = ({_zz_501_,_zz_150_} != (2'b00)); + assign _zz_498_ = {({_zz_502_,_zz_503_} != (5'b00000)),{(_zz_504_ != _zz_505_),{_zz_506_,{_zz_507_,_zz_508_}}}}; + assign _zz_499_ = (decode_INSTRUCTION & (32'b00000000000000000000000000010100)); + assign _zz_500_ = (32'b00000000000000000000000000000100); + assign _zz_501_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001000100)) == (32'b00000000000000000000000000000100)); + assign _zz_502_ = ((decode_INSTRUCTION & _zz_509_) == (32'b00000000000000000000000001000000)); + assign _zz_503_ = {_zz_149_,{_zz_510_,{_zz_511_,_zz_512_}}}; + assign _zz_504_ = ((decode_INSTRUCTION & _zz_513_) == (32'b00000010000000000100000000100000)); + assign _zz_505_ = (1'b0); + assign _zz_506_ = ({_zz_514_,{_zz_515_,_zz_516_}} != (3'b000)); + assign _zz_507_ = (_zz_517_ != (1'b0)); + assign _zz_508_ = {(_zz_518_ != _zz_519_),(_zz_520_ != _zz_521_)}; + assign _zz_509_ = (32'b00000000000000000000000001000000); + assign _zz_510_ = ((decode_INSTRUCTION & (32'b00000000000000000100000000100000)) == (32'b00000000000000000100000000100000)); + assign _zz_511_ = ((decode_INSTRUCTION & _zz_522_) == (32'b00000000000000000000000000010000)); + assign _zz_512_ = ((decode_INSTRUCTION & _zz_523_) == (32'b00000000000000000000000000100000)); + assign _zz_513_ = (32'b00000010000000000100000001100100); + assign _zz_514_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001010000)) == (32'b00000000000000000000000001000000)); + assign _zz_515_ = ((decode_INSTRUCTION & _zz_524_) == (32'b00000000000000000000000001000000)); + assign _zz_516_ = ((decode_INSTRUCTION & _zz_525_) == (32'b00000000000000000000000000000000)); + assign _zz_517_ = ((decode_INSTRUCTION & (32'b00000000000000000101000001001000)) == (32'b00000000000000000001000000001000)); + assign _zz_518_ = ((decode_INSTRUCTION & _zz_526_) == (32'b00000000000000000100000000010000)); + assign _zz_519_ = (1'b0); + assign _zz_520_ = ((decode_INSTRUCTION & _zz_527_) == (32'b00000000000000000010000000010000)); + assign _zz_521_ = (1'b0); + assign _zz_522_ = (32'b00000000000000000000000000110000); + assign _zz_523_ = (32'b00000010000000000000000000100000); + assign _zz_524_ = (32'b00000000000000000011000001000000); + assign _zz_525_ = (32'b00000000000000000000000000111000); + assign _zz_526_ = (32'b00000000000000000100000000010100); + assign _zz_527_ = (32'b00000000000000000110000000010100); + assign _zz_528_ = (32'b00000000000000000001000001111111); + assign _zz_529_ = (decode_INSTRUCTION & (32'b00000000000000000010000001111111)); + assign _zz_530_ = (32'b00000000000000000010000001110011); + assign _zz_531_ = ((decode_INSTRUCTION & (32'b00000000000000000100000001111111)) == (32'b00000000000000000100000001100011)); + assign _zz_532_ = ((decode_INSTRUCTION & (32'b00000000000000000010000001111111)) == (32'b00000000000000000010000000010011)); + assign _zz_533_ = {((decode_INSTRUCTION & (32'b00000000000000000110000000111111)) == (32'b00000000000000000000000000100011)),{((decode_INSTRUCTION & (32'b00000000000000000010000001111111)) == (32'b00000000000000000000000000000011)),{((decode_INSTRUCTION & _zz_534_) == (32'b00000000000000000000000000000011)),{(_zz_535_ == _zz_536_),{_zz_537_,{_zz_538_,_zz_539_}}}}}}; + assign _zz_534_ = (32'b00000000000000000101000001011111); + assign _zz_535_ = (decode_INSTRUCTION & (32'b00000000000000000111000001111011)); + assign _zz_536_ = (32'b00000000000000000000000001100011); + assign _zz_537_ = ((decode_INSTRUCTION & (32'b00000000000000000110000001111111)) == (32'b00000000000000000000000000001111)); + assign _zz_538_ = ((decode_INSTRUCTION & (32'b11111100000000000000000001111111)) == (32'b00000000000000000000000000110011)); + assign _zz_539_ = {((decode_INSTRUCTION & (32'b00000001111100000111000001111111)) == (32'b00000000000000000101000000001111)),{((decode_INSTRUCTION & (32'b10111100000000000111000001111111)) == (32'b00000000000000000101000000010011)),{((decode_INSTRUCTION & _zz_540_) == (32'b00000000000000000001000000010011)),{(_zz_541_ == _zz_542_),{_zz_543_,_zz_544_}}}}}; + assign _zz_540_ = (32'b11111100000000000011000001111111); + assign _zz_541_ = (decode_INSTRUCTION & (32'b10111110000000000111000001111111)); + assign _zz_542_ = (32'b00000000000000000101000000110011); + assign _zz_543_ = ((decode_INSTRUCTION & (32'b10111110000000000111000001111111)) == (32'b00000000000000000000000000110011)); + assign _zz_544_ = ((decode_INSTRUCTION & (32'b11011111111111111111111111111111)) == (32'b00010000001000000000000001110011)); + assign _zz_545_ = execute_INSTRUCTION[31]; + assign _zz_546_ = execute_INSTRUCTION[31]; + assign _zz_547_ = execute_INSTRUCTION[7]; + always @ (posedge clk) begin + if(_zz_61_) begin + RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; + end + end + + always @ (posedge clk) begin + if(_zz_370_) begin + _zz_241_ <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + end + end + + always @ (posedge clk) begin + if(_zz_371_) begin + _zz_242_ <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + end + end + + InstructionCache IBusCachedPlugin_cache ( + .io_flush(_zz_221_), + .io_cpu_prefetch_isValid(_zz_222_), + .io_cpu_prefetch_haltIt(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt), + .io_cpu_prefetch_pc(IBusCachedPlugin_iBusRsp_stages_0_input_payload), + .io_cpu_fetch_isValid(_zz_223_), + .io_cpu_fetch_isStuck(_zz_224_), + .io_cpu_fetch_isRemoved(_zz_225_), + .io_cpu_fetch_pc(IBusCachedPlugin_iBusRsp_stages_1_input_payload), + .io_cpu_fetch_data(IBusCachedPlugin_cache_io_cpu_fetch_data), + .io_cpu_fetch_dataBypassValid(IBusCachedPlugin_s1_tightlyCoupledHit), + .io_cpu_fetch_dataBypass(_zz_226_), + .io_cpu_fetch_mmuBus_cmd_isValid(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid), + .io_cpu_fetch_mmuBus_cmd_virtualAddress(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress), + .io_cpu_fetch_mmuBus_cmd_bypassTranslation(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_bypassTranslation), + .io_cpu_fetch_mmuBus_rsp_physicalAddress(IBusCachedPlugin_mmuBus_rsp_physicalAddress), + .io_cpu_fetch_mmuBus_rsp_isIoAccess(IBusCachedPlugin_mmuBus_rsp_isIoAccess), + .io_cpu_fetch_mmuBus_rsp_allowRead(IBusCachedPlugin_mmuBus_rsp_allowRead), + .io_cpu_fetch_mmuBus_rsp_allowWrite(IBusCachedPlugin_mmuBus_rsp_allowWrite), + .io_cpu_fetch_mmuBus_rsp_allowExecute(IBusCachedPlugin_mmuBus_rsp_allowExecute), + .io_cpu_fetch_mmuBus_rsp_exception(IBusCachedPlugin_mmuBus_rsp_exception), + .io_cpu_fetch_mmuBus_rsp_refilling(IBusCachedPlugin_mmuBus_rsp_refilling), + .io_cpu_fetch_mmuBus_end(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_end), + .io_cpu_fetch_mmuBus_busy(IBusCachedPlugin_mmuBus_busy), + .io_cpu_fetch_physicalAddress(IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress), + .io_cpu_fetch_haltIt(IBusCachedPlugin_cache_io_cpu_fetch_haltIt), + .io_cpu_decode_isValid(_zz_227_), + .io_cpu_decode_isStuck(_zz_228_), + .io_cpu_decode_pc(IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload), + .io_cpu_decode_physicalAddress(IBusCachedPlugin_cache_io_cpu_decode_physicalAddress), + .io_cpu_decode_data(IBusCachedPlugin_cache_io_cpu_decode_data), + .io_cpu_decode_cacheMiss(IBusCachedPlugin_cache_io_cpu_decode_cacheMiss), + .io_cpu_decode_error(IBusCachedPlugin_cache_io_cpu_decode_error), + .io_cpu_decode_mmuRefilling(IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling), + .io_cpu_decode_mmuException(IBusCachedPlugin_cache_io_cpu_decode_mmuException), + .io_cpu_decode_isUser(_zz_229_), + .io_cpu_fill_valid(_zz_230_), + .io_cpu_fill_payload(IBusCachedPlugin_cache_io_cpu_decode_physicalAddress), + .io_mem_cmd_valid(IBusCachedPlugin_cache_io_mem_cmd_valid), + .io_mem_cmd_ready(iBus_cmd_ready), + .io_mem_cmd_payload_address(IBusCachedPlugin_cache_io_mem_cmd_payload_address), + .io_mem_cmd_payload_size(IBusCachedPlugin_cache_io_mem_cmd_payload_size), + .io_mem_rsp_valid(iBus_rsp_valid), + .io_mem_rsp_payload_data(iBus_rsp_payload_data), + .io_mem_rsp_payload_error(iBus_rsp_payload_error), + .clk(clk), + .reset(reset) + ); + DataCache dataCache_1_ ( + .io_cpu_execute_isValid(_zz_231_), + .io_cpu_execute_address(_zz_232_), + .io_cpu_execute_args_wr(execute_MEMORY_WR), + .io_cpu_execute_args_data(_zz_143_), + .io_cpu_execute_args_size(execute_DBusCachedPlugin_size), + .io_cpu_memory_isValid(_zz_233_), + .io_cpu_memory_isStuck(memory_arbitration_isStuck), + .io_cpu_memory_isRemoved(memory_arbitration_removeIt), + .io_cpu_memory_isWrite(dataCache_1__io_cpu_memory_isWrite), + .io_cpu_memory_address(_zz_234_), + .io_cpu_memory_mmuBus_cmd_isValid(dataCache_1__io_cpu_memory_mmuBus_cmd_isValid), + .io_cpu_memory_mmuBus_cmd_virtualAddress(dataCache_1__io_cpu_memory_mmuBus_cmd_virtualAddress), + .io_cpu_memory_mmuBus_cmd_bypassTranslation(dataCache_1__io_cpu_memory_mmuBus_cmd_bypassTranslation), + .io_cpu_memory_mmuBus_rsp_physicalAddress(DBusCachedPlugin_mmuBus_rsp_physicalAddress), + .io_cpu_memory_mmuBus_rsp_isIoAccess(_zz_235_), + .io_cpu_memory_mmuBus_rsp_allowRead(DBusCachedPlugin_mmuBus_rsp_allowRead), + .io_cpu_memory_mmuBus_rsp_allowWrite(DBusCachedPlugin_mmuBus_rsp_allowWrite), + .io_cpu_memory_mmuBus_rsp_allowExecute(DBusCachedPlugin_mmuBus_rsp_allowExecute), + .io_cpu_memory_mmuBus_rsp_exception(DBusCachedPlugin_mmuBus_rsp_exception), + .io_cpu_memory_mmuBus_rsp_refilling(DBusCachedPlugin_mmuBus_rsp_refilling), + .io_cpu_memory_mmuBus_end(dataCache_1__io_cpu_memory_mmuBus_end), + .io_cpu_memory_mmuBus_busy(DBusCachedPlugin_mmuBus_busy), + .io_cpu_writeBack_isValid(_zz_236_), + .io_cpu_writeBack_isStuck(writeBack_arbitration_isStuck), + .io_cpu_writeBack_isUser(_zz_237_), + .io_cpu_writeBack_haltIt(dataCache_1__io_cpu_writeBack_haltIt), + .io_cpu_writeBack_isWrite(dataCache_1__io_cpu_writeBack_isWrite), + .io_cpu_writeBack_data(dataCache_1__io_cpu_writeBack_data), + .io_cpu_writeBack_address(_zz_238_), + .io_cpu_writeBack_mmuException(dataCache_1__io_cpu_writeBack_mmuException), + .io_cpu_writeBack_unalignedAccess(dataCache_1__io_cpu_writeBack_unalignedAccess), + .io_cpu_writeBack_accessError(dataCache_1__io_cpu_writeBack_accessError), + .io_cpu_redo(dataCache_1__io_cpu_redo), + .io_cpu_flush_valid(_zz_239_), + .io_cpu_flush_ready(dataCache_1__io_cpu_flush_ready), + .io_mem_cmd_valid(dataCache_1__io_mem_cmd_valid), + .io_mem_cmd_ready(_zz_240_), + .io_mem_cmd_payload_wr(dataCache_1__io_mem_cmd_payload_wr), + .io_mem_cmd_payload_address(dataCache_1__io_mem_cmd_payload_address), + .io_mem_cmd_payload_data(dataCache_1__io_mem_cmd_payload_data), + .io_mem_cmd_payload_mask(dataCache_1__io_mem_cmd_payload_mask), + .io_mem_cmd_payload_length(dataCache_1__io_mem_cmd_payload_length), + .io_mem_cmd_payload_last(dataCache_1__io_mem_cmd_payload_last), + .io_mem_rsp_valid(dBus_rsp_valid), + .io_mem_rsp_payload_data(dBus_rsp_payload_data), + .io_mem_rsp_payload_error(dBus_rsp_payload_error), + .clk(clk), + .reset(reset) + ); + always @(*) begin + case(_zz_372_) + 3'b000 : begin + _zz_243_ = DBusCachedPlugin_redoBranch_payload; + end + 3'b001 : begin + _zz_243_ = CsrPlugin_jumpInterface_payload; + end + 3'b010 : begin + _zz_243_ = BranchPlugin_jumpInterface_payload; + end + 3'b011 : begin + _zz_243_ = IBusCachedPlugin_redoBranch_payload; + end + default : begin + _zz_243_ = IBusCachedPlugin_pcs_4; + end + endcase + end + + `ifndef SYNTHESIS + always @(*) begin + case(decode_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; + default : decode_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_1_) + `Src1CtrlEnum_defaultEncoding_RS : _zz_1__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_1__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_1__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_1__string = "URS1 "; + default : _zz_1__string = "????????????"; + endcase + end + always @(*) begin + case(_zz_2_) + `Src1CtrlEnum_defaultEncoding_RS : _zz_2__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_2__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_2__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_2__string = "URS1 "; + default : _zz_2__string = "????????????"; + endcase + end + always @(*) begin + case(_zz_3_) + `Src1CtrlEnum_defaultEncoding_RS : _zz_3__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_3__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_3__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_3__string = "URS1 "; + default : _zz_3__string = "????????????"; + endcase + end + always @(*) begin + case(decode_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_4_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_4__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_4__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_4__string = "AND_1"; + default : _zz_4__string = "?????"; + endcase + end + always @(*) begin + case(_zz_5_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_5__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_5__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_5__string = "AND_1"; + default : _zz_5__string = "?????"; + endcase + end + always @(*) begin + case(_zz_6_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_6__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_6__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_6__string = "AND_1"; + default : _zz_6__string = "?????"; + endcase + end + always @(*) begin + case(_zz_7_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_7__string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_7__string = "XRET"; + default : _zz_7__string = "????"; + endcase + end + always @(*) begin + case(_zz_8_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_8__string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_8__string = "XRET"; + default : _zz_8__string = "????"; + endcase + end + always @(*) begin + case(_zz_9_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_9__string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_9__string = "XRET"; + default : _zz_9__string = "????"; + endcase + end + always @(*) begin + case(_zz_10_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_10__string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_10__string = "XRET"; + default : _zz_10__string = "????"; + endcase + end + always @(*) begin + case(decode_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET"; + default : decode_ENV_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_11_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_11__string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_11__string = "XRET"; + default : _zz_11__string = "????"; + endcase + end + always @(*) begin + case(_zz_12_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_12__string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_12__string = "XRET"; + default : _zz_12__string = "????"; + endcase + end + always @(*) begin + case(_zz_13_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_13__string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_13__string = "XRET"; + default : _zz_13__string = "????"; + endcase + end + always @(*) begin + case(_zz_14_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_14__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_14__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_14__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_14__string = "JALR"; + default : _zz_14__string = "????"; + endcase + end + always @(*) begin + case(_zz_15_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_15__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_15__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_15__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_15__string = "JALR"; + default : _zz_15__string = "????"; + endcase + end + always @(*) begin + case(decode_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; + default : decode_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(_zz_16_) + `Src2CtrlEnum_defaultEncoding_RS : _zz_16__string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_16__string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_16__string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_16__string = "PC "; + default : _zz_16__string = "???"; + endcase + end + always @(*) begin + case(_zz_17_) + `Src2CtrlEnum_defaultEncoding_RS : _zz_17__string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_17__string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_17__string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_17__string = "PC "; + default : _zz_17__string = "???"; + endcase + end + always @(*) begin + case(_zz_18_) + `Src2CtrlEnum_defaultEncoding_RS : _zz_18__string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_18__string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_18__string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_18__string = "PC "; + default : _zz_18__string = "???"; + endcase + end + always @(*) begin + case(decode_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; + default : decode_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_19_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_19__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_19__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_19__string = "BITWISE "; + default : _zz_19__string = "????????"; + endcase + end + always @(*) begin + case(_zz_20_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_20__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_20__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_20__string = "BITWISE "; + default : _zz_20__string = "????????"; + endcase + end + always @(*) begin + case(_zz_21_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_21__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_21__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_21__string = "BITWISE "; + default : _zz_21__string = "????????"; + endcase + end + always @(*) begin + case(_zz_22_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_22__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_22__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_22__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_22__string = "SRA_1 "; + default : _zz_22__string = "?????????"; + endcase + end + always @(*) begin + case(_zz_23_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_23__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_23__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_23__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_23__string = "SRA_1 "; + default : _zz_23__string = "?????????"; + endcase + end + always @(*) begin + case(decode_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; + default : decode_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_24_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_24__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_24__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_24__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_24__string = "SRA_1 "; + default : _zz_24__string = "?????????"; + endcase + end + always @(*) begin + case(_zz_25_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_25__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_25__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_25__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_25__string = "SRA_1 "; + default : _zz_25__string = "?????????"; + endcase + end + always @(*) begin + case(_zz_26_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_26__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_26__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_26__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_26__string = "SRA_1 "; + default : _zz_26__string = "?????????"; + endcase + end + always @(*) begin + case(memory_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : memory_ENV_CTRL_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : memory_ENV_CTRL_string = "XRET"; + default : memory_ENV_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_32_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_32__string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_32__string = "XRET"; + default : _zz_32__string = "????"; + endcase + end + always @(*) begin + case(execute_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : execute_ENV_CTRL_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : execute_ENV_CTRL_string = "XRET"; + default : execute_ENV_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_33_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_33__string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_33__string = "XRET"; + default : _zz_33__string = "????"; + endcase + end + always @(*) begin + case(writeBack_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : writeBack_ENV_CTRL_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : writeBack_ENV_CTRL_string = "XRET"; + default : writeBack_ENV_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_36_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_36__string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_36__string = "XRET"; + default : _zz_36__string = "????"; + endcase + end + always @(*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : execute_BRANCH_CTRL_string = "JALR"; + default : execute_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_39_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_39__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_39__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_39__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_39__string = "JALR"; + default : _zz_39__string = "????"; + endcase + end + always @(*) begin + case(memory_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 "; + default : memory_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_44_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_44__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_44__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_44__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_44__string = "SRA_1 "; + default : _zz_44__string = "?????????"; + endcase + end + always @(*) begin + case(execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; + default : execute_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_46_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_46__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_46__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_46__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_46__string = "SRA_1 "; + default : _zz_46__string = "?????????"; + endcase + end + always @(*) begin + case(execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : execute_SRC2_CTRL_string = "PC "; + default : execute_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(_zz_51_) + `Src2CtrlEnum_defaultEncoding_RS : _zz_51__string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_51__string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_51__string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_51__string = "PC "; + default : _zz_51__string = "???"; + endcase + end + always @(*) begin + case(execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : execute_SRC1_CTRL_string = "URS1 "; + default : execute_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_53_) + `Src1CtrlEnum_defaultEncoding_RS : _zz_53__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_53__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_53__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_53__string = "URS1 "; + default : _zz_53__string = "????????????"; + endcase + end + always @(*) begin + case(execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : execute_ALU_CTRL_string = "BITWISE "; + default : execute_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_56_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_56__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_56__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_56__string = "BITWISE "; + default : _zz_56__string = "????????"; + endcase + end + always @(*) begin + case(execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : execute_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_58_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_58__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_58__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_58__string = "AND_1"; + default : _zz_58__string = "?????"; + endcase + end + always @(*) begin + case(_zz_68_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_68__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_68__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_68__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_68__string = "JALR"; + default : _zz_68__string = "????"; + endcase + end + always @(*) begin + case(_zz_73_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_73__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_73__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_73__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_73__string = "SRA_1 "; + default : _zz_73__string = "?????????"; + endcase + end + always @(*) begin + case(_zz_74_) + `Src2CtrlEnum_defaultEncoding_RS : _zz_74__string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_74__string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_74__string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_74__string = "PC "; + default : _zz_74__string = "???"; + endcase + end + always @(*) begin + case(_zz_81_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_81__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_81__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_81__string = "AND_1"; + default : _zz_81__string = "?????"; + endcase + end + always @(*) begin + case(_zz_82_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_82__string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_82__string = "XRET"; + default : _zz_82__string = "????"; + endcase + end + always @(*) begin + case(_zz_83_) + `Src1CtrlEnum_defaultEncoding_RS : _zz_83__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_83__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_83__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_83__string = "URS1 "; + default : _zz_83__string = "????????????"; + endcase + end + always @(*) begin + case(_zz_87_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_87__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_87__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_87__string = "BITWISE "; + default : _zz_87__string = "????????"; + endcase + end + always @(*) begin + case(decode_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR"; + default : decode_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_95_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_95__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_95__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_95__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_95__string = "JALR"; + default : _zz_95__string = "????"; + endcase + end + always @(*) begin + case(_zz_153_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_153__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_153__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_153__string = "BITWISE "; + default : _zz_153__string = "????????"; + endcase + end + always @(*) begin + case(_zz_154_) + `Src1CtrlEnum_defaultEncoding_RS : _zz_154__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_154__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_154__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_154__string = "URS1 "; + default : _zz_154__string = "????????????"; + endcase + end + always @(*) begin + case(_zz_155_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_155__string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_155__string = "XRET"; + default : _zz_155__string = "????"; + endcase + end + always @(*) begin + case(_zz_156_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_156__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_156__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_156__string = "AND_1"; + default : _zz_156__string = "?????"; + endcase + end + always @(*) begin + case(_zz_157_) + `Src2CtrlEnum_defaultEncoding_RS : _zz_157__string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_157__string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_157__string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_157__string = "PC "; + default : _zz_157__string = "???"; + endcase + end + always @(*) begin + case(_zz_158_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_158__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_158__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_158__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_158__string = "SRA_1 "; + default : _zz_158__string = "?????????"; + endcase + end + always @(*) begin + case(_zz_159_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_159__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_159__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_159__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_159__string = "JALR"; + default : _zz_159__string = "????"; + endcase + end + always @(*) begin + case(decode_to_execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + default : decode_to_execute_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(execute_to_memory_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; + default : execute_to_memory_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(decode_to_execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; + default : decode_to_execute_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(decode_to_execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : decode_to_execute_SRC2_CTRL_string = "PC "; + default : decode_to_execute_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(decode_to_execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; + default : decode_to_execute_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(decode_to_execute_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : decode_to_execute_ENV_CTRL_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : decode_to_execute_ENV_CTRL_string = "XRET"; + default : decode_to_execute_ENV_CTRL_string = "????"; + endcase + end + always @(*) begin + case(execute_to_memory_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : execute_to_memory_ENV_CTRL_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : execute_to_memory_ENV_CTRL_string = "XRET"; + default : execute_to_memory_ENV_CTRL_string = "????"; + endcase + end + always @(*) begin + case(memory_to_writeBack_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET"; + default : memory_to_writeBack_ENV_CTRL_string = "????"; + endcase + end + always @(*) begin + case(decode_to_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(decode_to_execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; + default : decode_to_execute_SRC1_CTRL_string = "????????????"; + endcase + end + `endif + + assign decode_SRC1_CTRL = _zz_1_; + assign _zz_2_ = _zz_3_; + assign decode_MEMORY_MANAGMENT = _zz_78_; + assign decode_CSR_READ_OPCODE = _zz_34_; + assign decode_ALU_BITWISE_CTRL = _zz_4_; + assign _zz_5_ = _zz_6_; + assign decode_CSR_WRITE_OPCODE = _zz_35_; + assign decode_SRC2_FORCE_ZERO = _zz_55_; + assign execute_BRANCH_DO = _zz_38_; + assign execute_SHIFT_RIGHT = _zz_45_; + assign _zz_7_ = _zz_8_; + assign _zz_9_ = _zz_10_; + assign decode_ENV_CTRL = _zz_11_; + assign _zz_12_ = _zz_13_; + assign _zz_14_ = _zz_15_; + assign decode_IS_DIV = _zz_85_; + assign decode_SRC2_CTRL = _zz_16_; + assign _zz_17_ = _zz_18_; + assign decode_IS_RS1_SIGNED = _zz_76_; + assign decode_SRC_LESS_UNSIGNED = _zz_70_; + assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR; + assign decode_MEMORY_WR = _zz_79_; + assign decode_PREDICTION_HAD_BRANCHED2 = _zz_41_; + assign decode_IS_RS2_SIGNED = _zz_75_; + assign memory_MUL_HH = execute_to_memory_MUL_HH; + assign execute_MUL_HH = _zz_28_; + assign execute_MUL_HL = _zz_29_; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_77_; + assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; + assign execute_MEMORY_ADDRESS_LOW = _zz_90_; + assign execute_REGFILE_WRITE_DATA = _zz_57_; + assign memory_MUL_LOW = _zz_27_; + assign decode_ALU_CTRL = _zz_19_; + assign _zz_20_ = _zz_21_; + assign execute_BRANCH_CALC = _zz_37_; + assign execute_MUL_LL = _zz_31_; + assign decode_IS_CSR = _zz_72_; + assign memory_PC = execute_to_memory_PC; + assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_84_; + assign _zz_22_ = _zz_23_; + assign decode_SHIFT_CTRL = _zz_24_; + assign _zz_25_ = _zz_26_; + assign execute_MUL_LH = _zz_30_; + assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; + assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; + assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; + assign decode_FORMAL_PC_NEXT = _zz_98_; + assign memory_IS_MUL = execute_to_memory_IS_MUL; + assign execute_IS_MUL = decode_to_execute_IS_MUL; + assign decode_IS_MUL = _zz_80_; + assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED; + assign execute_IS_DIV = decode_to_execute_IS_DIV; + assign execute_IS_RS2_SIGNED = decode_to_execute_IS_RS2_SIGNED; + assign memory_IS_DIV = execute_to_memory_IS_DIV; + assign writeBack_IS_MUL = memory_to_writeBack_IS_MUL; + assign writeBack_MUL_HH = memory_to_writeBack_MUL_HH; + assign writeBack_MUL_LOW = memory_to_writeBack_MUL_LOW; + assign memory_MUL_HL = execute_to_memory_MUL_HL; + assign memory_MUL_LH = execute_to_memory_MUL_LH; + assign memory_MUL_LL = execute_to_memory_MUL_LL; + assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; + assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; + assign execute_IS_CSR = decode_to_execute_IS_CSR; + assign memory_ENV_CTRL = _zz_32_; + assign execute_ENV_CTRL = _zz_33_; + assign writeBack_ENV_CTRL = _zz_36_; + assign memory_BRANCH_CALC = execute_to_memory_BRANCH_CALC; + assign memory_BRANCH_DO = execute_to_memory_BRANCH_DO; + assign execute_PC = decode_to_execute_PC; + assign execute_PREDICTION_HAD_BRANCHED2 = decode_to_execute_PREDICTION_HAD_BRANCHED2; + assign execute_RS1 = decode_to_execute_RS1; + assign execute_BRANCH_COND_RESULT = _zz_40_; + assign execute_BRANCH_CTRL = _zz_39_; + assign decode_RS2_USE = _zz_71_; + assign decode_RS1_USE = _zz_64_; + always @ (*) begin + _zz_42_ = execute_REGFILE_WRITE_DATA; + if(_zz_244_)begin + _zz_42_ = execute_CsrPlugin_readData; + end + end + + assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID; + assign execute_BYPASSABLE_EXECUTE_STAGE = decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + assign memory_REGFILE_WRITE_VALID = execute_to_memory_REGFILE_WRITE_VALID; + assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION; + assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE; + assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; + always @ (*) begin + decode_RS2 = _zz_62_; + if(_zz_173_)begin + if((_zz_174_ == decode_INSTRUCTION[24 : 20]))begin + decode_RS2 = _zz_175_; + end + end + if(_zz_245_)begin + if(_zz_246_)begin + if(_zz_177_)begin + decode_RS2 = _zz_89_; + end + end + end + if(_zz_247_)begin + if(memory_BYPASSABLE_MEMORY_STAGE)begin + if(_zz_179_)begin + decode_RS2 = _zz_43_; + end + end + end + if(_zz_248_)begin + if(execute_BYPASSABLE_EXECUTE_STAGE)begin + if(_zz_181_)begin + decode_RS2 = _zz_42_; + end + end + end + end + + always @ (*) begin + decode_RS1 = _zz_63_; + if(_zz_173_)begin + if((_zz_174_ == decode_INSTRUCTION[19 : 15]))begin + decode_RS1 = _zz_175_; + end + end + if(_zz_245_)begin + if(_zz_246_)begin + if(_zz_176_)begin + decode_RS1 = _zz_89_; + end + end + end + if(_zz_247_)begin + if(memory_BYPASSABLE_MEMORY_STAGE)begin + if(_zz_178_)begin + decode_RS1 = _zz_43_; + end + end + end + if(_zz_248_)begin + if(execute_BYPASSABLE_EXECUTE_STAGE)begin + if(_zz_180_)begin + decode_RS1 = _zz_42_; + end + end + end + end + + assign memory_SHIFT_RIGHT = execute_to_memory_SHIFT_RIGHT; + always @ (*) begin + _zz_43_ = memory_REGFILE_WRITE_DATA; + if(memory_arbitration_isValid)begin + case(memory_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin + _zz_43_ = _zz_169_; + end + `ShiftCtrlEnum_defaultEncoding_SRL_1, `ShiftCtrlEnum_defaultEncoding_SRA_1 : begin + _zz_43_ = memory_SHIFT_RIGHT; + end + default : begin + end + endcase + end + if(_zz_249_)begin + _zz_43_ = memory_DivPlugin_div_result; + end + end + + assign memory_SHIFT_CTRL = _zz_44_; + assign execute_SHIFT_CTRL = _zz_46_; + assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; + assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; + assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; + assign _zz_50_ = execute_PC; + assign execute_SRC2_CTRL = _zz_51_; + assign execute_SRC1_CTRL = _zz_53_; + assign decode_SRC_USE_SUB_LESS = _zz_66_; + assign decode_SRC_ADD_ZERO = _zz_67_; + assign execute_SRC_ADD_SUB = _zz_49_; + assign execute_SRC_LESS = _zz_47_; + assign execute_ALU_CTRL = _zz_56_; + assign execute_SRC2 = _zz_52_; + assign execute_SRC1 = _zz_54_; + assign execute_ALU_BITWISE_CTRL = _zz_58_; + assign _zz_59_ = writeBack_INSTRUCTION; + assign _zz_60_ = writeBack_REGFILE_WRITE_VALID; + always @ (*) begin + _zz_61_ = 1'b0; + if(lastStageRegFileWrite_valid)begin + _zz_61_ = 1'b1; + end + end + + assign decode_INSTRUCTION_ANTICIPATED = _zz_94_; + always @ (*) begin + decode_REGFILE_WRITE_VALID = _zz_69_; + if((decode_INSTRUCTION[11 : 7] == (5'b00000)))begin + decode_REGFILE_WRITE_VALID = 1'b0; + end + end + + assign decode_LEGAL_INSTRUCTION = _zz_88_; + assign decode_INSTRUCTION_READY = 1'b1; + always @ (*) begin + _zz_89_ = writeBack_REGFILE_WRITE_DATA; + if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin + _zz_89_ = writeBack_DBusCachedPlugin_rspFormated; + end + if((writeBack_arbitration_isValid && writeBack_IS_MUL))begin + case(_zz_277_) + 2'b00 : begin + _zz_89_ = _zz_346_; + end + default : begin + _zz_89_ = _zz_347_; + end + endcase + end + end + + assign writeBack_MEMORY_ADDRESS_LOW = memory_to_writeBack_MEMORY_ADDRESS_LOW; + assign writeBack_MEMORY_WR = memory_to_writeBack_MEMORY_WR; + assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA; + assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE; + assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA; + assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE; + assign execute_MEMORY_MANAGMENT = decode_to_execute_MEMORY_MANAGMENT; + assign execute_RS2 = decode_to_execute_RS2; + assign execute_MEMORY_WR = decode_to_execute_MEMORY_WR; + assign execute_SRC_ADD = _zz_48_; + assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; + assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; + assign decode_MEMORY_ENABLE = _zz_65_; + assign decode_FLUSH_ALL = _zz_86_; + always @ (*) begin + IBusCachedPlugin_rsp_issueDetected = _zz_91_; + if(_zz_250_)begin + IBusCachedPlugin_rsp_issueDetected = 1'b1; + end + end + + always @ (*) begin + _zz_91_ = _zz_92_; + if(_zz_251_)begin + _zz_91_ = 1'b1; + end + end + + always @ (*) begin + _zz_92_ = _zz_93_; + if(_zz_252_)begin + _zz_92_ = 1'b1; + end + end + + always @ (*) begin + _zz_93_ = 1'b0; + if(_zz_253_)begin + _zz_93_ = 1'b1; + end + end + + assign decode_BRANCH_CTRL = _zz_95_; + assign decode_INSTRUCTION = _zz_99_; + always @ (*) begin + _zz_96_ = memory_FORMAL_PC_NEXT; + if(BranchPlugin_jumpInterface_valid)begin + _zz_96_ = BranchPlugin_jumpInterface_payload; + end + end + + always @ (*) begin + _zz_97_ = decode_FORMAL_PC_NEXT; + if(IBusCachedPlugin_predictionJumpInterface_valid)begin + _zz_97_ = IBusCachedPlugin_pcs_4; + end + if(IBusCachedPlugin_redoBranch_valid)begin + _zz_97_ = IBusCachedPlugin_redoBranch_payload; + end + end + + assign decode_PC = _zz_100_; + assign writeBack_PC = memory_to_writeBack_PC; + assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION; + always @ (*) begin + decode_arbitration_haltItself = 1'b0; + if(((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE))begin + decode_arbitration_haltItself = 1'b1; + end + end + + always @ (*) begin + decode_arbitration_haltByOther = 1'b0; + if((decode_arbitration_isValid && (_zz_170_ || _zz_171_)))begin + decode_arbitration_haltByOther = 1'b1; + end + if((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts))begin + decode_arbitration_haltByOther = decode_arbitration_isValid; + end + if(({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET))}} != (3'b000)))begin + decode_arbitration_haltByOther = 1'b1; + end + end + + always @ (*) begin + decode_arbitration_removeIt = 1'b0; + if(_zz_254_)begin + decode_arbitration_removeIt = 1'b1; + end + if(decode_arbitration_isFlushed)begin + decode_arbitration_removeIt = 1'b1; + end + end + + assign decode_arbitration_flushAll = 1'b0; + always @ (*) begin + execute_arbitration_haltItself = 1'b0; + if((_zz_239_ && (! dataCache_1__io_cpu_flush_ready)))begin + execute_arbitration_haltItself = 1'b1; + end + if(((dataCache_1__io_cpu_redo && execute_arbitration_isValid) && execute_MEMORY_ENABLE))begin + execute_arbitration_haltItself = 1'b1; + end + if(_zz_244_)begin + if(execute_CsrPlugin_blockedBySideEffects)begin + execute_arbitration_haltItself = 1'b1; + end + end + end + + assign execute_arbitration_haltByOther = 1'b0; + always @ (*) begin + execute_arbitration_removeIt = 1'b0; + if(execute_arbitration_isFlushed)begin + execute_arbitration_removeIt = 1'b1; + end + end + + always @ (*) begin + execute_arbitration_flushAll = 1'b0; + if(BranchPlugin_jumpInterface_valid)begin + execute_arbitration_flushAll = 1'b1; + end + if(BranchPlugin_branchExceptionPort_valid)begin + execute_arbitration_flushAll = 1'b1; + end + end + + always @ (*) begin + memory_arbitration_haltItself = 1'b0; + if(_zz_249_)begin + if(_zz_255_)begin + memory_arbitration_haltItself = 1'b1; + end + end + end + + assign memory_arbitration_haltByOther = 1'b0; + always @ (*) begin + memory_arbitration_removeIt = 1'b0; + if(BranchPlugin_branchExceptionPort_valid)begin + memory_arbitration_removeIt = 1'b1; + end + if(memory_arbitration_isFlushed)begin + memory_arbitration_removeIt = 1'b1; + end + end + + always @ (*) begin + memory_arbitration_flushAll = 1'b0; + if(DBusCachedPlugin_exceptionBus_valid)begin + memory_arbitration_flushAll = 1'b1; + end + if(_zz_256_)begin + memory_arbitration_flushAll = 1'b1; + end + if(_zz_257_)begin + memory_arbitration_flushAll = 1'b1; + end + end + + always @ (*) begin + writeBack_arbitration_haltItself = 1'b0; + if(dataCache_1__io_cpu_writeBack_haltIt)begin + writeBack_arbitration_haltItself = 1'b1; + end + end + + assign writeBack_arbitration_haltByOther = 1'b0; + always @ (*) begin + writeBack_arbitration_removeIt = 1'b0; + if(DBusCachedPlugin_exceptionBus_valid)begin + writeBack_arbitration_removeIt = 1'b1; + end + if(writeBack_arbitration_isFlushed)begin + writeBack_arbitration_removeIt = 1'b1; + end + end + + always @ (*) begin + writeBack_arbitration_flushAll = 1'b0; + if(DBusCachedPlugin_redoBranch_valid)begin + writeBack_arbitration_flushAll = 1'b1; + end + end + + assign lastStageInstruction = writeBack_INSTRUCTION; + assign lastStagePc = writeBack_PC; + assign lastStageIsValid = writeBack_arbitration_isValid; + assign lastStageIsFiring = writeBack_arbitration_isFiring; + always @ (*) begin + IBusCachedPlugin_fetcherHalt = 1'b0; + if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode}}} != (4'b0000)))begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(_zz_256_)begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(_zz_257_)begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + end + + assign IBusCachedPlugin_fetcherflushIt = 1'b0; + always @ (*) begin + IBusCachedPlugin_incomingInstruction = 1'b0; + if((IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid))begin + IBusCachedPlugin_incomingInstruction = 1'b1; + end + end + + always @ (*) begin + CsrPlugin_jumpInterface_valid = 1'b0; + if(_zz_256_)begin + CsrPlugin_jumpInterface_valid = 1'b1; + end + if(_zz_257_)begin + CsrPlugin_jumpInterface_valid = 1'b1; + end + end + + always @ (*) begin + CsrPlugin_jumpInterface_payload = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); + if(_zz_256_)begin + CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,(2'b00)}; + end + if(_zz_257_)begin + case(_zz_258_) + 2'b11 : begin + CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; + end + default : begin + end + endcase + end + end + + assign CsrPlugin_forceMachineWire = 1'b0; + assign CsrPlugin_allowInterrupts = 1'b1; + assign CsrPlugin_allowException = 1'b1; + assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusCachedPlugin_redoBranch_valid,{IBusCachedPlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}}} != (5'b00000)); + assign _zz_101_ = {IBusCachedPlugin_predictionJumpInterface_valid,{IBusCachedPlugin_redoBranch_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}}; + assign _zz_102_ = (_zz_101_ & (~ _zz_278_)); + assign _zz_103_ = _zz_102_[3]; + assign _zz_104_ = _zz_102_[4]; + assign _zz_105_ = (_zz_102_[1] || _zz_103_); + assign _zz_106_ = (_zz_102_[2] || _zz_103_); + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_243_; + assign _zz_107_ = (! IBusCachedPlugin_fetcherHalt); + assign IBusCachedPlugin_fetchPc_output_valid = (IBusCachedPlugin_fetchPc_preOutput_valid && _zz_107_); + assign IBusCachedPlugin_fetchPc_preOutput_ready = (IBusCachedPlugin_fetchPc_output_ready && _zz_107_); + assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_preOutput_payload; + always @ (*) begin + IBusCachedPlugin_fetchPc_propagatePc = 1'b0; + if((IBusCachedPlugin_iBusRsp_stages_1_input_valid && IBusCachedPlugin_iBusRsp_stages_1_input_ready))begin + IBusCachedPlugin_fetchPc_propagatePc = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_280_); + if(IBusCachedPlugin_jump_pcLoad_valid)begin + IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_jump_pcLoad_payload; + end + IBusCachedPlugin_fetchPc_pc[0] = 1'b0; + IBusCachedPlugin_fetchPc_pc[1] = 1'b0; + end + + always @ (*) begin + IBusCachedPlugin_fetchPc_samplePcNext = 1'b0; + if(IBusCachedPlugin_fetchPc_propagatePc)begin + IBusCachedPlugin_fetchPc_samplePcNext = 1'b1; + end + if(IBusCachedPlugin_jump_pcLoad_valid)begin + IBusCachedPlugin_fetchPc_samplePcNext = 1'b1; + end + if(_zz_259_)begin + IBusCachedPlugin_fetchPc_samplePcNext = 1'b1; + end + end + + assign IBusCachedPlugin_fetchPc_preOutput_valid = _zz_108_; + assign IBusCachedPlugin_fetchPc_preOutput_payload = IBusCachedPlugin_fetchPc_pc; + assign IBusCachedPlugin_iBusRsp_stages_0_input_valid = IBusCachedPlugin_fetchPc_output_valid; + assign IBusCachedPlugin_fetchPc_output_ready = IBusCachedPlugin_iBusRsp_stages_0_input_ready; + assign IBusCachedPlugin_iBusRsp_stages_0_input_payload = IBusCachedPlugin_fetchPc_output_payload; + assign IBusCachedPlugin_iBusRsp_stages_0_inputSample = 1'b1; + always @ (*) begin + IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b0; + if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt)begin + IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b1; + end + end + + assign _zz_109_ = (! IBusCachedPlugin_iBusRsp_stages_0_halt); + assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_109_); + assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_109_); + assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload; + always @ (*) begin + IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b0; + if(IBusCachedPlugin_cache_io_cpu_fetch_haltIt)begin + IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b1; + end + end + + assign _zz_110_ = (! IBusCachedPlugin_iBusRsp_stages_1_halt); + assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_110_); + assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_110_); + assign IBusCachedPlugin_iBusRsp_stages_1_output_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload; + always @ (*) begin + IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt = 1'b0; + if((IBusCachedPlugin_rsp_issueDetected || IBusCachedPlugin_rsp_iBusRspOutputHalt))begin + IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt = 1'b1; + end + end + + assign _zz_111_ = (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt); + assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready && _zz_111_); + assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid && _zz_111_); + assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload = IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload; + assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_112_; + assign _zz_112_ = ((1'b0 && (! _zz_113_)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign _zz_113_ = _zz_114_; + assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_113_; + assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = IBusCachedPlugin_fetchPc_pcReg; + assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! _zz_115_)) || IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready); + assign _zz_115_ = _zz_116_; + assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid = _zz_115_; + assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload = _zz_117_; + always @ (*) begin + IBusCachedPlugin_iBusRsp_readyForError = 1'b1; + if((! IBusCachedPlugin_pcValids_0))begin + IBusCachedPlugin_iBusRsp_readyForError = 1'b0; + end + end + + assign IBusCachedPlugin_pcValids_0 = IBusCachedPlugin_injector_nextPcCalc_valids_1; + assign IBusCachedPlugin_pcValids_1 = IBusCachedPlugin_injector_nextPcCalc_valids_2; + assign IBusCachedPlugin_pcValids_2 = IBusCachedPlugin_injector_nextPcCalc_valids_3; + assign IBusCachedPlugin_pcValids_3 = IBusCachedPlugin_injector_nextPcCalc_valids_4; + assign IBusCachedPlugin_iBusRsp_decodeInput_ready = (! decode_arbitration_isStuck); + assign decode_arbitration_isValid = (IBusCachedPlugin_iBusRsp_decodeInput_valid && (! IBusCachedPlugin_injector_decodeRemoved)); + assign _zz_100_ = IBusCachedPlugin_iBusRsp_decodeInput_payload_pc; + assign _zz_99_ = IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_inst; + assign _zz_98_ = (decode_PC + (32'b00000000000000000000000000000100)); + assign _zz_118_ = _zz_281_[11]; + always @ (*) begin + _zz_119_[18] = _zz_118_; + _zz_119_[17] = _zz_118_; + _zz_119_[16] = _zz_118_; + _zz_119_[15] = _zz_118_; + _zz_119_[14] = _zz_118_; + _zz_119_[13] = _zz_118_; + _zz_119_[12] = _zz_118_; + _zz_119_[11] = _zz_118_; + _zz_119_[10] = _zz_118_; + _zz_119_[9] = _zz_118_; + _zz_119_[8] = _zz_118_; + _zz_119_[7] = _zz_118_; + _zz_119_[6] = _zz_118_; + _zz_119_[5] = _zz_118_; + _zz_119_[4] = _zz_118_; + _zz_119_[3] = _zz_118_; + _zz_119_[2] = _zz_118_; + _zz_119_[1] = _zz_118_; + _zz_119_[0] = _zz_118_; + end + + always @ (*) begin + IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_282_[31])); + if(_zz_124_)begin + IBusCachedPlugin_decodePrediction_cmd_hadBranch = 1'b0; + end + end + + assign _zz_120_ = _zz_283_[19]; + always @ (*) begin + _zz_121_[10] = _zz_120_; + _zz_121_[9] = _zz_120_; + _zz_121_[8] = _zz_120_; + _zz_121_[7] = _zz_120_; + _zz_121_[6] = _zz_120_; + _zz_121_[5] = _zz_120_; + _zz_121_[4] = _zz_120_; + _zz_121_[3] = _zz_120_; + _zz_121_[2] = _zz_120_; + _zz_121_[1] = _zz_120_; + _zz_121_[0] = _zz_120_; + end + + assign _zz_122_ = _zz_284_[11]; + always @ (*) begin + _zz_123_[18] = _zz_122_; + _zz_123_[17] = _zz_122_; + _zz_123_[16] = _zz_122_; + _zz_123_[15] = _zz_122_; + _zz_123_[14] = _zz_122_; + _zz_123_[13] = _zz_122_; + _zz_123_[12] = _zz_122_; + _zz_123_[11] = _zz_122_; + _zz_123_[10] = _zz_122_; + _zz_123_[9] = _zz_122_; + _zz_123_[8] = _zz_122_; + _zz_123_[7] = _zz_122_; + _zz_123_[6] = _zz_122_; + _zz_123_[5] = _zz_122_; + _zz_123_[4] = _zz_122_; + _zz_123_[3] = _zz_122_; + _zz_123_[2] = _zz_122_; + _zz_123_[1] = _zz_122_; + _zz_123_[0] = _zz_122_; + end + + always @ (*) begin + case(decode_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JAL : begin + _zz_124_ = _zz_285_[1]; + end + default : begin + _zz_124_ = _zz_286_[1]; + end + endcase + end + + assign IBusCachedPlugin_predictionJumpInterface_valid = (IBusCachedPlugin_decodePrediction_cmd_hadBranch && decode_arbitration_isFiring); + assign _zz_125_ = _zz_287_[19]; + always @ (*) begin + _zz_126_[10] = _zz_125_; + _zz_126_[9] = _zz_125_; + _zz_126_[8] = _zz_125_; + _zz_126_[7] = _zz_125_; + _zz_126_[6] = _zz_125_; + _zz_126_[5] = _zz_125_; + _zz_126_[4] = _zz_125_; + _zz_126_[3] = _zz_125_; + _zz_126_[2] = _zz_125_; + _zz_126_[1] = _zz_125_; + _zz_126_[0] = _zz_125_; + end + + assign _zz_127_ = _zz_288_[11]; + always @ (*) begin + _zz_128_[18] = _zz_127_; + _zz_128_[17] = _zz_127_; + _zz_128_[16] = _zz_127_; + _zz_128_[15] = _zz_127_; + _zz_128_[14] = _zz_127_; + _zz_128_[13] = _zz_127_; + _zz_128_[12] = _zz_127_; + _zz_128_[11] = _zz_127_; + _zz_128_[10] = _zz_127_; + _zz_128_[9] = _zz_127_; + _zz_128_[8] = _zz_127_; + _zz_128_[7] = _zz_127_; + _zz_128_[6] = _zz_127_; + _zz_128_[5] = _zz_127_; + _zz_128_[4] = _zz_127_; + _zz_128_[3] = _zz_127_; + _zz_128_[2] = _zz_127_; + _zz_128_[1] = _zz_127_; + _zz_128_[0] = _zz_127_; + end + + assign IBusCachedPlugin_pcs_4 = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_126_,{{{_zz_373_,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_128_,{{{_zz_374_,_zz_375_},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); + assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; + always @ (*) begin + iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; + iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; + end + + assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; + assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; + assign _zz_222_ = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign _zz_225_ = (IBusCachedPlugin_jump_pcLoad_valid || IBusCachedPlugin_fetcherflushIt); + assign _zz_226_ = (32'b00000000000000000000000000000000); + assign _zz_223_ = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign _zz_224_ = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign _zz_227_ = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); + assign _zz_228_ = (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready); + assign _zz_229_ = (CsrPlugin_privilege == (2'b00)); + assign _zz_94_ = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); + assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; + always @ (*) begin + IBusCachedPlugin_rsp_redoFetch = 1'b0; + if(_zz_253_)begin + IBusCachedPlugin_rsp_redoFetch = 1'b1; + end + if(_zz_251_)begin + IBusCachedPlugin_rsp_redoFetch = 1'b1; + end + if((! IBusCachedPlugin_iBusRsp_readyForError))begin + IBusCachedPlugin_rsp_redoFetch = 1'b0; + end + end + + always @ (*) begin + _zz_230_ = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); + if(_zz_251_)begin + _zz_230_ = 1'b1; + end + if((! IBusCachedPlugin_iBusRsp_readyForError))begin + _zz_230_ = 1'b0; + end + end + + always @ (*) begin + IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; + if(_zz_252_)begin + IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; + end + if(_zz_250_)begin + IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; + end + if(IBusCachedPlugin_fetcherHalt)begin + IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; + end + end + + always @ (*) begin + IBusCachedPlugin_decodeExceptionPort_payload_code = (4'bxxxx); + if(_zz_252_)begin + IBusCachedPlugin_decodeExceptionPort_payload_code = (4'b1100); + end + if(_zz_250_)begin + IBusCachedPlugin_decodeExceptionPort_payload_code = (4'b0001); + end + end + + assign IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload[31 : 2],(2'b00)}; + assign IBusCachedPlugin_redoBranch_valid = IBusCachedPlugin_rsp_redoFetch; + assign IBusCachedPlugin_redoBranch_payload = IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload; + assign IBusCachedPlugin_iBusRsp_decodeInput_valid = IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid; + assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready = IBusCachedPlugin_iBusRsp_decodeInput_ready; + assign IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; + assign IBusCachedPlugin_iBusRsp_decodeInput_payload_pc = IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload; + assign IBusCachedPlugin_mmuBus_cmd_isValid = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid; + assign IBusCachedPlugin_mmuBus_cmd_virtualAddress = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress; + assign IBusCachedPlugin_mmuBus_cmd_bypassTranslation = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_bypassTranslation; + assign IBusCachedPlugin_mmuBus_end = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_end; + assign _zz_221_ = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign dataCache_1__io_mem_cmd_s2mPipe_valid = (dataCache_1__io_mem_cmd_valid || _zz_129_); + assign _zz_240_ = (! _zz_129_); + assign dataCache_1__io_mem_cmd_s2mPipe_payload_wr = (_zz_129_ ? _zz_130_ : dataCache_1__io_mem_cmd_payload_wr); + assign dataCache_1__io_mem_cmd_s2mPipe_payload_address = (_zz_129_ ? _zz_131_ : dataCache_1__io_mem_cmd_payload_address); + assign dataCache_1__io_mem_cmd_s2mPipe_payload_data = (_zz_129_ ? _zz_132_ : dataCache_1__io_mem_cmd_payload_data); + assign dataCache_1__io_mem_cmd_s2mPipe_payload_mask = (_zz_129_ ? _zz_133_ : dataCache_1__io_mem_cmd_payload_mask); + assign dataCache_1__io_mem_cmd_s2mPipe_payload_length = (_zz_129_ ? _zz_134_ : dataCache_1__io_mem_cmd_payload_length); + assign dataCache_1__io_mem_cmd_s2mPipe_payload_last = (_zz_129_ ? _zz_135_ : dataCache_1__io_mem_cmd_payload_last); + assign dataCache_1__io_mem_cmd_s2mPipe_ready = ((1'b1 && (! dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_valid)) || dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_ready); + assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_valid = _zz_136_; + assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_wr = _zz_137_; + assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_address = _zz_138_; + assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_data = _zz_139_; + assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_mask = _zz_140_; + assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_length = _zz_141_; + assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_last = _zz_142_; + assign dBus_cmd_valid = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_valid; + assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_ready = dBus_cmd_ready; + assign dBus_cmd_payload_wr = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_wr; + assign dBus_cmd_payload_address = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_address; + assign dBus_cmd_payload_data = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_data; + assign dBus_cmd_payload_mask = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_mask; + assign dBus_cmd_payload_length = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_length; + assign dBus_cmd_payload_last = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_last; + assign execute_DBusCachedPlugin_size = execute_INSTRUCTION[13 : 12]; + assign _zz_231_ = (execute_arbitration_isValid && execute_MEMORY_ENABLE); + assign _zz_232_ = execute_SRC_ADD; + always @ (*) begin + case(execute_DBusCachedPlugin_size) + 2'b00 : begin + _zz_143_ = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; + end + 2'b01 : begin + _zz_143_ = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; + end + default : begin + _zz_143_ = execute_RS2[31 : 0]; + end + endcase + end + + assign _zz_239_ = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); + assign _zz_90_ = _zz_232_[1 : 0]; + assign _zz_233_ = (memory_arbitration_isValid && memory_MEMORY_ENABLE); + assign _zz_234_ = memory_REGFILE_WRITE_DATA; + assign DBusCachedPlugin_mmuBus_cmd_isValid = dataCache_1__io_cpu_memory_mmuBus_cmd_isValid; + assign DBusCachedPlugin_mmuBus_cmd_virtualAddress = dataCache_1__io_cpu_memory_mmuBus_cmd_virtualAddress; + assign DBusCachedPlugin_mmuBus_cmd_bypassTranslation = dataCache_1__io_cpu_memory_mmuBus_cmd_bypassTranslation; + always @ (*) begin + _zz_235_ = DBusCachedPlugin_mmuBus_rsp_isIoAccess; + if((1'b0 && (! dataCache_1__io_cpu_memory_isWrite)))begin + _zz_235_ = 1'b1; + end + end + + assign DBusCachedPlugin_mmuBus_end = dataCache_1__io_cpu_memory_mmuBus_end; + assign _zz_236_ = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_237_ = (CsrPlugin_privilege == (2'b00)); + assign _zz_238_ = writeBack_REGFILE_WRITE_DATA; + always @ (*) begin + DBusCachedPlugin_redoBranch_valid = 1'b0; + if(_zz_260_)begin + if(dataCache_1__io_cpu_redo)begin + DBusCachedPlugin_redoBranch_valid = 1'b1; + end + end + end + + assign DBusCachedPlugin_redoBranch_payload = writeBack_PC; + always @ (*) begin + DBusCachedPlugin_exceptionBus_valid = 1'b0; + if(_zz_260_)begin + if(dataCache_1__io_cpu_writeBack_accessError)begin + DBusCachedPlugin_exceptionBus_valid = 1'b1; + end + if(dataCache_1__io_cpu_writeBack_unalignedAccess)begin + DBusCachedPlugin_exceptionBus_valid = 1'b1; + end + if(dataCache_1__io_cpu_writeBack_mmuException)begin + DBusCachedPlugin_exceptionBus_valid = 1'b1; + end + if(dataCache_1__io_cpu_redo)begin + DBusCachedPlugin_exceptionBus_valid = 1'b0; + end + end + end + + assign DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_REGFILE_WRITE_DATA; + always @ (*) begin + DBusCachedPlugin_exceptionBus_payload_code = (4'bxxxx); + if(_zz_260_)begin + if(dataCache_1__io_cpu_writeBack_accessError)begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_289_}; + end + if(dataCache_1__io_cpu_writeBack_unalignedAccess)begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_290_}; + end + if(dataCache_1__io_cpu_writeBack_mmuException)begin + DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? (4'b1111) : (4'b1101)); + end + end + end + + always @ (*) begin + writeBack_DBusCachedPlugin_rspShifted = dataCache_1__io_cpu_writeBack_data; + case(writeBack_MEMORY_ADDRESS_LOW) + 2'b01 : begin + writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1__io_cpu_writeBack_data[15 : 8]; + end + 2'b10 : begin + writeBack_DBusCachedPlugin_rspShifted[15 : 0] = dataCache_1__io_cpu_writeBack_data[31 : 16]; + end + 2'b11 : begin + writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1__io_cpu_writeBack_data[31 : 24]; + end + default : begin + end + endcase + end + + assign _zz_144_ = (writeBack_DBusCachedPlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); + always @ (*) begin + _zz_145_[31] = _zz_144_; + _zz_145_[30] = _zz_144_; + _zz_145_[29] = _zz_144_; + _zz_145_[28] = _zz_144_; + _zz_145_[27] = _zz_144_; + _zz_145_[26] = _zz_144_; + _zz_145_[25] = _zz_144_; + _zz_145_[24] = _zz_144_; + _zz_145_[23] = _zz_144_; + _zz_145_[22] = _zz_144_; + _zz_145_[21] = _zz_144_; + _zz_145_[20] = _zz_144_; + _zz_145_[19] = _zz_144_; + _zz_145_[18] = _zz_144_; + _zz_145_[17] = _zz_144_; + _zz_145_[16] = _zz_144_; + _zz_145_[15] = _zz_144_; + _zz_145_[14] = _zz_144_; + _zz_145_[13] = _zz_144_; + _zz_145_[12] = _zz_144_; + _zz_145_[11] = _zz_144_; + _zz_145_[10] = _zz_144_; + _zz_145_[9] = _zz_144_; + _zz_145_[8] = _zz_144_; + _zz_145_[7 : 0] = writeBack_DBusCachedPlugin_rspShifted[7 : 0]; + end + + assign _zz_146_ = (writeBack_DBusCachedPlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); + always @ (*) begin + _zz_147_[31] = _zz_146_; + _zz_147_[30] = _zz_146_; + _zz_147_[29] = _zz_146_; + _zz_147_[28] = _zz_146_; + _zz_147_[27] = _zz_146_; + _zz_147_[26] = _zz_146_; + _zz_147_[25] = _zz_146_; + _zz_147_[24] = _zz_146_; + _zz_147_[23] = _zz_146_; + _zz_147_[22] = _zz_146_; + _zz_147_[21] = _zz_146_; + _zz_147_[20] = _zz_146_; + _zz_147_[19] = _zz_146_; + _zz_147_[18] = _zz_146_; + _zz_147_[17] = _zz_146_; + _zz_147_[16] = _zz_146_; + _zz_147_[15 : 0] = writeBack_DBusCachedPlugin_rspShifted[15 : 0]; + end + + always @ (*) begin + case(_zz_275_) + 2'b00 : begin + writeBack_DBusCachedPlugin_rspFormated = _zz_145_; + end + 2'b01 : begin + writeBack_DBusCachedPlugin_rspFormated = _zz_147_; + end + default : begin + writeBack_DBusCachedPlugin_rspFormated = writeBack_DBusCachedPlugin_rspShifted; + end + endcase + end + + assign IBusCachedPlugin_mmuBus_rsp_physicalAddress = IBusCachedPlugin_mmuBus_cmd_virtualAddress; + assign IBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; + assign IBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; + assign IBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; + assign IBusCachedPlugin_mmuBus_rsp_isIoAccess = IBusCachedPlugin_mmuBus_rsp_physicalAddress[31]; + assign IBusCachedPlugin_mmuBus_rsp_exception = 1'b0; + assign IBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; + assign IBusCachedPlugin_mmuBus_busy = 1'b0; + assign DBusCachedPlugin_mmuBus_rsp_physicalAddress = DBusCachedPlugin_mmuBus_cmd_virtualAddress; + assign DBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; + assign DBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; + assign DBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; + assign DBusCachedPlugin_mmuBus_rsp_isIoAccess = DBusCachedPlugin_mmuBus_rsp_physicalAddress[31]; + assign DBusCachedPlugin_mmuBus_rsp_exception = 1'b0; + assign DBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; + assign DBusCachedPlugin_mmuBus_busy = 1'b0; + assign _zz_149_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000000100)) == (32'b00000000000000000000000000000100)); + assign _zz_150_ = ((decode_INSTRUCTION & (32'b00000000000000000100000001010000)) == (32'b00000000000000000100000001010000)); + assign _zz_151_ = ((decode_INSTRUCTION & (32'b00000000000000000001000000000000)) == (32'b00000000000000000000000000000000)); + assign _zz_152_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001001000)) == (32'b00000000000000000000000001001000)); + assign _zz_148_ = {({(_zz_376_ == _zz_377_),{_zz_378_,{_zz_379_,_zz_380_}}} != (4'b0000)),{((_zz_381_ == _zz_382_) != (1'b0)),{({_zz_383_,_zz_384_} != (3'b000)),{(_zz_385_ != _zz_386_),{_zz_387_,{_zz_388_,_zz_389_}}}}}}; + assign _zz_88_ = ({((decode_INSTRUCTION & (32'b00000000000000000000000001011111)) == (32'b00000000000000000000000000010111)),{((decode_INSTRUCTION & (32'b00000000000000000000000001111111)) == (32'b00000000000000000000000001101111)),{((decode_INSTRUCTION & (32'b00000000000000000001000001101111)) == (32'b00000000000000000000000000000011)),{((decode_INSTRUCTION & _zz_528_) == (32'b00000000000000000001000001110011)),{(_zz_529_ == _zz_530_),{_zz_531_,{_zz_532_,_zz_533_}}}}}}} != (19'b0000000000000000000)); + assign _zz_153_ = _zz_148_[1 : 0]; + assign _zz_87_ = _zz_153_; + assign _zz_86_ = _zz_291_[0]; + assign _zz_85_ = _zz_292_[0]; + assign _zz_84_ = _zz_293_[0]; + assign _zz_154_ = _zz_148_[7 : 6]; + assign _zz_83_ = _zz_154_; + assign _zz_155_ = _zz_148_[8 : 8]; + assign _zz_82_ = _zz_155_; + assign _zz_156_ = _zz_148_[10 : 9]; + assign _zz_81_ = _zz_156_; + assign _zz_80_ = _zz_294_[0]; + assign _zz_79_ = _zz_295_[0]; + assign _zz_78_ = _zz_296_[0]; + assign _zz_77_ = _zz_297_[0]; + assign _zz_76_ = _zz_298_[0]; + assign _zz_75_ = _zz_299_[0]; + assign _zz_157_ = _zz_148_[18 : 17]; + assign _zz_74_ = _zz_157_; + assign _zz_158_ = _zz_148_[20 : 19]; + assign _zz_73_ = _zz_158_; + assign _zz_72_ = _zz_300_[0]; + assign _zz_71_ = _zz_301_[0]; + assign _zz_70_ = _zz_302_[0]; + assign _zz_69_ = _zz_303_[0]; + assign _zz_159_ = _zz_148_[26 : 25]; + assign _zz_68_ = _zz_159_; + assign _zz_67_ = _zz_304_[0]; + assign _zz_66_ = _zz_305_[0]; + assign _zz_65_ = _zz_306_[0]; + assign _zz_64_ = _zz_307_[0]; + assign decodeExceptionPort_valid = ((decode_arbitration_isValid && decode_INSTRUCTION_READY) && (! decode_LEGAL_INSTRUCTION)); + assign decodeExceptionPort_payload_code = (4'b0010); + assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; + assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; + assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; + assign decode_RegFilePlugin_rs1Data = _zz_241_; + assign decode_RegFilePlugin_rs2Data = _zz_242_; + assign _zz_63_ = decode_RegFilePlugin_rs1Data; + assign _zz_62_ = decode_RegFilePlugin_rs2Data; + always @ (*) begin + lastStageRegFileWrite_valid = (_zz_60_ && writeBack_arbitration_isFiring); + if(_zz_160_)begin + lastStageRegFileWrite_valid = 1'b1; + end + end + + assign lastStageRegFileWrite_payload_address = _zz_59_[11 : 7]; + assign lastStageRegFileWrite_payload_data = _zz_89_; + always @ (*) begin + case(execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2); + end + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2); + end + default : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 ^ execute_SRC2); + end + endcase + end + + always @ (*) begin + case(execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_BITWISE : begin + _zz_161_ = execute_IntAluPlugin_bitwise; + end + `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin + _zz_161_ = {31'd0, _zz_308_}; + end + default : begin + _zz_161_ = execute_SRC_ADD_SUB; + end + endcase + end + + assign _zz_57_ = _zz_161_; + assign _zz_55_ = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); + always @ (*) begin + case(execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : begin + _zz_162_ = execute_RS1; + end + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin + _zz_162_ = {29'd0, _zz_309_}; + end + `Src1CtrlEnum_defaultEncoding_IMU : begin + _zz_162_ = {execute_INSTRUCTION[31 : 12],(12'b000000000000)}; + end + default : begin + _zz_162_ = {27'd0, _zz_310_}; + end + endcase + end + + assign _zz_54_ = _zz_162_; + assign _zz_163_ = _zz_311_[11]; + always @ (*) begin + _zz_164_[19] = _zz_163_; + _zz_164_[18] = _zz_163_; + _zz_164_[17] = _zz_163_; + _zz_164_[16] = _zz_163_; + _zz_164_[15] = _zz_163_; + _zz_164_[14] = _zz_163_; + _zz_164_[13] = _zz_163_; + _zz_164_[12] = _zz_163_; + _zz_164_[11] = _zz_163_; + _zz_164_[10] = _zz_163_; + _zz_164_[9] = _zz_163_; + _zz_164_[8] = _zz_163_; + _zz_164_[7] = _zz_163_; + _zz_164_[6] = _zz_163_; + _zz_164_[5] = _zz_163_; + _zz_164_[4] = _zz_163_; + _zz_164_[3] = _zz_163_; + _zz_164_[2] = _zz_163_; + _zz_164_[1] = _zz_163_; + _zz_164_[0] = _zz_163_; + end + + assign _zz_165_ = _zz_312_[11]; + always @ (*) begin + _zz_166_[19] = _zz_165_; + _zz_166_[18] = _zz_165_; + _zz_166_[17] = _zz_165_; + _zz_166_[16] = _zz_165_; + _zz_166_[15] = _zz_165_; + _zz_166_[14] = _zz_165_; + _zz_166_[13] = _zz_165_; + _zz_166_[12] = _zz_165_; + _zz_166_[11] = _zz_165_; + _zz_166_[10] = _zz_165_; + _zz_166_[9] = _zz_165_; + _zz_166_[8] = _zz_165_; + _zz_166_[7] = _zz_165_; + _zz_166_[6] = _zz_165_; + _zz_166_[5] = _zz_165_; + _zz_166_[4] = _zz_165_; + _zz_166_[3] = _zz_165_; + _zz_166_[2] = _zz_165_; + _zz_166_[1] = _zz_165_; + _zz_166_[0] = _zz_165_; + end + + always @ (*) begin + case(execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : begin + _zz_167_ = execute_RS2; + end + `Src2CtrlEnum_defaultEncoding_IMI : begin + _zz_167_ = {_zz_164_,execute_INSTRUCTION[31 : 20]}; + end + `Src2CtrlEnum_defaultEncoding_IMS : begin + _zz_167_ = {_zz_166_,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; + end + default : begin + _zz_167_ = _zz_50_; + end + endcase + end + + assign _zz_52_ = _zz_167_; + always @ (*) begin + execute_SrcPlugin_addSub = _zz_313_; + if(execute_SRC2_FORCE_ZERO)begin + execute_SrcPlugin_addSub = execute_SRC1; + end + end + + assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); + assign _zz_49_ = execute_SrcPlugin_addSub; + assign _zz_48_ = execute_SrcPlugin_addSub; + assign _zz_47_ = execute_SrcPlugin_less; + assign execute_FullBarrelShifterPlugin_amplitude = execute_SRC2[4 : 0]; + always @ (*) begin + _zz_168_[0] = execute_SRC1[31]; + _zz_168_[1] = execute_SRC1[30]; + _zz_168_[2] = execute_SRC1[29]; + _zz_168_[3] = execute_SRC1[28]; + _zz_168_[4] = execute_SRC1[27]; + _zz_168_[5] = execute_SRC1[26]; + _zz_168_[6] = execute_SRC1[25]; + _zz_168_[7] = execute_SRC1[24]; + _zz_168_[8] = execute_SRC1[23]; + _zz_168_[9] = execute_SRC1[22]; + _zz_168_[10] = execute_SRC1[21]; + _zz_168_[11] = execute_SRC1[20]; + _zz_168_[12] = execute_SRC1[19]; + _zz_168_[13] = execute_SRC1[18]; + _zz_168_[14] = execute_SRC1[17]; + _zz_168_[15] = execute_SRC1[16]; + _zz_168_[16] = execute_SRC1[15]; + _zz_168_[17] = execute_SRC1[14]; + _zz_168_[18] = execute_SRC1[13]; + _zz_168_[19] = execute_SRC1[12]; + _zz_168_[20] = execute_SRC1[11]; + _zz_168_[21] = execute_SRC1[10]; + _zz_168_[22] = execute_SRC1[9]; + _zz_168_[23] = execute_SRC1[8]; + _zz_168_[24] = execute_SRC1[7]; + _zz_168_[25] = execute_SRC1[6]; + _zz_168_[26] = execute_SRC1[5]; + _zz_168_[27] = execute_SRC1[4]; + _zz_168_[28] = execute_SRC1[3]; + _zz_168_[29] = execute_SRC1[2]; + _zz_168_[30] = execute_SRC1[1]; + _zz_168_[31] = execute_SRC1[0]; + end + + assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SLL_1) ? _zz_168_ : execute_SRC1); + assign _zz_45_ = _zz_321_; + always @ (*) begin + _zz_169_[0] = memory_SHIFT_RIGHT[31]; + _zz_169_[1] = memory_SHIFT_RIGHT[30]; + _zz_169_[2] = memory_SHIFT_RIGHT[29]; + _zz_169_[3] = memory_SHIFT_RIGHT[28]; + _zz_169_[4] = memory_SHIFT_RIGHT[27]; + _zz_169_[5] = memory_SHIFT_RIGHT[26]; + _zz_169_[6] = memory_SHIFT_RIGHT[25]; + _zz_169_[7] = memory_SHIFT_RIGHT[24]; + _zz_169_[8] = memory_SHIFT_RIGHT[23]; + _zz_169_[9] = memory_SHIFT_RIGHT[22]; + _zz_169_[10] = memory_SHIFT_RIGHT[21]; + _zz_169_[11] = memory_SHIFT_RIGHT[20]; + _zz_169_[12] = memory_SHIFT_RIGHT[19]; + _zz_169_[13] = memory_SHIFT_RIGHT[18]; + _zz_169_[14] = memory_SHIFT_RIGHT[17]; + _zz_169_[15] = memory_SHIFT_RIGHT[16]; + _zz_169_[16] = memory_SHIFT_RIGHT[15]; + _zz_169_[17] = memory_SHIFT_RIGHT[14]; + _zz_169_[18] = memory_SHIFT_RIGHT[13]; + _zz_169_[19] = memory_SHIFT_RIGHT[12]; + _zz_169_[20] = memory_SHIFT_RIGHT[11]; + _zz_169_[21] = memory_SHIFT_RIGHT[10]; + _zz_169_[22] = memory_SHIFT_RIGHT[9]; + _zz_169_[23] = memory_SHIFT_RIGHT[8]; + _zz_169_[24] = memory_SHIFT_RIGHT[7]; + _zz_169_[25] = memory_SHIFT_RIGHT[6]; + _zz_169_[26] = memory_SHIFT_RIGHT[5]; + _zz_169_[27] = memory_SHIFT_RIGHT[4]; + _zz_169_[28] = memory_SHIFT_RIGHT[3]; + _zz_169_[29] = memory_SHIFT_RIGHT[2]; + _zz_169_[30] = memory_SHIFT_RIGHT[1]; + _zz_169_[31] = memory_SHIFT_RIGHT[0]; + end + + always @ (*) begin + _zz_170_ = 1'b0; + if(_zz_261_)begin + if(_zz_262_)begin + if(_zz_176_)begin + _zz_170_ = 1'b1; + end + end + end + if(_zz_263_)begin + if(_zz_264_)begin + if(_zz_178_)begin + _zz_170_ = 1'b1; + end + end + end + if(_zz_265_)begin + if(_zz_266_)begin + if(_zz_180_)begin + _zz_170_ = 1'b1; + end + end + end + if((! decode_RS1_USE))begin + _zz_170_ = 1'b0; + end + end + + always @ (*) begin + _zz_171_ = 1'b0; + if(_zz_261_)begin + if(_zz_262_)begin + if(_zz_177_)begin + _zz_171_ = 1'b1; + end + end + end + if(_zz_263_)begin + if(_zz_264_)begin + if(_zz_179_)begin + _zz_171_ = 1'b1; + end + end + end + if(_zz_265_)begin + if(_zz_266_)begin + if(_zz_181_)begin + _zz_171_ = 1'b1; + end + end + end + if((! decode_RS2_USE))begin + _zz_171_ = 1'b0; + end + end + + assign _zz_172_ = (_zz_60_ && writeBack_arbitration_isFiring); + assign _zz_176_ = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_177_ = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_178_ = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_179_ = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_180_ = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_181_ = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_41_ = IBusCachedPlugin_decodePrediction_cmd_hadBranch; + assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); + assign _zz_182_ = execute_INSTRUCTION[14 : 12]; + always @ (*) begin + if((_zz_182_ == (3'b000))) begin + _zz_183_ = execute_BranchPlugin_eq; + end else if((_zz_182_ == (3'b001))) begin + _zz_183_ = (! execute_BranchPlugin_eq); + end else if((((_zz_182_ & (3'b101)) == (3'b101)))) begin + _zz_183_ = (! execute_SRC_LESS); + end else begin + _zz_183_ = execute_SRC_LESS; + end + end + + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : begin + _zz_184_ = 1'b0; + end + `BranchCtrlEnum_defaultEncoding_JAL : begin + _zz_184_ = 1'b1; + end + `BranchCtrlEnum_defaultEncoding_JALR : begin + _zz_184_ = 1'b1; + end + default : begin + _zz_184_ = _zz_183_; + end + endcase + end + + assign _zz_40_ = _zz_184_; + assign _zz_185_ = _zz_323_[11]; + always @ (*) begin + _zz_186_[19] = _zz_185_; + _zz_186_[18] = _zz_185_; + _zz_186_[17] = _zz_185_; + _zz_186_[16] = _zz_185_; + _zz_186_[15] = _zz_185_; + _zz_186_[14] = _zz_185_; + _zz_186_[13] = _zz_185_; + _zz_186_[12] = _zz_185_; + _zz_186_[11] = _zz_185_; + _zz_186_[10] = _zz_185_; + _zz_186_[9] = _zz_185_; + _zz_186_[8] = _zz_185_; + _zz_186_[7] = _zz_185_; + _zz_186_[6] = _zz_185_; + _zz_186_[5] = _zz_185_; + _zz_186_[4] = _zz_185_; + _zz_186_[3] = _zz_185_; + _zz_186_[2] = _zz_185_; + _zz_186_[1] = _zz_185_; + _zz_186_[0] = _zz_185_; + end + + assign _zz_187_ = _zz_324_[19]; + always @ (*) begin + _zz_188_[10] = _zz_187_; + _zz_188_[9] = _zz_187_; + _zz_188_[8] = _zz_187_; + _zz_188_[7] = _zz_187_; + _zz_188_[6] = _zz_187_; + _zz_188_[5] = _zz_187_; + _zz_188_[4] = _zz_187_; + _zz_188_[3] = _zz_187_; + _zz_188_[2] = _zz_187_; + _zz_188_[1] = _zz_187_; + _zz_188_[0] = _zz_187_; + end + + assign _zz_189_ = _zz_325_[11]; + always @ (*) begin + _zz_190_[18] = _zz_189_; + _zz_190_[17] = _zz_189_; + _zz_190_[16] = _zz_189_; + _zz_190_[15] = _zz_189_; + _zz_190_[14] = _zz_189_; + _zz_190_[13] = _zz_189_; + _zz_190_[12] = _zz_189_; + _zz_190_[11] = _zz_189_; + _zz_190_[10] = _zz_189_; + _zz_190_[9] = _zz_189_; + _zz_190_[8] = _zz_189_; + _zz_190_[7] = _zz_189_; + _zz_190_[6] = _zz_189_; + _zz_190_[5] = _zz_189_; + _zz_190_[4] = _zz_189_; + _zz_190_[3] = _zz_189_; + _zz_190_[2] = _zz_189_; + _zz_190_[1] = _zz_189_; + _zz_190_[0] = _zz_189_; + end + + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JALR : begin + _zz_191_ = (_zz_326_[1] ^ execute_RS1[1]); + end + `BranchCtrlEnum_defaultEncoding_JAL : begin + _zz_191_ = _zz_327_[1]; + end + default : begin + _zz_191_ = _zz_328_[1]; + end + endcase + end + + assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_191_); + assign _zz_38_ = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget); + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JALR : begin + execute_BranchPlugin_branch_src1 = execute_RS1; + end + default : begin + execute_BranchPlugin_branch_src1 = execute_PC; + end + endcase + end + + assign _zz_192_ = _zz_329_[11]; + always @ (*) begin + _zz_193_[19] = _zz_192_; + _zz_193_[18] = _zz_192_; + _zz_193_[17] = _zz_192_; + _zz_193_[16] = _zz_192_; + _zz_193_[15] = _zz_192_; + _zz_193_[14] = _zz_192_; + _zz_193_[13] = _zz_192_; + _zz_193_[12] = _zz_192_; + _zz_193_[11] = _zz_192_; + _zz_193_[10] = _zz_192_; + _zz_193_[9] = _zz_192_; + _zz_193_[8] = _zz_192_; + _zz_193_[7] = _zz_192_; + _zz_193_[6] = _zz_192_; + _zz_193_[5] = _zz_192_; + _zz_193_[4] = _zz_192_; + _zz_193_[3] = _zz_192_; + _zz_193_[2] = _zz_192_; + _zz_193_[1] = _zz_192_; + _zz_193_[0] = _zz_192_; + end + + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JALR : begin + execute_BranchPlugin_branch_src2 = {_zz_193_,execute_INSTRUCTION[31 : 20]}; + end + default : begin + execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_195_,{{{_zz_545_,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_197_,{{{_zz_546_,_zz_547_},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); + if(execute_PREDICTION_HAD_BRANCHED2)begin + execute_BranchPlugin_branch_src2 = {29'd0, _zz_332_}; + end + end + endcase + end + + assign _zz_194_ = _zz_330_[19]; + always @ (*) begin + _zz_195_[10] = _zz_194_; + _zz_195_[9] = _zz_194_; + _zz_195_[8] = _zz_194_; + _zz_195_[7] = _zz_194_; + _zz_195_[6] = _zz_194_; + _zz_195_[5] = _zz_194_; + _zz_195_[4] = _zz_194_; + _zz_195_[3] = _zz_194_; + _zz_195_[2] = _zz_194_; + _zz_195_[1] = _zz_194_; + _zz_195_[0] = _zz_194_; + end + + assign _zz_196_ = _zz_331_[11]; + always @ (*) begin + _zz_197_[18] = _zz_196_; + _zz_197_[17] = _zz_196_; + _zz_197_[16] = _zz_196_; + _zz_197_[15] = _zz_196_; + _zz_197_[14] = _zz_196_; + _zz_197_[13] = _zz_196_; + _zz_197_[12] = _zz_196_; + _zz_197_[11] = _zz_196_; + _zz_197_[10] = _zz_196_; + _zz_197_[9] = _zz_196_; + _zz_197_[8] = _zz_196_; + _zz_197_[7] = _zz_196_; + _zz_197_[6] = _zz_196_; + _zz_197_[5] = _zz_196_; + _zz_197_[4] = _zz_196_; + _zz_197_[3] = _zz_196_; + _zz_197_[2] = _zz_196_; + _zz_197_[1] = _zz_196_; + _zz_197_[0] = _zz_196_; + end + + assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); + assign _zz_37_ = {execute_BranchPlugin_branchAdder[31 : 1],(1'b0)}; + assign BranchPlugin_jumpInterface_valid = ((memory_arbitration_isValid && (! memory_arbitration_isStuckByOthers)) && memory_BRANCH_DO); + assign BranchPlugin_jumpInterface_payload = memory_BRANCH_CALC; + assign BranchPlugin_branchExceptionPort_valid = (memory_arbitration_isValid && (memory_BRANCH_DO && memory_BRANCH_CALC[1])); + assign BranchPlugin_branchExceptionPort_payload_code = (4'b0000); + assign BranchPlugin_branchExceptionPort_payload_badAddr = memory_BRANCH_CALC; + assign IBusCachedPlugin_decodePrediction_rsp_wasWrong = BranchPlugin_jumpInterface_valid; + always @ (*) begin + CsrPlugin_privilege = (2'b11); + if(CsrPlugin_forceMachineWire)begin + CsrPlugin_privilege = (2'b11); + end + end + + assign CsrPlugin_misa_base = (2'b01); + assign CsrPlugin_misa_extensions = (26'b00000000000000000001000010); + assign _zz_198_ = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_199_ = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_200_ = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = (2'b11); + assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); + assign _zz_201_ = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; + assign _zz_202_ = _zz_333_[0]; + always @ (*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + if(_zz_254_)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; + end + if(decode_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b0; + end + end + + always @ (*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + if(execute_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b0; + end + end + + always @ (*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + if(BranchPlugin_branchExceptionPort_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1; + end + if(memory_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b0; + end + end + + always @ (*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + if(DBusCachedPlugin_exceptionBus_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b1; + end + if(writeBack_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b0; + end + end + + assign CsrPlugin_exceptionPendings_0 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + assign CsrPlugin_exceptionPendings_1 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + assign CsrPlugin_exceptionPendings_2 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + assign CsrPlugin_exceptionPendings_3 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && CsrPlugin_allowException); + assign CsrPlugin_lastStageWasWfi = 1'b0; + always @ (*) begin + CsrPlugin_pipelineLiberator_done = ((! ({writeBack_arbitration_isValid,{memory_arbitration_isValid,execute_arbitration_isValid}} != (3'b000))) && IBusCachedPlugin_pcValids_3); + if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != (3'b000)))begin + CsrPlugin_pipelineLiberator_done = 1'b0; + end + if(CsrPlugin_hadException)begin + CsrPlugin_pipelineLiberator_done = 1'b0; + end + end + + assign CsrPlugin_interruptJump = ((CsrPlugin_interrupt_valid && CsrPlugin_pipelineLiberator_done) && CsrPlugin_allowInterrupts); + always @ (*) begin + CsrPlugin_targetPrivilege = CsrPlugin_interrupt_targetPrivilege; + if(CsrPlugin_hadException)begin + CsrPlugin_targetPrivilege = CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; + end + end + + always @ (*) begin + CsrPlugin_trapCause = CsrPlugin_interrupt_code; + if(CsrPlugin_hadException)begin + CsrPlugin_trapCause = CsrPlugin_exceptionPortCtrl_exceptionContext_code; + end + end + + always @ (*) begin + CsrPlugin_xtvec_mode = (2'bxx); + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_xtvec_mode = CsrPlugin_mtvec_mode; + end + default : begin + end + endcase + end + + always @ (*) begin + CsrPlugin_xtvec_base = (30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_xtvec_base = CsrPlugin_mtvec_base; + end + default : begin + end + endcase + end + + assign contextSwitching = CsrPlugin_jumpInterface_valid; + assign _zz_35_ = (! (((decode_INSTRUCTION[14 : 13] == (2'b01)) && (decode_INSTRUCTION[19 : 15] == (5'b00000))) || ((decode_INSTRUCTION[14 : 13] == (2'b11)) && (decode_INSTRUCTION[19 : 15] == (5'b00000))))); + assign _zz_34_ = (decode_INSTRUCTION[13 : 7] != (7'b0100000)); + assign execute_CsrPlugin_inWfi = 1'b0; + assign execute_CsrPlugin_blockedBySideEffects = ({writeBack_arbitration_isValid,memory_arbitration_isValid} != (2'b00)); + always @ (*) begin + execute_CsrPlugin_illegalAccess = 1'b1; + case(execute_CsrPlugin_csrAddress) + 12'b101111000000 : begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + 12'b001100000000 : begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + 12'b001101000001 : begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + 12'b001100000101 : begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + 12'b001101000100 : begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + 12'b110011000000 : begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + 12'b001101000011 : begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + 12'b111111000000 : begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + 12'b001100000100 : begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + 12'b001101000010 : begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + default : begin + end + endcase + if((CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]))begin + execute_CsrPlugin_illegalAccess = 1'b1; + end + if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + + always @ (*) begin + execute_CsrPlugin_illegalInstruction = 1'b0; + if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)))begin + if((CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]))begin + execute_CsrPlugin_illegalInstruction = 1'b1; + end + end + end + + always @ (*) begin + execute_CsrPlugin_readData = (32'b00000000000000000000000000000000); + case(execute_CsrPlugin_csrAddress) + 12'b101111000000 : begin + execute_CsrPlugin_readData[31 : 0] = _zz_210_; + end + 12'b001100000000 : begin + execute_CsrPlugin_readData[12 : 11] = CsrPlugin_mstatus_MPP; + execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mstatus_MPIE; + execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mstatus_MIE; + end + 12'b001101000001 : begin + execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mepc; + end + 12'b001100000101 : begin + end + 12'b001101000100 : begin + execute_CsrPlugin_readData[11 : 11] = CsrPlugin_mip_MEIP; + execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mip_MTIP; + execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mip_MSIP; + end + 12'b110011000000 : begin + execute_CsrPlugin_readData[12 : 0] = (13'b1000000000000); + execute_CsrPlugin_readData[25 : 20] = (6'b100000); + end + 12'b001101000011 : begin + execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mtval; + end + 12'b111111000000 : begin + execute_CsrPlugin_readData[31 : 0] = _zz_211_; + end + 12'b001100000100 : begin + execute_CsrPlugin_readData[11 : 11] = CsrPlugin_mie_MEIE; + execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mie_MTIE; + execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mie_MSIE; + end + 12'b001101000010 : begin + execute_CsrPlugin_readData[31 : 31] = CsrPlugin_mcause_interrupt; + execute_CsrPlugin_readData[3 : 0] = CsrPlugin_mcause_exceptionCode; + end + default : begin + end + endcase + end + + assign execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); + assign execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); + assign execute_CsrPlugin_writeEnable = ((execute_CsrPlugin_writeInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers)); + assign execute_CsrPlugin_readEnable = ((execute_CsrPlugin_readInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers)); + assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; + always @ (*) begin + case(_zz_276_) + 1'b0 : begin + execute_CsrPlugin_writeData = execute_SRC1; + end + default : begin + execute_CsrPlugin_writeData = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); + end + endcase + end + + assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; + assign execute_MulPlugin_a = execute_SRC1; + assign execute_MulPlugin_b = execute_SRC2; + always @ (*) begin + case(_zz_267_) + 2'b01 : begin + execute_MulPlugin_aSigned = 1'b1; + end + 2'b10 : begin + execute_MulPlugin_aSigned = 1'b1; + end + default : begin + execute_MulPlugin_aSigned = 1'b0; + end + endcase + end + + always @ (*) begin + case(_zz_267_) + 2'b01 : begin + execute_MulPlugin_bSigned = 1'b1; + end + 2'b10 : begin + execute_MulPlugin_bSigned = 1'b0; + end + default : begin + execute_MulPlugin_bSigned = 1'b0; + end + endcase + end + + assign execute_MulPlugin_aULow = execute_MulPlugin_a[15 : 0]; + assign execute_MulPlugin_bULow = execute_MulPlugin_b[15 : 0]; + assign execute_MulPlugin_aSLow = {1'b0,execute_MulPlugin_a[15 : 0]}; + assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]}; + assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]}; + assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]}; + assign _zz_31_ = (execute_MulPlugin_aULow * execute_MulPlugin_bULow); + assign _zz_30_ = ($signed(execute_MulPlugin_aSLow) * $signed(execute_MulPlugin_bHigh)); + assign _zz_29_ = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow)); + assign _zz_28_ = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh)); + assign _zz_27_ = ($signed(_zz_335_) + $signed(_zz_343_)); + assign writeBack_MulPlugin_result = ($signed(_zz_344_) + $signed(_zz_345_)); + always @ (*) begin + memory_DivPlugin_div_counter_willIncrement = 1'b0; + if(_zz_249_)begin + if(_zz_255_)begin + memory_DivPlugin_div_counter_willIncrement = 1'b1; + end + end + end + + always @ (*) begin + memory_DivPlugin_div_counter_willClear = 1'b0; + if(_zz_268_)begin + memory_DivPlugin_div_counter_willClear = 1'b1; + end + end + + assign memory_DivPlugin_div_counter_willOverflowIfInc = (memory_DivPlugin_div_counter_value == (6'b100001)); + assign memory_DivPlugin_div_counter_willOverflow = (memory_DivPlugin_div_counter_willOverflowIfInc && memory_DivPlugin_div_counter_willIncrement); + always @ (*) begin + if(memory_DivPlugin_div_counter_willOverflow)begin + memory_DivPlugin_div_counter_valueNext = (6'b000000); + end else begin + memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_349_); + end + if(memory_DivPlugin_div_counter_willClear)begin + memory_DivPlugin_div_counter_valueNext = (6'b000000); + end + end + + assign _zz_203_ = memory_DivPlugin_rs1[31 : 0]; + assign _zz_204_ = {memory_DivPlugin_accumulator[31 : 0],_zz_203_[31]}; + assign _zz_205_ = (_zz_204_ - _zz_350_); + assign _zz_206_ = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); + assign _zz_207_ = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_208_ = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); + always @ (*) begin + _zz_209_[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_209_[31 : 0] = execute_RS1; + end + + assign _zz_211_ = (_zz_210_ & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_211_ != (32'b00000000000000000000000000000000)); + assign _zz_26_ = decode_SHIFT_CTRL; + assign _zz_23_ = execute_SHIFT_CTRL; + assign _zz_24_ = _zz_73_; + assign _zz_46_ = decode_to_execute_SHIFT_CTRL; + assign _zz_44_ = execute_to_memory_SHIFT_CTRL; + assign _zz_21_ = decode_ALU_CTRL; + assign _zz_19_ = _zz_87_; + assign _zz_56_ = decode_to_execute_ALU_CTRL; + assign _zz_18_ = decode_SRC2_CTRL; + assign _zz_16_ = _zz_74_; + assign _zz_51_ = decode_to_execute_SRC2_CTRL; + assign _zz_15_ = decode_BRANCH_CTRL; + assign _zz_95_ = _zz_68_; + assign _zz_39_ = decode_to_execute_BRANCH_CTRL; + assign _zz_13_ = decode_ENV_CTRL; + assign _zz_10_ = execute_ENV_CTRL; + assign _zz_8_ = memory_ENV_CTRL; + assign _zz_11_ = _zz_82_; + assign _zz_33_ = decode_to_execute_ENV_CTRL; + assign _zz_32_ = execute_to_memory_ENV_CTRL; + assign _zz_36_ = memory_to_writeBack_ENV_CTRL; + assign _zz_6_ = decode_ALU_BITWISE_CTRL; + assign _zz_4_ = _zz_81_; + assign _zz_58_ = decode_to_execute_ALU_BITWISE_CTRL; + assign _zz_3_ = decode_SRC1_CTRL; + assign _zz_1_ = _zz_83_; + assign _zz_53_ = decode_to_execute_SRC1_CTRL; + assign decode_arbitration_isFlushed = ({writeBack_arbitration_flushAll,{memory_arbitration_flushAll,{execute_arbitration_flushAll,decode_arbitration_flushAll}}} != (4'b0000)); + assign execute_arbitration_isFlushed = ({writeBack_arbitration_flushAll,{memory_arbitration_flushAll,execute_arbitration_flushAll}} != (3'b000)); + assign memory_arbitration_isFlushed = ({writeBack_arbitration_flushAll,memory_arbitration_flushAll} != (2'b00)); + assign writeBack_arbitration_isFlushed = (writeBack_arbitration_flushAll != (1'b0)); + assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (((1'b0 || execute_arbitration_isStuck) || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); + assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers); + assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); + assign decode_arbitration_isFiring = ((decode_arbitration_isValid && (! decode_arbitration_isStuck)) && (! decode_arbitration_removeIt)); + assign execute_arbitration_isStuckByOthers = (execute_arbitration_haltByOther || ((1'b0 || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); + assign execute_arbitration_isStuck = (execute_arbitration_haltItself || execute_arbitration_isStuckByOthers); + assign execute_arbitration_isMoving = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); + assign execute_arbitration_isFiring = ((execute_arbitration_isValid && (! execute_arbitration_isStuck)) && (! execute_arbitration_removeIt)); + assign memory_arbitration_isStuckByOthers = (memory_arbitration_haltByOther || (1'b0 || writeBack_arbitration_isStuck)); + assign memory_arbitration_isStuck = (memory_arbitration_haltItself || memory_arbitration_isStuckByOthers); + assign memory_arbitration_isMoving = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)); + assign memory_arbitration_isFiring = ((memory_arbitration_isValid && (! memory_arbitration_isStuck)) && (! memory_arbitration_removeIt)); + assign writeBack_arbitration_isStuckByOthers = (writeBack_arbitration_haltByOther || 1'b0); + assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers); + assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); + assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); + assign iBusWishbone_ADR = {_zz_369_,_zz_212_}; + assign iBusWishbone_CTI = ((_zz_212_ == (3'b111)) ? (3'b111) : (3'b010)); + assign iBusWishbone_BTE = (2'b00); + assign iBusWishbone_SEL = (4'b1111); + assign iBusWishbone_WE = 1'b0; + assign iBusWishbone_DAT_MOSI = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); + always @ (*) begin + iBusWishbone_CYC = 1'b0; + if(_zz_269_)begin + iBusWishbone_CYC = 1'b1; + end + end + + always @ (*) begin + iBusWishbone_STB = 1'b0; + if(_zz_269_)begin + iBusWishbone_STB = 1'b1; + end + end + + assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); + assign iBus_rsp_valid = _zz_213_; + assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; + assign iBus_rsp_payload_error = 1'b0; + assign _zz_219_ = (dBus_cmd_payload_length != (3'b000)); + assign _zz_215_ = dBus_cmd_valid; + assign _zz_217_ = dBus_cmd_payload_wr; + assign _zz_218_ = (_zz_214_ == dBus_cmd_payload_length); + assign dBus_cmd_ready = (_zz_216_ && (_zz_217_ || _zz_218_)); + assign dBusWishbone_ADR = ((_zz_219_ ? {{dBus_cmd_payload_address[31 : 5],_zz_214_},(2'b00)} : {dBus_cmd_payload_address[31 : 2],(2'b00)}) >>> 2); + assign dBusWishbone_CTI = (_zz_219_ ? (_zz_218_ ? (3'b111) : (3'b010)) : (3'b000)); + assign dBusWishbone_BTE = (2'b00); + assign dBusWishbone_SEL = (_zz_217_ ? dBus_cmd_payload_mask : (4'b1111)); + assign dBusWishbone_WE = _zz_217_; + assign dBusWishbone_DAT_MOSI = dBus_cmd_payload_data; + assign _zz_216_ = (_zz_215_ && dBusWishbone_ACK); + assign dBusWishbone_CYC = _zz_215_; + assign dBusWishbone_STB = _zz_215_; + assign dBus_rsp_valid = _zz_220_; + assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext; + assign dBus_rsp_payload_error = 1'b0; + always @ (posedge clk) begin + if(reset) begin + IBusCachedPlugin_fetchPc_pcReg <= externalResetVector; + IBusCachedPlugin_fetchPc_inc <= 1'b0; + _zz_108_ <= 1'b0; + _zz_114_ <= 1'b0; + _zz_116_ <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; + IBusCachedPlugin_injector_decodeRemoved <= 1'b0; + _zz_129_ <= 1'b0; + _zz_136_ <= 1'b0; + _zz_160_ <= 1'b1; + _zz_173_ <= 1'b0; + CsrPlugin_mstatus_MIE <= 1'b0; + CsrPlugin_mstatus_MPIE <= 1'b0; + CsrPlugin_mstatus_MPP <= (2'b11); + CsrPlugin_mie_MEIE <= 1'b0; + CsrPlugin_mie_MTIE <= 1'b0; + CsrPlugin_mie_MSIE <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; + CsrPlugin_interrupt_valid <= 1'b0; + CsrPlugin_hadException <= 1'b0; + execute_CsrPlugin_wfiWake <= 1'b0; + memory_DivPlugin_div_counter_value <= (6'b000000); + _zz_210_ <= (32'b00000000000000000000000000000000); + execute_arbitration_isValid <= 1'b0; + memory_arbitration_isValid <= 1'b0; + writeBack_arbitration_isValid <= 1'b0; + memory_to_writeBack_REGFILE_WRITE_DATA <= (32'b00000000000000000000000000000000); + memory_to_writeBack_INSTRUCTION <= (32'b00000000000000000000000000000000); + _zz_212_ <= (3'b000); + _zz_213_ <= 1'b0; + _zz_214_ <= (3'b000); + _zz_220_ <= 1'b0; + end else begin + if(IBusCachedPlugin_fetchPc_propagatePc)begin + IBusCachedPlugin_fetchPc_inc <= 1'b0; + end + if(IBusCachedPlugin_jump_pcLoad_valid)begin + IBusCachedPlugin_fetchPc_inc <= 1'b0; + end + if(_zz_259_)begin + IBusCachedPlugin_fetchPc_inc <= 1'b1; + end + if(IBusCachedPlugin_fetchPc_samplePcNext)begin + IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc; + end + _zz_108_ <= 1'b1; + if((IBusCachedPlugin_jump_pcLoad_valid || IBusCachedPlugin_fetcherflushIt))begin + _zz_114_ <= 1'b0; + end + if(_zz_112_)begin + _zz_114_ <= IBusCachedPlugin_iBusRsp_stages_0_output_valid; + end + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin + _zz_116_ <= IBusCachedPlugin_iBusRsp_stages_1_output_valid; + end + if((IBusCachedPlugin_jump_pcLoad_valid || IBusCachedPlugin_fetcherflushIt))begin + _zz_116_ <= 1'b0; + end + if((IBusCachedPlugin_jump_pcLoad_valid || IBusCachedPlugin_fetcherflushIt))begin + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; + end + if((! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready)))begin + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b1; + end + if((IBusCachedPlugin_jump_pcLoad_valid || IBusCachedPlugin_fetcherflushIt))begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + end + if((! (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready)))begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= IBusCachedPlugin_injector_nextPcCalc_valids_0; + end + if((IBusCachedPlugin_jump_pcLoad_valid || IBusCachedPlugin_fetcherflushIt))begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + end + if((IBusCachedPlugin_jump_pcLoad_valid || IBusCachedPlugin_fetcherflushIt))begin + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; + end + if((! execute_arbitration_isStuck))begin + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= IBusCachedPlugin_injector_nextPcCalc_valids_1; + end + if((IBusCachedPlugin_jump_pcLoad_valid || IBusCachedPlugin_fetcherflushIt))begin + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; + end + if((IBusCachedPlugin_jump_pcLoad_valid || IBusCachedPlugin_fetcherflushIt))begin + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; + end + if((! memory_arbitration_isStuck))begin + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= IBusCachedPlugin_injector_nextPcCalc_valids_2; + end + if((IBusCachedPlugin_jump_pcLoad_valid || IBusCachedPlugin_fetcherflushIt))begin + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; + end + if((IBusCachedPlugin_jump_pcLoad_valid || IBusCachedPlugin_fetcherflushIt))begin + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; + end + if((! writeBack_arbitration_isStuck))begin + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= IBusCachedPlugin_injector_nextPcCalc_valids_3; + end + if((IBusCachedPlugin_jump_pcLoad_valid || IBusCachedPlugin_fetcherflushIt))begin + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; + end + if(decode_arbitration_removeIt)begin + IBusCachedPlugin_injector_decodeRemoved <= 1'b1; + end + if((IBusCachedPlugin_jump_pcLoad_valid || IBusCachedPlugin_fetcherflushIt))begin + IBusCachedPlugin_injector_decodeRemoved <= 1'b0; + end + if(dataCache_1__io_mem_cmd_s2mPipe_ready)begin + _zz_129_ <= 1'b0; + end + if(_zz_270_)begin + _zz_129_ <= dataCache_1__io_mem_cmd_valid; + end + if(dataCache_1__io_mem_cmd_s2mPipe_ready)begin + _zz_136_ <= dataCache_1__io_mem_cmd_s2mPipe_valid; + end + _zz_160_ <= 1'b0; + _zz_173_ <= _zz_172_; + if((! decode_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= CsrPlugin_exceptionPortCtrl_exceptionValids_decode; + end + if((! execute_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= (CsrPlugin_exceptionPortCtrl_exceptionValids_decode && (! decode_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= CsrPlugin_exceptionPortCtrl_exceptionValids_execute; + end + if((! memory_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && (! execute_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= CsrPlugin_exceptionPortCtrl_exceptionValids_memory; + end + if((! writeBack_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= (CsrPlugin_exceptionPortCtrl_exceptionValids_memory && (! memory_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; + end + CsrPlugin_interrupt_valid <= 1'b0; + if(_zz_271_)begin + if(_zz_272_)begin + CsrPlugin_interrupt_valid <= 1'b1; + end + if(_zz_273_)begin + CsrPlugin_interrupt_valid <= 1'b1; + end + if(_zz_274_)begin + CsrPlugin_interrupt_valid <= 1'b1; + end + end + CsrPlugin_hadException <= CsrPlugin_exception; + if(_zz_256_)begin + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_mstatus_MIE <= 1'b0; + CsrPlugin_mstatus_MPIE <= CsrPlugin_mstatus_MIE; + CsrPlugin_mstatus_MPP <= CsrPlugin_privilege; + end + default : begin + end + endcase + end + if(_zz_257_)begin + case(_zz_258_) + 2'b11 : begin + CsrPlugin_mstatus_MPP <= (2'b00); + CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; + CsrPlugin_mstatus_MPIE <= 1'b1; + end + default : begin + end + endcase + end + execute_CsrPlugin_wfiWake <= ({_zz_200_,{_zz_199_,_zz_198_}} != (3'b000)); + memory_DivPlugin_div_counter_value <= memory_DivPlugin_div_counter_valueNext; + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_43_; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; + end + if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin + execute_arbitration_isValid <= 1'b0; + end + if(((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)))begin + execute_arbitration_isValid <= decode_arbitration_isValid; + end + if(((! memory_arbitration_isStuck) || memory_arbitration_removeIt))begin + memory_arbitration_isValid <= 1'b0; + end + if(((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)))begin + memory_arbitration_isValid <= execute_arbitration_isValid; + end + if(((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt))begin + writeBack_arbitration_isValid <= 1'b0; + end + if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin + writeBack_arbitration_isValid <= memory_arbitration_isValid; + end + case(execute_CsrPlugin_csrAddress) + 12'b101111000000 : begin + if(execute_CsrPlugin_writeEnable)begin + _zz_210_ <= execute_CsrPlugin_writeData[31 : 0]; + end + end + 12'b001100000000 : begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; + CsrPlugin_mstatus_MPIE <= _zz_363_[0]; + CsrPlugin_mstatus_MIE <= _zz_364_[0]; + end + end + 12'b001101000001 : begin + end + 12'b001100000101 : begin + end + 12'b001101000100 : begin + end + 12'b110011000000 : begin + end + 12'b001101000011 : begin + end + 12'b111111000000 : begin + end + 12'b001100000100 : begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mie_MEIE <= _zz_366_[0]; + CsrPlugin_mie_MTIE <= _zz_367_[0]; + CsrPlugin_mie_MSIE <= _zz_368_[0]; + end + end + 12'b001101000010 : begin + end + default : begin + end + endcase + if(_zz_269_)begin + if(iBusWishbone_ACK)begin + _zz_212_ <= (_zz_212_ + (3'b001)); + end + end + _zz_213_ <= (iBusWishbone_CYC && iBusWishbone_ACK); + if((_zz_215_ && _zz_216_))begin + _zz_214_ <= (_zz_214_ + (3'b001)); + if(_zz_218_)begin + _zz_214_ <= (3'b000); + end + end + _zz_220_ <= ((_zz_215_ && (! dBusWishbone_WE)) && dBusWishbone_ACK); + end + end + + always @ (posedge clk) begin + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin + _zz_117_ <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; + end + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin + IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit; + end + if(IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready)begin + IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; + end + if(_zz_270_)begin + _zz_130_ <= dataCache_1__io_mem_cmd_payload_wr; + _zz_131_ <= dataCache_1__io_mem_cmd_payload_address; + _zz_132_ <= dataCache_1__io_mem_cmd_payload_data; + _zz_133_ <= dataCache_1__io_mem_cmd_payload_mask; + _zz_134_ <= dataCache_1__io_mem_cmd_payload_length; + _zz_135_ <= dataCache_1__io_mem_cmd_payload_last; + end + if(dataCache_1__io_mem_cmd_s2mPipe_ready)begin + _zz_137_ <= dataCache_1__io_mem_cmd_s2mPipe_payload_wr; + _zz_138_ <= dataCache_1__io_mem_cmd_s2mPipe_payload_address; + _zz_139_ <= dataCache_1__io_mem_cmd_s2mPipe_payload_data; + _zz_140_ <= dataCache_1__io_mem_cmd_s2mPipe_payload_mask; + _zz_141_ <= dataCache_1__io_mem_cmd_s2mPipe_payload_length; + _zz_142_ <= dataCache_1__io_mem_cmd_s2mPipe_payload_last; + end + if(_zz_172_)begin + _zz_174_ <= _zz_59_[11 : 7]; + _zz_175_ <= _zz_89_; + end + CsrPlugin_mip_MEIP <= externalInterrupt; + CsrPlugin_mip_MTIP <= timerInterrupt; + CsrPlugin_mip_MSIP <= softwareInterrupt; + CsrPlugin_mcycle <= (CsrPlugin_mcycle + (64'b0000000000000000000000000000000000000000000000000000000000000001)); + if(writeBack_arbitration_isFiring)begin + CsrPlugin_minstret <= (CsrPlugin_minstret + (64'b0000000000000000000000000000000000000000000000000000000000000001)); + end + if(_zz_254_)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_202_ ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_202_ ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); + end + if(BranchPlugin_branchExceptionPort_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= BranchPlugin_branchExceptionPort_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= BranchPlugin_branchExceptionPort_payload_badAddr; + end + if(DBusCachedPlugin_exceptionBus_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr; + end + if(_zz_271_)begin + if(_zz_272_)begin + CsrPlugin_interrupt_code <= (4'b0111); + CsrPlugin_interrupt_targetPrivilege <= (2'b11); + end + if(_zz_273_)begin + CsrPlugin_interrupt_code <= (4'b0011); + CsrPlugin_interrupt_targetPrivilege <= (2'b11); + end + if(_zz_274_)begin + CsrPlugin_interrupt_code <= (4'b1011); + CsrPlugin_interrupt_targetPrivilege <= (2'b11); + end + end + if(_zz_256_)begin + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); + CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause; + CsrPlugin_mepc <= writeBack_PC; + if(CsrPlugin_hadException)begin + CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + end + end + default : begin + end + endcase + end + if((memory_DivPlugin_div_counter_value == (6'b100000)))begin + memory_DivPlugin_div_done <= 1'b1; + end + if((! memory_arbitration_isStuck))begin + memory_DivPlugin_div_done <= 1'b0; + end + if(_zz_249_)begin + if(_zz_255_)begin + memory_DivPlugin_rs1[31 : 0] <= _zz_351_[31:0]; + memory_DivPlugin_accumulator[31 : 0] <= ((! _zz_205_[32]) ? _zz_352_ : _zz_353_); + if((memory_DivPlugin_div_counter_value == (6'b100000)))begin + memory_DivPlugin_div_result <= _zz_354_[31:0]; + end + end + end + if(_zz_268_)begin + memory_DivPlugin_accumulator <= (65'b00000000000000000000000000000000000000000000000000000000000000000); + memory_DivPlugin_rs1 <= ((_zz_208_ ? (~ _zz_209_) : _zz_209_) + _zz_360_); + memory_DivPlugin_rs2 <= ((_zz_207_ ? (~ execute_RS2) : execute_RS2) + _zz_362_); + memory_DivPlugin_div_needRevert <= ((_zz_208_ ^ (_zz_207_ && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == (32'b00000000000000000000000000000000)) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + end + externalInterruptArray_regNext <= externalInterruptArray; + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_MUL <= decode_IS_MUL; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_IS_MUL <= execute_IS_MUL; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_IS_MUL <= memory_IS_MUL; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_FORMAL_PC_NEXT <= _zz_97_; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_FORMAL_PC_NEXT <= execute_FORMAL_PC_NEXT; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_FORMAL_PC_NEXT <= _zz_96_; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_LH <= execute_MUL_LH; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SHIFT_CTRL <= _zz_25_; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_SHIFT_CTRL <= _zz_22_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_PC <= decode_PC; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_PC <= _zz_50_; + end + if(((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)))begin + memory_to_writeBack_PC <= memory_PC; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_CSR <= decode_IS_CSR; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_LL <= execute_MUL_LL; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ALU_CTRL <= _zz_20_; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MUL_LOW <= memory_MUL_LOW; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_REGFILE_WRITE_DATA <= _zz_42_; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_HL <= execute_MUL_HL; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_HH <= execute_MUL_HH; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MUL_HH <= memory_MUL_HH; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_RS2 <= decode_RS2; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_PREDICTION_HAD_BRANCHED2 <= decode_PREDICTION_HAD_BRANCHED2; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_WR <= decode_MEMORY_WR; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_WR <= execute_MEMORY_WR; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_WR <= memory_MEMORY_WR; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC2_CTRL <= _zz_17_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_DIV <= decode_IS_DIV; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_IS_DIV <= execute_IS_DIV; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_RS1 <= decode_RS1; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BRANCH_CTRL <= _zz_14_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ENV_CTRL <= _zz_12_; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_ENV_CTRL <= _zz_9_; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_ENV_CTRL <= _zz_7_; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_SHIFT_RIGHT <= execute_SHIFT_RIGHT; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BRANCH_DO <= execute_BRANCH_DO; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ALU_BITWISE_CTRL <= _zz_5_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_MANAGMENT <= decode_MEMORY_MANAGMENT; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC1_CTRL <= _zz_2_; + end + case(execute_CsrPlugin_csrAddress) + 12'b101111000000 : begin + end + 12'b001100000000 : begin + end + 12'b001101000001 : begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0]; + end + end + 12'b001100000101 : begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mtvec_base <= execute_CsrPlugin_writeData[31 : 2]; + CsrPlugin_mtvec_mode <= execute_CsrPlugin_writeData[1 : 0]; + end + end + 12'b001101000100 : begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mip_MSIP <= _zz_365_[0]; + end + end + 12'b110011000000 : begin + end + 12'b001101000011 : begin + end + 12'b111111000000 : begin + end + 12'b001100000100 : begin + end + 12'b001101000010 : begin + end + default : begin + end + endcase + iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; + dBusWishbone_DAT_MISO_regNext <= dBusWishbone_DAT_MISO; + end + +endmodule + diff --git a/openfpga_flow/benchmarks/processor/vexriscv/vexriscv-verilog_wrap.v b/openfpga_flow/benchmarks/processor/vexriscv/vexriscv-verilog_wrap.v new file mode 100644 index 0000000000..daef087986 --- /dev/null +++ b/openfpga_flow/benchmarks/processor/vexriscv/vexriscv-verilog_wrap.v @@ -0,0 +1,64 @@ +/* +* Copyright (C) 2020 The SymbiFlow Authors. +* +* Use of this source code is governed by a ISC-style +* license that can be found in the LICENSE file or at +* https://opensource.org/licenses/ISC +* +* SPDX-License-Identifier: ISC +*/ + +/* + * Generated by harness_gen.py + * From: VexRiscv.v + */ +module top(input wire clk, input wire stb, input wire di, output wire do); + localparam integer DIN_N = 134; + localparam integer DOUT_N = 148; + + reg [DIN_N-1:0] din; + wire [DOUT_N-1:0] dout; + + reg [DIN_N-1:0] din_shr; + reg [DOUT_N-1:0] dout_shr; + + always @(posedge clk) begin + din_shr <= {din_shr, di}; + dout_shr <= {dout_shr, din_shr[DIN_N-1]}; + if (stb) begin + din <= din_shr; + dout_shr <= dout; + end + end + + assign do = dout_shr[DOUT_N-1]; + VexRiscv dut( + .externalResetVector(din[31:0]), + .timerInterrupt(din[32]), + .externalInterruptArray(din[64:33]), + .iBusWishbone_CYC(dout[0]), + .iBusWishbone_STB(dout[1]), + .iBusWishbone_ACK(din[65]), + .iBusWishbone_WE(dout[2]), + .iBusWishbone_ADR(dout[32:3]), + .iBusWishbone_DAT_MISO(din[97:66]), + .iBusWishbone_DAT_MOSI(dout[64:33]), + .iBusWishbone_SEL(dout[68:65]), + .iBusWishbone_ERR(din[98]), + .iBusWishbone_BTE(dout[70:69]), + .iBusWishbone_CTI(dout[73:71]), + .dBusWishbone_CYC(dout[74]), + .dBusWishbone_STB(dout[75]), + .dBusWishbone_ACK(din[99]), + .dBusWishbone_WE(dout[76]), + .dBusWishbone_ADR(dout[106:77]), + .dBusWishbone_DAT_MISO(din[131:100]), + .dBusWishbone_DAT_MOSI(dout[138:107]), + .dBusWishbone_SEL(dout[142:139]), + .dBusWishbone_ERR(din[132]), + .dBusWishbone_BTE(dout[144:143]), + .dBusWishbone_CTI(dout[147:145]), + .clk(clk), + .reset(din[133]) + ); +endmodule diff --git a/openfpga_flow/benchmarks/processor/vexriscv/vexriscv_large.v b/openfpga_flow/benchmarks/processor/vexriscv_large.v similarity index 100% rename from openfpga_flow/benchmarks/processor/vexriscv/vexriscv_large.v rename to openfpga_flow/benchmarks/processor/vexriscv_large.v diff --git a/openfpga_flow/benchmarks/processor/vexriscv/vexriscv_linux.v b/openfpga_flow/benchmarks/processor/vexriscv_linux.v similarity index 100% rename from openfpga_flow/benchmarks/processor/vexriscv/vexriscv_linux.v rename to openfpga_flow/benchmarks/processor/vexriscv_linux.v diff --git a/openfpga_flow/benchmarks/processor/vexriscv/vexriscv_small.v b/openfpga_flow/benchmarks/processor/vexriscv_small.v similarity index 100% rename from openfpga_flow/benchmarks/processor/vexriscv/vexriscv_small.v rename to openfpga_flow/benchmarks/processor/vexriscv_small.v diff --git a/openfpga_flow/misc/fpgaflow_default_tool_path.conf b/openfpga_flow/misc/fpgaflow_default_tool_path.conf index 62220e5355..c9aa5617ca 100644 --- a/openfpga_flow/misc/fpgaflow_default_tool_path.conf +++ b/openfpga_flow/misc/fpgaflow_default_tool_path.conf @@ -18,21 +18,28 @@ valid_flows = vpr_blif,yosys_vpr [DEFAULT_PARSE_RESULT_VPR] # parser format = , +# io_blocks = "Netlist io blocks: ([0-9]+)", str + clb_blocks = "Netlist clb blocks: ([0-9]+)", str -io_blocks = "Netlist io blocks: ([0-9]+)", str + +lut3s = "lut3\s+: ([0-9]+)", str +lut4s = "lut4\s+: ([0-9]+)", str +lut5s = "lut5\s+: ([0-9]+)", str +lut6s = "lut6\s+: ([0-9]+)", str +total_luts = "lut\s+: ([0-9]+)", str + mult_blocks = "Netlist mult_36 blocks: ([0-9]+)", str memory_blocks = "Netlist memory blocks: ([0-9]+)", str + +grid_tiles = "FPGA sized to ([0-9]+)", str + +critical_path = "Final critical path: ([0-9.]+)", str +channel_width = "Circuit successfully routed with a channel width factor of ([0-9]+)", str + logic_delay = "Total logic delay: ([0-9.]+)", str total_net_delay = "total net delay: ([0-9.]+)", str total_routing_area = "Total routing area: ([0-9.]+)", str total_logic_block_area = "Total used logic block area: ([0-9]+)", str -total_wire_length = "Total wirelength: ([0-9]+)", str -packing_time = "Packing took ([0-9.]+) seconds", str -placement_time = "Placement took ([0-9.]+) seconds", str -routing_time = "Routing took ([0-9.]+) seconds", str -average_net_length = "average net length: ([0-9.]+)", str -critical_path = "Final critical path: ([0-9.]+) ([a-z])s", scientific -total_routing_time = "Routing took ([0-9.]+) seconds", float [DEFAULT_PARSE_RESULT_POWER] pb_type_power="PB Types\s+([0-9]+)", str diff --git a/openfpga_flow/openfpga_shell_scripts/iwls_benchmark_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/iwls_benchmark_example_script.openfpga index 49f1aac733..dbac0b8831 100644 --- a/openfpga_flow/openfpga_shell_scripts/iwls_benchmark_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/iwls_benchmark_example_script.openfpga @@ -2,7 +2,7 @@ # When the global clock is defined as a port of a tile, clock routing in VPR should be skipped # This is due to the Fc_in of clock port is set to 0 for global wiring # The constant net such as logic '0' and logic '1' must be routed because current architecture cannot produce them locally -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --route_chan_width ${VPR_ROUTE_CHAN_WIDTH} --constant_net_method route +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --route_chan_width ${VPR_ROUTE_CHAN_WIDTH} --constant_net_method route --disp on # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} diff --git a/openfpga_flow/openfpga_yosys_techlib/common/dpram_8K_bram.txt b/openfpga_flow/openfpga_yosys_techlib/common/dpram_8K_bram.txt new file mode 100644 index 0000000000..00e6a7ce2a --- /dev/null +++ b/openfpga_flow/openfpga_yosys_techlib/common/dpram_8K_bram.txt @@ -0,0 +1,18 @@ +bram $__MY_DPRAM_1024x8 + init 0 + abits 10 + dbits 8 + groups 2 + ports 1 1 + wrmode 1 0 + enable 1 1 + transp 0 0 + clocks 1 1 + clkpol 1 1 +endbram + +match $__MY_DPRAM_1024x8 + min efficiency 0 + make_transp +endmatch + diff --git a/openfpga_flow/openfpga_yosys_techlib/common/dpram_8K_bram_map.v b/openfpga_flow/openfpga_yosys_techlib/common/dpram_8K_bram_map.v new file mode 100644 index 0000000000..8040772580 --- /dev/null +++ b/openfpga_flow/openfpga_yosys_techlib/common/dpram_8K_bram_map.v @@ -0,0 +1,21 @@ +module $__MY_DPRAM_1024x8 ( + output [0:7] B1DATA, + input CLK1, + input [0:9] B1ADDR, + input [0:9] A1ADDR, + input [0:7] A1DATA, + input A1EN, + input B1EN ); + + generate + dpram_1024x8 #() _TECHMAP_REPLACE_ ( + .clk (CLK1), + .wen (A1EN), + .waddr (A1ADDR), + .data_in (A1DATA), + .ren (B1EN), + .raddr (B1ADDR), + .data_out (B1DATA) ); + endgenerate + +endmodule diff --git a/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm/k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm_cell_sim.v b/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm/k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm_cell_sim.v new file mode 100644 index 0000000000..9a5dfd26e6 --- /dev/null +++ b/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm/k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm_cell_sim.v @@ -0,0 +1,220 @@ +//----------------------------- +// Dual-port RAM 128x8 bit (1Kbit) +// Core logic +//----------------------------- +module dpram_128x8_core ( + input wclk, + input wen, + input [0:6] waddr, + input [0:7] data_in, + input rclk, + input ren, + input [0:6] raddr, + output [0:7] data_out ); + + reg [0:7] ram[0:127]; + reg [0:7] internal; + + assign data_out = internal; + + always @(posedge wclk) begin + if(wen) begin + ram[waddr] <= data_in; + end + end + + always @(posedge rclk) begin + if(ren) begin + internal <= ram[raddr]; + end + end + +endmodule + +//----------------------------- +// Dual-port RAM 128x8 bit (1Kbit) wrapper +// where the read clock and write clock +// are combined to a unified clock +//----------------------------- +module dpram_128x8 ( + input clk, + input wen, + input ren, + input [0:6] waddr, + input [0:6] raddr, + input [0:7] data_in, + output [0:7] data_out ); + + dpram_128x8_core memory_0 ( + .wclk (clk), + .wen (wen), + .waddr (waddr), + .data_in (data_in), + .rclk (clk), + .ren (ren), + .raddr (raddr), + .data_out (data_out) ); + +endmodule + +//----------------------------- +// 18-bit multiplier +//----------------------------- +module mult_18( + input [0:17] A, + input [0:17] B, + output [0:35] Y +); + +assign Y = A * B; + +endmodule + +//----------------------------- +// Native D-type flip-flop +//----------------------------- +(* abc9_flop, lib_whitebox *) +module dff( + output reg Q, + input D, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C) + Q <= D; + 1'b1: + always @(negedge C) + Q <= D; + endcase +endmodule + +//----------------------------- +// D-type flip-flop with active-high asynchronous reset +//----------------------------- +(* abc9_flop, lib_whitebox *) +module dffr( + output reg Q, + input D, + input R, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C or posedge R) + if (R == 1'b1) + Q <= 1'b0; + else + Q <= D; + 1'b1: + always @(negedge C or posedge R) + if (R == 1'b1) + Q <= 1'b0; + else + Q <= D; + endcase +endmodule + +//----------------------------- +// D-type flip-flop with active-high asynchronous set +//----------------------------- +(* abc9_flop, lib_whitebox *) +module dffs( + output reg Q, + input D, + input S, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C or posedge S) + if (S == 1'b1) + Q <= 1'b1; + else + Q <= D; + 1'b1: + always @(negedge C or posedge S) + if (S == 1'b1) + Q <= 1'b1; + else + Q <= D; + endcase +endmodule + +//----------------------------- +// D-type flip-flop with active-low asynchronous reset +//----------------------------- +(* abc9_flop, lib_whitebox *) +module dffrn( + output reg Q, + input D, + input RN, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C or negedge RN) + if (RN == 1'b0) + Q <= 1'b0; + else + Q <= D; + 1'b1: + always @(negedge C or negedge RN) + if (RN == 1'b0) + Q <= 1'b0; + else + Q <= D; + endcase +endmodule + +//----------------------------- +// D-type flip-flop with active-low asynchronous set +//----------------------------- +(* abc9_flop, lib_whitebox *) +module dffsn( + output reg Q, + input D, + input SN, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C or negedge SN) + if (SN == 1'b0) + Q <= 1'b1; + else + Q <= D; + 1'b1: + always @(negedge C or negedge SN) + if (SN == 1'b0) + Q <= 1'b1; + else + Q <= D; + endcase +endmodule + diff --git a/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm/k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm_dff_map.v b/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm/k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm_dff_map.v new file mode 100644 index 0000000000..f8eed8db05 --- /dev/null +++ b/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm/k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm_dff_map.v @@ -0,0 +1,48 @@ +// Basic DFF +module \$_DFF_P_ (D, C, Q); + input D; + input C; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + dff _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C)); +endmodule + +// Async active-high reset +module \$_DFF_PP0_ (D, C, R, Q); + input D; + input C; + input R; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + dffr _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .R(R)); +endmodule + +// Async active-high set +module \$_DFF_PP1_ (D, C, R, Q); + input D; + input C; + input R; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + dffs _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .S(R)); +endmodule + +// Async active-low reset +module \$_DFF_PN0_ (D, C, R, Q); + input D; + input C; + input R; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + dffrn _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .RN(R)); +endmodule + +// Async active-low set +module \$_DFF_PN1_ (D, C, R, Q); + input D; + input C; + input R; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + dffsn _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .SN(R)); +endmodule diff --git a/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_adder_chain_dpram8K_dsp18_fracff_skywater130nm/k4_frac_N8_tileable_adder_chain_dpram8K_dsp18_fracff_skywater130nm_cell_sim.v b/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_adder_chain_dpram8K_dsp18_fracff_skywater130nm/k4_frac_N8_tileable_adder_chain_dpram8K_dsp18_fracff_skywater130nm_cell_sim.v new file mode 100644 index 0000000000..b763446d43 --- /dev/null +++ b/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_adder_chain_dpram8K_dsp18_fracff_skywater130nm/k4_frac_N8_tileable_adder_chain_dpram8K_dsp18_fracff_skywater130nm_cell_sim.v @@ -0,0 +1,220 @@ +//----------------------------- +// Dual-port RAM 1024x8 bit (1Kbit) +// Core logic +//----------------------------- +module dpram_1024x8_core ( + input wclk, + input wen, + input [0:9] waddr, + input [0:7] data_in, + input rclk, + input ren, + input [0:9] raddr, + output [0:7] data_out ); + + reg [0:7] ram[0:1023]; + reg [0:7] internal; + + assign data_out = internal; + + always @(posedge wclk) begin + if(wen) begin + ram[waddr] <= data_in; + end + end + + always @(posedge rclk) begin + if(ren) begin + internal <= ram[raddr]; + end + end + +endmodule + +//----------------------------- +// Dual-port RAM 1024x8 bit (1Kbit) wrapper +// where the read clock and write clock +// are combined to a unified clock +//----------------------------- +module dpram_1024x8 ( + input clk, + input wen, + input ren, + input [0:9] waddr, + input [0:9] raddr, + input [0:7] data_in, + output [0:7] data_out ); + + dpram_1024x8_core memory_0 ( + .wclk (clk), + .wen (wen), + .waddr (waddr), + .data_in (data_in), + .rclk (clk), + .ren (ren), + .raddr (raddr), + .data_out (data_out) ); + +endmodule + +//----------------------------- +// 18-bit multiplier +//----------------------------- +module mult_18( + input [0:17] A, + input [0:17] B, + output [0:35] Y +); + +assign Y = A * B; + +endmodule + +//----------------------------- +// Native D-type flip-flop +//----------------------------- +(* abc9_flop, lib_whitebox *) +module dff( + output reg Q, + input D, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C) + Q <= D; + 1'b1: + always @(negedge C) + Q <= D; + endcase +endmodule + +//----------------------------- +// D-type flip-flop with active-high asynchronous reset +//----------------------------- +(* abc9_flop, lib_whitebox *) +module dffr( + output reg Q, + input D, + input R, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C or posedge R) + if (R == 1'b1) + Q <= 1'b0; + else + Q <= D; + 1'b1: + always @(negedge C or posedge R) + if (R == 1'b1) + Q <= 1'b0; + else + Q <= D; + endcase +endmodule + +//----------------------------- +// D-type flip-flop with active-high asynchronous set +//----------------------------- +(* abc9_flop, lib_whitebox *) +module dffs( + output reg Q, + input D, + input S, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C or posedge S) + if (S == 1'b1) + Q <= 1'b1; + else + Q <= D; + 1'b1: + always @(negedge C or posedge S) + if (S == 1'b1) + Q <= 1'b1; + else + Q <= D; + endcase +endmodule + +//----------------------------- +// D-type flip-flop with active-low asynchronous reset +//----------------------------- +(* abc9_flop, lib_whitebox *) +module dffrn( + output reg Q, + input D, + input RN, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C or negedge RN) + if (RN == 1'b0) + Q <= 1'b0; + else + Q <= D; + 1'b1: + always @(negedge C or negedge RN) + if (RN == 1'b0) + Q <= 1'b0; + else + Q <= D; + endcase +endmodule + +//----------------------------- +// D-type flip-flop with active-low asynchronous set +//----------------------------- +(* abc9_flop, lib_whitebox *) +module dffsn( + output reg Q, + input D, + input SN, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C or negedge SN) + if (SN == 1'b0) + Q <= 1'b1; + else + Q <= D; + 1'b1: + always @(negedge C or negedge SN) + if (SN == 1'b0) + Q <= 1'b1; + else + Q <= D; + endcase +endmodule + diff --git a/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_adder_chain_dpram8K_dsp18_fracff_skywater130nm/k4_frac_N8_tileable_adder_chain_dpram8K_dsp18_fracff_skywater130nm_dff_map.v b/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_adder_chain_dpram8K_dsp18_fracff_skywater130nm/k4_frac_N8_tileable_adder_chain_dpram8K_dsp18_fracff_skywater130nm_dff_map.v new file mode 100644 index 0000000000..f8eed8db05 --- /dev/null +++ b/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_adder_chain_dpram8K_dsp18_fracff_skywater130nm/k4_frac_N8_tileable_adder_chain_dpram8K_dsp18_fracff_skywater130nm_dff_map.v @@ -0,0 +1,48 @@ +// Basic DFF +module \$_DFF_P_ (D, C, Q); + input D; + input C; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + dff _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C)); +endmodule + +// Async active-high reset +module \$_DFF_PP0_ (D, C, R, Q); + input D; + input C; + input R; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + dffr _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .R(R)); +endmodule + +// Async active-high set +module \$_DFF_PP1_ (D, C, R, Q); + input D; + input C; + input R; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + dffs _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .S(R)); +endmodule + +// Async active-low reset +module \$_DFF_PN0_ (D, C, R, Q); + input D; + input C; + input R; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + dffrn _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .RN(R)); +endmodule + +// Async active-low set +module \$_DFF_PN1_ (D, C, R, Q); + input D; + input C; + input R; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + dffsn _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .SN(R)); +endmodule From 7f31f527a4ac7145a1e0713d55ed9636b1a543d3 Mon Sep 17 00:00:00 2001 From: Andrew Pond Date: Thu, 21 Oct 2021 09:55:57 -0600 Subject: [PATCH 17/22] 16 bit adder chain working --- .../micro_benchmark/adder/adder_16/adder_16.v | 2 +- .../adder/adder_16/adder_16_clk.v | 39 + .../micro_benchmark/adder/adder_16/wrapper.v | 41 + openfpga_flow/misc/1k_bram.xml | 1177 +++++++++++++++++ openfpga_flow/misc/1k_bram_openfpga.xml | 352 +++++ .../misc/ys_tmpl_yosys_vpr_adder_flow.ys | 78 ++ .../ys_tmpl_yosys_vpr_bram_dsp_dff_flow.ys | 9 +- ...generate_testbench_example_script.openfpga | 2 +- ...ch_no_clk_modeling_example_script.openfpga | 2 +- .../design_variables.yml | 70 + .../openfpga_yosys_techlib/common/arith_map.v | 88 ++ ...am1K_dsp18_fracff_skywater130nm_cell_sim.v | 9 + openfpga_flow/scripts/run_fpga_flow.py | 2 +- .../signal_gen/config/task.conf | 30 +- 14 files changed, 1884 insertions(+), 17 deletions(-) create mode 100644 openfpga_flow/benchmarks/micro_benchmark/adder/adder_16/adder_16_clk.v create mode 100644 openfpga_flow/benchmarks/micro_benchmark/adder/adder_16/wrapper.v create mode 100644 openfpga_flow/misc/1k_bram.xml create mode 100644 openfpga_flow/misc/1k_bram_openfpga.xml create mode 100644 openfpga_flow/misc/ys_tmpl_yosys_vpr_adder_flow.ys create mode 100644 openfpga_flow/openfpga_timing_annotation/design_variables.yml create mode 100644 openfpga_flow/openfpga_yosys_techlib/common/arith_map.v diff --git a/openfpga_flow/benchmarks/micro_benchmark/adder/adder_16/adder_16.v b/openfpga_flow/benchmarks/micro_benchmark/adder/adder_16/adder_16.v index 2e7d31076f..362d8f6153 100644 --- a/openfpga_flow/benchmarks/micro_benchmark/adder/adder_16/adder_16.v +++ b/openfpga_flow/benchmarks/micro_benchmark/adder/adder_16/adder_16.v @@ -1,7 +1,7 @@ // Creating a scaleable adder module adder_16(cout, sum, a, b, cin); -parameter size = 6; /* declare a parameter. default required */ +parameter size = 3; /* declare a parameter. default required */ output cout; output [size-1:0] sum; // sum uses the size parameter input cin; diff --git a/openfpga_flow/benchmarks/micro_benchmark/adder/adder_16/adder_16_clk.v b/openfpga_flow/benchmarks/micro_benchmark/adder/adder_16/adder_16_clk.v new file mode 100644 index 0000000000..e42f354143 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/adder/adder_16/adder_16_clk.v @@ -0,0 +1,39 @@ +// Creating a scaleable adder + +module adder_16_clk #( + parameter size = 2 +)( + output reg cout, + output reg [size-1:0] sum, // sum uses the size parameter + input cin, + input [size-1:0] a, b, // 'a' and 'b' use the size parameter + input clk_in, + input rst +); + + +// reg [size-1:0] _sum; +// reg _cout; + +always @(posedge clk_in) begin + if (rst) + {sum,cout} <= 0; + else + {sum,cout} <= a + b + cin; +end + +// assign sum = _sum; +// assign cout = _cout; + +// assign {cout, sum} = a + b + cin; + +endmodule + + + + + + + + + diff --git a/openfpga_flow/benchmarks/micro_benchmark/adder/adder_16/wrapper.v b/openfpga_flow/benchmarks/micro_benchmark/adder/adder_16/wrapper.v new file mode 100644 index 0000000000..8a54af1922 --- /dev/null +++ b/openfpga_flow/benchmarks/micro_benchmark/adder/adder_16/wrapper.v @@ -0,0 +1,41 @@ +module adder_16_wrapper( + output cout, + output sum_0, + output sum_1, + output sum_2, + output sum_3, + input cin, + input a_0, + input a_1, + input a_2, + input a_3, + input b_0, + input b_1, + input b_2, + input b_3 +); + +wire [4:0] sum; +assign sum_0 = sum[0]; +assign sum_1 = sum[1]; +assign sum_2 = sum[2]; +assign sum_3 = sum[3]; +wire [4:0] a; +assign a_0 = a[0]; +assign a_1 = a[1]; +assign a_2 = a[2]; +assign a_3 = a[3]; +wire [4:0] b; +assign b_0 = b[0]; +assign b_1 = b[1]; +assign b_2 = b[2]; +assign b_3 = b[3]; + +adder_16 DUT( + .cout(cout), + .sum(sum), + .cin(cin), + .a(a), + .b(b) ); + +endmodule \ No newline at end of file diff --git a/openfpga_flow/misc/1k_bram.xml b/openfpga_flow/misc/1k_bram.xml new file mode 100644 index 0000000000..6b27133503 --- /dev/null +++ b/openfpga_flow/misc/1k_bram.xml @@ -0,0 +1,1177 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + io_top.outpad io_top.inpad + + + + + + + + + + + + io_right.outpad io_right.inpad + + + + + + + + + + + + io_bottom.outpad io_bottom.inpad + + + + + + + + + + + + io_left.outpad io_left.inpad + + + + + + + + + + + + + + + + + + + + + + + + + + clb.clk clb.reset + clb.sc_in clb.cin clb.O[7:0] clb.I[8:0] + clb.O[15:8] clb.I[17:9] + clb.sc_out clb.cout + + + + + + + + + + + + + + mult_18.a[0:5] mult_18.b[0:5] mult_18.out[0:11] + mult_18.a[6:11] mult_18.b[6:11] mult_18.out[12:23] + mult_18.a[12:17] mult_18.b[12:17] mult_18.out[24:35] + + + + + + + + + + + + + + + + + + + + + memory.clk + + memory.waddr[2:0] memory.raddr[3:0] memory.data_in[3:0] memory.wen memory.data_out[3:0] + memory.waddr[6:3] memory.raddr[6:4] memory.data_in[7:4] memory.ren memory.data_out[7:4] + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 + 1 + + + + 1 1 1 + 1 1 + + + + 1 1 1 1 1 + 1 1 1 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ${LUT3_DELAY} + ${LUT3_DELAY} + ${LUT3_DELAY} + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ${LUT4_DELAY} + ${LUT4_DELAY} + ${LUT4_DELAY} + ${LUT4_DELAY} + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/misc/1k_bram_openfpga.xml b/openfpga_flow/misc/1k_bram_openfpga.xml new file mode 100644 index 0000000000..0a9a1d65ba --- /dev/null +++ b/openfpga_flow/misc/1k_bram_openfpga.xml @@ -0,0 +1,352 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + 10e-12 5e-12 + + + 10e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/misc/ys_tmpl_yosys_vpr_adder_flow.ys b/openfpga_flow/misc/ys_tmpl_yosys_vpr_adder_flow.ys new file mode 100644 index 0000000000..56c27123a3 --- /dev/null +++ b/openfpga_flow/misc/ys_tmpl_yosys_vpr_adder_flow.ys @@ -0,0 +1,78 @@ +${READ_VERILOG_FILE} +# read_verilog -lib cells_sim.v +hierarchy -check -top ${TOP_MODULE} +proc + +# flatten +# tribuf -logic +# deminout + +opt_expr +opt_clean +check +opt +wreduce +peepopt +opt_clean +share +# techmap -map +/cmp2lut.v -D LUT_WIDTH=4 +opt_expr +opt_clean +# ice40_dsp (if -dsp) +alumacc +opt +fsm +opt -fast +memory -nomap +opt_clean + +### BRAM +# memory_bram -rules +/ice40/brams.txt +# techmap -map +/ice40/brams_map.v +# ice40_braminit + +### Map +# opt -fast -mux_undef -undriven -fine +# memory_map +# opt -undriven -fine + +### map_gates +# techmap -map +/techmap.v -map +/ice40/arith_map.v +techmap -map ${YOSYS_ADDER_MAP_VERILOG} +opt +# abc -dff (only if -retime) +# ice40_opt + +### map_ffs +# dffsr2dff +# dff2dffe -direct-match $_DFF_* +# techmap -D NO_LUT -map +/ice40/cells_map.v +# opt_expr -mux_undef +# simplemap +# ice40_ffinit +# ice40_ffssr +# ice40_opt -full +stat +### map_luts +abc -lut ${LUT_SIZE} +# abc (only if -abc2) +# ice40_opt (only if -abc2) +# techmap -map +/ice40/latches_map.v +# simplemap (only if -noabc) +# techmap -map +/gate2lut.v -D LUT_WIDTH=4 (only if -noabc) +# abc -dress -lut 4 (skip if -noabc) +# clean +# ice40_unlut (only if -relut) +# opt_lut -dlogic SB_CARRY:I0=1:I1=2:CI=3 (only if -relut) + +### map_cells +# techmap -map +/ice40/cells_map.v (with -D NO_LUT in vpr mode) +# clean + +### check +# hierarchy -check +# stat +# check -noinit +### blif +opt_clean -purge +write_blif -conn -param ${OUTPUT_BLIF} diff --git a/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_dff_flow.ys b/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_dff_flow.ys index 81b1e21ffa..45c5fe758c 100644 --- a/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_dff_flow.ys +++ b/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_dff_flow.ys @@ -54,8 +54,6 @@ chtype -set $mul t:$__soft_mul# Extract arithmetic functions ######################### # Run coarse synthesis ######################### -# Run a tech map with default library -techmap alumacc share opt @@ -66,6 +64,11 @@ opt -fast memory -nomap opt_clean +######################### +# Map $alu to carry chain +######################### +techmap -map ${YOSYS_ADDER_MAP_VERILOG} + ######################### # Map logics to BRAMs ######################### @@ -92,6 +95,8 @@ opt_rmdff opt_clean opt +stat + ######################### # Map LUTs ######################### diff --git a/openfpga_flow/openfpga_shell_scripts/generate_testbench_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/generate_testbench_example_script.openfpga index 0b5cfa2321..e65745efd3 100644 --- a/openfpga_flow/openfpga_shell_scripts/generate_testbench_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/generate_testbench_example_script.openfpga @@ -10,7 +10,7 @@ read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} # Annotate the OpenFPGA architecture to VPR data base # to debug use --verbose options -link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges +link_openfpga_arch --sort_gsb_chan_node_in_edges # Check and correct any naming conflicts in the BLIF netlist check_netlist_naming_conflict --fix --report ./netlist_renaming.xml diff --git a/openfpga_flow/openfpga_shell_scripts/write_full_testbench_no_clk_modeling_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/write_full_testbench_no_clk_modeling_example_script.openfpga index 506364e308..ffb290c128 100644 --- a/openfpga_flow/openfpga_shell_scripts/write_full_testbench_no_clk_modeling_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/write_full_testbench_no_clk_modeling_example_script.openfpga @@ -10,7 +10,7 @@ read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} # Annotate the OpenFPGA architecture to VPR data base # to debug use --verbose options -link_openfpga_arch --sort_gsb_chan_node_in_edges +link_openfpga_arch --activity_file and2_ace_out.act --sort_gsb_chan_node_in_edges # Check and correct any naming conflicts in the BLIF netlist check_netlist_naming_conflict --fix --report ./netlist_renaming.xml diff --git a/openfpga_flow/openfpga_timing_annotation/design_variables.yml b/openfpga_flow/openfpga_timing_annotation/design_variables.yml new file mode 100644 index 0000000000..ca9d82179c --- /dev/null +++ b/openfpga_flow/openfpga_timing_annotation/design_variables.yml @@ -0,0 +1,70 @@ +L1_SB_MUX_DELAY: 1.44e-9 +L2_SB_MUX_DELAY: 1.44e-9 +L4_SB_MUX_DELAY: 1.44e-9 +CB_MUX_DELAY: 1.38e-9 +L1_WIRE_R: 100 +L1_WIRE_C: 1e-12 +L2_WIRE_R: 100 +L2_WIRE_C: 1e-12 +L4_WIRE_R: 100 +L4_WIRE_C: 1e-12 +INPAD_DELAY: 0.11e-9 +OUTPAD_DELAY: 0.11e-9 +FF_T_SETUP: 0.39e-9 +FF_T_CLK2Q: 0.43e-9 +LUT_OUT0_TO_FF_D_DELAY: 1.14e-9 +LUT_OUT1_TO_FF_D_DELAY: 0.56e-9 +LUT_OUT0_TO_FLE_OUT_DELAY: 0.89e-9 +FF0_Q_TO_FLE_OUT_DELAY: 0.88e-9 +LUT_OUT1_TO_FLE_OUT_DELAY: 0.78e-9 +FF1_Q_TO_FLE_OUT_DELAY: 0.89e-9 +LUT_CIN2LUT3_OUT_DELAY: 1.21e-9 +LUT_CIN2LUT4_OUT_DELAY: 1.21e-9 +LUT_CIN2COUT_DELAY: 1.21e-9 +LUT_IN2COUT_DELAY: 1.21e-9 +LUT3_DELAY: 0.92e-9 +LUT3_OUT_TO_FLE_OUT_DELAY: 1.44e-9 +LUT4_DELAY: 1.21e-9 +LUT4_OUT_TO_FLE_OUT_DELAY: 1.46e-9 +ADDER_LUT4_CIN2OUT_DELAY: 1.21e-9 +ADDER_LUT4_CIN2COUT_DELAY: 1.21e-9 +ADDER_LUT4_IN2OUT_DELAY: 1.21e-9 +ADDER_LUT4_IN2COUT_DELAY: 1.21e-9 +CLB_LR_IN2IN_DELAY: 1.46e-9 +CLB_LR_OUT2IN_DELAY: 1.46e-9 +MULT9_A2Y_DELAY_MAX: 1.523e-9 +MULT9_A2Y_DELAY_MIN: 0.776e-9 +MULT9_B2Y_DELAY_MAX: 1.523e-9 +MULT9_B2Y_DELAY_MIN: 0.776e-9 +MULT18_A2Y_DELAY_MAX: 1.523e-9 +MULT18_A2Y_DELAY_MIN: 0.776e-9 +MULT18_B2Y_DELAY_MAX: 1.523e-9 +MULT18_B2Y_DELAY_MIN: 0.776e-9 +MULT18_LR_A2A_DELAY_MAX: 1.46e-9 +MULT18_LR_A2A_DELAY_MIN: 1.46e-9 +MULT18_LR_B2B_DELAY_MAX: 1.46e-9 +MULT18_LR_B2B_DELAY_MIN: 1.46e-9 + + +################# BRAM Delays ################# + +DPRAM_128x8_CLK_TO_WADDR_DELAY: 509e-12 +DPRAM_128x8_CLK_TO_RADDR_DELAY: 509e-12 +DPRAM_128x8_CLK_TO_DATA_IN_DELAY: 509e-12 +DPRAM_128x8_CLK_TO_WEN_DELAY: 509e-12 +DPRAM_128x8_CLK_TO_REN_DELAY: 509e-12 +DPRAM_128x8_CLK_TO_DATA_OUT_DELAY: 6.73e-9 + +DPRAM_1024x8_CLK_TO_WADDR_DELAY: 509e-12 +DPRAM_1024x8_CLK_TO_RADDR_DELAY: 509e-12 +DPRAM_1024x8_CLK_TO_DATA_IN_DELAY: 509e-12 +DPRAM_1024x8_CLK_TO_WEN_DELAY: 509e-12 +DPRAM_1024x8_CLK_TO_REN_DELAY: 509e-12 +DPRAM_1024x8_CLK_TO_DATA_OUT_DELAY: 6.73e-9 + +MEMORY_WADDR_TO_BRAM_WADDR_DELAY: 132e-12 +MEMORY_RADDR_TO_BRAM_RADDR_DELAY: 132e-12 +MEMORY_DATA_IN_TO_BRAM_DATA_IN_DELAY: 132e-12 +MEMORY_WEN_TO_BRAM_WEN_DELAY: 132e-12 +MEMORY_REN_TO_BRAM_REN_DELAY: 132e-12 +BRAM_DATA_OUT_TO_MEMORY_DATA_OUT_DELAY: 40e-12 \ No newline at end of file diff --git a/openfpga_flow/openfpga_yosys_techlib/common/arith_map.v b/openfpga_flow/openfpga_yosys_techlib/common/arith_map.v new file mode 100644 index 0000000000..03f873b4b3 --- /dev/null +++ b/openfpga_flow/openfpga_yosys_techlib/common/arith_map.v @@ -0,0 +1,88 @@ +// Copyright (C) 2020-2021 The SymbiFlow Authors. +// +// Use of this source code is governed by a ISC-style +// license that can be found in the LICENSE file or at +// https://opensource.org/licenses/ISC +// +// SPDX-License-Identifier:ISC + + +// module adder ( +// input a, +// input b, +// input c_in, +// output c_out, +// output sum); + +// assign {c_out, sum} = a + b + c_in; + +// endmodule + + +////////////////////////// +// arithmetic // +////////////////////////// + +(* techmap_celltype = "$alu" *) +module _80_quicklogic_alu (A, B, CI, BI, X, Y, CO); + + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + parameter A_WIDTH = 1; + parameter B_WIDTH = 1; + parameter Y_WIDTH = 1; + + input [A_WIDTH-1:0] A; + input [B_WIDTH-1:0] B; + output [Y_WIDTH-1:0] X, Y; + + input CI, BI; + output [Y_WIDTH-1:0] CO; + + //wire [1024:0] _TECHMAP_DO_ = "splitnets CARRY; clean"; + + (* force_downto *) + wire [Y_WIDTH-1:0] A_buf, B_buf; + \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf)); + \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf)); + + (* force_downto *) + wire [Y_WIDTH-1:0] AA = A_buf; + (* force_downto *) + wire [Y_WIDTH-1:0] BB = B_buf; + wire [Y_WIDTH: 0 ] CARRY; + + assign CO[Y_WIDTH-1:0] = CARRY[Y_WIDTH:1]; + // Due to VPR limitations regarding IO connexion to carry chain, + // we generate the carry chain input signal using an intermediate adder + // since we can connect a & b from io pads, but not cin & cout + generate + adder intermediate_adder ( + .cin ( ), + .cout (CARRY[0]), + .a (CI ), + .b (CI ), + .sumout ( ) + ); + + adder first_adder ( + .cin (CARRY[0]), + .cout (CARRY[1]), + .a (AA[0] ), + .b (BB[0] ), + .sumout (Y[0] ) + ); + endgenerate + + genvar i; + generate for (i = 1; i < Y_WIDTH ; i = i+1) begin:gen3 + adder my_adder ( + .cin (CARRY[i] ), + .cout (CARRY[i+1]), + .a (AA[i] ), + .b (BB[i] ), + .sumout (Y[i] ) + ); + end endgenerate + assign X = AA ^ BB; +endmodule diff --git a/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm/k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm_cell_sim.v b/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm/k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm_cell_sim.v index 9a5dfd26e6..bc54335ac5 100644 --- a/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm/k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm_cell_sim.v +++ b/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm/k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm_cell_sim.v @@ -1,3 +1,12 @@ +module carry_adder ( + input a, b, cin, + output sumout, cout +); + + assign {cout, sumout} = a + b + cin; + +endmodule + //----------------------------- // Dual-port RAM 128x8 bit (1Kbit) // Core logic diff --git a/openfpga_flow/scripts/run_fpga_flow.py b/openfpga_flow/scripts/run_fpga_flow.py index a333ebb8f9..f74514e3c0 100644 --- a/openfpga_flow/scripts/run_fpga_flow.py +++ b/openfpga_flow/scripts/run_fpga_flow.py @@ -698,7 +698,7 @@ def run_rewrite_verilog(): # If there is a template script provided, replace parameters from configuration if not args.ys_rewrite_tmpl: script_cmd = [ - "read_blif %s" % args.top_module+".blif", + "read_blif -wideports %s" % args.top_module+".blif", "write_verilog %s" % args.top_module+"_output_verilog.v" ] command = [cad_tools["yosys_path"], "-p", "; ".join(script_cmd)] diff --git a/openfpga_flow/tasks/benchmark_sweep/signal_gen/config/task.conf b/openfpga_flow/tasks/benchmark_sweep/signal_gen/config/task.conf index f246a8cf17..0b8fde8fa1 100644 --- a/openfpga_flow/tasks/benchmark_sweep/signal_gen/config/task.conf +++ b/openfpga_flow/tasks/benchmark_sweep/signal_gen/config/task.conf @@ -9,7 +9,7 @@ [GENERAL] run_engine=openfpga_shell power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml -power_analysis = true +power_analysis = false spice_output=false verilog_output=true timeout_each_job = 20*60 @@ -17,29 +17,37 @@ fpga_flow=yosys_vpr [OpenFPGA_SHELL] openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga -openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml openfpga_vpr_device_layout= openfpga_clock_modeling=ideal openfpga_fast_configuration= +yosys_adder_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/common/arith_map.v + [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_40nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/clock_divider.v -bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/pulse_generator.v -bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/reset_generator.v +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/adder/adder_16/adder_16.v +# bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/clock_divider.v +# bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/pulse_generator.v +# bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/reset_generator.v [SYNTHESIS_PARAM] -bench0_top = clock_divider +bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_adder_flow.ys + +bench0_top = adder_16 bench0_chan_width = 300 -bench1_top = pulse_generator -bench1_chan_width = 300 +# bench0_top = clock_divider +# bench0_chan_width = 300 + +# bench1_top = pulse_generator +# bench1_chan_width = 300 -bench2_top = reset_generator -bench2_chan_width = 300 +# bench2_top = reset_generator +# bench2_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] end_flow_with_test= From 42d5c1403ad1b220045386ab50ee99eb3f62a490 Mon Sep 17 00:00:00 2001 From: Andrew Pond Date: Wed, 10 Nov 2021 16:20:31 -0700 Subject: [PATCH 18/22] adder chain arch working --- .../misc/ys_tmpl_yosys_vpr_adder_flow.ys | 78 -- .../ys_tmpl_yosys_vpr_bram_dsp_dff_flow.ys | 15 +- ...N8_adder_chain_mem1K_130nm_cc_openfpga.xml | 294 ++++++ .../common/openfpga_dff_map.v | 10 + ...am1K_dsp18_fracff_skywater130nm_cell_sim.v | 2 +- ...ac_N8_tileable_adder_chain_mem1K_130nm.xml | 930 ++++++++++++++++++ 6 files changed, 1243 insertions(+), 86 deletions(-) delete mode 100644 openfpga_flow/misc/ys_tmpl_yosys_vpr_adder_flow.ys create mode 100644 openfpga_flow/openfpga_arch/k4_frac_N8_adder_chain_mem1K_130nm_cc_openfpga.xml create mode 100644 openfpga_flow/vpr_arch/k4_frac_N8_tileable_adder_chain_mem1K_130nm.xml diff --git a/openfpga_flow/misc/ys_tmpl_yosys_vpr_adder_flow.ys b/openfpga_flow/misc/ys_tmpl_yosys_vpr_adder_flow.ys deleted file mode 100644 index 56c27123a3..0000000000 --- a/openfpga_flow/misc/ys_tmpl_yosys_vpr_adder_flow.ys +++ /dev/null @@ -1,78 +0,0 @@ -${READ_VERILOG_FILE} -# read_verilog -lib cells_sim.v -hierarchy -check -top ${TOP_MODULE} -proc - -# flatten -# tribuf -logic -# deminout - -opt_expr -opt_clean -check -opt -wreduce -peepopt -opt_clean -share -# techmap -map +/cmp2lut.v -D LUT_WIDTH=4 -opt_expr -opt_clean -# ice40_dsp (if -dsp) -alumacc -opt -fsm -opt -fast -memory -nomap -opt_clean - -### BRAM -# memory_bram -rules +/ice40/brams.txt -# techmap -map +/ice40/brams_map.v -# ice40_braminit - -### Map -# opt -fast -mux_undef -undriven -fine -# memory_map -# opt -undriven -fine - -### map_gates -# techmap -map +/techmap.v -map +/ice40/arith_map.v -techmap -map ${YOSYS_ADDER_MAP_VERILOG} -opt -# abc -dff (only if -retime) -# ice40_opt - -### map_ffs -# dffsr2dff -# dff2dffe -direct-match $_DFF_* -# techmap -D NO_LUT -map +/ice40/cells_map.v -# opt_expr -mux_undef -# simplemap -# ice40_ffinit -# ice40_ffssr -# ice40_opt -full -stat -### map_luts -abc -lut ${LUT_SIZE} -# abc (only if -abc2) -# ice40_opt (only if -abc2) -# techmap -map +/ice40/latches_map.v -# simplemap (only if -noabc) -# techmap -map +/gate2lut.v -D LUT_WIDTH=4 (only if -noabc) -# abc -dress -lut 4 (skip if -noabc) -# clean -# ice40_unlut (only if -relut) -# opt_lut -dlogic SB_CARRY:I0=1:I1=2:CI=3 (only if -relut) - -### map_cells -# techmap -map +/ice40/cells_map.v (with -D NO_LUT in vpr mode) -# clean - -### check -# hierarchy -check -# stat -# check -noinit -### blif -opt_clean -purge -write_blif -conn -param ${OUTPUT_BLIF} diff --git a/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_dff_flow.ys b/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_dff_flow.ys index 45c5fe758c..9a5d5c9705 100644 --- a/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_dff_flow.ys +++ b/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_dff_flow.ys @@ -52,9 +52,16 @@ select -clear chtype -set $mul t:$__soft_mul# Extract arithmetic functions ######################### -# Run coarse synthesis +# Map $alu to carry chain ######################### alumacc +techmap -map ${YOSYS_ADDER_MAP_VERILOG} + +######################### +# Run coarse synthesis +######################### +# Run a tech map with default library +techmap share opt fsm @@ -64,10 +71,6 @@ opt -fast memory -nomap opt_clean -######################### -# Map $alu to carry chain -######################### -techmap -map ${YOSYS_ADDER_MAP_VERILOG} ######################### # Map logics to BRAMs @@ -95,8 +98,6 @@ opt_rmdff opt_clean opt -stat - ######################### # Map LUTs ######################### diff --git a/openfpga_flow/openfpga_arch/k4_frac_N8_adder_chain_mem1K_130nm_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N8_adder_chain_mem1K_130nm_cc_openfpga.xml new file mode 100644 index 0000000000..0d0d939584 --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_frac_N8_adder_chain_mem1K_130nm_cc_openfpga.xml @@ -0,0 +1,294 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + 10e-12 5e-12 + + + 10e-12 5e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/openfpga_yosys_techlib/common/openfpga_dff_map.v b/openfpga_flow/openfpga_yosys_techlib/common/openfpga_dff_map.v index 8c6c149c42..eae75c5d3b 100644 --- a/openfpga_flow/openfpga_yosys_techlib/common/openfpga_dff_map.v +++ b/openfpga_flow/openfpga_yosys_techlib/common/openfpga_dff_map.v @@ -17,6 +17,16 @@ module \$_DFF_PP0_ (D, C, R, Q); dffr _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .R(R)); endmodule +// Async reset +module \$_DFF_PP1_ (D, C, R, Q); + input D; + input C; + input R; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + dffr _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .R(R)); +endmodule + // Async active-low reset module \$_DFF_PN0_ (D, C, R, Q); input D; diff --git a/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm/k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm_cell_sim.v b/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm/k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm_cell_sim.v index bc54335ac5..61fb154690 100644 --- a/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm/k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm_cell_sim.v +++ b/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm/k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm_cell_sim.v @@ -1,4 +1,4 @@ -module carry_adder ( +module adder ( input a, b, cin, output sumout, cout ); diff --git a/openfpga_flow/vpr_arch/k4_frac_N8_tileable_adder_chain_mem1K_130nm.xml b/openfpga_flow/vpr_arch/k4_frac_N8_tileable_adder_chain_mem1K_130nm.xml new file mode 100644 index 0000000000..788adc002b --- /dev/null +++ b/openfpga_flow/vpr_arch/k4_frac_N8_tileable_adder_chain_mem1K_130nm.xml @@ -0,0 +1,930 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + + + + + + + + + + + + + + + + + + + clb.clk + clb.cin + clb.O[7:0] clb.I[5:0] clb.reset + clb.cout clb.O[15:8] clb.I[11:6] + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 1 1 1 + 1 1 1 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 235e-12 + 235e-12 + 235e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 195e-12 + 195e-12 + 195e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 261e-12 + 261e-12 + 261e-12 + 261e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + From dd983ec348f3422c056786913fe8e4e32eccccef Mon Sep 17 00:00:00 2001 From: Andrew Pond Date: Thu, 11 Nov 2021 12:11:42 -0700 Subject: [PATCH 19/22] CLB carry issue --- .../misc/ys_tmpl_yosys_vpr_bram_dsp_flow.ys | 6 ++++++ .../openfpga_timing_annotation/design_variables.yml | 12 ++++++++++++ 2 files changed, 18 insertions(+) diff --git a/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_flow.ys b/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_flow.ys index d0ff395b63..4111e11d80 100644 --- a/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_flow.ys +++ b/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_flow.ys @@ -51,6 +51,12 @@ wreduce select -clear chtype -set $mul t:$__soft_mul# Extract arithmetic functions +######################### +# Map $alu to carry chain +######################### +alumacc +techmap -map ${YOSYS_ADDER_MAP_VERILOG} + ######################### # Run coarse synthesis ######################### diff --git a/openfpga_flow/openfpga_timing_annotation/design_variables.yml b/openfpga_flow/openfpga_timing_annotation/design_variables.yml index ca9d82179c..36a092e3d0 100644 --- a/openfpga_flow/openfpga_timing_annotation/design_variables.yml +++ b/openfpga_flow/openfpga_timing_annotation/design_variables.yml @@ -46,6 +46,18 @@ MULT18_LR_B2B_DELAY_MAX: 1.46e-9 MULT18_LR_B2B_DELAY_MIN: 1.46e-9 +################# Adder Delays ################# + +ADDER_CIN2OUT_DELAY: 1.21e-9 +ADDER_CIN2COUT_DELAY: 1.21e-9 +ADDER_IN2OUT_DELAY: 1.21e-9 +ADDER_IN2COUT_DELAY: 1.21e-9 + +ARITHMETIC_ADDER_OUT_TO_ARITHMETIC_OUT: 25e-12 +ARITHMETIC_FF_OUT_TO_ARITHMETIC_OUT: 45e-12 + + + ################# BRAM Delays ################# DPRAM_128x8_CLK_TO_WADDR_DELAY: 509e-12 From 727a2ac771edd72fe3c29994116e64d18e3942a7 Mon Sep 17 00:00:00 2001 From: Andrew Pond Date: Thu, 16 Dec 2021 09:05:06 -0700 Subject: [PATCH 20/22] added 4K bram --- .../openfpga_cell_library/verilog/dpram4k.v | 56 +++++++++++++++++++ 1 file changed, 56 insertions(+) create mode 100644 openfpga_flow/openfpga_cell_library/verilog/dpram4k.v diff --git a/openfpga_flow/openfpga_cell_library/verilog/dpram4k.v b/openfpga_flow/openfpga_cell_library/verilog/dpram4k.v new file mode 100644 index 0000000000..bab976c069 --- /dev/null +++ b/openfpga_flow/openfpga_cell_library/verilog/dpram4k.v @@ -0,0 +1,56 @@ +//----------------------------------------------------- +// Design Name : dual_port_ram +// File Name : dpram.v +// Function : Dual port RAM 8x512 +// Coder : Xifan Tang +//----------------------------------------------------- + +module dpram_512x8 ( + input clk, + input wen, + input ren, + input[0:8] waddr, + input[0:8] raddr, + input[0:7] d_in, + output[0:7] d_out ); + + dual_port_sram memory_0 ( + .wclk (clk), + .wen (wen), + .waddr (waddr), + .data_in (d_in), + .rclk (clk), + .ren (ren), + .raddr (raddr), + .d_out (d_out) ); + +endmodule + +module dual_port_sram ( + input wclk, + input wen, + input[0:8] waddr, + input[0:7] data_in, + input rclk, + input ren, + input[0:8] raddr, + output[0:7] d_out ); + + reg[0:7] ram[0:511]; + reg[0:7] internal; + + assign d_out = internal; + + always @(posedge wclk) begin + if(wen) begin + ram[waddr] <= data_in; + end + end + + always @(posedge rclk) begin + if(ren) begin + internal <= ram[raddr]; + end + end + +endmodule From 8c38747d6cbcd147c08c577656e808f73e183b8f Mon Sep 17 00:00:00 2001 From: Andrew Pond Date: Thu, 16 Dec 2021 09:53:16 -0700 Subject: [PATCH 21/22] revised PR --- .../micro_benchmark/adder/adder_16/adder_16.v | 2 +- .../adder/adder_16/adder_16_clk.v | 39 - .../micro_benchmark/adder/adder_16/wrapper.v | 41 - .../{ => VexRiscv_Symbiflow}/VexRiscv.v | 0 .../vexriscv-verilog_wrap.v | 0 .../processor/{ => vexriscv}/vexriscv_large.v | 0 .../processor/{ => vexriscv}/vexriscv_linux.v | 0 .../processor/{ => vexriscv}/vexriscv_small.v | 0 openfpga_flow/misc/1k_bram.xml | 1177 ----------------- openfpga_flow/misc/1k_bram_openfpga.xml | 352 ----- .../misc/ys_tmpl_yosys_vpr_bram_dff_flow.ys | 102 -- .../misc/ys_tmpl_yosys_vpr_bram_dsp_flow.ys | 116 -- ...rac_N4_adder_mem1K_dsp18_40nm_openfpga.xml | 253 ---- ...generate_testbench_example_script.openfpga | 2 +- .../iwls_benchmark_example_script.openfpga | 2 +- ...ite_full_testbench_example_script.openfpga | 2 +- .../micro_benchmark_reg_test.sh | 12 +- openfpga_flow/scripts/run_fpga_flow.py | 2 +- .../k4_series/k4n4_bram/config/task.conf | 4 +- .../signal_gen/config/task.conf | 40 +- 20 files changed, 32 insertions(+), 2114 deletions(-) delete mode 100644 openfpga_flow/benchmarks/micro_benchmark/adder/adder_16/adder_16_clk.v delete mode 100644 openfpga_flow/benchmarks/micro_benchmark/adder/adder_16/wrapper.v rename openfpga_flow/benchmarks/processor/vexriscv/{ => VexRiscv_Symbiflow}/VexRiscv.v (100%) rename openfpga_flow/benchmarks/processor/vexriscv/{ => VexRiscv_Symbiflow}/vexriscv-verilog_wrap.v (100%) rename openfpga_flow/benchmarks/processor/{ => vexriscv}/vexriscv_large.v (100%) rename openfpga_flow/benchmarks/processor/{ => vexriscv}/vexriscv_linux.v (100%) rename openfpga_flow/benchmarks/processor/{ => vexriscv}/vexriscv_small.v (100%) delete mode 100644 openfpga_flow/misc/1k_bram.xml delete mode 100644 openfpga_flow/misc/1k_bram_openfpga.xml delete mode 100644 openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dff_flow.ys delete mode 100644 openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_flow.ys delete mode 100644 openfpga_flow/openfpga_arch/k4_frac_N4_adder_mem1K_dsp18_40nm_openfpga.xml diff --git a/openfpga_flow/benchmarks/micro_benchmark/adder/adder_16/adder_16.v b/openfpga_flow/benchmarks/micro_benchmark/adder/adder_16/adder_16.v index 362d8f6153..30031ce7d7 100644 --- a/openfpga_flow/benchmarks/micro_benchmark/adder/adder_16/adder_16.v +++ b/openfpga_flow/benchmarks/micro_benchmark/adder/adder_16/adder_16.v @@ -1,7 +1,7 @@ // Creating a scaleable adder module adder_16(cout, sum, a, b, cin); -parameter size = 3; /* declare a parameter. default required */ +parameter size = 16; /* declare a parameter. default required */ output cout; output [size-1:0] sum; // sum uses the size parameter input cin; diff --git a/openfpga_flow/benchmarks/micro_benchmark/adder/adder_16/adder_16_clk.v b/openfpga_flow/benchmarks/micro_benchmark/adder/adder_16/adder_16_clk.v deleted file mode 100644 index e42f354143..0000000000 --- a/openfpga_flow/benchmarks/micro_benchmark/adder/adder_16/adder_16_clk.v +++ /dev/null @@ -1,39 +0,0 @@ -// Creating a scaleable adder - -module adder_16_clk #( - parameter size = 2 -)( - output reg cout, - output reg [size-1:0] sum, // sum uses the size parameter - input cin, - input [size-1:0] a, b, // 'a' and 'b' use the size parameter - input clk_in, - input rst -); - - -// reg [size-1:0] _sum; -// reg _cout; - -always @(posedge clk_in) begin - if (rst) - {sum,cout} <= 0; - else - {sum,cout} <= a + b + cin; -end - -// assign sum = _sum; -// assign cout = _cout; - -// assign {cout, sum} = a + b + cin; - -endmodule - - - - - - - - - diff --git a/openfpga_flow/benchmarks/micro_benchmark/adder/adder_16/wrapper.v b/openfpga_flow/benchmarks/micro_benchmark/adder/adder_16/wrapper.v deleted file mode 100644 index 8a54af1922..0000000000 --- a/openfpga_flow/benchmarks/micro_benchmark/adder/adder_16/wrapper.v +++ /dev/null @@ -1,41 +0,0 @@ -module adder_16_wrapper( - output cout, - output sum_0, - output sum_1, - output sum_2, - output sum_3, - input cin, - input a_0, - input a_1, - input a_2, - input a_3, - input b_0, - input b_1, - input b_2, - input b_3 -); - -wire [4:0] sum; -assign sum_0 = sum[0]; -assign sum_1 = sum[1]; -assign sum_2 = sum[2]; -assign sum_3 = sum[3]; -wire [4:0] a; -assign a_0 = a[0]; -assign a_1 = a[1]; -assign a_2 = a[2]; -assign a_3 = a[3]; -wire [4:0] b; -assign b_0 = b[0]; -assign b_1 = b[1]; -assign b_2 = b[2]; -assign b_3 = b[3]; - -adder_16 DUT( - .cout(cout), - .sum(sum), - .cin(cin), - .a(a), - .b(b) ); - -endmodule \ No newline at end of file diff --git a/openfpga_flow/benchmarks/processor/vexriscv/VexRiscv.v b/openfpga_flow/benchmarks/processor/vexriscv/VexRiscv_Symbiflow/VexRiscv.v similarity index 100% rename from openfpga_flow/benchmarks/processor/vexriscv/VexRiscv.v rename to openfpga_flow/benchmarks/processor/vexriscv/VexRiscv_Symbiflow/VexRiscv.v diff --git a/openfpga_flow/benchmarks/processor/vexriscv/vexriscv-verilog_wrap.v b/openfpga_flow/benchmarks/processor/vexriscv/VexRiscv_Symbiflow/vexriscv-verilog_wrap.v similarity index 100% rename from openfpga_flow/benchmarks/processor/vexriscv/vexriscv-verilog_wrap.v rename to openfpga_flow/benchmarks/processor/vexriscv/VexRiscv_Symbiflow/vexriscv-verilog_wrap.v diff --git a/openfpga_flow/benchmarks/processor/vexriscv_large.v b/openfpga_flow/benchmarks/processor/vexriscv/vexriscv_large.v similarity index 100% rename from openfpga_flow/benchmarks/processor/vexriscv_large.v rename to openfpga_flow/benchmarks/processor/vexriscv/vexriscv_large.v diff --git a/openfpga_flow/benchmarks/processor/vexriscv_linux.v b/openfpga_flow/benchmarks/processor/vexriscv/vexriscv_linux.v similarity index 100% rename from openfpga_flow/benchmarks/processor/vexriscv_linux.v rename to openfpga_flow/benchmarks/processor/vexriscv/vexriscv_linux.v diff --git a/openfpga_flow/benchmarks/processor/vexriscv_small.v b/openfpga_flow/benchmarks/processor/vexriscv/vexriscv_small.v similarity index 100% rename from openfpga_flow/benchmarks/processor/vexriscv_small.v rename to openfpga_flow/benchmarks/processor/vexriscv/vexriscv_small.v diff --git a/openfpga_flow/misc/1k_bram.xml b/openfpga_flow/misc/1k_bram.xml deleted file mode 100644 index 6b27133503..0000000000 --- a/openfpga_flow/misc/1k_bram.xml +++ /dev/null @@ -1,1177 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - io_top.outpad io_top.inpad - - - - - - - - - - - - io_right.outpad io_right.inpad - - - - - - - - - - - - io_bottom.outpad io_bottom.inpad - - - - - - - - - - - - io_left.outpad io_left.inpad - - - - - - - - - - - - - - - - - - - - - - - - - - clb.clk clb.reset - clb.sc_in clb.cin clb.O[7:0] clb.I[8:0] - clb.O[15:8] clb.I[17:9] - clb.sc_out clb.cout - - - - - - - - - - - - - - mult_18.a[0:5] mult_18.b[0:5] mult_18.out[0:11] - mult_18.a[6:11] mult_18.b[6:11] mult_18.out[12:23] - mult_18.a[12:17] mult_18.b[12:17] mult_18.out[24:35] - - - - - - - - - - - - - - - - - - - - - memory.clk - - memory.waddr[2:0] memory.raddr[3:0] memory.data_in[3:0] memory.wen memory.data_out[3:0] - memory.waddr[6:3] memory.raddr[6:4] memory.data_in[7:4] memory.ren memory.data_out[7:4] - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 - 1 - - - - 1 1 1 - 1 1 - - - - 1 1 1 1 1 - 1 1 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ${LUT3_DELAY} - ${LUT3_DELAY} - ${LUT3_DELAY} - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ${LUT4_DELAY} - ${LUT4_DELAY} - ${LUT4_DELAY} - ${LUT4_DELAY} - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga_flow/misc/1k_bram_openfpga.xml b/openfpga_flow/misc/1k_bram_openfpga.xml deleted file mode 100644 index 0a9a1d65ba..0000000000 --- a/openfpga_flow/misc/1k_bram_openfpga.xml +++ /dev/null @@ -1,352 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - - - - - 10e-12 5e-12 - - - 10e-12 5e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dff_flow.ys b/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dff_flow.ys deleted file mode 100644 index cd7ff02b54..0000000000 --- a/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dff_flow.ys +++ /dev/null @@ -1,102 +0,0 @@ -# Yosys synthesis script for ${TOP_MODULE} - -######################### -# Parse input files -######################### -# Read verilog files -${READ_VERILOG_FILE} -# Read technology library -read_verilog -lib -specify ${YOSYS_CELL_SIM_VERILOG} - -######################### -# Prepare for synthesis -######################### -# Identify top module from hierarchy -hierarchy -check -top ${TOP_MODULE} -# - Convert process blocks to AST -proc -# Flatten all the gates/primitives -flatten -# Identify tri-state buffers from 'z' signal in AST -# with follow-up optimizations to clean up AST -tribuf -logic -opt_expr -opt_clean -# demote inout ports to input or output port -# with follow-up optimizations to clean up AST -deminout -opt - -opt_expr -opt_clean -check -opt -wreduce -keepdc -peepopt -pmuxtree -opt_clean - -######################## -# Map multipliers -# Inspired from synth_xilinx.cc -######################### -# Avoid merging any registers into DSP, reserve memory port registers first -memory_dff - -######################### -# Run coarse synthesis -######################### -# Run a tech map with default library -techmap -alumacc -share -opt -fsm -# Run a quick follow-up optimization to sweep out unused nets/signals -opt -fast -# Optimize any memory cells by merging share-able ports and collecting all the ports belonging to memorcy cells -memory -nomap -opt_clean - -######################### -# Map logics to BRAMs -######################### -memory_bram -rules ${YOSYS_BRAM_MAP_RULES} -techmap -map ${YOSYS_BRAM_MAP_VERILOG} -opt -fast -mux_undef -undriven -fine -memory_map -opt -undriven -fine - -######################### -# Map pmuxes to muxes -######################### -techmap -map +/pmux2mux.v - -######################### -# Map flip-flops -######################### -techmap -map ${YOSYS_DFF_MAP_VERILOG} -opt_expr -mux_undef -simplemap -opt_expr -opt_merge -opt_rmdff -opt_clean -opt - -######################### -# Map LUTs -######################### -abc -lut ${LUT_SIZE} - -######################### -# Check and show statisitics -######################### -hierarchy -check -stat - -######################### -# Output netlists -######################### -opt_clean -purge -write_blif ${OUTPUT_BLIF} diff --git a/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_flow.ys b/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_flow.ys deleted file mode 100644 index 4111e11d80..0000000000 --- a/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_flow.ys +++ /dev/null @@ -1,116 +0,0 @@ -# Yosys synthesis script for ${TOP_MODULE} - -######################### -# Parse input files -######################### -# Read verilog files -${READ_VERILOG_FILE} -# Read technology library -read_verilog -lib -specify ${YOSYS_CELL_SIM_VERILOG} - -######################### -# Prepare for synthesis -######################### -# Identify top module from hierarchy -hierarchy -check -top ${TOP_MODULE} -# - Convert process blocks to AST -proc -# Flatten all the gates/primitives -flatten -# Identify tri-state buffers from 'z' signal in AST -# with follow-up optimizations to clean up AST -tribuf -logic -opt_expr -opt_clean -# demote inout ports to input or output port -# with follow-up optimizations to clean up AST -deminout -opt - -opt_expr -opt_clean -check -opt -wreduce -keepdc -peepopt -pmuxtree -opt_clean - -######################## -# Map multipliers -# Inspired from synth_xilinx.cc -######################### -# Avoid merging any registers into DSP, reserve memory port registers first -memory_dff -wreduce t:$mul -techmap -map +/mul2dsp.v -map ${YOSYS_DSP_MAP_VERILOG} ${YOSYS_DSP_MAP_PARAMETERS} -select a:mul2dsp -setattr -unset mul2dsp -opt_expr -fine -wreduce -select -clear -chtype -set $mul t:$__soft_mul# Extract arithmetic functions - -######################### -# Map $alu to carry chain -######################### -alumacc -techmap -map ${YOSYS_ADDER_MAP_VERILOG} - -######################### -# Run coarse synthesis -######################### -# Run a tech map with default library -techmap -alumacc -share -opt -fsm -# Run a quick follow-up optimization to sweep out unused nets/signals -opt -fast -# Optimize any memory cells by merging share-able ports and collecting all the ports belonging to memorcy cells -memory -nomap -opt_clean - -######################### -# Map logics to BRAMs -######################### -memory_bram -rules ${YOSYS_BRAM_MAP_RULES} -techmap -map ${YOSYS_BRAM_MAP_VERILOG} -opt -fast -mux_undef -undriven -fine -memory_map -opt -undriven -fine - -######################### -# Map muxes to pmuxes -######################### -techmap -map +/pmux2mux.v - -######################### -# Map flip-flops -######################### -techmap -map +/adff2dff.v -opt_expr -mux_undef -simplemap -opt_expr -opt_merge -opt_rmdff -opt_clean -opt - -######################### -# Map LUTs -######################### -abc -lut ${LUT_SIZE} - -######################### -# Check and show statisitics -######################### -hierarchy -check -stat - -######################### -# Output netlists -######################### -opt_clean -purge -write_blif ${OUTPUT_BLIF} diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_mem1K_dsp18_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_mem1K_dsp18_40nm_openfpga.xml deleted file mode 100644 index cd12856c52..0000000000 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_mem1K_dsp18_40nm_openfpga.xml +++ /dev/null @@ -1,253 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - - - - - 10e-12 5e-12 - - - 10e-12 5e-12 - - - - - - - - - - - - - 10e-12 5e-12 5e-12 - - - 10e-12 5e-12 5e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga_flow/openfpga_shell_scripts/generate_testbench_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/generate_testbench_example_script.openfpga index e65745efd3..0b5cfa2321 100644 --- a/openfpga_flow/openfpga_shell_scripts/generate_testbench_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/generate_testbench_example_script.openfpga @@ -10,7 +10,7 @@ read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} # Annotate the OpenFPGA architecture to VPR data base # to debug use --verbose options -link_openfpga_arch --sort_gsb_chan_node_in_edges +link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges # Check and correct any naming conflicts in the BLIF netlist check_netlist_naming_conflict --fix --report ./netlist_renaming.xml diff --git a/openfpga_flow/openfpga_shell_scripts/iwls_benchmark_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/iwls_benchmark_example_script.openfpga index dbac0b8831..49f1aac733 100644 --- a/openfpga_flow/openfpga_shell_scripts/iwls_benchmark_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/iwls_benchmark_example_script.openfpga @@ -2,7 +2,7 @@ # When the global clock is defined as a port of a tile, clock routing in VPR should be skipped # This is due to the Fc_in of clock port is set to 0 for global wiring # The constant net such as logic '0' and logic '1' must be routed because current architecture cannot produce them locally -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --route_chan_width ${VPR_ROUTE_CHAN_WIDTH} --constant_net_method route --disp on +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --route_chan_width ${VPR_ROUTE_CHAN_WIDTH} --constant_net_method route # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} diff --git a/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga index 347359d53e..e3e74a4091 100644 --- a/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga @@ -1,6 +1,6 @@ # Run VPR for the 'and' design #--write_rr_graph example_rr_graph.xml -vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ${OPENFPGA_CLOCK_MODELING} ${OPENFPGA_VPR_DEVICE_LAYOUT} +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route ${OPENFPGA_VPR_DEVICE_LAYOUT} # Read OpenFPGA architecture definition read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} diff --git a/openfpga_flow/regression_test_scripts/micro_benchmark_reg_test.sh b/openfpga_flow/regression_test_scripts/micro_benchmark_reg_test.sh index 57fae9f46f..93cd61c605 100755 --- a/openfpga_flow/regression_test_scripts/micro_benchmark_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/micro_benchmark_reg_test.sh @@ -7,13 +7,13 @@ PYTHON_EXEC=python3.8 # OpenFPGA Shell with VPR8 ############################################## echo -e "Micro benchmark regression tests"; -# run-task benchmark_sweep/counter --debug --show_thread_logs -# run-task benchmark_sweep/mac_units --debug --show_thread_logs +run-task benchmark_sweep/counter --debug --show_thread_logs +run-task benchmark_sweep/mac_units --debug --show_thread_logs -# # Verify MCNC big20 benchmark suite with ModelSim -# # Please make sure you have ModelSim installed in the environment -# # Otherwise, it will fail -# run-task benchmark_sweep/mcnc_big20 --debug --show_thread_logs +# Verify MCNC big20 benchmark suite with ModelSim +# Please make sure you have ModelSim installed in the environment +# Otherwise, it will fail +run-task benchmark_sweep/mcnc_big20 --debug --show_thread_logs #python3 openfpga_flow/scripts/run_modelsim.py mcnc_big20 --run_sim run-task benchmark_sweep/signal_gen --debug --show_thread_logs diff --git a/openfpga_flow/scripts/run_fpga_flow.py b/openfpga_flow/scripts/run_fpga_flow.py index f74514e3c0..a333ebb8f9 100644 --- a/openfpga_flow/scripts/run_fpga_flow.py +++ b/openfpga_flow/scripts/run_fpga_flow.py @@ -698,7 +698,7 @@ def run_rewrite_verilog(): # If there is a template script provided, replace parameters from configuration if not args.ys_rewrite_tmpl: script_cmd = [ - "read_blif -wideports %s" % args.top_module+".blif", + "read_blif %s" % args.top_module+".blif", "write_verilog %s" % args.top_module+"_output_verilog.v" ] command = [cad_tools["yosys_path"], "-p", "; ".join(script_cmd)] diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_bram/config/task.conf b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_bram/config/task.conf index 91c1237fc0..b47eea4111 100644 --- a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_bram/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_bram/config/task.conf @@ -21,9 +21,9 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_ openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml openfpga_vpr_device_layout=3x2 # Yosys script parameters -yosys_cell_sim_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/common/openfpga_dff_map.v +yosys_cell_sim_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/common/openfpga_brams_sim.v yosys_bram_map_rules=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/common/openfpga_brams.txt -yosys_bram_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/common/openfpga_dff_map.v +yosys_bram_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/common/openfpga_brams_map.v [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_mem1K_40nm.xml diff --git a/openfpga_flow/tasks/benchmark_sweep/signal_gen/config/task.conf b/openfpga_flow/tasks/benchmark_sweep/signal_gen/config/task.conf index 0b8fde8fa1..6661945a08 100644 --- a/openfpga_flow/tasks/benchmark_sweep/signal_gen/config/task.conf +++ b/openfpga_flow/tasks/benchmark_sweep/signal_gen/config/task.conf @@ -1,15 +1,22 @@ # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + # Configuration file for running experiments + # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + # timeout_each_job : FPGA Task script splits fpga flow into multiple jobs + # Each job execute fpga_flow script on combination of architecture & benchmark + # timeout_each_job is timeout for each job + # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + [GENERAL] run_engine=openfpga_shell power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml -power_analysis = false +power_analysis = true spice_output=false verilog_output=true timeout_each_job = 20*60 @@ -17,37 +24,28 @@ fpga_flow=yosys_vpr [OpenFPGA_SHELL] openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga -openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_openfpga.xml +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml openfpga_vpr_device_layout= -openfpga_clock_modeling=ideal openfpga_fast_configuration= -yosys_adder_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/common/arith_map.v - [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_40nm.xml +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/adder/adder_16/adder_16.v -# bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/clock_divider.v -# bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/pulse_generator.v -# bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/reset_generator.v +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/clock_divider.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/pulse_generator.v +bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/reset_generator.v [SYNTHESIS_PARAM] -bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_adder_flow.ys - -bench0_top = adder_16 +bench0_top = clock_divider bench0_chan_width = 300 -# bench0_top = clock_divider -# bench0_chan_width = 300 - -# bench1_top = pulse_generator -# bench1_chan_width = 300 +bench1_top = pulse_generator +bench1_chan_width = 300 -# bench2_top = reset_generator -# bench2_chan_width = 300 +bench2_top = reset_generator +bench2_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] -end_flow_with_test= +end_flow_with_test= \ No newline at end of file From 8f18a9ad9a0ae0ae7aa281af533ff7fba4bb294d Mon Sep 17 00:00:00 2001 From: Andrew Pond Date: Mon, 7 Feb 2022 12:19:31 -0700 Subject: [PATCH 22/22] added complete bram sizing files --- ..._tmpl_yosys_vpr_adder_bram_dsp_dff_flow.ys | 116 +++++++ .../ys_tmpl_yosys_vpr_bram_dsp_dff_flow.ys | 6 - ...ch_no_clk_modeling_example_script.openfpga | 2 +- .../common/bram_dsp_dff_cell_sim.v | 312 ++++++++++++++++++ ...am_1K_bram.txt => dpram_1K_bram_rules.txt} | 0 ...am_8K_bram.txt => dpram_8K_bram_rules.txt} | 0 .../benchmark_sweep/counter/config/task.conf | 2 +- .../processor/config/task.conf | 30 +- .../signal_gen/config/task.conf | 12 +- .../config/vtr_benchmark_golden_results.csv | 4 +- 10 files changed, 454 insertions(+), 30 deletions(-) create mode 100644 openfpga_flow/misc/ys_tmpl_yosys_vpr_adder_bram_dsp_dff_flow.ys create mode 100644 openfpga_flow/openfpga_yosys_techlib/common/bram_dsp_dff_cell_sim.v rename openfpga_flow/openfpga_yosys_techlib/common/{dpram_1K_bram.txt => dpram_1K_bram_rules.txt} (100%) rename openfpga_flow/openfpga_yosys_techlib/common/{dpram_8K_bram.txt => dpram_8K_bram_rules.txt} (100%) diff --git a/openfpga_flow/misc/ys_tmpl_yosys_vpr_adder_bram_dsp_dff_flow.ys b/openfpga_flow/misc/ys_tmpl_yosys_vpr_adder_bram_dsp_dff_flow.ys new file mode 100644 index 0000000000..9a5d5c9705 --- /dev/null +++ b/openfpga_flow/misc/ys_tmpl_yosys_vpr_adder_bram_dsp_dff_flow.ys @@ -0,0 +1,116 @@ +# Yosys synthesis script for ${TOP_MODULE} + +######################### +# Parse input files +######################### +# Read verilog files +${READ_VERILOG_FILE} +# Read technology library +read_verilog -lib -specify ${YOSYS_CELL_SIM_VERILOG} + +######################### +# Prepare for synthesis +######################### +# Identify top module from hierarchy +hierarchy -check -top ${TOP_MODULE} +# - Convert process blocks to AST +proc +# Flatten all the gates/primitives +flatten +# Identify tri-state buffers from 'z' signal in AST +# with follow-up optimizations to clean up AST +tribuf -logic +opt_expr +opt_clean +# demote inout ports to input or output port +# with follow-up optimizations to clean up AST +deminout +opt + +opt_expr +opt_clean +check +opt +wreduce -keepdc +peepopt +pmuxtree +opt_clean + +######################## +# Map multipliers +# Inspired from synth_xilinx.cc +######################### +# Avoid merging any registers into DSP, reserve memory port registers first +memory_dff +wreduce t:$mul +techmap -map +/mul2dsp.v -map ${YOSYS_DSP_MAP_VERILOG} ${YOSYS_DSP_MAP_PARAMETERS} +select a:mul2dsp +setattr -unset mul2dsp +opt_expr -fine +wreduce +select -clear +chtype -set $mul t:$__soft_mul# Extract arithmetic functions + +######################### +# Map $alu to carry chain +######################### +alumacc +techmap -map ${YOSYS_ADDER_MAP_VERILOG} + +######################### +# Run coarse synthesis +######################### +# Run a tech map with default library +techmap +share +opt +fsm +# Run a quick follow-up optimization to sweep out unused nets/signals +opt -fast +# Optimize any memory cells by merging share-able ports and collecting all the ports belonging to memorcy cells +memory -nomap +opt_clean + + +######################### +# Map logics to BRAMs +######################### +memory_bram -rules ${YOSYS_BRAM_MAP_RULES} +techmap -map ${YOSYS_BRAM_MAP_VERILOG} +opt -fast -mux_undef -undriven -fine +memory_map +opt -undriven -fine + +######################### +# Map muxes to pmuxes +######################### +techmap -map +/pmux2mux.v + +######################### +# Map flip-flops +######################### +techmap -map ${YOSYS_DFF_MAP_VERILOG} +opt_expr -mux_undef +simplemap +opt_expr +opt_merge +opt_rmdff +opt_clean +opt + +######################### +# Map LUTs +######################### +abc -lut ${LUT_SIZE} + +######################### +# Check and show statisitics +######################### +hierarchy -check +stat + +######################### +# Output netlists +######################### +opt_clean -purge +write_blif ${OUTPUT_BLIF} diff --git a/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_dff_flow.ys b/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_dff_flow.ys index 9a5d5c9705..6412ecf8c0 100644 --- a/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_dff_flow.ys +++ b/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_dff_flow.ys @@ -51,12 +51,6 @@ wreduce select -clear chtype -set $mul t:$__soft_mul# Extract arithmetic functions -######################### -# Map $alu to carry chain -######################### -alumacc -techmap -map ${YOSYS_ADDER_MAP_VERILOG} - ######################### # Run coarse synthesis ######################### diff --git a/openfpga_flow/openfpga_shell_scripts/write_full_testbench_no_clk_modeling_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/write_full_testbench_no_clk_modeling_example_script.openfpga index ffb290c128..506364e308 100644 --- a/openfpga_flow/openfpga_shell_scripts/write_full_testbench_no_clk_modeling_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/write_full_testbench_no_clk_modeling_example_script.openfpga @@ -10,7 +10,7 @@ read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} # Annotate the OpenFPGA architecture to VPR data base # to debug use --verbose options -link_openfpga_arch --activity_file and2_ace_out.act --sort_gsb_chan_node_in_edges +link_openfpga_arch --sort_gsb_chan_node_in_edges # Check and correct any naming conflicts in the BLIF netlist check_netlist_naming_conflict --fix --report ./netlist_renaming.xml diff --git a/openfpga_flow/openfpga_yosys_techlib/common/bram_dsp_dff_cell_sim.v b/openfpga_flow/openfpga_yosys_techlib/common/bram_dsp_dff_cell_sim.v new file mode 100644 index 0000000000..4783784137 --- /dev/null +++ b/openfpga_flow/openfpga_yosys_techlib/common/bram_dsp_dff_cell_sim.v @@ -0,0 +1,312 @@ +//----------------------------- +// Dual-port RAM 1024x8 bit (8Kbit) +// Core logic +//----------------------------- +module dpram_1024x8_core ( + input wclk, + input wen, + input [0:9] waddr, + input [0:7] data_in, + input rclk, + input ren, + input [0:9] raddr, + output [0:7] data_out ); + + reg [0:7] ram[0:1023]; + reg [0:7] internal; + + assign data_out = internal; + + always @(posedge wclk) begin + if(wen) begin + ram[waddr] <= data_in; + end + end + + always @(posedge rclk) begin + if(ren) begin + internal <= ram[raddr]; + end + end + +endmodule + +//----------------------------- +// Dual-port RAM 1024x8 bit (8Kbit) wrapper +// where the read clock and write clock +// are combined to a unified clock +//----------------------------- +module dpram_1024x8 ( + input clk, + input wen, + input ren, + input [0:9] waddr, + input [0:9] raddr, + input [0:7] data_in, + output [0:7] data_out ); + + dpram_1024x8_core memory_0 ( + .wclk (clk), + .wen (wen), + .waddr (waddr), + .data_in (data_in), + .rclk (clk), + .ren (ren), + .raddr (raddr), + .data_out (data_out) ); + +endmodule + + + + + +//----------------------------- +// Dual-port RAM 128x8 bit (1Kbit) +// Core logic +//----------------------------- +module dpram_128x8_core ( + input wclk, + input wen, + input [0:6] waddr, + input [0:7] data_in, + input rclk, + input ren, + input [0:6] raddr, + output [0:7] data_out ); + + reg [0:7] ram[0:127]; + reg [0:7] internal; + + assign data_out = internal; + + always @(posedge wclk) begin + if(wen) begin + ram[waddr] <= data_in; + end + end + + always @(posedge rclk) begin + if(ren) begin + internal <= ram[raddr]; + end + end + +endmodule + +//----------------------------- +// Dual-port RAM 128x8 bit (1Kbit) wrapper +// where the read clock and write clock +// are combined to a unified clock +//----------------------------- +module dpram_128x8 ( + input clk, + input wen, + input ren, + input [0:6] waddr, + input [0:6] raddr, + input [0:7] data_in, + output [0:7] data_out ); + + dpram_128x8_core memory_0 ( + .wclk (clk), + .wen (wen), + .waddr (waddr), + .data_in (data_in), + .rclk (clk), + .ren (ren), + .raddr (raddr), + .data_out (data_out) ); + +endmodule + + + +//----------------------------- +// 36-bit multiplier +//----------------------------- +module mult_36( + input [0:35] A, + input [0:35] B, + output [0:71] Y +); + +assign Y = A * B; + +endmodule + +//----------------------------- +// 18-bit multiplier +//----------------------------- +module mult_18( + input [0:17] A, + input [0:17] B, + output [0:35] Y +); + +assign Y = A * B; + +endmodule + + +//----------------------------- +// 8-bit multiplier +//----------------------------- +module mult_8( + input [0:7] A, + input [0:7] B, + output [0:15] Y +); + +assign Y = A * B; + +endmodule + + +//----------------------------- +// Native D-type flip-flop +//----------------------------- +(* abc9_flop, lib_whitebox *) +module dff( + output reg Q, + input D, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C) + Q <= D; + 1'b1: + always @(negedge C) + Q <= D; + endcase +endmodule + +//----------------------------- +// D-type flip-flop with active-high asynchronous reset +//----------------------------- +(* abc9_flop, lib_whitebox *) +module dffr( + output reg Q, + input D, + input R, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C or posedge R) + if (R == 1'b1) + Q <= 1'b0; + else + Q <= D; + 1'b1: + always @(negedge C or posedge R) + if (R == 1'b1) + Q <= 1'b0; + else + Q <= D; + endcase +endmodule + +//----------------------------- +// D-type flip-flop with active-high asynchronous set +//----------------------------- +(* abc9_flop, lib_whitebox *) +module dffs( + output reg Q, + input D, + input S, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C or posedge S) + if (S == 1'b1) + Q <= 1'b1; + else + Q <= D; + 1'b1: + always @(negedge C or posedge S) + if (S == 1'b1) + Q <= 1'b1; + else + Q <= D; + endcase +endmodule + +//----------------------------- +// D-type flip-flop with active-low asynchronous reset +//----------------------------- +(* abc9_flop, lib_whitebox *) +module dffrn( + output reg Q, + input D, + input RN, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C or negedge RN) + if (RN == 1'b0) + Q <= 1'b0; + else + Q <= D; + 1'b1: + always @(negedge C or negedge RN) + if (RN == 1'b0) + Q <= 1'b0; + else + Q <= D; + endcase +endmodule + +//----------------------------- +// D-type flip-flop with active-low asynchronous set +//----------------------------- +(* abc9_flop, lib_whitebox *) +module dffsn( + output reg Q, + input D, + input SN, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C or negedge SN) + if (SN == 1'b0) + Q <= 1'b1; + else + Q <= D; + 1'b1: + always @(negedge C or negedge SN) + if (SN == 1'b0) + Q <= 1'b1; + else + Q <= D; + endcase +endmodule diff --git a/openfpga_flow/openfpga_yosys_techlib/common/dpram_1K_bram.txt b/openfpga_flow/openfpga_yosys_techlib/common/dpram_1K_bram_rules.txt similarity index 100% rename from openfpga_flow/openfpga_yosys_techlib/common/dpram_1K_bram.txt rename to openfpga_flow/openfpga_yosys_techlib/common/dpram_1K_bram_rules.txt diff --git a/openfpga_flow/openfpga_yosys_techlib/common/dpram_8K_bram.txt b/openfpga_flow/openfpga_yosys_techlib/common/dpram_8K_bram_rules.txt similarity index 100% rename from openfpga_flow/openfpga_yosys_techlib/common/dpram_8K_bram.txt rename to openfpga_flow/openfpga_yosys_techlib/common/dpram_8K_bram_rules.txt diff --git a/openfpga_flow/tasks/benchmark_sweep/counter/config/task.conf b/openfpga_flow/tasks/benchmark_sweep/counter/config/task.conf index 6fefdb16d8..a0d8a07b4e 100644 --- a/openfpga_flow/tasks/benchmark_sweep/counter/config/task.conf +++ b/openfpga_flow/tasks/benchmark_sweep/counter/config/task.conf @@ -40,7 +40,7 @@ bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/c bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/counters/counter_128bit_async_resetb/counter.v [SYNTHESIS_PARAM] -bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_dff_flow.ys +bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys #bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys bench0_top = counter diff --git a/openfpga_flow/tasks/benchmark_sweep/processor/config/task.conf b/openfpga_flow/tasks/benchmark_sweep/processor/config/task.conf index ea252027f9..4f429b8d74 100644 --- a/openfpga_flow/tasks/benchmark_sweep/processor/config/task.conf +++ b/openfpga_flow/tasks/benchmark_sweep/processor/config/task.conf @@ -9,31 +9,39 @@ [GENERAL] run_engine=openfpga_shell power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml -power_analysis = true +power_analysis = false spice_output=false verilog_output=true timeout_each_job = 20*60 fpga_flow=yosys_vpr +arch_variable_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_timing_annotation/design_variables.yml [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/generate_bitstream_global_tile_multiclock_example_script.openfpga -openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_openfpga.xml -openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_no_clk_modeling_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N8_adder_chain_mem1K_130nm_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml openfpga_vpr_device_layout=auto openfpga_fast_configuration= +yosys_cell_sim_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm/k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm_cell_sim.v +yosys_bram_map_rules=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/common/dpram_1K_bram.txt +yosys_bram_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/common/dpram_1K_bram_map.v +yosys_dsp_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/common/dsp_map.v +yosys_dsp_map_parameters=-D DSP_A_MAXWIDTH=8 -D DSP_B_MAXWIDTH=8 -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_NAME=mult_8x8 +yosys_dff_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm/k4_frac_N8_tileable_adder_chain_dpram1K_dsp18_fracff_skywater130nm_dff_map.v + [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_40nm.xml +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N8_tileable_adder_chain_mem1K_130nm.xml [BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/processor/picorv32/picorv32.v -bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/processor/vexriscv/vexriscv_small.v +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/signal_gen/clock_divider.v [SYNTHESIS_PARAM] -bench0_top = picorv32 +bench0_top = clock_divider bench0_chan_width = 300 -bench1_top = VexRiscv -bench1_chan_width = 300 + +bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_dff_flow.ys [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] -end_flow_with_test= +#end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/benchmark_sweep/signal_gen/config/task.conf b/openfpga_flow/tasks/benchmark_sweep/signal_gen/config/task.conf index 6661945a08..a6825d8628 100644 --- a/openfpga_flow/tasks/benchmark_sweep/signal_gen/config/task.conf +++ b/openfpga_flow/tasks/benchmark_sweep/signal_gen/config/task.conf @@ -1,18 +1,11 @@ # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = - # Configuration file for running experiments - # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = - # timeout_each_job : FPGA Task script splits fpga flow into multiple jobs - # Each job execute fpga_flow script on combination of architecture & benchmark - # timeout_each_job is timeout for each job - # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = - [GENERAL] run_engine=openfpga_shell power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml @@ -23,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml openfpga_vpr_device_layout= @@ -48,4 +41,5 @@ bench2_top = reset_generator bench2_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] -end_flow_with_test= \ No newline at end of file +#end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/benchmark_sweep/vtr_benchmarks/config/vtr_benchmark_golden_results.csv b/openfpga_flow/tasks/benchmark_sweep/vtr_benchmarks/config/vtr_benchmark_golden_results.csv index af8842eed9..3b74e5d7f3 100644 --- a/openfpga_flow/tasks/benchmark_sweep/vtr_benchmarks/config/vtr_benchmark_golden_results.csv +++ b/openfpga_flow/tasks/benchmark_sweep/vtr_benchmarks/config/vtr_benchmark_golden_results.csv @@ -10,7 +10,7 @@ name,mult_blocks,memory_blocks 00_bgm_MIN_ROUTE_CHAN_WIDTH,11,0 00_RLE_BlobMerging_MIN_ROUTE_CHAN_WIDTH,0,0 00_paj_boundtop_hierarchy_no_mem_MIN_ROUTE_CHAN_WIDTH,0,1 -00_memset_MIN_ROUTE_CHAN_WIDTH,0,1 +00_memset_MIN_ROUTE_CHAN_WIDTH,0,0 00_diffeq_paj_convert_MIN_ROUTE_CHAN_WIDTH,5,0 00_diffeq_f_systemC_MIN_ROUTE_CHAN_WIDTH,5,0 00_LU8PEEng_MIN_ROUTE_CHAN_WIDTH,8,9 @@ -20,7 +20,7 @@ name,mult_blocks,memory_blocks 00_mkPktMerge_MIN_ROUTE_CHAN_WIDTH,0,3 00_mkSMAdapter4B_MIN_ROUTE_CHAN_WIDTH,0,3 00_or1200_flat_MIN_ROUTE_CHAN_WIDTH,1,2 -00_paj_raygentop_hierarchy_no_mem_MIN_ROUTE_CHAN_WIDTH,18,1 +00_paj_raygentop_hierarchy_no_mem_MIN_ROUTE_CHAN_WIDTH,18,0 00_sha1_MIN_ROUTE_CHAN_WIDTH,0,0 00_sv_chip0_hierarchy_no_mem_MIN_ROUTE_CHAN_WIDTH,0,0 00_sv_chip1_hierarchy_no_mem_MIN_ROUTE_CHAN_WIDTH,152,0