diff --git a/.nojekyll b/.nojekyll new file mode 100644 index 0000000..e69de29 diff --git a/LoongArch-ELF-ABI-CN.html b/LoongArch-ELF-ABI-CN.html new file mode 100644 index 0000000..3b96a39 --- /dev/null +++ b/LoongArch-ELF-ABI-CN.html @@ -0,0 +1,1328 @@ + + + + + + + + +龙芯架构 ELF psABI 规范 + + + + +
+
+

寄存器使用约定

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 1. 通用寄存器使用约定
名称别名用途在调用中是否保留

$r0

$zero

常数 0

（常数）

$r1

$ra

返回地址

否

$r2

$tp

线程指针

（不可分配）

$r3

$sp

栈指针

是

$r4 - $r5

$a0 - $a1

传参寄存器、返回值寄存器

否

$r6 - $r11

$a2 - $a7

传参寄存器

否

$r12 - $r20

$t0 - $t8

临时寄存器

否

$r21

保留

（不可分配）

$r22

$fp / $s9

栈帧指针 / 静态寄存器

是

$r23 - $r31

$s0 - $s8

静态寄存器

是

+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 2. 浮点寄存器使用约定
名称别名用途在调用中是否保留

$f0 - $f1

$fa0 - $fa1

传参寄存器、返回值寄存器

否

$f2 - $f7

$fa2 - $fa7

传参寄存器

否

$f8 - $f23

$ft0 - $ft15

临时寄存器

否

$f24 - $f31

$fs0 - $fs7

静态寄存器

是

+
+

临时寄存器也被称为调用者保存寄存器。 +静态寄存器也被称为被调用者保存寄存器。

+
+
+

返回值寄存器的别名写法

+
+

在一些早期的 LoongArch 汇编代码中，您可能会见到形如 $v0 $v1 $fv0 $fv1 +的寄存器写法：这些名字分别等价于 $a0 $a1 $fa0 $fa1 。 +这些别名最初是仿照 MIPS 的分立传参、返回值寄存器写法而设计的。 +由于 LoongArch 实际并没有专门的返回值寄存器，这种写法反而会造成误解， +因而不建议使用。

+
+
+

由于各下游项目的实现细节差异， +给一个寄存器赋予多个 ABI 名字并不一定是简单的事情。 +新写作的处理 LoongArch 汇编语言的程序不应当实现该套别名。 +可移植的 LoongArch 汇编代码不应当使用该套别名。

+
+
+ + + + + +
+
Note
+		 +
+

对于龙芯公司提供的工具链组件，迁移流程为：

+
+
+

设本规范生效时相应组件的当前版本为 N，

+
+
+
    +
  1. +

    在版本 N 及其稳定分支（补丁版本）保留支持，

    +
    2. +
  2. +

    在版本 N+1 对该用法进行警告，

    +
    3. +
  3. +

    在版本 N+2 删除该用法的支持。

    +
    4. +
+
+
+

对于这些组件相应的上游项目，已进入上游的那部分如果存在对该用法的支持，则按上述流程进行，“版本 N”理解为第一次加入 LoongArch 支持的那个正式发布版本。 +对于暂未进入上游，且不与预期必须使用该用法的其他组件交互的组件，上游版本将自始不支持该用法。

+
+
+
+
+
+
+
+

C 语言数据类型规格

+
+ + +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 3. LP64 数据模型 （对应基础 ABI 类型：lp64d lp64f lp64s）
标量类型大小（字节）对齐（字节）

bool / _Bool

1

1

unsigned char / char

1

1

unsigned short / short

2

2

unsigned int / int

4

4

unsigned long / long

8

8

unsigned long long / long long

8

8

指针类型

8

8

float

4

4

double

8

8

long double

16

16

+ + +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 4. ILP32 数据模型 （对应基础 ABI 类型：ilp32d ilp32f ilp32s）
标量类型大小（字节）对齐（字节）

bool / _Bool

1

1

unsigned char / char

1

1

unsigned short / short

2

2

unsigned int / int

4

4

unsigned long / long

4

4

unsigned long long / long long

8

8

指针类型

4

4

float

4

4

double

8

8

long double

16

16

+
+

对于任何基础 ABI 类型，char 默认是有符号类型。

+
+
+
+
+

ELF 目标文件

+
+
+

本节内容中关于 ELF 目标文件的通用格式定义 +均参考 最新版本的 SysV gABI。

+
+
+

EI_CLASS: ELF 文件格式

+ + +++++ + + + + + + + + + + + + + + + + + + + +
Table 5. ELF 文件格式
EI_CLASS枚举值含义

ELFCLASS32

1

32 位 ELF 格式 (ELF32)

ELFCLASS64

2

64 位 ELF 格式 (ELF64)

+
+
+

e_machine: 体系结构 ID

+
+

LoongArch (258)

+
+
+
+

e_flags: ABI 类型和版本 ID

+ + ++++++ + + + + + + + + + + + + + + + + +
Table 6. e_flags 中的 ABI 相关位
[31:8] 位[7:6] 位[5:3] 位[2:0] 位

（保留）

ABI 版本

ABI 扩展特性

基础 ABI 修饰符

+
+

EI_CLASS 和 e_flags[7:0] 完整确定了 ELF 目标文件使用的 ABI 类型。

+
+
+

其中，基础 ABI 类型由 EI_CLASS 和 e_flags[2:0] 共同标记， +前者唯一确定了 C 语言整数和指针类型的表示（数据模型）和传参方式， +后者则在此基础上表示其他基础 ABI 性质，如浮点类型传参方式，称为 基础 ABI 修饰符。

+
+
+

因此，龙芯架构的 ELF64 / ELF32 目标文件分别仅用于编码 lp64* / ilp32* ABI 的程序。

+
+
+

0x0 0x4 0x5 0x6 0x7 为 e_flags[2:0] 的保留值。

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 7. 基础 ABI 类型
基础 ABI 名称EI_CLASS基础 ABI 修饰符 (e_flags[2:0])含义

lp64s

ELFCLASS64

0x1

使用 64 位通用寄存器和栈传参， +数据模型为 LP64（long 和指针类型宽度为 64 位，int 为 32 位）

lp64f

ELFCLASS64

0x2

使用 64 位通用寄存器，32 位浮点寄存器和栈传参， +数据模型为 LP64（long 和指针类型宽度为 64 位，int 为 32 位）

lp64d

ELFCLASS64

0x3

使用 64 位通用寄存器，64 位浮点寄存器和栈传参， +数据模型为 LP64（long 和指针类型宽度为 64 位，int 为 32 位）

ilp32s

ELFCLASS32

0x1

使用 32 位通用寄存器和栈传参， +数据模型为 ILP32（int，long 和指针类型宽度为 32 位）

ilp32f

ELFCLASS32

0x2

使用 32 位通用寄存器，32 位浮点寄存器和栈传参， +数据模型为 ILP32（int，long 和指针类型宽度为 32 位）

ilp32d

ELFCLASS32

0x3

使用 32 位通用寄存器，64 位浮点寄存器和栈传参， +数据模型为 ILP32（int，long 和指针类型宽度为 32 位）

+
+

e_flags[5:3] 标记了 ABI 扩展特性。

+
+ + +++++ + + + + + + + + + + + + + + + + + + + +
Table 8. ABI 扩展特性类型
ABI 扩展特性名称e_flags[5:3]含义

base

0x0

默认，无扩展特性

0x1 - 0x7

保留值

+
+

e_flags[7:6] 标记了 ELF 目标文件使用的 ABI 版本。

+
+ + +++++ + + + + + + + + + + + + + + + + + + + + + + + + +
Table 9. ABI 版本
ABI 版本枚举值描述

v0

0x0

支持具有栈操作语义的重定位类型

v1

0x1

支持指令立即数域语义的重定位类型，可以不兼容v0单独实现。

0x2 0x3

保留值

+
+
+
+
+

重定位类型

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 10. ELF 重定位类型
枚举值名称描述语义

0

R_LARCH_NONE

1

R_LARCH_32

动态符号地址解析

*(int32_t *) PC = RtAddr + A

2

R_LARCH_64

动态符号地址解析

*(int64_t *) PC = RtAddr + A

3

R_LARCH_RELATIVE

模块动态加载地址修正

*(void **) PC = B + A

4

R_LARCH_COPY

可执行映像数据动态填充

memcpy (PC, RtAddr, sizeof (sym))

5

R_LARCH_JUMP_SLOT

PLT 跳转支持

由具体实现定义

6

R_LARCH_TLS_DTPMOD32

TLS-GD 动态重定位支持

*(int32_t *) PC = ID of module defining sym

7

R_LARCH_TLS_DTPMOD64

TLS-GD 动态重定位支持

*(int64_t *) PC = ID of module defining sym

8

R_LARCH_TLS_DTPREL32

TLS-GD 动态重定位支持

*(int32_t *) PC = DTV-relative offset for sym

9

R_LARCH_TLS_DTPREL64

TLS-GD 动态重定位支持

*(int64_t *) PC = DTV-relative offset for sym

10

R_LARCH_TLS_TPREL32

TLS-IE 动态重定位支持

*(int32_t *) PC = T

11

R_LARCH_TLS_TPREL64

TLS-IE 动态重定位支持

*(int64_t *) PC = T

12

R_LARCH_IRELATIVE

本地间接跳转解析

*(void **) PC = (((void *)(*)()) (B + A)) ()

…​ 动态链接器保留项

20

R_LARCH_MARK_LA

标记 la.abs 宏指令

静态填充符号绝对地址

21

R_LARCH_MARK_PCREL

标记外部标签跳转

静态填充符号地址偏移量

22

R_LARCH_SOP_PUSH_PCREL

将符号相对地址压栈

push (S - PC + A)

23

R_LARCH_SOP_PUSH_ABSOLUTE

将常数或绝对地址压栈

push (S + A)

24

R_LARCH_SOP_PUSH_DUP

复制栈顶元素

opr1 = pop (), push (opr1), push (opr1)

25

R_LARCH_SOP_PUSH_GPREL

将符号的 GOT 表项偏移量压栈

push (G)

26

R_LARCH_SOP_PUSH_TLS_TPREL

将 TLS-LE 偏移量压栈

push (T)

27

R_LARCH_SOP_PUSH_TLS_GOT

将 TLS-IE 偏移量压栈

push (IE)

28

R_LARCH_SOP_PUSH_TLS_GD

将 TLS-GD 偏移量压栈

push (GD)

29

R_LARCH_SOP_PUSH_PLT_PCREL

将符号 PLT stub 的地址偏移量压栈

push (PLT - PC)

30

R_LARCH_SOP_ASSERT

断言栈顶元素为真

assert (pop ())

31

R_LARCH_SOP_NOT

栈顶运算

push (!pop ())

32

R_LARCH_SOP_SUB

栈顶运算

opr2 = pop (), opr1 = pop (), push (opr1 - opr2)

33

R_LARCH_SOP_SL

栈顶运算

opr2 = pop (), opr1 = pop (), push (opr1 << opr2)

34

R_LARCH_SOP_SR

栈顶运算

opr2 = pop (), opr1 = pop (), push (opr1 >> opr2)

35

R_LARCH_SOP_ADD

栈顶运算

opr2 = pop (), opr1 = pop (), push (opr1 + opr2)

36

R_LARCH_SOP_AND

栈顶运算

opr2 = pop (), opr1 = pop (), push (opr1 & opr2)

37

R_LARCH_SOP_IF_ELSE

栈顶运算

opr3 = pop (), opr2 = pop (), opr1 = pop (), push (opr1 ? opr2 : opr3)

38

R_LARCH_SOP_POP_32_S_10_5

指令立即数重定位

opr1 = pop (), (*(uint32_t *) PC) [14 ... 10] = opr1 [4 ... 0]

+

带 5 位有符号数溢出检测功能

39

R_LARCH_SOP_POP_32_U_10_12

指令立即数重定位

opr1 = pop (), (*(uint32_t *) PC) [21 ... 10] = opr1 [11 ... 0]

+

带 12 位无符号数溢出检测功能

40

R_LARCH_SOP_POP_32_S_10_12

指令立即数重定位

opr1 = pop (), (*(uint32_t *) PC) [21 ... 10] = opr1 [11 ... 0]

+

带 12 位有符号数溢出检测功能

41

R_LARCH_SOP_POP_32_S_10_16

指令立即数重定位

opr1 = pop (), (*(uint32_t *) PC) [25 ... 10] = opr1 [15 ... 0]

+

带 16 位有符号数溢出检测功能

42

R_LARCH_SOP_POP_32_S_10_16_S2

指令立即数重定位

opr1 = pop (), (*(uint32_t *) PC) [25 ... 10] = opr1 [17 ... 2]

+

带 18 位有符号数溢出和4字节对齐检测功能

43

R_LARCH_SOP_POP_32_S_5_20

指令立即数重定位

opr1 = pop (), (*(uint32_t *) PC) [24 ... 5] = opr1 [19 ... 0]

+

带 20 位有符号数溢出检测功能

44

R_LARCH_SOP_POP_32_S_0_5_10_16_S2

指令立即数重定位

opr1 = pop (), (*(uint32_t *) PC) [4 ... 0] = opr1 [22 ... 18],

+

(*(uint32_t *) PC) [25 ... 10] = opr1 [17 ... 2]

+

带 23 位有符号数溢出和4字节对齐检测功能

45

R_LARCH_SOP_POP_32_S_0_10_10_16_S2

指令立即数重定位

opr1 = pop (), (*(uint32_t *) PC) [9 ... 0] = opr1 [27 ... 18],

+

(*(uint32_t *) PC) [25 ... 10] = opr1 [17 ... 2]

+

带 28 位有符号数溢出和4字节对齐检测功能

46

R_LARCH_SOP_POP_32_U

指令修正

(*(uint32_t *) PC) = pop ()

+

带 32 位无符号数溢出检测功能

47

R_LARCH_ADD8

8 位原地加法

*(int8_t *) PC += S + A

48

R_LARCH_ADD16

16 位原地加法

*(int16_t *) PC += S + A

49

R_LARCH_ADD24

24 位原地加法

*(int24_t *) PC += S + A

50

R_LARCH_ADD32

32 位原地加法

*(int32_t *) PC += S + A

51

R_LARCH_ADD64

64 位原地加法

*(int64_t *) PC += S + A

52

R_LARCH_SUB8

8 位原地减法

*(int8_t *) PC -= S + A

53

R_LARCH_SUB16

16 位原地减法

*(int16_t *) PC -= S + A

54

R_LARCH_SUB24

24 位原地减法

*(int24_t *) PC -= S + A

55

R_LARCH_SUB32

32 位原地减法

*(int32_t *) PC -= S + A

56

R_LARCH_SUB64

64 位原地减法

*(int64_t *) PC -= S + A

57

R_LARCH_GNU_VTINHERIT

GNU C++ vtable 支持

58

R_LARCH_GNU_VTENTRY

GNU C++ vtable 支持

…​ 保留项

64

R_LARCH_B16

18 位相对 PC 跳转

(*(uint32_t *) PC) [25 ... 10] = (S+A-PC) [17 ... 2]

+

带 18 位有符号数溢出和4字节对齐检测功能

65

R_LARCH_B21

23 位相对 PC 跳转

(*(uint32_t *) PC) [4 ... 0] = (S+A-PC) [22 ... 18],

+

(*(uint32_t *) PC) [25 ... 10] = (S+A-PC) [17 ... 2]

+

带 23 位有符号数溢出和4字节对齐检测功能

66

R_LARCH_B26

28 位相对 PC 跳转

(*(uint32_t *) PC) [9 ... 0] = (S+A-PC) [27 ... 18],

+

(*(uint32_t *) PC) [25 ... 10] = (S+A-PC) [17 ... 2]

+

带 28 位有符号数溢出和4字节对齐检测功能

67

R_LARCH_ABS_HI20

32/64 位绝对地址的 [31 …​ 12] 位

(*(uint32_t *) PC) [24 ... 5] = (S+A) [31 ... 12]

68

R_LARCH_ABS_LO12

32/64 位绝对地址的 [11 …​ 0] 位

(*(uint32_t *) PC) [21 ... 10] = (S+A) [11 ... 0]

69

R_LARCH_ABS64_LO20

64 位绝对地址 [51 …​ 32] 位

(*(uint32_t *) PC) [24 ... 5] = (S+A) [51 ... 32]

70

R_LARCH_ABS64_HI12

64 位绝对地址 [63 …​ 52] 位

(*(uint32_t *) PC) [21 ... 10] = (S+A) [63 ... 52]

71

R_LARCH_PCALA_HI20

相对 PC 偏移 32/64 位的 [31 …​ 12] 位

(*(uint32_t *) PC) [24 ... 5] = (((S+A) & ~0xfff) - (PC & ~0xfff)) [31 ... 12]

+

注意：所有相对 PC 偏移计算都不包含低12位。

72

R_LARCH_PCALA_LO12

32/64 位地址的 [11 …​ 0] 位

(*(uint32_t *) PC) [21 ... 10] = (S+A) [11 ... 0]

73

R_LARCH_PCALA64_LO20

相对 PC 偏移 64 位的 [51 …​ 32] 位

(*(uint32_t *) PC) [24 ... 5] = (S+A - (PC & ~0xffffffff)) [51 ... 32]

74

R_LARCH_PCALA64_HI12

相对 PC 偏移 64 位的 [63 …​ 52] 位

(*(uint32_t *) PC) [21 ... 10] = (S+A - (PC & ~0xffffffff)) [63 ... 52]

75

R_LARCH_GOT_PC_HI20

GOT 表项相对 PC 偏移 32/64 位的 [31 …​ 12] 位

(*(uint32_t *) PC) [24 ... 5] = (((GP+G) & ~0xfff) - (PC & ~0xfff)) [31 ... 12]

76

R_LARCH_GOT_PC_LO12

GOT 表项 32/64 位地址的 [11 …​ 0] 位

(*(uint32_t *) PC) [21 ... 10] = (GP+G) [11 ... 0]

77

R_LARCH_GOT64_PC_LO20

GOT 表项相对 PC 偏移 64 位的 [51 …​ 32] 位

(*(uint32_t *) PC) [24 ... 5] = (GP+G - (PC & ~0xffffffff)) [51 ... 32]

78

R_LARCH_GOT64_PC_HI12

GOT 表项相对 PC 偏移 64 位的 [63 …​ 52] 位

(*(uint32_t *) PC) [21 ... 10] = (GP+G - (PC & ~0xffffffff)) [63 ... 52]

79

R_LARCH_GOT_HI20

GOT 表项 32/64 位绝对地址的 [31 …​ 12] 位

(*(uint32_t *) PC) [24 ... 5] = (GP+G) [31 ... 12]

80

R_LARCH_GOT_LO12

GOT 表项 32/64 位绝对地址的 [11 …​ 0] 位

(*(uint32_t *) PC) [21 ... 10] = (GP+G) [11 ... 0]

81

R_LARCH_GOT64_LO20

GOT 表项 64 位绝对地址的 [51 …​ 32] 位

(*(uint32_t *) PC) [24 ... 5] = (GP+G) [51 ... 32]

82

R_LARCH_GOT64_HI12

GOT 表项 64 位绝对地址的 [63 …​ 52] 位

(*(uint32_t *) PC) [21 ... 10] = (GP+G) [63 ... 52]

83

R_LARCH_TLS_LE_HI20

TLS LE 符号相对 TP 寄存器偏移 32/64 位的 [31 …​ 12] 位

(*(uint32_t *) PC) [24 ... 5] = T [31 ... 12]

84

R_LARCH_TLS_LE_LO12

TLS LE 符号相对 TP 寄存器偏移 32/64 位的 [11 …​ 0] 位

(*(uint32_t *) PC) [21 ... 10] = T [11 ... 0]

85

R_LARCH_TLS_LE64_LO20

TLS LE 符号相对 TP 寄存器偏移 64 位的 [51 …​ 32] 位

(*(uint32_t *) PC) [24 ... 5] = T [51 ... 32]

86

R_LARCH_TLS_LE64_HI12

TLS LE 符号相对 TP 寄存器偏移 64 位的 [63 …​ 52] 位

(*(uint32_t *) PC) [21 ... 10] = T [63 ... 52]

87

R_LARCH_TLS_IE_PC_HI20

TLS IE 符号 GOT 表项相对 PC 偏移 32/64 位的 [31 …​ 12] 位

(*(uint32_t *) PC) [24 ... 5] = (((GP+IE) & ~0xfff) - (PC & ~0xfff)) [31 ... 12]

88

R_LARCH_TLS_IE_PC_LO12

TLS IE 符号 GOT 表项 32/64 位地址的 [11 …​ 0] 位

(*(uint32_t *) PC) [21 ... 10] = (GP+IE) [11 ... 0]

89

R_LARCH_TLS_IE64_PC_LO20

TLS IE 符号 GOT 表项相对 PC 偏移 64 位的 [51 …​ 32] 位

(*(uint32_t *) PC) [24 ... 5] = (GP+IE - (PC & ~0xffffffff)) [51 ... 32]

90

R_LARCH_TLS_IE64_PC_HI12

TLS IE 符号 GOT 表项相对 PC 偏移 64 位的 [63 …​ 52] 位

(*(uint32_t *) PC) [21 ... 10] = (GP+IE - (PC & ~0xffffffff)) [63 ... 52]

91

R_LARCH_TLS_IE_HI20

TLS IE 符号 GOT 表项 32/64 位绝对地址的 [31 …​ 12] 位

(*(uint32_t *) PC) [24 ... 5] = (GP+IE) [31 ... 12]

92

R_LARCH_TLS_IE_LO12

TLS IE 符号 GOT 表项 32/64 位绝对地址的 [11 …​ 0] 位

(*(uint32_t *) PC) [21 ... 10] = (GP+IE) [11 ... 0]

93

R_LARCH_TLS_IE64_LO20

TLS IE 符号 GOT 表项 64 位绝对地址的 [51 …​ 32] 位

(*(uint32_t *) PC) [24 ... 5] = (GP+IE) [51 ... 32]

94

R_LARCH_TLS_IE64_HI12

TLS IE 符号 GOT 表项 64 位绝对地址的 [63 …​ 52] 位

(*(uint32_t *) PC) [21 ... 10] = (GP+IE) [63 ... 52]

95

R_LARCH_TLS_LD_PC_HI20

TLS LD 符号 GOT 表项相对 PC 偏移 32/64 位的 [31 …​ 12] 位

(*(uint32_t *) PC) [24 ... 5] = (((GP+GD) & ~0xfff) - (PC & ~0xfff)) [31 ... 12]

96

R_LARCH_TLS_LD_HI20

TLS LD 符号 GOT 表项 32/64 位绝对地址的 [31 …​ 12] 位

(*(uint32_t *) PC) [24 ... 5] = (GP+IE) [31 ... 12]

97

R_LARCH_TLS_GD_PC_HI20

TLS GD 符号 GOT 表项相对 PC 偏移 32/64 位的 [31 …​ 12] 位

(*(uint32_t *) PC) [24 ... 5] = (((GP+GD) & ~0xfff) - (PC & ~0xfff)) [31 ... 12]

98

R_LARCH_TLS_GD_HI20

TLS GD 符号 GOT 表项 32/64 位绝对地址的 [31 …​ 12] 位

(*(uint32_t *) PC) [24 ... 5] = (GP+IE) [31 ... 12]

99

R_LARCH_32_PCREL

32 位相对 PC 偏移

(*(uint32_t *) PC) = (S+A-PC) [31 ... 0]

100

R_LARCH_RELAX

在相同的地址和其它重定位成对使用，标识指令可能被修改或删除(relaxed)。

+
+
+
+

动态链接器路径

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 11. 标准动态链接器路径列表：
基础 ABI 类型ABI 扩展特性操作系统 / C 库ELF interpreter 路径

lp64d

base

Linux, Glibc

/lib64/ld-linux-loongarch-lp64d.so.1

lp64f

base

Linux, Glibc

/lib64/ld-linux-loongarch-lp64f.so.1

lp64s

base

Linux, Glibc

/lib64/ld-linux-loongarch-lp64s.so.1

ilp32d

base

Linux, Glibc

/lib32/ld-linux-loongarch-ilp32d.so.1

ilp32f

base

Linux, Glibc

/lib32/ld-linux-loongarch-ilp32f.so.1

ilp32s

base

Linux, Glibc

/lib32/ld-linux-loongarch-ilp32s.so.1

+
+
+
+

附录：版本修订历史

+
+
+
    +
  • +

    v1.00

    +
    +
      +
    • +

      新增寄存器使用惯例、数据类型惯例和重定位类型列表；

      +
      • +
    +
    +
    • +
  • +

    v2.00

    +
    +
      +
    • +

      新增 ILP32 数据模型说明；

      +
      • +
    • +

      新增返回值寄存器别名写法说明；

      +
      • +
    • +

      新增指令立即数域语义的重定位类型；

      +
      • +
    • +

      新增 ABI 规范修订时，工具链实现的指导迁移流程；

      +
      • +
    • +

      增加 SysV gABI 参考链接；

      +
      • +
    • +

      调整 asciidoc 代码风格；

      +
      • +
    +
    +
    • +
  • +

    v2.01

    +
    +
      +
    • +

      调整关于 ABI 类型在 ELF 文件中编码方式的说明；

      +
      • +
    • +

      各表格统一添加表头；

      +
      • +
    +
    +
    • +
+
+
+
+
+ + +
+ + Creative Commons License + +
+ This work is licensed under a + Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License. +
+ + + + + + + + + \ No newline at end of file diff --git a/LoongArch-ELF-ABI-CN.pdf b/LoongArch-ELF-ABI-CN.pdf new file mode 100644 index 0000000..39efc12 Binary files /dev/null and b/LoongArch-ELF-ABI-CN.pdf differ diff --git a/LoongArch-ELF-ABI-EN.html b/LoongArch-ELF-ABI-EN.html new file mode 100644 index 0000000..9c4494e --- /dev/null +++ b/LoongArch-ELF-ABI-EN.html @@ -0,0 +1,1721 @@ + + + + + + + + +LoongArch ELF ABI specification + + + + +
+
+

Register Convention

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 1. General-purpose Register Convention
NameAliasMeaningPreserved across calls

$r0

$zero

Constant zero

(Constant)

$r1

$ra

Return address

No

$r2

$tp

Thread pointer

(Non-allocatable)

$r3

$sp

Stack pointer

Yes

$r4 - $r5

$a0 - $a1

Argument registers / return value registers

No

$r6 - $r11

$a2 - $a7

Argument registers

No

$r12 - $r20

$t0 - $t8

Temporary registers

No

$r21

Reserved

(Non-allocatable)

$r22

$fp / $s9

Frame pointer / Static register

Yes

$r23 - $r31

$s0 - $s8

Static registers

Yes

+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 2. Floating-point Register Convention
NameAliasMeaningPreserved across calls

$f0 - $f1

$fa0 - $fa1

Argument registers / return value registers

No

$f2 - $f7

$fa2 - $fa7

Argument registers

No

$f8 - $f23

$ft0 - $ft15

Temporary registers

No

$f24 - $f31

$fs0 - $fs7

Static registers

Yes

+
+

Temporary registers are also known as caller-saved registers. +Static registers are also known as callee-saved registers.

+
+
+

Aliases for return value registers

+
+

You may see the names $v0 $v1 $fv0 $fv1 in some very early LoongArch +assembly code; they simply alias to $a0 $a1 $fa0 $fa1 respectively. +The aliases are initially meant to match MIPS convention with separate +argument / return value registers. However, because LoongArch actually has no +dedicated return value registers, such usage may lead to confusion. +Hence, it is not recommended to use these aliases.

+
+
+

Due to implementation details, it may not be easy to give a register multiple +ABI names for a given downstream project. +New programs processing LoongArch assembly should not support these aliases. +Portable LoongArch assembly should avoid these aliases.

+
+
+ + + + + +
+
Note
+		 +
+

For toolchain components provided by the Loongson Corporation, the migration procedure is:

+
+
+

Let the version of the component at this spec’s effect date be N,

+
+
+
    +
  1. +

    keep support in the version N and its stable branch,

    +
    2. +
  2. +

    warn on such usage in the version N+1,

    +
    3. +
  3. +

    remove support in the version N+2.

    +
    4. +
+
+
+

For the respective upstream projects of the components, the procedure above shall be followed if support for such usage is already upstream; +"version N" shall be interpreted as the first release version containing LoongArch support in that case. +For the components not yet upstream, and not interacting with other components that may expect such usage, support for such usage will never be implemented.

+
+
+
+
+
+
+
+

Type Size and Alignment

+
+ + +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 3. LP64 Data Model (base ABI types: lp64d lp64f lp64s)
Scalar typeSize (Bytes)Alignment (Bytes)

bool / _Bool

1

1

unsigned char / char

1

1

unsigned short / short

2

2

unsigned int / int

4

4

unsigned long / long

8

8

unsigned long long / long long

8

8

pointer types

8

8

float

4

4

double

8

8

long double

16

16

+ + +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 4. ILP32 Data Model (base ABI types: ilp32d ilp32f ilp32s)
Scalar typeSize (Bytes)Alignment (Bytes)

bool / _Bool

1

1

unsigned char / char

1

1

unsigned short / short

2

2

unsigned int / int

4

4

unsigned long / long

4

4

unsigned long long / long long

8

8

pointer types

4

4

float

4

4

double

8

8

long double

16

16

+
+

For all base ABI types of LoongArch, +the char datatype is signed by default.

+
+
+
+
+

ELF Object Files

+
+
+

All common ELF definitions referenced in this section +can be found in the latest SysV gABI specification.

+
+
+

EI_CLASS: File class

+ + +++++ + + + + + + + + + + + + + + + + + + + +
Table 5. ELF file classes
EI_CLASSValueDescription

ELFCLASS32

1

ELF32 object file

ELFCLASS64

2

ELF64 object file

+
+
+

e_machine: Identifies the machine

+
+

LoongArch (258)

+
+
+
+

e_flags: Identifies ABI type and version

+ + ++++++ + + + + + + + + + + + + + + + + +
Table 6. ABI-related bits in e_flags
Bit 31 - 8Bit 7 - 6Bit 5 - 3Bit 2 - 0

(reserved)

ABI version

ABI extension

Base ABI Modifier

+
+

The ABI type of an ELF object is uniquely identified by EI_CLASS and e_flags[7:0] in its header.

+
+
+

Within this combination, EI_CLASS and e_flags[2:0] correspond to the base ABI type, +where the expression of C integral and pointer types (data model) +is uniquely determined by EI_CLASS value, and e_flags[2:0] represents additional properties +of the base ABI type, including the FP calling convention. We refer to e_flags[2:0] as +the base ABI modifier.

+
+
+

As a result, programs in lp64* / ilp32* ABI should only be encoded with ELF64 / ELF32 +object files, respectively.

+
+
+

0x0 0x4 0x5 0x6 0x7 are reserved values for e_flags[2:0].

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 7. Base ABI Types
NameEI_CLASSBase ABI Modifier (e_flags[2:0])Description

lp64s

ELFCLASS64

0x1

Uses 64-bit GPRs and the stack for parameter passing. +Data model is LP64, where long and pointers are 64-bit while int is 32-bit.

lp64f

ELFCLASS64

0x2

Uses 64-bit GPRs, 32-bit FPRs and the stack for parameter passing. +Data model is LP64, where long and pointers are 64-bit while int is 32-bit.

lp64d

ELFCLASS64

0x3

Uses 64-bit GPRs, 64-bit FPRs and the stack for parameter passing. +Data model is LP64, where long and pointers are 64-bit while int is 32-bit.

ilp32s

ELFCLASS32

0x1

Uses 32-bit GPRs and the stack for parameter passing. +Data model is ILP32, where int, long and pointers are 32-bit.

ilp32f

ELFCLASS32

0x2

Uses 32-bit GPRs, 32-bit FPRs and the stack for parameter passing. +Data model is ILP32, where int, long and pointers are 32-bit.

ilp32d

ELFCLASS32

0x3

Uses 32-bit GPRs, 64-bit FPRs and the stack for parameter passing. +Data model is ILP32, where int, long and pointers are 32-bit.

+
+

e_flags[5:3] correspond to the ABI extension type.

+
+ + +++++ + + + + + + + + + + + + + + + + + + + +
Table 8. ABI Extension types
Namee_flags[5:3]Description

base

0x0

No extra ABI features.

0x1 - 0x7

(reserved)

+
+

e_flags[7:6] marks the ABI version of an ELF object.

+
+ + +++++ + + + + + + + + + + + + + + + + + + + + + + + + +
Table 9. ABI Version
ABI versionValueDescription

v0

0x0

Stack operands base relocation type.

v1

0x1

Supporting relocation types directly writing to immediate slots. Can be implemented separately without compatibility with v0.

0x2 0x3

Reserved.

+
+
+
+
+

Relocations

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 10. ELF Relocation types
EnumELF reloc typeUsageDetail

0

R_LARCH_NONE

1

R_LARCH_32

Runtime address resolving

*(int32_t *) PC = RtAddr + A

2

R_LARCH_64

Runtime address resolving

*(int64_t *) PC = RtAddr + A

3

R_LARCH_RELATIVE

Runtime fixup for load-address

*(void **) PC = B + A

4

R_LARCH_COPY

Runtime memory copy in executable

memcpy (PC, RtAddr, sizeof (sym))

5

R_LARCH_JUMP_SLOT

Runtime PLT supporting

implementation-defined

6

R_LARCH_TLS_DTPMOD32

Runtime relocation for TLS-GD

*(int32_t *) PC = ID of module defining sym

7

R_LARCH_TLS_DTPMOD64

Runtime relocation for TLS-GD

*(int64_t *) PC = ID of module defining sym

8

R_LARCH_TLS_DTPREL32

Runtime relocation for TLS-GD

*(int32_t *) PC = DTV-relative offset for sym

9

R_LARCH_TLS_DTPREL64

Runtime relocation for TLS-GD

*(int64_t *) PC = DTV-relative offset for sym

10

R_LARCH_TLS_TPREL32

Runtime relocation for TLE-IE

*(int32_t *) PC = T

11

R_LARCH_TLS_TPREL64

Runtime relocation for TLE-IE

*(int64_t *) PC = T

12

R_LARCH_IRELATIVE

Runtime local indirect function resolving

*(void **) PC = (((void *)(*)()) (B + A)) ()

…​ Reserved for dynamic linker.

20

R_LARCH_MARK_LA

Mark la.abs

Load absolute address for static link.

21

R_LARCH_MARK_PCREL

Mark external label branch

Access PC relative address for static link.

22

R_LARCH_SOP_PUSH_PCREL

Push PC-relative offset

push (S - PC + A)

23

R_LARCH_SOP_PUSH_ABSOLUTE

Push constant or absolute address

push (S + A)

24

R_LARCH_SOP_PUSH_DUP

Duplicate stack top

opr1 = pop (), push (opr1), push (opr1)

25

R_LARCH_SOP_PUSH_GPREL

Push for access GOT entry

push (G)

26

R_LARCH_SOP_PUSH_TLS_TPREL

Push for TLS-LE

push (T)

27

R_LARCH_SOP_PUSH_TLS_GOT

Push for TLS-IE

push (IE)

28

R_LARCH_SOP_PUSH_TLS_GD

Push for TLS-GD

push (GD)

29

R_LARCH_SOP_PUSH_PLT_PCREL

Push for external function calling

push (PLT - PC)

30

R_LARCH_SOP_ASSERT

Assert stack top

assert (pop ())

31

R_LARCH_SOP_NOT

Stack top operation

push (!pop ())

32

R_LARCH_SOP_SUB

Stack top operation

opr2 = pop (), opr1 = pop (), push (opr1 - opr2)

33

R_LARCH_SOP_SL

Stack top operation

opr2 = pop (), opr1 = pop (), push (opr1 << opr2)

34

R_LARCH_SOP_SR

Stack top operation

opr2 = pop (), opr1 = pop (), push (opr1 >> opr2)

35

R_LARCH_SOP_ADD

Stack top operation

opr2 = pop (), opr1 = pop (), push (opr1 + opr2)

36

R_LARCH_SOP_AND

Stack top operation

opr2 = pop (), opr1 = pop (), push (opr1 & opr2)

37

R_LARCH_SOP_IF_ELSE

Stack top operation

opr3 = pop (), opr2 = pop (), opr1 = pop (), push (opr1 ? opr2 : opr3)

38

R_LARCH_SOP_POP_32_S_10_5

Instruction imm-field relocation

opr1 = pop (), (*(uint32_t *) PC) [14 ... 10] = opr1 [4 ... 0]

+

with check 5-bit signed overflow

39

R_LARCH_SOP_POP_32_U_10_12

Instruction imm-field relocation

opr1 = pop (), (*(uint32_t *) PC) [21 ... 10] = opr1 [11 ... 0]

+

with check 12-bit unsigned overflow

40

R_LARCH_SOP_POP_32_S_10_12

Instruction imm-field relocation

opr1 = pop (), (*(uint32_t *) PC) [21 ... 10] = opr1 [11 ... 0]

+

with check 12-bit signed overflow

41

R_LARCH_SOP_POP_32_S_10_16

Instruction imm-field relocation

opr1 = pop (), (*(uint32_t *) PC) [25 ... 10] = opr1 [15 ... 0]

+

with check 16-bit signed overflow

42

R_LARCH_SOP_POP_32_S_10_16_S2

Instruction imm-field relocation

opr1 = pop (), (*(uint32_t *) PC) [25 ... 10] = opr1 [17 ... 2]

+

with check 18-bit signed overflow and 4-bit aligned

43

R_LARCH_SOP_POP_32_S_5_20

Instruction imm-field relocation

opr1 = pop (), (*(uint32_t *) PC) [24 ... 5] = opr1 [19 ... 0]

+

with check 20-bit signed overflow

44

R_LARCH_SOP_POP_32_S_0_5_10_16_S2

Instruction imm-field relocation

opr1 = pop (), (*(uint32_t *) PC) [4 ... 0] = opr1 [22 ... 18],

+

(*(uint32_t *) PC) [25 ... 10] = opr1 [17 ... 2]

+

with check 23-bit signed overflow and 4-bit aligned

45

R_LARCH_SOP_POP_32_S_0_10_10_16_S2

Instruction imm-field relocation

opr1 = pop (), (*(uint32_t *) PC) [9 ... 0] = opr1 [27 ... 18],

+

(*(uint32_t *) PC) [25 ... 10] = opr1 [17 ... 2]

+

with check 28-bit signed overflow and 4-bit aligned

46

R_LARCH_SOP_POP_32_U

Instruction fixup

(*(uint32_t *) PC) = pop ()

+

with check 32-bit unsigned overflow

47

R_LARCH_ADD8

8-bit in-place addition

*(int8_t *) PC += S + A

48

R_LARCH_ADD16

16-bit in-place addition

*(int16_t *) PC += S + A

49

R_LARCH_ADD24

24-bit in-place addition

*(int24_t *) PC += S + A

50

R_LARCH_ADD32

32-bit in-place addition

*(int32_t *) PC += S + A

51

R_LARCH_ADD64

64-bit in-place addition

*(int64_t *) PC += S + A

52

R_LARCH_SUB8

8-bit in-place subtraction

*(int8_t *) PC -= S + A

53

R_LARCH_SUB16

16-bit in-place subtraction

*(int16_t *) PC -= S + A

54

R_LARCH_SUB24

24-bit in-place subtraction

*(int24_t *) PC -= S + A

55

R_LARCH_SUB32

32-bit in-place subtraction

*(int32_t *) PC -= S + A

56

R_LARCH_SUB64

64-bit in-place subtraction

*(int64_t *) PC -= S + A

57

R_LARCH_GNU_VTINHERIT

GNU C++ vtable hierarchy

58

R_LARCH_GNU_VTENTRY

GNU C++ vtable member usage

…​ Reserved

64

R_LARCH_B16

18-bit PC-relative jump

(*(uint32_t *) PC) [25 ... 10] = (S+A-PC) [17 ... 2]

+

with check 18-bit signed overflow and 4-bit aligned

65

R_LARCH_B21

23-bit PC-relative jump

(*(uint32_t *) PC) [4 ... 0] = (S+A-PC) [22 ... 18],

+

(*(uint32_t *) PC) [25 ... 10] = (S+A-PC) [17 ... 2]

+

with check 23-bit signed overflow and 4-bit aligned

66

R_LARCH_B26

28-bit PC-relative jump

(*(uint32_t *) PC) [9 ... 0] = (S+A-PC) [27 ... 18],

+

(*(uint32_t *) PC) [25 ... 10] = (S+A-PC) [17 ... 2]

+

with check 28-bit signed overflow and 4-bit aligned

67

R_LARCH_ABS_HI20

[31 …​ 12] bits of 32/64-bit absolute address

(*(uint32_t *) PC) [24 ... 5] = (S+A) [31 ... 12]

68

R_LARCH_ABS_LO12

[11 …​ 0] bits of 32/64-bit absolute address

(*(uint32_t *) PC) [21 ... 10] = (S+A) [11 ... 0]

69

R_LARCH_ABS64_LO20

[51 …​ 32] bits of 64-bit absolute address

(*(uint32_t *) PC) [24 ... 5] = (S+A) [51 ... 32]

70

R_LARCH_ABS64_HI12

[63 …​ 52] bits of 64-bit absolute address

(*(uint32_t *) PC) [21 ... 10] = (S+A) [63 ... 52]

71

R_LARCH_PCALA_HI20

[31 …​ 12] bits of 32/64-bit PC-relative offset

(*(uint32_t *) PC) [24 ... 5] = (((S+A) & ~0xfff) - (PC & ~0xfff)) [31 ... 12]

+

Note: The lower 12 bits are not included when calculating the PC-relative offset.

72

R_LARCH_PCALA_LO12

[11 …​ 0] bits of 32/64-bit address

(*(uint32_t *) PC) [21 ... 10] = (S+A) [11 ... 0]

73

R_LARCH_PCALA64_LO20

[51 …​ 32] bits of 64-bit PC-relative offset

(*(uint32_t *) PC) [24 ... 5] = (S+A - (PC & ~0xffffffff)) [51 ... 32]

74

R_LARCH_PCALA64_HI12

[63 …​ 52] bits of 64-bit PC-relative offset

(*(uint32_t *) PC) [21 ... 10] = (S+A - (PC & ~0xffffffff)) [63 ... 52]

75

R_LARCH_GOT_PC_HI20

[31 …​ 12] bits of 32/64-bit PC-relative offset to GOT entry

(*(uint32_t *) PC) [24 ... 5] = (((GP+G) & ~0xfff) - (PC & ~0xfff)) [31 ... 12]

76

R_LARCH_GOT_PC_LO12

[11 …​ 0] bits of 32/64-bit GOT entry address

(*(uint32_t *) PC) [21 ... 10] = (GP+G) [11 ... 0]

77

R_LARCH_GOT64_PC_LO20

[51 …​ 32] bits of 64-bit PC-relative offset to GOT entry

(*(uint32_t *) PC) [24 ... 5] = (GP+G - (PC & ~0xffffffff)) [51 ... 32]

78

R_LARCH_GOT64_PC_HI12

[63 …​ 52] bits of 64-bit PC-relative offset to GOT entry

(*(uint32_t *) PC) [21 ... 10] = (GP+G - (PC & ~0xffffffff)) [63 ... 52]

79

R_LARCH_GOT_HI20

[31 …​ 12] bits of 32/64-bit GOT entry absolute address

(*(uint32_t *) PC) [24 ... 5] = (GP+G) [31 ... 12]

80

R_LARCH_GOT_LO12

[11 …​ 0] bits of 32/64-bit GOT entry absolute address

(*(uint32_t *) PC) [21 ... 10] = (GP+G) [11 ... 0]

81

R_LARCH_GOT64_LO20

[51 …​ 32] bits of 64-bit GOT entry absolute address

(*(uint32_t *) PC) [24 ... 5] = (GP+G) [51 ... 32]

82

R_LARCH_GOT64_HI12

[63 …​ 52] bits of 64-bit GOT entry absolute address

(*(uint32_t *) PC) [21 ... 10] = (GP+G) [63 ... 52]

83

R_LARCH_TLS_LE_HI20

[31 …​ 12] bits of TLS LE 32/64-bit offset from TP register

(*(uint32_t *) PC) [24 ... 5] = T [31 ... 12]

84

R_LARCH_TLS_LE_LO12

[11 …​ 0] bits of TLS LE 32/64-bit offset from TP register

(*(uint32_t *) PC) [21 ... 10] = T [11 ... 0]

85

R_LARCH_TLS_LE64_LO20

[51 …​ 32] bits of TLS LE 64-bit offset from TP register

(*(uint32_t *) PC) [24 ... 5] = T [51 ... 32]

86

R_LARCH_TLS_LE64_HI12

[63 …​ 52] bits of TLS LE 64-bit offset from TP register

(*(uint32_t *) PC) [21 ... 10] = T [63 ... 52]

87

R_LARCH_TLS_IE_PC_HI20

[31 …​ 12] bits of 32/64-bit PC-relative offset to TLS IE GOT entry

(*(uint32_t *) PC) [24 ... 5] = (((GP+IE) & ~0xfff) - (PC & ~0xfff)) [31 ... 12]

88

R_LARCH_TLS_IE_PC_LO12

[11 …​ 0] bits of 32/64-bit TLS IE GOT entry address

(*(uint32_t *) PC) [21 ... 10] = (GP+IE) [11 ... 0]

89

R_LARCH_TLS_IE64_PC_LO20

[51 …​ 32] bits of 64-bit PC-relative offset to TLS IE GOT entry

(*(uint32_t *) PC) [24 ... 5] = (GP+IE - (PC & ~0xffffffff)) [51 ... 32]

90

R_LARCH_TLS_IE64_PC_HI12

[63 …​ 52] bits of 64-bit PC-relative offset to TLS IE GOT entry

(*(uint32_t *) PC) [21 ... 10] = (GP+IE - (PC & ~0xffffffff)) [63 ... 52]

91

R_LARCH_TLS_IE_HI20

[31 …​ 12] bits of 32/64-bit TLS IE GOT entry absolute address

(*(uint32_t *) PC) [24 ... 5] = (GP+IE) [31 ... 12]

92

R_LARCH_TLS_IE_LO12

[11 …​ 0] bits of 32/64-bit TLS IE GOT entry absolute address

(*(uint32_t *) PC) [21 ... 10] = (GP+IE) [11 ... 0]

93

R_LARCH_TLS_IE64_LO20

[51 …​ 32] bits of 64-bit TLS IE GOT entry absolute address

(*(uint32_t *) PC) [24 ... 5] = (GP+IE) [51 ... 32]

94

R_LARCH_TLS_IE64_HI12

[63 …​ 52] bits of 64-bit TLS IE GOT entry absolute address

(*(uint32_t *) PC) [21 ... 10] = (GP+IE) [63 ... 52]

95

R_LARCH_TLS_LD_PC_HI20

[31 …​ 12] bits of 32/64-bit PC-relative offset to TLS LD GOT entry

(*(uint32_t *) PC) [24 ... 5] = (((GP+GD) & ~0xfff) - (PC & ~0xfff)) [31 ... 12]

96

R_LARCH_TLS_LD_HI20

[31 …​ 12] bits of 32/64-bit TLS LD GOT entry absolute address

(*(uint32_t *) PC) [24 ... 5] = (GP+IE) [31 ... 12]

97

R_LARCH_TLS_GD_PC_HI20

[31 …​ 12] bits of 32/64-bit PC-relative offset to TLS GD GOT entry

(*(uint32_t *) PC) [24 ... 5] = (((GP+GD) & ~0xfff) - (PC & ~0xfff)) [31 ... 12]

98

R_LARCH_TLS_GD_HI20

[31 …​ 12] bits of 32/64-bit TLS GD GOT entry absolute address

(*(uint32_t *) PC) [24 ... 5] = (GP+IE) [31 ... 12]

99

R_LARCH_32_PCREL

32-bit PC relative

(*(uint32_t *) PC) = (S+A-PC) [31 ... 0]

100

R_LARCH_RELAX

Instruction can be relaxed, paired with a normal relocation at the same address

+
+
+
+

Program Interpreter Path

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 11. Standard Program Interpreter Paths
Base ABI typeABI extension typeOperating system / C libraryProgram interpreter path

lp64d

base

Linux, Glibc

/lib64/ld-linux-loongarch-lp64d.so.1

lp64f

base

Linux, Glibc

/lib64/ld-linux-loongarch-lp64f.so.1

lp64s

base

Linux, Glibc

/lib64/ld-linux-loongarch-lp64s.so.1

ilp32d

base

Linux, Glibc

/lib32/ld-linux-loongarch-ilp32d.so.1

ilp32f

base

Linux, Glibc

/lib32/ld-linux-loongarch-ilp32f.so.1

ilp32s

base

Linux, Glibc

/lib32/ld-linux-loongarch-ilp32s.so.1

+
+
+
+

Procedure Calling Convention

+
+
+

Abbreviations

+
+

In this document, GRLEN is the bit width of general-purpose register, FRLEN is the bit width of floating-point register and WOA is the bit width of the argument. +The general-purpose argument register is denoted as GAR and the floating-point argument register is denoted as FAR.

+
+
+
+

Argument Registers

+
+

The basic principle of the LoongArch procedure calling convention is to pass arguments in registers as much as possible (i.e. floating-point arguments are passed in floating-point registers and non floating-point arguments are passed in general-purpose registers, as much as possible); arguments are passed on the stack only when no appropriate register is available.

+
+
+

The argument registers are:

+
+
+
    +
  1. +

    Eight floating-point registers fa0-fa7 used for passing pass floating-point arguments, and fa0-fa1 are also used to return values.

    +
    2. +
  2. +

    Eight general-purpose registers a0-a7 used for passing pass integer arguments, with a0-a1 reused to return values.

    +
    3. +
+
+
+

Generally, the GARs are used to pass fixed-point arguments, and floating-point arguments when no FAR is available. +Bit fields are stored in little endian. +In addition, subroutines should ensure that the values of general-purpose registers s0-s9 and floating-point registers fs0-fs7 are preserved across procedure calls.

+
+
+
+

ABI LP64D

+
+

That is, GRLEN = 64, FRLEN = 64.

+
+
+
+

C Data Types and Alignment

+
+

The C data types and alignment in the LP64D ABI are defined in the table 3.

+
+
+

In most cases, the unsigned integer data types are zero-extended when stored in general-purpose register, and the signed integer data types are sign-extended. +However, in the LP64D ABI, unsigned 32-bit types, such as unsigned int, are stored in general-purpose registers as proper sign extensions of their 32-bit values.

+
+
+
+

Argument passing

+
+

Generally speaking, FARs are only used to pass floating-point arguments, GARs are used to pass non floating-point arguments and floating-point arguments when no FAR is available(long double type is also passed in a pair of GARs) and the reference.

+
+
+

Arguments passed by reference may be modified by the callee.

+
+
+

Scalar

+
+

There are two cases:

+
+
+
    +
  1. +

    0 < WOA ≤ GRLEN

    +
    +
      +
    1. +

      Argument is passed in a single argument register, or on the stack by value if none is available.

      +
      +
        +
      1. +

        If the argument is floating-point type, the argument is passed in FAR. +if no FAR is available, it’s passed in GAR. If no GAR is available, it’s passed on the stack. +When passed in registers or on the stack, floating-point types narrower than GRLEN bits are widened to GRLEN bits, with the upper bits undefined.

        +
        2. +
      2. +

        If the argument is integer or pointer type, the argument is passed in GAR. +If no GAR is available, it’s passed on the stack. +When passed in registers or on the stack, the unsigned integer scalars narrower than GRLEN bits are zero-extended to GRLEN bits, and the signed integer scalars are sign-extended.

        +
        3. +
      +
      +
      2. +
    +
    +
    2. +
  2. +

    GRLEN < WOA ≤ 2 × GRLEN

    +
    +
      +
    1. +

      The argument is passed in a pair of GAR, with the low-order GRLEN bits in the lower-numbered register and the high-order GRLEN bits in the higher-numbered register. +If exactly one register is available, the low-order GRLEN bits are passed in the register and the high-order GRLEN bits are passed on the stack. +If no GAR is available, it’s passed on the stack.

      +
      2. +
    +
    +
    3. +
+
+
+
+

Structure

+
+

Empty structures are ignored by C compilers which support them as a non-standard extension(same as union arguments and return values). +Bits unused due to padding, and bits past the end of a structure whose size in bits is not divisible by GRLEN, are undefined. +And the layout of the structure on the stack is consistent with that in memory.

+
+
+
    +
  1. +

    0 < WOA ≤ GRLEN

    +
    +
      +
    1. +

      The structure has only fixed-point members. +If there is an available GAR, the structure is passed through the GAR by value passing; If no GAR is available, it’s passed on the stack.

      +
      2. +
    2. +

      The structure has only floating-point members:

      +
      +
        +
      1. +

        One floating-point member. +The argument is passed in a FAR; If no FAR is available, the value is passed in a GAR; if no GAR is available, the value is passed on the stack.

        +
        2. +
      2. +

        Two floating-point members. +The argument is passed in a pair of available FAR, with the low-order float member bits in the lower-numbered FAR and the high-order float member bits in the higher-numbered FAR. +If the number of available FAR is less than 2, it’s passed in a GAR, and passed on the stack if no GAR is available.

        +
        3. +
      +
      +
      3. +
    3. +

      The structure has both fixed-point and floating-point members, i.e. the structure has one float member and…​

      +
      +
        +
      1. +

        Multiple fixed-point members. +If there are available GAR, the structure is passed in a GAR, and passed on the stack if no GAR is available.

        +
        2. +
      2. +

        Only one fixed-point member. +If one FAR and one GAR are available, the floating-point member of the structure is passed in the FAR, and the integer member of the structure is passed in the GAR; If no floating-point register but one GAR is available, it’s passed in GAR; If no GAR is available, it’s passed on the stack.

        +
        3. +
      +
      +
      4. +
    +
    +
    2. +
  2. +

    GRLEN < WOA ≤ 2 × GRLEN

    +
    +
      +
    1. +

      Only fixed-point members.

      +
      +
        +
      1. +

        The argument is passed in a pair of available GAR, with the low-order bits in the lower-numbered GAR and the high-order bits in the higher-numbered GAR. +If only one GAR is available, the low-order bits are in the GAR and the high-order bits are on the stack, and passed on the stack if no GAR is available.

        +
        2. +
      +
      +
      2. +
    2. +

      Only floating-point members.

      +
      +
        +
      1. +

        The structure has one long double member or one double member and two adjacent float members or 3-4 float members. +The argument is passed in a pair of available GAR, with the low-order bits in the lower-numbered GAR and the high-order bits in the higher-numbered GAR. +If only one GAR is available, the low-order bits are in the GAR and the high-order bits are on the stack, and passed on the stack if no GAR is available.

        +
        2. +
      2. +

        The structure with two double members is passed in a pair of available FARs. If no a pair of available FARs, it’s passed in GARs. A structure with one double member and one float member is same.

        +
        3. +
      +
      +
      3. +
    3. +

      Both fixed-point and floating-point members.

      +
      +
        +
      1. +

        The structure has one double member and only one fixed-point member.

        +
        +
          +
        1. +

          If one FAR and one GAR are available, the floating-point member of the structure is passed in the FAR, and the integer member of the structure is passed in the GAR; If no floating-point registers but two GARs are available, it’s passed in the two GARs; If only one GAR is available, the low-order bits are in the GAR and the high-order bits are on the stack; And it’s passed on the stack if no GAR is available.

          +
          2. +
        +
        +
        2. +
      2. +

        Others

        +
        +
          +
        1. +

          The argument is passed in a pair of available GAR, with the low-order bits in the lower-numbered GAR and the high-order bits in the higher-numbered GAR. +If only one GAR is available, the low-order bits are in the GAR and the high-order bits are on the stack, and passed on the stack if no GAR is available.

          +
          2. +
        +
        +
        3. +
      +
      +
      4. +
    +
    +
    3. +
  3. +

    WOA > 2 × GRLEN

    +
    +
      +
    1. +

      It’s passed by reference and are replaced in the argument list with the address. +If there is an available GAR, the reference is passed in the GAR, and passed on the stack if no GAR is available.

      +
      2. +
    +
    +
    4. +
+
+
+

Structure and scalars passed on the stack are aligned to the greater of the type alignment and GRLEN bits, but never more than the stack alignment.

+
+
+
+

Union

+
+

Union is passed in GAR or stack.

+
+
+
    +
  1. +

    0 < WOA ≤ GRLEN

    +
    +
      +
    1. +

      The argument is passed in a GAR, or on the stack by value if no GAR is available.

      +
      2. +
    +
    +
    2. +
  2. +

    GRLEN < WOA ≤ 2 × GRLEN

    +
    +
      +
    1. +

      The argument is passed in a pair of available GAR, with the low-order bits in the lower-numbered GAR and the high-order bits in the higher-numbered GAR. +If only one GAR is available, the low-order bits are in the GAR and the high-order bits are on the stack. +The arguments are passed on the stack when no GAR is available.

      +
      2. +
    +
    +
    3. +
  3. +

    WOA > 2 × GRLEN

    +
    +
      +
    1. +

      It’s passed by reference and are replaced in the argument list with the address. +If there is an available GAR, the reference is passed in the GAR, and passed on the stack if no GAR is available.

      +
      2. +
    +
    +
    4. +
+
+
+
+

Complex

+
+

A complex floating-point number, or a structure containing just one complex floating-point number, is passed as though it were a structure containing two floating-point reals.

+
+
+
+

Variadic arguments

+
+

Variadic arguments are passed in GARs in the same manner as named arguments. And after a variadic argument has been passed on the stack, all future arguments will also be passed on the stack, i.e., the last argument register may be left unused due to the aligned register pair rule.

+
+
+
    +
  1. +

    0 < WOA ≤ GRLEN

    +
    +
      +
    1. +

      The variadic arguments are passed in a GAR, or on the stack by value if no GAR is available.

      +
      2. +
    +
    +
    2. +
  2. +

    GRLEN < WOA ≤ 2 × GRLEN

    +
    +
      +
    1. +

      The variadic arguments are passed in a pair of GARs. If only one GAR is available, the low-order bits are in the GAR and the high-order bits are on the stack, and passed on the stack if no GAR is available. or on the stack by value if none is available. It should be noted that long double data tpye is passed in an aligned GAR pair(the first register in the pair is even-numbered).

      +
      2. +
    +
    +
    3. +
  3. +

    WOA > 2 × GRLEN

    +
    +
      +
    1. +

      It’s passed by reference and are replaced in the argument list with the address. +If there is an available GAR, the reference is passed in the GAR, and passed on the stack if no GAR is available.

      +
      2. +
    +
    +
    4. +
+
+
+
+
+

Return values

+
+
    +
  1. +

    Generally speaking, a0 and a1 are used to return non floating-point values, and fa0 and fa1 are used to return floating-point values.

    +
    2. +
  2. +

    Values are returned in the same manner as a first named argument of the same type would be passed. +If such an argument would have been passed by reference, the caller allocates memory for the return value, and passes the address as an implicit first argument.

    +
    3. +
  3. +

    The reference of the return value is returned that is stored in GAR a0 if the size of the return value is larger than 2×GRLEN bits.

    +
    4. +
+
+
+
+

Stack

+
+
    +
  1. +

    In general, the stack frame for a subroutine may contain space to contain the following:

    +
    +
      +
    1. +

      Space to store arguments passed to subroutines that this subroutine calls.

      +
      2. +
    2. +

      A place to store the subroutine’s return address.

      +
      3. +
    3. +

      A place to store the values of saved registers.

      +
      4. +
    4. +

      A place for local data storage.

      +
      5. +
    +
    +
    2. +
  2. +

    The stack grows downwards (towards lower addresses) and the stack pointer shall be aligned to a 128-bit boundary upon procedure entry. +The first argument passed on the stack is located at offset zero of the stack pointer on function entry; following arguments are stored at correspondingly higher addresses.

    +
    3. +
  3. +

    Procedures must not rely upon the persistence of stack-allocated data whose addresses lies below the stack pointer.

    +
    4. +
+
+
+
+
+
+

Appendix: Revision History

+
+
+
    +
  • +

    v1.00

    +
    +
      +
    • +

      Add register usage convention, data type conventions and the list of ELF relocation types.

      +
      • +
    +
    +
    • +
  • +

    v2.00

    +
    +
      +
    • +

      Add description of ILP32 data model.

      +
      • +
    • +

      Add description of return value register aliases.

      +
      • +
    • +

      Add relocation types with direct immediate-filling semantics.

      +
      • +
    • +

      Add ABI version porting guidelines for toolchain implementations.

      +
      • +
    • +

      Add link to SysV gABI documentation.

      +
      • +
    • +

      Adjust asciidoc code style.

      +
      • +
    +
    +
    • +
  • +

    v2.01

    +
    +
      +
    • +

      Adjust description of ABI type encoding scheme.

      +
      • +
    • +

      Add header for all tables.

      +
      • +
    +
    +
    • +
+
+
+
+
+ + +
+ + Creative Commons License + +
+ This work is licensed under a + Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License. +
+ + + + + + + + + \ No newline at end of file diff --git a/LoongArch-ELF-ABI-EN.pdf b/LoongArch-ELF-ABI-EN.pdf new file mode 100644 index 0000000..18b0e7e Binary files /dev/null and b/LoongArch-ELF-ABI-EN.pdf differ diff --git a/LoongArch-Processor-SMBIOS-Spec-EN.html b/LoongArch-Processor-SMBIOS-Spec-EN.html new file mode 100644 index 0000000..2e76bb9 --- /dev/null +++ b/LoongArch-Processor-SMBIOS-Spec-EN.html @@ -0,0 +1,303 @@ + + + + + + + + +LoongArch Processor SMBIOS Spec + + + + +
+
+
+
+

This document defines LoongArch processor-specific data block to supplement the upstream definition of SMBIOS structure Type 44 (Processor Additional Information, section 7.45 in SMBIOS specification V3.5.0 or later).

+
+
+
+
+

1. Symbols

+
+
+
    +
  • +

    DQWORD
    +128-bits (In the SMBIOS specification, WORD is 16-bits, DWORD is 32-bits, and QWORD is 64-bits).

    +
    • +
+
+
+
+
+

2. Vendor Name register and CPU Name register

+
+
+

The LoongArch CPUs designed by Loongson have two registers representing Machine Vendor Name and CPU Name, both of which are DQWORD-format NUL-terminated ASCII string values, located at offsets 0x10 and 0x20 of the IOCSR space respectively.

+
+
+
+
+

3. LoongArch Type 44 Processor Additional Information

+
+
+

The information in this structure defines the processor additional information in case SMBIOS type 4 is not sufficient to describe processor characteristics. The SMBIOS type 44 structure has a reference handle field to link back to the related SMBIOS type 4 structure. There may be multiple SMBIOS type 44 structures linked to the same SMBIOS type 4 structure. For example, when cores are not identical in a processor, SMBIOS type 44 structures describe different core-specific information.

+
+
+

SMBIOS type 44 defines the standard header for the processor-specific block (see 7.45.1), while the contents of processor-specific data are maintained by processor architecture workgroups or vendors in separate documents (see 7.45.2).

+
+
+

3.1 Standard Processor Additonal Information (Type 44) structure

+
+

The following is the standard header of SMBIOS type 44 defined in SMBIOS specification section 7.45.

+
+ +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
OffsetNameLengthValueDescription

00h

Type

BYTE

44

Processor Additional Information

01h

Length

BYTE

6 + Y

Length of the structure. Y is the length of Processor-specific Block specified at offset 06h.

02h

Handle

WORD

Varies

Handle, or instance number, associated with the structure

04h

Referenced Handle

WORD

Varies

Handle, or instance number, associated with the Processor structure (SMBIOS type 4) which the Processor Additional Information structure describes.

06h

Processor-Specific Block

Varies (Y)

Varies

Processor-specific block (See section 3.2)

+
+
+

3.2 Standard Processor-specific Block

+
+

Processor-specific block is the standard header of processor-specific data as defined in SMBIOS section 7.45.1.

+
+ +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
OffsetNameLengthValueDescription

00h

Block Length

BYTE

Varies (N)

Length of Processor-specific Data

01h

Processor Type

BYTE

Varies

The processor architecture delineated by this Processor-specific Block. (See SMBIOS Table 131)

02h

Processor-Specific Data

N BYTEs

Varies

Processor-specific data. (See section 3.3)

+
+
+

3.3 LoongArch Processor-specific Block Structure

+ +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
OffsetNameLengthValueDescription

00h

Revision

WORD

0100h (v1.00)

Revision of LoongArch Processor-specific Block structure.
+Bits [15:8] Major revision, bits [7:0] Minor revision.

02h

Block Length

BYTE

28h (40d)

Length of Processor-specific Data

03h

Reserved

BYTE

0

Reserved.

04h

Machine Vendor ID

DQWORD

Varies

The manufacturer vendor ID of the processor.
+It is semantically equivalent to the value at the offset 0x10 of the IOCSR space on a Loongson CPU.

14h

CPU ID

DQWORD

Varies

The CPU ID used for this LoongArch processor manufacturer to mark different CPU types or CPU instances.
+It is semantically equivalent to the value at the offset 0x20 of the IOCSR space on a Loongson CPU.

24h

ISA extensions support

DWORD

Bit-field

The bit field [3:0] indicates support for the existing LoongArch standard ISA extensions. It is modeled after the LoongArch EUEN register (CSR 0x2), and meaning of each bit is the same as defined for the EUEN register.
+Setting a bit in this field indicates that this system supports the corresponding ISA extension.

+
+
+
+
+ + +
+ + Creative Commons License + +
+ This work is licensed under a + Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License. +
+ + + + + + + + + \ No newline at end of file diff --git a/LoongArch-Processor-SMBIOS-Spec-EN.pdf b/LoongArch-Processor-SMBIOS-Spec-EN.pdf new file mode 100644 index 0000000..c117ead Binary files /dev/null and b/LoongArch-Processor-SMBIOS-Spec-EN.pdf differ diff --git a/LoongArch-Vol1-EN.html b/LoongArch-Vol1-EN.html new file mode 100644 index 0000000..f0c0394 --- /dev/null +++ b/LoongArch-Vol1-EN.html @@ -0,0 +1,22157 @@ + + + + + + + + +LoongArch Reference Manual - Volume 1: Basic Architecture + + + + +
+
+

List of Figures

+
+
+ +
+
+
+
+

List of Tables

+
+
+ +
+
+
+
+

About this manual

+
+
+

Copyright Statement

+
+

The copyright of this document belongs to Loongson Technology Corporation Limited. +Without written permission, no company or individualmay disclose, reproduce or otherwise distribute any part of this document to third parties. +Otherwise, they will be held legally responsible.

+
+
+
+

Disclaimer

+
+

This document provides only periodic information, and the contents contained may be updated at any time without notice, depending on the actual situation of the product. +Loongson Technology Corporation Limited is not responsible for any direct or indirect damage aused by the improper use of the document.

+
+
+
+

Loongson Technology Corporation Limited

+
+

Building No.2, Loongson Industrial Park,
+Zhongguancun Environmental Protection Park, Haidian District, Beijing

+
+
+

Tel: 010-62546668

+
+
+

Fax: 010-62600826

+
+
+
+

Reading Guide

+
+

This is the first volume of LoongArch Reference Manual, which describes the basic part of the LoongArch architecture.

+
+
+
+

Translator’s Note

+
+

These documents were translated by Yanteng Si and Feiyang Chen.

+
+
+

This is the translation of https://github.com/loongson/LoongArch-Documentation/releases/latest/download/LoongArch-Vol1-v1.00-CN.pdf.

+
+
+

Due to the limited knowledge of the translators, there are some inevitable errors and omissions existing in this document, please feel free to correct.

+
+
+
+

License

+
+

This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License. +To view a copy of this license, visit http://creativecommons.org/licenses/by-nc-nd/4.0/ or send a letter to Creative Commons, PO Box 1866, Mountain View, CA 94042, USA.

+
+
+
+

Contributors

+
+

Since the release of the project, we have gotten several errata and content changes donated. +Here are all the people who have contributed to LoongArch Documentation as an open source project. +Thank you everyone for helping make this a better book for everyone.

+
+
+

The contributors are listed in alphabetical order.

+
+
+
+
Chao LI <lichao@loongson.cn>
+Chenghua Xu <xuchenghua@loongson.cn>
+Dandan Zhang <zhangdandan@loongson.cn>
+Feiyang Chen <chenfeiyang@loongson.cn>
+FreeFlyingSheep <fyang.168.hi@163.com>
+Konstantin Romanov <konstantinsromanov@gmail.com>
+LI Chao <lichao@loongson.cn>
+limeidan <limeidan@loongson.cn>
+liuzhensong <liuzhensong@loongson.cn>
+mengqinggang <mengqinggang@loongson.cn>
+Qi Hu <huqi@loongson.cn>
+qmuntal <quimmuntal@gmail.com>
+tangxiaolin <tangxiaolin@loongson.cn>
+WANG Xuerui <git@xen0n.name>
+wangguofeng <wangguofeng@loongson.cn>
+Wu Xiaotian <wuxiaotian@loongson.cn>
+Wu Xiaotian <yetist@gmail.com>
+Xi Ruoyao <xry111@mengyan1223.wang>
+Yang Yujie <yangyujie@alumni.sjtu.edu.cn>
+Yang Yujie <yangyujie@loongson.cn>
+Yanteng <siyanteng@loongson.cn>
+Yanteng Si <siyanteng@loongson.cn>
+
+
+
+
+
+
+

1. Introduction

+
+
+

The LoongArch architecture (LoongArch) is an Instruction Set Architecture (ISA) that has Reduced Instruction Set Computer (RISC) style. +The LoongArch Reference Manual is used to explain the LoongArch specification. +This is the first of three volumes, which describes the basic part of LoongArch.

+
+
+

1.1. Overview of LoongArch ISA

+
+

LoongArch has the typical characteristics of RISC. +LoongArch instructions are of fixed size and have regular instruction formats. +Most of the instructions have two source operands and one destination operand. +LoongArch is a load-store architecture; this means only the load/store instructions can access memory the operands of the other instructions are within the processor core or the immediate number in the instruction opcode.

+
+
+

LoongArch is divided into two versions, the 32-bit version (LA32) and the 64-bit version (LA64). +LA64 applications are “application-level backward binary compatibility” with LA32 applications. +That means LA32 applications can run directly on the machine compatible with LA64, but the behavior of system softwares (such as the kernel) on the machine compatible with LA32 is not guaranteed to be the same as on the machine compatible with LA64.

+
+
+

LoongArch is composed of a basic part (Loongson Base) and an expanded part, as shown in the figure. +The expansion part includes Loongson Binary Translation (LBT), Loongson VirtualiZation (LVZ), Loongson SIMD EXtension (LSX), and Loongson Advanced SIMD EXtension(LASX).

+
+
+
+loongarch components +
+
Figure 1. LoongArch components
+
+
+

The basic part of LoongArch includes an non-privileged instruction set and a privileged instruction set. +The non-privileged instruction set defines commonly used integer and floating-point instructions, which can adequately support the current mainstream compiler to generate efficient target codes.

+
+
+

The virtualization extension part of LoongArch is used for operating system virtualization to provide hardware acceleration to improve performance. +This part involves basically all privileged resources, including some privileged instructions and control and status registers, functions added in exceptions and interrupts, memory management, and so on.

+
+
+

The binary translation extension part of LoongArch is used to improve the execution efficiency of the cross-instruction system binary translation on the LoongArch platform. +It expands on the basic part and also includes two parts, the non-privileged instruction set and the privileged instruction set.

+
+
+

LoongArch vector instruction extension and advanced vector instruction extension both use SIMD instructions to accelerate CPU-bound applications. +They are basically the same in terms of instruction functions. +The difference is that the vector length of the vector instruction extension operation is 128 bits and the vector length of the advanced vector instruction extension operation is 256 bits.

+
+
+

For the architecture compatible with LoongArch, the basic part of the LoongArch must be implemented, and the extended part can be implemented optionally. +Each extension part can be selected flexibly, but when choosing to implement LASX, LSX must be implemented. +Some optional subsets of functions are included in the basic part and each extension part. +The software can detect whether these optional functions are implemented via the CPUCFG instruction.

+
+
+

The follow-up evolution of the LoongArch adopts a “fine-grained incremental evolution” method. +The so-called “fine-grained” means that each functional subset in the basic part or the extended part can evolve independently. +The so-called “incremental” means that for any part that can be evolved independently, the higher version is always forward binary compatible[1] with the lower version.

+
+
+

Starting from Chapter 2 of this manual, the specification of the LoongArch will be described in detail. +The contents of Chapter 2 and 3 involve the non-privileged instruction set part of the architecture, including the function definitions of basic integer instructions and basic floating-point instructions and their application-level programming models. +Chapters 4 to 7 are used to describe the privileged resources in the architecture, mainly including the introduction of privileged instructions, control and status registers, function specifications in operating modes, exceptions and interrupts, memory management, and etc. +The pseudo-code descriptions designed to describe the function definitions of instructions are concentrated in Appendix A. +The specific coding definitions of the instructions involved are listed in Appendix B.

+
+
+
+

1.2. Instruction formats

+
+

All LoongArch instructions are fixed 32 bits and required to be aligned on 4-byte boundaries. +If the address of an instruction is not aligned, address error exception will be triggered.

+
+
+

The style of instruction encoding is that all register operand fields are placed in order from low to high starting from the 0th bit, while the opcode field is placed in order from the 31st bit from high to low. +The immediate field, which has different lengths according to different instruction types, is located between the register field and the opcode field if the instruction contains an immediate operand. +Specifically, it contains 9 typical instruction formats, including 3 formats without immediate data (2R, 3R, and 4R), and 6 formats with immediate data (2RI8, 2RI12, 2RI14, 2RI16, 1RI21, and I26). +The table below lists the specific definitions of these 9 typical formats. +There are a few instructions whose encoding style is not completely equivalent to these 9 typical instruction formats. +However, the number of such instructions is small and the instructions change little, which will not be inconvenient for compiler developers.

+
+ + +++++++++++++++++++++++++++++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 1. Typical Instruction Formats in LoongArch
3130292827262524232221201918171615141312111009080706050403020100

2R-type

opcode

rj

rd

3R-type

opcode

rk

rj

rd

4R-type

opcode

ra

rk

rj

rd

2RI8-type

opcode

I8

rj

rd

2RI12-type

opcode

I12

rj

rd

2RI14-type

opcode

I14

rj

rd

2RI16-type

opcode

I16

rj

rd

1RI21-type

opcode

I21[15:0]

rj

I21[20:16]

I26-type

opcode

I26[15:0]

I26[25:16]

+
+
+

1.3. Assembly Instruction Mnemonic Formats

+
+

The assembly instruction mnemonic mainly includes the instruction name and the operand. +LoongArch considers the prefix and suffix of instruction names and operands to make it easier for assembly programmers and compiler developers to use.

+
+
+

First, non-vector instructions and vector instructions, as well as integer and floating-point instructions, can be distinguished by the prefix of instruction name. +The instruction name of a 128-bit vector instruction begins with the letter V; the instruction name of a 256-bit vector instruction begins with the letter XV. +The instruction name of a non-vector floating-point instruction begins with the letter F; the instruction name of a 128-bit vector floating-point instruction begins with VF; the instruction name of a 256-bit vector floating-point instruction begins with XVF.

+
+
+

Secondly, most instructions use a suffix in the form of .XX in the instruction name to indicate the operand type of the instruction. +This form of suffix is only used to characterize the type of the instruction operand. +If the operand is an integer, the suffixes of the instruction name include .B (signed byte), .H (signed half word), .W (signed word), .D (signed double word), .BU (unsigned byte), .HU (unsigned half word), .WU (unsigned word), and .DU (unsigned double word). +An exception is that if whether the operand is signed or unsigned does not affect the result of the operation, the suffix of the instruction name will not carry U. +In this case, the suffix does not limit the operand to the signed number. +If operand is a floating-point number, the suffixes of the instruction name are .H (half precision), .S (single-precision), .D (double-precision), .W (signed word), .L (signed double word), .WU (unsigned word), .LU (unsigned double word). +In addition, for instructions involving vector operations, the suffix .V of the instruction name indicates that the entire vector data is operated as a whole. +An exception is that if the length of the operand of an instruction is determined by whether the processor is 32-bit or 64-bit, the instruction name has no suffix, such as SLT instruction and SLTU instruction. +Privileged instructions for operating CSRs, TLB, and Cache, and instructions for moving data between different register files have no suffix.

+
+
+

If the length and sign of the source operand and the destination operand are the same, the instruction name will have only one suffix. +If the length and sign of all source operands are the same, but not the same as the destination operand, the instruction name will have two suffixes. +From left to right, the first suffix decorates the destination operand, and the second suffix decorates the source operand. +If the source operation and destination operand are more complicated, the instruction name will list the destination operand and each source operand in order from left to right. +The order is consistent with the order of the subsequent operands in the instruction mnemonic. +For example, in the instruction MULW.D.WU rd, rj, rk, .D decorates the destination operand rd, and .WU decorates the source operands rj and rk; this means that the multiplication is to multiply two unsigned words to obtain a double word result which will be written into rd. +For another example, in the instruction CRC.WBW rd, rj, rk, the first .W decorates rd, .B decorates rj, and the second .W decorates rk; this means that the CRC check operation is to use the byte message in rj and the 32-bit original check value in rk to generate a new 32-bit check value which will be written into rd.

+
+
+

Register operands distinguish register files by the first letter. +rN refers to general registers; fN refers to floating-point registers; vN refers to 128-bit vector registers; xN refers to 256-bit vector registers. +Among them, N is a number that represents the Nth register.

+
+
+
+

1.4. Conventions Used in this Manual

+
+

1.4.1. Instruction Abbreviation

+
+

There are many instructions defined by LoongArch that appear frequently and have similar behaviors. +Generally, they only have some differences in operands. +For the convenience of readers, such instructions are often introduced together. +For the sake of brevity, this manual uses abbreviation rules for the instruction name. +{A/B/C} means to use A, B, and C to combine the instruction name. +A[B] means to use A and AB to combine the instruction name. +For example, ADD.{W/D} represents two instruction names ADD.W and ADD.D, while BLT[U] represents two instruction names BLT and BLTU. +A more complicated example is ADD[I].{W/D}, which represents four instruction names ADD.W, ADD.D, ADDI.W and ADDI.D. +Even though instruction names can be abbreviated, it does not mean that their opcode fields have similar contents.

+
+
+
+

1.4.2. References to Control and Status Registers

+
+

LoongArch defines a series of Control and Status Registers (CSRs), which are used to control the execution behavior of instructions. +Each CSR usually contains several fields. +This manual use CSR.%%%%.#### to refer to the #### field of the control and status register whose name is abbreviated as %%%%. +For example, CSR.CRMD.PLV represents the PLV field in the CRMD register. +When the virtualization extension is implemented, there are two sets of CSRs in the processor, one belongs to the Host and the other belongs to the Guest. +If the two sets of CSRs cannot be distinguished by the context, CSR.XXXX is used to represent the CSRs of the Host and GCSR.XXXX is used to represent the CSRs of the Guest.

+
+
+
+
+

1.5. Version Evolution

+
+

The initial version of LoongArch is V1, denoted as LoongArch V1. The content of the standard is not specified in the LoongArch Reference Manual and belongs to LoongArch V1 by default. Since LoongArch V1, the subsequent evolution of LoongArch adopts the method of fine-grained incremental evolution. By "fine-grained" evolution, I mean that each subset of functionality in the base or extensions can evolve independently; By "incremental" I mean that a higher version is always compatible with the previous binary for any part that can be evolved independently. In order to more concisely reflect the stages of the above architecture evolution process, a number of new feature subset extensions added in a certain stage are collectively referred to as a new version extension. For example, the new hardware page table traversal support, byte/half-word atomic memory access instructions, and other additions to LoongArch V1 are collectively referred to as LoongArch V1.1. It should be pointed out that the subset of features added in each new version has its own identifier in the CPUCFG instruction return value. It is recommended that the software use this information rather than the version number of the Godson architecture to determine the supported features of the running processor. Architecture specifications do not require processor hardware to implement functions that directly reflect the supported architecture version number.

+
+
+

1.5.1. New In LoongArch V1.1

+
+

LoongArch V1.1 adds the following:

+
+
+
    +
  1. +

    New instructions for approximately solving floating-point root and inverse floating-point root, including FRECIPE.S, FRECIPE.D, FRSQRTE.S, FRSQRTE.D for scalar operations. VFRECIPE.S, VFRECIPE.D, VFRSQRTE.S, VFRSQRTE.D commands for 128-bit SIMD operations and XVFRECIPE.S, XVFRECIPE.D, XVFRSQRTE.S, XVFRSQRTE.D commands for 256-bit SIMD operations instructions.

    +
    2. +
  2. +

    Add SC.Q instruction.

    +
    3. +
  3. +

    Add LLACQ.W, SCREL.W, LLACQ.D, SCREL instructions.

    +
    4. +
  4. +

    Add AMCAS.B, AMCAS.H, AMCAS.W, AMCAS.D, AMCAS_DB.B, AMCAS_DB.H, AMCAS_DB.W, AMCAS_DB.D, AMSWAP.B, AMSWAP.H instructions.

    +
    5. +
  5. +

    Add AMADD.B, AMADD.H, AMSWAP_DB.B, AMSWAP_DB.H, AMADD_DB.B, AMADD_DB.H instructions.

    +
    6. +
  6. +

    Add the function definition of non-zero hint value in the dbar instruction part.

    +
    7. +
  7. +

    A new method for determining whether 32-bit integer division instructions on 64-bit machines are affected by the higher 32-bit value of the source operand register.

    +
    8. +
  8. +

    Standardize the way to determine the sequential execution behavior of load memory access operations at the same address.

    +
    9. +
  9. +

    Add the definition of a message interrupt.

    +
    10. +
  10. +

    Hardware page table traversals are allowed.

    +
    11. +
+
+
+
+
+
+
+

2. Basic Integer Instructions

+
+
+

According to the context of the software runtime, the non-privileged instruction set of the basic part of LoongArch includes basic integer instructions and basic floating-point instructions. +This chapter will describe the integer instruction part. +The basic integer instruction part is the most basic part of the non-privileged instruction subset.

+
+
+

2.1. Programming Model of Basic Integer Instruction

+
+

The basic integer instruction programming model described in this section only involves the operating environment of the application software, which is always related to some privileged resources. +Therefore, the concept of privileged resources will be introduced where necessary to ensure the completeness of the description. +Although the content of privileged resources is covered here, it will not be expanded in detail. +Readers who need a comprehensive and in-depth understanding can refer to the relevant chapters in the manual according to the prompts in the text.

+
+
+

2.1.1. Data Types

+
+

There are 5 data types operated by basic integer instructions, namely: bit (b), Byte (B, length 8b), Halfword (H, length 16b), Word (W, length 32b), Doubleword (D, length 64b). +In LA32, there are no integer instructions for operating doubleword. +Byte, half-word, word and double-word data types all use two’s complement encoding.

+
+
+
+

2.1.2. Registers

+
+

The registers involved in basic integer instructions include General Registers (GR) and Program Counters (PC), as shown in the figure.

+
+
+
+gr and pc +
+
Figure 2. GR and PC
+
+
+
2.1.2.1. General-purpose Registers
+
+

There are 32 General purpose Registers (GR), denoted as r0-r31, and the value of register r0 is always 0. +The length of GR is recorded as GRLEN. +The length of GR in LA32 is 32 bits, and the length of GR in LA64 is 64 bits. +There is an orthogonal relationship between basic integer instructions and general registers. +That is, from an architectural point of view, any register operand in this instruction can use any of the 32 GRs. +The only exception is that the destination register implicit in the BL instruction must be r1. +In the standard LoongArch Application Binary Interface (ABI), r1 is as storing the return address of a function call.

+
+
+
+
2.1.2.2. PC
+
+

There is only one PC, which records the address of the current instruction. +The PC register cannot be modified directly by instructions, it can only be modified indirectly by branch instructions, exception trap and exception return instructions. +However, the PC register can be directly read as the source operand of some non-branch instructions. +The length of PC is always the same as the length of GR.

+
+
+
+
+

2.1.3. Running Privilege Levels

+
+

LoongArch defines 4 running Privilege LeVels (PLV), namely PLV0-PLV3. +The specific privilege level of the application is determined by the system software at runtime, and the application cannot accurately aware this. +In LoongArch, the application usually runs on PLV3. +For more information about privilege levels, see Privilege Levels.

+
+
+
2.1.3.1. Privileged Resources Accessible by Applications
+
+

Generally speaking, privileged resources cannot be directly accessed by application running at a non-privileged level, but when RPCNTL1/RPCNTL2/RPCNTL3 in CSR.MISC is set, the CSRRD instruction can be executed at the privilege level of PLV1/PLV2/PLV3 to read performance monitor counters. +For more information about performance monitor counters, see Control and Status Registers Related to Performance Monitoring.

+
+
+
+
2.1.3.2. Disabling of Some Non-privileged Functions
+
+

Some non-privileged functions that are enabled by default after power-on reset can be disabled by the system software during execution. +By setting the DRDTL1/DRDTL2/DRDTL3 bits in CSR.MISC to 1, the execution of RDTIME instructions at the PLV1/PLV2/PLV3 level can be prohibited, or will trigger the Instruction Privilege error Exception (IPE).

+
+
+
+
+

2.1.4. Exceptions and interrupts

+
+

Exceptions and interrupts will interrupt the currently executing program and switch the control flow to the entry of the exception/interrupt handler to start execution. +Exceptions are caused by abnormal conditions that occur during the execution of the instruction, and interrupts are caused by external events (such as interrupt signal input). +In the manual, it will strictly distinguish the two concepts of “generating an exception/interrupt” and “triggering an exception/interrupt”. +The difference between the two is that the former does not necessarily cause a change in the control flow, while the latter must change the current control flow to an entry point of the exception/interrupt handler.

+
+
+

The handling specifications for exceptions and interrupts belong to the privileged resource handling part of the architecture. +Here is a brief introduction to the exceptions that the application can perceive.

+
+
+
    +
  • +

    SYStem call exception (SYS): the execution of the SYSCALL instruction will trigger the system call exception immediately.

    +
    • +
  • +

    BrEaKpoint exception (BEK): executing the BREAK instruction will trigger a breakpoint exception immediately.

    +
    • +
  • +

    Instruction Non-defined Exception (INE): if the executed instruction code is not defined in the architecture, or the architecture specification defines the instruction as not existing in the current context, then the instruction non-defined exception will be triggered immediately.

    +
    • +
  • +

    Instruction Privilege error Exception (IPE): in addition to the special circumstances listed in Running Privilege Levels, executing a privileged instruction in the application software will definitely trigger the instruction privilege level error exception immediately.

    +
    • +
  • +

    ADdress error Exception (ADE): when the program has a functional error that causes the address of the instruction fetch or memory access instruction to appear illegal (such as the instruction fetch address is not aligned on 4-byte boundaries, and the privileged address space is accessed), ADdress error Exception for Fetching instructions (ADEF) or ADdress error Exception for Memory access instructions (ADEM) will be triggered.

    +
    • +
  • +

    Floating-Point error Exception (FPE): when the floating-point number instruction is executed, special processing is required for data exceptions, which can generate or trigger the basic floating-point error exception. +See Floating-Point Move Instructions for more information.

    +
    • +
+
+
+
+

2.1.5. Memory Address Space

+
+

Only the virtual address space visible to the application is involved here. +The translation of virtual memory addresses to physical memory addresses is determined by the runtime environment. +These contents relate to the relevant specifications of privileged resources in the architecture and will be introduced in the second half of this manual. +The memory address space on LoongArch is a continuous linear address space, which is addressed in bytes.

+
+
+

In LA32, the specification of the memory address space that application can access is: 0-231-1.

+
+
+

In LA64, the range of memory address space accessible by application is: 0-2VALEN-1-1. +Generally VALEN is in the range of [40,48]. +Application can determine the specific value of VALEN by executing the CPUCFG instruction to read the VALEN field of the 0x1 configuration word.

+
+
+

When the virtual address of the instruction fetch or memory access instruction in the application exceeds the above range, ADEF or ADEM will be triggered.

+
+
+
+

2.1.6. Endian

+
+

LoongArch bit designations are always little-endian.

+
+
+
+

2.1.7. Memory Access Types

+
+

LoongArch supports three types of memory access: Coherent Cached (CC), Strongly-ordered UnCached (SUC) and Weakly-ordered UnCached (WUC). +The memory access type used for a location is associated with the virtual address, which is determined by the Memory Access Type field. +The relationship of the memory access type and MAT field is: 0 - SUC, 1 - CC, 2 - WUC, and 3 - reserved. +The memory access type setting process is transparent to the application.

+
+
+

When using consistent cacheable access type, the accessed object can be either the final memory object or the caches. +This type of access is usually used to access faster.

+
+
+

When using SUC or WUC access, the final memory object can only be directly accessed. +The difference between the two is: SUC access meets sequential consistency, that is, all accesses are executed in strict accordance with the order in the program and the next memory access operation cannot be started before the current memory access operation is completely completed. +While the WUC read access allows speculative execution, and WUC written data can be merged inside the processor core to a larger scale (such as a Cache line) and then written out in a burst mode. +Subsequent writes in the merge process can overwrite the data written earlier.

+
+
+

In LoongArch, only SUC memory access instructions must not have side effects, that is, such instructions cannot be predictive executed. +Software can use this feature to access I/O devices in the system through SUC type memory access instructions. +However, LoongArch allows SUC fetch instruction operations to have side effects. +This means that the access type is a SUC type of fetch instruction operation, even if it originates from the result of branch prediction, it is allowed to be executed. +In order to prevent the out-of-core memory access operations generated by such speculative execution from erroneously entering the illegal physical address space, it is necessary to filter out the risky accesses, This will be done on the chip.

+
+
+

The WUC type of access is usually used to accelerate the access to UC memory data, such as video memory data.

+
+
+
2.1.7.1. Cache Coherency Maintenance of Instruction Cache
+
+

The Cache coherency between the instruction Cache of a certain processor core and the Cache in other processor cores or Cache Coherenr I/O Master must be maintained by hardware.

+
+
+

The Cache coherency maintenance between the instruction Cache and the data Cache within the processor core can be implemented as hardware maintenance. +This means that for the self-modifying code, the software does not need to use the CACOP instruction to maintain the Cache coherency between the instruction Cache and the data Cache within the same core. +However, due to the pipeline structure and speculative instruction fetching behavior, the software still needs to use the IBAR instruction to ensure that the instruction fetching must be able to see the execution effect of the store instruction.

+
+
+
+
+

2.1.8. Unaligned Memory Access

+
+

The fetch addresses of all instruction fetches must be aligned on 4-byte boundaries, otherwise the ADEF will be triggered.

+
+
+

Except for atomic memory access instructions, integer bound check memory access instructions and floating-point bound check memory access instructions, other load/store memory access instructions can be implemented to allow memory access addresses to be unaligned. +However, in an implementation that allows memory access address misalignment, the system mode software can configure the ALCL0-ALCL3 control bits in CSR.MISC to address these load/store memory access instructions at the privilege levels of PLV0-PLV3. +Alignment check is needed, too. +For memory accessed instructions that require address alignment checks, if the address accessed is not naturally aligned, an Address aLignment fault Exception (ALE) will be triggered.

+
+
+
+

2.1.9. Overview of Memory Consistency

+
+

The memory consistency model of the LoongArch uses the Weak Consistency (WC) model. +This section only gives a brief description of the weak consistency model adopted by the architecture.

+
+
+

In the weak consistency model, synchronization operations need to be distinguished from ordinary memory accesses. +The programmer must use the synchronization operations defined by the architecture to protect the access to the write shared unit to ensure that multiple processor cores have access to the write shared unit mutually exclusive. +The following restrictions are imposed on the sequence of memory access events:

+
+
+
    +
  • +

    The execution of the synchronization operation satisfies the sequence consistency condition. +That is, synchronization operations are executed in all processor cores strictly in the order in which they appear in the program, and the next synchronization operation cannot be started until the current synchronization operation is completely completed.

    +
    • +
  • +

    Before any ordinary memory access operation is allowed to be executed, all synchronization operations prior to this memory access operation in the same processor core have been completed.

    +
    • +
  • +

    Before any synchronization operation is allowed to be executed, all ordinary memory access operations that precede this synchronization operation in the same processor have been completed.

    +
    • +
+
+
+

The instructions that can generate synchronous operations in LoongArch include DBAR, IBAR, AM atomic memory access instructions with DBAR function, and LL-SC instruction pairs.

+
+
+
+
+

2.2. Overview of Basic Integer Instructions

+
+

This section will describe the functions of application-level basic integer instructions in LA64. +For LA32, it only needs to implement a subset of them. +The instruction list contained in this subset is shown in the table. +Because the length of GR in LA32 is only 32 bits, the sign extension operation in “sign extend the 32-bit result into the general register rd” in the subsequent instruction description is not required.

+
+ + ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 2. Application-level basic integer instructions in LA32

Arithmetic operation instructions

ADD.W, SUB.W, ADDIW, ALSL.W, LU12L.W, SLT, SLTU, SLTI, SLTUI,

+

PCADDI, PCADDU12I, PCALAU12I,

+

AND, OR, NOR, XOR, ANDN, ORN, ANDI, ORI, XORI,

+

MUL.W, MULH.W, MULH.WU, DIV.W, MOD.W, DIV.WU, MOD.WU

Bit-shift instructions

SLL.W, SRL.W, SRA.W, ROTR.W, SLLI.W, SRLI.W, SRAI.W, ROTRI.W

Bit-manipulation instructions

EXT.W.B, EXT.W.H, CLO.W, CLZ.W, CTO.W, CTZ.W, BYTEPICK.W,

+

REVB.2H, BITREV.4B, BITREV.W, BSTRINS.W, BSTRPICK.W, MASKEQZ, MASKNEZ

Branch instructions

BEQ, BNE, BLT, BGE, BLTU, BGEU, BEQZ, BNEZ, B, BL, JIRL

Memory access instructions

LD.B, LD.H, LD.W, LD.BU, LD.HU, ST.B, ST.H, STW, PRELD

Atomic memory access instructions

LL.W, SC.W

Barrier instructions

DBAR, IBAR

Other instructions

SYSCALL, BREAK, RDTIMEL.W, RDTIMEH.W, CPUCFG

+
+

In addition, for those instructions whose data length of the operation object is GR length, the operation length is 32 bits in LA32 and 64 bits in LA64. +Unless there are special circumstances, no special instructions will be given in the instruction function description.

+
+
+

2.2.1. Arithmetic Operation Instructions

+
+
2.2.1.1. ADD.{W/D}, SUB.{W/D}
+
+

Instruction formats:

+
+
+
+
add.w   rd, rj, rk
+add.d   rd, rj, rk
+sub.w   rd, rj, rk
+sub.d   rd, rj, rk
+
+
+
+

The ADD.W instruction performs the operation that the [31:0] bit data in the general register rj plus the [31:0] bit data in the general register rk; the resultant [31:0] bit is sign extension, then written into the general register rd.

+
+
+
+
ADD.W:
+    tmp = GR[rj][31:0] + GR[rk][31:0]
+    GR[rd] = SignExtend(tmp[31:0],GRLEN)
+
+
+
+

The SUB.W instruction performs the operation that the [31:0] bit data in the general register rk minus the [31:0] bit data in the general register rj; the resultant [31:0] bit is sign extension, then written into the general register rd.

+
+
+
+
SUB.W:
+    tmp = GR[rj][31:0] - GR[rk][31:0]
+    GR[rd] = SignExtend(tmp[31:0], GRLEN)
+
+
+
+

The ADD.D instruction performs the operation that the [63:0] bit data in the general register rj plus the [63:0] bit data in the general register rk; the result is written into the general register rd.

+
+
+
+
ADD.D:
+    tmp = GR[rj][63:0] + GR[rk][63:0]
+    GR[rd] = tmp[63:0]
+
+
+
+

The SUB.D instruction performs the operation that the [63:0] bit data in the general register rj minus the [63:0] bit data in the general register rk; writes the result into the general register rd.

+
+
+
+
SUB.D:
+    tmp = GR[rj][63:0] - GR[rk][63:0]
+    GR[rd] = tmp[63:0]
+
+
+
+

When the above instructions are executed, no special handling will be done on overflow.

+
+
+
+
2.2.1.2. ADDI.{W/D}, ADDU16I.D
+
+

Instruction formats:

+
+
+
+
addi.w      rd, rj, si12
+addi.d      rd, rj, si12
+addu16i.d   rd, rj, si16
+
+
+
+

The ADDI.W instruction performs the operation that the [31:0] bit data in the general register rj plus the 12-bit immediate si12 sign extension 32-bit data; the resultant [31:0] bit is sign extension, then written into the general register rd.

+
+
+
+
ADDI.W:
+    tmp = GR[rj][31:0] + SignExtend(si12, 32)
+    GR[rd] = SignExtend(tmp[31:0], GRLEN)
+
+
+
+

The ADDI.D instruction performs the operation that the [63:0] bit data in the general register plus to the 64-bit data after 12-bit immediate si12 sign-extension; the result is written into the general register rd.

+
+
+
+
ADDI.D:
+    tmp = GR[rj][63:0] + SignExtend(si12, 64)
+    GR[rd] = tmp[63:0]
+
+
+
+

ADDU16I.D shifts the 16-bit immediate sil6 logic to the left by 16 bits and then sign extensions the resultant data, the result plus [63:0] bit data in the general register rj, and the result of the addition is written into the general register rd. +The ADDU16I.D instruction is used in conjunction with the LDPTR.W/D and STPTR.W/D instructions to accelerate GOT table-based access in position-independent codes.

+
+
+
+
ADDU16I.D:
+    tmp = GR[rj][63:0] + SignExtend({si16, 16'b0}, 64)
+    GR[rd] = tmp[63:0]
+
+
+
+

When the above instructions are executed, no special handling will be done on overflow.

+
+
+
+
2.2.1.3. ALSL.{W[U]/D}
+
+

Instruction formats:

+
+
+
+
alsl.w  rd, rj, rk, sa2
+alsl.d  rd, rj, rk, sa2
+alsl.wu rd, rj, rk, sa2
+
+
+
+

The ALSL.W instruction performs the operation that logical shift the [31:0] bit data in the general register rj to the left (sa2 + 1) and it plus the [31:0] bit data in the general register rk; then write the result into the general register rd after the sign extension.

+
+
+
+
ALSL.W:
+    tmp = (GR[rj][31:0] << (sa2+1)) + GR[rk][31:0]
+    GR[rd] = SignExtend(tmp[31:0], GRLEN)
+
+
+
+

ALSL.WU logical shift the [31:0] bit data in the general register rj to the left (sa2 + 1) bit and it plus the [31:0] bit data in the general register rk; then the result is [31:0] bit zero after expansion, write to general register rd.

+
+
+
+
ALSL.WU:
+    tmp = (GR[rj][31:0] << (sa2+1)) + GR[rk][31:0]
+    GR[rd] = ZeroExtend(tmp[31:0], GRLEN)
+
+
+
+

The ALSL.D instruction performs the operation that logical shift the [63:0] bit data in the general register rj (sa2 + 1) to the left and it plus the [63:0] bit data in the general register rk; then the result is written into the general register rd.

+
+
+
+
ALSL.D:
+    tmp = (GR[rj][63:0] << (sa2+1)) + GR[rk][63:0]
+    GR[rd] = tmp[63:0]
+
+
+
+

When the above instructions are executed, no special handling will be done on overflow.

+
+
+ + + + + +
+
Tip
+		 +
+

When writing assembly, you need to fill in the immediate field with the real shift value, i.e. (sa2+1), not the value in the immediate field of the instruction code.

+
+
+
+
+
+
2.2.1.4. LU12I.W, LU32I.D, LU52I.D
+
+

Instruction formats:

+
+
+
+
lu12i.w     rd, si20
+lu32i.d     rd, si20
+lu52i.d     rd, rj, si12
+
+
+
+

The LU12I.W instruction performs the operation that splice the 12-bit 0 behind the lowest bit of the 20-bit immediate si20, then writes it into the general register rd after sign extension.

+
+
+
+
LU12I.W:
+    GR[rd] = SignExtend({si20, 12'b0}, GRLEN)
+
+
+
+

The LU32I.D instruction performs the operation that splice the bit data [31:0] in the general register rd behind the lowest bit of the 20-bit immediate si20 sign extension data; then the result is written into the general register rd.

+
+
+
+
LU32I.D:
+    GR[rd] = {SignExtend(si20, 32), GR[rd][31:0]}
+
+
+
+

The LU52I.D instruction performs the operation that splice the [51:0] bit data in the general register rj behind the lowest bit of the 12-bit immediate sil2 sign extension data; then the result is written into the general register rd.

+
+
+
+
LU52I.D:
+    GR[rd] = {si12, GR[rj][51:0]}
+
+
+
+

When the above instructions are executed, no special handling will be done on overflow.

+
+
+
+
2.2.1.5. SLT[U]
+
+

Instruction formats:

+
+
+
+
    slt     rd, rj, rk
+    sltu    rd, rj, rk
+
+
+
+

The SLT instruction performs the operation that compares the data in the general register rj with the data in the general register rk as signed integers. +If the former is smaller than the latter, the value of the general register rd is set to 1, otherwise it is set to 0.

+
+
+
+
SLT:
+    GR[rd] = (signed(GR[rj]) < signed(GR[rk])) ? 1 : 0
+
+
+
+

The SLTU instruction performs the operation that compares the data in the general register rj with the data in the general register rk as unsigned integers. +If the former is less than the latter, the value of the general register rd is set to 1, otherwise it is set to 0.

+
+
+
+
SLTU:
+    GR[rd] = (unsigned(GR[rj]) < unsigned(GR[rk])) ? 1 : 0
+
+
+
+

The data length compared by SLT and SLTU is consistent with the length of the general register of the executing machine.

+
+
+
+
2.2.1.6. SLT[U]I
+
+

Instruction formats:

+
+
+
+
slti    rd, rj, si12
+sltui   rd, rj, si12
+
+
+
+

The SLTI instruction performs the operation that compares the data in the general register rj and the 12-bit immediate sil2 sign extension data as a signed integer for size comparison. +If the former is smaller than the latter, the value of the general register rd is set to 1, otherwise it is set to 0.

+
+
+
+
SLTI:
+    tmp = SignExtend(si12, GRLEN)
+    GR[rd] = (signed(GR[rj]) < signed(tmp)) ? 1 : 0
+
+
+
+

The SLTUI instruction performs the operation that compares the data in the general register rj and the 12-bit immediate sil2 sign extension data as an unsigned integer for size comparison. +If the former is smaller than the latter, the value of the general register rd is set to 1, otherwise it is set to 0.

+
+
+
+
SLTUI:
+    tmp = SignExtend(si12, GRLEN)
+    GR[rd] = (unsigned(GR[rj]) < unsigned(tmp)) ? 1 : 0
+
+
+
+

The data length compared by SLTI and SLTUI is consistent with the length of the general register of the executing machine. +Note that for SLTUI instructions, immediate data is still sign extended.

+
+
+
+
2.2.1.7. PCADDI, PCADDU121, PCADDU18l, PCALAU12I
+
+

Instruction formats:

+
+
+
+
pcaddi      rd, si20
+pcaddu12i   rd, si20
+pcaddu18i   rd, si20
+pcalau12i   rd, si20
+
+
+
+

The PCADDI instruction performs the operation that splice the 2 bit 0 behind the lowest bit of the 20-bit immediate data si20 and sign extension, the resultant data plus the PC of the instruction; then the result of the addition is written into the general register rd.

+
+
+
+
PCADDI:
+    GR[rd]= PC + SignExtend({si20, 2'b0}, GRLEN)
+
+
+
+

The PCADDU12I instruction performs the operation that splice the 12-bit 0 behind the lowest bit of the 20-bit immediate data si20 and signs extension, the resultant data plus the PC of the instruction; then the result of the addition is written into the general register rd.

+
+
+
+
PCADDU12I:
+    GR[rd] = PC + SignExtend({si20, 12'b0}, GRLEN)
+
+
+
+

The PCADDU18I instruction performs the operation that splice the 18-bit 0 behind the lowest bit of the 20-bit immediate si20 and signs extension, the resultant data plus the PC of the instruction; then the result of the addition is written into the general register rd.

+
+
+
+
PCADDU18I:
+    GR[rd] = PC + SignExtend({si20, 18'b0}, GRLEN)
+
+
+
+

The PCALAU12I instruction performs the operation that splice the 12-bit 0 behind the lowest bit of the 20-bit immediate data si20 and sign extension; the resultant data plus the PC of the instruction; then the lowest 12 bits of the addition result are erased and written into the general register rd.

+
+
+
+
PCALAU12I:
+    tmp = PC + SignExtend({si20, 12'b0}, GRLEN)
+    GR[rd] = {tmp[GRLEN-1:12], 12'b0}
+
+
+
+

The data length of the above instruction operation is consistent with the length of the general register of the executed machine.

+
+
+
+
2.2.1.8. AND, OR, NOR, XOR, ANDN, ORN
+
+

Instruction formats:

+
+
+
+
and     rd, rj, rk
+or      rd, rj, rk
+nor     rd, rj, rk
+xor     rd, rj, rk
+andn    rd, rj, rk
+orn     rd, rj, rk
+
+
+
+

The AND instruction performs the bitwise AND operation between the data in the general register rj and the data in the general register rk; then the result is written into the general register rd.

+
+
+
+
AND:
+    GR[rd] = GR[rj] & GR[rk]
+
+
+
+

The OR instruction performs the bitwise OR operation between the data in the general register rj and the data in the general register rk; then the result is written into the general register rd.

+
+
+
+
OR:
+    GR[rd] = GR[rj] | GR[rk]
+
+
+
+

The NOR instruction performs the bitwise OR operation between the data in the general register rj and the data in the general register rk; then the result is written into the general register rd.

+
+
+
+
NOR:
+    GR[rd] = ~(GR[rj] | GR[rk])
+
+
+
+

The XOR instruction performs the bitwise XOR operation between the data in the general register rj and the data in the general register rk; then the result is written into the general register rd.

+
+
+
+
XOR:
+    GR[rd] = GR[rj] ^ GR[rk]
+
+
+
+

The ANDN instruction performs the operation that reverses the data in the general register rk bit by bit, then performs the bitwise AND operation with the data in the general register rk and the data in the general register rj; then the result is written into the general register rd.

+
+
+
+
ANDN:
+    GR[rd] = GR[rj] & (~GR[rk])
+
+
+
+

The ORN instruction performs the operation that reverses the data in the general register rk bit by bit, then performs a bitwise OR operation with the data in the general register rk and the data in the general register rj, and the result is written into the general register rd.

+
+
+
+
ORN:
+    GR[rd] = GR[rj] | (~GR[rk])
+
+
+
+

The data length of the above instruction operation is consistent with the length of the general register of the executed machine.

+
+
+
+
2.2.1.9. ANDI, ORI, XORI
+
+

Instruction formats:

+
+
+
+
andi    rd, rj, ui12
+ori     rd, rj, ui12
+xori    rd, rj, ui12
+
+
+
+

The ANDI instruction performs the bitwise AND operation between the data in the general register rj and the 12-bit immediate zero extension data; then the result is written into the general register rd.

+
+
+
+
ANDI:
+    GR[rd] = GR[rj] & ZeroExtend(ui12, GRLEN)
+
+
+
+

The ORI instruction performs the bitwise OR operation between the data in the general register rj and the 12-bit immediate zero extension data; then the result is written into the general register rd.

+
+
+
+
ORI:
+    GR[rd] = GR[rj] | ZeroExtend(ui12, GRLEN)
+
+
+
+

The XORI instruction performs the bitwise XOR operation between the data in the general register rj and the 12-bit immediate zero extension data; then the result is written into the general register rd.

+
+
+
+
XORI:
+    GR[rd] = GR[rj] ^ ZeroExtend(ui12, GRLEN)
+
+
+
+

The data length of the above instruction operation is consistent with the length of the general register of the executed machine.

+
+
+
+
2.2.1.10. NOP
+
+

The NOP instruction is an alias for the instruction andi r0, r0, 0. +Its function is only to occupy the 4-byte instruction code position and increase the PC by 4, except that it will not change any other software-visible processor state.

+
+
+
+
2.2.1.11. MUL.{W/D}, MULH, {W[U]/D[U]}
+
+

Instruction formats:

+
+
+
+
mul.w       rd, rj, rk
+mulh.w      rd, rj, rk
+mulh.wu     rd, rj, rk
+mul.d       rd, rj, rk
+mulh.d      rd, rj, rk
+mulh.du     rd, rj, rk
+
+
+
+

The MUL.W instruction performs the operation that multiplies the [31:0] bit data in the general register rj with the [31:0] bit data in the general register rk, the result of the multiplication [31:0] bit data is signed and written into the general register rd.

+
+
+
+
MUL.W:
+    product = signed(GR[rj][31:0]) * signed(GR[rk][31:0])
+    GR[rd] = SignExtend(product[31:0], GRLEN)
+
+
+
+

The MULH.W instruction performs the operation that multiplies the [31:0] bit data in the general register rj with the [31:0] bit data in the general register rk as a signed number, the result of the multiplication [63:32] bit data is sign extension and written into the general register rd.

+
+
+
+
MULH.W:
+    product = signed(GR[rj][31:0]) * signed(GR[rk][31:0])
+    GR[rd] = SignExtend(product[63:32], GRLEN)
+
+
+
+

The MULH.WU instruction performs the operation that multiplies the [31:0] bit data in the general register rj with the [31:0] bit data in the general register rk as unsigned numbers, the result of the multiplication [63:32] bit data is sign extension and written into the general register rd.

+
+
+
+
MULH.WU:
+    product = unsigned(GR[rj][31:0]) * unsigned(GR[rk][31:0])
+    GR[rd] = SignExtend(product[63:32], GRLEN)
+
+
+
+

The MUL.D instruction performs the operation that multiplies the [63:0] bit data in the general register rj with the [63:0] bit data in the general register rk, the result of the multiplication [63:0] bit data and written into the general register rd.

+
+
+
+
MUL.D:
+    product = signed(GR[rj][63:0]) * signed(GR[rk][63:0])
+    GR[rd] = product[63:0]
+
+
+
+

The MULH.D instruction performs the operation that multiplies the [63:0] bit data in the general register rj with the [63:0] bit data in the general register rk as a signed number, the result of the multiplication [127:64] bit data and written into the general register rd.

+
+
+
+
MULH.D:
+    product = signed(GR[rj][63:0]) * signed(GR[rk][63:0])
+    GR[rd] = product[127:64]
+
+
+
+

The MULH.DU instruction performs the operation that multiplies the [63:0] bit data in the general register rj and the [63:0] bit data in the general register rk as unsigned numbers, the result of the multiplication [127:64] bit data and written into the general register rd.

+
+
+
+
MULH.DU:
+    product = unsigned(GR[rj][63:0]) * unsigned(GR[rk][63:0])
+    GR[rd] = product[127:64]
+
+
+
+
+
2.2.1.12. MULW.D.W[U]
+
+

Instruction formats:

+
+
+
+
    mulw.d.w    rd, rj, rk
+    mulw.d.wu   rd, rj, rk
+
+
+
+

The MULW.D.W instruction performs the operation that multiplies the [31:0] bit data in the general register rj with the [31:0] bit data in the general register rk as a signed number, and the 64-bit product result is written into the general register rd.

+
+
+
+
MULW.D.W:
+    product = signed(GR[rj][31:0]) * signed(GR[rk][31:0])
+    GR[rd] = product[63:0]
+
+
+
+

The MULW.D.WU instruction performs the operation that multiplies the [31:0] bit data in the general register rj with the [31:0] bit data in the general register rk as unsigned numbers, and writes the 64-bit product result into the general register rd.

+
+
+
+
MULW.D.WU:
+    product = unsigned(GR[rj][31:0]) * unsigned(GR[rk][31:0])
+    GR[rd] = product[63:0]
+
+
+
+
+
2.2.1.13. DIV.{W[U]/D[U]}, MOD.{W[U]/D[U]}
+
+

Instruction formats:

+
+
+
+
div.w       rd, rj, rk
+mod.w       rd, rj, rk
+div.wu      rd, rj, rk
+mod.wu      rd, rj, rk
+div.d       rd, rj, rk
+mod.d       rd, rj, rk
+div.du      rd, rj, rk
+mod.du      rd, rj, rk
+
+
+
+

The DIV.W and DIV.WU instruction performs the operation that divide the [31:0] bit data in the general register rj by the [31:0] bit data in the general register rk, and the resulting quotient is sign extension and written into the general register rd.

+
+
+
+
DIV.W:
+    quotient = signed(GR[rj][31:0]) / signed(GR[rk][31:0])
+    GR[rd] = SignExtend(quotient[31:0], GRLEN)
+
+DIV.WU:
+    quotient = unsigned(GR[rj][31:0]) / unsigned(GR[rk][31:0])
+    GR[rd] = SignExtend(quotient[31:0], GRLEN)
+
+
+
+

The MOD.W and MOD.WU instruction performs the operation that divide the [31:0] bit data in the general register rj by the [31:0] bit data in the general register rk, and the resulting remainder is sign extension and written into the general register rd.

+
+
+
+
MOD.W:
+    remainder = signed(GR[rj][31:0]) % signed(GR[rk][31:0])
+    GR[rd] = SignExtend(remainder[31:0], GRLEN)
+
+MOD.WU:
+    remainder = unsigned(GR[rj][31:0]) % unsigned(GR[rk][31:0])
+    GR[rd] = SignExtend(remainder[31:0], GRLEN)
+
+
+
+

The DIV.D and DIV.DU instruction performs the operation that divide the [63:0] bit data in the general register rj by the [63:0] bit data in the general register rk, and the resulting quotient sign extension and written into the general register rd.

+
+
+
+
DIV.D:
+    GR[rd] = signed(GR[rj][63:0]) / signed(GR[rk][63:0])
+
+DIV.DU:
+    GR[rd] = unsigned(GR[rj][63:0]) / unsigned(GR[rk][63:0])
+
+
+
+

The MOD.D and MOD.DU instruction performs the operation that divide the [63:0] bit data in the general register rj by the [63:0] bit data in the general register rk, and the resulting remainder is sign extension and written into the general register rd.

+
+
+
+
MOD.D:
+    GR[rd] = signed(GR[rj][63:0]) % signed(GR[rk][63:0])
+
+MOD.DU:
+    GR[rd] = unsigned(GR[rj][63:0]) % unsigned(GR[rk][63:0])
+
+
+
+

When DIV.W, MOD.W, DIV.D and MOD.D perform division operations, the operands are all regarded as signed numbers. +When DIV.WU, M0D.WU, DIV.DU and MOD.DU perform division operations, the source operands are all regarded as unsigned numbers.

+
+
+

Each pair of instructions for finding the quotient/remainder satisfies the result of DIV.W/MOD.W, DIV.WU/MOD.WU, DIV.D/MOD.D, DIV.DU/MOD.DU, the remainder and the dividend The sign is consistent and the absolute value of the remainder is less than the absolute value of the divisor.

+
+
+

When the divisor is 0, the result can be any value, but no exception will be triggered.

+
+
+
+
+

2.2.2. Bit-shift Instructions

+
+
2.2.2.1. SLL.W, SRL.W, SRA.W, ROTR.W
+
+

Instruction formats:

+
+
+
+
sll.w       rd, rj, rk
+srl.w       rd, rj, rk
+sra.w       rd, rj, rk
+rotr.w      rd, ri, rk
+
+
+
+

The SLL.W instruction performs the operation that logical left shifts the bit data of [31:0] in the general register rj, and writes the sign extension of the shift result into the general register rd.

+
+
+
+
SLL.W:
+    tmp = SLL(GR[rj][31:0], GR[rk][4:0])
+    GR[rd] = SignExtend(tmp[31:0], GRLEN)
+
+
+
+

The SRL.W instruction performs the operation that logical right shifts the bit data of [31:0] in the general register rj, and writes the sign extension of the shift result into the general register rd.

+
+
+
+
SRL.W:
+    tmp = SRL(GR[rj][31:0], GR[rk][4:0])
+    GR[rd] = SignExtend(tmp[31:0], GRLEN)
+
+
+
+

The SRA.W instruction performs the operation that arithmetical right shifts [31:0] bit data in the general register rj, and writes the sign extension of the shift result into the general register rd.

+
+
+
+
SRA.W:
+    tmp = SRA(GR[rj][31:0], GR[rk][4:0])
+    GR[rd] = SignExtend(tmp[31:0], GRLEN)
+
+
+
+

The ROTR.W instruction performs the operation that cyclical right shifts the [31:0] bit data in the general register rj, and writes the sign extension of the shift result into the general register rd.

+
+
+
+
ROTR.W:
+    tmp = ROTR(GR[rj][31:0], GR[rk][4:0])
+    GR[rd] = SignExtend(tmp[31:0], GRLEN)
+
+
+
+

The shift amount of the above-mentioned shift instruction is all [4:0] bit data in the general register rk, and is regarded as an unsigned number.

+
+
+
+
2.2.2.2. SLLI.W, SRLI.W, SRAI.W, ROTRI.W
+
+

Instruction formats:

+
+
+
+
sliw        rd, rj, ui5
+srli.w      rd, rj, ui5
+srai.w      rd, rj, ui5
+rotri.w     rd, rj, ui5
+
+
+
+

The SLLI.W instruction performs the operation that logical left shifts the [31:0] bit data in the general register rj, and writes the sign extension of the shift result into the general register rd.

+
+
+
+
SLLI.W:
+    tmp = SLL(GR[rj][31:0], ui5)
+    GR[rd] = SignExtend(tmp[31:0], GRLEN)
+
+
+
+

The SRLI.W instruction performs the operation that logical right shifts the [31:0] bit data in the general register rj to the right, and writes the sign extension of the shift result into the general register rd.

+
+
+
+
SRLI.W:
+    tmp = SRL(GR[rj][31:0], ui5)
+    GR[rd] = SignExtend(tmp[31:0], GRLEN)
+
+
+
+

The SRAI.W instruction performs the operation that arithmetical right shifts the bit data of [31:0] in the general register rj, and writes the sign extension of the shift result into the general register rd.

+
+
+
+
SRAI.W:
+    tmp = SRA(GR[rj][31:0], ui5)
+    GR[rd] = SignExtend(tmp[31:0], GRLEN)
+
+
+
+

The ROTRI.W instruction performs the operation that cyclical right shifts the [31:0] bit data in the general register rj, and the sign extension of the shift result is written into the general register rd.

+
+
+
+
ROTRI.W:
+    tmp = ROTR(GR[rj][31:0], ui5)
+    GR[rd] = SignExtend(tmp[31:0], GRLEN)
+
+
+
+

The shift amounts of the above shift instructions are all 5-bit unsigned immediate ui5 in the instruction code.

+
+
+
+
2.2.2.3. SLL.D, SRL.D, SRA.D, ROTR.D
+
+

Instruction formats:

+
+
+
+
sl.d        rd, rj, rk
+srl.d       rd, rj, rk
+sra.d       rd, rj, rk
+rotr.d      rd, rj, rk
+
+
+
+

The SLL.D instruction performs the operation that logical left shifts the bit data of [63:0] in the general register rj, and writes the sign extension of the shift result into the general register rd.

+
+
+
+
SLL.D:
+    GR[rd] = SLL(GR[rj][63:0], GR[rk][5:0])
+
+
+
+

The SRL.D instruction performs the operation that logical right shifts the bit data of [63:0] in the general register rj, and writes the sign extension of the shift result into the general register rd.

+
+
+
+
SRL.D:
+    GR[rd] = SRL(GR[rj][63:0], GR[rk][5:0])
+
+
+
+

The SRA.D instruction performs the operation that arithmetic right shifts the bit data of [63:0] in the general register rj, and writes the sign extension of the shift result into the general register rd.

+
+
+
+
SRA.D:
+    GR[rd] = SRA(GR[rj][63:0], GR[rk][5:0])
+
+
+
+

The ROTR.D instruction performs the operation that cyclical right shifts the bit data of [63:0] in the general register rj, and writes the sign extension of the shift result into the general register rd.

+
+
+
+
ROTR.D:
+    GR[rd] = ROTR(GR[rj][63:0], GR[rk][5:0])
+
+
+
+

The shift amount of the above-mentioned shift instruction is all [5:0] bit data in the general register rk, and is regarded as an unsigned number.

+
+
+
+
2.2.2.4. SLLI.D, SRLI.D, SRAI.D, ROTRI.D
+
+

Instruction formats:

+
+
+
+
slli.d      rd, rj, ui6
+srli.d      rd, rj, ui6
+srai.d      rd, rj, ui6
+rotri.d     rd, rj, ui6
+
+
+
+

The SLII.D instruction performs the operation that logicalleft shifts the bit data of [63:0] in the general register rj, and the sign extension of the shift result is written into the general register rd.

+
+
+
+
SLLI.D:
+    GR[rd] = SLL(GR[rj][63:0], ui6)
+
+
+
+

The SRLI.D instruction performs the operation that logical right shifts the bit data of [63:0] in the general register rj, and writes the sign extension of the shift result into the general register rd.

+
+
+
+
SRLI.D:
+    GR[rd] = SRL(GR[rj][63:0], ui6)
+
+
+
+

The SRAI.D instruction performs the operation that arithmetically right shifts the bit data of [63:0] in the general register rj, and writes the sign extension of the shift result into the general register rd.

+
+
+
+
SRAI.D:
+    GR[rd] = SRA(GR[rj][63:0], ui6)
+
+
+
+

The ROTRI.D instruction performs the operation that cyclical right shifts the [63:0] bit data in the general register rj, and the sign extension of the shift result is written into the general register rd.

+
+
+
+
ROTRI.D:
+    GR[rd] = ROTR(GR[rj][63:0], ui6)
+
+
+
+

The shift amount of the above-mentioned shift instruction is the 6-bit unsigned immediate ui6 in the instruction code.

+
+
+
+
+

2.2.3. Bit-manipulation Instructions

+
+
2.2.3.1. EXT.W{B/H}
+
+

Instruction formats:

+
+
+
+
ext.w.b     rd, rj
+ext.w.h     rd, rj
+
+
+
+

The EXT.W.B instruction performs the operation that will sign extension the bit data of [7:0] in the general register rj and write it into the general register rd.

+
+
+
+
EXT.W.B:
+    GR[rd] = SignExtend(GR[rj][7:0], GRLEN)
+
+
+
+

The EXT.W.H instruction performs the operation that will sign extension the bit data of [15:0] in the general register rj and write it into the general register rd.

+
+
+
+
EXT.W.H:
+    GR[rd] = SignExtend(GR[rj][15:0], GRLEN)
+
+
+
+
+
2.2.3.2. CL{O/Z}.{W/D}, CT{O/Z}.{W/D}
+
+

Instruction formats:

+
+
+
+
clo.w       rd, rj
+clo.d       rd, rj
+clz.w       rd, rj
+clz.d       rd, rj
+cto.w       rd, rj
+cto.d       rd, rj
+ctz.w       rd, rj
+ctz.d       rd, rj
+
+
+
+

The CLO.W instruction performs the operation that for the data of bit [31:0] in the general register rj, the number of continuous bits 1 is measured from bit 31 to bit 0, and the result is written into the universal register rd.

+
+
+
+
CLO.W:
+    GR[rd] = CLO(GR[rj][31:0])
+
+
+
+

The CLZ.W instruction performs the operation that for the data of bit [31:0] in the general register rj, the number of continuous bits 0 is measured from bit 31 to bit 0, and the result is written into the universal register rd.

+
+
+
+
CLZ.W:
+    GR[rd] = CLZ(GR[rj][31:0])
+
+
+
+

The CTO.W instruction performs the operation that for the data of bit [31:0] in the general register rj, the number of continuous bits 1 is measured from bit 0 to bit 31, and the result is written into the universal register rd.

+
+
+
+
CTO.W:
+    GR[rd] = CTO(GR[rj][31:0])
+
+
+
+

The CTZ.W instruction performs the operation that for the data of bit [31:0] in the general register rj, the number of continuous bits 0 is measured from bit 0 to bit 31, and the result is written into the universal register rd.

+
+
+
+
CTZ.W:
+    GR[rd] = CTZ(GR[rj][31:0])
+
+
+
+

The CLO.D instruction performs the operation that for the data of bit [63:0] in the general register rj, the number of continuous bits 1 is measured from bit 63 to bit 0, and the result is written into the universal register rd.

+
+
+
+
CLO.D:
+    GR[rd] = CL0(GR[rj][63:0])
+
+
+
+

The CLZ.D instruction performs the operation that for the data of bit [63:0] in the general register rj, the number of continuous bits 1 is measured from bit 0 to bit 63, and the result is written into the universal register rd.

+
+
+
+
CLZ.D:
+    GR[rd] = CLZ(GR[rj][63:0])
+
+
+
+

The CTO.D instruction performs the operation that for the data of bit [63:0] in the general register rj, the number of continuous bits 0 is measured from bit 0 to bit 63, and the result is written into the universal register rd.

+
+
+
+
CTO.D:
+    GR[rd] = CTO(GR[rj][63:0])
+
+
+
+

The CTZ.D instruction performs the operation that for the data of bit [63:0] in the general register rj, the number of continuous bits 0 is measured from bit 0 to bit 63, and the result is written into the universal register rd.

+
+
+
+
CTZ.D:
+    GR[rd] = CTZ(GR[rj][63:0])
+
+
+
+
+
2.2.3.3. BYTEPICK.{W/D}
+
+

Instruction formats:

+
+
+
+
bytepick.w  rd, rj, rk, sa2
+bytepick.d  rd, rj, rk, sa3
+
+
+
+

The BYTEPICK.W instruction performs the operation that splice [31:0] bits in the general register rj behind [31:0] bits in the general register rk, and intercepts 4 consecutive bytes starting from the leftmost sa2 byte, and writes the 32-bit bit string symbol into universal register rd after expansion.

+
+
+
+
BYTEPICK.W:
+    tmp = {GR[rk][8*(4-sa2):0], GR[rj][31:8*(4-sa2)]}
+    GR[rd] = SignExtend(tmp[31:0], GRLEN)
+
+
+
+

The BYTEPICK.D instruction performs the operation that splice [63:0] bits in the general register rj behind [63:0] bits in the general register rk, and intercepts 8 consecutive bytes starting from the leftmost sa3 byte, and writes the 64-bit bit string symbol into universal register rd after expansion.

+
+
+
+
BYTEPICK.D:
+    GR[rd] = {GR[rk][8*(8-sa3):0], GR[rj][63:8*(8-sa3)]}
+
+
+
+
+
2.2.3.4. REVB.{2H/4H/2W/D}
+
+

Instruction formats:

+
+
+
+
revb.2h     rd, rj
+revb.4h     rd, ri
+revb.2w     rd, rj
+revb.d      rd, rj
+
+
+
+

The REVB.2H instruction performs the operation that arranges the 2 bytes in the [15:0] bits in the general register rj in reverse order to form the [15:0] bits of the intermediate result, and reverses the 2 bytes in the [31:16] in the general register rj Arrange the [31:16] bits of the intermediate result, and write the 32-bit intermediate result sign extended to the general register rd.

+
+
+
+
REVB.2H:
+    tmp0 = {GR[rj][ 7: 0], GR[rj][15: 8]}
+    tmp1 = {GR[rj][23:16], GR[rj][31:24]}
+    GR[rd] = SignExtend({tmp1, tmp0}, GRLEN)
+
+
+
+

The REVB.4H instruction performs the operation that arranges the 2 bytes in the [15:0] bits of the general register rj in reverse order and writes them into the [15:0] bits of the general register rd, and writes 2 words in the [31:16] bits of the general register rj. +Write the sections in reverse order to bits [31:16] of the general register rd, and write the 2 bytes of bits [47:32] in the general register rj in reverse order to bits [47:32] of the general register rd. +The 2 bytes in the [63:48] bits in the register rj are written in the [63:48] bits in the general register rd in reverse order.

+
+
+
+
REVB.4H:
+    tmp0 = {GR[rj][ 7: 0], GR[rj][15: 8]}
+    tmp1 = {GR[rj][23:16], GR[rj][31:24]}
+    tmp2 = {GR[rj][39:32], GR[rj][47:40]}
+    tmp3 = {GR[rj][55:48], GR[rj][63:56]}
+    GR[rd] = {tmp3, tmp2, tmp1, tmp0}
+
+
+
+

The REVB.2W instruction performs the operation that writes the 4 bytes in the [31:0] bits of the general register rj into the [31:0] bits of the general register rd in reverse order, and writes 4 of the [63:32] bits in the general register rj. +Write the byte in reverse order to bits [63:32] of the general register rd.

+
+
+
+
REVB.2W:
+    tmp0 = {GR[rj][ 7: 0], GR[rj][15: 8], GR[rj][31:24], GR[rj][23:16]}
+    tmp1 = {GR[rj][39:32], GR[rj][47:40], GR[rj][55:48], GR[rj][63:56]}
+    GR[rd] = {tmp1, tmp0}
+
+
+
+

REVB.D writes the 8 bytes in the [63:0] bits in the general register rj into the general register rd in reverse order.

+
+
+
+
REVB.D:
+    GR[rd] = {GR[rj][ 7: 0], GR[rj][15: 8], GR[rj][31:24], GR[rj][23:16],
+            GR[rj][39:32], GR[rj][47:40], GR[rj][55:48], GR[rj][63:56]}
+
+
+
+
+
2.2.3.5. REVH.{2W/D}
+
+

Instruction formats:

+
+
+
+
revh.2w     rd, rj
+revh.d      rd, rj
+
+
+
+

The REVH.2W instruction performs the operation that writes two half-words in bit [31:0] of general purpose register rj into bit [31:0] of general purpose register rd, and two half-words in bit [63:32] of general purpose register rj into bit [63:32] of general purpose register rd.

+
+
+
+
REVH.2W:
+    tmp0 = {GR[rj][15: 0], GR[rj][31:16]}
+    tmp1 = {GR[rj][47:32], GR[rj][63:48]}
+    GR[rd] = {tmp1, tmp0}
+
+
+
+

The REVH.D instruction performs the operation that write four half-words in [63:0] bit of universal register rj in reverse order to universal register rd.

+
+
+
+
REVH.D:
+    GR[rd] = {GR[rj][15:0], GR[rj][31:16], GR[rj][47:32], GR[rj][63:48]}
+
+
+
+
+
2.2.3.6. BITREV.{4B/8B}
+
+

Instruction formats:

+
+
+
+
bitrev.4b   rd, rj
+bitrev.8b   rd, rj
+
+
+
+

The BITREV.4B instruction performs the operation that the [7:0] bit in general register rj is arranged in reverse order, the [15:8] bit in general register rj is arranged in reverse order, the [23:16] bit in general register rj is arranged in reverse order, and the [31:24] bit in general register rj is arranged in reverse order; the 32-bit intermediate result sign extension is written into general register rd in turn.

+
+
+
+
BITREV.4B:
+    bstr32[31:24] = BITREV(GR[rj][31:24])
+    bstr32[23:16] = BITREV(GR[rj][23:16])
+    bstr32[15: 8] = BITREV(GR[rj][15: 8])
+    bstr32[ 7: 0] = BITREV(GR[rj][ 7: 0])
+    GR[rd] = SignExtend(bstr32, GRLEN)
+
+
+
+

The BITREV.8B instruction performs the operation that the [7:0] bit in general register rj is arranged in reverse order, the [15:8] bit in general register rj is arranged in reverse order, the [23:16] bit in general register rj is arranged in reverse order, the [31:24] bit in general register rj is arranged in reverse order; the [39:32] bit in general register rj is arranged in reverse order; the [47:40] bit in general register rj is arranged in reverse order; the [55:48] bit in general register rj is arranged in reverse order; the [63:56] bit in general register rj is arranged in reverse order; the 32-bit intermediate result sign extension is written into general register rd in turn.

+
+
+
+
BITREV.8B:
+    GR[rd][63:56] = BITREV(GR[rj][63:56])
+    GR[rd][55:48] = BITREV(GR[rj][55:48])
+    GR[rd][47:40] = BITREV(GR[rj][47:40])
+    GR[rd][39:32] = BITREV(GR[rj][39:32])
+    GR[rd][31:24] = BITREV(GR[rj][31:24])
+    GR[rd][23:16] = BITREV(GR[rj][23:16])
+    GR[rd][15: 8] = BITREV(GR[rj][15: 8])
+    GR[rd][ 7: 0] = BITREV(GR[rj][ 7: 0])
+
+
+
+
+
2.2.3.7. BITREV.{W/D}
+
+

Instruction formats:

+
+
+
+
bitrev.w        rd, rj
+bitrev.d        rd, rj
+
+
+
+

The BITREV.W instruction performs the operation that the [31:0] bit in general register rj is arranged in reverse order; the 32-bit intermediate result sign extension is written into general register rd in turn.

+
+
+
+
BITREV.W:
+    bstr32[31:0] = BITREV(GR[rj][31:0])
+    GR[rd] = SignExtend(bstr32, GRLEN)
+
+
+
+

The BITREV.D instruction performs the operation that the [63:0] bit in general register rj is arranged in reverse order; the 32-bit intermediate result sign extension is written into general register rd in turn.

+
+
+
+
BITREV.D:
+    GR[rd] = BITREV(GR[rj][63:0])
+
+
+
+
+
2.2.3.8. BSTRINS.{W/D}
+
+

Instruction formats:

+
+
+
+
bstrins.w       rd, rj, msbw, lsbw
+bstrins.d       rd, rj, msbd, lsbd
+
+
+
+

The BSTRINS.W instruction performs the operation that replaces the [msbw:lsbw] bit in the lowest 32 bits of the general register rd with the [msbw-lsbw:0] bit in the general register rj, and the resulting 32-bit result is sign extension and written into the general register rd.

+
+
+
+
BSTRINS.W:
+    bstr32[31:msbw+1] = GR[rd][31: msbw+1]
+    bstr32[msbw:lsbw] = GR[rj][msbw-lsbw:0]
+    bstr32[lsbw-1:0] = GR[rd][lsbw-1:0]
+    GR[rd] = SignExtend(bstr32[31:0], GRLEN)
+
+
+
+

The BSTRINS.D instruction performs the operation that replaces the [msbd:lsbd] bit in the general register rd with the [msbd-lsbd:0] bit in the general register rj, and the rest of the general register rd remains unchanged.

+
+
+
+
BSTRINS.D:
+    GR[rd][63:msbd+1] = GR[rd][63:msbd+1]
+    GR[rd][msbd:lsbd] = GR[rj][msbd-lsbd:0]
+    GR[rd][lsbd-1:0] = GR[rd][lsbd-1:0]
+
+
+
+
+
2.2.3.9. BSTRPICK.{W/D}
+
+

Instruction formats:

+
+
+
+
bstrpick.w  rd, rj, msbw, lsbw
+bstrpick.d  rd, rj, msbd, lsbd
+
+
+
+

BSTRPICK.W extracts the [msbw:Isbw] bit in the general register rj and zero-extends it to 32 bits, and the formed 32-bit intermediate result is sign extension and written into the general register rd.

+
+
+
+
BSTRPICK.W:
+    bstr32[31:0] = ZeroExtend(GR[rj][msbw:lsbw], 32)
+    GR[rd] = SignExtend(bstr32[31:0], GRLEN)
+
+
+
+

BSTRPICK.D extracts the [msbd:Isbd] bit in the general register rj and zero-extends it to 64 bits and writes it into the general register rd.

+
+
+
+
BSTRPICK.D:
+    GR[rd] = ZeroExtend(GR[rj][msbd:lsbd], 64)
+
+
+
+
+
2.2.3.10. MASKEQZ, MASKNEZ
+
+

Instruction formats:

+
+
+
+
maskeqz     rd, rj, rk
+masknez     rd, rj, rk
+
+
+
+

MASKEQZ and MASKNEZ instructions perform conditional assignment operations. +When MASKEQZ is executed, if the value of the general register rk is equal to 0, the general register rd is set to 0, otherwise it is assigned to the value of the rj register.

+
+
+
+
MASKEQZ:
+    GR[rd] = (GR[rk] == 0) ? 0 : GR[rj]
+
+
+
+

When MASKNEZ is executed, if the value of the general register rk is not equal to 0, the general register rd is set to 0, otherwise it is assigned to the value of the rj register.

+
+
+
+
MASKNEZ:
+    GR[rd] = (GR[rk] != 0) ? 0 : GR[rj]
+
+
+
+
+
+

2.2.4. Branch Instructions

+
+
2.2.4.1. BEQ, BNE, BLT[U], BGE[U]
+
+

Instruction formats:

+
+
+
+
beq     rj, rd, offs16
+bne     rj, rd, offs16
+blt     rj, rd, offs16
+bge     rj, rd, offs16
+bltu    rj, rd, offs16
+bgeu    rj, rd, offs16
+
+
+
+

The BEQ instruction performs the operation that compares the values of general register rj and general register rd, if the two are equal, jump to the target address, otherwise it does not jump.

+
+
+
+
BEQ:
+    if GR[rj] == GR[rd]:
+        PC = PC + SignExtend({offs16, 2'b0}, GRLEN)
+
+
+
+

The BNE instruction performs the operation that compares the values of general register rj and general register rd, if the two are not equal, jump to the target address, otherwise it does not jump.

+
+
+
+
BNE:
+    if GR[rj] != GR[rd]:
+        PC = PC + SignExtend({offs16, 2'b0}, GRLEN)
+
+
+
+

The BLT instruction performs the operation that compares the values of general register rj and general register rd as signed numbers. +If the former is smaller than the latter, it jumps to the target address, otherwise it does not jump.

+
+
+
+
BLT:
+    if signed(GR[rj]) < signed(GR[rd]):
+        PC = PC + SignExtend({offs16, 2'b0}, GRLEN)
+
+
+
+

The BGE instruction performs the operation that compares the values of general register rj and general register rd as signed numbers. +If the former is greater than or equal to the latter, it jumps to the target address, otherwise it does not jump.

+
+
+
+
BGE:
+    if signed(GR[rj]) >= signed(GR[rd]):
+        PC = PC + SignExtend({offs16, 2'b0}, GRLEN)
+
+
+
+

The BLTU instruction performs the operation that compares the values of general register rj and general register rd as unsigned numbers. +If the former is less than the latter, it jumps to the target address, otherwise it does not jump.

+
+
+
+
BLTU:
+    if unsigned(GR[rj]) < unsigned(GR[rd]):
+        PC = PC + SignExtend({offs16, 2'b0}, GRLEN)
+
+
+
+

The BGEU instruction performs the operation that compares the values of general register rj and general register rd as unsigned numbers. +If the former is greater than or equal to the latter, it jumps to the target address, otherwise it does not jump.

+
+
+
+
BGEU:
+    if unsigned(GR[rj]) >= unsigned(GR[rd]):
+        PC = PC + SignExtend({offs16, 2'b0}, GRLEN)
+
+
+
+

The calculation method of the jump target address of the above-mentioned six branch instructions is to logically shift the 16-bit immediate offs16 in the instruction code by 2 bits and then sign expand, and the resulting offset value is added to the PC of the branch instruction.

+
+
+ + + + + +
+
Tip
+		 +
+

When writing assembly, you need to fill in the immediate field with the real offset value in bytes, i.e. (offs16<<2).

+
+
+
+
+
+
2.2.4.2. BEQZ, BNEZ
+
+

Instruction formats:

+
+
+
+
beqz        rj, offs21
+bnez        rj, offs21
+
+
+
+

The BEQZ instruction performs the operation that judges the value of the general register rj, if it is equal to 0, jump to the target address, otherwise it does not jump.

+
+
+
+
BEQZ:
+    if GR[rj] == 0:
+        PC = PC + SignExtend({offs21, 2'b0}, GRLEN)
+
+
+
+

The BNEZ instruction performs the operation that judges the value of the general register rj, if it is not equal to 0, it jumps to the target address, otherwise it does not jump.

+
+
+
+
BNEZ:
+    if GR[rj] != 0:
+        PC = PC + SignExtend({offs21, 2'b0}, GRLEN)
+
+
+
+

The jump target address of the above two branch instructions is to logical left shift the 21-bit immediate offs21 in the instruction code by 2 bits and then sign extension, and the resulting offset value is added to the PC of the branch instruction.

+
+
+ + + + + +
+
Tip
+		 +
+

When writing assembly, you need to fill in the immediate field with the real offset value in bytes, i.e. (offs21<<2).

+
+
+
+
+
+
2.2.4.3. B
+
+

Instruction formats:

+
+
+
+
b       offs26
+
+
+
+

The B instruction performs the operation that jumps to the target address unconditionally. +The jump target address is to logical left shift the 26-bit immediate offs26 in the instruction code by 2 bits and then sign extension, and the resulting offset value is added to the PC of the branch instruction.

+
+
+
+
B:
+    PC = PC + SignExtend({offs26, 2' b0}, GRLEN)
+
+
+
+ + + + + +
+
Tip
+		 +
+

When writing assembly, you need to fill in the immediate field with the real offset value in bytes, i.e. (offs26<<2).

+
+
+
+
+
+
2.2.4.4. BL
+
+

Instruction formats:

+
+
+
+
bl      offs26
+
+
+
+

The BL instruction performs the operation that jumps to the target address unconditionally, and writes the result of adding 4 to the PC value of the instruction into the No.1 general register r1.

+
+
+

The jump target address of the instruction is to shift the 26-bit immediate offs26 in the instruction code to the left by 2 bits and then sign extend it. +The shift value is added to the PC of the branch instruction.

+
+
+
+
BL:
+    GR[1] = PC + 4
+    PC = PC + SignExtend({offs26, 2'b0}, GRLEN)
+
+
+
+

In LA ABI, the No.1 general register r1 serves as the return address register ra.

+
+
+ + + + + +
+
Tip
+		 +
+

When writing assembly, you need to fill in the immediate field with the real offset value in bytes, i.e. (offs26<<2).

+
+
+
+
+
+
2.2.4.5. JIRL
+
+

Instruction formats:

+
+
+
+
jirl        rd, rj, offs16
+
+
+
+

JIRL jumps to the target address unconditionally, and the PC value of the instruction plus 4; then writes the result into the general register rd.

+
+
+

The jump target address of the instruction is to logically shift the 16-bit immediate offs16 in the instruction code by 2 bits to the left and then sign extension, and the resulting offset value is added to the value in the general register rj.

+
+
+
+
JIRL:
+    GR[rd] = PC + 4
+    PC = GR[rj] + SignExtend({offs16, 2'b0}, GRLEN)
+
+
+
+

When rd is equal to 0, the function of JIRL is a common non-call indirect jump instruction.

+
+
+

JIRL with rd equal to 0, rj equal to 1 and offs16 equal to 0 is often used as an indirect jump from call return.

+
+
+ + + + + +
+
Tip
+		 +
+

When writing assembly, you need to fill in the immediate field with the real offset value in bytes, i.e. (offs16<<2).

+
+
+
+
+
+
+

2.2.5. Common Memory Access Instructions

+
+
2.2.5.1. LD.{B[U]/H[U]/W[U]/D}, ST.{B/H/W/D}
+
+

Instruction formats:

+
+
+
+
ld.b        rd, rj, si12
+ld.h        rd, rj, si12
+ld.w        rd, rj, si12
+ld.d        rd, rj, si12
+ld.bu       rd, rj, si12
+ld.hu       rd, rj, si12
+ld.wu       rd, rj, si12
+st.b        rd, rj, si12
+st.h        rd, rj, si12
+st.w        rd, rj, si12
+st.d        rd, rj, si12
+
+
+
+

LD.{B/H/W/D} retrieves the data of one byte/halfword/word/double word from the internal sign extension and writes it into the general register rd.

+
+
+
+
LD.B:
+    vaddr = GR[rj] + SignExtend(si12, GRLEN)
+    AddressComplianceCheck(vaddr)
+    paddr = AddressTranslation(vaddr)
+    byte = MemoryLoad(paddr, BYTE)
+    GR[rd] = SignExtend(byte, GRLEN)
+
+LD.H:
+    vaddr = GR[rj] + SignExtend(si12, GRLEN)
+    AddressComplianceCheck(vaddr)
+    paddr = AddressTranslation(vaddr)
+    halfword = MemoryLoad(paddr, HALFWORD)
+    GR[rd] = SignExtend(halfword, GRLEN)
+
+LD.W:
+    vaddr = GR[rj] + SignExtend(si12, GRLEN)
+    AddressComplianceCheck(vaddr)
+    paddr = AddressTranslation(vaddr)
+    word = MemoryLoad(paddr, WORD)
+    GR[rd] = SignExtend(word, GRLEN)
+
+LD.D:
+    vaddr = GR[rj] + SignExtend(si12, GRLEN)
+    AddressComplianceCheck(vaddr)
+    paddr = AddressTranslation(vaddr)
+    GR[rd] = MemoryLoad(paddr, DOUBLEWORD)
+
+
+
+

LD.{BU/HU/WU} retrieves one byte/halfword/word data from the memory and writes it into the general register rd after zero extension.

+
+
+
+
LD.BU:
+    vaddr = GR[rj] + SignExtend(si12, GRLEN)
+    AddressComplianceCheck(vaddr)
+    paddr = AddressTranslation(vaddr)
+    byte = MemoryLoad(paddr, BYTE)
+    GR[rd] = ZeroExtend(byte, GRLEN)
+
+LD.HU:
+    vaddr = GR[rj] + SignExtend(si12, GRLEN)
+    AddressCompli anceCheck(vaddr)
+    paddr = AddressTranslation(vaddr)
+    halfword = MemoryLoad(paddr, HALFWORD)
+    GR[rd] = ZeroExtend(halfword, GRLEN)
+
+LD.WU:
+    vaddr = GR[rj] + SignExtend(si12, GRLEN)
+    AddressComplianceCheck(vaddr)
+    paddr = AddressTranslation(vaddr)
+    word = MemoryLoad(paddr, WORD)
+    GR[rd] = ZeroExtend(word, GRLEN)
+
+
+
+

ST.{B/H/W/D} writes [7:0]/[15:0]/[31:0]/[63:0] bit data in general register rd into the memory.

+
+
+
+
ST.B:
+    vaddr = GR[rj] + SignExtend(si12, GRLEN)
+    AddressComplianceCheck(vaddr)
+    paddr = AddressTranslation(vaddr)
+    MemoryStore(GR[rd][7:0], paddr, BYTE)
+
+ST.H:
+    vaddr = GR[rj] + SignExtend(si12, GRLEN)
+    AddressComplianceCheck(vaddr)
+    paddr = AddressTranslation(vaddr)
+    MemoryStore(GR[rd][15:0], paddr, HALFWORD)
+
+ST.W:
+    vaddr = GR[rj] + SignExtend(si12, GRLEN)
+    AddressComplianceCheck(vaddr)
+    paddr = AddressTranslation(vaddr)
+    MemoryStore(GR[rd][31:0], paddr, WORD)
+
+ST.D:
+    vaddr = GR[rj] + SignExtend(si12, GRLEN)
+    AddressComplianceCheck(vaddr)
+    paddr = AddressTranslation(vaddr)
+    MemoryStore(GR[rd][63:0], paddr, DOUBLEWORD)
+
+
+
+

The memory access address calculation method of the above instruction is sum the value in the general register rj and the sign extension 12-bit immediate value sil2.

+
+
+

For LD.{H[U]/W[U]/D} and ST.{B/H/W/D} instructions, no matter what kind of hardware implementation and environmental configuration, as long as their memory access addresses are naturally aligned When the memory access address is not naturally aligned, if the hardware implementation supports non-aligned memory access and the current computing environment is configured to allow non-aligned memory access, then the non-aligned exception will not be triggered, otherwise a non-aligned exception will be triggered.

+
+
+
+
2.2.5.2. LDX.{B[U]/H[U]/W[U]/D}, STX.{B/H/W/D}
+
+

Instruction formats:

+
+
+
+
ldx.b       rd, rj, rk
+ldx.h       rd, rj, rk
+ldx.w       rd, rj, rk
+ldx.d       rd, rj, rk
+ldx.bu      rd, rj, rk
+ldx.hu      rd, rj, rk
+ldx.wu      rd, rj, rk
+stx.b       rd, rj, rk
+stx.h       rd, rj, rk
+stx.w       rd, rj, rk
+sbx.d       rd, rj, rk
+
+
+
+

LDX.{B/H/W/D} retrieves the data of one byte/halfword/word/double word from the internal sign extension and writes it into the general register rd.

+
+
+
+
LDX.B:
+    vaddr = GR[rj] + GR[rk]
+    AddressComplianceCheck(vaddr)
+    paddr = AddressTranslation(vaddr)
+    byte = MemoryLoad(paddr, BYTE)
+    GR[rd] = SignExtend(byte, GRLEN)
+
+LDX.H:
+    vaddr = GR[rj] + GR[rk]
+    AddressComplianceCheck(vaddr)
+    paddr = AddressTranslation(vaddr)
+    halfword = MemoryLoad(paddr, HALFWORD)
+    GR[rd] = SignExtend(halfword, GRLEN)
+
+LDX.W:
+    vaddr = GR[rj] + GR[rk]
+    AddressComplianceCheck(vaddr)
+    paddr = AddressTranslation(vaddr)
+    word = MemoryLoad(paddr, WORD)
+    GR[rd] = SignExtend(word, GRLEN)
+
+LDX.D:
+    vaddr = GR[rj] + GR[rk]
+    AddressComplianceCheck(vaddr)
+    paddr = AddressTranslation(vaddr)
+    GR[rd] = MemoryLoad(paddr, DOUBLEWORD)
+
+
+
+

LDX.{BU/HU/WU} retrieves one byte/halfword/word data from the internal zero extension and writes it into the general register rd.

+
+
+
+
LDX.BU:
+    vaddr = GR[rj] + GR[rk]
+    AddressComplianceCheck(vaddr)
+    paddr = AddressTranslation(vaddr)
+    byte = MemoryLoad(paddr, BYTE)
+    GR[rd] = ZeroExtend(byte, GRLEN)
+
+LDX.HU:
+    vaddr = GR[rj] + GR[rk]
+    AddressComplianceCheck(vaddr)
+    paddr = AddressTranslation(vaddr)
+    halfword = MemoryLoad(paddr, HALFWORD)
+    GR[rd] = ZeroExtend(halfword, GRLEN)
+
+LDX.WU:
+    vaddr = GR[rj] + GR[rk]
+    AddressCompli anceCheck(vaddr)
+    paddr = AddressTranslation(vaddr)
+    word = MemoryLoad(paddr, WORD)
+    GR[rd] = ZeroExtend(word, GRLEN)
+
+
+
+

STX.{B/H/W/D} writes [7:0], [15:0], [31:0] and [63:0] bits of data in the general register rd into the memory.

+
+
+
+
STX.B:
+    vaddr = GR[rj] + GR[rk]
+    AddressComplianceCheck(vaddr)
+    paddr = AddressTranslation(vaddr)
+    MemoryStore(GR[rd][7:0], paddr, BYTE)
+
+STX.H:
+    vaddr = GR[rj] + GR[rk]
+    AddressComplianceCheck(vaddr)
+    paddr = AddressTranslation(vaddr)
+    MemoryStore(GR[rd][15:0], paddr, HALFWORD)
+
+STX.W:
+    vaddr = GR[rj] + GR[rk]
+    AddressCompli anceCheck(vaddr)
+    paddr = AddressTranslation(vaddr)
+    MemoryStore(GR[rd][31:0], paddr, WORD)
+
+STX.D:
+    vaddr = GR[rj] + GR[rk]
+    AddressComplianceCheck(vaddr)
+    paddr = AddressTranslation(vaddr)
+    MemoryStore(GR[rd][63:0], paddr, DOUBLEWORD)
+
+
+
+

The memory access address calculation method of the above instruction is the value in the general register rj and the value in the general register rk. +For LDX.{H[U]/W[U]/D} and STX.{B/H/W/D} instructions, no matter what kind of hardware implementation and environment configuration, as long as its memory access address is natural Aligned, will not trigger non-aligned exception; when the fetch address is not naturally aligned, if the hardware implementation supports non-aligned memory access and the current computing environment is configured to allow non-aligned memory access, then the non-aligned exception will not be triggered, otherwise a non-aligned exception will be triggered.

+
+
+
+
2.2.5.3. LDPTR.{W/D}, STPTR.{W/D}
+
+

Instruction formats:

+
+
+
+
ldptr.w     rd, rj, si14
+ldptr.d     rd, rj, si14
+stptr.w     rd, rj, si14
+stptr.d     rd, rj, si14
+
+
+
+

LDPTR.{W/D} retrieves the data of a word/double word from the internal sign extension and writes it into the general register rd.

+
+
+
+
LDPTR.W:
+    vaddr = GR[rj] + SignExtend({si14, 2'b0}, GRLEN)
+    AddressComplianceCheck(vaddr)
+    paddr = AddressTranslation(vaddr)
+    word = MemoryLoad(paddr, WORD)
+    GR[rd] = SignExtend(word, GRLEN)
+
+LDPTR.D:
+    vaddr = GR[rj] + SignExtend({si14, 2'b0}, GRLEN)
+    AddressComplianceCheck(vaddr)
+    paddr = AddressTranslation(vaddr)
+    GR[rd] = MemoryLoad(paddr, DOUBLEWORD)
+
+
+
+

STPTR.{W/D} Write the data of bits [31:0]/[63:0] in the general register rd into the memory.

+
+
+
+
STPTR.W:
+    vaddr = GR[rj] + SignExtend({si14, 2'b0}, GRLEN)
+    AddressComplianceCheck(vaddr)
+    paddr = AddressTranslation(vaddr)
+    MemoryStore(GR[rd][31:0], paddr, WORD)
+
+STPTR.D:
+    vaddr = GR[rj] + SignExtend({si14, 2'b0}, GRLEN)
+    AddressComplianceCheck(vaddr)
+    paddr = AddressTranslation(vaddr)
+    MemoryStore(GR[rd][63:0], paddr, DOUBLEWORD)
+
+
+
+

The memory access address calculation method of the above instruction is to logical left shift the 14-bit immediate data si14 by 2 bits, sign extension, and then sum the value in the general register rj.

+
+
+ + + + + +
+
Tip
+		 +
+

When writing assembly, you need to fill in the immediate field with the real offset value in bytes, i.e. (si14<<2).

+
+
+
+
+

For LDPTR.{W/D} and STPTR.{W/D} instructions, no matter what kind of hardware implementation and environmental configuration, as long as the memory access address is naturally aligned, the non-aligned exception will not be triggered; when the memory address is not naturally aligned, if the hardware implementation supports unaligned memory access and the current computing environment is configured to allow unaligned memory access, then the unaligned exception will not be triggered, otherwise it will trigger the unaligned exception.

+
+
+

LDPTR.{W/D}, STPTR.{W/D} instructions are used in conjunction with ADDU16I.D instructions to accelerate GOT table-based access in position-independent codes.

+
+
+
+
2.2.5.4. PRELD
+
+

Instruction formats:

+
+
+
+
preld       hint, rj, si12
+
+
+
+

PRELD Reads a cache-line of data from memory in advance into the Cache. +The access address is the 12bit immediate number of the value in the general register rj plus the symbol extension.

+
+
+

The processor learns from the hint in the PRELD instruction what type will be acquired and which level of Cache the data to be taken back fill in, hint has 32 optional values (0 to 31), 0 represents load to level 1 Cache, and 8 represents store to level 1 Cache. +The remaining hint values are not defined and are processed for nop instructions when the processor executes.

+
+
+

If the Cache attribute of the access address of the PRELD instruction is not cached, then the instruction cannot generate a memory access action and is treated as a NOP instruction. +The PRELD instruction will not trigger any exceptions related to MMU or address.

+
+
+
+
2.2.5.5. PRELDX
+
+

Instruction formats:

+
+
+
+
preldx      hint, rj, rk
+
+
+
+

The PRELDX instruction continuously prefetches data from memory into the Cache according to the configuration parameters, and the continuously prefetched data is a block (block) of length block_size starting from the specified base address (base) with a number of (block_num) spacing stride. +The base address is the sum of the [63:0] bits in the general register rj and the sign extension [15:0] bits in the general register rk. +The [I16] bits in general register rk are the address sequence ascending and descending flag bits, with 0 indicating address ascending and 1 indicating address descending. +The value of bits [25:20] in general register rk is block_size, the basic unit of block_size is 16 bytes, so the maximum length of a single block is 1KB. +The value of bits [39:32] in general register rk is block_num-1, so a single instruction can prefetch up to 256 blocks. +The value of bits [59:44] in the block general register rk is treated as a signed number and defines the stride between adjacent blocks, the basic unit of stride is 1 byte. +The value of bits [39:32] in rk is block.num-1, so a single instruction can prefetch up to 256 blocks. +The value of bits [59:44] in general register rk is regarded as a signed number, which defines the corresponding The basic unit of stride and stride between adjacent blocks is 1 byte.

+
+
+

hint in the PRELDX instruction indicates the type of prefetch and the level of Cache into which the fetched data is to be filled. +hint has 32 selectable values from 0 to 31. +Currently, hint=0 is defined as load prefetch to level 1 data Cache, hint=2 is defined as load prefetch to level 3 Cache, hint-8 is defined as store prefetch to level 1 data Cache. +The meaning of the rest of hint values is not defined yet, and the processor executes it as NOP instruction.

+
+
+

If the Cache attribute of the access address of the PRELDX instruction is not cached, then the instruction cannot generate a memory access action and is treated as a NOP instruction.

+
+
+

The PRELDX instruction does not trigger any exceptions related to MMU or address.

+
+
+
+
+

2.2.6. Bound Check Memory Access Instructions

+
+
2.2.6.1. LD{GT/LE}.{B/H/W/D}, ST{GT/LE}.{B/H/W/D}
+
+

Instruction formats:

+
+
+
+
ldgt.b      rd, rj, rk
+ldgt.h      rd, rj, rk
+ldgt.w      rd, rj, rk
+ldgt.d      rd, rj, rk
+ldle.b      rd, rj, rk
+ldle.h      rd, rj, rk
+ldle.w      rd, rj, rk
+ldle.d      rd, rj, rk
+stgt.b      rd, rj, rk
+stgt.h      rd, rj, rk
+stgt.w      rd, rj, rk
+stgt.d      rd, rj, rk
+stle.b      rd, rj, rk
+stle.h      rd, rj, rk
+stle.w      rd, rj, rk
+stle.d      rd, rj, rk
+
+
+
+

LDGT/LDLE.B/H/W/D fetches a byte/half word word/double word data symbol extension from memory and writes it to the general register rd.

+
+
+

STGT/STLE.B/H/W/D writes the [7:0]/[15:0]/[31:0]/[63:0] bits of data from the general register rd to memory.

+
+
+

The access addresses of the above instructions come directly from the values in the general register rj. +The access addresses of the above instructions are required to be naturally aligned, otherwise a non-alignment exception will be triggered.

+
+
+

B/H/W/D and STGT.B/H/W/D instructions check whether the value in general register rj is greater than the value in general register rk, and terminate the access operation and trigger the bound check exception if the condition is not satisfied; B/H/W/D and STLE.B/H/W/D instructions check whether the value in general register rj is less than or equal to the value in general register rk, and if the condition is not satisfied, the access operation is terminated and the bound check exception is triggered.

+
+
+
+
LDGT.B:
+    vaddr = GR[rj]
+    AddressComplianceCheck(vaddr)
+    paddr = AddressTranslation(vaddr)
+    if GR[rj] > GR[rk]:
+        byte = MemoryLoad(paddr, BYTE)
+        GR[rd] = SignExtend(byte, GRLEN)
+    else:
+        RaiseException(BCE)    # Bound Check Exception
+
+LDGT.H:
+    vaddr = GR[rj]
+    AddressComplianceCheck(vaddr)
+    paddr = AddressTranslation(vaddr)
+    if GR[rj] > GR[rk]:
+        halfword = MemoryLoad(paddr, HALFWORD)
+        GR[rd] = SignExtend(halfword, GRLEN)
+    else:
+        RaiseException(BCE)    # Bound Check Exception
+
+LDGT.W:
+    vaddr = GR[rj]
+    AddressComplianceCheck(vaddr)
+    paddr = AddressTranslation(vaddr)
+    if GR[rj] > GR[rk]:
+        word = MemoryLoad(paddr, WORD)
+        GR[rd] = SignExtend(word, GRLEN)
+    else:
+        RaiseException(BCE)    # Bound Check Exception
+
+LDGT.D:
+    vaddr = GR[rj]
+    AddressComplianceCheck(vaddr)
+    paddr = AddressTranslation(vaddr)
+    if GR[rj] > GR[rk]:
+        GR[rd] = MemoryLoad(paddr, DOUBLEWORD)
+    else:
+        RaiseException(BCE)    # Bound Check Exception
+
+LDLE.B:
+    vaddr = GR[rj]
+    AddressComplianceCheck(vaddr)
+    paddr = AddressTranslation(vaddr)
+    if GR[rj] <= GR[rk]:
+        byte = MemoryLoad(paddr, BYTE)
+        GR[rd] = SignExtend(byte, GRLEN)
+    else:
+        RaiseException(BCE)    # Bound Check Exception
+
+LDLE.H:
+    vaddr = GR[rj]
+    AddressComplianceCheck(vaddr)
+    paddr = AddressTranslation(vaddr)
+    if GR[rj] <= GR[rk]:
+        halfword = MemoryLoad(paddr, HALFWORD)
+        GR[rd] = SignExtend(halfword, GRLEN)
+    else:
+        RaiseException(BCE)    # Bound Check Exception
+
+LDLE.W:
+    vaddr = GR[rj]
+    AddressComplianceCheck(vaddr)
+    paddr = AddressTranslation(vaddr)
+    if GR[rj] <= GR[rk]:
+        word = MemoryLoad(paddr, WORD)
+        GR[rd] = SignExtend(word, GRLEN)
+    else:
+        RaiseException(BCE)    # Bound Check Exception
+
+LDLE.D:
+    vaddr = GR[rj]
+    AddressComplianceCheck(vaddr)
+    paddr = AddressTranslation(vaddr)
+    if GR[rj] <= GR[rk]:
+        GR[rd] = MemoryLoad(paddr, DOUBLEWORD)
+    else:
+        RaiseException(BCE)    # Bound Check Exception
+
+STGT.B:
+    vaddr = GR[rj]
+    AddressComplianceCheck(vaddr)
+    paddr = AddressTranslation(vaddr)
+    if GR[rj] > GR[rk]:
+        MemoryStore(GR[rd][7:0], paddr, BYTE)
+    else:
+        RaiseException(BCE)    # Bound Check Exception
+
+STGT.H:
+    vaddr = GR[rj]
+    AddressComplianceCheck(vaddr)
+    paddr = AddressTranslation(vaddr)
+    if GR[rj] > GR[rk]:
+        MemoryStore(GR[rd][15:0], paddr, HALFWORD)
+    else:
+        RaiseException(BCE)    # Bound Check Exception
+
+STGT.W:
+    vaddr = GR[rj]
+    AddressComplianceCheck(vaddr)
+    paddr = AddressTranslation(vaddr)
+    if GR[rj] > GR[rk]:
+        MemoryStore(GR[rd][31:0], paddr, WORD)
+    else:
+        RaiseException(BCE)    # Bound Check Exception
+
+STGT.D:
+    vaddr = GR[rj]
+    AddressComplianceCheck(vaddr)
+    paddr = AddressTranslation(vaddr)
+    if GR[rj] > GR[rk]:
+        MemoryStore(GR[rd][63:0], paddr, DOUBLEWORD)
+    else:
+        RaiseException(BCE)    # Bound Check Exception
+
+STLE.B:
+    vaddr = GR[rj]
+    AddressComplianceCheck(vaddr)
+    paddr = AddressTranslation(vaddr)
+    if GR[rj] <= GR[rk]:
+        MemoryStore(GR[rd][7:0], paddr, BYTE)
+    else:
+        RaiseException(BCE)    # Bound Check Exception
+
+STLE.H:
+    vaddr = GR[rj]
+    AddressComplianceCheck(vaddr)
+    paddr = AddressTranslation(vaddr)
+    if GR[rj] <= GR[rk]:
+        MemoryStore(GR[rd][15:0], paddr, HALFWORD)
+    else:
+        RaiseException(BCE)    # Bound Check Exception
+
+STLE.W:
+    vaddr = GR[rij]
+    AddressComplianceCheck(vaddr)
+    paddr = AddressTranslation(vaddr)
+    if GR[rj] <= GR[rk]:
+        MemoryStore(GR[rd][31:0], paddr, WORD)
+    else:
+        RaiseException(BCE)    # Bound Check Exception
+
+STLE.D:
+    vaddr = GR[rj]
+    AddressComplianceCheck(vaddr)
+    paddr = AddressTranslation(vaddr)
+    if GR[rj] <= GR[rk]:
+        MemoryStore(GR[rd][63:0], paddr, DOUBLEWORD)
+    else:
+        RaiseException(BCE)    # Bound Check Exception
+
+
+
+
+
+

2.2.7. Atomic Memory Access Instructions

+
+
2.2.7.1. AM{SWAP/ADD/AND/OR/XOR/MAX/MIN}[DB].{W/D}, AM{MAX/MIN}[_DB].{WU/DU}
+
+

Instruction formats:

+
+
+
+
amswap.w        rd, rk, rj
+amswap_db.w     rd, rk, rj
+amswap.d        rd, rk, rj
+amswap_db.d     rd, rk, rj
+amadd.w         rd, rk, rj
+amadd_db.w      rd, rk, rj
+amadd.d         rd, rk, rj
+amadd_db.d      rd, rk, rj
+amand.w         rd, rk, rj
+amand_db.w      rd, rk, rj
+amand.d         rd, rk, rj
+amand_db.d      rd, rk, rj
+amor.w          rd, rk, rj
+amor_db.w       rd, rk, rj
+amor.d          rd, rk, rj
+amor_db.d       rd, rk, rj
+amxor.w         rd, rk, rj
+amxor_db.w      rd, rk, rj
+amxor.d         rd, rk, rj
+amxor_db.d      rd, rk, rj
+ammax.w         rd, rk, rj
+ammax_db.w      rd, rk, rj
+ammax.d         rd, rk, rj
+ammax_db.d      rd, rk, rj
+ammin.w         rd, rk, rj
+ammin_db.w      rd, rk, rj
+ammin.d         rd, rk, rj
+ammin_db.d      rd, rk, rj
+ammax.wu        rd, rk, rj
+ammax_db.wu     rd, rk, rj
+ammax.du        rd, rk, rj
+ammax_db.du     rd, rk, rj
+ammin.wu        rd, rk, rj
+ammin_db.wu     rd, rk, rj
+ammin.du        rd, rk, rj
+ammin_db.du     rd, rk, rj
+
+
+
+

The AM* atomic access instruction performs a sequence of “read-modify-write” operations on a memory cell atomically. +Specifically, it retrieves the old value at the specified address in memory and writes it to the general register rd, performs some simple operations on the old value in memory and the value in the general register rk, and then writes the result of the operations back to the specified address in memory. +The entire “read-modify-write” process is atomic, meaning that the processor executing the instruction does not perform any other access-write operations nor does it trigger any exceptions during the time between the return of the access read operation data and the global visibility of the access write operation, and no other processor cores or cache-consistent. +The module has global visibility of the execution of the write operation on the Cache row where the instruction accesses the object.

+
+
+

The access address of an AM* atomic access instruction is the value of the general register rj. +The access address of an AM* atomic access instruction always requires natural alignment, and failure to meet this condition will trigger a non-alignment exception.

+
+
+

Atomic access instructions ending in .W and .WU read and write memory and intermediate operations with a data length of 32 bits, while atomic access instructions ending in .D and .DU read and write memory and intermediate operations with a data length of 64 bits. +Whether ending in .W or .WU, the data of a word retrieved from memory by an atomic access instruction is symbolically extended and written to the general register rd.

+
+
+

AMSWAP[.DB].{W/D} instruction writes the new value of memory from the general register rk. +AMADD[.DB].{W/D} instruction writes the new value of memory from the result ofold value of memory plus the value in general register rk. +AMAND[DB].{W/D} instruction writes the new value to memory as a result of the bitwise AND operation of the old value in memory and the value in general register rk. +AMOR[DB].{W/D} instruction writes a new value to memory from AMXOR[.DB]. +The new value written to memory by the {W/D} instruction is the result of the bitwise OR operation of the old value in memory and the value in general register rk. +AMMAX[_DB].{W/D} instruction writes the new value to memory as the result of the bitwise AND operation of the old value in memory and the value in general register rk. +The new value written to memory is the maximum value obtained by comparing the old value in memory with the value in general register rk as a signed number. +[_DB].{W/D} instruction The new value written to memory is the minimum value obtained by comparing the old value of memory with the value in general register rk as if it were a signed number. +The new value written to memory by the AMMAX[DB].[WU/DU] instruction is the maximum value obtained by comparing the old value in memory with the value in general register rk as an unsigned number. +AMMIN[_DB].{WU/DU} instruction writes the new value to memory by comparing the old value in memory with the value in general register rk as an unsigned number. +The new value written to memory is the minimum value obtained by comparing the old value in memory with the value in general register rk as an unsigned number.

+
+
+

AM*_DB.W[U]/D[U] instruction not only completes the above atomized operation sequence, but also implements the data barrier function at the same time. +That is, all access operations preceding the atomic access instruction in the same processor core are completed before such atomic access instructions are allowed to be executed, and all access operations following the atomic access instruction in the same processor core are allowed to be executed only after such atomic access instructions are executed.

+
+
+

If the AM* atomic memory access instruction has the same register number as rd and rj, the execution will trigger an Instruction Non-defined Exception.

+
+
+

If the AM* atomic memory access instruction has the same register number as rd and rk, the execution result is uncertain. +Please software to avoid this situation.

+
+
+
+
2.2.7.2. AM.{SWAP/ADD}[_DB].{B/H}
+
+

Instruction formats:

+
+
+
+
amswap.b        rd, rk, rj
+amswap_db.b     rd, rk, rj
+amswap.h        rd, rk, rj
+amswap_db.h     rd, rk, rj
+amadd.b         rd, rk, rj
+amadd_db.b      rd, rk, rj
+amadd.h         rd, rk, rj
+amadd_db.h      rd, rk, rj
+
+
+
+

AM{SWAP/ADD}[_DB].{B/H} and AM{SWAP/ADD}[_DB].{W/D} are atomic access instructions, can atomically complete the "read - modify - write" sequence of operations on a memory cell, the main difference is that the data being accessed is byte/half-word or word/double-word.

+
+
+

AM{SWAP/ADD}[_DB].{B/H} retrieve the old byte/half word value at the specified address in memory and write it to the general register rd after symbol extension, At the same time, the old value in the memory is exchanged or added with the byte/half-word value of the general register rk [7:0]/[15:0] bit, and then the byte/half-word results will be written back to the specified address of the memory. +The entire "read-modify-write" process is atomic, meaning that the execution of the instruction, from the access to read the data return to the access to write the implementation of the effect of global visibility at the time, the processor executing the instruction neither executes other memory access write operations nor triggers any exception, and no other processor core or Cache coherence module can globally see the execution effect of the write operation on the Cache line of the object accessed by the instruction.

+
+
+

AM{SWAP/ADD}[_DB].{B/H} The access address of an atomic access instruction is the value of general-purpose register rj.

+
+
+

AM{SWAP/ADD}[_DB].H access address of an atomic access instruction is always required to be naturally aligned, and a non-alignment exception is triggered if this condition is not met.

+
+
+

In addition to the above atomic sequence of operations, the AM{SWAP/ADD}_DB.{B/H} instruction also implements the data barrier function. +That is, when this kind of atomic access instruction is allowed to execute before, all in the same processor core before the atomic access instruction access operations have been completed; +at the same time, only until the completion of this kind of atomic access instruction execution, all in the same processor core after the atomic access instruction access operation is allowed to execute.

+
+
+

If rd and rj have the same register number in AM{SWAP/ADD}[_DB].{B/H} instruction, there is no exception for trigger instruction.

+
+
+

If the register numbers of rd and rk in an AM{SWAP/ADD}[_DB].{B/H} instruction are the same, the execution result is uncertain, so please ask the software to avoid this situation.

+
+
+
+
2.2.7.3. AMCAS[_DB].{B/H/W/D}
+
+

Instruction formats:

+
+
+
+
amcas.b         rd, rk, rj
+amcas_db.b      rd, rk, rj
+amcas.h         rd, rk, rj
+amcas_db.h      rd, rk, rj
+amcas.w         rd, rk, rj
+amcas_db.w      rd, rk, rj
+amcas.d         rd, rk, rj
+amcas_db.d      rd, rk, rj
+
+
+
+

AMCAS[_DB].{B/H/W/D} instruction performs a byte/half-word/word/double-word sized Compare-and-Swap operation on a specified address in memory: The byte/half-word/word/double-word value retrieved from memory (old memory value) is compared with the value stored in the [7:0]/[15:0]/[31:0]/[63:0] location of the general-purpose register rd (expected value), and the value stored in the [7:0]/[15:0]/[31:0]/[63:0] location of the general-purpose register rk (new value) is written to the same location in the memory only when the comparison results are equal. +Regardless of whether the comparison results are equal or not, the old memory value is written to the general-purpose register rd after sign expansion.

+
+
+

The above process, If a write occurs because the old memory value is equal to the expected value, then the entire "read - modify - write" process is atomic, that is, from the access to the read operation data return to the access to the write operation to perform the effect of the global visibility of this time, the processor executing the instruction is neither the implementation of the other access to the write operation nor trigger Any exception, and no other processor core or Cache Consistency Module to the instruction access object where the Cache line of the write operation of the execution of the effect of the global visible.

+
+
+

AMCAS[_DB].{H/W/D} The access address of the instruction is the value of general-purpose register rj, and the access address is always required to be naturally aligned, if this condition is not met, a non-aligned exception will be triggered.

+
+
+

In addition to the above atomic sequence of operations, the AMCAS_DB.{B/H/W/D} instruction also implements the data barrier function. +That is, when this kind of atomic access instruction is allowed to execute before, all in the same processor core before the atomic access instruction access operations have been completed; at the same time, only when this kind of atomic access instruction execution is completed, all in the same processor core after the atomic access instruction access operations are allowed to execute.

+
+
+
+
2.2.7.4. LL.{W/D}, SC.{W/D}
+
+

Instruction formats:

+
+
+
+
ll.w        rd, rj, si14
+ll.d        rd, rj, si14
+sc.w        rd, rj, si14
+sc.d        rd, rj, si14
+
+
+
+

The two pairs of instructions, LL.W and SC.W, LL.D and SC.D, are used to implement an atomic “read, modify, and write” sequence of memory access operations. +The LL.{W/D} instruction retrieves a word/double-word data from the specified address of the memory and writes it to the general register rd after sign extension, and the paired SC. +{W/D} instruction operates on the same length of data and has the same access Memory address. +The atomic maintenance mechanism for the sequence of memory access operations is that when LL.{W/D} is executed, the access address is recorded and the previous flag is set (LLbit is set to 1), and the LLbit is checked when the SC.{W/D} instruction is executed. +Only when the LLbit is 1, the write action will actually occur, otherwise it will not be written. +When the software needs to successfully complete an atomic “read-modify-write” memory access operation sequence, it needs to construct a loop to repeatedly execute the LLSC instruction pair until the SC is successfully completed. +In order to construct this loop, the SC.[W/D] instruction will write the flag of its execution success (or simply the LLbit value seen when the SC instruction is executed) into the general register rd and return.

+
+
+

During the execution of the paired LLSC, the following events will clear the LLbit to 0:

+
+
+
    +
  • +

    The ERTN instruction is executed and the KL0 bit in CSR.LLBCTL is not equal to 1 when executed;

    +
    • +
  • +

    Other processor cores or Cache Coherent I/O masters perform a store operation on the Cache line where the address corresponding to the LLbit is located.

    +
    • +
+
+
+

If the memory access attribute of the LLSC instruction to the access address is not Cached, then the execution result is uncertain.

+
+
+
+
2.2.7.5. SC.Q
+
+

Instruction formats:

+
+
+
+
SC.Q            rd, rk, rj
+
+
+
+

The SC.Q instruction is similar to the SC.D instruction and is used in conjunction with the LL.D instruction to implement an atomic "read-modify-write" access sequence for 128-bit data.

+
+
+

SC.Q writes the 128-bit data {GR[rk][63:0], GR[rd][63:0]} obtained by splicing the general-purpose registers rk and rd into memory, and its access address is the value of the general-purpose register rj. +SC.Q instruction will check LLbit when executing, and only when LLbit is 1, then it will write, otherwise it will not write, SC.Q instruction will write the flag of success or failure (also can be understood as the value of LLbit when SC.Q instruction executes) into general register rd and return to the memory.

+
+
+

The access address of SC.Q instruction is always required to be 16-byte aligned, if this condition is not met, a non-aligned exception will be triggered.

+
+
+

If the SC.Q instruction’s memory access attribute for the access address is not consistently cacheable (CC), the result of the execution is indeterminate.

+
+
+
+
2.2.7.6. LL.ACQ.{W/D}, SC.REL.{W/D}
+
+

Instruction formats:

+
+
+
+
ll.acq.w        rd, rj
+ll.acq.d        rd, rj
+sc.rel.w        rd, rj
+sc.rel.d        rd, rj
+
+
+
+

LL.ACQ.{W/D} is an LL.{W/D} instruction with read-acquire semantics, that is, only when LL.ACQ.{W/D} is executed (globally visible), all subsequent access operations can start executing (globally visible effect); SC.REL.{W/D} is an SC.{W/D} instruction with write-release semantics, that is, only when SC.REL.{W/D} is executed (globally visible), all access operations can start executing (globally visible effect).

+
+
+

The LL.ACQ.{W/D} instruction fetches a word/double word of data symbol expansion from the specified address in memory and writes it to the general-purpose register rd, and at the same time records the access address and places a flag (LLbit set to 1). +The SC.REL.{W/D} instruction conditionally writes the word/double-word value of [31:0]/[63:0] in the general-purpose register rd to the specified address in the memory, whether or not to write to the memory depends on the LLbit, and only when the LLbit is 1 does it really generate a write action, otherwise it does not write. +SC.REL instruction will write the flag of success or failure of its execution (which can be simply understood as the LLbit value seen by the SC.REL instruction when it is executed) into the general-purpose register rd and return it, regardless of whether it writes to the memory or not.

+
+
+

During paired LL-SC execution, the following events clear the LLbit to zero:

+
+
+
    +
  • +

    An ERTN instruction is executed and the KLO bit in CSR.LLBCTL is not equal to 1 at the time of execution.

    +
    • +
  • +

    another processor core or Cache Coherent master completes a store operation on the Cache line corresponding to the address of the LLbit.

    +
    • +
+
+
+

LL.ACQ and SC.REL instructions always require a natural alignment of the access address, if this condition is not met a non-alignment exception is triggered.

+
+
+

If the LL.ACQ and SC.REL instructions direct that the store access attribute of the access address is not cache-consistent (CC), then the result of the execution is indeterminate.

+
+
+
+
+

2.2.8. Barrier Instructions

+
+
2.2.8.1. DBAR
+
+

Instruction formats:

+
+
+
+
dbar        hint
+
+
+
+

The DBAR instruction is used to complete the barrier function between load/store memory access operations. +The immediate hint it carries is used to indicate the synchronization object and synchronization degree of the barrier.

+
+
+

A hint value of 0 is mandatory by default, and it indicates a fully functional synchronization barrier. +Only after all previous load/store access operations are completely executed, the DBAR 0 instruction can be executed; and only after the execution of DBAR 0 is completed, all subsequent load/store access operations can be executed.

+
+
+

If there is no special function implementation, all other hint values must be executed according to hint=0.

+
+
+
+
2.2.8.2. IBAR
+
+

Instruction formats:

+
+
+
+
ibar        hint
+
+
+
+

The IBAR instruction is used to complete the synchronization between the store operation and the instruction fetch operation within a single processor core. +The immediate hint it carries is used to indicate the synchronization object and synchronization degree of the barrier.

+
+
+

A hint value of 0 is mandatory by default. +It can ensure that the instruction fetch after the IBAR 0 instruction must be able to observe the execution effect of all store operations before the IBAR 0 instruction.

+
+
+
+
+

2.2.9. CRC Check Instructions

+
+
2.2.9.1. CRC[C].W.{B/H/W/D}.W
+
+

Instruction formats:

+
+
+
+
crc.w.b.w       rd, rj, rk
+crc.w.h.w       rd, rj, rk
+crc.w.w.w       rd, rj, rk
+crc.w.d.w       rd, rj, rk
+crcc.w.b.w      rd, rj, rk
+crcc.w.h.w      rd, rj, rk
+crcc.w.w.w      rd, rj, rk
+crcc.w.d.w      rd, rj, rk
+
+
+
+

CRC[C]W.{B/H/W/D}.W is used to calculate the CRC-32 checksum, which stores the 32-bit cumulative CRC checksum stored in the general register rk in the general register rj [7:0]/[15:0]/[31:0]/[63:0] bit message, get a new 32-bit CRC checksum according to the CRC-32 checksum generation algorithm, and write it after sign extension into the general register rd. +The difference is that CRC.W.{B/H/W/D}.W uses IEEE802.3 polynomial (polynomial value is 0xEDB88320), CRCC.W.{B/H/W/D}.W uses Castagnoli polynomial (polynomial value is 0x82F63B78). +The CRC instructions defined in this manual only support the “LSB first” (little endian) standard, which means that the lowest bit of data (little endian) is transmitted first, and the lowest bit of the data is mapped to the coefficient of the most significant term of the message polynomial.

+
+
+
+
CRC.W.B.W:
+    chksum = CRC32(GR[rk][31:0], GR[rj][7:0], 8, 0xEDB88320)
+    GR[rd] = SignExtend(chksum, GRLEN)
+
+CRC.W.H.W:
+    chksum = CRC32(GR[rk][31:0], GR[rj][15:0], 16, 0xEDB88320)
+    GR[rd] = SignExtend(chksum, GRLEN)
+
+CRC.W.W.W:
+    chksum = CRC32(GR[rk][31:0], GR[rj][31:0], 32, 0xEDB88320)
+    GR[rd] = SignExtend(chksum, GRLEN)
+
+CRC.W.D.W:
+    chksum = CRC32(GR[rk][31:0], GR[rj][63:0], 64, 0xEDB88320)
+    GR[rd] = SignExtend(chksum, GRLEN)
+
+CRCC.W.B.W:
+    chksum = CRC32(GR[rk][31:0], GR[rj][7:0], 8, 0x82F63B78)
+    GR[rd] = SignExtend(chksum, GRLEN)
+
+CRCC.W.H.W:
+    chksum = CRC32(GR[rk][31:0], GR[rj][15:0], 16, 0x82F63B78)
+    GR[rd] = SignExtend(chksum, GRLEN)
+
+CRCC.W.W.W:
+    chksum = CRC32(GR[rk][31:0], GR[rj][31:0], 32, 0x82F63B78)
+    GR[rd] = SignExtend(chksum, GRLEN)
+
+CRCC.W.D.W:
+    chksum = CRC32(GR[rk][31:0], GR[rj][63:0], 64, 0x82F63B78)
+    GR[rd] = SignExtend(chksum, GRLEN)
+
+
+
+
+
+

2.2.10. Other Miscellaneous Instructions

+
+
2.2.10.1. syscall
+
+

Instruction formats:

+
+
+
+
syscall     code
+
+
+
+

Executing the SYSCALL instruction will immediately and unconditionally trigger the system call exception.

+
+
+

The information carried in the code field in the instruction code can be used as a parameter passed by the exception handling routine.

+
+
+
+
2.2.10.2. break
+
+

Instruction formats:

+
+
+
+
break       code
+
+
+
+

Executing the BREAK instruction will immediately and unconditionally trigger the breakpoint exception.

+
+
+

The information carried in the code field in the instruction code can be used as a parameter passed by the exception handling routine.

+
+
+
+
2.2.10.3. ASRT{LE/GT}.D
+
+

Instruction formats:

+
+
+
+
asrtle.d        rj, rk
+asrtgt.d        rj, rk
+
+
+
+

The value in general register rj and general register rk are compared as signed numbers. +If the comparison conditions are not met, an exception for address bound checking is triggered. +For the ASRTLE.D instruction, if the value in the general register rj is greater than the value in the general register rk, an exception is triggered; for the ASRTGT.D instruction, if the value in the general register rj is less than or equal to the value in the general register rk, an exception is triggered.

+
+
+
+
2.2.10.4. RDTIME{L/H}.W, RDTIME.D
+
+

Instruction formats:

+
+
+
+
rdtimel.w       rd, rj
+rdtimeh.w       rd, rj
+rdtime.d        rd, rj
+
+
+
+

The LoongArch instruction system defines-a constant frequency timer, whose main body is-a 64-bit counter called StableCounter. +StableCounter is set to 0 after reset, and then increments by 1 every counting clock cycle. +When the count reaches all 1s, it automatically wraps around to 0 and continues to increment. +At the same time, each timer has a software-configurable globally unique-number, called Counter ID. +The characteristic of the constant frequency timer is that its timing frequency remains unchanged after reset, no matter how the clock frequency of the processor core changes.

+
+
+

The RDTIME{L/W}.W and RDTIME.D instructions are used to read constant frequency timer information, the StableCounter value is written into the general register rd, and the Counter ID number information is written into the general register rj. +The difference between the three instructions is the difference in the Stable Counter information read. +RDTIMEL.W reads the [31:0] bits of the Counter, RDTIMEH.W reads the [63:32] bits of the Counter, and RDTIME.D reads The entire 64-bit Counter value. +On a 64-bit processor, the 32-bit value read by the RDTIME{L/H}.W instruction is sign extension and written to the general register rd. +The RDTIME(L/H).W instruction is defined so that the 64-bit Counter can also be accessed on a 32-bit processor.

+
+
+
+
2.2.10.5. cpucfg
+
+

Instruction formats:

+
+
+
+
cpucfg      rd, rj
+
+
+
+

The CPUCFG instruction is used to dynamically identify which features of LoongArch are implemented in the running processor during the execution of the software. +The realization of the functional characteristics of these instruction systems is recorded in the series of configuration information words. +One configuration information word can be read once the CPUCFG instruction is executed.

+
+
+

When using the CPUCFG instruction, the source operand register rj stores the number of the configuration information word to be accessed, and the configuration information word information read after the instruction is executed is written into the general register rd. +In LA64, each configuration information word is 32 bits, which is written into the result register after the sign extension.

+
+
+

The configuration information word contains-series of configuration bits (fields), and its record form is CPUCFG.<configuration word number>.<configuration information mnemonic name>[bit subscript], where the single bit configuration bit is marked as bitXX, which means The XX bit of the configuration word; the bit under the multi-bit configuration field is marked as bitXX:YY, which means the continuous (XX-YY+1) bit from the XX bit to the YY bit of the configuration word. +For example, the 0th bit in the configuration word No.1 is used to indicate whether to implement LA32. +Record this configuration information as CPUCFG.1.LA32[bit0], where 0x1 indicates that the font size of the configuration information word is No.1, and LA32 indicates this configuration The mnemonic name of the information field is called LA32, and bit 0 means that the field of LA32 is located at bit 0 of the configuration word. +The PALEN field of the number of physical address bits supported by the 11th to 4th digits of the configuration word No.1 is recorded as CPUCFG.1.PALEN[itl1:4].

+
+
+

The configuration information accessible by the CPUCFG instruction in the Godson architecture is listed in the table. +CPUCFG access to undefined configuration words will read back all 0 values. +The undefined field in the defined configuration word can be read back to any value when CPUCFG is executed, and the software should not make any interpretation of it.

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 3. The configuration information accessible by the CPUCFG instruction
Word numberBit numberAnnotationImplication

0x0

31:0

PRID

Processor Identity

0x1

1:0

ARCH

2’b00 indicates the implementation of simplified LA32;

+

2’b01 indicates the implementation of LA32;

+

2’b10 indicates the implementation of LA64;

+

2’b11 is reserved.

2

PGMMU

1 indicates that the MMU supports page mapping mode

3

IOCSR

1 indicates support for the IOCSR instruction

11:4

PALEN

The supported physical address bits PALEN value minus 1

19:12

VALEN

The supported virtual address bits VALEN value minus 1

20

UAL

1 indicates support for non-aligned memory access

21

RI

1 indicates support for page attribute of “Read Inhibit”

22

EP

1 indicates support for page attribute of “Execution Protection”

23

RPLV

1 indicates support for page attributes of RPLV

24

HP

1 indicates support for page attributes of huge page

25

CRC

1 indicates that support CRC instruction

+

That is, information such as “Loongson3A5000 @ 2.5GHz”

26

MSG_INT

1 indicates that the external interrupt uses the message interrupt mode, otherwise it is the level interrupt line mode

2

0

FP

1 indicates support for basic floating-point instructions

1

FP_SP

1 indicates support for single-precision floating-point numbers

2

FP_DP

1 indicates support for double-precision floating-point numbers

5:3

FP_ver

The version number of the floating-point arithmetic standard. +1 is the initial version number, indicating that it is compatible with the IEEE 754-2008 standard

6

LSX

1 indicates support for 128-bit vector extension

7

LASX

1 indicates support for 256-bit vector expansion

8

COMPLEX

1 indicates support for complex vector operation instructions

9

CRYPTO

1 indicates support for encryption and decryption vector instructions

10

LVZ

1 indicates support for virtualization expansion

13:11

LVZ_ver

The version number of the virtualization hardware acceleration specification. +1 is the initial version number

14

LLFTP

1 indicates support for constant frequency counter and timer

17:15

LLFTP_ver

Constant frequency counter and timer version number. +1 is the initial version

18

LBT_X86

1 indicates support for X86 binary translation extension

19

LBT_ARM

1 indicates support for ARM binary translation extension

20

LBT_MIPS

1 indicates support for MIPS binary translation extension

21

LSPW

1 indicates support for the software page table walking instruction

22

LAM

1 indicates support AM* atomic memory access instruction

24

HPTW

1 indicates support Page Table Walker

25

FRECIPE

1 indicates support FRECIPE.{S/D}、FRSQRTE.{S/D}. +If 128-bit vector extension is also supported, VFRECIPE.{S/D}、VFRSQRTE.{S/D} is supported. +If 256-bit vector extension is also supported, XVFRECIPE.{S/D}、XVFRSQRTE.{S/D} is supported.

26

DIV32

1 indicates that DIV.W[U] and MOD.W[U] instructions on 64-bit machines compute only the low 32-bit data of the input register

27

LAM_BH

1 indicates support AM{SWAP/ADD}[_DB].{B/H}.

28

LAMCAS

1 indicates support AMCAS[_DB].{B/H/W/D}.

29

LLACQ_SCREL

1 indicates support LLACQ.{W/D}、SCREL.{W/D}.

30

SCQ

1 indicates support SC.Q.

3

0

CCDMA

1 indicates support for hardware Cache coherent DMA

1

SFB

1 indicates support for Store Fill Buffer (SFB)

2

UCACC

1 indicates support for ucacc win

3

LLEXC

1 indicates support for LL instruction to fetch exclusive block function_

4

SCDLY

1 indicates support random delay function after SC

5

LLDBAR

1 indicates support LL automatic with dbar function

6

ITLBTHMC

1 indicates that the hardware maintains the consistency between ITLB and TLB

7

ICHMC

1 indicates that the hardware maintains the data consistency between ICache and DCache in one processor core

10:8

SPW_LVL

The maximum number of directory levels supported by the page walk instruction

11

SPW_HP_HF

1 indicates that the page walk instruction fills the TLB in half when it encounters a large page

12

RVA

1 indicates that the software configuration can be used to shorten the virtual address range

16:13

RVAMAX-1

The maximum configurable virtual address is shortened by -1

17

DBAR_hints

1 indicates that the non-0 value of the DBAR is implemented according to the recommended meaning of the manual.

23

LD_SEQ_SA

1 indicates that the hardware is enabled to guarantee sequential execution of load operations at the same address.

0x4

31:0

CC_FREQ

Constant frequency timer and the crystal frequency corresponding to the clock used by the timer

0x5

15:0

CC_MUL

Constant frequency timer and the corresponding multiplication factor of the clock used by the timer

31:16

CC_DIV

Constant frequency timer and the division coefficient corresponding to the clock used by the timer

0x6

0

PMP

1 indicates support for the performance counter

3:1

PMVER

In the performance monitor, the architecture defines the version number of the event, and 1 is the initial version

7:4

PMNUM

Number of performance monitors minus 1

13:8

PMBITS

Number of bits of a performance monitor minus 1

14

UPM

1 indicates support for reading performance counter in user mode

0x10

0

L1 IU_Present

1 indicates that there is a first-level instruction Cache or a first-level unified Cache

1

L1 IU Unify

1 indicates that the Cache shown by L1 IU_Present is the unified Cache

2

L1 D Present

1 indicates there is a first-level data Cache

3

L2 IU Present

1 indicates there is a second-level instruction Cache or a second-level unified Cache

4

L2 IU Unitfy

1 indicates that the Cache shown by L2 IU_Present is the unified Cache

5

L2 IU Private

1 indicates that the Cache shown by L2 IU_Present is private to each core

6

L2 IU Inclusive

1 indicates that the Cache shown by L2 IU_Present has an inclusive relationship to the lower levels (L1)

7

L2 D Present

1 indicates there is a secondary data Cache

8

L2 D Private

1 indicates that the secondary data Cache is private to each core

9

L2 D Inclusive

1 indicates that the secondary data Cache has a containment relationship to the lower level (L1)

10

L3 IU Present

1 indicates there is a three-level instruction Cache or a three-level system Cache

11

L3 IU Unify

1 indicates that the Cache shown by L3 IU_Present is unified Cache

12

L3 IU Private

1 indicates that the Cache shown by L3 IU_Present is private to each core

13

L3 IU Inclusive

1 indicates that the Cache shown by L3 IU_Present has an inclusive relationship to the lower levels (L1 and L2)

14

L3 D Present

1 indicates there is a three-level data Cache

15

L3 D Private

1 indicates that the three-level data Cache is private to each core

16

L3 D Inclusive

1 indicates that the three-level data Cache has an inclusive relationship to the lower levels (L1 and 12)

0x11

15:0

Way-1

Number of channels minus 1 (Cache corresponding to L1 IU_Present in configuration word 10)

23:16

Index-log2

log2(number of Cache rows per channel) (Cache corresponding to L1 IU_Present in configuration word 10)

30:24

Linesize-log2

log2(Cache line bytes) (Cache corresponding to L1 IU_Present in configuration word 10)

0x12

15:0

Way-1

Number of channels minus 1 (Cache corresponding to L1 D Present in configuration word 10)

23:16

Index-log2

log2(number of Cache rows per channel) (Cache corresponding to L1 D Present in configuration word 10)

30:24

Linesize-log2

log2(Cache row bytes) (Cache corresponding to L1 D Present in configuration word 10)

0x13

15:0

Way-1

Number of channels minus 1 (Cache corresponding to L2 IU Present in configuration word 10)

23:16

Index-log2

log2(number of Cache rows per channel) (Cache corresponding to L2 IU Present in configuration word 10)

30:24

Linesize-log2

log2(Cache row bytes) (Cache corresponding to L2 IU Present in configuration word 10)

0x14

15:0

Way-1

Number of channels minus 1 (Cache corresponding to L3 IU Present in configuration word 10)

23:16

Index-log2

log2(number of Cache rows per channel) (Cache corresponding to L3 IU Present in configuration word 10)

30:24

Linesize-log2

log2(Cache row bytes) (Cache corresponding to L3 IU Present in configuration word 10)

+
+
+
+
+
+
+

3. Basic Floating-Point Instructions

+
+
+

This chapter will introduce the floating-point number instructions in the basic part of the non-privileged subset of LoongArch. +The function definition of the basic floating-point instructions in LoongArch follows the IEEE 754-2008 standard.

+
+
+

Basic floating-point instructions cannot be implemented separately from basic integer instructions. +Generally speaking, it recommends that implementing both basic integer instructions and basic floating-point instructions at the same time. +However, for some embedded applications that are cost-sensitive and have extremely low floating-point processing performance requirements, the architecture specification also allows not to implement basic floating-point instructions, or only implement single-precision floating-point numbers and word integers in basic floating-point instructions. +Whether the implementation of basic floating-point instructions includes instructions for operating double-precision floating-point numbers and double-word integers has nothing to do with whether the architecture is LA32 or LA64.

+
+
+

3.1. Programming Model of Basic Floating-Point Instructions

+
+

The basic floating-point instruction programming model described in this section only involves the content that application software developers need to pay attention to. +When software personnel use basic floating-point instructions to program, they are on the basis of the basic integer instruction programming model, and then proceed to involve the content described in this section.

+
+
+

3.1.1. Floating-Point Data Types

+
+

Floating-point data types include single-precision floating-point numbers and double-precision floating-point numbers, both of which follow the definition in the IEEE 754-2008 standard specification.

+
+
+
3.1.1.1. Single-precision Floating-point
+
+

Single-precision floating-point numbers have a length of 32 bits and are organized into the following format:

+
+
+
+single precision floating point number format +
+
Figure 3. Single-precision floating-point number format
+
+
+

According to the different values of the fields of S, Exponent and Fraction, the floating-point number values represented are shown in the table:

+
+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 4. Single-precision floating-point number calculation method
ExponentFractionSbit[22]V

0

0

0

0

+0

1

0

-0

0

!=0

0

Any value

Denormalized number, the value is +2-126×(0.Fraction)

1

Any value

Denormalized number, the value is -2-126×(0.Fraction)

[1,0xFE]

Any value

0

Any value

Normalized number, the value is +2Exponent-127×(1.Fraction)

1

Any value

Normalized number, the value is -2Exponent-127×(1.Fraction)

0xFF

0

0

0

+∞

1

0

-∞

0xFF

!=0

Any value

0

Signaling Not a Number, SNaN

Any value

1

Quiet Not a Number, QNaN

+
+

For the specific meaning of ±∞, SNaN and QNaN, please refer to the IEEE 754-2008 standard specification.

+
+
+
+
3.1.1.2. Double-precision Floating-point
+
+
+double precision floating point number format +
+
Figure 4. Double-precision floating-point number format
+
+
+

According to the different values of the fields of S, Exponent and Fraction, the floating-point number values represented are shown in the table:

+
+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 5. Double-precision floating-point number calculation method
ExponentFractionSbit[51]V

0

0

0

0

+0

1

0

-0

0

!=0

0

Any value

Denormalized number, the value is +2-1022×(0.Fraction)

1

Any value

Denormalized number, the value is -2-1022×(0.Fraction)

[1,0x7FE]

Any value

0

Any value

Normalized number, the value is +2Exponent-1023×(1.Fraction)

1

Any value

Normalized number, the value is -2Exponent-1023×(1.Fraction)

0x7FF

0

0

0

+∞

1

0

-∞

0x7FF

!=0

Any value

0

Signaling Not a Number, SNaN

Any value

1

Quiet Not a Number, QNaN

+
+

For the specific meaning of ±∞, SNaN and QNaN, please refer to the IEEE 754-2008 standard specification.

+
+
+
+
3.1.1.3. Non-numerical Result of Instructions
+
+

The non-numerical results produced by floating-point number instructions either come from NaN propagation or are directly generated. +There are two situations where NaN propagation is required.

+
+
+

Case 1: When the instruction generates an Invalid Operation floating-point exception due to a source operand containing SNaN, but the InvalidOperation floating-point exception enable is invalid, a QNaN result will be generated at this time. +The value of this QNaN is to select the SNaN with the highest priority in the source operand and propagate it to the corresponding NaN.

+
+
+

The rule for determining the priority of the source operand is: if there are two source operands fj and fk, then the priority of fj is higher than fk; if there are three source operands fa, fj and fk, then the priority of fa is higher than fj, fj have higher priority than fk.

+
+
+

The value generation rules for propagation of SNaN to QNaN are as follows:

+
+
+
    +
  • +

    If the result is the same length as the source operand, then the highest position of the SNaN mantissa will be propagated to 1, and the remaining bits remain unchanged. +If the result is narrower than the source operand, then keep the high bits of the mantissa, discard the low bits that exceed the range, and finally set the highest bit of the mantissa to 1.

    +
    • +
  • +

    If the result is wider than the source operand, then the lowest bit of the mantissa will be filled with 0, and finally the highest position of the mantissa will be 1.

    +
    • +
+
+
+

Case 2: When there is no SNaN in the source operand but QNaN exists, the QNaN with the highest priority is selected as the result of this instruction. +At this time, the way of judging the priority of the source operand is the same as in the above situation.

+
+
+

Except for the above two cases, other cases that need to produce QNaN results will be directly set to the default QNaN value. +The default single-precision QNaN value is 0x7FC00000, and the default double-precision QNaN value is 0x7FF8000000000000.

+
+
+
+
+

3.1.2. Fixed-Point Data Types

+
+

Some floating-point instructions (such as floating-point conversion instructions) also manipulate fixed-point data, including Word (W, length 32b), and Longword (L, length 64b). +Both word and longword data types use two’s complement encoding.

+
+
+
+

3.1.3. Registers

+
+

Floating-point instruction programming involves registers such as Floating-point Register (FR), Condition Flag Register (CFR) and Floatingpoint Control and Status Register (FCSR).

+
+
+
3.1.3.1. Floating-point Registers
+
+

There are 32 FRs, denoted as f0-f31, each of which can be read and written. +Only when only floating-point instructions that manipulate single-precision floating-point numbers and word integers are implemented, the length of FR is 32 bits. +Under normal circumstances, the length of FR is 64 bits, regardless of the LA32 or LA64. +There is an “orthogonal” relationship between basic floating-point instructions and floating-point registers, that is, from an architectural perspective, any floating-point register operand in these instructions can use any one of the 32 FRs.

+
+
+
+floating point registers +
+
Figure 5. Floating-point Registers
+
+
+

When the floating-point register records a single-precision floating-point number or word integer, the data always appears in the [31:0] bits of the floating-point register, at this time the [63:32] bits of the floating-point register can be any value.

+
+
+
+
3.1.3.2. Condition Flag Register
+
+

There are 8 CFRs, denoted as fcc0-fcc7, each of which can be read and written. +The length of CFR is 1 bit. +The result of the floating-point comparison will be written into the condition flag register. +When the comparison result is true, it is set to 1, otherwise it is set to 0. +The judgment condition of the floating-point branch instruction comes from the condition register.

+
+
+
+
3.1.3.3. Floating-point Control and Status Register
+
+

There are 4 FCSRs, denoted as fcsr0-fcsr3. +Among them, fcsr1-fcsr3 are aliases of some fields in fcsr0, that is, accessing fcsrl-fcsr3 is actually accessing some fields of fcsr0. +When the software writes fcsr1-fcsr3, the corresponding field in fcsr0 is modified while the remaining bits remain unchanged. +The definition of each field of fcsr0 is shown in the table.

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 6. Definitions of FCSR0 Register Fields
BitsNameRead&writeDescription

4:0

Enables

RW

The floating-point operation VZOUI exceptions each allow the enable bit to trigger the exception trap.

+

Bit 4 corresponds to V, bit 3 corresponds to Z, bit 2 corresponds to O, bit 1 corresponds to U, and bit 0 corresponds to I.

9:8

RM

RW

Rounding mode control. +It contains 4 legal values, each with the following meaning:

+

0: RNE, corresponding to roundTiesToEven in IEEE 754-2008;

+

1: RZ, corresponding to roundTowardZero in IEE 754-2008;

+

2: RP, corresponding to roundTowardsPositive in IEEE 754-2008;

+

3: RM, corresponding to roundTowardsNegative in IEEE 754-2008.

20:16

Flags

RW

Since the last time the Flags field was cleared by the software, the cumulative status of various floating-point operations VZOUI exceptions that were generated but not caught.

+

Bit 20 corresponds to V, bit 19 corresponds to Z, bit 18 corresponds to O, bit 17 corresponds to U, and bit 16 corresponds to I.

28:24

Cause

RW

The VZOUI exception caused by the last floating-point operation.

+

Bit 28 corresponds to V, bit 27 corresponds to Z, bit 26 corresponds to O, bit 25 corresponds to U, and bit 24 corresponds to I.

+
+

FCSR1 is the alias of the Enables field in FCSR0. +Its location is the same as in FCSR0.

+
+
+

FCSR2 is the alias of the Cause and Flags fields in FCSR0. +The location of each field is consistent with FCSR0.

+
+
+

FCSR3 is the alias of the RM field in FCSR0. +Its location is the same as in FCSR0.

+
+
+
+
+

3.1.4. Floating-Point Exceptions

+
+

Floating-point exception means that when the floating-point processing unit cannot process the operand or the result of floating-point calculation in a conventional manner, the floating-point functional unit will generate a corresponding exception.

+
+
+

The basic floating-point instructions support five floating-point exceptions defined by IEEE 754-2008:

+
+
+
    +
  • +

    Inexact (I)

    +
    • +
  • +

    Underflow (U)

    +
    • +
  • +

    Overflow (O)

    +
    • +
  • +

    Division by Zero (Z)

    +
    • +
  • +

    Invalid Operation (V)

    +
    • +
+
+
+

Each bit of the Cause field in FCSR0 corresponds to the above-mentioned exceptions. +After the execution of each floating-point instruction, the occurrence of its exception will be updated to the Cause field of FCSR0.

+
+
+

FCSR0 also contains an enable bit (Enables field) for each floating-point exception. +The enable bit determines whether an exception generated by the floating-point processing unit will trigger an exception trap or set a status flag. +When a floating-point exception occurs, if its corresponding Enable bit is 1, then a floating-point exception trap will be triggered; if its corresponding Enable bit is 0, then the floating-point exception trap will not be triggered, but Set the corresponding position of the Flag field in FCSR0 to 1.

+
+
+

During the execution of a floating-point instruction, multiple floating-point exceptions can be generated at the same time.

+
+
+

When a floating-point exception is generated during the execution of a floating-point instruction but the floating-point exception is not triggered, the floating-point processing unit will generate a default result. +Different exceptions produce default results in different ways. +The table lists specific generation rules.

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 7. Default results of floating-point exceptions
AreaDescriptionRounding modeDefault result

I

Inexact

Any mode

The result after rounding or the result after overflow

U

Underflow

RNE

The result after rounding may be 0, subnormal, the normal number with the smallest absolute value (single-precision: ±2-126, double-precision: ±2-1022)

RZ

The result after rounding, may be 0, subnormal

RP

The rounded result may be 0, subnormal, the smallest positive normal number (single-precision: +2-126, double-precision: +2-1022)

RM

The rounded result may be 0, subnormal, the largest negative normal number (single-precision: -2-126, double-precision: -2-1022)

O

Overflow

RNE

Set the result to +∞ or -∞ according to the sign of the intermediate result

RZ

Set the result to the maximum number according to the sign of the intermediate result

RP

Correct negative overflow to the smallest negative number, and correct positive overflow to +∞

RM

Correct the positive overflow to the largest positive number, and correct the negative overflow to -∞

Z

Division by Zero

Any mode

Provide a corresponding signed infinity number

V

InValid Operation

Any mode

Provide a QNaN

+
+
3.1.4.1. Illegal Operation Exception (V)
+
+

An invalid operation exception notification signal will be sent if and only if there is no valid defined result. +If no exception is triggered, a QNaN will be generated. +Please refer to Characteristics of Accessing Control and Status Registers of the IEEE 754-2008 specification for specific determination details of extraordinary operation exceptions.

+
+
+

If an exception is allowed to fall into: the result register is not modified, the source register remains.

+
+
+

If exceptions are prohibited from trapping: If no other exceptions occur, QNaN is written to the target register.

+
+
+
+
3.1.4.2. Division by Zero Exception (Z)
+
+

In the division operation, when the divisor is 0 and the dividend is-a limited non-zero data, the division by zero exception is signaled.

+
+
+

If an exception is allowed to fall into: the result register is not modified, the source register remains

+
+
+

If an exception is forbidden to fall into: if no trap occurs, the result is a signed infinite value.

+
+
+
+
3.1.4.3. Overflow Exception (O)
+
+

Regarding the exponent field as an unbounded rounding of the intermediate result, when the absolute value of the result obtained exceeds the maximum finite number of the target format, an overflow exception will be notified.(This exception sets both inexact exception and flag bit)

+
+
+

If an exception is allowed to fall into: the result register is not modified, the source register remains.

+
+
+

If exceptions are forbidden to fall into: If no trap occurs, the final result is determined by the rounding mode and the sign of the intermediate result.

+
+
+
+
3.1.4.4. Underflow Exception (U)
+
+

When the detection result is a small non-zero value, an underflow exception will occur. +The way to detect small non-zero values is to detect after rounding. +that is, for a non-zero result is in (-2Emin, 2Emin), the result is considered to be a small non-zero value (Single-precision number Emin=-126, double-precision number Emin=-1022). +When FCSR.Enable.U=0, if the result is detected, a non-zero tiny value:

+
+
+
    +
  1. +

    If the final rounded result of the floating-point operation is inaccurate, both U and I in FCSR.Cause should be set to 1;

    +
    2. +
  2. +

    If the final rounded result of the floating-point operation is accurate, then U and I in FCSR.Cause are not set to 1.

    +
    3. +
+
+
+

When FCSR.Enable.U=1, if the result is a non-zero tiny value, regardless of whether the final rounded result of the floating-point operation is accurate or inaccurate, it will trigger a floating-point exception trap.

+
+
+
+
3.1.4.5. Inexact Exception (I)
+
+

FPU generates inaccurate exceptions when the following situations occur:

+
+
+
    +
  • +

    Rounding result is imprecise.

    +
    • +
  • +

    The rounding result overflows, and the enable bit of the overflow exception is not set.

    +
    • +
+
+
+

If an exception is allowed to fall: If an inexact exception trap is enabled, the result register is not modified and the source register is retained. +Because this execution mode affects performance, inaccurate exception traps are only enabled when necessary.

+
+
+

If an exception is prohibited, trapping is prohibited: If no other software trap occurs, the rounding or overflow result is sent to the destination register.

+
+
+
+
+
+

3.2. Overview of Floating-Point Instructions

+
+

The instructions described in this section, except for FLDX.{S/D}, FSTX.{S/D}, FLD{GT/LE}.{S/D} and FST{GT/LE}.{S/D} these 12 The floating-point memory access instructions only belong to the LA64, and all other floating-point instructions are applicable to both LA32 and LA64.

+
+
+

3.2.1. Floating-Point Arithmetic Operation Instructions

+
+
3.2.1.1. F{ADD/SUB/MUL/DIV}.{S/D}
+
+

Instruction formats:

+
+
+
+
fadd.s      fd, fj, fk
+fadd.d      fd, fj, fk
+fsub.s      fd, fj, fk
+fsub.d      fd, fj, fk
+fmul.s      fd, fj, fk
+fmul.d      fd, fj, fk
+fdiv.s      fd, fj, fk
+fdiv.d      fd, fj, fk
+
+
+
+

The FADD.{S/D} instruction performs the operation that the single-precision/double-precision floating-point number in the floating-point register fj plus the single-precision/double-precision floating-point number in the floating-point register fk; then writes the result of the single-precision/double-precision floating-point number to floating-point register fd. +Floating-point addition operation follows the specification of addition(x,y) operation in the IEEE 754-2008 standard.

+
+
+
+
FADD.S:
+    FR[fd][31:0] = FP32_addition(FR[fj][31:0], FR[fk][31:0])
+
+FADD.D:
+    FR[fd] = FP64_addition(FR[fj], FR[fk])
+
+
+
+

The FSUB.{S/D} instruction performs the operation that the single-precision/double-precision floating-point number in the floating-point register fj minus the single-precision/double-precision floating-point number in the floating-point register fk, and write the result of the single-precision/double-precision floating-point number to floating-point register fd. +The floating-point subtraction operation follows the subtraction(xy) operation specification in the IEEE 754-2008 standard.

+
+
+
+
FSUB.S:
+    FR[fd][31:0] = FP32_subtraction(FR[fj][31:0], FR[fk][31:0])
+
+FSUB.D:
+    FR[fd] = FP64_subtraction(FR[fj], FR[fk])
+
+
+
+

The FMUL.{S/D} instruction performs the operation that multiplies the single-precision/double-precision floating-point number in the floating-point register fj by the single-precision/double-precision floating-point number in the floating-point register fk, and writes the result of the single-precision/double-precision floating-point number To the floating-point register fd. +The floating-point multiplication operation follows the multiplication(xy) operation specification in the IEE 754-2008 standard.

+
+
+
+
FMUL.S:
+    FR[fd][31:0] = FP32_multiplication(FR[fj][31:0], FR[fk][31:0])
+
+FMUL.D:
+    FR[fd] = FP64_multiplication(FR[fj], FR[fk])
+
+
+
+

The FDIV.{S/D} instruction performs the operation that divides the single-precision/double-precision floating-point number in the floating-point register fj by the single-precision/double-precision floating-point number in the floating-point register fk, and writes the result of the single-precision/double-precision floating-point number To the floating-point register fd. +The floating-point division operation follows the division(x, y) operation specification in the IEEE 754-2008 standard.

+
+
+
+
FDIV.S:
+    FR[fd][31:0] = FP32_division(FR[fj][31:0], FR[fk][31:0])
+
+FDIV.D:
+    FR[fd] = FP64_division(FR[fj], FR[fk])
+
+
+
+

When the operand is a single-precision floating-point number, the upper 32 bits of the resulting floating-point register can be any value.

+
+
+
+
3.2.1.2. F{MADD/MSUB/NMADD/NMSUB}.{S/D}
+
+

Instruction formats:

+
+
+
+
fmadd.s     fd,fj,fk,fa
+fmadd.d     fd,fj,fk,fa
+fmsub.s     fd,fj,fk,fa
+fmsub.d     fd,fj,fk,fa
+fnmadd.s    fd,fj,fk,fa
+fnmadd.d    fd,fj,fk,fa
+fnmsub.s    fd,fj,fk,fa
+fnmsub.d    fd,fj,fk,fa
+
+
+
+

The FMADD.{S/D} instruction performs the operation that multiplies the single-precision/double-precision floating point number in floating point register fj with the single-precision/double-precision floating point number in floating point register fk. +The result is added to the single-precision/double-precision floating point number in the floating point register fa. +The result of the single-precision/double-precision floating point number is written to the floating point register fd

+
+
+
+
FMADD.S:
+    FR[fd][31:0] = FP32_fusedMultiplyAdd(FR[fj][31:0], FR[fk][31:0], FR[fa][31:0])
+
+FMADD.D:
+    FR[fd] = FP64_fusedMultiplyAdd(FR[fj], FR[fk], FR[fa])
+
+
+
+

The FMSUB.{S/D} instruction performs the operation that multiplies the single-precision/double-precision floating-point number in the floating-point register fj with the single-precision/double-precision floating-point number in the floating-point register fk, the result minus the floating-point register fa Single-precision/double-precision floating-point numbers, the single-precision/double-precision floating-point number results obtained are written into the floating-point register fd.

+
+
+
+
FMSUB.S:
+    FR[fd][31:0] = FP32_fusedMultiplyAdd(FR[fj][31:0], FR[fk][31:0], -FR[fa][31:0])
+
+FMSUB.D:
+    FR[fd] = FP64_fusedMultiplyAdd(FR[fj], FR[fk], -FR[fa])
+
+
+
+

The FNMADD.{S/D} instruction performs the operation that multiplies the single-precision/double-precision floating-point number in the floating-point register fj with the single-precision/double-precision floating-point number in the floating-point register fk, the result plus the single-precision/double-precision floating-point number in the floating-point register fa Precision/double-precision floating-point number, the obtained single-precision/double-precision floating-point number result is negative and written into the floating-point register fd.

+
+
+
+
FNMADD.S:
+    FR[fd][31:0] = -FP32_fusedMultiplyAdd(FR[fj][31:0], FR[fk][31:0], FR[fa][31:0])
+
+FNMADD.D:
+    FR[fd] = -FP64_fusedMultiplyAdd(FR[fj], FR[fk], FR[fa])
+
+
+
+

The FNMSUB.{S/D} instruction performs the operation that multiplies the single-precision/double-precision floating-point number in the floating-point register fj with the single-precision/double-precision floating-point number in the floating-point register fk, the result minus the floating-point register fa Single-precision/double-precision floating-point number, the result of the single-precision/double-precision floating-point number obtained is negative and written into the floating-point register fd.

+
+
+
+
FNMSUB.S:
+    FR[fd][31:0] = -FP32_fusedMultiplyAdd(FR[fj][31:0], FR[fk][31:0], -FR[fa][31:0])
+
+FNMSUB.D:
+    FR[fd] = -FP64_fusedMultiplyAdd(FR[fj], FR[fk], -FR[fa])
+
+
+
+

The above four floating-point fusion multiply-add operations follow the specification of the fusedMultiplyAdd(xy,z) operation in the IEEE 754-2008 standard.

+
+
+
+
3.2.1.3. F{MAX/MIN}{S/D}
+
+

Instruction formats:

+
+
+
+
fmax.s      fd, fj, fk
+fmax.d      fd, fj, fk
+fmin.s      fd, fj, fk
+fmin.d      fd, fj, fk
+
+
+
+

The FMAX.{S/D} instruction selects the larger of the single-precision/double-precision floating-point number in the floating-point register fj and the single-precision/double-precision floating-point number in the floating-point register fk to write into the floating-point register fd. +The operation of these two instructions follows the specification of maxNum(x,y) operation in the IEEE 754-2008 standard.

+
+
+
+
FMAX.S:
+    FR[fd][31:0] = FP32_maxNum(FR[fj][31:0], FR[fk][31:0])
+
+FMAX.D:
+    FR[fd] = FP64_maxNum(FR[fj], FR[fk])
+
+
+
+

The FMIN.{S/D} instruction selects the smaller of the single-precision/double-precision floating-point number in the floating-point register fj and the single-precision/double-precision floating-point number in the floating-point register fk to write into the floating-point register fd. +The operation of these two instructions follows the minNum(x,y) operation specification in the IEEE 754-2008 standard.

+
+
+
+
FMIN.S:
+    FR[fd][31:0] = FP32_minNum(FR[fj][31:0], FR[fk][31:0])
+
+FMIN.D:
+    FR[fd] = FP64_minNum(FR[fj], FR[fk])
+
+
+
+
+
3.2.1.4. F{MAXA/MINA}.{S/D}
+
+

Instruction formats:

+
+
+
+
fmaxa.s     fd, fj, fk
+fmaxa.d     fd, fj, fk
+fmina.s     fd, fj, fk
+fmina.d     fd, fj, fk
+
+
+
+

The FMAXA.{S/D} instruction selects the larger absolute value of the single-precision/double-precision floating-point number in the floating-point register fj and the single-precision/double-precision floating-point number in the floating-point register fk to write to the floating-point register fd. +The floating-point addition operation follows the specification of maxNumMag(x.v) operation in IEEE 754-2008 standard.

+
+
+
+
FMAXA.S:
+    FR[fd][31:0] = FP32_maxNumMag(FR[fj][31:0], FR[fk][31:0])
+
+FMAXA.D:
+    FR[fd] = FP64_maxNumMag(FR[fj], FR[fk])
+
+
+
+

The FMINA.{S/D} instruction selects the smaller absolute value of the single-precision/double-precision floating-point number in the floating-point register fj and the single-precision/double-precision floating-point number in the floating-point register fk to write to the floating-point register fd. +The floating-point addition operation follows the specification of minNumMag(x,y) operation in IEEE 754-2008 standard.

+
+
+
+
FMINA.S:
+    FR[fd][31:0] = FP32_minNumMag(FR[fj][31:0], FR[fk][31:0])
+
+FMINA.D:
+    FR[fd] = FP64_minNumMag(FR[fj], FR[fk])
+
+
+
+
+
3.2.1.5. F{ABS/NEG}.{S/D}
+
+

Instruction formats:

+
+
+
+
fabs.s      fd, fj
+fabs.d      fd, fj
+fneg.s      fd, fj
+fneg.d      fd, fj
+
+
+
+

The FABS.{S/D} instruction selects the single-precision/double-precision floating-point number in the floating-point register fj, takes its absolute value(that is, the symbol position is 0, and other parts remain unchanged), and writes it into the floating-point register fd. +Floating-point addition operations follow the specification of abs(x) operation in the EEE 754-2008 standard.

+
+
+
+
FABS.S:
+    FR[fd][31:0] = FP32_abs(FR[fj][31:0])
+
+FABS.D:
+    FR[fd] = FP64_abs(FR[fj])
+
+
+
+

The FNEG.{S/D} instruction selects the single-precision/double-precision floating-point number in the floating-point register fj, takes the opposite number(that is, inverts the sign bit, and other parts remain unchanged), and writes it into the floating-point register fd. +Floating-point addition operations follow the negate(x) operation specification in the EEE 754-2008 standard.

+
+
+
+
FNEG.S:
+    FR[fd][31:0] = FP32_negate(FR[fj][31:0])
+
+FNEG.D:
+    FR[fd] = FP64_negate(FR[fj])
+
+
+
+
+
3.2.1.6. F{SQRT/RECIP/RSQRT}.{S/D}
+
+

Instruction formats:

+
+
+
+
fsqrt.s         fd, fj
+fsqrt.d         fd, fj
+frecip.s        fd, fj
+frecip.d        fd, fj
+frsqrt.s        fd, fj
+frsqrt.d        fd, fj
+
+
+
+

These instructions are operations related to square root and reciprocal.

+
+
+

The FSQRT.{S/D} instruction selects the single-precision/double-precision floating-point number in the floating-point register fj, and writes the single-precision/double-precision floating-point number obtained after the square root to the floating-point register fd. +The floating-point root operation follows the squareRoot(x) operation specification in the IEEE 754-2008 standard.

+
+
+
+
FSQRT.S:
+    FR[fd][31:0] = FP32_squareRoot(FR[fj][31:0])
+
+FSQRT.D:
+    FR[fd] = FP64_squareRoot(FR[fj])
+
+
+
+

The FRECIP.{S/D} instruction selects the single-precision/double-precision floating-point number in the floating-point register fj, divides the floating-point number by 1.0, and writes the resulting single-precision/double-precision floating-point number into the floating-point register fd. +It is equivalent to the division(1.0, x) operation in the IEEE 754-2008 standard.

+
+
+
+
FRECIP.S:
+    FR[fd][31:0] = FP32_division(1.0,FR[fj][31:0])
+
+FRECIP.D:
+    FR[fd] = FP64_division(1.0,FR[fj])
+
+
+
+

The FRSQRT.{S/D} instruction selects the single-precision/double-precision floating-point number in the floating-point register fj, takes its square root and then divides the obtained single-precision/double-precision floating-point number by 1.0, and the obtained single-precision/double-precision floating-point number is written to the floating-point register fd. +The floating-point squared-inverse operation follows the specification of rSqrt(x) operation in IEEE 754-2008 standard.

+
+
+
+
FRSQRT.S:
+    FR[fd][31:0] = FP32_division(1.0, FP_squareRoot(FR[fj][31:0]))
+
+FRSQRT.D:
+    FR[fd] = FP64_division(1.0, FP_squareRoot(R[fj]))
+
+
+
+
+
3.2.1.7. F{SCALEB/LOGB/COPYSIGN}.{S/D}
+
+

Instruction formats:

+
+
+
+
fscaleb.s       fd, fj, fk
+fscaleb.d       fd, fj, fk
+flogb.s         fd, fj
+flogb.d         fd, fj
+fcopysign.s     fd, fj, fk
+fcopysign.d     fd, fj, fk
+
+
+
+

The FSCALEB.{S/D} instruction selects the single-precision/double-precision floating point number a in the floating point register fj, +Then take the word/double word integer N in the floating point register fk, and calculate a*2N, +The obtained single-precision/double-precision floating point number is written to the floating point register fd. +These two instructions follow the IEEE754-2008 standard scaleB(x, N) operation specification.

+
+
+
+
FSCALEB.S:
+    FR[fd][31:0] = FP32_scaleB(FR[fj][31:0], FR[fk][31:0])
+
+FSCALEB.D:
+    FR[fd] = FP64_scaleB(FR[fj], FR[fk])
+
+
+
+

The FLOGB.{S/D} instruction selects the single-precision/double-precision floating-point number in the floating-point register fj, calculates its logarithm based on 2, and writes the obtained single-precision/double-precision floating-point number into the floating-point register fd . +Floating-point exponential operations follow the specification of logB(x) operation in the IEEE 754-2008 standard.

+
+
+
+
FLOGB.S:
+    FR[fd][31:0] = FP32_logB(FR[fj][31:0])
+
+FLOGB.D:
+    FR[fd] = FP64_logB(FR[fj])
+
+
+
+

The FCOPYSIGN.{S/D} instruction selects the single-precision/double-precision floating-point number in the floating-point register fj, and changes its sign bit to the sign bit of the single-precision/double-precision floating-point number in the floating-point register fk, and the new one is obtained Single-precision/double-precision floating-point numbers are written into the floating-point register fd. +The floating-point copy sign operation follows the specification of copySign(x, y) operation in the IEEE 754-2008 standard.

+
+
+
+
FCOPYSIGN.S:
+    FR[fd][31:0] = FP32_copySign(FR[fi][31:01, FR[fk][31:0]])
+
+FCOPYSIGN.D:
+    FR[fd] = FP64_copySign(FR[fj], FR[fk])
+
+
+
+
+
3.2.1.8. FCLASS.{S/D}
+
+

Instruction formats:

+
+
+
+
fclass.s    fd, fj
+fclass.d    fd, fj
+
+
+
+

This instruction judges the category of the floating-point number in the floating-point register fj. +The result of the judgment is composed of 10 bits of information. +The meaning of each bit is shown in the following table:

+
+ + ++++++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 8. Results of floating-point classification
Bit 0Bit 1Bit 2Bit 3Bit 4Bit 5Bit 6Bit 7Bit 8Bit 9

SNaN

QNaN

Negative value

Positive value

∞

Normal

Subnormal

0

∞

Normal

Subnormal

0

+
+

When the determined data meets the condition corresponding to a certain bit, the corresponding bit of the result information vector will be set to 1. +This instruction corresponds to the class(x) function in the IEEE-754-2008 standard.

+
+
+
+
FCLASS.S:
+    FR[fd][31:0] = FP32_class(FR[fj][31:0])
+
+FCLASS.D:
+    FR[fd] = FP64_class(FR[fj])
+    sedMultiplyAdd(FR[fj], FR[fk], FR[fa])
+
+
+
+
+
3.2.1.9. F{RECIPE/RSQRTE}.{S/D}
+
+

Instruction formats:

+
+
+
+
frecipe.s           fd, fj
+frecipe.d           fd, fj
+frsqrte.s           fd, fj
+frsqrte.d           fd, fj
+
+
+
+

The FRECIPE.{S/D} instruction selects the single-precision or double-precision floating-point number in the floating-point register fj, calculates the single-precision or double-precision floating-point number approximation obtained by dividing the floating-point number by 1.0, and writes the approximation to the floating-point register fd . The relative error of the approximation is less than 2^-14.

+
+
+

When the input value is 2^N, the output value is 2^-N. The results when the input value is QNaN, SNaN, ±∞, ±0, the conditions for generating floating-point exceptions, and the default results when floating-point exceptions are generated without triggering exceptions are the same as those of the FRECIP.{S/D} instruction.

+
+
+
+
FRECIPE.S:
+    FR[fd][31:0] = FP32_reciprocal_estimate(FR[fj][31:0])
+FRECIPE.D:
+    FR[fd] = FP64_reciprocal_estimate(FR[fj])
+
+
+
+

FRSQRTE.{S/D} instruction selects the single/double precision floating point number in the floating point register fj, first extract the Square Root it, and then divides the approximate result by 1.0, and then writes the obtained single/double precision floating point number into the floating point register fd. The relative error of the obtained approximation is less than 2^-14.

+
+
+

When the input value is 2^2N, the output value is 2^-N. The results when the inputs are QNaN, SNaN, ±∞, and ±0, the conditions for generating floating-point exceptions, and the default results when floating-point exceptions are generated but not triggered are the same as those of the FRSQRT.{S/D} instruction.

+
+
+
+
FRSQRTE.S:
+    FR[fd][31:0] = FP32_reciprocal_squareroot_estimate(FR[fj][31:0])
+FRSQRTE.D:
+    FR[fd] = FP64_reciprocal_squareroot_estimate(FR[fj])
+
+
+
+
+
+

3.2.2. Floating-Point Comparison Instructions

+
+
3.2.2.1. FCMP.cond.{S/D}
+
+

Instruction formats:

+
+
+
+
fcmp.cond.s    cc, fj, fk
+fcmp.cond.d    cc, fj, fk
+
+
+
+

This is a floating-point comparison instruction, which stores the result of the comparison into the specified status code (CC). +There are 22 types of cond for this instruction. +These comparison conditions and judgment standards are listed in the following table.

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 9. Floating-point comparison conditions and judgment standards
MnemonicCondMeaningTrue ConditionQNaN ExceptionIEEE 754-2008 Funtion

CAF

0x0

None

None

No

CUN

0x8

Incomparable

UN

compareQuietUnordered

CEQ

0x4

Equal

EQ

compareQuietEqual

CUEQ

0xC

Equal or incomparable

UN EQ

CLT

0x2

Less than

IT

compareQuietLess

CULT

0xA

Less than or incomparable

UN LT

compareQuietLessUnordered

CLE

0x6

Less than or equal to

LT EQ

compareQuietLessEqual

CULE

0xE

Less than or equal to or incomparable

UN LT EQ

compareQuietNotGreater

CNE

0x10

Vary

GT LT

COR

0x14

Orderly

GT LT EQ

CUNE

0x18

Incomparable or unequal

UN GT LT

compareSignalingNotEqual

SAF

0x1

None

None

Yes

SUN

0x9

Is not greater than or equal to

UN

SEQ

0x5

equal

EQ

compareSignalingEqual

SUEQ

0xD

Not greater than or less than

UN EQ

SLT

0x3

Less than

IT

compareSignalingLess

SULT

0xB

Is not greater than or equal to

UN LT

compareSignalingLessUnordered

SLE

0x7

Less than or equal to

IT EQ

compareSignalingLessEqual

SULE

0xF

Not greater than

UN LT EQ

compareSignalingNotGreater

SNE

0x11

Vary

GT LT

SOR

0x15

Orderly

GT LT EQ

SUNE:

0x19

Incomparable or unequal

UN GT LT

+
+

Note: UN means no comparison, EQ means equal, IT means less than. +When there is at least one NaN in two operands, the two numbers cannot be compared.

+
+
+
+
+

3.2.3. Floating-Point Conversion Instructions

+
+
3.2.3.1. FCVT.S.D, FCVT.D.S
+
+

Instruction formats:

+
+
+
+
fcvt.s.d    fd, fj
+fcvt.d.s    fd, fj
+
+
+
+

The FCVT.S.D instruction performs the operation that the double-precision floating-point number in the floating-point register fj to be converted into a single-precision floating-point number, and the obtained single-precision floating-point number is written into the floating-point register fd.

+
+
+
+
FCVT.S.D:
+    FR[fd][31:0] = FP32_convertFormat(FR[fj], FP64)
+
+
+
+

The FCVT.D.S instruction performs the operation that the single-precision floating-point number in the floating-point register fj to be converted into a double-precision floating-point number, and the obtained double-precision floating-point number is written into the floating-point register fd.

+
+
+
+
FCVT.D.S:
+    FR[fd] = FP64_convertFormat(FR[fj][31:0], FP32)
+
+
+
+

The floating-point format conversion operation follows the specification of the convertFormat(x) operation in the IEEE 754-2008 standard.

+
+
+
+
3.2.3.2. FFINT{S/D}.{W/L}, FTINT.{W/L}.{S/D}
+
+

Instruction formats:

+
+
+
+
ffint.s.w       fj
+ffint.s.I       fj
+ffint.d.w       fj
+ffint.d.I       fj
+ftint.w.s       fj
+ftint.w.d       fj
+ftint.l.s       fj
+ftint.l.d       fj
+
+
+
+

The FFINT{S/D}.{W/L} instruction selects the integer/long-integer fixed-point number in the floating-point register fj and converts it into a single-degree/double-precision floating-point number, and the obtained single-precision/double-precision floating-point number is written to Floating-point register fd. +This floating-point format conversion operation follows the convertFromInt(x) operation specification in the EEE 754-2008 standard.

+
+
+
+
FFINT.S.W:
+    FR[fd][31:0] = FP32_convertFromInt(FR[fj][31:0], SINT32)
+
+FFINT.S.L:
+    FR[fd][31:0] = FP32_convertFromInt(FR[fj], SINT64)
+
+FFINT.D.W:
+    FR[fd] = FP64_convertFromInt(FR[fj][31:0], SINT32)
+
+FFINT.D.L:
+    FR[fd] = FP64_convertFromInt(FR[fj], SINT64)
+
+
+
+

FTINT{W/L}.{S/D} instruction selects the single-degree/double-precision floating-point number in the floating-point register fj to be converted into an integer/long-integer fixed-point number, and the obtained integer/long-integer fixed-point number is written To the floating-point memory fd. +According to the different states in FCSR, the operations in the IEEE 754-2008 standard followed by this floating-point format conversion operation are shown in the following table.

+
+ + +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 10. Standard for converting to integer
Rounding modeWhether to report floating-point imprecision exceptionsIEEE 754-2008 Function

Round to the nearest even number

Yes

convertToIntegerTiesToEven(X)

Round towards zero

convertToIntegerTowardZero(x)

Round towards positive infinity

convertToIntegerTowardPositive(x)

Round towards negative infinity

converrtToIntegerTowardNegative(x)

Round to the nearest even number

No

convertToIntegerExactTiesToEven(x)

Round towards zero

convertToIntegerExactTowardZero(x)

Round towards positive infinity

convertToIntegerExactTowardPositive(x)

Round towards negative infinity

convertToIntegerExactTowardNegative(x)

+
+
+
FTINT.W.S:
+    FR[fd][31:0] = FP32convertToSint32(FR[fj][31:0], FCSR.Enables.I, FCSR.RM)
+
+FTINT.W.D:
+    FR[fd] = FP64convertToSint32(FR[fj], FCSR.Enables.I, FCSR.RM)
+
+FTINT.L.S:
+    FR[fd][31:0] = FP32convertToSint64(FR[fj][31:0], FCSR.Enables.I, FCSR.RM)
+
+FTINT.L.D:
+    FR[fd] = FP64convertToSint64(FR[fj], FCSR.Enables.I, FCSR.RM)
+
+
+
+
+
3.2.3.3. FTINT{RM/RP/RZ/RNE}.{W/L}.{S/D}
+
+

Instruction formats:

+
+
+
+
ftintrm.w.s     fd, fj
+ftintrm.w.d     fd, fj
+ftintrm.l.s     fd, fj
+ftintrm.l.d     fd, fj
+ftintrp.w.s     fd, fj
+ftintrp.w.d     fd, fj
+ftintrp.l.s     fd, fj
+ftintrp.l.d     fd, fj
+ftintrz.w.s     fd, fj
+ftintrz.w.d     fd, fj
+ftintrz.l.s     fd, fj
+ftintrz.l.d     fd, fj
+ftintrne.w.s    fd, fj
+ftintrne.w.d    fd, fj
+ftintrne.l.s    fd, fj
+ftintrne.l.d    fd, fj
+
+
+
+

These instructions convert floating-point numbers to fixed-point numbers with the specified rounding pattern. +FTINTRM.{W/L}.{S/D} instruction selects the single-precision/double-precision floating-point number in the floating-point register fj and converts it to integer-type long integer-type fixed point number, and the resulting integer-type/long integer-type fixed point number is written to the floating-point register fd, using the “round to negative infinity” mode.

+
+
+
+
FTINTRM.W.S:
+    FR[fd][31:0] = FP32convertToSint32(FR[fj][31:0], FCSR.Enables.I, 3)
+
+FTINTRM.W.D:
+    FR[fd] = FP64convertToSint32(FR[fj], FCSR.Enables.I, 3)
+
+FTINTRM.L.S:
+    FR[fd][31:0] = FP32convertToSint64(FR[fj][31:0], FCSR.Enables.I, 3)
+
+FTINTRM.L.D:
+    FR[fd] = FP64convertToSint64(FR[fj], FCSR.Enables.I, 3)
+
+
+
+

FTINTRP.{W/L}.{S/D} instruction selects the single-precision/double-precision floating-point number in the floating-point register fj, converts it to integer/long-integer fixed point number, and writes the integer/long-integer fixed point number into the floating-point register fd, using the "rounding to positive infinity" method.

+
+
+
+
FTINTRP.W.S:
+    FR[fd][31:0] = FP32convertToSint32(FR[fj][31:0], FCSR.Enables.I, 2)
+
+FTINTRP.W.D:
+    FR[fd] = FP64convertToSint32(FR[fj], FCSR.Enables.I, 2)
+
+FTINTRP.L.S:
+    FR[fd][31:0] = FP32convertToSint64(FR[fj][31:0], FCSR.Enables.I, 2)
+
+FTINTRP.L.D:
+    FR[fd] = FP64convertToSint64(FR[fj], FCSR.Enables.I, 2)
+
+
+
+

FTINTRZ.{W/L}.{S/D} instruction selects the single-degree/double-precision floating-point number in floating-point register fj, converts it to integer/long-integer fixed-point number, and writes the obtained integer/long-integer fixed-point number to floating-point register fd, using the "rounding to zero" method.

+
+
+
+
FTINTRZ.W.S:
+    FR[fd][31:0] = FP32convertToSint32(FR[fj][31:0], FCSR.Enables.I, 1)
+
+FTINTRZ.W.D:
+    FR[fd] = FP64convertToSint32(FR[fj], FCSR.Enables.I, 1)
+
+FTINTRZ.L.S:
+    FR[fd][31:0] = FP32convertToSint64(FR[fj][31:0], FCSR.Enables.I, 1)
+
+FTINTRZ.L.D:
+    FR[fd] = FP64convertToSint64(FR[fj], FCSR.Enables.I, 1)
+
+
+
+

FTINTRNE.{W/L}{S/D} instruction selects the single-precision/double-precision floating-point number in floating-point register fj, converts it to integer long integer fixed point number, and writes the obtained integer/long-integer fixed point number to floating-point register fd, using the "rounding to the nearest even number" method.

+
+
+
+
FTINTRNE.W.S:
+    FR[fd][31:0] = FP32convertToSint32(FR[fj][31:0], FCSR.Enables.I, 0)
+
+FTINTRNE.W.D:
+    FR[fd] = FP64convertToSint32(FR[fj], FCSR.Enables.I, 0)
+
+FTINTRNE.L.S:
+    FR[fd][31:0] = FP32convertToSint64(FR[fj][31:0], FCSR.Enables.I, 0)
+
+FTINTRNE.L.D:
+    FR[fd] = FP64convertToSint64(FR[fj], FCSR.Enables.I, 0)
+
+
+
+

The operations in the IEEE 754-2008 standard that the above four floating-point format conversion operations follow are shown in the following table.

+
+ + +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 11. Standard for floating-point conversion
Instruction nameWhether to report floating-point imprecision exceptionsIEEE 754-2008 Function

FTINTRNE.{W/L}.{S/D}

Yes

convertToIntegerExactTiesToEven(x)

FTINTRZ.{W/L}.{S/D}

convertToIntegerExactTowardZero(x)

FTINTRP.{W/L}.{S/D}

convertToIntegerExactTowardPositive(x)

FTINTRM.{W/L}{S/D}

convertToIntegerExactTowardNegative(x)

FTINTRNE.{W/L}.{S/D}

No

convertToIntegerTiesToEven(x)

FTINTRZ.{W/L}.{S/D}

convertToIntegerTowardZero(x)

FTINTRP{W/L}.{S/D}

convertToIntegerTowardPositive(x)

FTINTRM.{W/L}.{S/D}

convertToIntegerTowardNegative(x)

+
+
+
3.2.3.4. FRINT.{S/D}
+
+

Instruction formats:

+
+
+
+
frint.s    fd, fj
+frint.d    fd, fj
+
+
+
+

The FRINT.{S/D} instruction selects the single-precision/double-precision floating-point number in the floating-point register fj and converts it to a single-precision/double-precision floating-point number with integer value, and the resulting single-precision/double-precision floating-point number is written to the floating-point register fd. +According to the different states in FCSR, this floating-point format conversion operation follows the operation in IEEE 7542008 standard as shown in the following table.

+
+ + +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 12. Standard for rounding to integer
Rounding modeWhether to report floating-point imprecision exceptionsIEEE 754-2008 Function

Round to the nearest even number

Yes

roundToIntegralExact(x)

Round towards zero

Round towards positive infinity

Round towards negative infinity

Round to the nearest even number

No

roundToIntegerTiesToEven(x)

Round towards zero

roundToIntegerTowardZero(x)

Round towards positive infinity

roundToIntegerTowardPositive(x)

Round towards negative infinity

roundToInteger TowardNegative(x)

+
+
+
FRINT.S:
+    FR[fd][31:0] = FP32_roundToInteger(FR[fj], FCSR.Enables.I, FCSR.RM)
+
+FRINT.D:
+    FR[fd] = FP64_roundToInteger(FR[fj], FCSR.Enables.I, FCSR.RM)
+
+
+
+
+
+

3.2.4. Floating-Point Move Instructions

+
+
3.2.4.1. FMOV.{S/D}
+
+

Instruction formats:

+
+
+
+
fmov.s      fd, fj
+fmov.d      fd, fj
+
+
+
+

FMOV{S/D} writes the value of the floating-point register fj into the floating-point register fd in the single-precision/double-precision floating-point number format. +If the value of fj is not in the single-precision/double-precision floating-point number format, the result is uncertain.

+
+
+
+
FMOV.S:
+    FR[fd][31:0] = FR[fj][31:0]
+
+FMOV.D:
+    FR[fd] = FR[fj]
+
+
+
+

The above instruction operations are non-arithmetic and will not cause IEEE 754 exceptions, nor will they modify the Cause and Flags fields of the floating-point control and status register.

+
+
+
+
3.2.4.2. FSEL
+
+

Instruction formats:

+
+
+
+
fsel        fd, fj, fk, ca
+
+
+
+

The FSEL instruction performs conditional assignment operations.

+
+
+

When FSEL is executed, if the value of the condition flag register ca is equal to 0, the value of the floating-point register fj is written into the floating-point register fd, otherwise the value of the floating-point register fk is written into the floating-point register fd.

+
+
+
+
FSEL:
+    FR[fd] = CFR[ca] ? FR[fk] : FR[fj]
+
+
+
+
+
3.2.4.3. MOVGR2FR.{W/D}, MOVGR2FRH.W
+
+

Instruction formats:

+
+
+
+
movgr2fr.w      fd, rj
+movgr2fr.d      fd, rj
+movgr2frh.w     fd, rj
+
+
+
+

MOVGR2FR.W writes the low 32-bit value of the general register rj into the low 32-bit of the floating-point register fd. +If the length of the floating-point register is 64 bits, the high 32-bit value of fd is uncertain.

+
+
+
+
MOVGR2FR.W:
+    FR[fd][31:0] = GR[rj][31:0]
+
+
+
+

MOVGR2FRH.W writes the low 32-bit value of the general register rj into the high 32-bit of the floating-point register fd, and the low 32-bit value of the floating-point register fd remains unchanged.

+
+
+
+
MOVGR2FRH.W:
+    FR[fd][63:32] = GR[rj][31:0]
+    FR[fd][31: 0] = FR[fd][31:0]
+
+
+
+

MOVGR2FR.D writes the 64-bit value of general register rj into floating-point register fd.

+
+
+
+
MOVGR2FR.D:
+    FR[fd] = GR[rj]
+
+
+
+
+
3.2.4.4. MOVFR2GR.{S/D}, MOVFRH2GR.S
+
+

Instruction formats:

+
+
+
+
movfr2gr.s      rd, fj
+movfr2gr.d      rd, fj
+movfrh2gr.s     rd, fj
+
+
+
+

MOVFR2GRMOVFRH2GR.S sign extensions the low/high 32-bit value of the floating-point register fj and writes it into the general register rd.

+
+
+
+
MOVFR2GR.S:
+    GR[rd] = SignExtend(FR[fj][31: 0], GRLEN)
+
+MOVFRH2GR.S:
+    GR[rd] = SignExtend(FR[fj][63:32], GRLEN)
+
+
+
+

MOVFR2GR.D writes the 64-bit value of the floating-point register fj into the general register rd.

+
+
+
+
MOVFR2GR.D:
+    GR[rd] = FR[fj]
+
+
+
+
+
3.2.4.5. MOVGR2FCSR, MOVFCSR2GR
+
+

Instruction formats:

+
+
+
+
movgr2fcsr      fcsr, rj
+movfcsr2gr      rd,   fcsr
+
+
+
+

MOVGR2FCSR modifies the value of the software writable field corresponding to the floating-point control and status register indicated by fcsr according to the value of the lower 32 bits of the general register rj. +If the MOVGR2FCSR instruction modifies FCSR0 so that the bits of the Cause field and the corresponding Enables bit are both 1, or modify the Enables field of FCSR1 and the Cause field of FCSR2 so that the Cause bit and the corresponding Enables bit are both 1, the M0VGR2FCSR instruction itself No floating-point exception will be triggered.

+
+
+
+
MOVGR2FCSR:
+    FCSR[fcsr] = GR[rd][31:0]
+
+
+
+

MOVFCSR2GR sign extensions the 32-bit value of the floating-point control and status register indicated by fcsr and writes it into the general register rd.

+
+
+
+
MOVFCSR2GR:
+    GR[rd] = SignExtend(FCSR[fcsr], GRLEN)
+
+
+
+

If the floating-point control and status register indicated by fcsr in the above instruction does not exist, the result is uncertain.

+
+
+
+
3.2.4.6. MOVFR2CF, MOVCF2FR
+
+

Instruction formats:

+
+
+
+
movfr2cf        cd, fj
+movcf2fr        fd, cj
+
+
+
+

MOVFR2CF writes the value of the lowest bit of the floating-point register fj into the condition flag register cd.

+
+
+
+
MOVFR2CF:
+    CFR[cd] = FR[fj][0]
+
+
+
+

MOVCF2FR writes the value of the condition flag register cj into the lowest bit of the floating-point register fd.

+
+
+
+
MOVCF2FR:
+    FR[fd][0] = CFR[cj]
+
+
+
+
+
3.2.4.7. MOVGR2CF, MOVCF2GR
+
+

Instruction formats:

+
+
+
+
movgr2cf    cd, rj
+movcf2gr    rd, cj
+
+
+
+

MOVGR2CF writes the value of the lowest bit of the general register rj into the condition flag register cd.

+
+
+
+
MOVGR2CF:
+    CFR[cd] = GR[rj][0]
+
+
+
+

MOVCF2GR writes the value of the condition flag register cj into the lowest bit of the general register rd and clears the other bits.

+
+
+
+
MOVCF2GR:
+    GR[rd][0] = CFR[cj]
+
+
+
+
+
+

3.2.5. Floating-Point Branch Instructions

+
+
3.2.5.1. BCEQZ, BCNEZ
+
+

Instruction formats:

+
+
+
+
bceqz   cj, offs21
+bcnez   cj, offs21
+
+
+
+

BCEQZ judges the value of the condition flag register cj, if it is equal to 0, jump to the target address, otherwise it does not jump. +BCNEZ judges the value of the condition flag register cj, if it is not equal to 0, jump to the target address, otherwise it does not jump. +The jump target address of the above two branch instructions is to logically shift the 21-bit immediate offs21 in the instruction code to the left by 2 bits and then sign extension, and the resulting offset value plus the PC of the branch instruction.

+
+
+
+
BCEQZ:
+    if CFR[cj] == 0:
+        PC = PC + SignExtend({offs21, 2'b0}, GRLEN)
+
+BCNEZ:
+    if CFR[cj] != 0:
+        PC = PC + SignExtend({offs21, 2'b0}, GRLEN)
+
+
+
+ + + + + +
+
Tip
+		 +
+

When writing assembly, you need to fill in the immediate field with the real offset value in bytes, i.e. (offs21<<2).

+
+
+
+
+
+
+

3.2.6. Floating-Point Common Memory Access Instructions

+
+
3.2.6.1. FLD.{S/D}, FST.{S/D}
+
+

Instruction formats:

+
+
+
+
flds    fd, rj, si12
+fld.d   fd, rj, si12
+fst.s   fd, rj, si12
+fst.d   fd, rj, si12
+
+
+
+

FLD.S retrieves a word of data from the internal memory and writes it into the lower 32 bits of the floating-point register fd. +If the length of the floating-point register is 64 bits, the high 32-bit value of fd is uncertain.

+
+
+

FLD.D retrieves a double word from the internal memory and writes it into the floating-point register fd.

+
+
+

FST.S writes the low 32-bit word data in the floating-point register fd into the memory.

+
+
+

FST.D writes double-word data in the floating-point register fd into the memory.

+
+
+

The access address of the above instruction is calculated by summing the value in the general register rj with the symbolically expanded 12-bit immediate number si12.

+
+
+

FLD.{S/D} and FST.{S/D} instructions, regardless of the hardware implementation and environment configuration, as long as the access address is naturally aligned, the non-alignment exception will not be triggered; when the access address is not naturally aligned, if the hardware implementation supports non-aligned access and the current computing environment is configured to allow non-aligned access, then the non-alignment exception will not be triggered; otherwise, the non-alignment exception will be triggered. +Otherwise, the non-alignment exception will be triggered.

+
+
+
+
FLD.S:
+    vaddr = GR[rj] + SignExtend(si12, GRLEN)
+    AddressComplianceCheck(vaddr)
+    paddr = AddressTranslation(vaddr)
+    word = MemoryLoad(paddr, WORD)
+    FR[fd][31:0] = word
+
+FLD.D:
+    vaddr = GR[rj] + SignExtend(si12, GRLEN)
+    AddressComplianceCheck(vaddr)
+    paddr = AddressTranslation(vaddr)
+    doubleword = MemoryLoad(paddr, DOUBLEWORD)
+    FR[fd] = doubleword
+
+FST.S:
+    vaddr = GR[rj] + SignExtend(si12, GRLEN)
+    AddressComplianceCheck(vaddr)
+    paddr = AddressTranslation(vaddr)
+    MemoryStore(FR[fd][31:0], paddr, WORD)
+
+FST.D:
+    vaddr = GR[rj] + SignExtend(si12, GRLEN)
+    AddressComplianceCheck(vaddr)
+    paddr = AddressTranslation(vaddr)
+    MemoryStore(FR[fd][63:0], paddr, DOUBLEWORD)
+
+
+
+
+
3.2.6.2. FLDX.{S/D}, FSTX.{S/D}
+
+

Instruction formats:

+
+
+
+
fldx.s  fd, rj, rk
+fldx.d  fd, rj, rk
+fstx.s  fd, rj, rk
+fstx.d  fd, rj, rk
+
+
+
+

FLDX.S retrieves a word of data from the memory and writes it into the lower 32 bits of the floating-point register fd. +If the length of the floating-point register is 64 bits, the high 32-bit value of fd is uncertain.

+
+
+

FLDX.D retrieves a double word of data from the memory and writes it into the floating-point register fd.

+
+
+

FSTX.S writes the low 32-bit word data in the floating-point register fd into the memory.

+
+
+

FSTX.D writes the double word data in the floating-point register fd into the memory.

+
+
+

The memory access address calculation method of the above instruction is to add sum the value in the general register rj and the value in the general register rk.

+
+
+

For FLDX.{S/D} and FSTX.{S/D} instructions, no matter what kind of hardware implementation and environmental configuration, as long as the memory access address is naturally aligned, the non-aligned exception will not be triggered; When the memory address is not naturally aligned, if the hardware implementation supports unaligned memory access and the current computing environment is configured to allow unaligned memory access, then the unaligned exception will not be triggered, otherwise it will trigger the unaligned exception.

+
+
+
+
FLDX.S:
+    vaddr = GR[rj] + GR[rk]
+    AddressComplianceCheck(vaddr)
+    paddr = AddressTranslation(vaddr)
+    word = MemoryLoad(paddr, WORD)
+    FR[fd][31:0] = word
+
+FLDX.D:
+    vaddr = GR[rj] + GR[rk]
+    AddressComplianceCheck(vaddr)
+    paddr = AddressTranslation(vaddr)
+    doubleword = MemoryLoad(paddr, DOUBLEWORD)
+    FR[fd] = doubleword
+
+FSTX.S:
+    vaddr = GR[rj] + GR[rk]
+    AddressComplianceCheck(vaddr)
+    paddr = AddressTranslation(vaddr)
+    MemoryStore(FR[fd][31:0], paddr, WORD)
+
+FSTX.D:
+    vaddr = GR[rj] + GR[rk]
+    AddressCompli anceCheck(vaddr)
+    paddr = AddressTranslation(vaddr)
+    MemoryStore(FR[fd][63:0], paddr, DOUBLEWORD)
+
+
+
+
+
+

3.2.7. Floating-Point Bound Check Memory Access Instructions

+
+
3.2.7.1. FLD{GT/LE}.{S/D}, FST{GT/LE}.{S/D}
+
+

Instruction formats:

+
+
+
+
fldgt.s     fd, rj, rk
+fldgt.d     fd, rj, rk
+fldle.s     fd, rj, rk
+fldle.d     fd, rj, rk
+fstgt.s     fd, rj, rk
+fstgt.d     fd, rj, rk
+fstle.s     fd, rj, rk
+fstle.d     fd, rj, rk
+
+
+
+

FLD{GT/LE}.{S/D} determines if the valid address is out of bounds and writes the value from memory to the floating-point register.

+
+
+

FLD{GT/LE}.S checks if the value in general register rj is greater/less than/equal to the value in general register rk, and if the condition is met, fetches a word of data from memory and writes it to the lower 32 bits of floating-point register fd. +If the floating-point register is 64 bits wide, the high 32-bit value of fd is not determined.

+
+
+

FLD{GT/LE}.D checks if the value in general register rj is greater than/less than/equal to the value in general register rk, and if the condition is met, fetches a double word of data from memory and writes it to floating-point register fd.

+
+
+

FST{GT/LE}.{S/D} determines if the valid address is out of bounds, and writes the value of the floating-point register to memory.

+
+
+

FST{GT/LE}.S checks if the value in general register rj is greater/less than/equal to the value in general register rk, and if the condition is met, writes the low 32-bit word data in floating-point register fd to memory.

+
+
+

FST{GT/LE}.D checks if the value in general register rj is greater than/less than or equal to the value in general register rk, and if the condition is satisfied, writes the double word data in floating-point register fd to memory.

+
+
+

The access address of the above instruction comes directly from the value in general register rj. +The access addresses of the above instructions are required to be naturally aligned, otherwise a non-alignment exception will be triggered. +The above instruction terminates the access operation and triggers the bound check exception if the check condition is not satisfied.

+
+
+
+
FLDGT.S:
+    vaddr = GR[rj]
+    AddressComplianceCheck(vaddr)
+    paddr = AddressTranslation(vaddr)
+    if GR[rj] > GR[rk]:
+        word = MemoryLoad(paddr, WORD)
+        FR[fd][31:0] = word
+    else:
+        RaiseException(BCE)    # Bound Check Exception
+
+FLDGT.D:
+    vaddr = GR [rj]
+    AddressComplianceCheck(vaddr)
+    paddr = AddressTranslation(vaddr)
+    if GR[rj] > GR[rk]:
+        FR[fd] = MemoryLoad(paddr, DOUBLEWORD)
+    else:
+        RaiseException(BCE)    # Bound Check Exception
+
+FLDLE.S:
+    vaddr = GR[rj]
+    AddressComplianceCheck(vaddr)
+    paddr = AddressTranslation(vaddr)
+    if GR[rj] <= GR[rk]:
+        word = MemoryLoad(paddr, WORD)
+        FR[fd][31:0] = word
+    else:
+        RaiseException(BCE)    # Bound Check Exception
+
+FLDLE.D:
+    vaddr = GR[rj]
+    AddressComplianceCheck(vaddr)
+    paddr = AddressTranslation(vaddr)
+    if GR[rj] <= GR[rk]:
+        FR[fd] = MemoryLoad(paddr, DOUBLEWORD)
+    else:
+        RaiseException(BCE)    # Bound Check Exception
+
+FSTGT.S:
+    vaddr = GR[rj]
+    AddressComplianceCheck(vaddr)
+    paddr = AddressTranslation(vaddr)
+    if GR[rj] > GR[rk]:
+        MemoryStore(FR[fd][31:0], paddr, WORD)
+    else:
+        RaiseException(BCE)    # Bound Check Exception
+
+FSTGT.D:
+    vaddr = GR[rij]
+    AddressComplianceCheck(vaddr)
+    paddr = AddressTranslation(vaddr)
+    if GR[rj] > GR[rk]:
+        MemoryStore(FR[fd][63:0], paddr, DOUBLEWORD)
+    else:
+        RaiseException(BCE)    # Bound Check Exception
+
+FSTLE.S:
+    vaddr = GR[rj]
+    AddressComplianceCheck(vaddr)
+    paddr = AddressTranslation(vaddr)
+    if GR[rj] <= GR[rk]:
+        MemoryStore(FR[fd][31:0], paddr, WORD)
+    else:
+        RaiseException(BCE)    # Bound Check Exception
+
+FSTLE.D:
+    vaddr = GR[rj]
+    AddressComplianceCheck(vaddr)
+    paddr = AddressTranslation(vaddr)
+    if GR[rj] <= GR[rk]:
+        MemoryStore(FR[fd][63:0], paddr, DOUBLEWORD)
+    else:
+        RaiseException(BCE)    # Bound Check Exception
+
+
+
+
+
+
+
+
+

4. Overview of Privileged Resources

+
+
+

4.1. Privilege Levels

+
+

The processor cores are divided into four privilege levels (PLV0 to PLV3), which are uniquely determined by the value of the PLV field in CSR.CRMD.

+
+
+

Among all privilege levels, PLV0 is the privilege level with the highest privilege and is the only privilege level that can use privileged instructions and access all privileged resources. +The three privilege levels, PLV1 to PLV3, cannot execute privileged instructions to access privileged resources, but the three privilege levels have different access rights under the MMU’s mapped address translation mode.

+
+
+

For Linux systems, only the PLV0 level can correspond to the kernel state in the architecture, while the PLV3 level is recommended for the user state.

+
+
+
+

4.2. Overview of Privilege Instructions

+
+

All privileged instructions are accessible only at the PLV0 privilege level. +The only exception is that when the RPERF1/RPERF2/RPERF3 in CSR.MISC is configured to 1, the CSRRD instruction can be executed at PLV1/PLV2/PLV3 privilege level to read the performance counter.

+
+
+

4.2.1. CSR Access Instructions

+
+

Instruction formats:

+
+
+
+
csrrd       rd, csr_num
+csrwr       rd, csr_num
+csrxchg     rd, rj, csr_num
+
+
+
+

The CSRRD, CSRWR, and CSRXCHG instructions are used to access the CSRs in software. +The CSRRD instruction writes the value of the specified CSR to the general register rd. +The CSRWR instruction writes the old value of the general register rd to the specified CSR and updates the old value of the specified CSR to the general register rd. +The CSRXCHG instruction writes the old value of the general register rd to the bits of the specified CSR corresponding to the write mask 1 according to the write mask information stored in the general register rj. +The CSRXCHG instruction writes the old value of the general register rd to the bits of the specified CSR corresponding to the write mask of 1 according to the write mask information stored in the general register rj. +The rest of the bits in the CSR remain unchanged, and the old value of the CSR is updated to the general register rd.

+
+
+

All CSRs are addressed independently. +The addressable value of the CSRs in the above instruction is derived from the 14-bit immediate csr_num in the instruction. +csr_num for CSR 0 is 0, csr_num for CSR 1 is 1, and so on.

+
+
+

The length of all CSR registers is either 32 bits or equal to the length of GR in the architecture, so CSR access instructions do not distinguish between lengths. +In LA32, all CSRs are naturally 32 bits wide. +In LA64, CSRs with a fixed 32-bit length in the definition are always written to the general purpose register rd after symbolic expansion.

+
+
+

When a CSR access instruction accesses a CSR that is not defined in the architecture or not implemented in hardware, the read operation returns an all 0 values and the write operation does not modify any software-visible state of the processor.

+
+
+
+

4.2.2. IOCSR Access Instructions

+
+
4.2.2.1. IOCSR{RD/WR}.{B/H/W/D}
+
+

Instruction formats:

+
+
+
+
iocsrrd.b       rd, rj
+iocsrrd.h       rd, rj
+iocsrrd.w       rd, rj
+iocsrrd.d       rd, rj
+iocsrwr.b       rd, rj
+iocsrwr.h       rd, rj
+iocsrwr.w       rd, rj
+iocsrwr.d       rd, rj
+
+
+
+

I0CSR{RD/WR}.{B/H/W/D} instructions are used to access the IOCSR.

+
+
+

All IOCSR registers use independent addressing space, and the basic unit of addressing is byte. +All data is stored in the IOCSR space in a little-endian storing {B/H/W/D} instruction’s IOCSR address is from the general register rj.

+
+
+

The IOCSRRD.{B/H/W/D} instruction fetches byte/half-word/word/double-word length data from the specified address in the IOCSR space, and writes it to the general register rd after symbolic expansion.

+
+
+

The IOCSRWR.{B/H/W/D} instruction writes the [7:0]/[15:0]/[31:0]/[63:0] bits of data in the general register rd to the beginning of the specified address in the IOCSR space.

+
+
+

The IOCSRRD.D and IOCSRWR.D instructions appear only in LA64.

+
+
+

IOCSR registers can typically be accessed by multiple processor cores simultaneously. +The execution of IOCSR access instructions on multiple processor cores satisfies the sequential consistency condition.

+
+
+
+
+

4.2.3. Cache Maintenance Instructions

+
+
4.2.3.1. CACOP
+
+

Instruction formats:

+
+
+
+
cacop   op, rj, si12
+
+
+
+

The CACOP instruction is mainly used for Cache initialization and cache-consistency maintenance.

+
+
+

The value of the general register rj, plus the sign-extended 12-bit immediate number si12, gives the virtual address VA used by the CACOP instruction, which is used to indicate the location of the Cache line being operated on.

+
+
+

Which Cache is accessed by the CACOP instruction and what Cache operation is performed is determined by the 5-bit op in the instruction. +op[2:0] indicates the Cache object to be operated on, and op[4:3] indicates the type of operation.

+
+
+

The Cache object indicated by op[2:0] is in the same order as the Cache identified in CPUCFG10. +For example, when CPUCFG10=0x02C3D, op[2:0]=0 indicates operation of the first-level private instruction Cache, op[2:0]=1 indicates operation of the first-level private data Cache, op[2:0]=2 indicates operation of the second-level private mixed Cache, and op[2:0]=3 indicates operation of the third-level shared mixed Cache.

+
+
+

op[4:3]=0 is used for Cache initialization (StoreTag), mainly to write the contents of the CSR.CTAG to the tag of the specified Cache row using direct address indexing. +Suppose the Cache to be accessed has (1<<Way) ways, each ways has (1<<Index) Cache line, and each Cache line size is (1<<0ffset) bytes, then the direct address indexing method means that the VA[Index+offset1.0ffset] of the VA[Way-1:0] way of the Cache is [operated: 0ffset] line of the Cache.

+
+
+

op[4:3]=1 means that the cache-consistency (Index Invalidate / Invalidate and Writeback) is maintained by direct address indexing. +See the previous paragraph for a definition of the direct address indexing method. +The operation to maintain consistency is an invalidate and writeback operation on the specified Cache. +If the operation is on the instruction Cache, then only the invalidation operation is performed, not the writing back of the data in the Cache row. +The data written back into which level of memory is determined by the specific implementation of the Cache hierarchy and the inclusion or mutually exclusive relationship between the levels. +For data Cache or mixed Cache, it is up to the implementation to decide whether to write back the data in the Cacche row only if it is dirty.

+
+
+

op[4:3]=2 means that Cache coherency is maintained by query indexing (Hit Invalidate / Invalidate and Writeback).

+
+
+

The operation of maintaining Cache coherency here is the same as described in the above paragraph. +The so-called query index approach treats the VA of the CACOP instruction as a normal load instruction to access the Cache to be operated on, and if it hits, it operates on the hit Cache row, otherwise it does not do any operation. +Since this query process may involve virtual-to-real address translation, the CACOP instruction may trigger TLB-related exceptions in this case. +However, since the CACOP instruction operates on Cache rows, there is no need to consider address alignment or not in this case.

+
+
+

op[4:3]=3 is an implementation of a custom Cache operation and is not explicitly functionally defined in the architecture specification.

+
+
+
+
+

4.2.4. TLB Maintenance Instructions

+
+
4.2.4.1. TLBSRCH
+
+

Instruction formats:

+
+
+
+
tlbsrch
+
+
+
+

The functional definition of the TLBSRCH instruction without implementing the LVZ extension is given here.

+
+
+

Use the information of CSR.ASID and CSR.TLBEHI to query TLB. +If there is a hit entry, the index of the hit entry is written to the Index field of CSR.TLBIDX, and the INV field of CSR.TLBIDX is set to 0; if there is no hit entry, the INV field of CSR.TLBIDX is set to 1.

+
+
+

The rules for calculating the index of each entry in the TLB are, starting from 0, incremental numbering, first STLB and then MTLB, STLB from the 0th line to the last line of the 0th way, then the 0th line to the last line of the 1st way, until the last line of the last way, MTLB from the 0th line to the last line.

+
+
+
+
4.2.4.2. TLBRD
+
+

Instruction formats:

+
+
+
+
tlbrd
+
+
+
+

The functional definition of the TLBRD instruction without implementing the LVZ extension is given here.

+
+
+

The value of the Index field of CSR.TLBIDX is used as the index to read the specified entry in the TLB. +If the specified location is a valid TLB entry, the page table information of the TLB entry is written to CSR.TLBEHI, CSR.TLBELO0, CSR.TLBELO1 and CSR.TLBIDX.PS, and the INV field of CSR.TLBIDX is set to 0; if the specified location is an invalid TLB entry, then CSR.TLBEHI, CSR.TLBELO0 and CSR.TLBELO1 is set to 0; and the INV field of CSR.TLBIDX is set to 1; TLBIDX.PS is set to 0 and the INV field of CSR.TLBIDX is set to 1.

+
+
+

Note that valid/invalid TLB entries and valid/invalid page table entries in the TLB are two concepts.

+
+
+

If the index used for the access exceeds the range of the TLB, the behavior of the processor is undefinded.

+
+
+
+
4.2.4.3. TLBWR
+
+

Instruction formats:

+
+
+
+
tlbwr
+
+
+
+

The functional definition of the TLBWR instruction without implementing the LVZ extension is given here.

+
+
+

The TLBWR instruction fills the page table entry information stored in the TLB-related CSRs into the TLB. +The page table entry information to be populated comes from CSR.TLBEHI, CSR.TLBELO0, CSR.TLBELO1 and CSR.TLBIDX_PS. +If CSR.TLBIDX.NE=1, then the TLB is populated with an invalid TLB entry; only if CSR.TLBIDX.NE=0, the TLB is populated with a valid TLB entry.

+
+
+

The location where the page table entry is written to the TLB is specified by the value of the Index field of CSR.TLBIDX. +Please refer to the TLBSRCH instruction for the calculation rules of each index in the TLB for the specific corresponding rules. +If a page table entry is to be written to the STLB, but a conflict occurs between the value of the Index field of CSR.TLBIDX and VPPN and CSR.TLBIDX.PS in CSR.TLBEHI, the behavior of the processor is undefinded.

+
+
+
+
4.2.4.4. TLBFILL
+
+

The functional definition of the TLBFILL instruction without implementing the LVZ extension is given here.

+
+
+

The TLBFILL instruction fills the page table entry information stored in the TLB-related CSRs into the TLB. +The page table entry information to be populated comes from CSR.TLBEHI, CSR.TLBELO0, CSR.TLBELO1 and CSR.TLBIDX_PS. +If CSR.TLBIDX.NE=1, then the TLB is populated with an invalid TLB entry; only if CSR.TLBIDX.NE=0, the TLB is populated with a valid TLB entry.

+
+
+

Whether to write to STLB or MTLB is first made based on the page size of the page table entry being filled. +When the page size of the page table entry being filled is equal to the page size configured for STLB (CSR.STLBPS) it will be filled to STLB, otherwise it will be filled to MTLB. +Which way the page table entry is filled to STLB, or which entry is filled to MTLB is randomly selected by the hardware.

+
+
+
+
4.2.4.5. TLBCLR
+
+

Instruction formats:

+
+
+
+
tlbclr
+
+
+
+

The contents of the TLB are invalidated according to the information of the TLB-related CSRs to maintain the consistency of the page table data between the TLB and the memory. +The functional definition of the TLBCLR instruction without implementing the LVZ extension is given here.

+
+
+

When CSR.index.index falls within the range of MTLB (greater than or equal to the number of STLB entries), TLBCLR is executed to invalidate all page table entries in MTLB with G=0 and ASID equal to CSR.ASID.ASID.

+
+
+

When CSR.index.index falls within the STLB range (less than the number of STLB entries), execute a TLBCLR to invalidate all page table entries in the STLB that are equal to G=0 and ASID equal to CSR.ASID.ASID in the group indicated by the low bit of CSR.index.index.

+
+
+
+
4.2.4.6. TLBFLUSH
+
+

Instruction formats:

+
+
+
+
tlbflush
+
+
+
+

The contents of the TLB are invalidated according to the information of the TLB-related CSRs to maintain the consistency of the page table data between the TLB and the memory. +The functional definition of TLBCLR instruction without implementing LVZ extension is given here.

+
+
+

When CSR.index.index falls within the MTLB range (greater than or equal to the number of STLB entries), TLBCLR is executed to invalidate all page table entries in the MTLB.

+
+
+

When CSR.index.index falls within the STLB range (less than the number of STLB entries), a TLBCLR is executed to invalidate all page table entries in the group indicated by the low CSR.index.index in the STLB.

+
+
+
+
4.2.4.7. INVTLB
+
+

Instruction formats:

+
+
+
+
invtlb  op, rj, rk
+
+
+
+

The INVTLB instruction is used to invalidate the contents of the TLB to maintain consistency of the page table data between the TLB and memory. +The functional definition of the INVTLB instruction is given here for the case where the LVZ extension is not implemented.

+
+
+

Of the three source operands of the instruction, op is a 5-bit immediate number to indicate the type of operation.

+
+
+

The [9:0] bits of the general register rj hold the ASID information required for the invalid operation (called “register specified ASID”), and the remaining bits must be filled with 0. +When the operation indicated by op does not require an ASID, the general register rj should be set to r0.

+
+
+

The general register rk is used to store the virtual address information required for invalid operations (called “register specified VA”). +When the operation indicated by the op does not require virtual address information, the general register rk should be set to r0.

+
+
+

The operations corresponding to each op are shown in the following table, and the op that does not appear in the table will trigger a reserved instruction exception.

+
+ + ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 13. Operations corresponding to each op in the INVTLB instruction
opOperation

0x0

Clear all page table entries

0x1

Clears all page table entries. +The effect of this operation is exactly the same as op=0.

0x2

Clears all G=1 page table entries.

0x3

Clears all page table entries with G=0.

0x4

Clears all page table entries with G=0 and ASID equal to the ASID specified in the register.

0x5

Clear all page table entries with G=0 and ASID equal to the register specified ASID, and VA equal to the register specified VA.

0x6

Clear all page table entries where G=1 or ASID is equal to the ASID specified in the register and VA is equal to the VA specified in the register.

+
+
+
+

4.2.5. Software page walking Instructions

+
+
4.2.5.1. LDDIR
+
+

Instruction formats:

+
+
+
+
lddir   rd, rj, level
+
+
+
+

The LDDIR instruction is used for accessing directory entries during software page table walking.

+
+
+

The 5-bit immediate level in the LDDIR instruction indicates which page table is currently being accessed. +level=1 corresponds to Dir0 in PWCL, level=2 corresponds to Dirl in PWCL, level=3 corresponds to Dir2 in PWCH, and level=4 corresponds to Dir3 in PWCH.

+
+
+

If bit [6] of the general register rj is 0, it means that the content of rj is the physical address of the base address of the level page table at this time. +In this case, the LDDIR instruction will access the level page table according to the current TLB refill address, retrieve the base address of the corresponding level+1 page table, and write it to the general register rd.

+
+
+

If bit [6] of general register rj is 1, it means that the content in rj is a large page (Huge Page) page table entry. +In this case, after executing the LDDRI instruction, the value in the general register rj will be written directly to the general register rd.

+
+
+
+
4.2.5.2. LDPTE
+
+

Instruction formats:

+
+
+
+
ldpte   rj, seq
+
+
+
+

The LDPTE instruction is used for page table entry accesses during software page table walking.

+
+
+

The immediate number seq in the LDPTE instruction is used to indicate whether an even or odd number of pages are being accessed. +The result is written to CSR.TLBRELO0 when an even page is accessed. +The result will be written to CSR.TLBRELO1 when an odd page is accessed.

+
+
+

If bit [6] of the general register rj is 0, the content of rj is the physical address of the base address of the page table at that level of the PTE. +In this case, the LDPTE instruction will access the PTE level page table according to the currently processed TLB refill address, retrieve the page table entry and write it to the corresponding CSR.

+
+
+

If bit [6] of the general register rj is 1, it means that the content of rj is a large page (Huge Page) page table entry. +In this case, the LDPTE instruction is executed, and the value in general register rj is directly converted into the final page table entry format and written to the corresponding CSR.

+
+
+
+
+

4.2.6. Other Miscellaneous Instructions

+
+
4.2.6.1. ERTN
+
+

Instruction formats:

+
+
+
+
ertn
+
+
+
+

The ERTN instruction is used to return from exception processing.

+
+
+

If the exception being processed is a debug exception clear the DM bit in the CSR.DEBUG to 0, and jump to the address stored in the CSR.DEBUG to start fetching.

+
+
+

If the exception being processed is something other than a debug exception, update the PPLV, PIE, and PWE information corresponding to the exception to CSR.CRMD, update the PVM in CSR.VMCTL to CSR.VMCTL.VM, and jump to the ERA corresponding to the exception to start fetching instructions.

+
+
+

If the exception processed is an error-related exception, the PPLV, PIE and PWE information corresponding to the exception is from CSR.MERRCTL, and the ERA corresponding to the exception is from CSR.MERRERA. +In addition, the PDA, PPG, PDCAF and PDCAM information in CSR.MERRCTL should be updated to CSR.CRMD.

+
+
+

If the exception being processed is a TLB refill exception, the PPLV, PIE, and PWE information corresponding to the exception is from CSR.TLBRPRMD, and the ERA corresponding to the exception is from CSR.TLBRERA. +In addition, it is necessary to clear DA field 0 and PG field 1 in CSR.CRMD.

+
+
+

If the exception being handled is not a debug exception, an error-related exception, or a TLB refill exception, then the PPLV, PIE and PWE information corresponding to the exception is from CSR.PRMD, and the ERA corresponding to the exception is from CSR.ERA.

+
+
+

When executing the ERTN instruction, if the KL0 bit in CSR.LLBCTL is not equal to 1, then the LLbit is set to 0, otherwise the LLbit is not modified.

+
+
+
+
4.2.6.2. DBCL
+
+

Instruction formats:

+
+
+
+
dbcl        code
+
+
+
+

Executing DBCL instruction will immediately enter debug mode.

+
+
+
+
4.2.6.3. IDLE
+
+

Instruction formats:

+
+
+
+
idle        hint
+
+
+
+

After executing the IDLE instruction, the processor core will stop fetching instructions and enter the wait state until it is woken up by an interrupt or is reset. +After waking up from the wait state by an interrupt, the first instruction executed by the processor core is the one after IDLE.

+
+
+
+
+
+
+
+

5. Memory Management

+
+
+

5.1. Physical Address Space

+
+

The physical address space range of memory is 0-2PALEN-1.

+
+
+

In LA32, PALEN is theoretically a positive integer not exceeding 32, and its specific value is determined by the implementation, which is usually recommended to be 32.

+
+
+

In LA64, PALEN is theoretically a positive integer not exceeding 60, and its specific value is determined by the implementation.

+
+
+

The system software can determine the specific value of PALEN by reading the PALEN field of the 0x1 configuration word with the CPUCFG instruction.

+
+
+
+

5.2. Virtual Address Space and Address Translation Mode

+
+

The virtual address space is linear/flat in LoongArch. +For PLV0 level, the virtual address space size is 232 bytes in LA32 and 264 bytes in LA64. +However, the 264-byte virtual address space is not always legal in LA64. +It can be assumed that there are some virtual address holes. +The legal virtual address space is closely related to the address translation mode, which is described in the next section in conjunction with the definition of the address translation mode.

+
+
+

The MMU in LoongArch supports two modes of translating virtual addresses to physical addresses: direct address translation mode and mapped address translation mode.

+
+
+

When CSR.CRMD.DA=1 and CSR.CRMD.PG=0, the MMU of the processor core is in direct address translation mode. +In this mode, the physical address is by default equal to the [PALEN-1:0] bits of the virtual address (zero extension if necessary), unless the implementation uses other higher priority translation rules. +The entire virtual address space is legal at this point. +The processor will enter the direct address translation mode after reset.

+
+
+

When CSR.CRMD.DA=0 and CSR.CRMD.PG=1, the MMU of the processor core is in mapped address translation mode. +Specifically, there are two types of address translation modes: direct mapped address translation mode (direct mapped mode) and page table mapped address translation mode (page table mapped mode). +When translating addresses, the direct mapped mode is preferred. +Only when the address cannot be translated by the direct mapped mode, the page table mapped mode is used for translation. +See Direct Mapped Address Translation Mode for details on the direct mapped mode and Memory Management of Page Table Mapping for details on the page table mapped mode. +The rules for virtual address space legality during using the page table mapped mode in LA64 are presented here. +The [63:PALEN] bits of the legal virtual address must be the same as the [PALEN-1] bits, otherwise an ADdress error Exception (ADE) will be triggered. +In direct mapped mode, however, this address illegality check is not required.

+
+
+

5.2.1. Direct Mapped Address Translation Mode

+
+

When the MMU of the processor core is in mapped address translation mode, direct mapping of virtual and physical addresses can also be accomplished through the mechanism of direct mapping configuration windows. +There are four direct mapping configuration windows. +The first two windows can be used for both fetch and load/store operations, and the last two windows are used for load/store operations only.

+
+
+

The system software sets each of the four direct mapping configuration windows by configuring the CSR.DMW0-CSR.DMW3 configuration window registers. +Each window can be used to configure not only for the address range, but also for the privilege levels under which the window is available, as well as the type of memory access for virtual address within the address range.

+
+
+

In LA64, each direct mapping configuration window can be configured with a virtual address space which length is PALEN bytes. +When a virtual address hits a valid direct mapping configuration window, its physical address is equal to the [PALEN-1:0] bits of itself. +The hit is determined as follows: the highest 8 bits of the virtual address ([63:60] bits) are equal to the VSEG field in the configuration window register, and the current privilege level is available.

+
+
+

For example, if PALEN is equal to 48 and DMWO is set to 0x9000000000000011, virtual address space 0x9000000000000000-0x9000FFFFFFFFFFFF will be directly mapped to physical address space 0x0-0xFFFFFFFFFFFF at the PLV0 privilege level, the memory access type of which is consistent and cacheable.

+
+
+

In LA32, each direct mapping configuration window can be configured with a virtual address space which length is 229 bytes. +When a virtual address hits a valid direct mapping configuration window, its physical address is equal to the combination of the [28:0] bits of itself and the high bits of the the configuration window register. +The hit is determined as follows: the highest 4 bits of the virtual address ([31:29] bits) are equal to the [31:29] bits in the configuration window register, and the current privilege level is available.

+
+
+

For example, if DMW0 is set to 0x80000011, virtual address space 0x80000000-0x8FFFFFFF will be directly mapped to physical address space 0x0-0x1FFFFFFF at the PLV0 privilege level, the memory access type of which is consistent and cacheable.

+
+
+
+

5.2.2. 32-bit Address Mode in LA64

+
+

When the binary application in LA32 runs on the processor that implements LA64, the calculation involving address in the instruction needs to be handled specially in order to obtain the same operation result, which is the 32-bit address mode control in LA64. +When VA32L1/VA32L2/VA32L3 in CSR.MISC is set to 1, the software running at PLV1/PLV2/PLV3 level will run in 32-bit address mode. +At this time, the virtual address will be zero extended to 64 bits. +The 32-bit results of executing instructions like BL, JIRL and PCADD will also be sign extended to 64 bits.

+
+
+
+

5.2.3. Virtual Address Reduction Mode in LA64

+
+

In order to reduce the number of page table levels in some occasions, the virtual address reduction mode is also provided in LA64. +When the system software set RDVA in the CSR.RVACFG register to a value from 1 to 8, the valid bits of the virtual address in mapped address translation mode are treated as (VALEN-RDVA) bits. +For example, when VALEN=48 and RDVA is set to 8, the [63:40] bits of the legal address must be a sign expansion of the [39] bit.

+
+
+
+
+

5.3. Memory Access Types

+
+

As mentioned in Memory Access Types, there are three types of memory access in LoongArch, including CC, SUC, and WUC.

+
+
+

When the MMU of the processor core is in direct address translation mode, the memory access types of all fetch operations are determined by CSR.CRMD.DATF, and the memory access types of all load/store operations are determined by CSR.CRMD.DATM.

+
+
+

When the MMU of the processor core is in mapped address translation mode, the memory access types are divided into two cases. +If the address of a fetch or load/store operation falls on one of the direct mapping configuration windows, then its memory access type is determined by the MAT field in the CSR register that is configured in the window. +If the fetch or load/store can only be mapped through the page table, then its memory access type is determined by the MAT field in the page table entry.

+
+
+

In any case, the definition of the control value for the memory access type is always the same: 0 for strongly-ordered uncached, 1 for coherent cached, 2 for weakly-ordered uncached, and 3 for reserved.

+
+
+
+

5.4. Memory Management of Page Table Mapping

+
+

In mapped address translation mode, all legal addresses, except those that fall in the direct mapping configuration window, must be mapped through the page table to complete the translation of virtual addresses to physical addresses. +As a temporary Cache for the processor to store information about page tables in the operating system, TLB is used to speed up the translation of virtual addresses to physical addresses for fetch and load/store operations in mapped address translation mode.

+
+
+

5.4.1. TLB Organizational Structure

+
+

The TLB in LoongArch is divided into two parts, one is Singular-Page-Size TLB (STLB) which has the same page size for all table entries, and the other is Multiple page size TLB (MTLB) which supports different page sizes for different table entries.

+
+
+

The page size is the same as the page size configured in the STLB, and it is up to the implementation to decide whether a page table entry can enter the MTLB, with no restrictions in the architecture specification.

+
+
+

During the translation of a virtual address to a physical address, the STLB and the MTLB look up simultaneously. +Accordingly, the software needs to ensure that there are no simultaneous hits of MTLB and STLB, otherwise the processor behavior will be undefined.

+
+
+

The MTLBs are fully associative, and the STLBs are multi-way set associative. +For STLB, if it has 2INDEX groups and the configured page size is 2PS bytes, the hardware querying STLB is using the [PS+INDEX:PS] bits of the virtual address as the index of each way.

+
+
+
+

5.4.2. TLB Entry

+
+

The table entry formats of STLB and MTLB is basically the same, the only difference is that each table entry of MTLB contains the page size information, while STLB does not need to store the page size information repeatedly because it is the same page size. +For STLB, the page size of the page table entry is configured by the system software in the PS field of the CSR.STLBPS register.

+
+
+

The format of each TLB table entry is shown in the figure and contains two parts: the comparison part and the physical translation part.

+
+
+
+tlb entry formats +
+
Figure 6. TLB entry formats
+
+
+

The comparison part of TLB table entries includes:

+
+
+
    +
  • +

    Existence bit (E), 1 bit. +When this bit is set, it indicates that the page table entry exists and can participate in lookup matching.

    +
    • +
  • +

    Address Space IDentifier (ASID), 10 bits. +ASID is used to distinguish the same virtual address in different processes and to avoid performance loss caused by clearing the entire TLB during process switching. +The operating system assigns a unique ASID to each process, and the TLB needs to match the ASID in addition to the address when performing lookups.

    +
    • +
  • +

    Global flag bit (G), 1 bit. +When this bit is set, the lookup is not checked for ASID consistency. +If the operating system needs to share the same virtual address among all processes, this bit can be set.

    +
    • +
  • +

    Page Size (PS), 6 bits. +PS appears only in the MTLB. +It is used to specify the size of the pages stored in this page table entry. +The value is a power of 2 of the page size. +That is, for a page size of 16KB, PS=14.

    +
    • +
  • +

    Virtual Pair of Page frames Number (VPPN), (VALEN-13) bits. +The physical translation part holds the translation information for a adjacent odd even pair of page tables, so the virtual page number stored in the TLB page table entry is the content of the virtual page number divided by 2 in the operating system. +The lowest bit of the virtual page number does not need to be stored. +When searching for the TLB, the lowest bit of the virtual page number is used to decide whether to select the odd-numbered page or the even-numbered page for physical translation.

    +
    • +
+
+
+

The physical translation part of the table entry holds the translation information for a adjacent odd even pair of page tables, and the information for each page includes:

+
+
+
    +
  • +

    Valid bit (V), 1 bit. +This bit is set when the page table entry is valid. +Note the difference between the P bit when performing lookups. +The P bit refers to whether a page table entry on the TLB table entry is present. +A page table entry is present even if it is invalid (V=0).

    +
    • +
  • +

    Dirty bit (D), 1 bit. +This bit is set when there is dirty data on the address space where the page table entry is located.

    +
    • +
  • +

    Non-Readable bit (NR), 1 bit. +This bit is set when no load operation is allowed on the address space where this page table entry is located. +This control bit is only exist in LA64.

    +
    • +
  • +

    Non-eXecutable bit (NX), 1 bit. +This bit is set when a fetch operation is not allowed on the address space where this page table entry is located. +This control bit is only exist in LA64.

    +
    • +
  • +

    Memory Access Type (MAT), 2 bits. +MAT controls the type of memory access that falls on the address space where the page table entry is located. +See Memory Access Types for the specific meaning of each value.

    +
    • +
  • +

    Privilege LeVel (PLV), 2 bits. +PLV refers to the privilege level corresponding to this page table entry. +When RPLV=0, the page table entry can be accessed by any program whose privilege level is not lower than PLV; when RPLV=1, the page table entry can only be accessed by programs whose privilege level is equal to PLV.

    +
    • +
  • +

    Restricted Privilege LeVel (RPLV), 1 bit. +RPLV refers to whether a page table entry is accessed only by programs corresponding to the privilege level. +See above in PLV. +This control bit is only exist in LA64.

    +
    • +
  • +

    Physical Page Number (PPN), (PALEN-12) bits. +When the page size is larger than 4KB, the [log2PS-1:12] bits of the PPN stored in the TLB can be any value.

    +
    • +
+
+
+
+

5.4.3. Software Management of TLB

+
+

The management of TLBs in LoongArch involves software work. +In the current version of this architecture specification, TLB refill and consistent maintenance between TLB and page tables are still all led by software.

+
+
+
5.4.3.1. TLB-related Exceptions
+
+

The TLB performs translation of virtual addresses to physical addresses automatically by hardware. +However, when there is no match in the TLB, or when the page table entry is invalid or illegally accessed despite the match, an exception needs to be triggered and handed over to the OS kernel or other supervisory programs. +The exception is further handled by software to maintain the content of the TLB or to make a final ruling on the legality of the program execution. +The exceptions related to TLB management in LoongArch are as follows:

+
+
+
    +
  • +

    TLB refill exception: This exception is triggered when the virtual address of an access operation does not have a match in the TLB, which notifies the system software to perform a TLB refill. +This exception has a separate exception entry, a separate CSR for maintaining the exception context, and a separate set of CSRs as TLB access interface; that means the exception is allowed to be triggered during the processing of other exceptions. +While the TLB refill exception being caught, CRMD will be set to 1 and PG will be set to 0. +This means the hardware will enter the direct address translation mode automatically, so that the TLB refill exception handler itself will not trigger the TLB refill exception again, and the exception context will not be saved and recovered. +In order to distinguish CSRs used by the TLB refill exception and CSRs available for other exceptions, the hardware will automatically set CSR.TLBRERA.ISTLBR to 1 while the exception is caught.

    +
    • +
  • +

    Page invalid exception for load operation: This exception is triggered when the virtual address of the load operation finds a match in the TLB with V=0.

    +
    • +
  • +

    Page invalid exception for store operation: This exception is triggered when the virtual address of the store operation finds a match in the TLB with V=0.

    +
    • +
  • +

    Page invalid exception for fetch operation: This exception is triggered when the virtual address of the fetch operation finds a match in the TLB with V=0.

    +
    • +
  • +

    Page privilege level ilegal exception: This exception is triggered when the virtual address of the access operation finds a matching entry in the TLB with V=1, but the privilege level of the access is illegal. +The privilege level is illegal when RPLV=0 and CSR.CRMD.PLV is greater than the PLV in the page table entry, or when RPLV=1 and CSR.CRMD.PLV is not equal to the PLV in the page table entry.

    +
    • +
  • +

    Page modify exception: This exception is triggered when the virtual address of the store operation finds a match in the TLB with V=1 and privilege level is legal and D=0.

    +
    • +
  • +

    Page non-readable exception: This exception is triggered when the virtual address of the load operation finds a match in the TLB with V=1 and privilege level is legal and NR=1.

    +
    • +
  • +

    Page non-executable exception: This exception is triggered when the virtual address of the fetch operation finds a match in the TLB with V=1 and privilege level is legal and NX=1.

    +
    • +
+
+
+
+
5.4.3.2. TLB-related Instructions
+
+

The TLB-related instructions mainly involve operations such as lookup, read, write, and invalidate the TLB for filling, updating, and consistency maintenance of the TLB. +See TLB Maintenance Instructions and Software page walking Instructions for specific instruction definitions.

+
+
+
+
5.4.3.3. TLB-related CSRs
+
+

TLB-related CSRs are divided into three categories according to their functions. +The first category is used for the interactive interface of TLBs other than TLB refill exceptions. +The second category is used for software and hardware page walking. +The third category is used for TLB refill exceptions.

+
+
+

The first category includes:

+
+
+
    +
  • +

    BADV

    +
    • +
  • +

    TLBEHI

    +
    • +
  • +

    TLBELO0

    +
    • +
  • +

    TLBELO1

    +
    • +
  • +

    TLBIDX

    +
    • +
  • +

    ASID

    +
    • +
  • +

    STLBPS

    +
    • +
+
+
+

The second category includes:

+
+
+
    +
  • +

    PGDL

    +
    • +
  • +

    PGDH

    +
    • +
  • +

    PGD

    +
    • +
  • +

    PWCL

    +
    • +
  • +

    PWCH

    +
    • +
+
+
+

The third category includes:

+
+
+
    +
  • +

    TLBRENTRY

    +
    • +
  • +

    TLBRERA

    +
    • +
  • +

    TLBRBADV

    +
    • +
  • +

    TLBREHI

    +
    • +
  • +

    TLBRELO0

    +
    • +
  • +

    TLBRELO1

    +
    • +
  • +

    TLBRPRMD

    +
    • +
  • +

    TLBRSAVE

    +
    • +
+
+
+

See Basic Control and Status Registers for details of how each CSR register above interacts with the TLB.

+
+
+
+
5.4.3.4. Initialization of TLB
+
+

LoongArch allows not to implement the hardware initialization of the TLB, but to let the software in the boot phase perform this function by executing INVTLB r0, r0.

+
+
+
+
+

5.4.4. TLB-based Translation of Virtual Addresses to Physical Addresses

+
+

The TLB-based translation of virtual addresses to physical addresses is described here. +For the convenience of description, the following is presented in pseudocode form with STLB first and MTLB second, while the hardware implementation of the processor can look up STLB and MTLB at the same time.

+
+
+
+
# va: virtual address to be found.
+# mem_type: memory acess type. FETCH refers to fetch operation, LOAD refers to load operation, and STORE refers to store operation.
+# plv: current privilege level, i.e., CSR.CRMD.PLV.
+# pa: physical addresses after translation.
+# mat: memory acess type after translation.
+# VALEN: number of valid bits of the virtual address.
+# PALEN: number of valid bits of the physical address.
+# STLB[][]: STLB[N][M] refers to the Nth way and the Mth entry of STLB.
+# STLB_WAY: number of ways of STLB.
+# STLB_INDEX: the power of 2 of the number of groups in each way of STLB, i.e., each way has 2STLB_INDEX groups.
+# MTLB[]: MTLB[N] refers to the Nth entry of MTLB.
+# MTLB_ENTRIES: number of entries of MTLB.
+
+# look up STLB
+stlb_found = 0
+stlb_ps = CSR.STLBPS.PS
+stlb_idx = va[stlb_ps+STLB_INDEX-1:stlb_ps]
+for way in range(STLB_WAY):
+    if (STLB[way][stlb_idx].E == 1) and
+    ((STLB[way][stlb_idx].G == 1) or (STLB[way][stlb_idx].ASID == CSR.ASID.ASID))
+ and
+    (STLB[way][stlb_idx].VPPN[VALEN-1:stlb_ps+1]==va[VALEN-1:stlb_ps+1]):
+    if (stlb_found == 0):
+        stlb_found = 1
+        if (va[stlb_s] == 0):
+            sfound_v = STLB[way][stlb_idx].V0
+            sfound_d = STLB[way][stlb_idx].D0
+            sfoundnr = STLB[way][stlb_idx].NR0
+            sfound_ne = STLB[way][stlb_idx].NE0
+            sfound_mat = STLB[way][stlb_idx].MAT0
+            sfound_plv = STLB[way][stlb_idx].PLV0
+            sfound_rplv = STLB[way][stlb_idx].RPLV0
+            sfound_pfn = STLB[way][stlb_idx].PFN0
+        else:
+            sfound_v = STLB[way][stlb_idx].V1
+            sfound_d = STLB[way][stlb_idx].D1
+            sfound_nr = STLB[way][stlb_idx].NR1
+            sfound_ne = STLB[way][stlb_idx].NE1
+            sfound_mat = STLB[way][stlb_idx].MAT1
+            sfound_plv = STLB[way][stlb_idx].PLV1
+            sfound_rplv = STLB[way][stlb_idx].RPLV1
+            sfound_pfn = STLB[way][stlb_idx].PFN1
+        else:
+            # There are multiple hits, so the processor behavior will be undefined.
+
+# look up MTLB
+mtlb_found = 0
+for i in range (MTLB_ENTRIES):
+    if (MTLB[i].E == 1) and
+    ((MTLB[i].G == 1) or (MTLB[i].ASID == CSR.ASID.ASID)) and
+    (MTLB[i].VPPN[VALEN-1:MTLB[i].PS+1] == va[VALEN-1:MTLB[i].PS+1]):
+    if (mtlb_found == 0):
+            mtlb_found = 1
+            mfound_ps - MTLB[i].PS
+        if (va[mfound_ps] == 0):
+            mfound_v = MTLB[i].V0
+            mfound_d = MTLB[i].DO
+            mfound_nr = MTLB[i].NRO
+            mfound_ne - MTLB[i].NEO
+            mfound_mat = MTLB[i].MATO
+            mfound_plv = MTLB[i].PLV0
+            mfound_rplv = MTLB[i].RPLVO
+            mfound_pfn = MTLB[i].PFNO
+        else:
+            mfound_v = MTLB[i].V1
+            mfound_d = MTLB[i].D1
+            mfound_nr = MTLB[i].NR1
+            mfound_ne = MTLB[i].NE1
+            mfound_mat = MTLB[i].MAT1
+            mfound_plv = MTLB[i].PLV1
+            mfound_rplv = MTLB[i].RPLV1
+            mfound_pfn = MTLB[i].PFN1
+    else:
+        # There are multiple hits, so the processor behavior will be undefined.
+
+if (stlb_found == 1) and (mtlb_found == 1):
+    # There are multiple hits, so the processor behavior will be undefined.
+elif (stlb_found == 1):
+    found_v = sfound_v
+    found_d = sfound_d
+    found_nr = sfound_nr
+    found_ne = sfound_ne
+    found_mat = sfound_mat
+    found_plv = sfound_plv
+    found_rplv = sfound_rplv
+    found_pfn = sfound_pfn
+    found_ps = stlb_ps
+elif (mtlb_found == 1):
+    found_v = mfound_v
+    found_d = mfound_d
+    found_nr = mfound_nr
+    found_ne = mfound_ne
+    found_mat = mfound_mat
+    found_plv = mfound_plv
+    found_rplv = mfound_rplv
+    found_pfn = mfound_pfn
+    found_ps = mfound_ps
+else:
+    SignalException(TLBRD)    # Trigger TLB refill exception.
+
+if (found_v == 0):
+    case mem_type:
+    FETCH : SignalException(PIF)    # Trigger page invalid exception for fetch operation.
+    LOAD : SignalException(PIL)     # Trigger page invalid exception for load operation.
+    STORE : SignalException(PIS)    # Trigger page invalid exception for store operation.
+elif (mem_type == FETCH) and (found_ne == 1):
+    SignalException(PNX)    # Trigger page non-executable exception.
+elif ((found_rplv == 0) and (plv > found_plv)) or
+     ((found_rplv == 1) and (plv != found_plv)):
+    SignalException(PPE)    # Trigger page privilege level ilegal exception.
+elif (mem_type == L0AD) and (found_nr == 1):
+    SignalException(PNR)    # Trigger page non-readable exception.
+elif (mem_type == STORE) and (found_d == 0)
+     and ((plv == 3) or (CSR.MISC[16+plv] == 0)) :    # The function that disable the check of write protection is not enabled.
+    SignalException(PME)    # Trigger page modify exception.
+else:
+    pa = {found_pfn[PALEN-1:found_ps], va[found.ps-1:0]}
+    mat = found_mat
+
+
+
+
+

5.4.5. Multi-level Page Table Structure Supported by page walking

+
+

Whether the LDDIR and LDPTE instructions are used to implement software page walking or hardware page walking, the supported multi-level page table structure is the same, as shown in the figure.

+
+
+
+multi level page table structure supported by page walking +
+
Figure 7. Multi-level page table structure supported by page walking
+
+
+

The base address of the top-level directory (global directory) of the traversed page table called PGD is determined by the (PALEN-1) bit of the queried virtual address. +When this bit is 0, the PGD comes from CSR.PGDL; when this bit is 1, the PGD comes from CSR.PGDH. +This means that the entire page table structure is (PALEN-1) bits.

+
+
+

The specifications of each level of directory entries and page table entries are configured by the system software in CSR.PWCL and CSR.PWCH.

+
+
+

Whether the LDDIR and LDPTE instructions are used to implement software page walking or hardware page walking, the system software needs to define the page table entries in the following format.

+
+
+
+table entry format for common pages +
+
Figure 8. Table entry format for common pages
+
+
+
+table entry format for huge pages +
+
Figure 9. Table entry format for huge pages
+
+
+

In the above definition of the page table entry format, the main differences between the page table entry of a huge page and the page table entry of a common page are:

+
+
+
    +
  1. +

    Bit 6 of the directory entry is the huge page table entry flag bit, and 1 indicates that the directory entry actually stores the page table entry of a huge page at this time;

    +
    2. +
  2. +

    The G bit of the common page table entry is in bit 6, while the G bit of the huge page table entry is in bit 12.

    +
    3. +
+
+
+

Bits not defined in either of these formats are automatically ignored by the LDDIR and LDPTE instructions or hardware page walking.

+
+
+

The P field defined in the above page table entry format represents whether the physical page exists, and the W field represents whether the page is writable. +This information is not filled in the TLB table entry, but is used during the page walking.

+
+
+

Due to the double-page memory structure of the TLB table entries, for the huge page table entries (which has only one), the hardware page table refill or the software LDPTE instruction will automatically split the two page table entries in half according to the information of the huge page table entries and then fill in the TLB. +For example, if the standard page size is 16KB, the size of the first-level huge page size is usually 32MB. +After the LDPTE rj, 0 and LDPTE rj, 1 instructions are executed during page walking, The TLB will be filled with two page table entries (page size is 16MB) without special software intervention.

+
+
+

Because the address mapping is in direct address translation mode during TLB Refill exception (TLBR), the addresses configured in the PGD and in the directory entries of the page table in memory must be physical addresses.

+
+
+
+
+
+
+

6. Exceptions and interrupts

+
+
+

6.1. Interrupts

+
+

6.1.1. Interrupt Types

+
+

Interrupts in LoongArch take the form of line-based interrupts. +Each processor core can record 13 line-based interrupts: one Inter-Processor Interrupt (IPI), one Timer Interrupt (TI), one Performance Monitor Counter Overflow Interrupt (PMCOV), eight HardWare Interrupts (HWI0-HWI7), and two SoftWare Interrupts (SWI0-SWI1). +All line-based interrupts are level-triggered and are high level triggered.

+
+
+

The interrupt source for inter-processor interrupts comes from an interrupt controller outside the core, which is recorded by the processor core in the CSR.ESTA.IS[12] bit.

+
+
+

The interrupt source for the timer interrupt is from the constant frequency timer in the core. +This interrupt is triggered when the constant frequency timer counts down to zero. +The timer interrupt is recorded by the processor core in the CSR.ESTA.IS[11] bit. +Clearing the timer interrupt is accomplished by the software via writing 1 to CSR.TICLR.TI.

+
+
+

The interrupt source for the performance monitor counter overflow interrupt comes from the performance monitor counter in the core. +This interrupt is triggered when the [63] bit of the performance counter of any enabled interrupt is 1. +The performance monitor counter overflow interrupt is recorded by the processor core in the CSR.ESTA.IS[10] bit. +To clear a performance monitor counter overflow interrupt, set the performance monitor counter of the interrupt that is triggered to 0 at the [63] bit, or disable the interrupt for that performance monitor counter.

+
+
+

The interrupt source for hardware interrupts comes from outside the processor core, and its direct source is usually an interrupt controller outside the core. +8 hardware interrupts (HWI[7:0]) are recorded by the processor core in the CSR.ESTA.IS[9:2] bits .

+
+
+

The source of the software interrupt comes from the internal core of the processor, and the software writes 1 to CSR.ESTA.IS[1:0] to set up the software interrupt and 0 to clear it.

+
+
+

The index of the location of the interrupt recorded by the CSR.ESTA.IS field is also called the Interrupt Number (Int Number). +Int number for SWI0 is equal to 0, int number for SWI1 is equal to 1, …​ , int number of IPI is equal to 12.

+
+
+
+

6.1.2. Interrupt Priority

+
+

The response to multiple interrupts at the same time is arbitrated by a fixed priority. +The higher the int number, the higher the priority. +Therefore, IPI has the highest priority, TI the second highest, …​ , SWI0 has the lowest priority.

+
+
+
+

6.1.3. Interrupt Entry

+
+

Interrupts are treated as an exception once they are marked to the instruction by the processor, so the calculation of interrupt entries follows the rules for calculating general exception entries. +See Exception Entry for the rules of calculating the general exception entries. +The exception number for an interrupt is its own int number plus 64. +The exception number for interrupt SWI0 is 64, the exception number for interrupt SWI1 is 65, …​ , and so on.

+
+
+
+

6.1.4. Process of Processor Responding to Interrupts

+
+

The interrupt signal from each interrupt source is recorded by the processor in the CSR.ESTA.IS field. +The value of this field and the value of the local interrupt enable field configured by software in the CSR.ECFG.LIE field perform the bitwise AND operation to obtain a 13-bit interrupt vector (int_vec). +When CSR.CRMD.IE=1 and int_vec is not all 0 values, the processor considers that there is an interrupt that needs to be responded to. +So the processor picks an instruction from the executed instruction stream and marks it with a special kind of exception — interrupt exception.

+
+
+

The subsequent process of the processor is the same as that of the general exception, see the description in General Hardware Exception Handling of General Exceptions.

+
+
+
+
+

6.2. Message-Interrupts

+
+

6.2.1. Message-Interrupt Types

+
+

In the Loongson architecture, 256 message interrupts can be recorded inside each logical processor core, which can include message-type intercore interrupts and message-type hard interrupts input from outside the processor core. +Within a processor core, four 64-bit CSRS, CSR.MSGIS0 to CSR.MSGIS3, record in turn whether messages from 0 to 255 are interrupted or not. +The exact source of the 256 message interrupts inside each processor core is determined by the implementation, and software developers need to refer to the specific chip user manual for information.

+
+
+
+

6.2.2. Message-Interrupt-Priority

+
+

Loongson architecture adopts a fixed priority among 256 message interrupts in each logical processor core. The larger the interrupt number, the higher the priority, that is, message number 255 has the highest priority, message number 254 has the second,…​…​ , message 0 has the lowest interrupt priority.

+
+
+

Only message interrupts recorded inside each logical processor core whose priority is not lower than the message interrupt enable priority threshold (recorded in the CSR.MSGIE.PT field) can be further selected and set by the hardware.

+
+
+

When there are both message interrupt request and line interrupt request in a processor core, the message interrupt request has higher priority than the line interrupt request.

+
+
+
+

6.2.3. Message-Interrupt-Entry

+
+

All message interrupts adopt a uniform entry, and the "entry page number" of their computed entry address coincides with the line interrupt, coming from an "in-page offset" equal to 2(CSR.ECFG.VS+2)×78(0x4E) of their computed entry address.

+
+
+
+

6.2.4. Message-Interrupt-Response-Processing

+
+

When the message interrupt is routed to the specified processor core, the processor core will set the corresponding status position of internal CSR.MSGIS0~CSR.MSGIS3 to 1 according to the interrupt number, and this process is recorded for the message interrupt. Then the processor core selects the interrupt with the highest priority among the recorded message interrupts whose interrupt number is not lower than the message interrupt enable priority threshold (recorded in the CSR.MSGIE.PT field), and records its message interrupt number in the CSR.MSGOR.INTNUM field, and sets the CSR.MSGOR.NULL bit to zero CSR.ESTAT.MSGINT position 1, this process picks and sets the message interrupt request for the message interrupt. When the CSR.ESTAT.MSGINT bit is 1, only the global interrupt enables CSR.CRMD.IE to block the message interrupt requests that are picked and set.

+
+
+

In the case that the CSR.ESTAT.MsgInt bit is 1, if the software reads the CSR.MSGIR register, the hardware will automatically clear the corresponding status of CSR.MSGIS0 to CSR.MSGIS3 according to the message interrupt number currently recorded in the CSR.MSGIR.INTUM field 0. If there is no more selected message interrupt in CSR.MSGIS0~CSR.MSGIS3 after the interrupt status bit of this message is cleared 0, the CSR.ESTAT.MSGINT bit will be cleared 0 by the hardware and CSR.MSGIR.NULL position 1 in the next processor core internal clock cycle. Software developers are especially reminded that because of the "read clear" nature of the CSR.MSGIR register, it is recommended to read the CSR.ESTAT.MSGINT bits when checking for pending message interrupts.

+
+
+
+
+

6.3. Exceptions

+
+

6.3.1. Exception Entry

+
+

The entry for the TLB refill exception comes from CSR.TLBRENTRY.

+
+
+

The entry for the machine error exception comes from CSR.MERRENTRY.

+
+
+

Exceptions other than the above two exceptions are called general exceptions, and their entries are calculated by address|offset. +Here | is a bitwise OR operation.

+
+
+

All general exception entries have the same base address from CSR.EENTRY.

+
+
+

The offset of the general exception entry is determined by both the mode of the interrupt offset and the exception number (ecode), which is equal to 2(CSR.ERG.V+2)×(ecode+64). +See the ecode column in Table of exception encoding for general exceptions except interrupts; the ecode for interrupts is its int number plus 64.

+
+
+

When CSR.ECFG.VS=0, all general exceptions have the same entry, and the software needs to determine the specific exception type by Ecode and IS fields in CSR.ESTA. +When CSR.ECFG.VS!=0, different interrupt sources have different exception entries and the software does not need to confirm the exception type by CSR.ESTA.

+
+
+

Since the exception entry is an offset on the base address calculated by bitwise OR operation, when CSR.ECFG.VS!=0, during assigning the exception entry base address, the software needs to ensure that all possible offsets do not exceed the bound alignment space corresponding to the low bit of the entry base address.

+
+
+
+

6.3.2. Exception Priority

+
+

The exception priority follows two basic principles: first, the interrupt priority is higher than the exception; second, for the exception, the highest priority is detected in the fetching stage, followed by the priority detected in the decoding stage, and the priority detected in the execution stage.

+
+
+

For exceptions detected in the fetching stage: the highest priority is given to the fetch operation watchpoint exception, the second highest priority is given to the fetch operation address error exception, the second highest priority is given to TLB-related exceptions, and the lowest priority is given to the machine error exception.

+
+
+

The exceptions that can be detected in the decoding stage are mutually exclusive, so there is no need to consider the priority between them.

+
+
+

Only memory access instructions may trigger multiple exceptions at the same time during the execution stage, with the following priorities in descending order: Address aLignment fault Exception (ALE) caused by unaligned addresses for memory access instructions requesting alignment addresses > ADdress error Exception (ADE) > Bound Check Exception (BCE)[2] > TLB-related exceptions[3] > Address aLignment fault Exception (ALE) caused by addresses that span two pages of different Cache attributes for memory access instructions allowing non-alignment addresses.

+
+
+
+

6.3.3. General Hardware Exception Handling of General Exceptions

+
+

There may be some differences in the handling of different general exceptions by the processor, and the general hardware exception handling of general exceptions is described here.

+
+
+

When a general exception is triggered, the processor does the following:

+
+
+
    +
  • +

    Store PLV and IE in CSR.CRMD to PPLV and PIE in CSR.PRMD, then set PLV in CSR.CRMD to 0 and IE to 0;

    +
    • +
  • +

    For implementations that support the Watch function, also store WE in CSR.CRMD to PWE in CSR.PRMD and then set WE in CSR.CRMD to 0;

    +
    • +
  • +

    Record PC that triggered the exception by CSR.ERA;

    +
    • +
  • +

    Jump to the exception entry to fetch instructions.

    +
    • +
+
+
+

When the software executes the ERTN instruction returning from general exceptions, the processor does the following:

+
+
+
    +
  • +

    Restore PPLV and PIE in CSR.PRMD to PLV and IE in CSR.CRMD;

    +
    • +
  • +

    For implementations that support the Watch function, also restore PWE in CSR.PRMD to WE in CSR.CRMD;

    +
    • +
  • +

    Jump to the address recorded by CSR.ERA to fetch instructions.

    +
    • +
+
+
+

For the above hardware implementation, the software needs to save PPLV and PIE in CSR.PRMD if the interrupt needs to be enabled during the exception handling, and restore the saved contents to CSR.PRMD before the exception returns.

+
+
+
+

6.3.4. Hardware Exception Handling of TLB Refill Exception

+
+

When the TLB refill exception is triggered, the processor does the following:

+
+
+
    +
  • +

    Store PLV and IE in CSR.CRMD to PPLV and PIE in CSR.TLBRPRMD, then set PLV in CSR.CRMD to 0, IE to 0, DA to 1 and PG to 0.

    +
    • +
  • +

    For implementations that support the Watch function, also store WE in CSR.CRMD to PWE in CSR.TLBRPRMD, and then set WE in CSR.CRMD to 0;

    +
    • +
  • +

    Record the [GRLEN-1:2] bits of the PC that triggered the exception instruction by ERA in CSR.TLBRERA, and set IsTLBR in CSR.TLBRERA to 1;

    +
    • +
  • +

    Record the virtual memory access address that triggered the exception (or PC if triggered by fetching instructions) by CSR.TLBRBADV and the [PALEN-1:13] bits of address by VPPN in CSR.TLBREHI;

    +
    • +
  • +

    Jump to the exception entry configured by CSR.TLBRENTRY to fetch instructions.

    +
    • +
+
+
+

When software executes the ERTN instruction to return from TLB refill exception, the processor does the following:

+
+
+
    +
  • +

    Restore PPLV and PIE in CSR.TLBRPRMD to PLV and IE in CSR.CRMD;

    +
    • +
  • +

    For implementations that support the Watch function, restore PWE in CSR.TLBRPRMD to WE in CSR.CRMD;

    +
    • +
  • +

    Set DA in CSR.CRMD to 0 and PG to 1;

    +
    • +
  • +

    Set IsTLBR in CSR.TLBRERA to 0;

    +
    • +
  • +

    Jump to the address recorded by CSR.TLBRERA to fetch instructions.

    +
    • +
+
+
+
+

6.3.5. Hardware Exception Handling of Machine Error Exception

+
+

When the machine error exception is triggered, the processor does the following:

+
+
+
    +
  • +

    Store PLV, IE, DA, PG, DATF and DATM in CSR.CRMD to PPLV, PIE, PDA, PPG, PDATF and PDATM in CSR.MERRCTL, then set PLV in CSR.CRMD to 0, IE to 0, DA to 1, PG to 0, DATF to 0, and DATM to 0;

    +
    • +
  • +

    For implementations that support the Watch function, also store WE in CSR.CRMD to PWE in CSR.MERRCTL, and then set WE in CSR.CRMD to 0;

    +
    • +
  • +

    Record PC that triggered the exception instruction by CSR.MERRERA;

    +
    • +
  • +

    Set IsMERR in CSR.MERRCTL to 1;

    +
    • +
  • +

    Record the specific error message by CSR.ERRINFO and CSR.MERRINFO1;

    +
    • +
  • +

    Jump to the exception entry configured by CSR.MERRENTRY to fetch instructions.

    +
    • +
+
+
+

When the software executes the ERTN instruction returning from the machine error exception, the processor does the following:

+
+
+
    +
  • +

    Restore PPLV, PIE, PDA, PPG, PDATF and PDATM in CSR.MERRCTL;

    +
    • +
  • +

    For implementations that support the Watch function, also restore PWE in CSR.MERRCTL to WE in CSR.CRMD;

    +
    • +
  • +

    Set the IsMERR in CSR.TLBRERA to 0;

    +
    • +
  • +

    Jump to the address recorded by CSR.MERRERA to fetch instructions.

    +
    • +
+
+
+
+
+

6.4. Reset

+
+

A reset will reset all logic in the processor core and place the circuit in a determined state. +The definition of the state of the processor after reset is given here.

+
+
+

The PC after the reset is 0x1C000000. +Since the MMU must be in direct address translation mode after the reset, the physical address of the first instruction fetched after reset is also 0x1000000.

+
+
+

After the reset, the contents of the registers in the determined state are:

+
+
+
    +
  • +

    PLV in CSR.CRMD is 0, IE is 0, DA is 1, PG is 0, DATF is 0, DATM is 0, and WE is 0;

    +
    • +
  • +

    FPUen, VPUen, XVPUen and BTUen in CSR.PUCTL are all 0 values;

    +
    • +
  • +

    All configurable bits in CSR.MISC are 0;

    +
    • +
  • +

    VS and LIE in CSR.ECFG are 0;

    +
    • +
  • +

    All bits of IS[1:0] in CSR.ESTA are 0;

    +
    • +
  • +

    RDVA in CSR.RVACFG is 0;

    +
    • +
  • +

    En in CSR.TCFG is 0;

    +
    • +
  • +

    KLO in CSR.LLBCTL is 0;

    +
    • +
  • +

    IsTLBR in CSR.TLBRERA is 0;

    +
    • +
  • +

    IsMERR in CSR.MERRCTL is 0;

    +
    • +
  • +

    PLV0-PLV3 in all implemented CSR.DMWs are 0;

    +
    • +
  • +

    All configurable bits except EvCode in all implemented CSR.PMCFGs are 0;

    +
    • +
  • +

    All configurable bits in all implemented data breakpoint CSRs are 0;

    +
    • +
  • +

    All configurable bits in all implemented instruction breakpoint CSRs are 0;

    +
    • +
  • +

    DST in CSR.DEBUG is 0.

    +
    • +
+
+
+

In addition to what is specified above, the values of all other software-visible registers in the processor are undefinded after the reset. +The software has to set their values before they can be used.

+
+
+

Whether TLB and Cache need to do a hardware reset during the reset is decided by the implementation. +The software responsible for booting determines whether to do a software reset via the processor configuration information.

+
+
+
+
+
+

7. Control and Status Registers

+
+
+

7.1. Overview of Control and Status Registers

+ + +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 14. Overview of Control and Status Registers
AddressName

0x0

CuRrent MoDe information

CRMD

0x1

PRe-exception MoDe information

PRMD

0x2

Extended component Unit ENable

EUEN

0x3

MISCellaneous controller

MISC

0x4

Exception ConFiGuration

ECFG

0x5

Exception STATus

ESTAT

0x6

Exception Return Address

ERA

0x7

BAD virtual Address

BADV

0x8

BAD Instruction

BADI

0xC

Exception ENTRY address

EENTRY

0x10

TLB InDeX

TLBIDX

0x11

TLB Entry HIgh-order bits

TLBEHI

0x12

TLB Entry LOw-order bits 0

TLBELO0

0x13

TLB Entry LOw-order bits 1

TLBELO1

0x18

Address Space IDentifier

ASID

0x19

Page Global Directory base address for Lower half address space

PGDL

0x1A

Page Global Directory base address for Higher half address space

PGDH

0x1B

Page Global Directory base address

PGD

0x1C

Page Walk Controller for Lower half address space

PWCL

0x1D

Page Walk Controller for Higher half address space

PWCH

0x1E

STLB Page Size

STLBPS

0x1F

Reduced Virtual Address ConFiGuration

RVACFG

0x20

CPU IDentity

CPUID

0x21

Privileged Resource ConFiGuration 1

PRCFG1

0x22

Privileged Resource ConFiGuration 2

PRCFG2

0x23

Privileged Resource ConFiGuration 3

PRCFG3

0x30+n (0 ≤ n ≤ 15)

Data SAVA register

SAVEn

0x40

Timer IDentity

TID

0x41

Timer ConFiGuration

TCFG

0x42

Timer VALue

TVAL

0x43

CouNTer Compensation

CNTC

0x44

Timer Interrupt CLeaRing

TICLR

0x60

LLBit ConTroLler

LLBCTL

0x80

IMPlementation-specific ConTroLler 1

IMPCTL1

0x81

IMPlementation-specific ConTroLler 2

IMPCTL2

0x88

TLB Refill exception ENTRY address

TLBRENTRY

0x89

TLB Refill exception BAD Virtual address

TLBRBADV

0x8A

TLB Refill Exception Return Address

TLBRERA

0x8B

TLB Refill exception data SAVE register

TLBRSAVE

0x8C

TLB Refill exception Entry LOw-order bits 0

TLBRELO0

0x8D

TLB Refill exception Entry LOw-order bits 1

TLBRELO1

0x8E

TLB Refill exception Entry HIgh-order bits

TLBREHI

0x8F

TLB Refill exception PRe-exception MoDe information

TLBRPRMD

0x90

Machine ERRor ConTroLler

MERRCTL

0x91

Machine ERRor INFOrmation 1

MERRINFO1

0x92

Machine ERRor INFOrmation 2

MERRINFO2

0x93

Machine ERRor exception ENTRY address

MERRENTRY

0x94

Machine ERRor Exception Return Address

MERRERA

0x95

Machine ERRor exception data SAVE register

MERRSAVE

0x98

Cache TAGs

CTAG

0x180+n (0 ≤ n ≤ 3)

Direct Mapping configuration Window n

DMWn

0x200+2n (0 ≤ n ≤ 31)

Performance Monitor ConFiGuration n

PMCFGn

0x201+2n (0 ≤ n ≤ 31)

Performance Monitor overall CouNTer n

PMCNTn

0x300

Memory load/store WatchPoint overall Controller

MWPC

0x301

Memory load/store WatchPoint overall Status

MWPS

0x310+8n (0 ≤ n ≤ 7)

Memory load/store WatchPoint n ConFiGuration 1

MWPnCFG1

0x311+8n (0 ≤ n ≤ 7)

Memory load/store WatchPoint n ConFiGuration 2

MWPnCFG2

0x312+8n (0 ≤ n ≤ 7)

Memory load/store WatchPoint n ConFiGuration 3

MWPnCFG3

0x313+8n (0 ≤ n ≤ 7)

Memory load/store WatchPoint n ConFiGuration 4

MWPnCFG4

0x380

Fetch WatchPoint overall Controller

FWPC

0x381

Fetch WatchPoint overall Status

FWPS

0x390+8n (0 ≤ n ≤ 7)

Fetch WatchPoint n ConFiGuration 1

FWPnCFG1

0x391+8n (0 ≤ n ≤ 7)

Fetch WatchPoint n ConFiGuration 2

FWPnCFG2

0x392+8n (0 ≤ n ≤ 7)

Fetch WatchPoint n ConFiGuration 3

FWPnCFG3

0x393+8n (0 ≤ n ≤ 7)

Fetch WatchPoint n ConFiGuration 4

FWPnCFG4

0x500

DeBuG register

DBG

0x501

Debug Exception Return Address

DERA

0x502

Debug data SAVE register

DSAVE

+
+
+

7.2. Characteristics of Accessing Control and Status Registers

+
+

7.2.1. Attributes of Reading and Writing

+
+

The definition of the “read/write” attribute for each field is described later in this manual in the control and status register field definition. +The “read/write” attributes are defined primarily from the perspective of software and are divided into four types:

+
+
+
    +
  • +

    RW - readable and writable. +Software can write any value, except for illegal values that are explicitly stated in the definition and lead to uncertainty in the processor’s execution. +Normally, software writes to these fields before it reads them, and what is read should be the value written. +However, when the accessed field can be updated by hardware, or when an interrupt occurs between the two instructions executing the read and write operation, it is possible that the read value is not consistent with the written value.

    +
    • +
  • +

    R - read-only. +Software writes to these fields will not update their contents, and will have no side effects.

    +
    • +
  • +

    R0 - always return 0 if read these fields. +But at the same time software must ensure that either it avoids updating these fields by setting the CSR write mask bit, or it must write 0 when updating these fields. +This requirement is to ensure software backward compatibility. +For hardware implementations, fields marked with this attribute will prohibit software writing.

    +
    • +
  • +

    W1 - write 1 is valid. +Software writes 0 to these fields will not clear them to 0 and will have no side effects. +Also, the read values of these fields have no real meaning and software should ignore these values.

    +
    • +
+
+
+
+

7.2.2. Length of Control and Status Registers in LA32 and LA64

+
+

The length of all status control registers is either fixed 32 bits, or it depends on whether the implementation is LA32 or LA64. +For the first type of registers, when they are accessed by CSR instructions in LA64, retrun values of reading these registers are symbolic expansion to 64 bits, and bits higher than 32 bits of values of writing to them are automatically ignored by hardware. +For the second type, the definitions will clearly indicate the difference between LA32 and LA64.

+
+
+
+

7.2.3. Access Effects of Undefined and Unimplemented Control and Status Registers

+
+

When software uses CSR instructions to access CSR objects that are not defined in the architecture specification or that are implementable entries defined in the architecture specification but not implemented by the specific hardware, the return value of reading can be any value, but the write operation will not change the software-visible processor state.

+
+
+

Although software writes to these undefined or unimplemented status control registers do not change the software-visible processor state, software should not write to these registers if it wants to ensure backward compatibility.

+
+
+
+
+

7.3. Conflicts Caused by Control and Status Registers

+
+

Conflicts caused by the control and status register are maintained by the hardware, and the software does not need to add barrier-type instructions for avoiding conflict.

+
+
+
+

7.4. Basic Control and Status Registers

+
+

7.4.1. Current Mode Information (CRMD)

+
+

The information in this register is used to determine the the processor core’s privilege level, global interrupt enable bit, watchpoint enable bit, and address translation mode at that time.

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 15. Definition of current mode information register
BitsNameRead/WriteDescription

1:0

PLV

RW

Current privilege level. +The legal value range is 0 to 3, where 0 is the highest privilege level and 3 is the lowest privilege level.

+

When an exception is triggered, the hardware sets the value of this field to 0 to ensure that it is at the highest privilege level after being caught.

+

When the ERTN instruction is executed to return from the exception handler, if CSR.MERRCTL.IsMERR=1, the hardware restores the value of the PPLV field of CSR.MERRCTL to here;

+

otherwise, if CSR.TLBRERA.IsTLBR=1, the hardware restores the value of the PPLV field of CSR.TLBRPRMD to here; otherwise, the hardware restores the value of the PPLV field of CSR.TLBRPRMD to here;

+

otherwise, the hardware restores the value of the PPLV field of CSR.TLBRPRMD to here. +Hardware restores the value of the PPLV field of CSR.PRMD to here.

2

IE

RW

Current global interrupt enable bit, which is active high.

+

When an exception is triggered, the hardware sets the value of this field to 0, to ensure that the interrupt is masked when caught. +This field needs to be explicitly set to 1 when the exception handler decides to re-open the interrupt response.

+

When the ERTN instruction is executed to return from the exception handler, +if CSR.MERRCTL.IsMERR=1, the hardware restores the value of the PIE field of CSR.MERRCTL to this field;

+

Otherwise, if CSR.TLBRERA.IsTLBR=1, the hardware restores the value of the PIE field of CSR.TLBRPRMD here;

+

Otherwise, the hardware restores the value of the PIE field of CSR.PRMD to here.

3

DA

RW

Direct address translation mode enable bit, which is active high.

+

The hardware sets this field to 1 when a TLB refill exception or a machine error exception is triggered.

+

If CSR.MERRCTL.IsMERR=1, the hardware restores the value of the PDA field of CSR.MERRCTL when the ERTN instruction is executed and returns from the exception handler;

+

otherwise, if CSR.TLBRERA.IsTLBR=1, the hardware sets this field to 0.

+

The legal combination of DA and PG bits is 0, 1 or 1, 0. +The result is uncertain when the software is configured for other combinations.

4

PG

RW

Mapped address translation mode enable bit, which is active high.

+

The hardware sets this field to 0 when a TLB refill exception or a machine error exception is triggered.

+

When the ERTN instruction is executed to return from an exception handler,

+

if CSR.MERRCTL.IsMERR=1, the hardware restores the value of the PPG field of CSR.MERRCTL to this;

+

otherwise, if CSR.TLBRERA.IsTLBR=1, the hardware sets this field to 1.

+

The legal combination of PG and DA bits is 0, 1 or 1, 0. +The result is uncertain when the software is configured for other combinations.

6:5

DATF

RW

The type of memory access for fetch operations when in direct address translation mode.

+

The hardware sets this field to 0 when a machine error exception is triggered.

+

When the execution of the ERTN instruction returns from the exception handler and CSR.MERRCTL.IsMERR=1, the hardware restores the value of the PDATF field of CSR.MERRCTL to here.

+

In the case of using software to handle TLB refill, when the software sets PG to 1, it needs to set the DATF field to 0b01 at the same time, which is the consistent cacheable type.

8:7

DATM

RW

The type of memory access for load and store operations when in direct address translation mode.

+

The hardware sets this field to 0 when a machine error exception is triggered.

+

When the execution of the ERTN instruction returns from the exception handler and CSR.MERRCTL.IsMERR=1, the hardware restores the value of the PDATM field of CSR.MERRCTL to here.

+

In the case of using software to handle TLB refill, when the software sets PG to 1, it needs to set DATM to 0b01 at the same time, i.e., consistent cacheable type.

9

WE

RW

Instruction and data watchpoints enable bit, which is active high.

+

The hardware sets the value of this field to 0 when an exception is triggered.

+

When the ERTN instruction is executed to return from the exception handler.

+

If CSR.MERRCTL.IsMERR=1, the hardware restores the value of the PWE field of CSR.MERRCTL to here;

+

otherwise, if CSR.TLBRERA.IsTLBR=1, the hardware restores the value of the PWE field of CSR.TLBRPRMD to here;

+

Otherwise, the hardware restores the value of the PWE field of CSR.PRMD here.

31:10

0

R0

Reserved field. +Return 0 if read this field and the software does not allow to change its value.

+
+
+

7.4.2. Pre-exception Mode Information (PRMD)

+
+

When an exception is triggered, if the exception type is not TLB refill exception and machine error exception, the hardware will save the processor core’s privilege level, global interrupt enable bit and watchpoint enable bit at that time to the pre-exception mode information register for restoring the processor core to the context when the exception returns.

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 16. Definition of pre-exception mode information register
BitsNameRead/WriteDescription

1:0

PPLV

RW

When an exception is triggered, the hardware records the old value of the PLV field in CSR.CRMD in this field if the exception type is not a TLB refill exception and a machine error exception.

+

When the exception being processed is neither a TLB refill exception (CSR.TLBRERA.IsTLBR=0) nor a machine error exception (CSR.MERRCTL.IsMERR=0), the hardware restores the value of this field to the PLV field of CSR.CRMD when the ERTN instruction is executed to return from the exception handler.

2

PIE

RW

When an exception is triggered, the hardware records the old value of the IE field in CSR.CRMD in this field if the exception type is not a TLB refill exception and a machine error exception.

+

When the exception being processed is neither a TLB refill exception (CSR.TLBRERA.IsTLBR=0) nor a machine error exception (CSR.MERRCTL.IsMERR=0), the hardware restores the value of this field to the IE field of CSR.CRMD when the ERTN instruction is executed to return from the exception handler.

3

PWE

RW

When an exception is triggered, the hardware records the old value of the WE field in CSR.CRMD in this field if the exception type is not a TLB refill exception and a machine error exception.

+

When the exception being processed is neither a TLB refill exception (CSR.TLBRERA.IsTLBR=0) nor a machine error exception (CSR.MERRCTL.IsMERR=0), the hardware restores the value of this field to the WE field of CSR.CRMD when the ERTN instruction is executed to return from the exception handler.

31:4

0

R0

Reserved field. +Return 0 if read this field and the software does not allow to change its value.

+
+
+

7.4.3. Extended Component Unit Enable (EUEN)

+
+

In addition to the base integer instruction set and the privileged instruction set, the base floating-point instruction set, the binary translation extension instruction set, the 128-bit vector extension instruction set, and the 256-bit vector extension instruction set each have software-configurable enable bits. +When these enable controls are disabled, execution of the corresponding instruction will trigger the corresponding instruction unavailable exception. +Software uses this mechanism to determine the scope when saving the context. +Hardware implementations can also use the control bits here to implement circuit power control.

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 17. Definition of extended component unit enable register
BitsNameRead/WriteDescription

0

FPE

RW

The base floating-point instruction enable bit. +When this bit is 0, execution of the base floating-point instruction as described in Overview of Floating-Point Instructions will trigger a floating-point instruction disable exception (FPD).

1

SXE

RW

The 128-bit vector expansion instruction enable bit. +When this bit is 0, execution of the 128-bit vector expansion instruction as described in Volume 2 will trigger the 128-bit vector expansion instruction disable exception (SXD).

2

ASXE

RW

The 256-bit vector expansion instruction enables the control bit. +When this bit is 0, execution of the 256-bit vector expansion instruction as described in Volume 2 will trigger the 256-bit vector expansion instruction disable exception (ASXD).

3

BTE

RW

Binary translation expansion instruction enable bit. +When this bit is 0, execution of the binary translation expansion instruction described in Volume 2 will trigger the binary translation expansion instruction disable exception (BTD).

31:4

0

R0

Reserved field. +Return 0 if read this field, and software is not allowed to change its value.

+
+
+

7.4.4. Miscellaneous Controller (MISC)

+
+

This register contains a number of control bits for the operating behavior of the processor core at different privilege levels, including whether to enable 32-bit address mode, whether to allow partially privileged instructions at non-privileged levels, whether to enable address non-alignment check, and whether to enable page table write protection check.

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 18. Definition of miscellaneous controller register
BitsNameRead/WriteDescription

0

0

RO

Reserved field. +Return 0 if read this field and software is not allowed to change its value.

1

VA32L1

RW

Whether to enable 32-bit address mode at the PLV1 privilege level. +0 - disable, 1 - enable. +This bit can be read and written only in LA64, at the LA32 privilege level, this attribute is R0.

2

VA32L2

RW

Whether to turn on 32-bit address mode at the PLV2 privilege level. +0 - disable, 1 - enable. +This bit is read/write only in LA64, and at the LA32 privilege level, this attribute is R0.

3

VA32L3

RW

Whether to enable 32-bit address mode at the PLV3 privilege level. +0 - disable, 1 - enable. +This bit is read/write only in LA64, and at the LA32 privilege level, this attribute is R0.

4

0

R0

Reserved field. +Return 0 if read this field and software is not allowed to change its value.

5

DRDTL1

RW

Whether to disable RDTIME-like instructions at the PLV1 privilege level. +When this bit is 1, execution of an RDTIME-like instruction at the PLV1 privilege level will trigger an instruction privilege level error exception (IPE).

6

DRDTL2

RW

Whether to disable RDTIME-like instructions at the PLV2 privilege level. +When this bit is 1, execution of RDTIME-like instructions at PLV2 privilege level will trigger instruction privilege level error exception (IPE).

7

DRDTL3

RW

Whether to disable RDTIME class instructions at the PLV3 privilege level. +When this bit is 1, execution of RDTIME-like instructions at the PLV3 privilege level will trigger an instruction privilege level error exception (IPE).

8

0

R0

Reserved field. +Return 0 if read this field and software is not allowed to change its value.

9

RPCNTL1

RW

Whether to allow software reads of the performance counter at the PLV1 privilege level. +When this bit is 1, the PLV1 privilege level PCNT will not trigger an instruction privilege level error exception (IPE), if the CSRRD instruction is used to access any of the implemented performance counters at the PLV1 privilege level.

10

RPCNTL2

RW

Whether software reads of the performance counter are allowed at the PLV2 privilege level. +When this bit is 1, the PLV2 privilege level When this bit is 1, accessing any implemented performance counter PCNT with CSRRD instruction at the PLV2 privilege level does not trigger instruction privilege level error exception (IPE).

11

RPCNTL3

RW

Whether software reads of the read performance counter are allowed at the PLV3 privilege level. +When this bit is 1, the PLV3 privilege level When this bit is 1, accessing any implemented performance counter PCNT with the CSRRD instruction at the PLV3 privilege level does not trigger an instruction privilege level error exception (IPE).

12

ALCL0

RW

Whether to perform a non-alignment check for non-vector load/store instructions that are allowed to be non-aligned at PLV0 privilege level. +1 indicates that the check is performed, and an address alignment error exception is triggered if illegal. +This bit is read/write only if the hardware implementation supports non-aligned addresses for these non-vector load/store instructions. +Otherwise, the bit is a read-only constant 1.

13

ALCL1

RW

Whether to perform a non-alignment check for non-vector load/store instructions[4] that are allowed to be non-aligned at the PLV1 privilege level. +1 indicates that the check is performed and triggers an address alignment error exception if illegal.

+

This bit is read/write only if the hardware implementation supports non-aligned addresses for these non-vector load/store instructions. +Otherwise, the bit is a read-only constant 1.

14

ALCL2

RW

Whether to perform a non-alignment check for non-vector load/store instructions[4] that are allowed to be non-aligned at the PLV2 privilege level. +1 indicates that the check is performed and triggers an address alignment error exception if illegal.

+

This bit is read/write only if the hardware implementation supports non-aligned addresses for these non-vector load/store instructions. +Otherwise, the bit is a read-only constant 1.

15

ALCL3

RW

Whether to perform a non-alignment check for non-vector load/store instructions[4] that are allowed to be non-aligned at the PLV3 privilege level. +1 indicates that the check is performed and triggers an address alignment error exception if illegal.

+

This bit is read/write only if the hardware implementation supports non-aligned addresses for these non-vector load/store instructions. +Otherwise, the bit is a read-only constant 1.

16

DWPL0

RW

Whether to disable the check of the page table entry write protection during TLB virtual and real address translation at the PLV0 privilege level. +When this bit is 1, the store instruction will not trigger a page modification exception even if it accesses a page table entry with D=0.

17

DWPL1

RW

Whether to disable the check of the page table entry write protection during TLB virtual and real address translation at the PLV1 privilege level. +When this bit is 1, the store instruction will not trigger a page modification exception even if it accesses a page table entry with D=0.

18

DWPL2

RW

Whether to disable the check of the page table entry write protection during TLB virtual and real address translation at the PLV2 privilege level. +When this bit is 1, the store instruction will not trigger a page modification exception even if it accesses a page table entry with D=0.

31:19

0

RO

Reserved field. +Return 0 if read this field and software is not allowed to change its value.

+
+
+

7.4.5. Exception Configuration (ECFG)

+
+

This register is used to control the entry calculation method of exceptions and interrupts and the local enable bit of each interrupt.

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 19. Definition of exception configuration register
BitsNameRead/WriteDescription

12:0

LIE

RW

Local interrupt enable bits, which are high valid. +These local interrupt enable bits correspond to the 13 interrupt sources recorded in the IS field in CSR.ESTAT. +Each bit controls one interrupt source.

15:13

0

R0

Reserved field. +Return 0 if read this field, and software is not allowed to change its value.

18:16

VS

KW

Configure the spacing of exceptions and interrupt entries. +When VS=0, all exceptions and interrupts have the same entry base address. +When VS!=0, the entry base address spacing between each exception and interrupt is 2VS instructions. +Since the TLB refill exceptions and machine error exceptions have separate entry base addresses, the entry of both exceptions is not affected by the VS field.

31:19

0

RO

Reserved field. +Return 0 if read this field, and software is not allowed to change its value.

+
+
+

7.4.6. Exception Status (ESTAT)

+
+

This register records the status information of the exceptions, including the first and second level encoding of the triggered exceptions, and the status of each interrupt.

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 20. Definition of exception status register
BitsNameRead/WriteDescription

1:0

IS[1:0]

RW

The status bits of the two software interrupts. +Bit 0 and 1 correspond to SWI0 and SWI1 respectively.

+

Software interrupt setting is also done by these two bits, writing 1 sets the interrupt, and writing 0 clears the interrupt.

12:2

IS[12:2]

R

The interrupt status bit. +1 indicates that the corresponding interrupt is set up. +There is 1 inter-processor interrupt (IPI), 1 timer interrupt (TI), 1 performance counter overflow interrupt (PCOV), 8 hardware interrupts (HWI0-HWI7).

+

In line-based interrupt mode, the hardware only records each interrupt source per clock cycle to these bits. +The requirement that all interrupts must be level interrupts at this time is guaranteed by the interrupt source and is not maintained here.

15:13

0

R0

Reserved field. +Return 0 if read this field, and software is not allowed to change its value.

21:16

Ecode

R

Exception encoding. +When an exception is triggered: if it is a TLB refill exception or a machine error exception, this field remains unchanged; otherwise, the hardware writes the value defined in the Ecode column in the following table to this field according to the exception type.

30:22

EsubCode

R

Exception sub encoding. +When an exception is triggered: if it is a TLB refill exception or a machine error exception, the field remains unchanged; otherwise, the hardware writes the value defined in the EsubCode column in the following table to this field according to the exception type.

31

0

R0

Reserved field. +Return 0 if read this field and software is not allowed to change its value.

+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 21. Table of exception encoding
EcodeEsubCodeException CodeException Type

0x0

INT

Only when CSR.ECFG.VS=0, it means it is an INTerrupt.

0x1

PIL

Page Invalid exception for Load operation

0x2

PIS

Page Invalid exception for Store operation

0x3

PIF

Page Invalid exception for Fetch operation

0x4

PME

Page Modification Exception

0x5

PNR

Page Non-Readable exception

0x6

PNX

Page Non-eXecutable exception

0x7

PPI

Page Privilege level Illegal exception

0x8

0

ADEF

ADdress error Exception for Fetching instructions

1

ADEM

ADdress error Exception for Memory access instructions

0x9

ALE

Address aLignment fault Exception

0xA

BCE

Bound Check Exception

0xB

SYS

SYStem call exception

0xC

BRK

BReaKpoint exception

0xD

INE

Instruction Non-defined Exception

0xE

IPE

Instruction Privilege error Exception

0xF

FPD

Floating-Point instruction Disable exception

0x10

SXD

128-bit vector (SIMD instructions) eXpansion instruction Disable exception

0x11

ASXD

256-bit vector (Advanced SIMD instructions) eXpansion instruction Disable exception

0x12

0

FPE

Floating-Point error Exception

1

VFPE

Vecctor Floating-Point error Exception

0x13

0

WPEF

WatchPoint Exception for Fetch watchpoint

1

WPEM

WatchPoint Exception for Memory load/store watchpoint

0x14

BTD

Binary Translation expansion instruction Disable exception

0x15

BTE

Binary Translation related exceptions

0x16

GSPR

Guest Sensitive Privileged Resource exception

0x17

HVC

HyperVisor Call exception

0x18

0

GCSC

Guest CSR Software Change exception

1

GCHC

Guest CSR Hardware Change exception

0x1A-0x3E

Reserved Codes

+
+
+

7.4.7. Exception Return Address (ERA)

+
+

When an exception is triggered, if the exception type is neither a TLB refill exception nor a machine error exception, the PC of the instruction that triggered the exception will be recorded in this register.

+
+ + ++++++ + + + + + + + + + + + + + + + + +
Table 22. Definition of exception program counter register
BitsNameRead/WriteDescription

GRLEN-1:0

PC

RW

When an exception is triggered:

+

this field remains unchanged if the exception is a TLB refill exception or a machine error exception;

+

otherwise, the hardware records the PC of the instruction that triggered the exception here. +For LA64, in this case, if the privilege level that triggered the exception is in 32-bit address mode, then the higher 32 bits of the recorded PC are forced to 0.

+
+
+

7.4.8. Bad Virtual Address (BADV)

+
+

This register is used to record the bad address when a bad address exception is triggered. +Such exceptions include:

+
+
+
    +
  • +

    ADdress error Exception for Fetching instructions (ADEF), at this time the PC of the instruction is recorded

    +
    • +
  • +

    ADdress error Exception for Memory access instructions (ADEM)

    +
    • +
  • +

    Address aLignment fault Exception (ALE)

    +
    • +
  • +

    Bound Check Exception (BCE)

    +
    • +
  • +

    Page Invalid exception for Load operation (PIL)

    +
    • +
  • +

    Page Invalid exception for Store operation (PIS)

    +
    • +
  • +

    Page Invalid exception for Fetch operation (PIF)

    +
    • +
  • +

    Page Modification Exception (PME)

    +
    • +
  • +

    Page Non-Readable exception (PNR)

    +
    • +
  • +

    Page Non-eXecutable exception (PNX)

    +
    • +
  • +

    Page Privilege level Illegal exception (PPI)

    +
    • +
+
+ + ++++++ + + + + + + + + + + + + + + + + +
Table 23. Definition of bad virtual address register
BitsNameRead/WriteDescription

GRLEN-1:0

VAddr

RW

When a bad address exception exception is triggered, the hardware records the bad address here. +For LA64, if the privilege level that triggered the exception is in 32-bit address mode, the high 32 bits of the recorded virtual address are forced to 0.

+
+
+

7.4.9. Bad Instruction (BADI)

+
+

This register is used to record the instruction code of the instruction that triggers the synchronous-related exception. +The so-called synchronous-related exceptions are all exceptions except the INTerrupt (INT), the Guest CSR Hardware Change exception (GCHC), and the Machine ERRor exception (MERR).

+
+ + ++++++ + + + + + + + + + + + + + + + + +
Table 24. Definition of bad instruction register
BitsNameRead/WriteDescription

31:0

Inst

R

When a synchronous-related exception is triggered, the hardware records the instruction code that triggered the exception here.

+
+
+

7.4.10. Exception Entry Base Address (EENTRY)

+
+

This register is used to configure the entry base address for general exceptions and interrupts.

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + +
Table 25. Definition of exception entry base address register
BitsNameRead/WriteDescription

11:0

0

R

Read-only constant 0, writing to this field is ignored.

GRLEN-1:12

VPN

RW

The virtual page table number of the entry base address for general exceptions and interrupts.

+
+
+

7.4.11. Reduced Virtual Address Configuration (RVACFG)

+
+

This register is used to control the length of the address being reduced in the virtual address reduction mode.

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + +
Table 26. Definition of reduced virtual address configuration register
BitsNameRead/WriteDescription

3:0

RBits

RW

The number of the high order bits of the address to be reduced in the virtual address reduction mode. +It can be configured to a value between 0 and 8.

+

0 is a special configuration value that means that the virtual address reduction mode is disabled.

+

If the configured value is greater than 8, the processor behavior is undefined.

31:4

0

R0

Reserved field. +Return 0 if read this field and software is not allowed to change its value.

+
+
+

7.4.12. CPU Identity (CPUID)

+
+

This register contains the processor core number information.

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + +
Table 27. Definition of CPU identity register
BitsNameRead/WriteDescription

8:0

CoreID

R

The number of the processor core. +This information is used by the software to distinguish the individual processor cores in a multi-core system. +When the system is integrated, the processor core number information for each processor core is set by the hardware according to the specific implementation. +It is recommended that the processor core number be incremented from 0 in the system.

31:9

0

R0

Reserved field. +Return 0 if read this field and software is not allowed to change its value.

+
+
+

7.4.13. Privileged Resource Configuration 1 (PRCFG1)

+
+

This register contains the privileged resources information.

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 28. Definition of privileged resource configuration 1 register
BitsNameRead/WriteDescription

3:0

SAVENum

R

The number of SAVE control and status registers.

11:4

TimerBits

R

The number of valid bits of the timer minus 1.

14:12

VSMax

R

The maximum value that can be set for the exception and interrupt vector entry spacing (CSR.ECTL.VS).

31:15

0

R0

Reserved field. +Return 0 if read this field and software is not allowed to change its value.

+
+
+

7.4.14. Privileged Resource Configuration 2 (PRCFG2)

+
+

This register contains the privileged resources information.

+
+ + ++++++ + + + + + + + + + + + + + + + + +
Table 29. Definition of privileged resource configuration 2 register
BitsNameRead/WriteDescription

GRLEN-1:0

PSAVL

R

Indicates the page size that the TLB can support (Page Size). +When bit i is 1, it indicates that a page size of 2i bytes is supported.

+
+
+

7.4.15. Privileged Resource Configuration 3 (PRCFG3)

+
+

This register contains the privileged resources information.

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 30. Definition of privileged resource configuration 3 register
BitsNameRead/WriteDescription

3:0

TLBType

R

Indicates how the TLB is organized:

+

0: No TLB;

+

1: a fully associated Multiple page size TLB (MTLB)

+

2: One fully associative Multiple page size TLB (MTLB) + one group associative Singular-Page-Size TLB (STLB);

+

Other values: Reserved.

11:4

MTLBEntries

R

When TLBType=0, the field is read-only constant 0;

+

When TLBType=1 or TLBType=2, the value of this field is the number of entries in the fully associative multipage size TLB minus 1.

19:12

STLBWays

R

When TLBType=0 or TLBType=1, the field is read-only constant at 0;

+

When TLBType=2, the value of this field is the number of ways in the group associative singular-page-size TLB minus 1.

25:20

STLBSets

R

When TLBType=0 or TLBType=1, the field is read-only constant to 0;

+

When TLBType=2, the value of this field is the power of the number of entries per way in the group associative singular-page-size TLB, i.e., 2STLBSets entries per way.

31:26

0

R0

Reserved field. +Return 0 if read this field and the software is not allowed to change its value.

+
+
+

7.4.16. Data Save Register (SAVE)

+
+

The data save registers are used to temporarily store data for the system software. +Each data save register can store data from one general-purpose register.

+
+
+

The minimum number of data save registers is 1, and the maximum number is 16. +The exact number of registers can be found in CSR.PRCFG1.SAVENum. +Starting from SAVE0, the addresses of each SAVE register are 0x30, 0x31, …​ , 0x30+SAVENum-1.

+
+
+

All data save control and status registers have the same format, as shown in the table.

+
+ + ++++++ + + + + + + + + + + + + + + + + +
Table 31. Definition of data save register
BitsNameRead/WriteDescription

GRLEN-1:0

Data

RW

Data for software to read and write only. +The hardware does not modify the contents of this field except for the execution of CSR instructions.

+
+
+

7.4.17. LLBit Controller (LLBCTL)

+
+

This register is used for the access control operations performed on the LLBit.

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 32. Definition of LLBit controller register
BitsNameRead/WriteDescription

0

ROLLB

R

A read-only bit. +Reading this bit will return the value of the current LLBit.

1

WCLLB

W1

A software writing 1 to this bit will clear the LLBit to 0. +A software writing 0 to this bit will be ignored by hardware.

2

KLO

RW

Used to control the operation of the LLBit when the ERTN instruction is executed. +When this bit is 1, the LLBit is not cleared to 0 when the ERTN instruction is executed. +But the bit is automatically cleared to 0 by the hardware; it means that each time KLO is set to 1, it can only affect the execution of the ERTN instruction once.

31:3

0

R0

Reserved field. +Return 0 if read this field, and software is not allowed to change its value.

+
+
+

7.4.18. Implementation-specific Controller 1 (IMPCTL1)

+
+

This register contains control information related to the microstructure characteristics at the time of the specific implementation. +Its format and the specific meaning of each field are defined by the specific implementation.

+
+
+
+

7.4.19. Implementation-specific Controller 2 (IMPCTL2)

+
+

This register contains control information related to the microstructure characteristics at the time of the specific implementation. +Its format and the specific meaning of each field are defined by the specific implementation.

+
+
+
+

7.4.20. Cache Tags (CTAG)

+
+

This register is used when the CACOP instruction accesses the Cache directly, to store the contents read from the CacheTag or the contents to be written to the CacheTag. +The format and the meaning of each field are defined by the implementation.

+
+
+
+
+ +
+

7.5.1. TLB Index (TLBIDX)

+
+

This register contains information such as the index associated with the TLB-related instruction when executing TLB-related instructions. +The length of the Index field in the table depends on implementation, although LoongArch allows for an Index length of no more than 16 bits.

+
+
+

This register also contains the information related to the PS and P fields in the TLB table entry when executing TLB-related instructions.

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 33. Definition of TLB index register
BitsNameRead/WriteDescription

n-1:0

Index

RW

When executing the TLBRD and TLBWR instructions, the index of the access TLB table entry comes from here.

+

When executing the TLBSRCH instruction, if it hits, the index of the hit entry is recorded here.

+

For the correspondence between index values and TLB table entries, refer to the relevant section in TLB Maintenance Instructions.

15:n

0

R

Read-only constant 0, writing to this field is ignored.

23:16

0

RO

Reserved field. +Return 0 if read this field and software is not allowed to change its value.

29:24

PS

RW

When executing the TLBRD instruction, the value read from the PS field of the TLB table entry is recorded here.

+

When executing the TLBWR and TLBFILL instructions with CSR.TLBRERA.IsTLBR=0, the value written to the PS field of the TLB table entry comes from here.

30

0

RO

Reserved field. +Return 0 if read this field and the software does not allow to change its value.

31

NE

RW

1 means the TLB table entry is empty (invalid TLB table entry), and 0 means the TLB table entry is non-empty (valid TLB table entry)

+

When executing the TLBSRCH instruction, this bit is recorded as 0 if there is a hit entry, otherwise it is recorded as 1.

+

When executing the TLBRD instruction, the E bit read from the TLB table entry is inverted and recorded here.

+

When executing the TLBWR instruction, and when CSR.TI.BRFPC.IsTT.BR=0, the value written to the E bit of the TLB entry is written after it is inverted. +If CSR.TLBRERA.IsTLBR=1, then the E bit of the TLB entry being written is always set to 1, regardless of the value of that bit.

+
+
+

7.5.2. TLB Entry High-order Bits (TLBEHI)

+
+

This register contains the information related to the virtual page number of the high-order bits of the TLB table entry during ececuting TLB-related instructions. +Since the length of the VPPN field contained in the high-order bits of the TLB table entry is related to the range of valid virtual addresses supported by the implementation, the definition of the relevant register field is expressed separately.

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 34. Definition of TLB entry high order bits register in LA64
BitsNameRead/WriteDescription

12:0

0

R

Read-only constant 0, writing to this field is ignored.

VALEN-1:13

VPPN

RW

When executing the TLBRD instruction, the value of the VPPN field read from the TLB table entry is recorded here.

+

If CSR.TLBRERA.IsTLBR=0, the VPPN value used to query TLB when executing TLBSRCH instruction and the value of VPPN field written to TLB table entry when executing TLBWR and TLBFILL instructions come from here.

+

When the page invalid exception for load operation, page invalid exception for store operation, page invalid exception for fetch operation, page modification exception, page non-readable exception, page non-executable exception, and page privilege level ilegal exception are triggered, the [VALEN-1:13] bits of the virual address that triggered the exception are recorded here.

63:VALEN

Sign_Ext

R

Return a signed extension value of the highest bits of the VPPN field if read this field and writing to this field is ignored.

+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + +
Table 35. Definition of TLB entry high order bits register in LA32
BitsNameRead/WriteDescription

12:0

0

R

Read-only constant 0, writing to this field is ignored.

31:13

VPPN

RW

When executing the TLBRD instruction, the value of the VPPN field read from the TLB table entry is recorded here.

+

If CSR.TLBRERA.IsTLBR=0, the VPPN value used to query TLB when executing TLBSRCH instruction and the value of VPPN field written to TLB table entry when executing TLBWR and TLBFILL instructions come from here.

+

When the page invalid exception for load operation, page invalid exception for store operation, page invalid exception for fetch operation, page modification exception, page non-readable exception, page non-executable exception, and page privilege level ilegal exception are triggered, the [31:13] bits of the virual address that triggered the exception are recorded here.

+
+
+

7.5.3. TLB Entry Low-order Bits (TLBELO0, TLBELO1)

+
+

TLBELO0 and TLBELO1 registers contain the information related to the physical page number of the low-order bits of the TLB table entry during executing TLB-related instructions. +Since TLB adopts a dual-page structure, the low-order bits of TLB table entry corresponds to the odd and even physical page table entries, where the even page information is in TLBELO0 and the odd page information is in TLBELO1. +TLBELO0 and TLBELO1 registers have exactly the same format definition, and the definition of each field is in the table.

+
+
+

When CSR.TLBRERA.IsTLBR=0, and when executing the TLBWR and TLBFILL instructions, and the written values of the G, PFN0, V0, PLV0, MATO, D0, NR0, NX0, RPLV0, PFN1, V1, PLV1, MATl, D1, NR1, NX1, and RPLV1 fields of the TLB table entry come from TLBELOO and TLBELO1 fields, respectively.

+
+
+

When executing the TLBRD instruction, the above information read from the TLB table entry is written to the corresponding fields in the TLBELO0 and TLBELO1 registers one by one.

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 36. Definition of TLB entry low order bits in LA64
BitsNameRead/WriteDescription

0

V

RW

Valid bit (V) of the page table entry.

1

D

RW

Dirty bit (D) of the page table entry.

3:2

PLV

RW

Privilege LeVel of the page table entry (PLV).

5:4

MAT

RW

Memory Access Type (MAT) of the page table entry.

6

G

RW

Global flag bit (G) of the page table entry.

+

When executing the TLBFILL and TLBWR instructions, the G bit in TLBELO0 and TLBELO1 is 1 only if both bits are 1.

+

The G bit of the page table entry filled into the TLB will be 1 only when the G bit in both TLBELO0 and TLBELO1 is 1.

+

When executing the TLBRD instruction, when the G bit of the TLB table entry read is 1, the G bits in TLBELO0 and TLBELO1 are set to 1 at the same time.

11:7

0

R

Read-only constant 0, writing to this field is ignored.

PALEN-1:12

PPN

RW

Physical Page Number (PPN) of the page table.

60:PALEN

0

R

Read-only constant 0, writing to this field is ignored.

61

NR

RW

Non-Readable bit (NR) of the page table entry.

62

NX

RW

Non-eXecutable bit (NX) of the page table entry.

63

RPLV

RW

Restricted Privilege LeVel enable (RPLV) of the page table. +When RPLV=0, the page table entry can be accessed by any program whose privilege level is not lower than PLV; when RPLV=1, the page table entry can only be accessed by programs whose privilege level is equal to PLV.

+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 37. Definition of TLB entry low order bits in LA32
BitsNameRead/WriteDescription

0

V

RW

Valid bit (V) of the page table entry.

1

D

RW

Dirty bit (D) of the page table entry.

3:2

PLV

RW

Privilege LeVel (PLV) of the page table entry.

5:4

MAT

RW

Memory Access Type (MAT) of the page table entry.

6

G

G

Global flag bit (G) of the page table entry.

+

When executing the TLBFILL and TLBWR instructions, the G bit in TLBELO0 and TLBELO1 is 1 only if both bits are 1.

+

The G bit of the page table entry filled into the TLB will be 1 only when the G bit in both TLBELO0 and TLBELO1 is 1.

+

When executing the TLBRD instruction, when the G bit of the TLB table entry read is 1, the G bits in TLBELO0 and TLBELO1 are set to 1 at the same time.

7

0

R

Read-only constant 0, writing to this field is ignored.

31:8

PPN

RW

Physical Page Number (PPN) of the page table.

+
+
+

7.5.4. Address Space Identifier (ASID)

+
+

This register contains the Address Space IDentifier (ASID) information for access operations and TLB-related instructions. +The length of the ASID may increase further as the architecture specification evolves, and this information is given directly to facilitate software to specify the length of the ASID.

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 38. Definition of address space identifier register
BitsNameRead/WriteDescription

9:0

ASID

RW

The address space identifier corresponding to the currently executing program.

+

It is used as the ASID key value information for querying the TLB when fetching instructions and executing the load/store instructions.

+

When executing the TLBSRCH, TLBCLR and INVTLB instructions, it is used as the ASID key value information for querying the TLB.

+

When executing the TLBWR or TLBFILL instructions, the value written to the ASID field of the TLB table entry is derived from this.

+

The contents of the ASID field read from the TLB table entry when executing the TLBRD instruction are recorded here.

15:0

0

R

Read-only constant 0, writing to this field is ignored.

23:16

ASIDBITS

R

The length of the ASID field. +It is directly equal to the value of this field.

31:24

0

R0

Reserved field. +Return 0 if read this field and software is not allowed to change its value.

+
+
+

7.5.5. Page Global Directory Base Address for Lower Half Address Space (PGDL)

+
+

This register is used to configure the base address of the global directory for the lower half address space. +It is required that the base address of the global directory must be aligned to a 4KB bound address.

+
+
+

This register also contains the information related to the PS and P fields in the TLB table entry when executing the TLB-related instructions.

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + +
Table 39. Definition of page global directory base address for lower half address space register
BitsNameRead/WriteDescription

11:0

0

R

Read-only constant 0, writing to this field is ignored.

GRLEN-1:12

Base

RW

The base address of the global directory in the lower half address space. +By lower half address space, it means that the [VALEN-1] bit of the virtual address is equal to 0.

+
+
+

7.5.6. Page Global Directory Base Address for Higher Half Address Space (PGDH)

+
+

This register is used to configure the base address of the global directory for the higher half address space. +The base address of the global directory must be aligned to the 4KB bound address, so the lowest 12 bits of this register are not configurable by software and are read-only constant 0.

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + +
Table 40. Definition of page global directory base address for higher half address space register
BitsNameRead/WriteDescription

11:0

0

R

Read-only constant 0, writing to this field is ignored.

GRLEN-1:12

Base

RW

The base address of the global directory in the high half address space. +By higher half address space, it means that the [VALEN-1] bit of the virtual address is equal to 1.

+
+
+

7.5.7. Page Global Directory Base Address (PGD)

+
+

This register is a read-only register, whose content is the global directory base address information corresponding to the bad virtual address in the current context.

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + +
Table 41. Definition of page global directory base address register
BitsNameRead/WriteDescription

11:0

0

R

Read-only constant 0, writing to this field is ignored.

GRLEN_1:12

Base

R

If the highest bit of the bad virtual address in the current context is 0, the return value of reading is equal to the Base field of CSR.PGDL; otherwise, the read return value is equal to the Base field of CSR.PGDH.

+

When CSR.TLBRERA.IsTLBR=0, the bad virtual address information in the current context is located in CSR.BADV; otherwise, the bad virtual address information is located in CSR.TLBRBADV.

+
+
+

7.5.8. Page Walk Controller for Lower Half Address Space (PWCL)

+
+

The information in this register and the CSR.PWCH register together define the page table structure used in the operating system. +This information will be used to instruct software or hardware to perform page table walking. +See Multi-level Page Table Structure Supported by page walking for an illustration of the page table structure and walking process.

+
+
+

PWCL is implemented in LA32 only, for which the PWCL register must contain all the information needed to describe the page table structure, resulting in the last page table and the lowest two levels of the directory starting at no more than 32 bits, a restriction that still exists in LA64.

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 42. Definition of page walk controller for lower half address space register
BitsNameRead/WriteDescription

4:0

PTbase

RW

The start address of the last page table.

9:5

PTwidth

RW

The number of index bits of the last level page table.

14:10

Dirl_base

RW

The starting address of the lowest level directory.

19:15

Dirl_width

RW

The number of index bits of the lowest level directory. +0 means there is no such level.

24:20

Dir2_base

RW

The starting address of the next lower level directory.

29:25

Dir2_width

RW

The number of index bits of the next lowest level directory. +0 means there is no such level.

31:30

PTEWidth

RW

The length of each page table entry in the memory. +0 - 64 bit; 1 - 128 bit; 2 - 192 bit; 3 - 256 bit.

+
+
+

7.5.9. Page Walk Controller for Higher Half Address Space (PWCH)

+
+

This register and the information in the CSR.PWCL register together define the page table structure used in the operating system. +This information will be used to instruct software or hardware to perform page table walking. +See Multi-level Page Table Structure Supported by page walking for an illustration of the page table structure and walking process.

+
+
+

This register is only defined in LA64.

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 43. Definition of page walk controller for higher half address space register
BitsNameRead/WriteDescription

5:0

Dir3_base

RW

The starting address of the next higher level directory.

11:6

Dir3_width

RW

The number of index bits of the next higher level directory. +0 means there is no such level.

17:12

Dir4_base

RW

The starting address of the highest level directory.

23:18

Dir4_width

RW

The number of index bits of the highest level directory. +0 means there is no such level.

31:24

0

R0

Reserved field. +Return 0 if read this field, and the software does not allow to change its value.

+
+
+

7.5.10. STLB Page Size (STLBPS)

+
+

This register is used to configure the size of the page in the STLB.

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + +
Table 44. Definition of STLB page size register
BitsNameRead/WriteDescription

5:0

PS

RW

The STLB is a power of 2 of the page size. +For example, if the page size is 16KB, then PS=0xE.

31:6

0

R0

Reserved field. +Return 0 if read this field and software is not allowed to change its value.

+
+
+

7.5.11. TLB Refill Exception Entry Base Address (TLBRENTRY)

+
+

This register is used to configure the entry base address of the TLB refill exception. +Since the processor core will enter direct address translation mode after the TLB refill exception is triggered, the entry base address filled here should be a physical address.

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 45. Definition of TLB refill exception entry base address register in LA64
BitsNameRead/WriteDescription

11:0

0

R

Read-only constant 0, writing to this field is ignored.

PALEN-1:12

PPN

RW

The [PALEN-1:12] bits of the entry base address of the TLB refill exception entry base address. +The address filled in here by the system software should be the physical address.

63:PALEN

0

R

Read-only constant 0, writing to this field is ignored.

+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + +
Table 46. Definition of TLB refill exception entry base address register in LA32
BitsNameRead/WriteDescription

11:0

0

R

Read-only constant 0, writing to this field is ignored.

31:12

PPN

RW

The [31:12] bits of the entry base address of the TLB refill exception entry base address. +The address filled in here by the system software should be the physical address.

+
+
+

7.5.12. TLB Refill Exception Bad Virtual Address (TLBRBADV)

+
+

This register is used to record the bad virtual address that triggered the TLB refill exception.

+
+ + ++++++ + + + + + + + + + + + + + + + + +
Table 47. Definition of TLB refill exception bad virtual address register
BitsNameRead/WriteDescription

GRLEN-1:0

VAddr

RW

When the TLB refill exception is triggered, the hardware records the bad virtual address here. +For LA64, in this case, if the privilege level that triggered the exception is in 32-bit address mode, then the high 32 bits of the recorded virtual address will be set to 0.

+
+
+

7.5.13. TLB Refill Exception Return Address (TLBRERA)

+
+

This register is used to record the PC of the instruction that triggered the TLB refill exception. +In addition, this register contains flag bits to identify the current exception as a TLB refill exception.

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 48. Definition of TLB refill exception program counter register
BitsNameRead/WriteDescription

0

IsTLBR

RW

+

1 indicates that it is currently in the context of TLB refill exception processing.

+
+
+

The hardware sets this bit to 1 when a TLB refill exception is triggered.

+
+
+

When this bit is 1, execution of the ERTN instruction will clear it to 0 only if CSR.MERRCTL.IsMERR=0, otherwise it remains unchanged.

+
+
+

Because the architecture defines a separate set of CSRs for TLB refill exceptions, when this bit is 1.

+
+
+
    +
  • +

    When ERTN returns, the information used to recover CSR.CRMD will come from CSR.TLBRPRMD;

    +
    • +
  • +

    ERTN return address will come from CSR.TLBRERA;

    +
    • +
  • +

    The table entries to be written by TLBWR and TLBFILL instructions will come from CSR.TLBREHI, CSR.TLBELO0 and CSR.TLBELO1;

    +
    • +
  • +

    TLBSRCH instruction queries information from CSR.TLBREHI;

    +
    • +
  • +

    The bad virtual address required for LDDIR and LDPTE instruction execution will come from CSR.TLBRBADV.

    +
    • +
+

1

0

R

Read-only constant 0, writing to this field is ignored.

GRLEN-1:2

PC

RW

Record the [GRLEN-1:2] bits of the PC of the instruction that triggered the TLB refill exception. +When the execution of ERTN instruction returns from the TLB refill exception handler (at this time, this register IsTLBR=1 and CSR.MERRCTL.IsMERR=0).

+
+
+

7.5.14. TLB Refill Exception Data Save Register (TLBRSAVE)

+
+

This register is used to store data temporarily for the system software. +Each dava save register can hold the data of one general-purpose register.

+
+
+

The reason for the additional SAVE register for TLB refill exception processing is to address the case where a TLB refill exception is triggered during the processing of exceptions except the TLB refill exception.

+
+ + ++++++ + + + + + + + + + + + + + + + + +
Table 49. Definition of TLB refill exception data save register
BitsNameRead/WriteDescription

GRLEN-1:0

Data

RW

Data for software to read and write only. +The hardware does not modify the contents of this field except for the execution of CSR instructions.

+
+
+

7.5.15. TLB Refill Exception Entry Low-order Bits (TLBRELO0, TLBRELO1)

+
+

The TLBRELO0/TLBRELO1 registers are used to store the information related to the physical page number of the low-order bits of the TLB table entry during executing the TLB-related instructions (when the TLB refill exception context CSR.TLBRERA.IsTLBR=1). +The format of TLBRELO0/TLBRELO1 registers and the meaning of each field are the same as TLBELO0/TLBELO1 registers.

+
+
+

However, the TLBRELO0/TLBRELO1 registers are not an exact copy of the TLBELO0/TLBELO1 registers in the case of CSR.TLBRERA.IsTLBR=1. +This is reflected in two points:

+
+
+
    +
  • +

    Regardless of the value of CSR.TLBRERA.IsTLBR, the TLBRD instruction updates only the TLBELO0/TLBELO1 registers.

    +
    • +
  • +

    Regardless of the value of CSR.TLBRERA.IsTLBR, the LDPTE instruction updates only the TLBRELO0/TLBRELO1 registers.

    +
    • +
+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 50. Definition of TLB refill exception entry low order bits register in LA64
BitsNameRead/WriteDescription

0

V

RW

Valid bit (V) of the page table entry.

1

D

RW

Dirty bit (D) of the page table entry.

3:2

PLV

RW

Privilege LeVel (PLV) of the page table entry.

5:4

MAT

RW

Memory Access Type (MAT) of the page table entry.

6

G

RW

Global flag bit (G) of the page table entry.

+

When executing the TLBFILL and TLBWR instructions, the G bit of the page table entry filled into the TLB is 1 only when the G bit in both TLBELO0 and TLBELO1 is 1.

11:7

0

R

Read-only constant 0, writing to this field is ignored.

PALEN-1:12

PPN

RW

Physical Page Number (PPN) of the page table.

60:PALEN

0

R

Read-only constant 0, writing to this field is ignored.

61

NR

RW

Non-Readable bit (NR) of the page table entry.

62

NX

RW

Non-eXecutable bit (NX) of the page table entry.

63

RPLV

RW

Restricted Privilege LeVel enable (RPLV) for the page table. +When RPLV=0, the page table entry can be accessed by any program whose privilege level is not lower than PLV; when RPLV=1, the page table entry can only be accessed by programs whose privilege level is equal to PLV.

+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 51. Definition of tlb refill exception entry low order bits register in LA32
BitsNameRead/WriteDescription

0

V

RW

Valid bit (V) of the page table entry.

1

D

RW

Dirty bit (D) of the page table entry.

3:2

PLV

RW

Privilege LeVel of the page table entry (PLV).

5:4

MAT

RW

Memory Access Type (MAT) of the page table entry.

6

G

RW

Global flag bit (G) of the page table entry. +When executing TLBFILL and TLBWR instructions, the G bit of the page table entry filled into the TLB is 1 only when the G bits in both TLBELO0 and TLBELO1 are 1.

11:7

0

R

Read-only constant 0, writing to this field is ignored.

31:12

PPN

RW

Physical Page Number (PPN) of the page table.

+
+
+

7.5.16. TLB Refill Exception Entry High-order Bits (TLBREHI)

+
+

When in the TLB refill exception context (CSR.TLBRERA.IsTLBR=1), the TLBREHI register stores the information related to the physical page number of the low-order bits of the TLB table entry during executing TLB-related instructions, etc. +The format of the TLBREHI register and the meaning of each field are the same as the TLBEHI register.

+
+
+

However, the TLBREHI register is not an exact replica of the TLBEHI register in the case of CSR.TLBRERA.IsTLBR=1. +This is reflected in:

+
+
+
    +
  • +

    Regardless of the value of CSR.TLBRERA.IsTLBR equals, the execution of the TLBRD instruction updates only the TLBEHI register.

    +
    • +
+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 52. Definition of TLB refill exception entry high order bits register in LA64
BitsNameRead/WriteDescription

5:0

PS

RW

Page size specified by TLB refill exception. +That is, when CSR.TLBRERA.IsTLBR=1, when executing TLBWR and TLBFILL instructions and the value of the PS field of the written TLB table entry comes from this.

12:0

0

R

The read-only constant is 0, and writes are ignored.

VALEN-1:13

VPPN

RW

When CSR.TLBRERA.IsTLBR=1, the value of VPPN used for querying TLB when executing TLBSRCH instruction, and the value of VPPN field of TLB table entry written when executing TLBWR and TLBFILL instructions come from here. +When a TLB refill exception is triggered, the [VALEN-1:13] bits of the virtual address that triggered the exception are recorded here.

63:VALEN

Sign_Ext

R

The return value read from these bits is a signed extension of the highest bits of the VPPN field; writing to these bits is ignored.

+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + +
Table 53. Definition of tlb refill exception entry high order bits register in LA32
BitsNameRead/WriteDescription

12:0

0

R

Read-only is constant to 0, and writes are ignored.

31:13

VPPN

RW

With CSR.TLBRERA.ISTLBR=1, the VPPN value used to query the TLB when executing the TLBSRCH instruction, and the value of the VPPN field written to the TLB table entry when executing the TLBWR and TLBFILL instructions come from here. +When a TLB refill exception is triggered, the [31:13] bits of the virtual address that triggered the exception are recorded here.

+
+
+

7.5.17. TLB Refill Exception Pre-exception Mode Information (TLBRPRMD)

+
+

When a TLB refill exception is triggered, the hardware saves the processor core’s privilege level, Guest mode, global interrupt enable bit, and watchpoint enable bit into this register at that time, which is used to restore the processor core to the field when the exception returns.

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 54. Definition of TLB refill exception pre-exception mode information register
BitsNameRead/WriteDescription

1:0

PPLV

RW

When the TLB refill exception is triggered, the hardware records the old value of the PLV field in CSR.CRMD in this field. +When CSR.TLBRERAIsTLBR=1, the hardware restores the value of this field to the PLV field of CSR.CRMD when the ERTN instruction is executed to return from the exception handler.

2

PIE

RW

When the TLB refill exception is triggered, the hardware records the old value of the IE field in the CSR.CRMD in this field. +When CSR.TLBRERAIsTLBR=1, the hardware restores the value of this field to the IE field of CSR.CRMD when the ERTN instruction is executed to return from the exception handler.

3

0

R

If the virtualization extension is not implemented, this bit is read-only constant to 0 and writes are ignored.

4

PWE

RW

When the TLB refill exception is triggered, the hardware records the old value of the WE field in the CSR.CRMD in this field. +When CSR.TLBRERAIsTLBR=1, the hardware restores the value of this field to the WE field of CSR.CRMD when the ERTN instruction is executed to return from the exception handler.

31:5

0

R0

Reserved field. +Return 0 if read this field, and software is not allowed to change its value.

+
+
+

7.5.18. Direct Mapping Configuration Window n (DMW0-DMW3)

+
+

This -group sender is involved in completing the direct mapping address translation mode. +See Direct Mapped Address Translation Mode for more information about this address translation mode.

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 55. Definition of direct mapping configuration window n register in LA64
BitsNameRead/WriteDescription

0

PLV0

RW

1 indicates that the configuration of this window can be used for direct mapping address translation at the PLV0 privilege level.

1

PLV1

RW

1 indicates that the configuration of this window can be used for direct mapping address translation at the PLV1 privilege level.

2

PLV2

RW

1 indicates that the configuration of this window can be used for direct map address translation at the PLV2 privilege level.

3

PLV3

RW

1 indicates that the configuration of this window can be used for direct mapping address translation at the PLV3 privilege level.

5:4

MAT

RW

The virtual address falls under the memory access type of the access operation in this mapping window.

59:6

0

R0

Reserved field. +Return 0 if read this field and software is not allowed to change its value.

63:60

VSEG

RW

The [63:60] bits of the virtual address of the direct mapping window.

+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 56. Definition of direct mapping configuration window n register in LA32
BitsNameRead/WriteDescription

0

PLV0

RW

1 indicates that the configuration of this window can be used for direct mapping address translation at the PLV0 privilege level.

1

PLV1

RW

1 indicates that the configuration of this window can be used for direct mapping address translation at the PLV1 privilege level.

2

PLV2

RW

1 indicates that the configuration of this window can be used for direct map address translation at the PLV2 privilege level.

3

PLV3

RW

1 indicates that the configuration of this window can be used for direct mapping address translation at the PLV3 privilege level.

5:4

MAT

RW

The virtual address falls under the memory access type of the access operation in this mapping window.

24:6

0

R0

Reserved field. +Return 0 if read this field and software is not allowed to change its value.

27:25

PSEG

RW

The [31:29] bits of the physical address of the direct mapping window.

28

0

R0

Reserved field. +Return 0 if read this field and software is not allowed to change its value.

31:29

VSEG

RW

The [31:29] bits of the virtual address of the direct mapping window.

+
+
+
+ +
+

7.6.1. Timer Identity (TID)

+
+

Each timer in the processor has a unique identifiable number, which is configured by the software in this register. +Each timer also uniquely corresponds to a timer, and when the software reads the timer value using the RDTIME instruction, the timer ID number that is returned along with it is the corresponding timer number.

+
+ + ++++++ + + + + + + + + + + + + + + + + +
Table 57. Definition of timer identity register
BitsNameRead/WriteDescription

31:0

TID

RW

Timer number. +It can be configured via software. +During a processor core reset, the hardware can reset it to the same value as the CoreID in CSR.CPUID.

+
+
+

7.6.2. Timer Configuration (TCFG)

+
+

This register is the interface to the software configuration timer. +The number of valid bits of the timer is determined by the implementation, so the length of the TimeVal field in this register will change accordingly.

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 58. Definition of timer configuration register
BitsNameRead/WriteDescription

0

En

RW

Timer enable bit. +Only when this bit is 1, the timer will perform countdown self decrement and set up the timing interrupt signal when it decrements to 0 value.

1

Periodic

RW

Timer cycle mode control bit. +If this bit is 1, when the timer decreases to 0, the timer will set up the timer interrupt signal and reload the timer to the initial value configured in the TimeVal field, and then continue to decrement itself in the next clock cycle. +If this bit is 0, the timer will stop counting until the software configures the timer again when the countdown reaches 0.

n-1:2

InitVal

RW

The initial value of the timer countdown self decrement count. +This initial value must be an integer multiple of 4. +The hardware will automatically fill in the lowest bit of the field value. +Two bits of 0 are added before it is used.

GRLEN-1:n

0

R

Read-only constant 0, writing to this field is ignored.

+
+
+

7.6.3. Timer Value (TVAL)

+
+

The software can read this register to know the current count value of the timer. +The number of valid bits of the timer is determined by the implementation, so the length of the TimeVal field in this register will also change.

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + +
Table 59. Definition of timer value register
BitsNameRead/WriteDescription

n-1:0

TimeVal

R

The count value of the current timer.

GRLEN-1:n

0

R

Read-only constant 0, writing to this field is ignored.

+
+
+

7.6.4. Counter Compensation (CNTC)

+
+

This register can be configured by the software to correct the timer’s readout value. +The final readout value will be the original timer count value plus the timer compensation value. +It is important to note that configuring this register does not directly change the timer’s count value.

+
+
+

In LA32, this register is 32-bit and its value will be sign extended to 64 bits and then added to the original counter value.

+
+ + ++++++ + + + + + + + + + + + + + + + + +
Table 60. Definition of counter compensation register
BitsNameRead/WriteDescription

GRLEN-1:0

Compenstaion

RW

Software-configurable counter compensation values.

+
+
+

7.6.5. Timer Interrupt Clearing (TICLR)

+
+

The software clears the timed interrupt signal set by the timer by writing 1 to bit 0 of this register.

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + +
Table 61. Definition of timer interrupt clearing register
BitsNameRead/WriteDescription

0

CLR

W1

When 1 is written to this bit, the clock interrupt flag is cleared. +The value read from this register is always 0.

31:1

0

R0

Reserved field. +Return 0 if read this field and software is not allowed to change its value.

+
+
+
+ +
+

7.7.1. Machine Error Controller (MERRCTL)

+
+

Since the timing of machine error exceptions cannot be predicted and controlled by the software, a separate set of CSRs is defined for machine error exceptions in order not to destroy any other site when triggering machine error exceptions, which is used by the system software to save and restore other sites. +This set of independent CSRs except MERRERA and MERRSAVE, the rest are concentrated in MERRCTL register.

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 62. Definition of machine error controller register
BitsNameRead/WriteDescription

0

IsMERR

R

1 indicates that it is currently in the context of machine error exception processing. +The hardware sets this bit to 1 when a machine error exception is triggered.

+

When this bit is 1, execution of the ERTN instruction will clear it to 0.

+

Because the architecture defines a separate set of CSRs for machine error exceptions, when this bit is 1,

+

* when ERTN returns, information used to restore the CSRs will come from PPLV, PLV and so on of this field;

+

* when ERTN returns, address information will come from CSR.MERRERA.

1

Repairable

RW

1 means that the hardware can automatically fix machine errors that occur, so the exception handler can return directly without any processing.

3:2

PPLV

RW

When a machine error exception is triggered, the hardware records the old value of the PLV field in CSR.CRMD in this field.

+

When the IsMERR of this register is 1, the hardware returns from the exception handler by executing the ERTN instruction. +The hardware restores the value of this field to the PLV field of CSR.CRMD.

4

PIE

R

When a machine error exception is triggered, the hardware records the old value of the IE field in CSR.CRMD in this field.

+

When IsMERR of this register is 1, the hardware restores the value of this field to the IE field of CSR.CRMD when the ERTN instruction is executed to return from the exception handler.

5

0

RW

If the virtualization expansion is not implemented, this field is read-only constant 0 and writing to this field is ignored.

6

PWE

RW

When a machine error exception is triggered, the hardware records the old value of the WE field in CSR.CRMD in this field.

+

When IsMERR of this register is 1, the hardware restores the value of this field to the WE field in CSR.CRMD when the ERTN instruction is executed to return from the exception handler.

7

PDA

RW

When a machine error exception is triggered, the hardware records the old value of the DA field in the CSR.CRMD in this field.

+

When IsMERR of this register is 1, the hardware restores the value of this field to the DA field of CSR.CRMD when the ERTN instruction is executed to return from the exception handler.

8

PPG

RW

When a machine error exception is triggered, the hardware records the old value of the PG field in the CSR.CRMD in this field.

+

When IsMERR of this register is 1, the hardware restores the value of this field to the PG field of CSR.CRMD when the ERTN instruction is executed to return from the exception handler.

10:9

PDATF

RW

When a machine error exception is triggered, the hardware records the old value of the DATF field in the CSR.CRMD in this field.

+

When IsMERR of this register is 1, the hardware restores the value of this field to the DATF field of CSR.CRMD when the ERTN instruction is executed to return from the exception handler.

12:11

PDATM

RW

When a machine error exception is triggered, the hardware records the old value of the DATM field in the CSR.CRMD in this field.

+

When IsMERR of this register is 1, the hardware restores the value of this field to the DATM field of CSR.CRMD when the ERTN instruction is executed to return from the exception handler.

15:13

0

R0

Reserved field. +Return 0 if read this field and software must write 0, or mask out this field by csr mask write.

23:16

Cause

R

Machine error type code. +Currently only the 0x1 value is defined for Cache checksum errors.

+

The rest of the encoded values are reserved.

31:24

0

R0

Reserved field. +Return 0 if read this field and software is not allowed to change its value.

+
+
+

7.7.2. Machine Error Information (MERRINFO1, MERRINFO2)

+
+

When a machine error exception is triggered, the hardware will store more information related to that error into these two registers for system software diagnostic purposes. +The format and the meaning of each field are defined by the implementation.

+
+
+
+

7.7.3. Machine Error Exception Entry Base Address (MERRENTRY)

+
+

This register is used to configure the entry base address of the machine error exception. +Since the processor core will enter the direct address translation mode after the machine error exception is triggered, the entry base address filled here should be the physical address.

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 63. Definition of machine error exception entry base address register in LA64
BitsNameRead/WriteDescription

11:0

0

R

Read-only constant 0, writing to this field is ignored.

PALEN-1:12

PPN

RW

The [PALEN-1:12] bits of the entry base address of the machine error exception. +The address filled in here by the system software should be the physical address.

63:PALEN

0

R

Read-only constant 0, writing to this field is ignored.

+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + +
Table 64. Definition of machine error exception entry base address register in LA32
BitsNameRead/WriteDescription

11:0

0

R

Read-only constant 0, writing to this field is ignored.

31:12

PPN

RW

The [31:12] bits of the entry base address of the machine error exception. +The address entered here by the system software should be a physical address.

+
+
+

7.7.4. Machine Error Exception Return Address (MERRERA)

+
+

This register is used to record the PC of the instruction that triggered the machine error exception.

+
+ + ++++++ + + + + + + + + + + + + + + + + +
Table 65. Definition of machine error exception return address register
BitsNameRead/WriteDescription

GRLEN-1:0

PC

RW

The PC of the instruction that triggered the machine error exception is recorded. +The value stored here is used as the return address when the ERTN instruction is executed to return from the machine error exception handler (when CSR.MERRCTL.IsMERR=1).

+
+
+

7.7.5. Machine Error Exception Data Save Register (MERRSAVE)

+
+

This register is used to store data temporarily for the system software. +Each dava save register can hold the data of one general-purpose register.

+
+
+

The reason for the additional SAVE register for the machine error exception handler is that the timing of the machine error exception cannot be predicted and controlled by the software, and it may occur during the processing of any other exception.

+
+ + ++++++ + + + + + + + + + + + + + + + + +
Table 66. Definition of machine error exception data save register
BitsNameRead/WriteDescription

GRLEN-1:0

DATA

RW

Data for software to read and write only. +The hardware will not modify the contents of this field except for the execution of CSR instructions.

+
+
+
+ +
+

LoongArch defines a hardware performance monitoring mechanism to support software performance analysis. +The main body of this mechanism is a series of performance monitors. +At least one performance monitor is implemented, and up to 32 monitors are implemented, the number is determined by the implementation. +The software can determine how many performance monitors are available by reading the CPUCFG.6.PMNUM[bit7:4].

+
+
+

Each performance monitor contains two CSRs: a Performance Monitoring ConFiGuration register (PMCFG) and a Performance Monitoring CouNTer register (PMCNT).

+
+
+

All CSRs related to performance monitoring are alternately addressed starting at address 0x200, with the nth performance monitoring configuration register at address 0x200+n, and the nth performance monitoring counter at address 0x201+n. +The format of all performance monitoring configuration registers is the same, as described in Performance Monitor Configuration n (PMCFG); the format of all performance monitoring counters is the same, as described in Performance Monitor Overall Counter n (PMCNT).

+
+
+

7.8.1. Performance Monitor Configuration n (PMCFG)

+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 67. Definition of performance monitor configuration n register
BitsNameRead/WriteDescription

9:0

EvCode

RW

The event number of the performance event being monitored. +The definition of event numbers is divided into two parts, a part whose meaning is specified in the architecture specification and must be implemented by all processors compatible with this architecture, and a remaining part whose meaning is implementation specific and is defined by the processor’s implementer.

15:10

0

R0

Reserved fields. +Return 0 if read this field, and software is not allowed to change its value.

16

PLV0

RW

PLV0 privilege level enables counting for this performance monitor. +1 - count, 0 - stop.

17

PLV1

RW

PLV1 privilege level enables counting for this performance monitor. +1 - count, 0 - stop.

18

PLV2

RW

PLV2 privilege level enables counting for this performance monitor. +1 - count, 0 - stop.

19

PLV3

RW

Count enable for this performance monitor at the PLV3 privilege level. +1 - count, 0 - stop.

20

PMIEn

RW

Performance monitoring count overflow interrupt enable bit for this performance monitor. +1 - enable, 0 - disable.

22:21

0

R

If the virtualization expansion is not implemented, this field is read-only constant 0 and writing to this field is ignored.

31:23

0

R0

Reserved field. +Return 0 if read this field and software is not allowed to change its value.

+
+
+

7.8.2. Performance Monitor Overall Counter n (PMCNT)

+ + ++++++ + + + + + + + + + + + + + + + + +
Table 68. Definition of performance monitor overall counter n register
BitsNameRead/WriteDescription

GRLEN-1:0

Count

RW

The counter is incremented by 1 for each performance event monitored by the performance monitor.

+

If the performance monitor has enabled the performance monitoring count overflow interrupt, and when the highest bit of Count is 1, the interrupt is triggered. +This also means that the software can cancel the interrupt by clearing the highest bit of Count to 0.

+
+
+
+ +
+

LoongArch defines hardware watchpoint functions for fetch and load/store operations. +After the software configures the watchpoints for fetch and load/store, the processor hardware will monitor the access addresses of the fetch and load/store operations and trigger a watchpoint exception when the watchpoint setting conditions are met.

+
+
+

The control and status registers associated with the watchpoints are used as interfaces for software to configure the watchpoints for fetch and load/store operations. +Load/store watchpoints and fetch watchpoints each have a similar layout of control and status registers, a register for the overall configuration of all watchpoints, a register for the status of all watchpoints, and the four registers. +The address of the overall configuration register of the load/store watchpoint is 0x300, the address of the overall status register of the load/store watchpoint is 0x301, and the addresses of the four configuration registers from 1 to 4 of the nth load/store watchpoint are 0x310+8n, 0x311+8n, 0x312+8n, and 0x313+8n, respectively. +The address of the overall configuration register of the fetch instruction watchpoint is 0x380, the address of the overall status register of the fetch instruction watchpoint is 0x381, and the addresses of the four configuration registers 1-4 of the nth fetch instruction watchpoint are 0x390+8n, 0x391+8n, 0x392+8n, 0x393+8n in order.

+
+
+

The maximum number of load/store watchpoints and fetch instruction watchpoints is 14 each, and the actual number is determined by the implementation. +The software can determine how many hardware watchpoints can be used by reading the values of CSR.MWPC.Num and CSR.FWPC.Num.

+
+
+

7.9.1. Memory Load/Store Watchpoint Overall Controller (MWPC)

+
+

This register contains configuration information to inform the software of the exact number of load/store watchpoints.

+
+
+

It is important to note that the global enable control signal for all watchpoints is in the WE bit of CSR.CRMD.

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 69. Definition of memory load/store watchpoint overall controller register
BitsNameRead/WriteDescription

5:0

Num

R

The number of load/store watchpoints.

19:16

0

R

If no virtualization extension is implemented, the field is read-only constant to 0 and writes are ignored.

31:20

0

R0

Reserved field. +Reads return 0 and the software does not allow to change its value.

+
+
+

7.9.2. Memory Load/Store Watchpoint Overall Status (MWPS)

+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 70. Definition of memory load/store watchpoint overall status register
BitsNameRead/WriteDescription

n-1:0

Status

RW1[5]

The hit status of the load/store watchpoint. +It corresponds to the watchpoint one by one, and bit i corresponds to watchpoint i.

+

When an address with a load/store operation hits a watchpoint, the corresponding bit is set to 1. +The hardware does not clear the bits in this field except during a reset.

+

The software can only clear them by writing 1, writing 0 is ignored.

15:n

0

R

Read-only constant 0, writing to this field is ignored.

16

Skip

RW

The software notifies the hardware to ignore the next load/store watchpoint hit by setting this location to 1. +By ignoring, it means that neither the corresponding bit in the Stauts field of this register is set to 1 nor the watchpoint exception is triggered. +This function can avoid endlessly triggering the same watchpoint repeatedly without canceling it, thus simplifying the handling of watchpoint exceptions.

+

When the Skip bit is 1, if the hardware encounters a loadjstore hit, it will ignore the hit and clear the Skip bit to 0. +This means that each time the software sets the Skip bit to 1, the hardware will ignore at most one hit. +This feature also causes the software to write 1 to this bit and then read out the value which may not be 1.

+

This Skip bit corresponds to all load/store watchpoints. +If the software modifies the configuration of the breakpoint and replaces it, do not set this bit, or even write 0 to clear it for safety reasons.

31:17

0

R

Read-only constant 0, writing to this field is ignored.

+
+
+

7.9.3. Memory Load/Store Watchpoint n Configuration (MWPnCFG1-MWPnCFG4)

+
+

The information contained in the configuration 1 to 3 registers of each load/store watchpoint is used directly for the comparison judgment of the watchpoint check. +Assuming that the address of the operation to be compared is maddr and the byte range is mbyten, the process of determining the hit of each watchpoint is as follows:

+
+
+
    +
  1. +

    If CSR.CRMD.WE=0, the judgment is terminated, otherwise turn 2;

    +
    2. +
  2. +

    If the current is not in debug mode but the DMOnly bit of MWPCFG3 is equal to 1, the judgment is terminated, otherwise turn to 3;

    +
    3. +
  3. +

    If the bit corresponding to the current privilege level in PLV0-PLV3 of MWPCFG3 is equal to 0, the judgment is terminated, otherwise turn to 4;

    +
    4. +
  4. +

    If the operation is a load operation but the LoadEn bit in MWPCFG3 is equal to 0, or the operation is a store operation but the StoreEn bit in MWPCFG3 is equal to 0, the judgment is terminated, otherwise go to 5;

    +
    5. +
  5. +

    If the LCL bit in MWPCFG3 is equal to 1, but the CSR.ASID.ASID is not equal to the ASID in MWPCFG4, the judgment is terminated, otherwise go to 6;

    +
    6. +
  6. +

    If (maddr & (~MWPCFG2.Mask)) != (MWPCFG1.VAaddr & (~MWPCFG2.Mak)), that is, the address comparison is not equal, the judgment terminates, otherwise turn 7;

    +
    7. +
  7. +

    If (~bytemask[7:0] & mbyten[7:0]) is equal to all 0 values, the judgment is terminated, otherwise the watchpoint is considered to be hit.

    +
    8. +
+
+
+

The concepts of mbyten and bytemask, which appear in the description of the judgment process above, are explained further below.

+
+
+

mbyten represents the bytes involved in the operation, which is an 8-bit bit vector whose value is related to the type of load/store operation and the low value of the address, as defined in the table:

+
+ + +++++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 71. Definition of load/store watchpoint judgment process mbyten
Intsruction Namemaddr[2:0]

0

1

2

3

4

5

6

7

LD[X].B[U], ST[X].B,

+

LD{GT/LE}.B, ST{GT/LE}.B

0x01

0x02

0x04

0x08

0x10

0x20

0x40

0x80

LD[X].H[U], ST[X].H

+

LD{GT/LE}.H, ST{GT/LE}.H

0x30

0x0C

0x30

0xC0

LD[X].W[U], ST[X].W,

+

LD{GT/LE}.W, ST{GT/LE}.W,

+

LDPTR.W, STPTR.W,

+

LL.W, SC.W,

+

AM{SWAP/ADD/AND/OR/XOR/MAX/MIN}[.DB].W,

+

AM{MAX/MIN}[_DBI].WU,

+

FLD[X].S, FST[X]S,

+

FLD{GT/LE}.S, FST{GT/LE}.S

0x0F

0xF0

LD[X].D, ST[X].D,

+

LD{GT/LE}.D, ST[GT/LE].D,

+

LDPTR.D, STPTR.D,

+

LL.D, SC.D,

+

AM{SWAP/ADD/AND/OR/XOR/MAX/MIN}[_DB].D,

+

AM{MAX/MIN}[_DB].DU,

+

FLD[X].D, FST[X].D,

+

FLD{GT/LE}.D, FST{GT/LE}.D

0xFF

+
+

bytemask indicates which bytes do not participate in the comparison mask when watchpoint comparison, which is an 8-bit bit vector whose value is related to the low bit of VAddr in MWPCFG1 and Size in MWPCF`G3, as defined as shown.

+
+ + +++++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 72. Definition of load store watchpoint bytemask
MWPCFG3.SizeMWPCFG1.Vaddr[2:0]

0

1

2

3

4

5

6

7

0b00

0x00

0b01

0xF0

0x0F

0b10

0xFC

0xF3

0xCF

0x3F

0b11

0xFE

0xFD

0xFB

0xF7

0xEF

0xDF

0xBF

0x7F

+ + ++++++ + + + + + + + + + + + + + + + + +
Table 73. Definition of memory load/store watchpoint n configuration 1 register
BitsNameRead/WriteDescription

GRLEN-1:0

VAddr

RW

The virtual address to be compared for this load/store watchpoint.

+ + ++++++ + + + + + + + + + + + + + + + + +
Table 74. Definition of memory load/store watchpoint n configuration 2 register
BitsNameRead/WriteDescription

GRLEN-1:0

Mask

RW

Mask bit for address comparison for this load/store watchpoint. +If bit i (0 ≤ i < GRLEN) is 1, it means that bit i of the address is not involved in the comparison.

+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 75. Definition of memory load/store watchpoint n configuration 3 register
BitsNameRead/WriteDescription

0

DMOnly

RW

A bit of 1 indicates that the load/store watchpoint is only available in debug mode. +Here “available” contains two meanings: first, the configuration register of the watchpoint can be modified by software in this mode, and second, the check hit of the watchpoint will trigger the watchpoint exception and mark the status of the watchpoint only in this mode.

+

This bit can only be modified in debug mode (CSR.DBG.DM=1). +This means that the (Host) software running in debug mode has the priority to use the watchpoint.

1

PLV0

RW

This watchpoint triggers the enable of the watchpoint exception at the PLV0 privilege level. +1 - enable, 0 - disable.

2

PLV1

RW

The watchpoint triggers the watchpoint exception enable at the PLV1 privilege level. +1 - enable, 0 - disable.

3

PLV2

RW

The watchpoint triggers the enable of the watchpoint exception at the PLV2 privilege level. +1 - enable, 0 - disable.

4

PLV3

RW

The watchpoint triggers the enablement of the watchpoint exception at the PLV3 privilege level. +1 - enable, 0 - disable.

6:5

0

R

If virtualization extensions are not implemented, the field is read-only constant at 0 and writes are ignored.

7

LCL

RW

1 indicates that the ASID comparison is performed during the watchpoint check

8

LoadEn

RW

1 indicates a watchpoint check for load operations, otherwise no check.

9

StoreEn

RW

1 means that a watchpoint check is performed for the store operation, otherwise, no check is performed.

11:10

Size

RW

Which bytes fall within the comparison range when the watchpoint check is performed.

31:12

0

R0

Reserved field. +Return 0 if read this field, and the software does not allow to change its value.

+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 76. Definition of memory load/store watchpoint n configuration 4 register
BitsNameRead/WriteDescription

9:0

ASID

RW

The ASID being compared

15:10

0

R

Read-only is always 0, writes are ignored.

23:16

0

R

If the virtualization extension is not implemented, the field is read-only constant to 0 and writes are ignored.

31:24

0

R

Read-only constant 0, writing to this field is ignored.

+
+
+

7.9.4. Fetch Watchpoint Overall Controller (FWPC)

+
+

This register contains configuration information to inform the software of the exact number of watchpoints to be fetched.

+
+
+

It is important to note that the global enable control signal for all watchpoints is in the WE bit of the CSR.CRMD.

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 77. Definition of fetch watchpoint overall controller register
BitsNameRead/WriteDescription

5:0

Num

R

the number of fetch watchpoints.

19:16

0

R

If the virtualization extension is not implemented, the field is read-only constant 0, and writing to this field is ignored.

31:20

0

R0

Reserved field. +Reads return 0 and the software does not allow to change its value.

+
+
+

7.9.5. Fetch Watchpoint Overall Status (FWPS)

+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 78. Definition of fetch watchpoint overall status register
BitsNameRead/WriteDescription

n-1:0

Status

RW1[6]

The hit status of the surveillance point. +It corresponds to the watchpoint one by one, with bit i corresponding to watchpoint i.

+

When a PC with a fetch instruction hits a watchpoint, its corresponding bit is set to 1, the hardware does not clear the bits in this field except during reset.

+

The software can only clear them by writing 1, writing 0 is ignored.

15:n .

0

R

Read-only constant 0, writing to this field is ignored.

16

Skip

RW

The software notifies the hardware to ignore the next fetch point hit result by setting this location to 1. +By ignore, it means that neither the corresponding bit in the Stauts field of this register is set to 1 nor the watchpoint exception is triggered. +This function can avoid endlessly triggering the same watchpoint repeatedly without canceling it, thus simplifying the handling of watchpoint exceptions.

+

When the Skip bit is 1, if the hardware encounters a hit on a fetch point, it will ignore the hit and clear the Skip bit to 0. +This means that each time the software sets the Skip bit to 1, the hardware will ignore at most one hit on the point. +This feature also causes the software to write 1 to this bit and then read out the value which may not be 1.

+

This Skip bit corresponds to all fetch watchpoints. +If the software modifies the configuration of the breakpoint and replaces it, do not set this bit, or even write 0 to clear it for safety reasons.

31:17

0

R

Read-only constant 0, writing to this field is ignored.

+
+
+

7.9.6. Fetch Watchpoint n Configuration (FWPnCFG1-FWPnCFG3)

+
+

The information contained in the configuration 1 to 3 registers of each fetch instruction watchpoint is used directly for comparison judgments of watchpoint checks. +The process of judging the hit of each watchpoint is as follows:

+
+
+
    +
  1. +

    If CSR.CRMD.WE=0, the judgment is terminated, otherwise turn 2;

    +
    2. +
  2. +

    If the current is not in debug mode but the DMOnly bit of FWPCFG3 is equal to 1, the judgment is terminated, otherwise turn to 3;

    +
    3. +
  3. +

    If the bit corresponding to the current privilege level in PLV0-PLV3 of FWPCFG3 is equal to 0, judge and terminate, otherwise turn to 4;

    +
    4. +
  4. +

    If the LCL bit in FWPCFG3 is equal to 1, but the CSR.ASID.ASID is not equal to the ASID in FWPCFG4, the judgment is terminated, otherwise turn 6;

    +
    5. +
  5. +

    If (pc & (~FWPCFG2.Mask)) != (FWPCFG1.VAddr & (~FWPCFG2.Mask)), that is, the address comparison is not equal, the judgment is terminated, otherwise the watchpoint is considered hit.

    +
    6. +
+
+ + ++++++ + + + + + + + + + + + + + + + + +
Table 79. Definition of fetch watchpoint n configuration 1 register
BitsNameRead/WriteDescription

GRLEN-1:0

VAddr

RW

the virtual address of the fatch watchpoint to be compared.

+ + ++++++ + + + + + + + + + + + + + + + + +
Table 80. Definition of fetch watchpoint n configuration 2 register
BitsNameRead/WriteDescription

GRLEN-1:0

Mask

RW

the mask bit of the fetch watchpoint address comparison. +If bit i (0 ≤ i < GRLEN) is 1, it means that bit i of the address is not involved in the comparison.

+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 81. Definition of fetch watchpoint n configuration 3 register
BitsNameRead/WriteDescription

0

DMOnly

RW

A bit of 1 indicates that the fetch point is only available in debug mode. +Here "available" contains two meanings: +First, the configuration register of the fetch watchpoint can be modified by software in this mode, and second, the check hit of the watchpoint will trigger a watchpoint exception and mark the status of the watchpoint only in this mode.

+

This bit can only be modified in debug mode (CSR.DBG.DM=1). +This means that the (Host) software running in debug mode has the priority to use the watchpoint.

1

PLV0

RW

This watchpoint triggers the enable of the watchpoint exception at the PLV0 privilege level. +1 - enable, 0 - disable.

2

PLV1

RW

The watchpoint triggers the watchpoint exception enable at PLV1 privilege level. +1 - enable, 0 - disable.

3

PLV2

RW

The watchpoint triggers the enable of the watchpoint exception at the PLV2 privilege level. +1 - enable, 0 - disable.

4

PLV3

RW

This watchpoint triggers the enablement of the watchpoint exception at the PLV3 privilege level. +1 - enable, 0 - disable.

6:5

0

R

If virtualization extensions are not implemented, the field is read-only constant to 0 and writes are ignored.

7

LCL

RW

1 indicates that the comparison of ASIDs is performed during the watchpoint check.

31:8

0

R0

Reserved field. +Return 0 if read this field and software is not allowed to change its value.

+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 82. Definition of fetch watchpoint n configuration 4 register
BitsNameRead/WriteDescription

9:0

ASID

RW

The ASID being compared

15:10

0

R

Read-only constant 0, writing to this field is ignored.

23:16

0

R

If the virtualization extension is not implemented, the field is read-only constant 0 and writing to this field is ignored.

31:24

0

R

Read-only constant 0, writing to this field is ignored.

+
+
+
+ +
+

7.10.1. Debug Register (DBG)

+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 83. Definition of debug data save register
BitsNameRead/WriteDescription

0

DST

R

1 to indicate that it is currently in debug mode.

+

The hardware sets this bit to 1 when a debug exception is triggered in non-debug mode.

+

When this bit is 1, the ERTN instruction is executed to clear this bit to 0.

7:1

DRev

R

The version number of the debugging mechanism. +1 is the initial version.

8

DEI

R

1 indicates that the debug exception type caught in debug mode is DEbug Interrupt (DEI).

9

DCL

R

1 indicates that the type of debug exception caught in debug mode is a Debug CaLl exception (DCL).

10

DFW

R

1 indicates that the type of debug exception caught in debug mode is the Debug Fetch Watchpoint exception (DFW).

11

DMW

R

1 indicates that the debug exception type caught in debug mode is the Debug load/store (Memory) Watchpoint exception (DMW).

15:12

0

R0

Read only as 0.

21:16

Ecode

R

+

When a non-debug exception occurs in debug mode, the exception type code is recorded here. +The meaning of the codes here is basically the same as the definitions in Table of exception encoding, with only three differences:

+
+
+
    +
  • +

    The TLB refill exception reuses the 0x7 exception code;

    +
    • +
  • +

    The debug call exception uses the 0xC exception code;

    +
    • +
  • +

    The machine error exception uses the 0xE exception code.

    +
    • +
+

31:22

0

R0

Read only as 0.

+
+
+

7.10.2. Debug Exception Return Address (DERA)

+ + ++++++ + + + + + + + + + + + + + + + + +
Table 84. Definition of debug exception program counter register
BitsNameRead/WriteDescription

63:0

PC

RW

When a debug exception is triggered in non-debug mode, the hardware records the PC that triggered the exception here.

+

When CSR.DBG.DM=1, the return address is fetched from here when the ERTN instruction is executed.

+
+
+

7.10.3. Debug Data Save Register (DSAVE)

+
+

This register is used to store data temporarily for the system software. +Each dava save register can hold the data of one general-purpose register.

+
+
+

An additional SAVE register for debug exception handler is provided because debug exceptions can occur in any scenario and the handling of debug exceptions should be transparent to the software on the Host being debugged.

+
+ + ++++++ + + + + + + + + + + + + + + + + +
Table 85. Definition of debug register
BitsNameRead/WriteDescription

63:0

Data

RW

Data for software to read and write only. +The hardware does not modify the contents of this field except for the execution of CSR instructions.

+
+
+
+
+
+

Appendix A: Pseudocode Descriptions of the Function Definitions

+
+
+

A.1. Interpretation of Operators in Pseudocode

+
+

This section lists the meaning of the statement keywords and various operators involved in pseudocode, as well as the operator precedence relationships. +In addition, the common conventions for different binary representations of numeric values in pseudocode are as follows:

+
+
+
    +
  • +

    No prefix or 'd or ##'d prefix for decimal numbers, where the ##'d prefix means that the decimal number is ## bits wide;

    +
    • +
  • +

    The prefix 'b or ##'b is used for binary numbers, where the prefix ##'b indicates that the length of the binary number is ## bits;

    +
    • +
  • +

    The prefix 'h or ##'h indicates the hexadecimal number, where the prefix ##'h indicates that the hexadecimal number is ## bits wide, and the hexadecimal value of A-F uses uppercase letters.

    +
    • +
+
+ + ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 86. Interpretation of semantic keyword
OperatorsMeaning
+
+
Return_Type Function_Name(Variable, ...):
+    Function_Body
+return Return_Value
+
+

Function Definition

+
+
if Condition1:
+    Statement1
+elif Condition2:
+    Statement2
+else:
+    Statement3
+
+

Conditional Statements

+
+
case Variable of:
+    value1: Statement1
+    value2: Statement2
+    default: Default_Statement
+
+

case conditional statement

+
+
Condition ? TRUE_Statement: FALSE_Statement
+
+

Conditional Judgment Statements

+
+
for Variable in Sequence:
+    Statements
+
+

for loop statement

+
+
range(N)
+
+

A sequence of integers from 0 to N-1 in steps of 1

+
+
range(Start, End, Step)
+
+

Sequence of specified step values from the start value (inclusive) to the end value (exclusive)

+
+
break
+
+

Terminate the current loop

+
+
signed(...)
+
+

Signed integers

+
+
unsigned(...)
+
+

Unsigned integers

+
+
fp16(...)
+
+

Half-precision floating-point numbers

+
+
fp32(...)
+
+

Single-precision floating-point numbers

+
+
fp64(...)
+
+

Double-precision floating-point numbers

+
+
boolean
+
+

Boolean Type

+
+
bit
+
+

Bit type

+
+
integer
+
+

Integer type

+
+
bits(N)
+
+

N-bit type

+
+
ZeroExtend(Variable, N)
+
+

Variable zero extended to N bits

+
+
SignExtend(Variable, N)
+
+

Variable sign extended to N bits

+
+
isSNaN(Variable)
+
+

TRUE if the variable is a signaling NaN number, FALSE otherwise

+
+
isQNaN(Variable)
+
+

TRUE if the variable is quiet NaN number, FALSE otherwise

+
+
SignalException(Exception)
+
+

Trigger exception

+
+
#
+
+

Single line comment

+
+
=
+
+

Assignment

+ + ++++ + + + + + + + + + + + + + + + + + + + + +
Table 87. Interpretation of bit string operators
OperatorsMeaning

[M:N]

Bit N to bit M of the bit string

{N{M}}

Copy bit string M N times and splice them

{N, M, …​}

Splice bit strings N, M, …​ in order

+ + ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 88. Interpretation of arithmetic operators
OperatorsMeaning

+

Add

-

Subtract

*

Multiply

/

Divide

%

Modulo

**

Power

+ + ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 89. Interpretation of comparison operators
OperatorsMeaning

==

equal to

!=

Not equal to

>

Greater than

<

Less than

>=

Greater than or equal to

<=

Less than or equal to

+ + ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 90. Interpretation of bit operators
OperatorsMeaning

&

Bitwise AND

|

Bitwise OR

^

Bitwise XOR

~

Bitwise INVERSE

<<

Logical Left Shift

>>

Logical Right Shift

>>>

Arithmetic Right Shift

+ + ++++ + + + + + + + + + + + + + + + + + + + + +
Table 91. Interpretation of logical operators
OperatorsMeaning

and

Logical AND

or

Logical OR

not

Logical NOT

+ + ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 92. Operator priority
OperatorsMeaning

**

Power

-

Inverse by place

*, /, %

Multiply, Divide, Modulo

+, -

Add, Subtract

<<, >>, >>>

Logical left shift, logical right shift, arithmetic right shift

&

Bitwise AND

^, |

Bitwise XOR, bitwise OR

>, <, >=, <=

Greater than, less than, greater than or equal to, less than or equal to

==, !=

Equal to, not equal to

not

Logical NOT

and, or

Logical AND, logical OR

+
+
+

A.2. Pseudocode Descriptions of Functional Functions

+
+

The pseudocode involved in the instruction descriptions in this manual is defined as follows.

+
+
+

A.2.1. Logical Left Shift

+
+
+
bits(N) SLL(bits(N) x, integer sa):
+    if sa == 0:
+        result = x
+    else:
+        result = {x[N-sa-1:0], {sa{1'b0}}}
+    return result
+
+
+
+
+

A.2.2. Logical Right Shift

+
+
+
bits(N) SRL(bits(N) x, integer sa):
+    if sa == 0:
+        result = x
+    else:
+        result = {{sa{1'b0}}, x[N-1:sa]}
+    return result
+
+
+
+
+

A.2.3. Arithmetic Right Shift

+
+
+
bits(N) SRA(bits(N) x, integer sa):
+    if sa == 0:
+        result = x
+    else:
+        result = {{sa{x[N-1]}}, x[N-1:sa]}
+    return result
+
+
+
+
+

A.2.4. Circular Right Shift

+
+
+
bits(N) ROTR(bits(N) x, integer sa):
+    if sa == 0:
+        result = x
+    else:
+        result = {x[sa-1:0], x[N-1:sa]}
+    return result
+
+
+
+
+

A.2.5. Count the Number of Consecutive 1’s Starting from High Order Bits

+
+
+
{bits(N)} CLO(bits(N) x):
+    cnt = 0
+    for i in range(N):
+        if x[N-1-i] == 1'b0:
+            return cnt
+        else:
+            cnt = cnt + 1
+
+
+
+
+

A.2.6. Count the Number of Consecutive 0’s Starting from High Order Bits

+
+
+
{bits(N)} CLZ(bits(N) x):
+    cnt = 0
+    for i in range(N):
+        if x[N-1-i] == 1'b1:
+            return cnt
+        else:
+            cnt = cnt + 1
+
+
+
+
+

A.2.7. Count the Number of Consecutive 1’s Starting from Low Order Bits

+
+
+
{bits(N)} CTO(bits(N) x):
+    cnt = 0
+    for i in range(N):
+        if x[i] == 1'b0:
+            return cnt
+        else:
+            cnt = cnt + 1
+
+
+
+
+

A.2.8. Count the Number of Consecutive 0’s Starting from Low Order Bits

+
+
+
{bits(N)} CTZ(bits(N) x):
+    cnt = 0
+    for i in range(N):
+        if x[i] == 1'b1:
+            return cnt
+        else:
+            cnt = cnt + 1
+
+
+
+
+

A.2.9. Reverse the Order of the Bit String

+
+
+
{bits(N)} BITREV(bits(N) x):
+    for i in range(N):
+        res[i] = x[N-1-i]
+    return res
+
+
+
+
+

A.2.10. CRC-32 Checksum Calculation

+
+
+
bits(32) CRC32(old_chksum, msg, width, poly):
+    new_chksum = (old_chksum & 0xFFFFFFFF) ^ {{(64-width){1'b0}}, msg}
+    for i in range(width):
+        if (new_chksum & 1'b1):
+            new_chksum = (new_chksum >> 1) ^ poly
+        else:
+            new_chksum = (new_chksum >> 1)
+    return new_chksum
+
+
+
+
+

A.2.11. Single Precision Floating-point to Signed Word Integer

+
+
+
{bits(32)} FP32convertToSint32(bits(32) x, bits(1) I_en, bits(2) rm):
+    case {I_en, rm} of:
+        {1'b1, 2'd0}: return Sint32_convertToIntegerExactTiesToEven(x)
+        {1'b1, 2'd1}: return Sint32_convertToIntegerExactTowardZero(x)
+        {1'b1, 2'd2}: return Sint32_convertToIntegerExactTowardPositive(x)
+        {1'b1, 2'd3}: return Sint32_convertToIntegerExactTowardNegative(x)
+        {1'b0, 2'd0}: return Sint32_convertToIntegerTiesToEven(x)
+        {1'b0, 2'd1}: return Sint32_convertToIntegerTowardZero(x)
+        {1'b0, 2'd2}: return Sint32_convertToIntegerTowardPositive(x)
+        {1'b0, 2'd3}: return Sint32_convertToIntegerTowardNegative(x)
+
+
+
+
+

A.2.12. Single Precision Floating-point to Signed Double Word Integer

+
+
+
{bits(64)} FP32convertToSint64(bits(32) x, bits(1) I_en, bits(2) rm):
+    case {I_en, rm} of:
+        {1'b1, 2'd0}: return Sint32_convertToIntegerExactTiesToEven(x)
+        {1'b1, 2'd1}: return Sint32_convertToIntegerExactTowardZero(x)
+        {1'b1, 2'd2}: return Sint32_convertToIntegerExactTowardPositive(x)
+        {1'b1, 2'd3}: return Sint32_convertToIntegerExactTowardNegative(x)
+        {1'b0, 2'd0}: return Sint32_convertToIntegerTiesToEven(x)
+        {1'b0, 2'd1}: return Sint32_convertToIntegerTowardZero(x)
+        {1'b0, 2'd2}: return Sint32_convertToIntegerTowardPositive(x)
+        {1'b0, 2'd3}: return Sint32_convertToIntegerTowardNegative(x)
+
+
+
+
+

A.2.13. Double Precision Floating-point to Signed Word Integer

+
+
+
{bits(64)} FP64convertToSint32(bits(64) x, bits(1) I_en, bits(2) rm):
+    case {I_en, rm} of:
+        {1'b1, 2'd0}: return Sint64_convertToIntegerExactTiesToEven(x)
+        {1'b1, 2'd1}: return Sint64_convertToIntegerExactTowardZero(x)
+        {1'b1, 2'd2}: return Sint64_convertToIntegerExactTowardPositive(x)
+        {1'b1, 2'd3}: return Sint64_convertToIntegerExactTowardNegative(x)
+        {1'b0, 2'd0}: return Sint64_convertToIntegerTiesToEven(x)
+        {1'b0, 2'd1}: return Sint64_convertToIntegerTowardZero(x)
+        {1'b0, 2'd2}: return Sint64_convertToIntegerTowardPositive(x)
+        {1'b0, 2'd3}: return Sint64_convertToIntegerTowardNegative(x)
+
+
+
+
+

A.2.14. Double Precision Floating-point to Signed Double Word Integer

+
+
+
{bits(64)} FP64convertToSint64(bits(64) x, bits(1) I_en, bits(2) rm):
+    case {I_en, rm} of:
+        {1'b1, 2'd0}: return Sint64_convertToIntegerExactTiesToEven(x)
+        {1'b1, 2'd1}: return Sint64_convertToIntegerExactTowardZero(x)
+        {1'b1, 2'd2}: return Sint64_convertToIntegerExactTowardPositive(x)
+        {1'b1, 2'd3}: return Sint64_convertToIntegerExactTowardNegative(x)
+        {1'b0, 2'd0}: return Sint64_convertToIntegerTiesToEven(x)
+        {1'b0, 2'd1}: return Sint64_convertToIntegerTowardZero(x)
+        {1'b0, 2'd2}: return Sint64_convertToIntegerTowardPositive(x)
+        {1'b0, 2'd3}: return Sint64_convertToIntegerTowardNegative(x)
+
+
+
+
+

A.2.15. Round Single Precision Floating-point

+
+
+
{bits(32)} FP32_roundToInteger(bits(N) x, bits(1) I_en, bits(2) rm):
+    if (I_en):
+        return FP32_roundToIntegralExact(x)
+    elif (rm == 0):
+        return FP32_roundToIntegerTiesToEven(x)
+    elif (rm == 1):
+        return FP32_roundToIntegerTowardZero(x)
+    elif (rm == 2):
+        return FP32_roundToIntegerTowardPositive(x)
+    elif (rm == 3):
+        return FP32_roundToIntegerTowardNegative(x)
+
+
+
+
+

A.2.16. Round Double Precision Floating-point

+
+
+
{bits(64)} FP64_roundToInteger(bits(N) x, bits(1) I_en, bits(2) rm):
+    if (I_en):
+        return FP64_roundToIntegralExact(x)
+    elif (rm=0):
+        return FP64_roundToIntegerTi esToEven(x)
+    elif (rm=1):
+        return FP64_roundToIntegerTowardZero(x)
+    elif (rm=2):
+        return FP64_roundToIntegerTowardPositive(x)
+    elif (rm=3):
+        return FP64_roundToIntegerTowardNegative(x)
+
+
+
+
+
+
+
+

Appendix B: Table of Instruction Encoding

+
+ + ++++++++++++++++++++++++++++++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 93. Table of instruction encoding
3130292827262524232221201918171615141312111009080706050403020100

CLO.W

rd, rj

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

0

0

rj

rd

CLZ.W

rd, rj

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

0

1

rj

rd

CTO.W

rd, rj

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

0

rj

rd

CTZ.W

rd, rj

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

1

rj

rd

CLO.D

rd, rj

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

0

0

0

rj

rd

CLZ.D

rd, rj

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

0

0

1

rj

rd

CTO.D

rd, rj

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

0

1

0

rj

rd

CTZ.D

rd, rj

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

0

1

1

rj

rd

REVB.2H

rd, rj

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

0

0

rj

rd

REVB.4H

rd, rj

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

0

1

rj

rd

REVB.2W

rd, rj

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

1

0

rj

rd

REVB.D

rd, rj

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

1

1

rj

rd

REVH.2W

rd, rj

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

0

0

0

0

rj

rd

REVH.D

rd, rj

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

0

0

0

1

rj

rd

BITREV.4B

rd, rj

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

0

0

1

0

rj

rd

BITREV.8B

rd, rj

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

0

0

1

1

rj

rd

BITREV.W

rd, rj

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

0

1

0

0

rj

rd

BITREV.D

rd, rj

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

0

1

0

1

rj

rd

EXT.W.H

rd, rj

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

0

1

1

0

rj

rd

EXT.W.B

rd, rj

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

0

1

1

1

rj

rd

RDTIMEL.W

rd, rj

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

0

0

0

rj

rd

RDTIMEH.W

rd, rj

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

0

0

1

rj

rd

RDTIME.D

rd, rj

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

0

1

0

rj

rd

CPUCFG

rd, rj

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

0

1

1

rj

rd

ASRTLE.D

rj, rk

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

0

rk

rj

0

0

0

0

0

ASRTGT.D

rj, rk

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

rk

rj

0

0

0

0

0

ALSL.W

rd, rj, rk, sa2

0

0

0

0

0

0

0

0

0

0

0

0

0

1

0

sa2

rk

rj

rd

ALSL.WU

rd, rj, rk, sa2

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

sa2

rk

rj

rd

BYTEPICK.W

rd, rj, rk, sa2

0

0

0

0

0

0

0

0

0

0

0

0

1

0

0

sa2

rk

rj

rd

BYTEPICK.D

rd, rj, rk, sa3

0

0

0

0

0

0

0

0

0

0

0

0

1

1

sa3

rk

rj

rd

ADD.W

rd, rj, rk

0

0

0

0

0

0

0

0

0

0

0

1

0

0

0

0

0

rk

rj

rd

ADD.D

rd, rj, rk

0

0

0

0

0

0

0

0

0

0

0

1

0

0

0

0

1

rk

rj

rd

SUB.W

rd, rj, rk

0

0

0

0

0

0

0

0

0

0

0

1

0

0

0

1

0

rk

rj

rd

SUB.D

rd, rj, rk

0

0

0

0

0

0

0

0

0

0

0

1

0

0

0

1

1

rk

rj

rd

SLT

rd, rj, rk

0

0

0

0

0

0

0

0

0

0

0

1

0

0

1

0

0

rk

rj

rd

SLTU

rd, rj, rk

0

0

0

0

0

0

0

0

0

0

0

1

0

0

1

0

1

rk

rj

rd

MASKEQZ

rd, rj, rk

0

0

0

0

0

0

0

0

0

0

0

1

0

0

1

1

0

rk

rj

rd

MASKNEZ

rd, rj, rk

0

0

0

0

0

0

0

0

0

0

0

1

0

0

1

1

1

rk

rj

rd

NOR

rd, rj, rk

0

0

0

0

0

0

0

0

0

0

0

1

0

1

0

0

0

rk

rj

rd

AND

rd, rj, rk

0

0

0

0

0

0

0

0

0

0

0

1

0

1

0

0

1

rk

rj

rd

OR

rd, rj, rk

0

0

0

0

0

0

0

0

0

0

0

1

0

1

0

1

0

rk

rj

rd

XOR

rd, rj, rk

0

0

0

0

0

0

0

0

0

0

0

1

0

1

0

1

1

rk

rj

rd

ORN

rd, rj, rk

0

0

0

0

0

0

0

0

0

0

0

1

0

1

1

0

0

rk

rj

rd

ANDN

rd, rj, rk

0

0

0

0

0

0

0

0

0

0

0

1

0

1

1

0

1

rk

rj

rd

SLL.W

rd, rj, rk

0

0

0

0

0

0

0

0

0

0

0

1

0

1

1

1

0

rk

rj

rd

SRL.W

rd, rj, rk

0

0

0

0

0

0

0

0

0

0

0

1

0

1

1

1

1

rk

rj

rd

SRA.W

rd, rj, rk

0

0

0

0

0

0

0

0

0

0

0

1

1

0

0

0

0

rk

rj

rd

SLL.D

rd, rj, rk

0

0

0

0

0

0

0

0

0

0

0

1

1

0

0

0

1

rk

rj

rd

SRL.D

rd, rj, rk

0

0

0

0

0

0

0

0

0

0

0

1

1

0

0

1

0

rk

rj

rd

SRA.D

rd, rj, rk

0

0

0

0

0

0

0

0

0

0

0

1

1

0

0

1

1

rk

rj

rd

ROTR.W

rd, rj, rk

0

0

0

0

0

0

0

0

0

0

0

1

1

0

1

1

0

rk

rj

rd

ROTR.D

rd, rj, rk

0

0

0

0

0

0

0

0

0

0

0

1

1

0

1

1

1

rk

rj

rd

MUL.W

rd, rj, rk

0

0

0

0

0

0

0

0

0

0

0

1

1

1

0

0

0

rk

rj

rd

MULH.W

rd, rj, rk

0

0

0

0

0

0

0

0

0

0

0

1

1

1

0

0

1

rk

rj

rd

MULH.WU

rd, rj, rk

0

0

0

0

0

0

0

0

0

0

0

1

1

1

0

1

0

rk

rj

rd

MUL.D

rd, rj, rk

0

0

0

0

0

0

0

0

0

0

0

1

1

1

0

1

1

rk

rj

rd

MULH.D

rd, rj, rk

0

0

0

0

0

0

0

0

0

0

0

1

1

1

1

0

0

rk

rj

rd

MULH.DU

rd, rj, rk

0

0

0

0

0

0

0

0

0

0

0

1

1

1

1

0

1

rk

rj

rd

MULW.D.W

rd, rj, rk

0

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

0

rk

rj

rd

MULW.D.WU

rd, rj, rk

0

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

rk

rj

rd

DIV.W

rd, rj, rk

0

0

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

rk

rj

rd

MOD.W

rd, rj, rk

0

0

0

0

0

0

0

0

0

0

1

0

0

0

0

0

1

rk

rj

rd

DIV.WU

rd, rj, rk

0

0

0

0

0

0

0

0

0

0

1

0

0

0

0

1

0

rk

rj

rd

MOD.WU

rd, rj, rk

0

0

0

0

0

0

0

0

0

0

1

0

0

0

0

1

1

rk

rj

rd

DIV.D

rd, rj, rk

0

0

0

0

0

0

0

0

0

0

1

0

0

0

1

0

0

rk

rj

rd

MOD.D

rd, rj, rk

0

0

0

0

0

0

0

0

0

0

1

0

0

0

1

0

1

rk

rj

rd

DIV.DU

rd, rj, rk

0

0

0

0

0

0

0

0

0

0

1

0

0

0

1

1

0

rk

rj

rd

MOD.DU

rd, rj, rk

0

0

0

0

0

0

0

0

0

0

1

0

0

0

1

1

1

rk

rj

rd

CRC.W.B.W

rd, rj, rk

0

0

0

0

0

0

0

0

0

0

1

0

0

1

0

0

0

rk

rj

rd

CRC.W.H.W

rd, rj, rk

0

0

0

0

0

0

0

0

0

0

1

0

0

1

0

0

1

rk

rj

rd

CRC.W.W.W

rd, rj, rk

0

0

0

0

0

0

0

0

0

0

1

0

0

1

0

1

0

rk

rj

rd

CRC.W.D.W

rd, rj, rk

0

0

0

0

0

0

0

0

0

0

1

0

0

1

0

1

1

rk

rj

rd

CRCC.W.B.W

rd, rj, rk

0

0

0

0

0

0

0

0

0

0

1

0

0

1

1

0

0

rk

rj

rd

CRCC.W.H.W

rd, rj, rk

0

0

0

0

0

0

0

0

0

0

1

0

0

1

1

0

1

rk

rj

rd

CRCC.W.W.W

rd, rj, rk

0

0

0

0

0

0

0

0

0

0

1

0

0

1

1

1

0

rk

rj

rd

CRCC.W.D.W

rd, rj, rk

0

0

0

0

0

0

0

0

0

0

1

0

0

1

1

1

1

rk

rj

rd

BREAK

code

0

0

0

0

0

0

0

0

0

0

1

0

1

0

1

0

0

code

DBCL

code

0

0

0

0

0

0

0

0

0

0

1

0

1

0

1

0

1

code

SYSCALL

code

0

0

0

0

0

0

0

0

0

0

1

0

1

0

1

1

0

code

ALSL.D

rd, rj, rk, sa2

0

0

0

0

0

0

0

0

0

0

1

0

1

1

0

sa2

rk

rj

rd

SLLI.W

rd, rj, ui5

0

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

1

ui5

rj

rd

SLLI.D

rd, rj, ui6

0

0

0

0

0

0

0

0

0

1

0

0

0

0

0

1

ui6

rj

rd

SRLI.W

rd, rj, ui5

0

0

0

0

0

0

0

0

0

1

0

0

0

1

0

0

1

ui5

rj

rd

SRLI.D

rd, rj, ui6

0

0

0

0

0

0

0

0

0

1

0

0

0

1

0

1

ui6

rj

rd

SRAI.W

rd, rj, ui5

0

0

0

0

0

0

0

0

0

1

0

0

1

0

0

0

1

ui5

rj

rd

SRAI.D

rd, rj, ui6

0

0

0

0

0

0

0

0

0

1

0

0

1

0

0

1

ui6

rj

rd

ROTRI.W

rd, rj, ui5

0

0

0

0

0

0

0

0

0

1

0

0

1

1

0

0

1

ui5

rj

rd

ROTRI.D

rd, rj, ui6

0

0

0

0

0

0

0

0

0

1

0

0

1

1

0

1

ui6

rj

rd

BSTRINS.W

rd, rj, msbw, lsbw

0

0

0

0

0

0

0

0

0

1

1

msbw

0

lsbw

rj

rd

BSTRPICK.W

rd, rj, msbw, lsbw

0

0

0

0

0

0

0

0

0

1

1

msbw

1

lsbw

rj

rd

BSTRINS.D

rd, rj, msbd, lsbd

0

0

0

0

0

0

0

0

1

0

msbd

lsbd

rj

rd

BSTRPICK.D

rd, rj, msbd, lsbd

0

0

0

0

0

0

0

0

1

1

msbd

lsbd

rj

rd

FADD.S

fd, fj, fk

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

1

fk

fj

fd

FADD.D

fd, fj, fk

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

1

0

fk

fj

fd

FSUB.S

fd, fj, fk

0

0

0

0

0

0

0

1

0

0

0

0

0

0

1

0

1

fk

fj

fd

FSUB.D

fd, fj, fk

0

0

0

0

0

0

0

1

0

0

0

0

0

0

1

1

0

fk

fj

fd

FMUL.S

fd, fj, fk

0

0

0

0

0

0

0

1

0

0

0

0

0

1

0

0

1

fk

fj

fd

FMUL.D

fd, fj, fk

0

0

0

0

0

0

0

1

0

0

0

0

0

1

0

1

0

fk

fj

fd

FDIV.S

fd, fj, fk

0

0

0

0

0

0

0

1

0

0

0

0

0

1

1

0

1

fk

fj

fd

FDIV.D

fd, fj, fk

0

0

0

0

0

0

0

1

0

0

0

0

0

1

1

1

0

fk

fj

fd

FMAX.S

fd, fj, fk

0

0

0

0

0

0

0

1

0

0

0

0

1

0

0

0

1

fk

fj

fd

FMAX.D

fd, fj, fk

0

0

0

0

0

0

0

1

0

0

0

0

1

0

0

1

0

fk

fj

fd

FMIN.S

fd, fj, fk

0

0

0

0

0

0

0

1

0

0

0

0

1

0

1

0

1

fk

fj

fd

FMIN.D

fd, fj, fk

0

0

0

0

0

0

0

1

0

0

0

0

1

0

1

1

0

fk

fj

fd

FMAXA.S

fd, fj, fk

0

0

0

0

0

0

0

1

0

0

0

0

1

1

0

0

1

fk

fj

fd

FMAXA.D

fd, fj, fk

0

0

0

0

0

0

0

1

0

0

0

0

1

1

0

1

0

fk

fj

fd

FMINA.S

fd, fj, fk

0

0

0

0

0

0

0

1

0

0

0

0

1

1

1

0

1

fk

fj

fd

FMINA.D

fd, fj, fk

0

0

0

0

0

0

0

1

0

0

0

0

1

1

1

1

0

fk

fj

fd

FSCALEB.S

fd, fj, fk

0

0

0

0

0

0

0

1

0

0

0

1

0

0

0

0

1

fk

fj

fd

FSCALEB.D

fd, fj, fk

0

0

0

0

0

0

0

1

0

0

0

1

0

0

0

1

0

fk

fj

fd

FCOPYSIGN.S

fd, fj, fk

0

0

0

0

0

0

0

1

0

0

0

1

0

0

1

0

1

fk

fj

fd

FCOPYSIGN.D

fd, fj, fk

0

0

0

0

0

0

0

1

0

0

0

1

0

0

1

1

0

fk

fj

fd

FABS.S

fd, fj

0

0

0

0

0

0

0

1

0

0

0

1

0

1

0

0

0

0

0

0

0

1

fj

fd

FABS.D

fd, fj

0

0

0

0

0

0

0

1

0

0

0

1

0

1

0

0

0

0

0

0

1

0

fj

fd

FNEG.S

fd, fj

0

0

0

0

0

0

0

1

0

0

0

1

0

1

0

0

0

0

0

1

0

1

fj

fd

FNEG.D

fd, fj

0

0

0

0

0

0

0

1

0

0

0

1

0

1

0

0

0

0

0

1

1

0

fj

fd

FLOGB.S

fd, fj

0

0

0

0

0

0

0

1

0

0

0

1

0

1

0

0

0

0

1

0

0

1

fj

fd

FLOGB.D

fd, fj

0

0

0

0

0

0

0

1

0

0

0

1

0

1

0

0

0

0

1

0

1

0

fj

fd

FCLASS.S

fd, fj

0

0

0

0

0

0

0

1

0

0

0

1

0

1

0

0

0

0

1

1

0

1

fj

fd

FCLASS.D

fd, fj

0

0

0

0

0

0

0

1

0

0

0

1

0

1

0

0

0

0

1

1

1

0

fj

fd

FSQRT.S

fd, fj

0

0

0

0

0

0

0

1

0

0

0

1

0

1

0

0

0

1

0

0

0

1

fj

fd

FSQRT.D

fd, fj

0

0

0

0

0

0

0

1

0

0

0

1

0

1

0

0

0

1

0

0

1

0

fj

fd

FRECIP.S

fd, fj

0

0

0

0

0

0

0

1

0

0

0

1

0

1

0

0

0

1

0

1

0

1

fj

fd

FRECIP.D

fd, fj

0

0

0

0

0

0

0

1

0

0

0

1

0

1

0

0

0

1

0

1

1

0

fj

fd

FRSQRT.S

fd, fj

0

0

0

0

0

0

0

1

0

0

0

1

0

1

0

0

0

1

1

0

0

1

fj

fd

FRSQRT.D

fd, fj

0

0

0

0

0

0

0

1

0

0

0

1

0

1

0

0

0

1

1

0

1

0

fj

fd

FRECIPE.S

fd, fj

0

0

0

0

0

0

0

1

0

0

0

1

0

1

0

0

0

1

1

1

0

1

fj

fd

FRECIPE.D

fd, fj

0

0

0

0

0

0

0

1

0

0

0

1

0

1

0

0

0

1

1

1

1

0

fj

fd

FRSQRTE.S

fd, fj

0

0

0

0

0

0

0

1

0

0

0

1

0

1

0

0

1

0

0

0

0

1

fj

fd

FRSQRTE.D

fd, fj

0

0

0

0

0

0

0

1

0

0

0

1

0

1

0

0

1

0

0

0

1

0

fj

fd

FMOV.S

fd, fj

0

0

0

0

0

0

0

1

0

0

0

1

0

1

0

0

1

0

0

1

0

1

fj

fd

FMOV.D

fd, fj

0

0

0

0

0

0

0

1

0

0

0

1

0

1

0

0

1

0

0

1

1

0

fj

fd

MOVGR2FR.W

fd, rj

0

0

0

0

0

0

0

1

0

0

0

1

0

1

0

0

1

0

1

0

0

1

rj

fd

MOVGR2FR.D

fd, rj

0

0

0

0

0

0

0

1

0

0

0

1

0

1

0

0

1

0

1

0

1

0

rj

fd

MOVGR2FRH.W

fd, rj

0

0

0

0

0

0

0

1

0

0

0

1

0

1

0

0

1

0

1

0

1

1

rj

fd

MOVFR2GR.S

rd, fj

0

0

0

0

0

0

0

1

0

0

0

1

0

1

0

0

1

0

1

1

0

1

fj

rd

MOVFR2GR.D

rd, fj

0

0

0

0

0

0

0

1

0

0

0

1

0

1

0

0

1

0

1

1

1

0

fj

rd

MOVFRH2GR.S

rd, fj

0

0

0

0

0

0

0

1

0

0

0

1

0

1

0

0

1

0

1

1

1

1

fj

rd

MOVGR2FCSR

fcsr, rj

0

0

0

0

0

0

0

1

0

0

0

1

0

1

0

0

1

1

0

0

0

0

rj

fcsr

MOVFCSR2GR

rd, fcsr

0

0

0

0

0

0

0

1

0

0

0

1

0

1

0

0

1

1

0

0

1

0

fcsr

rd

MOVFR2CF

cd, fj

0

0

0

0

0

0

0

1

0

0

0

1

0

1

0

0

1

1

0

1

0

0

fj

0

0

cd

MOVCF2FR

fd, cj

0

0

0

0

0

0

0

1

0

0

0

1

0

1

0

0

1

1

0

1

0

1

0

0

cj

fd

MOVGR2CF

cd, rj

0

0

0

0

0

0

0

1

0

0

0

1

0

1

0

0

1

1

0

1

1

0

rj

0

0

cd

MOVCF2GR

rd, cj

0

0

0

0

0

0

0

1

0

0

0

1

0

1

0

0

1

1

0

1

1

1

0

0

cj

rd

FCVT.S.D

fd, fj

0

0

0

0

0

0

0

1

0

0

0

1

1

0

0

1

0

0

0

1

1

0

fj

fd

FCVT.D.S

fd, fj

0

0

0

0

0

0

0

1

0

0

0

1

1

0

0

1

0

0

1

0

0

1

fj

fd

FTINTRM.W.S

fd, fj

0

0

0

0

0

0

0

1

0

0

0

1

1

0

1

0

0

0

0

0

0

1

fj

fd

FTINTRM.W.D

fd, fj

0

0

0

0

0

0

0

1

0

0

0

1

1

0

1

0

0

0

0

0

1

0

fj

fd

FTINTRM.L.S

fd, fj

0

0

0

0

0

0

0

1

0

0

0

1

1

0

1

0

0

0

1

0

0

1

fj

fd

FTINTRM.L.D

fd, fj

0

0

0

0

0

0

0

1

0

0

0

1

1

0

1

0

0

0

1

0

1

0

fj

fd

FTINTRP.W.S

fd, fj

0

0

0

0

0

0

0

1

0

0

0

1

1

0

1

0

0

1

0

0

0

1

fj

fd

FTINTRP.W.D

fd, fj

0

0

0

0

0

0

0

1

0

0

0

1

1

0

1

0

0

1

0

0

1

0

fj

fd

FTINTRP.L.S

fd, fj

0

0

0

0

0

0

0

1

0

0

0

1

1

0

1

0

0

1

1

0

0

1

fj

fd

FTINTRP.L.D

fd, fj

0

0

0

0

0

0

0

1

0

0

0

1

1

0

1

0

0

1

1

0

1

0

fj

fd

FTINTRZ.W.S

fd, fj

0

0

0

0

0

0

0

1

0

0

0

1

1

0

1

0

1

0

0

0

0

1

fj

fd

FTINTRZ.W.D

fd, fj

0

0

0

0

0

0

0

1

0

0

0

1

1

0

1

0

1

0

0

0

1

0

fj

fd

FTINTRZ.L.S

fd, fj

0

0

0

0

0

0

0

1

0

0

0

1

1

0

1

0

1

0

1

0

0

1

fj

fd

FTINTRZ.L.D

fd, fj

0

0

0

0

0

0

0

1

0

0

0

1

1

0

1

0

1

0

1

0

1

0

fj

fd

FTINTRNE.W.S

fd, fj

0

0

0

0

0

0

0

1

0

0

0

1

1

0

1

0

1

1

0

0

0

1

fj

fd

FTINTRNE.W.D

fd, fj

0

0

0

0

0

0

0

1

0

0

0

1

1

0

1

0

1

1

0

0

1

0

fj

fd

FTINTRNE.L.S

fd, fj

0

0

0

0

0

0

0

1

0

0

0

1

1

0

1

0

1

1

1

0

0

1

fj

fd

FTINTRNE.L.D

fd, fj

0

0

0

0

0

0

0

1

0

0

0

1

1

0

1

0

1

1

1

0

1

0

fj

fd

FTINT.W.S

fd, fj

0

0

0

0

0

0

0

1

0

0

0

1

1

0

1

1

0

0

0

0

0

1

fj

fd

FTINT.W.D

fd, fj

0

0

0

0

0

0

0

1

0

0

0

1

1

0

1

1

0

0

0

0

1

0

fj

fd

FTINT.L.S

fd, fj

0

0

0

0

0

0

0

1

0

0

0

1

1

0

1

1

0

0

1

0

0

1

fj

fd

FTINT.L.D

fd, fj

0

0

0

0

0

0

0

1

0

0

0

1

1

0

1

1

0

0

1

0

1

0

fj

fd

FFINT.S.W

fd, fj

0

0

0

0

0

0

0

1

0

0

0

1

1

1

0

1

0

0

0

1

0

0

fj

fd

FFINT.S.L

fd, fj

0

0

0

0

0

0

0

1

0

0

0

1

1

1

0

1

0

0

0

1

1

0

fj

fd

FFINT.D.W

fd, fj

0

0

0

0

0

0

0

1

0

0

0

1

1

1

0

1

0

0

1

0

0

0

fj

fd

FFINT.D.L

fd, fj

0

0

0

0

0

0

0

1

0

0

0

1

1

1

0

1

0

0

1

0

1

0

fj

fd

FRINT.S

fd, fj

0

0

0

0

0

0

0

1

0

0

0

1

1

1

1

0

0

1

0

0

0

1

fj

fd

FRINT.D

fd, fj

0

0

0

0

0

0

0

1

0

0

0

1

1

1

1

0

0

1

0

0

1

0

fj

fd

SLTI

rd, rj, si12

0

0

0

0

0

0

1

0

0

0

si12

rj

rd

SLTUI

rd, rj, si12

0

0

0

0

0

0

1

0

0

1

si12

rj

rd

ADDI.W

rd, rj, si12

0

0

0

0

0

0

1

0

1

0

si12

rj

rd

ADDI.D

rd, rj, si12

0

0

0

0

0

0

1

0

1

1

si12

rj

rd

LU52I.D

rd, rj, si12

0

0

0

0

0

0

1

1

0

0

si12

rj

rd

ANDI

rd, rj, ui12

0

0

0

0

0

0

1

1

0

1

ui12

rj

rd

ORI

rd, rj, ui12

0

0

0

0

0

0

1

1

1

0

ui12

rj

rd

XORI

rd, rj, ui12

0

0

0

0

0

0

1

1

1

1

ui12

rj

rd

CSRRD

rd, csr

0

0

0

0

0

1

0

0

csr

0

0

0

0

0

rd

CSRWR

rd, csr

0

0

0

0

0

1

0

0

csr

0

0

0

0

1

rd

CSRXCHG

rd, rj, csr

0

0

0

0

0

1

0

0

csr

rj!=0,1

rd

CACOP

code, rj, si12

0

0

0

0

0

1

1

0

0

0

si12

rj

code

LDDIR

rd, rj, level

0

0

0

0

0

1

1

0

0

1

0

0

0

0

level

rj

rd

LDPTE

rj, seq

0

0

0

0

0

1

1

0

0

1

0

0

0

1

seq

rj

0

0

0

0

0

IOCSRRD.B

rd, rj

0

0

0

0

0

1

1

0

0

1

0

0

1

0

0

0

0

0

0

0

0

0

rj

rd

IOCSRRD.H

rd, rj

0

0

0

0

0

1

1

0

0

1

0

0

1

0

0

0

0

0

0

0

0

1

rj

rd

IOCSRRD.W

rd, rj

0

0

0

0

0

1

1

0

0

1

0

0

1

0

0

0

0

0

0

0

1

0

rj

rd

IOCSRRD.D

rd, rj

0

0

0

0

0

1

1

0

0

1

0

0

1

0

0

0

0

0

0

0

1

1

rj

rd

IOCSRWR.B

rd, rj

0

0

0

0

0

1

1

0

0

1

0

0

1

0

0

0

0

0

0

1

0

0

rj

rd

IOCSRWR.H

rd, rj

0

0

0

0

0

1

1

0

0

1

0

0

1

0

0

0

0

0

0

1

0

1

rj

rd

IOCSRWR.W

rd, rj

0

0

0

0

0

1

1

0

0

1

0

0

1

0

0

0

0

0

0

1

1

0

rj

rd

IOCSRWR.D

rd, rj

0

0

0

0

0

1

1

0

0

1

0

0

1

0

0

0

0

0

0

1

1

1

rj

rd

TLBCLR

0

0

0

0

0

1

1

0

0

1

0

0

1

0

0

0

0

0

1

0

0

0

0

0

0

0

0

0

0

0

0

0

TLBFLUSH

0

0

0

0

0

1

1

0

0

1

0

0

1

0

0

0

0

0

1

0

0

1

0

0

0

0

0

0

0

0

0

0

TLBSRCH

0

0

0

0

0

1

1

0

0

1

0

0

1

0

0

0

0

0

1

0

1

0

0

0

0

0

0

0

0

0

0

0

TLBRD

0

0

0

0

0

1

1

0

0

1

0

0

1

0

0

0

0

0

1

0

1

1

0

0

0

0

0

0

0

0

0

0

TLBWR

0

0

0

0

0

1

1

0

0

1

0

0

1

0

0

0

0

0

1

1

0

0

0

0

0

0

0

0

0

0

0

0

TLBFILL

0

0

0

0

0

1

1

0

0

1

0

0

1

0

0

0

0

0

1

1

0

1

0

0

0

0

0

0

0

0

0

0

ERTN

0

0

0

0

0

1

1

0

0

1

0

0

1

0

0

0

0

0

1

1

1

0

0

0

0

0

0

0

0

0

0

0

IDLE

level

0

0

0

0

0

1

1

0

0

1

0

0

1

0

0

0

1

level

INVTLB

op, rj, rk

0

0

0

0

0

1

1

0

0

1

0

0

1

0

0

1

1

rk

rj

op

FMADD.S

fd, fj, fk, fa

0

0

0

0

1

0

0

0

0

0

0

1

fa

fk

fj

fd

FMADD.D

fd, fj, fk, fa

0

0

0

0

1

0

0

0

0

0

1

0

fa

fk

fj

fd

FMSUB.S

fd, fj, fk, fa

0

0

0

0

1

0

0

0

0

1

0

1

fa

fk

fj

fd

FMSUB.D

fd, fj, fk, fa

0

0

0

0

1

0

0

0

0

1

1

0

fa

fk

fj

fd

FNMADD.S

fd, fj, fk, fa

0

0

0

0

1

0

0

0

1

0

0

1

fa

fk

fj

fd

FNMADD.D

fd, fj, fk, fa

0

0

0

0

1

0

0

0

1

0

1

0

fa

fk

fj

fd

FNMSUB.S

fd, fj, fk, fa

0

0

0

0

1

0

0

0

1

1

0

1

fa

fk

fj

fd

FNMSUB.D

fd, fj, fk, fa

0

0

0

0

1

0

0

0

1

1

1

0

fa

fk

fj

fd

FCMP.cond.S

cd, fj, fk

0

0

0

0

1

1

0

0

0

0

0

1

cond

fk

fj

0

0

cd

FCMP.cond.D

cd, fj, fk

0

0

0

0

1

1

0

0

0

0

1

0

cond

fk

fj

0

0

cd

FSEL

fd, fj, fk, ca

0

0

0

0

1

1

0

1

0

0

0

0

0

0

ca

fk

fj

fd

ADDU16I.D

rd, rj, si16

0

0

0

1

0

0

si16

rj

rd

LU12I.W

rd, si20

0

0

0

1

0

1

0

si20

rd

LU32I.D

rd, si20

0

0

0

1

0

1

1

si20

rd

PCADDI

rd, si20

0

0

0

1

1

0

0

si20

rd

PCALAU12I

rd, si20

0

0

0

1

1

0

1

si20

rd

PCADDU12I

rd, si20

0

0

0

1

1

1

0

si20

rd

PCADDU18I

rd, si20

0

0

0

1

1

1

1

si20

rd

LL.W

rd, rj, si14

0

0

1

0

0

0

0

0

si14

rj

rd

SC.W

rd, rj, si14

0

0

1

0

0

0

0

1

si14

rj

rd

LL.D

rd, rj, si14

0

0

1

0

0

0

1

0

si14

rj

rd

SC.D

rd, rj, si14

0

0

1

0

0

0

1

1

si14

rj

rd

LDPTR.W

rd, rj, si14

0

0

1

0

0

1

0

0

si14

rj

rd

STPTR.W

rd, rj, si14

0

0

1

0

0

1

0

1

si14

rj

rd

LDPTR.D

rd, rj, si14

0

0

1

0

0

1

1

0

si14

rj

rd

STPTR.D

rd, rj, si14

0

0

1

0

0

1

1

1

si14

rj

rd

LD.B

rd, rj, si12

0

0

1

0

1

0

0

0

0

0

si12

rj

rd

LD.H

rd, rj, si12

0

0

1

0

1

0

0

0

0

1

si12

rj

rd

LD.W

rd, rj, si12

0

0

1

0

1

0

0

0

1

0

si12

rj

rd

LD.D

rd, rj, si12

0

0

1

0

1

0

0

0

1

1

si12

rj

rd

ST.B

rd, rj, si12

0

0

1

0

1

0

0

1

0

0

si12

rj

rd

ST.H

rd, rj, si12

0

0

1

0

1

0

0

1

0

1

si12

rj

rd

ST.W

rd, rj, si12

0

0

1

0

1

0

0

1

1

0

si12

rj

rd

ST.D

rd, rj, si12

0

0

1

0

1

0

0

1

1

1

si12

rj

rd

LD.BU

rd, rj, si12

0

0

1

0

1

0

1

0

0

0

si12

rj

rd

LD.HU

rd, rj, si12

0

0

1

0

1

0

1

0

0

1

si12

rj

rd

LD.WU

rd, rj, si12

0

0

1

0

1

0

1

0

1

0

si12

rj

rd

PRELD

hint, rj, si12

0

0

1

0

1

0

1

0

1

1

si12

rj

hint

FLD.S

fd, rj, si12

0

0

1

0

1

0

1

1

0

0

si12

rj

fd

FST.S

fd, rj, si12

0

0

1

0

1

0

1

1

0

1

si12

rj

fd

FLD.D

fd, rj, si12

0

0

1

0

1

0

1

1

1

0

si12

rj

fd

FST.D

fd, rj, si12

0

0

1

0

1

0

1

1

1

1

si12

rj

fd

LDX.B

rd, rj, rk

0

0

1

1

1

0

0

0

0

0

0

0

0

0

0

0

0

rk

rj

rd

LDX.H

rd, rj, rk

0

0

1

1

1

0

0

0

0

0

0

0

0

1

0

0

0

rk

rj

rd

LDX.W

rd, rj, rk

0

0

1

1

1

0

0

0

0

0

0

0

1

0

0

0

0

rk

rj

rd

LDX.D

rd, rj, rk

0

0

1

1

1

0

0

0

0

0

0

0

1

1

0

0

0

rk

rj

rd

STX.B

rd, rj, rk

0

0

1

1

1

0

0

0

0

0

0

1

0

0

0

0

0

rk

rj

rd

STX.H

rd, rj, rk

0

0

1

1

1

0

0

0

0

0

0

1

0

1

0

0

0

rk

rj

rd

STX.W

rd, rj, rk

0

0

1

1

1

0

0

0

0

0

0

1

1

0

0

0

0

rk

rj

rd

STX.D

rd, rj, rk

0

0

1

1

1

0

0

0

0

0

0

1

1

1

0

0

0

rk

rj

rd

LDX.BU

rd, rj, rk

0

0

1

1

1

0

0

0

0

0

1

0

0

0

0

0

0

rk

rj

rd

LDX.HU

rd, rj, rk

0

0

1

1

1

0

0

0

0

0

1

0

0

1

0

0

0

rk

rj

rd

LDX.WU

rd, rj, rk

0

0

1

1

1

0

0

0

0

0

1

0

1

0

0

0

0

rk

rj

rd

PRELDX

hint, rj, rk

0

0

1

1

1

0

0

0

0

0

1

0

1

1

0

0

0

rk

rj

hint

FLDX.S

fd, rj, rk

0

0

1

1

1

0

0

0

0

0

1

1

0

0

0

0

0

rk

rj

fd

FLDX.D

fd, rj, rk

0

0

1

1

1

0

0

0

0

0

1

1

0

1

0

0

0

rk

rj

fd

FSTX.S

fd, rj, rk

0

0

1

1

1

0

0

0

0

0

1

1

1

0

0

0

0

rk

rj

fd

FSTX.D

fd, rj, rk

0

0

1

1

1

0

0

0

0

0

1

1

1

1

0

0

0

rk

rj

fd

SC.Q

rd, rk, rj

0

0

1

1

1

0

0

0

0

1

0

1

0

1

1

1

0

rk

rj

fd

LLACQ.W

rd, rj

0

0

1

1

1

0

0

0

0

1

0

1

0

1

1

1

1

0

0

0

0

0

rj

fd

SCREL.W

rd, rj

0

0

1

1

1

0

0

0

0

1

0

1

0

1

1

1

1

0

0

0

0

1

rj

fd

LLACQ.D

rd, rj

0

0

1

1

1

0

0

0

0

1

0

1

0

1

1

1

1

0

0

0

1

0

rj

fd

SCREL.D

rd, rj

0

0

1

1

1

0

0

0

0

1

0

1

0

1

1

1

1

0

0

0

1

1

rj

fd

AMCAS.B

rd, rk, rj

0

0

1

1

1

0

0

0

0

1

0

1

1

0

0

0

0

rk

rj

fd

AMCAS.H

rd, rk, rj

0

0

1

1

1

0

0

0

0

1

0

1

1

0

0

0

1

rk

rj

fd

AMCAS.W

rd, rk, rj

0

0

1

1

1

0

0

0

0

1

0

1

1

0

0

1

0

rk

rj

fd

AMCAS.D

rd, rk, rj

0

0

1

1

1

0

0

0

0

1

0

1

1

0

0

1

1

rk

rj

fd

AMCAS_DB.B

rd, rk, rj

0

0

1

1

1

0

0

0

0

1

0

1

1

0

1

0

0

rk

rj

fd

AMCAS_DB.H

rd, rk, rj

0

0

1

1

1

0

0

0

0

1

0

1

1

0

1

0

1

rk

rj

fd

AMCAS_DB.W

rd, rk, rj

0

0

1

1

1

0

0

0

0

1

0

1

1

0

1

1

0

rk

rj

fd

AMCAS_DB.D

rd, rk, rj

0

0

1

1

1

0

0

0

0

1

0

1

1

0

1

1

1

rk

rj

fd

AMSWAP.B

rd, rk, rj

0

0

1

1

1

0

0

0

0

1

0

1

1

1

0

0

0

rk

rj

fd

AMSWAP.H

rd, rk, rj

0

0

1

1

1

0

0

0

0

1

0

1

1

1

0

0

1

rk

rj

fd

AMADD.B

rd, rk, rj

0

0

1

1

1

0

0

0

0

1

0

1

1

1

0

1

0

rk

rj

fd

AMADD.H

rd, rk, rj

0

0

1

1

1

0

0

0

0

1

0

1

1

1

0

1

1

rk

rj

fd

AMSWAP_DB.B

rd, rk, rj

0

0

1

1

1

0

0

0

0

1

0

1

1

1

1

0

0

rk

rj

fd

AMSWAP_DB.H

rd, rk, rj

0

0

1

1

1

0

0

0

0

1

0

1

1

1

1

0

1

rk

rj

fd

AMADD_DB.B

rd, rk, rj

0

0

1

1

1

0

0

0

0

1

0

1

1

1

1

1

0

rk

rj

fd

AMADD_DB.H

rd, rk, rj

0

0

1

1

1

0

0

0

0

1

0

1

1

1

1

1

1

rk

rj

fd

AMSWAP.W

rd, rk, rj

0

0

1

1

1

0

0

0

0

1

1

0

0

0

0

0

0

rk

rj

rd

AMSWAP.D

rd, rk, rj

0

0

1

1

1

0

0

0

0

1

1

0

0

0

0

0

1

rk

rj

rd

AMADD.W

rd, rk, rj

0

0

1

1

1

0

0

0

0

1

1

0

0

0

0

1

0

rk

rj

rd

AMADD.D

rd, rk, rj

0

0

1

1

1

0

0

0

0

1

1

0

0

0

0

1

1

rk

rj

rd

AMAND.W

rd, rk, rj

0

0

1

1

1

0

0

0

0

1

1

0

0

0

1

0

0

rk

rj

rd

AMAND.D

rd, rk, rj

0

0

1

1

1

0

0

0

0

1

1

0

0

0

1

0

1

rk

rj

rd

AMOR.W

rd, rk, rj

0

0

1

1

1

0

0

0

0

1

1

0

0

0

1

1

0

rk

rj

rd

AMOR.D

rd, rk, rj

0

0

1

1

1

0

0

0

0

1

1

0

0

0

1

1

1

rk

rj

rd

AMXOR.W

rd, rk, rj

0

0

1

1

1

0

0

0

0

1

1

0

0

1

0

0

0

rk

rj

rd

AMXOR.D

rd, rk, rj

0

0

1

1

1

0

0

0

0

1

1

0

0

1

0

0

1

rk

rj

rd

AMMAX.W

rd, rk, rj

0

0

1

1

1

0

0

0

0

1

1

0

0

1

0

1

0

rk

rj

rd

AMMAX.D

rd, rk, rj

0

0

1

1

1

0

0

0

0

1

1

0

0

1

0

1

1

rk

rj

rd

AMMIN.W

rd, rk, rj

0

0

1

1

1

0

0

0

0

1

1

0

0

1

1

0

0

rk

rj

rd

AMMIN.D

rd, rk, rj

0

0

1

1

1

0

0

0

0

1

1

0

0

1

1

0

1

rk

rj

rd

AMMAX.WU

rd, rk, rj

0

0

1

1

1

0

0

0

0

1

1

0

0

1

1

1

0

rk

rj

rd

AMMAX.DU

rd, rk, rj

0

0

1

1

1

0

0

0

0

1

1

0

0

1

1

1

1

rk

rj

rd

AMMIN.WU

rd, rk, rj

0

0

1

1

1

0

0

0

0

1

1

0

1

0

0

0

0

rk

rj

rd

AMMIN.DU

rd, rk, rj

0

0

1

1

1

0

0

0

0

1

1

0

1

0

0

0

1

rk

rj

rd

AMSWAP_DB.W

rd, rk, rj

0

0

1

1

1

0

0

0

0

1

1

0

1

0

0

1

0

rk

rj

rd

AMSWAP_DB.D

rd, rk, rj

0

0

1

1

1

0

0

0

0

1

1

0

1

0

0

1

1

rk

rj

rd

AMADD_DB.W

rd, rk, rj

0

0

1

1

1

0

0

0

0

1

1

0

1

0

1

0

0

rk

rj

rd

AMADD_DB.D

rd, rk, rj

0

0

1

1

1

0

0

0

0

1

1

0

1

0

1

0

1

rk

rj

rd

AMAND_DB.W

rd, rk, rj

0

0

1

1

1

0

0

0

0

1

1

0

1

0

1

1

0

rk

rj

rd

AMAND_DB.D

rd, rk, rj

0

0

1

1

1

0

0

0

0

1

1

0

1

0

1

1

1

rk

rj

rd

AMOR_DB.W

rd, rk, rj

0

0

1

1

1

0

0

0

0

1

1

0

1

1

0

0

0

rk

rj

rd

AMOR_DB.D

rd, rk, rj

0

0

1

1

1

0

0

0

0

1

1

0

1

1

0

0

1

rk

rj

rd

AMXOR_DB.W

rd, rk, rj

0

0

1

1

1

0

0

0

0

1

1

0

1

1

0

1

0

rk

rj

rd

AMXOR_DB.D

rd, rk, rj

0

0

1

1

1

0

0

0

0

1

1

0

1

1

0

1

1

rk

rj

rd

AMMAX_DB.W

rd, rk, rj

0

0

1

1

1

0

0

0

0

1

1

0

1

1

1

0

0

rk

rj

rd

AMMAX_DB.D

rd, rk, rj

0

0

1

1

1

0

0

0

0

1

1

0

1

1

1

0

1

rk

rj

rd

AMMIN_DB.W

rd, rk, rj

0

0

1

1

1

0

0

0

0

1

1

0

1

1

1

1

0

rk

rj

rd

AMMIN_DB.D

rd, rk, rj

0

0

1

1

1

0

0

0

0

1

1

0

1

1

1

1

1

rk

rj

rd

AMMAX_DB.WU

rd, rk, rj

0

0

1

1

1

0

0

0

0

1

1

1

0

0

0

0

0

rk

rj

rd

AMMAX_DB.DU

rd, rk, rj

0

0

1

1

1

0

0

0

0

1

1

1

0

0

0

0

1

rk

rj

rd

AMMIN_DB.WU

rd, rk, rj

0

0

1

1

1

0

0

0

0

1

1

1

0

0

0

1

0

rk

rj

rd

AMMIN_DB.DU

rd, rk, rj

0

0

1

1

1

0

0

0

0

1

1

1

0

0

0

1

1

rk

rj

rd

DBAR

hint

0

0

1

1

1

0

0

0

0

1

1

1

0

0

1

0

0

hint

IBAR

hint

0

0

1

1

1

0

0

0

0

1

1

1

0

0

1

0

1

hint

FLDGT.S

fd, rj, rk

0

0

1

1

1

0

0

0

0

1

1

1

0

1

0

0

0

rk

rj

fd

FLDGT.D

fd, rj, rk

0

0

1

1

1

0

0

0

0

1

1

1

0

1

0

0

1

rk

rj

fd

FLDLE.S

fd, rj, rk

0

0

1

1

1

0

0

0

0

1

1

1

0

1

0

1

0

rk

rj

fd

FLDLE.D

fd, rj, rk

0

0

1

1

1

0

0

0

0

1

1

1

0

1

0

1

1

rk

rj

fd

FSTGT.S

fd, rj, rk

0

0

1

1

1

0

0

0

0

1

1

1

0

1

1

0

0

rk

rj

fd

FSTGT.D

fd, rj, rk

0

0

1

1

1

0

0

0

0

1

1

1

0

1

1

0

1

rk

rj

fd

FSTLE.S

fd, rj, rk

0

0

1

1

1

0

0

0

0

1

1

1

0

1

1

1

0

rk

rj

fd

FSTLE.D

fd, rj, rk

0

0

1

1

1

0

0

0

0

1

1

1

0

1

1

1

1

rk

rj

fd

LDGT.B

rd, rj, rk

0

0

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

rk

rj

rd

LDGT.H

rd, rj, rk

0

0

1

1

1

0

0

0

0

1

1

1

1

0

0

0

1

rk

rj

rd

LDGT.W

rd, rj, rk

0

0

1

1

1

0

0

0

0

1

1

1

1

0

0

1

0

rk

rj

rd

LDGT.D

rd, rj, rk

0

0

1

1

1

0

0

0

0

1

1

1

1

0

0

1

1

rk

rj

rd

LDLE.B

rd, rj, rk

0

0

1

1

1

0

0

0

0

1

1

1

1

0

1

0

0

rk

rj

rd

LDLE.H

rd, rj, rk

0

0

1

1

1

0

0

0

0

1

1

1

1

0

1

0

1

rk

rj

rd

LDLE.W

rd, rj, rk

0

0

1

1

1

0

0

0

0

1

1

1

1

0

1

1

0

rk

rj

rd

LDLE.D

rd, rj, rk

0

0

1

1

1

0

0

0

0

1

1

1

1

0

1

1

1

rk

rj

rd

STGT.B

rd, rj, rk

0

0

1

1

1

0

0

0

0

1

1

1

1

1

0

0

0

rk

rj

rd

STGT.H

rd, rj, rk

0

0

1

1

1

0

0

0

0

1

1

1

1

1

0

0

1

rk

rj

rd

STGT.W

rd, rj, rk

0

0

1

1

1

0

0

0

0

1

1

1

1

1

0

1

0

rk

rj

rd

STGT.D

rd, rj, rk

0

0

1

1

1

0

0

0

0

1

1

1

1

1

0

1

1

rk

rj

rd

STLE.B

rd, rj, rk

0

0

1

1

1

0

0

0

0

1

1

1

1

1

1

0

0

rk

rj

rd

STLE.H

rd, rj, rk

0

0

1

1

1

0

0

0

0

1

1

1

1

1

1

0

1

rk

rj

rd

STLE.W

rd, rj, rk

0

0

1

1

1

0

0

0

0

1

1

1

1

1

1

1

0

rk

rj

rd

STLE.D

rd, rj, rk

0

0

1

1

1

0

0

0

0

1

1

1

1

1

1

1

1

rk

rj

rd

BEQZ

rj, offs

0

1

0

0

0

0

offs[15:0]

rj

offs[20:16]

BNEZ

rj, offs

0

1

0

0

0

1

offs[15:0]

rj

offs[20:16]

BCEQZ

cj, offs

0

1

0

0

1

0

offs[15:0]

0

0

cj

offs[20:16]

BCNEZ

cj, offs

0

1

0

0

1

0

offs[15:0]

0

1

cj

offs[20:16]

JIRL

rd, rj, offs

0

1

0

0

1

1

offs[15:0]

rj

rd

B

offs

0

1

0

1

0

0

offs[15:0]

offs[25:16]

BL

offs

0

1

0

1

0

1

offs[15:0]

offs[25:16]

BEQ

rj, rd, offs

0

1

0

1

1

0

offs[15:0]

rj

rd

BNE

rj, rd, offs

0

1

0

1

1

1

offs[15:0]

rj

rd

BLT

rj, rd, offs

0

1

1

0

0

0

offs[15:0]

rj

rd

BGE

rj, rd, offs

0

1

1

0

0

1

offs[15:0]

rj

rd

BLTU

rj, rd, offs

0

1

1

0

1

0

offs[15:0]

rj

rd

BGEU

rj, rd, offs

0

1

1

0

1

1

offs[15:0]

rj

rd

+
+
+
+
+
+
+1. Translator’s note: Forward compatibility here may be ambiguous. +
+
+2. It is generated only when it is a memory access instruction of bound class. +
+
+3. The definition of TLB-related exceptions dictates that only one TLB-related exception will be generated by a single memory access instruction in any case. +
+
+4. The instructions affected by this control bit include LD[X].{H[U]/W[U]/D}, ST[X].{H/W/D}, LDPTR.{W/D}, STPTR.{W/D}, FLD[X].{S/D}, FST[X].{S/D}, LDPTE, LDDIR, IOCSRRD.{H/W/D} and IOCSRWR.{H/WD}. +
+
+5. Translator’s note: This may be the fifth attribute not listed in Attributes of Reading and Writing. +
+
+6. Translator’s note: This may be the fifth attribute not listed in Attributes of Reading and Writing. +
+
+ + +
+ + Creative Commons License + +
+ This work is licensed under a + Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License. +
+ + + + + + + + + \ No newline at end of file diff --git a/LoongArch-Vol1-EN.pdf b/LoongArch-Vol1-EN.pdf new file mode 100644 index 0000000..86b39cf Binary files /dev/null and b/LoongArch-Vol1-EN.pdf differ diff --git a/LoongArch-Vol2-EN.html b/LoongArch-Vol2-EN.html new file mode 100644 index 0000000..20c2df5 --- /dev/null +++ b/LoongArch-Vol2-EN.html @@ -0,0 +1,80 @@ + + + + + + + + +LoongArch Reference Manual - Volume 2: Vector Extensions + + + + +
+
+
+
+

TBD

+
+
+
+
+ + +
+ + Creative Commons License + +
+ This work is licensed under a + Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License. +
+ + + + + + + + + \ No newline at end of file diff --git a/LoongArch-Vol2-EN.pdf b/LoongArch-Vol2-EN.pdf new file mode 100644 index 0000000..853ca87 Binary files /dev/null and b/LoongArch-Vol2-EN.pdf differ diff --git a/LoongArch-Vol3-EN.html b/LoongArch-Vol3-EN.html new file mode 100644 index 0000000..916c97e --- /dev/null +++ b/LoongArch-Vol3-EN.html @@ -0,0 +1,80 @@ + + + + + + + + +LoongArch Reference Manual - Volume 3: Virtualization and Binary Translation Extensions + + + + +
+
+
+
+

TBD

+
+
+
+
+ + +
+ + Creative Commons License + +
+ This work is licensed under a + Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License. +
+ + + + + + + + + \ No newline at end of file diff --git a/LoongArch-Vol3-EN.pdf b/LoongArch-Vol3-EN.pdf new file mode 100644 index 0000000..f8e6548 Binary files /dev/null and b/LoongArch-Vol3-EN.pdf differ diff --git a/LoongArch-toolchain-conventions-CN.html b/LoongArch-toolchain-conventions-CN.html new file mode 100644 index 0000000..addb7b4 --- /dev/null +++ b/LoongArch-toolchain-conventions-CN.html @@ -0,0 +1,888 @@ + + + + + + + + +龙芯架构工具链约定 + + + + +
+
+
+
+

注：在本文档中，"架构"、"指令集架构"、"ISA" 均表示某一指令集和可操作的寄存器集合。

+
+
+
+
+

编译器命令行选项

+
+
+

概述

+
+

与龙芯架构相关的编译器选项含义包括以下三方面：

+
+
+
    +
  • +

    配置目标架构：允许使用的指令集和寄存器范围；

    +
    • +
  • +

    配置目标 ABI：标准数据类型的表示方法，函数调用传参、返回的实现方式；

    +
    • +
  • +

    配置优化参数：用于指导编译器优化的微架构特性。

    +
    • +
+
+
+

为此，编译器应实现以下两类命令行选项：

+
+
+
    +
  • +

    基础选项：选择编译目标的基本配置，包括 -march -mabi -mtune；

    +
    • +
  • +

    扩展选项：对基础选项或基础选项默认值的配置进行增量调整。

    +
    • +
+
+ + +++++ + + + + + + + + + + + + + + + + + + + + + + + + +
Table 1. 基础选项
选项可用值描述

-march=

native loongarch64 la464

选择目标架构：设定默认可用的指令集和寄存器范围 +（即默认使用的 指令集模块 集合）

-mabi=

lp64d lp64f lp64s ilp32d ilp32f ilp32s

选择基础 ABI 类型

-mtune=

native loongarch64 la464

选择目标微架构：设定微架构相关的性能调优参数； +取值范围是 -march 选项的超集，默认值与 -march 值相同

+
+
    +
  • +

    -march 和 -mtune 参数的取值应代表实现龙芯架构的处理器或产品系列。

    +
    • +
  • +

    原则上，不同 -march 取值所代表的默认指令集互不相同。

    +
    • +
+
+ + +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 2. 扩展选项
选项可用值描述

-msoft-float

禁止使用浮点数指令， +并对当前选择的基础 ABI 进行调整，以采用软浮点调用惯例。 +(调整后的基础 ABI 名称后缀为 s)

-msingle-float

允许使用 32 位浮点数指令， +并对当前选择的基础 ABI 进行调整，以采用 32 位浮点调用惯例。 +(调整后的基础 ABI 名称后缀为 f)

-mdouble-float

允许使用 32 位和 64 位浮点数指令， +并对当前选择的基础 ABI 进行调整，以采用 64 位浮点调用惯例。 +(调整后的基础 ABI 名称后缀为 d)

-mfpu=

64 32 0 none (等同于 0)

(可选实现) 选择可用的基础浮点数指令和寄存器范围，非必要不调整浮点调用惯例。 +(在软件项目或脚本中，建议直接使用 `-m*-float'。)

+
+

在一条编译命令中，各龙芯架构相关选项的总体配置效果等同于它们按先后顺序依次生效的结果。 +唯一的例外是 -m*-float ：它们对浮点指令集和调用惯例的配置不会被除 -m*-float 之外 +其他类型的后续选项改变。

+
+
+
+

目标指令集架构 (ISA) 的构成

+
+

龙芯架构采用 基础部分 加 扩展部分 的组织形式， +在后续更新过程中，基础部分或扩展部分中的各功能子集都可以独立地演进， +并保证高版本总是二进制兼容低版本。

+
+
+

针对这一特点，编译器应当对目标 ISA 进行模块化抽象。 +约定 ISA 模块分为两类： 基础架构 和 ISA 扩展特性 。

+
+
+

其中，基础架构 为目标 ISA 的核心部分，包含基础整数指令、基础浮点数指令等功能， +由 -march 选项的取值唯一确定。ISA 扩展特性 可能对应一种单独的指令集扩展， +也可能对应基础架构或指令集扩展的增量/演进部分，由扩展选项控制是否开启。

+
+
+

在确定目标 ISA 配置时，应以 基础架构 隐含的 ISA 模块为基础， +再根据选用 / 关闭 ISA 扩展的命令行选项进行调整，得出结果。

+
+
+
+compiler isa config model CN +
+
+
+

在以下列举的所有的 ISA 模块中，编译器必须至少实现一种基础架构。

+
+ + +++++ + + + + + + + + + + + + + + +
Table 3. 基础架构
名称选择该基础架构的 -march 值描述

LA64 基础架构 v1.00 (la64v100)

loongarch64 la464

由 《龙芯架构参考手册 - 卷1 - 基础架构》 +v1.00 定义的指令集架构

+
+

下表列举了由编译器抽象的全体 ISA 扩展特性，以及选用/关闭这些特性的命令行选项。

+
+ + +++++ + + + + + + + + + + + + + + +
Table 4. ISA 扩展特性
名称编译器选项描述

基础浮点运算单元 (fpu*)

-mfpu=* (* 可能取值为 none 32 64)

选择编译器可用的基础浮点数指令和浮点寄存器，属于基础架构的一部分， +默认值由基础架构决定。

+
+

下表列举了所有可同时作为 -march 和 -mtune 选项参数的目标 CPU 类型 +及其相关属性。

+
+ + +++++ + + + + + + + + + + + + + + + + + + + + + + + + +
Table 5. 目标 CPU
名称 / 选项值默认选择的 ISA 模块性能调优目标

native

由 cpucfg 指令自动检测（仅适用于本地编译器）

由 cpucfg 自动检测的处理器类型

loongarch64

la64v100 [fpu64]

通用 64 位龙芯架构 (LA64) 处理器

la464

la64v100 [fpu64]

LA464 处理器核

+
+
+

应用二进制接口 (ABI) 的构成

+
+

对于龙芯架构编译器，完整的 ABI 配置应包含两个部分： +基础 ABI 和 ABI 扩展特性 。前者描述了 ABI 中整型和浮点数据的表示、 +传参和返回方式，后者则代表对基础 ABI 进行的总体调整，可能需要特定 ISA 扩展支持。

+
+
+

需要注意的是，不同 ABI 扩展特性之间是 互斥 的，不能相互叠加； +具有不同扩展特性的 ABI 配置之间也 互不兼容 。

+
+
+

原则上本文档不会增加新的 ABI 扩展特性，除非它能提供 +其他编译器优化技术不能单独实现的功能或性能优势。

+
+
+

基础 ABI 共有六种，编译器可根据实现的目标架构范围，选择实现其中的一种或多种， +其标准名称和对应的 -mabi 选项值一致。

+
+ + +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 6. 基础 ABI 类型
标准名称数据模型可用于传参、返回的通用/浮点寄存器宽度

lp64d

LP64

64 / 64

lp64f

LP64

64 / 32

lp64s

LP64

64 / （无）

ilp32d

ILP32

32 / 64

ilp32f

ILP32

32 / 32

ilp32s

ILP32

32 / （无）

+
+

下表列举了全体 ABI 扩展特性类型及其相关命令行选项，除 base 必须实现之外， +编译器可选择实现或不实现其中任何一种。

+
+
+

当引述一种 ABI 名称时，若仅给出基础 ABI 类型， +则 ABI 扩展特性类型默认为 base 。

+
+ + +++++ + + + + + + + + + + + + + + +
Table 7. ABI 扩展特性类型
名称编译器选项含义

base

（无）

符合 龙芯架构 ELF psABI 规范

+
+

编译器的默认 ABI 应在构建时确定。此时若未明确配置 ABI 扩展特性类型， +则采用 base 。

+
+
+

原则上，实际配置的目标架构不应该对目标 ABI 的确定造成影响， +当命令行选项对 ABI 的明确约束导致实现它所需的指令集特性 +超出了编译选项对 ISA 配置的约束范围。编译器应报错退出。

+
+
+

若命令行选项未声明或未完整声明目标 ABI 类型， +缺失的部分（基础 ABI 或 ABI 扩展类型）应当取构建时确定的默认值。 +当编译选项中明确约束的 ISA 范围不足以实现该默认 ABI 配置时， +编译器的实际行为 不确定 ，因为在缩减默认可用指令集范围的同时， +用户应该通过命令行选项明确表示使用何种 ABI 。

+
+
+

对于编译器实现来说，此时推荐的行为是报错退出，但出于易用性的考量， +也可以在默认配置允许的范围内谨慎地选择一种当前可用指令集能够实现的 +备选 ABI。对于这种情况，建议编译器输出提示或警告信息以通知用户。 +例如，对于默认 ABI 为 lp64d / base 的编译器， +若编译选项为 -mfpu=none ，则可能自动调整 ABI 到 lp64s / base 。

+
+
+

当编译选项不能唯一确定目标架构时，编译器应当首先检查默认值是否能满足 +ABI 配置的需要。若不能，则应根据下表，在默认可用指令集基础上增加选用 +缺失的模块，但不违反已给出编译选项对目标架构的明确约束。

+
+ + +++++ + + + + + + + + + + + + + + + + + + + + + + + + +
Table 8. 实现各 ABI 类型所需的最小目标架构
基础 ABI 类型ABI 扩展特性类型最小目标架构包含的 ISA 模块

lp64d

base

la64v100 [fpu64]

lp64f

base

la64v100 fpu32

lp64s

base

la64v100 fpunone

+
+
+
+
+

GNU 目标三元组和 Multiarch 架构标识符

+
+
+

GNU 目标三元组 (target triplet) 是 GNU 构建系统用于描述目标平台的字符串， +一般包含三个字段：处理器类型 (machine) ，系统厂商 (vendor)，操作系统 (os)。

+
+
+

Multiarch 架构标识符 是用于 multiarch 库安装路径的目录名称， +可以看作规范的 GNU 目标三元组，参见 Debian 文档 。

+
+
+

对于龙芯架构的合法 GNU 目标三元组，约定 machine 字段的取值范围及其含义如下：

+
+ + ++++ + + + + + + + + + + + + + + + + +
Table 9. 龙芯架构 machine 字符串
machine 字符串含义

loongarch64

LA64 基础架构，基础 ABI 为 lp64*

loongarch32

LA32 基础架构，基础 ABI 为 ilp32*

+
+

作为标准的库路径名称，龙芯架构的标准 multiarch 架构标识符至少应该反映 +发行到对应目录的二进制库 ABI 类型。

+
+
+

原则上，在编译以二进制形式发行的库时，应当采用 +所选 ABI 对应的默认目标指令集架构， +因此 multiarch 架构标识符应与目标 ABI 配置一一对应。 +其中，关于整型 ABI 的部分由 machine 字段隐含， +基础 ABI 的浮点部分和 ABI 扩展特性则分别由连续附加在 multiarch 标识符 +os 字段后的两个字符串后缀 (<fabi_suffix><abiext_suffix>) 标记。

+
+ + ++++ + + + + + + + + + + + + + + + + + + + + +
Table 10. Multiarch os 字段，<fabi_suffix> 后缀标记及其含义
<fabi_suffix> 字符串含义

（空）

基础 ABI 使用 64 位浮点寄存器传参 (lp64d)

f32

基础 ABI 使用 32 位浮点寄存器传参 (lp64f)

sf

基础 ABI 不使用浮点寄存器传参 (lp64s)

+ + ++++ + + + + + + + + + + + + +
Table 11. Multiarch os 字段，<abiext_suffix> 后缀标记及其对应的 ABI 扩展特性
<abiext_suffix> 字符串ABI 扩展特性

（空）

base

+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 12. 全体 Mulitarch 标识符列表
ABI 类型（基础 ABI / ABI 扩展特性）C 库内核Multiarch 架构标识符

lp64d / base

glibc

Linux

loongarch64-linux-gnu

lp64f / base

glibc

Linux

loongarch64-linux-gnuf32

lp64s / base

glibc

Linux

loongarch64-linux-gnusf

lp64d / base

musl libc

Linux

loongarch64-linux-musl

lp64f / base

musl libc

Linux

loongarch64-linux-muslf32

lp64s / base

musl libc

Linux

loongarch64-linux-muslsf

+
+
+
+

C/C++ 预处理器内建宏定义

+
+
+

下表列举的预处理器内建宏定义并非 LoongArch 独有。 +通过使用它们，用户可以尽量减少为 LoongArch 特殊编写的代码量， +而往往足以取得架构适配的预期结果。

+
+ + +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 13. 非特定于 LoongArch 的 C/C++ 预处理器内建宏
名称值描述

__BYTE_ORDER__

（略）

字节序

__FLOAT_WORD_ORDER__

（略）

浮点数据的字节序

__LP64__ _LP64

（略）

ABI 是否使用 64 位通用寄存器传参，采用 LP64 数据模型

__SIZEOF_SHORT__

（略）

C/C++ short 类型位宽，单位为字节

__SIZEOF_INT__

（略）

C/C++ int 类型位宽，单位为字节

__SIZEOF_LONG__

（略）

C/C++ long 类型位宽，单位为字节

__SIZEOF_LONG_LONG__

（略）

C/C++ long long 类型位宽，单位为字节

__SIZEOF_INT128__

（略）

C/C++ __int128 类型位宽，单位为字节

__SIZEOF_POINTER__

（略）

C/C++ 指针类型位宽，单位为字节

__SIZEOF_PTRDIFF_T__

（略）

C/C++ ptrdiff_t 类型位宽，单位为字节

__SIZEOF_SIZE_T__

（略）

C/C++ size_t 类型位宽，单位为字节

__SIZEOF_WINT_T__

（略）

C/C++ wint_t 类型位宽，单位为字节

__SIZEOF_WCHAR_T__

（略）

C/C++ wchar_t 类型位宽，单位为字节

__SIZEOF_FLOAT__

（略）

C/C++ float 类型位宽，单位为字节

__SIZEOF_DOUBLE__

（略）

C/C++ double 类型位宽，单位为字节

__SIZEOF_LONG_DOUBLE__

（略）

C/C++ long double 类型位宽，单位为字节

+
+

在上述通用的定义之外，为了沟通那些与架构强相关的信息，仍然需要提供一些 +LoongArch 平台特有的预处理器内建宏。下表列举了这些架构相关的宏定义。

+
+ + +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 14. LoongArch 架构相关 C/C++ 预处理器内建宏
名称值描述

__loongarch__

1

目标为龙芯架构

__loongarch_grlen

64 32

通用寄存器位宽

__loongarch_frlen

0 32 64

浮点寄存器位宽（无 FPU 则为 0 ）

__loongarch_arch

"loongarch64" "la464"

-march 指定的目标 CPU 名称， +若未指定则为编译器构建时指定的默认值

__loongarch_tune

"loongarch64" "la464"

-mtune 指定的目标 CPU 名称， +若未指定则为编译器构建时指定的默认值

__loongarch_lp64

未定义或 1

ABI 使用 64 位通用寄存器传参，采用 LP64 数据模型

__loongarch_hard_float

未定义或 1

ABI 使用浮点寄存器传参

__loongarch_soft_float

未定义或 1

ABI 不使用浮点寄存器传参

__loongarch_single_float

未定义或 1

ABI 仅使用 32 位浮点寄存器传参

__loongarch_double_float

未定义或 1

ABI 使用 64 位浮点寄存器传参

+
+

由于历史原因，最早期的 LoongArch C/C++ 编译器提供了一批 MIPS 风格的预处理器内建宏。 +因为用到这些宏的旧代码可能仍在被使用，符合本规范的编译器实现可以选择提供下表所述的预处理器内建宏。

+
+
+

由于这些宏的命名风格、使用姿势多多少少都与上表中的宏不一致， +且使用它们并不会有额外好处，还造成额外的学习成本，因此不建议新的编译器实现这些宏。 +可移植的代码不应当假定这些宏存在，也不应当使用它们。

+
+ + +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 15. 用于兼容早期移植代码的 C/C++ 预处理器内建宏
名称等价于备注

__loongarch64

__loongarch_grlen == 64

行为类似 mips64 ，当且仅当 loongarch_grlen == 64 时被定义。

_LOONGARCH_ARCH

__loongarch_arch

（无）

_LOONGARCH_TUNE

__loongarch_tune

（无）

_LOONGARCH_SIM

（无）

行为类似于 MIPS 架构上的 _MIPS_SIM ；其取值形如 _ABILP64 （对应数据模型为 LP64 的情况）、 _ABILP32 （对应数据模型为 ILP32 的情况；注意取值中少了个 I ）。

_LOONGARCH_SZINT

__SIZEOF_INT__ 乘以 8

（无）

_LOONGARCH_SZLONG

__SIZEOF_LONG__ 乘以 8

（无）

_LOONGARCH_SZPTR

__SIZEOF_POINTER__ 乘以 8

（无）

+
+
+
+ + +
+ + Creative Commons License + +
+ This work is licensed under a + Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License. +
+ + + + + + + + + \ No newline at end of file diff --git a/LoongArch-toolchain-conventions-CN.pdf b/LoongArch-toolchain-conventions-CN.pdf new file mode 100644 index 0000000..80a18f7 Binary files /dev/null and b/LoongArch-toolchain-conventions-CN.pdf differ diff --git a/LoongArch-toolchain-conventions-EN.html b/LoongArch-toolchain-conventions-EN.html new file mode 100644 index 0000000..57d2802 --- /dev/null +++ b/LoongArch-toolchain-conventions-EN.html @@ -0,0 +1,934 @@ + + + + + + + + +LoongArch Toolchain Conventions + + + + +
+
+
+
+

Note: In this document, the terms "architecture", "instruction set architecture" and "ISA" +are used synonymously and refer to a certain set of instructions and the set of registers +they can operate upon.

+
+
+
+
+

Compiler Options

+
+
+

Rationale

+
+

Compiler options that are specific to LoongArch should denote a change +in the following compiler settings:

+
+
+
    +
  • +

    Target architecture: the allowed set of instructions and registers +to be used by the compiler.

    +
    • +
  • +

    Target ABI type: the data model and calling conventions.

    +
    • +
  • +

    Target microarchitecture: microarchitectural features that guides +compiler optimizations.

    +
    • +
+
+
+

For this model, two categories of LoongArch-specific compiler options +should be implemented：

+
+
+
    +
  • +

    Basic options: select the base configuration of the compilation target. +(include only -march -mabi and -mtune)

    +
    • +
  • +

    Extended options: make incremental changes to the target configuration.

    +
    • +
+
+ + +++++ + + + + + + + + + + + + + + + + + + + + + + + + +
Table 1. Basic Options
OptionPossible valuesDescription

-march=

native loongarch64 la464

Selects the target architecture, i.e. +the basic set of ISA modules to be enabled.

-mabi=

lp64d lp64f lp64s ilp32d ilp32f ilp32s

Selects the base ABI type.

-mtune=

native loongarch64 la464

Selects the type of target microarchitecture, defaults to the value of -march. +The set of possible values should be a superset of -march values.

+
+
    +
  • +

    Valid parameter values of -march and -mtune options should correspond to +actual LoongArch processor implementations / families.

    +
    • +
  • +

    In principle, different -march values should not imply the same set +of ISA modules.

    +
    • +
+
+ + +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 2. Extended Options
OptionPossible valuesDescription

-msoft-float

Prevent the compiler from generating hardware floating-point instructions, +and adjust the selected base ABI type to use soft-float calling convention. +(The adjusted base ABI identifier should have suffix s.)

-msingle-float

Allow generating 32-bit floating-point instructions, +and adjust the selected base ABI type to use 32-bit FP calling convention. +(The adjusted base ABI identifier should have suffix f.)

-mdouble-float

Allow generating 32- and 64-bit floating-point instructions. +and adjust the selected base ABI type to use 64-bit FP calling convention. +(The adjusted base ABI identifier should have suffix d.)

-mfpu=

64 32 0 none (equivalent to 0)

Selects the allowed set of basic floating-point instructions and registers. +This option should not change the FP calling convention unless it’s necessary. +(The implementation of this option is not mandatory. It is recommended to use +-m*-float options in software projects and scripts.)

+
+

As a general rule, the effect of all LoongArch-specific compiler options +that are given for one compiler invocation should be as if they are +processed in the order they appear on the command line. +The only exception to this rule is -m*-float: their configuration of +floating-point instruction set and calling convention will not be changed +by subsequent options other than -m*-float.

+
+
+
+

Configuring Target ISA

+
+

The LoongArch ISA is organized in a "base-extension" manner. +For future updates, each component in the base or extened part of the ISA +may evolve independently while keeping compatibility with previous versions of itself.

+
+
+

For this purpose, the compiler should make a modular abstraction about the target ISA. +The ISA modules are divided into two categories： base architectures and ISA extensions. +A base architecture is the core component of the target ISA, which defines the base +set of functionalities like integer and floating-point operations, and is decided +by the value of -march. An ISA extension may represent either the base of a certain +extended ISA component or an incremental update to it, and is enabled / disabled by +extended options.

+
+
+

For a complier, the final ISA configuration should be derived by applying various +ISA extension configurations from extended options to the base ISA, +which is selected via the -march option and consists of the base +architecture and the set of default ISA extensions.

+
+
+
+compiler isa config model EN +
+
+
+

Among all ISA modules listed below, the compiler should at least implement +one base architecture.

+
+ + +++++ + + + + + + + + + + + + + + +
Table 3. Base Architecture
Name-march values that selects this moduleDescription

LA64 basic architecture v1.00 (la64v100)

loongarch64 la464

ISA defined in +LoongArch Reference Manual - Volume 1: Basic Architecture v1.00.

+
+

The following table lists all ISA extensions that should be abstracted by the compiler +and the compiler options to enable / disable them.

+
+ + +++++ + + + + + + + + + + + + + + +
Table 4. ISA extensions
NameRelated compiler optionsDescription

Basic Floating-Point Processing Unit (fpu*)

-mfpu=* (Possible values of *: none 32 64)

Selects the allowed set of basic floating-point instructions +and floating-point registers. This is a constituent part of +the base architecture, where it gets its default value.

+
+

The following table lists the properties of all target CPU models +that can serve as arguments to -march and -mtune options +at the same time.

+
+ + +++++ + + + + + + + + + + + + + + + + + + + + + + + + +
Table 5. Target CPU Models (-march=<model> and -mtune=<model>)
Name / ValueISA modules that are enabled by defaultTarget of optimization

native

auto-detected with cpucfg (only on native and cross-native compilers)

auto-detected microarchitecture model / features

loongarch64

la64v100 [fpu64]

generic LoongArch LA64 processors

la464

la64v100 [fpu64]

LA464 processor core

+
+
+

Configuring Target ABI

+
+

Like configuring the target ISA, a complete ABI configuration of LoongArch +consists of two parts, the base ABI and the ABI extension. The former +describes the data model and calling convention in general, while the latter +denotes an overall adjustment to the base ABI, which may require support +from certain ISA extensions.

+
+
+

Please be noted that there is only ONE ABI extension slot in an ABI +configuration. They do not combine with one another, +and are, in principle, mutually incompatible.

+
+
+

A new ABI extension type will not be added to this document unless +it implies certain significant performance / functional advantage +that no compiler optimization techniques can provide without +altering the ABI.

+
+
+

There are six base ABI types, whose standard names are the same as +the -mabi values that select them. The compiler may choose to implement +one or more of these base ABI types, possibly according to the range of +implemented target ISA variants.

+
+ + +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 6. Base ABI Types
Standard nameData modelBit-width of argument / return value GPRs / FPRs

lp64d

LP64

64 / 64

lp64f

LP64

64 / 32

lp64s

LP64

64 / (none)

ilp32d

ILP32

32 / 64

ilp32f

ILP32

32 / 32

ilp32s

ILP32

32 / (none)

+
+

The following table lists all ABI extension types and +related compiler options. A compiler may choose to implement +any subset of these extensions that contains base.

+
+
+

The default ABI extension type is base when referring to +an ABI type with only the "base" component.

+
+ + +++++ + + + + + + + + + + + + + + +
Table 7. ABI Extension Types
NameCompiler optionsDescription

base

(none)

conforms to the LoongArch ELF psABI

+
+

The compiler should know the default ABI to use during its build time. +If the ABI extension type is not explicitly configured, +base should be used.

+
+
+

In principle, the target ISA configuration should not affect the decision +of the target ABI. When certain ISA feature required by explicit +(i.e. from the compiler’s command-line arguments) ABI configuration +cannot be met due constraints imposed by ISA options, the compiler should +abort with an error message to complain about the conflict.

+
+
+

When the ABI is not fully constrained by the compiler options, the default +configuration of either the base ABI or the ABI extension, whichever is missing +from the command line, should be attempted. If this default ABI setting +cannot be implemented by the explicitly configured target ISA, the expected +behavior is undefined since the user is encouraged to specify which +ABI to use when choosing a smaller instruction set than the default.

+
+
+

In this case, it is suggested that the compiler should abort with +an error message, however, for user-friendliness, it may also choose +to ignore the default base ABI or ABI extension and select a viable +fallback ABI for the currently enabled ISA modules with caution. +It is also recommended that the compiler should notify the user about the +ABI change, optionally with a compiler warning. +For example, passing -mfpu=none as the only command-line argument +may cause a compiler configured with lp64d / base default ABI +to automatically select lp64s / base instead.

+
+
+

When the target ISA configuration cannot be uniquely decided from the given +compiler options, the build-time default should be consulted first. +If the default ISA setting is insufficient for implementing the ABI configuration, +the compiler should try enabling the missing ISA modules according to the following +table, as long as they are not explicitly disabled or excluded from usage.

+
+ + +++++ + + + + + + + + + + + + + + + + + + + + + + + + +
Table 8. Minimal architecture requirements for implementing each ABI type.
Base ABI typeABI extension typeMinimal required ISA modules

lp64d

base

la64v100 [fpu64]

lp64f

base

la64v100 fpu32

lp64s

base

la64v100 fpunone

+
+
+
+
+

GNU Target Triplets and Multiarch Specifiers

+
+
+

Target triplet is a core concept in the GNU build system. +It describes a platform on which the code runs and mostly consists of three fields: +the CPU family / model (machine), the vendor (vendor), and the operating +system name (os).

+
+
+

Multiarch architecture apecifiers are essentially standard directory names +where libraries are installed on a multiarch-flavored filesystem. +These strings are normalized GNU target triplets. See +debian documentation for details.

+
+
+

This document recognizes the following machine strings +for the GNU triplets of LoongArch:

+
+ + ++++ + + + + + + + + + + + + + + + + +
Table 9. LoongArch machine strings：
machineDescription

loongarch64

LA64 base architecture (implies lp64* ABI)

loongarch32

LA32 base architecture (implies ilp32* ABI)

+
+

As standard library directory names, the canonical multiarch architecture specifiers +of LoongArch should contain information about the ABI type of the libraries +that are meant to be released in the binary form and installed there.

+
+
+

While the integer base ABI is implied by the machine field, +the floating-point base ABI and the ABI extension type are encoded +with two string suffices (<fabi-suffix><abiext-suffix>) to the os field of the +specifier, respectively.

+
+ + ++++ + + + + + + + + + + + + + + + + + + + + +
Table 10. List of possible <fabi-suffix>
<fabi-suffix>Description

(empty string)

The base ABI uses 64-bit FPRs for parameter passing. (lp64d)

f32

The base ABI uses 32-bit FPRs for parameter passing. (lp64f)

sf

The base ABI uses no FPR for parameter passing. (lp64s)

+ + ++++ + + + + + + + + + + + + +
Table 11. List of possible <abiext-suffix>
<abiext-suffix>ABI extension type

(empty string)

base

+
+

(Note: Since in principle, The default ISA configuration of the ABI +should be used in this binary-release scenario, it is not necessary to reserve +multiple multiarch specifiers for one OS / ABI combination.)

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 12. List of LoongArch mulitarch specifiers
ABI type (Base ABI / ABI extension)C LibraryKernelMultiarch specifier

lp64d / base

glibc

Linux

loongarch64-linux-gnu

lp64f / base

glibc

Linux

loongarch64-linux-gnuf32

lp64s / base

glibc

Linux

loongarch64-linux-gnusf

lp64d / base

musl libc

Linux

loongarch64-linux-musl

lp64f / base

musl libc

Linux

loongarch64-linux-muslf32

lp64s / base

musl libc

Linux

loongarch64-linux-muslsf

+
+
+
+

C/C++ Preprocessor Built-in Macro Definitions

+
+
+

The definitions listed below is not specific to LoongArch. +Amount of LoongArch-specific code can be minimized by utilizing them, +while achieving expected portability in most of cases.

+
+ + +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 13. Non-LoongArch-specific C/C++ Built-in Macros：
NamePossible ValuesDescription

__BYTE_ORDER__

(omitted)

Byte order

__FLOAT_WORD_ORDER__

(omitted)

Byte order for floating-point data

__LP64__ _LP64

(omitted)

Whether the ABI passes arguments in 64-bit GPRs and uses the LP64 data model

__SIZEOF_SHORT__

(omitted)

Width of C/C++ short type, in bytes

__SIZEOF_INT__

(omitted)

Width of C/C++ int type, in bytes

__SIZEOF_LONG__

(omitted)

Width of C/C++ long type, in bytes

__SIZEOF_LONG_LONG__

(omitted)

Width of C/C++ long long type, in bytes

__SIZEOF_INT128__

(omitted)

Width of C/C++ __int128 type, in bytes

__SIZEOF_POINTER__

(omitted)

Width of C/C++ pointer types, in bytes

__SIZEOF_PTRDIFF_T__

(omitted)

Width of C/C++ ptrdiff_t type, in bytes

__SIZEOF_SIZE_T__

(omitted)

Width of C/C++ size_t type, in bytes

__SIZEOF_WINT_T__

(omitted)

Width of C/C++ wint_t type, in bytes

__SIZEOF_WCHAR_T__

(omitted)

Width of C/C++ wchar_t type, in bytes

__SIZEOF_FLOAT__

(omitted)

Width of C/C++ float type, in bytes

__SIZEOF_DOUBLE__

(omitted)

Width of C/C++ double type, in bytes

__SIZEOF_LONG_DOUBLE__

(omitted)

Width of C/C++ long double type, in bytes

+
+

Apart from the generic definitions described above, some architecture-specific macros are still needed to convey those information strongly tied to the architecture; these macros are listed below.

+
+ + +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 14. LoongArch-specific C/C++ Built-in Macros：
NamePossible ValuesDescription

__loongarch__

1

Defined if the target is LoongArch.

__loongarch_grlen

64

Bit-width of general purpose registers.

__loongarch_frlen

0 32 64

Bit-width of floating-point registers (0 if there is no FPU).

__loongarch_arch

"loongarch64" "la464"

Processor model as specified by -march. +If -march is not present, the build-time default should be used.

__loongarch_tune

"loongarch64" "la464"

Processor model as specified by -mtune. +If -mtune is not present, the build-time default should be used.

__loongarch_lp64

undefined or 1

Defined if ABI uses the LP64 data model and 64-bit GPRs for parameter passing.

__loongarch_hard_float

undefined or 1

Defined if floating-point/extended ABI type is single or double.

__loongarch_soft_float

undefined or 1

Defined if floating-point/extended ABI type is soft.

__loongarch_single_float

undefined or 1

Defined if floating-point/extended ABI type is single.

__loongarch_double_float

undefined or 1

Defined if floating-point/extended ABI type is double.

+
+

For historical reasons, the earliest LoongArch C/C++ compilers provided some MIPS-style built-in macros. +Because legacy code dependent on those macros is possibly still in use, compilers conformant to this specification may provide the macros as listed below.

+
+
+

Because the naming style and usage of these macros are more-or-less inconsistent with the other macros described above, there is learning cost involved in using these macros. +As they bring no advantage over the other macros, it is not recommended for newer compilers to implement them; +portable code should not assume existence of these macros, nor use them.

+
+ + +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 15. C/C++ Built-in Macros Provided for Compatibility with Historical Code
NameEquivalent toDescription

__loongarch64

__loongarch_grlen == 64

Similar to mips64; defined iff loongarch_grlen == 64.

_LOONGARCH_ARCH

__loongarch_arch

n/a

_LOONGARCH_TUNE

__loongarch_tune

n/a

_LOONGARCH_SIM

n/a

Similar to _MIPS_SIM on MIPS; possible values are _ABILP64 (in case data model is LP64) and _ABILP32 (in case data model is ILP32; notice the omission of letter I).

_LOONGARCH_SZINT

__SIZEOF_INT__ multiplied by 8

n/a

_LOONGARCH_SZLONG

__SIZEOF_LONG__ multiplied by 8

n/a

_LOONGARCH_SZPTR

__SIZEOF_POINTER__ multiplied by 8

n/a

+
+
+
+ + +
+ + Creative Commons License + +
+ This work is licensed under a + Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License. +
+ + + + + + + + + \ No newline at end of file diff --git a/LoongArch-toolchain-conventions-EN.pdf b/LoongArch-toolchain-conventions-EN.pdf new file mode 100644 index 0000000..99bf51f Binary files /dev/null and b/LoongArch-toolchain-conventions-EN.pdf differ diff --git a/Loongson-3A5000-usermanual-EN.html b/Loongson-3A5000-usermanual-EN.html new file mode 100644 index 0000000..cff41eb --- /dev/null +++ b/Loongson-3A5000-usermanual-EN.html @@ -0,0 +1,24454 @@ + + + + + + + + +Loongson 3A5000/3B5000 Processor Reference Manual - Multicore Processor Architecture, Register Descriptions and System Software Programming Guide + + + + +
+
+

List of Figures

+
+
+ +
+
+
+
+

List of Tables

+
+
+ +
+
+
+
+

About this manual

+
+
+

Copyright Statement

+
+

The copyright of this document belongs to Loongson Technology Corporation Limited. +Without written permission, no company or individualmay disclose, reproduce or otherwise distribute any part of this document to third parties. +Otherwise, they will be held legally responsible.

+
+
+
+

Disclaimer

+
+

This document provides only periodic information, and the contents contained may be updated at any time without notice, depending on the actual situation of the product. +Loongson Technology Corporation Limited is not responsible for any direct or indirect damage aused by the improper use of the document.

+
+
+
+

Loongson Technology Corporation Limited

+
+

Building No.2, Loongson Industrial Park,
+Zhongguancun Environmental Protection Park, Haidian District, Beijing

+
+
+

Tel: 010-62546668

+
+
+

Fax: 010-62600826

+
+
+
+

Reading Guide

+
+

This manual introduces the Loongson 3A5000/3B5000 multicore processor architecture and register descriptions. +It provides detailed descriptions of the chip system architecture, functions and configurations of the main modules, register lists and bit fields.

+
+
+
+

Translator’s Note

+
+

These documents were translated by Yanteng Si and Feiyang Chen.

+
+
+

This is the translation of https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-3A5000-usermanual-v1.03-CN.pdf.

+
+
+

Due to the limited knowledge of the translators, there are some inevitable errors and omissions existing in this document, please feel free to correct.

+
+
+
+

License

+
+

This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License. +To view a copy of this license, visit http://creativecommons.org/licenses/by-nc-nd/4.0/ or send a letter to Creative Commons, PO Box 1866, Mountain View, CA 94042, USA.

+
+
+
+

Contributors

+
+

Since the release of the project, we have gotten several errata and content changes donated. +Here are all the people who have contributed to LoongArch Documentation as an open source project. +Thank you everyone for helping make this a better book for everyone.

+
+
+

The contributors are listed in alphabetical order.

+
+
+
+
Chao LI <lichao@loongson.cn>
+Chenghua Xu <xuchenghua@loongson.cn>
+Dandan Zhang <zhangdandan@loongson.cn>
+Feiyang Chen <chenfeiyang@loongson.cn>
+FreeFlyingSheep <fyang.168.hi@163.com>
+Konstantin Romanov <konstantinsromanov@gmail.com>
+LI Chao <lichao@loongson.cn>
+limeidan <limeidan@loongson.cn>
+liuzhensong <liuzhensong@loongson.cn>
+mengqinggang <mengqinggang@loongson.cn>
+Qi Hu <huqi@loongson.cn>
+qmuntal <quimmuntal@gmail.com>
+tangxiaolin <tangxiaolin@loongson.cn>
+WANG Xuerui <git@xen0n.name>
+wangguofeng <wangguofeng@loongson.cn>
+Wu Xiaotian <wuxiaotian@loongson.cn>
+Wu Xiaotian <yetist@gmail.com>
+Xi Ruoyao <xry111@mengyan1223.wang>
+Yang Yujie <yangyujie@alumni.sjtu.edu.cn>
+Yang Yujie <yangyujie@loongson.cn>
+Yanteng <siyanteng@loongson.cn>
+Yanteng Si <siyanteng@loongson.cn>
+
+
+
+
+
+
+

1. Introduction

+
+
+

1.1. Introduction to the Loongson Family of Processors

+
+

Loongson processors mainly include three series. +Loongson Series 1 processor adopts 32-bit processor cores and integrates various peripheral interfaces to form application-specific monolithic solutions, which are mainly applied to IOT terminals, instrumentation devices, data acquisition and other fields. +Loongson Series 2 processor adopts 32-bit/64-bit processor cores and integrates various peripheral interfaces to form a high-performance low-power SoC chip for network devices, industrial terminals, intelligent manufacturing, etc. +Loongson Series 3 processors integrate multiple 64-bit processor cores and necessary storage and IO interfaces on-chip, targeting high-end embedded computers, desktops, servers and other applications.

+
+
+

The Loongson 3 multi-core series processors are designed based on a scalable multi-core interconnect architecture, which integrates multiple high-performance processor cores and a large amount of Level 2 Cache on a single chip, and interconnects multiple chips through high-speed I/O interfaces to form a larger scale system.

+
+
+

The scalable interconnect architecture adopted by Loongson 3 is shown in the figure below. +Each node consists of 8 × 8 cross-switches, with each cross-switch connecting four processor cores and four shared caches, and interconnecting with other nodes in four directions: East (E), South (N), West (W), and North (N).

+
+
+
+loongson 3 system architecture +
+
Figure 1. Loongson 3 System architecture
+
+
+

The node structure of the Loongson 3 is shown in the figure below. +Each node has two levels of AXI cross-switches connecting the processor, the shared Cache, the memory controller, and the I/O controller. +The first level AXI cross-switch (called X1 Switch) connects the processor and the shared Cache, and the second level cross-switch (called X2 Switch) connects the shared Cache and the memory controller.

+
+
+
+loongson 3 node structure +
+
Figure 2. Loongson 3 node structure
+
+
+

In each node, up to 8 × 8 X1 cross switches are connected to four processor cores (P0, P1, P2, P3 in the figure) through four Master ports. +The four interleave shared Cache blocks (S0, S1, S2, S3 in the figure) are universally addressed through the four slave ports. +Other nodes or I/O nodes in the East, South, West and North directions are connected via four pairs of Master/Slave ports (EM/ES, SM/SS, WM/WS, NM/NS in the figure).

+
+
+

The X2 cross-switch connects four shared Caches via four Master ports, at least one Slave port to a memory controller, and at least one slave port to a configuration module (Xconf) of the cross-switch that is used to configure the address windows of X1 and X2 of this node. +Additional memory controllers, I/O ports, can be connected as needed.

+
+
+
+

1.2. Introduction to Loongson 3A5000/3B5000

+
+

The Loongson 3A5000/3B5000 is a quad-core Loongson processor with a stable operating frequency of 2.0-2.5GHz.

+
+
+

The main technical features are as follows:

+
+
+
    +
  • +

    On-chip integration of four 64-bit quad-launch superscalar LA464 processor cores.

    +
    • +
  • +

    Peak floating-point computing power 160GFLOPS@2.5GHz.

    +
    • +
  • +

    On-chip integration of 16MB of split shared tertiary Cache.

    +
    • +
  • +

    Maintenance of Cache consistency for multi-core and I/O DMA accesses via directory protocol.

    +
    • +
  • +

    On-chip integration of two 72-bit DDR4 controllers with ECC, supporting DDR4-3200.

    +
    • +
  • +

    On-chip integration of two 16-bit HyperTransport controllers (hereinafter referred to as HT) with a maximum bus frequency of 3.2 GHz.

    +
    • +
  • +

    Each group of 16-bit HT ports can be split into two groups of 8-bit HT ports for use.

    +
    • +
  • +

    2 I2C, 1 UART, 1 SPI, 16 GPIO interfaces on-chip

    +
    • +
+
+
+

The architecture of the Loongson 3A5000/3B5000 is designed to increase the shared Cache capacity based on the 3A4000 and supports 16-way interconnect.

+
+
+

The Loongson 3B5000 supports consistent interconnects on the HT0 interface compared to the 3A5000, with special filtering based on server scenario requirements. +There is no difference in the other parts from the hardware and software perspective, and they are collectively referred to as 3A5000.

+
+
+

The overall architecture of the Loongson 3A5000 chip is based on multi-level interconnects and is shown in the figure below.

+
+
+
+loongson 3a5000 chip structure +
+
Figure 3. Loongson 3A5000 chip structure
+
+
+

The first level of interconnect uses a 5 × 5 frequency division switch to connect four LA464 cores (as masters), four shared Cache modules (as slaves), and one I/O port to I/O-RING (The I/O port uses one Master and one Slave).

+
+
+

The second level interconnect uses a 5 × 3 cross-switch to connect four shared Cache modules (as masters), two DDR3/4 memory controllers, and one I/O port to the I/O-RING.

+
+
+

The I/O-RING contains 8 ports and the connections include 4 HT controllers, MISC module, SE module and two level cross switches. +The two HT controllers (lo/hi) share the 16-bit HT bus, which is used as two 8-bit HT buses, or lo can occupy the 16-bit HT bus exclusively. +A DMA controller is integrated into the HT controller, which is responsible for the DMA control of the I/O and the maintenance of inter-chip consistency.

+
+
+

All of these interconnect structures use read/write separated data channels with a 128-bit data channel width operating at the same frequency as the processor core to provide high-speed on-chip data transport. +In addition, a one-level cross-switch connects the four processor cores to the SCache with a 256-bit read data channel to increase the read bandwidth of the on-chip processor cores accessing the SCache.

+
+
+
+
+
+

2. System Configuration and Control

+
+
+

2.1. Chip Operating Modes

+
+

Depending on the structure of the constituent systems, the Loongson 3A5000 consists of two main operating modes. +Single-chip mode: The system contains only 1 chip of Loongson 3A5000, which is a symmetric multiprocessor system (SMP). +Multi-chip interconnect mode: The system contains 2, 4, or 16 chips of the Loongson 3A5000 interconnected through HT ports to form a non-uniform access multiprocessor system (CC-NUMA).

+
+
+
+

2.2. Descriptions of Pins

+
+

Main control pins include DO_TEST, ICCC_EN, NODE_ID[2:0], CLKSEL[9:0], and CHIP_CONFIG[5:0].

+
+ + +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 5. Descriptions of control pins
SignalPull-up or Pull-downDescription

DO_TEST

Pull-up

1’b1 indicates functional mode

+

1’b0 indicates test mode

ICCC_EN

Pull-down

1’b1 indicates multi-chip coherent interconnect mode

+

1’b0 indicates single chip mode

NODE_ID[2:0]

Indicates the processor number in multi-chip coherent interconnect mode

CLKSEL[9:0]

+ ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 1. HT clock control
SignalDescription

CLKSEL[9]

1’b1 indicates that HT PLL clock uses CLKSEL[7:6] to control

+

1’b0 indicates that initial frequency multiplier is 1X and can be reconfigured by software

CLKSEL[8]

1’b1 indicates that HT PLL uses the SYSCLK clock input

+

1’b0 indicates that HT PLL uses the differential clock input

CLKSEL[7:6]

2’b00 indicates that PHY clock frequency is 1.6GHz

+

2’b01 indicates that PHY clock frequency is 6.4GHz

+

2’b10 Reserved

+

2’b11 indicates that PHY clock frequency is 4.8GHz

CLKSEL[5]

Reserved

CLKSEL[4]

1’b1 - the reference clock is 25MHz

+

1’b0 - the reference clock is 100MHz

+ + ++++ + + + + + + + + + + + + + + + + + + + + + + + + +
Table 2. MEM clock control (clock frequency should be 1/2 of the interface clock)
CLKSEL[3:2]Output Frequency

2’b00

466MHz

2’b01

600MHz

2’b10

Software configuration (PLL clock multiplier is 1.6-3.2GHz)

2’b11

SYSCLK (100MHz/25MHz)

+ + ++++ + + + + + + + + + + + + + + + + + + + + + + + + +
Table 3. Main clock control (network and maximum processor core frequency)
CLKSEL[1:0]Output Frequency

2’b00

1GHz

2’b01

2GHz

2’b10

Software configuration (PLL clock multiplier is 4.8-6.4GHz)

2’b11

SYSCLK (100MHz/25MHz)

CHIP_CONFIG[5:0]

+ ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 4. Chip configuration control
CHIP_CONFIG[0]SE function enable

CHIP_CONFIG[1]

Default HT Gen1 Mode

CHIP_CONFIG[2]

NodeID[3]

CHIP_CONFIG[3]

HT1-hi enters consistency mode by default

CHIP_CONFIG[4]

HT1-lo enters consistency mode by default and is used to support 8/16 way interconnects

CHIP_CONFIG[5]

On-chip clock debug enable (DCDL)

+
+
+
+
+

3. Physical Address Space Layout

+
+
+

The Loongson 3 Seriesprocessor has a globally accessible hierarchical addressing design for system physical address distribution to ensure extended system development compatibility. +The physical address width of the entire system is 48 bits. +The entire address space is evenly distributed over 16 nodes according to the high 4 bits of the address, i.e., 44 bits of address space per node.

+
+
+

3.1. Physical Address Space Layout Between Nodes

+
+

The Loongson 3A5000 processor can be directly connected with 2/4/8/16 3A5000 chips to build a CC-NUMA system, the processor number of each chip is determined by the pin NODEID, and the address space of each chip is distributed as follows:

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 6. System global address layout at the node level
Chip Node ID (NODEID)[47:44] Bits of the AddressStart addressEnd address

0

0

0x0000_0000_0000

0x0FFF_FFFF_FFFF

1

1

0x1000_0000_0000

0x1FFF_FFFF_FFFF

2

2

0x2000_0000_0000

0x2FFF_FFFF_FFFF

3

3

0x3000_0000_0000

0x3FFF_FFFF_FFFF

4

4

0x4000_0000_0000

0x4FFF_FFFF_FFFF

5

5

0x5000_0000_0000

0x5FFF_FFFF_FFFF

6

6

0x6000_0000_0000

0x6FFF_FFFF_FFFF

7

7

0x7000_0000_0000

0x7FFF_FFFF_FFFF

8

8

0x8000_0000_0000

0x8FFF_FFFF_FFFF

9

9

0x9000_0000_0000

0x9FFF_FFFF_FFFF

10

10

0xA000_0000_0000

0xAFFF_FFFF_FFFF

11

11

0xB000_0000_0000

0xBFFF_FFFF_FFFF

12

12

0xC000_0000_0000

0xCFFF_FFFF_FFFF

13

13

0xD000_0000_0000

0xDFFF_FFFF_FFFF

14

14

0xE000_0000_0000

0xEFFF_FFFF_FFFF

15

15

0xF000_0000_0000

0xFFFF_FFFF_FFFF

+
+

When the number of system nodes is less than 16 nodes, the nodemask field of the route setting register (0x1fe00400) should be set to ensure that a response can be obtained even if there is no physical node address when a guessed access occurs (2-way: 0x1; 4-way: 0x3; 8-way: 0x7; 16-way: 0xF).

+
+
+
+

3.2. Physical Address Space Layout Within Nodes

+
+

The Loongson 3A5000 uses a single node 4-core configuration, so the corresponding addresses of the DDR memory controller and HT bus integrated in the Loongson 3A5000 chip are contained in a 44-bit address space from 0x0 (inclusive) to 0x1000_0000_0000 (exclusive). +Within each node, the 44-bit address space is further divided among all devices connected within the node, and requests are routed to the four shared Cache modules only when the access type is cached. +Depending on the chip and system architecture configuration, if there is no slave device connected on a port, the corresponding address space is reserved address space and access is not allowed.

+
+
+

The address space corresponding to each slave device side of the Loongson 3A5000 chip internal interconnect is as follows:

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 7. Address layout within nodes
Devicethe [43:40] bits of the addressStart address within nodesEnd address within nodes

MC0

4

0x400_0000_0000

0x4FF_FFFF_FFFF

MC1

5

0x500_0000_0000

0x5FF_FFFF_FFFF

SE

c

0xC00_0000_0000

0xCFF_FFFF_FFFF

HT0 Lo controller

a

0xA00_0000_0000

0xAFF_FFFF_FFFF

HT0 Hi controller

b

0xB00_0000_0000

0xBFF_FFFF_FFFF

HT1 Lo controller

e

0xE00_0000_0000

0xEFF_FFFF_FFFF

HT1 Hi controller

f

0xF00_0000_0000

0xFFF_FFFF_FFFF

+
+

Unlike the directional port mapping relationship, the Loongson 3A5000 can determine the cross-addressing method of the shared Cache based on the access behavior of the actual application. +The address space corresponding to the four shared Cache modules in the node is determined based on one or two select bits of the address bits, and can be dynamically configured and modified by software. +A configuration register named SCID_SEL is set to determine the address selection bits, as shown in the following table. +By default the [7:6] address hash is used for distribution, i.e., the two bits of address [7:6] determine the corresponding shared Cache number. +This register is addressed as 0x1fe00400 and can also be accessed using the configuration register instruction (IOCSR).

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 8. SCID_SEL Address bit configuration
SCID_SELAddress Bit SelectionSCID_SELAddress Bit Selection

4’h0

7: 6

4’h8

23:22

4’h1

9: 8

4’h9

25:24

4’h2

11:10

4’ha

27:26

4’h3

13:12

4’hb

29:28

4’h4

15:14

4’hc

31:30

4’h5

17:16

4’hd

33:32

4’h6

19:18

4’he

35:34

4’h7

21:20

4’hf

37:36

+
+

The default distribution of the internal 44-bit physical addresses for each node of the Loongson 3A5000 processor is shown in the table below:

+
+ + +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 9. 44-bit physical address layout within nodes
Address RangeAccess PropertiesDestination

addr[43:40]==4’ha

Local node, uncache

HT0_LO

addr[43:40]==4’hb

Local node, uncache

HT0_HI

addr[43:40]==4’hc

Local node, uncache

SE

addr[43:40]==4’he

Local node, uncache

HT1_LO

addr[43:40]==4’hf

Local node, uncache

HT1_HI

0x10000000-0x1fffffff, 0x3ff00000-0x3ff0ffff (can be turned off)

Local node, uncache

MISC

Mc interleave is 0 and is not the above address

Local node, uncache

MC0

Mc interleave is 1 and is not the above address

Local node, uncache

MC1

SCache interleave is 0 (address bit selection is determined by scid_sel)

Local node, Cache

Scache0

SCache interleave is 1 (address bit selection is determined by scid_sel)

Local node, Cache

Scache1

SCache interleave is 2 (address bit selection is determined by scid_sel)

Local node, Cache

Scache2

SCache interleave is 3 (address bit selection is determined by scid_sel)

Local node, Cache

Scache3

+
+
+

3.3. Address Routing Layout and Configuration

+
+

The routing of the loongson 3A5000 is mainly implemented through the system’s two-level cross switch with IO-RING. +The software can configure the routing of the requests received by each Master port. +Each Master port has 8 address windows, and the target routing of 8 address windows can be completed. +Each address window consists of three 64-bit registers, BASE, MASK and MMAP, with BASE aligned by K bytes; MASK adopts a format similar to network mask with high bit of 1; the lower four bits of MMAP indicate the number of the corresponding target Slave port; MMAP[4] indicates allow fetch instrustions; MMAP[5] indicates allow block read; MMAP[6] indicates allow interleaved access enable; MMAP[7] indicates window enable.

+
+ + ++++++ + + + + + + + + + + + + + + + + +
Table 10. Space access attributes corresponding to MMAP
[7][6][5][4]

Window enable

Allow interleaved access to SCache/memory

Allow to read blocks

Allow to fetch instructions

+
+

Window hit formula: (IN_ADDR & MASK) == BASE

+
+
+

Since Loongson 3 uses fixed routing by default, the configuration window is closed at power-up and requires system software to enable it for use.

+
+
+

When the SCache/memory interleaved access configuration is enabled, the slave number is only valid when it is 0 or 4. +0 indicates routing to SCACHE and SCID_SEL determines how interleaved access is performed across the 4 SCaches. +4 indicates routing to memory and interleave_bit determines how interleaved accesses are performed across the 2 MCs.

+
+
+

The address window translation registers are shown in the table below. +The base address is 0x1FE0_0000, or accessed via the IOCSR instruction.

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 11. Table of address window registers
AddressRegisterAddressRegister

2000

CORE0_WIN0_BASE

2100

CORE1_WIN0_BASE

2008

CORE0_WIN1_BASE

2108

CORE1_WIN1_BASE

2010

CORE0_WIN2_BASE

2110

CORE1_WIN2_BASE

2018

CORE0_WIN3_BASE

2118

CORE1_WIN3_BASE

2020

CORE0_WIN4_BASE

2120

CORE1_WIN4_BASE

2028

CORE0_WIN5_BASE

2128

CORE1_WIN5_BASE

2030

CORE0_WIN6_BASE

2130

CORE1_WIN6_BASE

2038

CORE0_WIN7_BASE

2138

CORE1_WIN7_BASE

2040

CORE0_WIN0_MASK

2140

CORE1_WIN0_MASK

2048

CORE0_WIN1_MASK

2148

CORE1_WIN1_MASK

2050

CORE0_WIN2_MASK

2150

CORE1_WIN2_MASK

2058

CORE0_WIN3_MASK

2158

CORE1_WIN3_MASK

2060

CORE0_WIN4_MASK

2160

CORE1_WIN4_MASK

2068

CORE0_WIN5_MASK

2168

CORE1_WIN5_MASK

2070

CORE0_WIN6_MASK

2170

CORE1_WIN6_MASK

2078

CORE0_WIN7_MASK

2178

CORE1_WIN7_MASK

2080

CORE0_WIN0_MMAP

2180

CORE1_WIN0_MMAP

2088

CORE0_WIN1_MMAP

2188

CORE1_WIN1_MMAP

2090

CORE0_WIN2_MMAP

2190

CORE1_WIN2_MMAP

2098

CORE0_WIN3_MMAP

2198

CORE1_WIN3_MMAP

20a0

CORE0_WIN4_MMAP

21a0

CORE1_WIN4_MMAP

20a8

CORE0_WIN5_MMAP

21a8

CORE1_WIN5_MMAP

20b0

CORE0_WIN6_MMAP

21b0

CORE1_WIN6_MMAP

20b8

CORE0_WIN7_MMAP

21b8

CORE1_WIN7_MMAP

2200

CORE2_WIN0_BASE

2300

CORE3_WIN0_BASE

2208

CORE2_WIN1_BASE

2308

CORE3_WIN1_BASE

2210

CORE2_WIN2_BASE

2310

CORE3_WIN2_BASE

2218

CORE2_WIN3_BASE

2318

CORE3_WIN3_BASE

2220

CORE2_WIN4_BASE

2320

CORE3_WIN4_BASE

2228

CORE2_WIN5_BASE

2328

CORE3_WIN5_BASE

2230

CORE2_WIN6_BASE

2330

CORE3_WIN6_BASE

2238

CORE2_WIN7_BASE

2338

CORE3_WIN7_BASE

2240

CORE2_WIN0_MASK

2340

CORE3_WIN0_MASK

2248

CORE2_WIN1_MASK

2348

CORE3_WIN1_MASK

2250

CORE2_WIN2_MASK

2350

CORE3_WIN2_MASK

2258

CORE2_WIN3_MASK

2358

CORE3_WIN3_MASK

2260

CORE2_WIN4_MASK

2360

CORE3_WIN4_MASK

2268

CORE2_WIN5_MASK

2368

CORE3_WIN5_MASK

2270

CORE2_WIN6_MASK

2370

CORE3_WIN6_MASK

2278

CORE2_WIN7_MASK

2378

CORE3_WIN7_MASK

2280

CORE2_WIN0_MMAP

2380

CORE3_WIN0_MMAP

2288

CORE2_WIN1_MMAP

2388

CORE3_WIN1_MMAP

2290

CORE2_WIN2_MMAP

2390

CORE3_WIN2_MMAP

2298

CORE2_WIN3_MMAP

2398

CORE3_WIN3_MMAP

22a0

CORE2_WIN4_MMAP

23a0

CORE3_WIN4_MMAP

22a8

CORE2_WIN5_MMAP

23a8

CORE3_WIN5_MMAP

22b0

CORE2_WIN6_MMAP

23b0

CORE3_WIN6_MMAP

22b8

CORE2_WIN7_MMAP

23b8

CORE3_WIN7_MMAP

2400

SCACHE0_WIN0_BASE

2500

SCACHE1_WIN0_BASE

2408

SCACHE0_WIN1_BASE

2508

SCACHE1_WIN1_BASE

2410

SCACHE0_WIN2_BASE

2510

SCACHE1_WIN2_BASE

2418

SCACHE0_WIN3_BASE

2518

SCACHE1_WIN3_BASE

2420

SCACHE0_WIN4_BASE

2520

SCACHE1_WIN4_BASE

2428

SCACHE0_WIN5_BASE

2528

SCACHE1_WIN5_BASE

2430

SCACHE0_WIN6_BASE

2530

SCACHE1_WIN6_BASE

2438

SCACHE0_WIN7_BASE

2538

SCACHE1_WIN7_BASE

2440

SCACHE0_WIN0_MASK

2540

SCACHE1_WIN0_MASK

2448

SCACHE0_WIN1_MASK

2548

SCACHE1_WIN1_MASK

2450

SCACHE0_WIN2_MASK

2550

SCACHE1_WIN2_MASK

2458

SCACHE0_WIN3_MASK

2558

SCACHE1_WIN3_MASK

2460

SCACHE0_WIN4_MASK

2560

SCACHE1_WIN4_MASK

2468

SCACHE0_WIN5_MASK

2568

SCACHE1_WIN5_MASK

2470

SCACHE0_WIN6_MASK

2570

SCACHE1_WIN6_MASK

2478

SCACHE0_WIN7_MASK

2578

SCACHE1_WIN7_MASK

2480

SCACHE0_WIN0_MMAP

2580

SCACHE1_WIN0_MMAP

2488

SCACHE0_WIN1_MMAP

2588

SCACHE1_WIN1_MMAP

2490

SCACHE0_WIN2_MMAP

2590

SCACHE1_WIN2_MMAP

2498

SCACHE0_WIN3_MMAP

2598

SCACHE1_WIN3_MMAP

24a0

SCACHE0_WIN4_MMAP

25a0

SCACHE1_WIN4_MMAP

24a8

SCACHE0_WIN5_MMAP

25a8

SCACHE1_WIN5_MMAP

24b0

SCACHE0_WIN6_MMAP

25b0

SCACHE1_WIN6_MMAP

24b8

SCACHE0_WIN7_MMAP

25b8

SCACHE1_WIN7_MMAP

2600

SCACHE2_WIN0_BASE

2700

SCACHE3_WIN0_BASE

2608

SCACHE2_WIN1_BASE

2708

SCACHE3_WIN1_BASE

2610

SCACHE2_WIN2_BASE

2710

SCACHE3_WIN2_BASE

2618

SCACHE2_WIN3_BASE

2718

SCACHE3_WIN3_BASE

2620

SCACHE2_WIN4_BASE

2720

SCACHE3_WIN4_BASE

2628

SCACHE2_WIN5_BASE

2728

SCACHE3_WIN5_BASE

2630

SCACHE2_WIN6_BASE

2730

SCACHE3_WIN6_BASE

2638

SCACHE2_WIN7_BASE

2738

SCACHE3_WIN7_BASE

2640

SCACHE2_WIN0_MASK

2740

SCACHE3_WIN0_MASK

2648

SCACHE2_WIN1_MASK

2748

SCACHE3_WIN1_MASK

2650

SCACHE2_WIN2_MASK

2750

SCACHE3_WIN2_MASK

2658

SCACHE2_WIN3_MASK

2758

SCACHE3_WIN3_MASK

2660

SCACHE2_WIN4_MASK

2760

SCACHE3_WIN4_MASK

2668

SCACHE2_WIN5_MASK

2768

SCACHE3_WIN5_MASK

2670

SCACHE2_WIN6_MASK

2770

SCACHE3_WIN6_MASK

2678

SCACHE2_WIN7_MASK

2778

SCACHE3_WIN7_MASK

2680

SCACHE2_WIN0_MMAP

2780

SCACHE3_WIN0_MMAP

2688

SCACHE2_WIN1_MMAP

2788

SCACHE3_WIN1_MMAP

2690

SCACHE2_WIN2_MMAP

2790

SCACHE3_WIN2_MMAP

2698

SCACHE2_WIN3_MMAP

2798

SCACHE3_WIN3_MMAP

26a0

SCACHE2_WIN4_MMAP

27a0

SCACHE3_WIN4_MMAP

26a8

SCACHE2_WIN5_MMAP

27a8

SCACHE3_WIN5_MMAP

26b0

SCACHE2_WIN6_MMAP

27b0

SCACHE3_WIN6_MMAP

26b8

SCACHE2_WIN7_MMAP

27b8

SCACHE3_WIN7_MMAP

-

-

2900

IO_L2X_WIN0_BASE

-

-

2908

IO_L2X_WIN1_BASE

-

-

2910

IO_L2X_WIN2_BASE

-

-

2918

IO_L2X_WIN3_BASE

-

-

2920

IO_L2X_WIN4_BASE

-

-

2928

IO_L2X_WIN5_BASE

-

-

2930

IO_L2X_WIN6_BASE

-

-

2938

IO_L2X_WIN7_BASE

-

-

2940

IO_L2X_WIN0_MASK

-

-

2948

IO_L2X_WIN1_MASK

-

-

2950

IO_L2X_WIN2_MASK

-

-

2958

IO_L2X_WIN3_MASK

-

-

2960

IO_L2X_WIN4_MASK

-

-

2968

IO_L2X_WIN5_MASK

-

-

2970

IO_L2X_WIN6_MASK

-

-

2978

IO_L2X_WIN7_MASK

-

-

2980

IO_L2X_WIN0_MMAP

-

-

2988

IO_L2X_WIN1_MMAP

-

-

2990

IO_L2X_WIN2_MMAP

-

-

2998

IO_L2X_WIN3_MMAP

-

-

29a0

IO_L2X_WIN4_MMAP

-

-

29a8

IO_L2X_WIN5_MMAP

-

-

29b0

IO_L2X_WIN6_MMAP

-

-

29b8

IO_L2X_WIN7_MMAP

2a00

HT0_LO_WIN0_BASE

2b00

HT0_HI_WIN0_BASE

2a08

HT0_LO_WIN1_BASE

2b08

HT0_HI_WIN1_BASE

2a10

HT0_LO_WIN2_BASE

2b10

HT0_HI_WIN2_BASE

2a18

HT0_LO_WIN3_BASE

2b18

HT0_HI_WIN3_BASE

2a20

HT0_LO_WIN4_BASE

2b20

HT0_HI_WIN4_BASE

2a28

HT0_LO_WIN5_BASE

2b28

HT0_HI_WIN5_BASE

2a30

HT0_LO_WIN6_BASE

2b30

HT0_HI_WIN6_BASE

2a38

HT0_LO_WIN7_BASE

2b38

HT0_HI_WIN7_BASE

2a40

HT0_LO_WIN0_MASK

2b40

HT0_HI_WIN0_MASK

2a48

HT0_LO_WIN1_MASK

2b48

HT0_HI_WIN1_MASK

2a50

HT0_LO_WIN2_MASK

2b50

HT0_HI_WIN2_MASK

2a58

HT0_LO_WIN3_MASK

2b58

HT0_HI_WIN3_MASK

2a60

HT0_LO_WIN4_MASK

2b60

HT0_HI_WIN4_MASK

2a68

HT0_LO_WIN5_MASK

2b68

HT0_HI_WIN5_MASK

2a70

HT0_LO_WIN6_MASK

2b70

HT0_HI_WIN6_MASK

2a78

HT0_LO_WIN7_MASK

2b78

HT0_HI_WIN7_MASK

2a80

HT0_LO_WIN0_MMAP

2b80

HT0_HI_WIN0_MMAP

2a88

HT0_LO_WIN1_MMAP

2b88

HT0_HI_WIN1_MMAP

2a90

HT0_LO_WIN2_MMAP

2b90

HT0_HI_WIN2_MMAP

2a98

HT0_LO_WIN3_MMAP

2b98

HT0_HI_WIN3_MMAP

2aa0

HT0_LO_WIN4_MMAP

2ba0

HT0_HI_WIN4_MMAP

2aa8

HT0_LO_WIN5_MMAP

2ba8

HT0_HI_WIN5_MMAP

2ab0

HT0_LO_WIN6_MMAP

2bb0

HT0_HI_WIN6_MMAP

2ab8

HT0_LO_WIN7_MMAP

2bb8

HT0_HI_WIN7_MMAP

2c00

SE_WIN0_BASE

2d00

MISC_WIN0_BASE

2c08

SE_WIN1_BASE

2d08

MISC_WIN1_BASE

2c10

SE_WIN2_BASE

2d10

MISC_WIN2_BASE

2c18

SE_WIN3_BASE

2d18

MISC_WIN3_BASE

2c20

SE_WIN4_BASE

2d20

MISC_WIN4_BASE

2c28

SE_WIN5_BASE

2d28

MISC_WIN5_BASE

2c30

SE_WIN6_BASE

2d30

MISC_WIN6_BASE

2c38

SE_WIN7_BASE

2d38

MISC_WIN7_BASE

2c40

SE_WIN0_MASK

2d40

MISC_WIN0_MASK

2c48

SE_WIN1_MASK

2d48

MISC_WIN1_MASK

2c50

SE_WIN2_MASK

2d50

MISC_WIN2_MASK

2c58

SE_WIN3_MASK

2d58

MISC_WIN3_MASK

2c60

SE_WIN4_MASK

2d60

MISC_WIN4_MASK

2c68

SE_WIN5_MASK

2d68

MISC_WIN5_MASK

2c70

SE_WIN6_MASK

2d70

MISC_WIN6_MASK

2c78

SE_WIN7_MASK

2d78

MISC_WIN7_MASK

2c80

SE_WIN0_MMAP

2d80

MISC_WIN0_MMAP

2c88

SE_WIN1_MMAP

2d88

MISC_WIN1_MMAP

2c90

SE_WIN2_MMAP

2d90

MISC_WIN2_MMAP

2c98

SE_WIN3_MMAP

2d98

MISC_WIN3_MMAP

2ca0

SE_WIN4_MMAP

2da0

MISC_WIN4_MMAP

2ca8

SE_WIN5_MMAP

2da8

MISC_WIN5_MMAP

2cb0

SE_WIN6_MMAP

2db0

MISC_WIN6_MMAP

2cb8

SE_WIN7_MMAP

2db8

MISC_WIN7_MMAP

2e00

HT1_LO_WIN0_BASE

2f00

HT1_HI_WIN0_BASE

2e08

HT1_LO_WIN1_BASE

2f08

HT1_HI_WIN1_BASE

2e10

HT1_LO_WIN2_BASE

2f10

HT1_HI_WIN2_BASE

2e18

HT1_LO_WIN3_BASE

2f18

HT1_HI_WIN3_BASE

2e20

HT1_LO_WIN4_BASE

2f20

HT1_HI_WIN4_BASE

2e28

HT1_LO_WIN5_BASE

2f28

HT1_HI_WIN5_BASE

2e30

HT1_LO_WIN6_BASE

2f30

HT1_HI_WIN6_BASE

2e38

HT1_LO_WIN7_BASE

2f38

HT1_HI_WIN7_BASE

2e40

HT1_LO_WIN0_MASK

2f40

HT1_HI_WIN0_MASK

2e48

HT1_LO_WIN1_MASK

2f48

HT1_HI_WIN1_MASK

2e50

HT1_LO_WIN2_MASK

2f50

HT1_HI_WIN2_MASK

2e58

HT1_LO_WIN3_MASK

2f58

HT1_HI_WIN3_MASK

2e60

HT1_LO_WIN4_MASK

2f60

HT1_HI_WIN4_MASK

2e68

HT1_LO_WIN5_MASK

2f68

HT1_HI_WIN5_MASK

2e70

HT1_LO_WIN6_MASK

2f70

HT1_HI_WIN6_MASK

2e78

HT1_LO_WIN7_MASK

2f78

HT1_HI_WIN7_MASK

2e80

HT1_LO_WIN0_MMAP

2f80

HT1_HI_WIN0_MMAP

2e88

HT1_LO_WIN1_MMAP

2f88

HT1_HI_WIN1_MMAP

2e90

HT1_LO_WIN2_MMAP

2f90

HT1_HI_WIN2_MMAP

2e98

HT1_LO_WIN3_MMAP

2f98

HT1_HI_WIN3_MMAP

2ea0

HT1_LO_WIN4_MMAP

2fa0

HT1_HI_WIN4_MMAP

2ea8

HT1_LO_WIN5_MMAP

2fa8

HT1_HI_WIN5_MMAP

2eb0

HT1_LO_WIN6_MMAP

2fb0

HT1_HI_WIN6_MMAP

2eb8

HT1_LO_WIN7_MMAP

2fb8

HT1_HI_WIN7_MMAP

+
+

The secondary xbar mainly connects 2 memory controllers and IO-RING as slave devices, with 4 SCache (4, representing 4xxx, same as 5, 6, 7) and IO-RING (9) as master devices for window mapping, which can use these window configuration registers (4, 5, 6, 7, 9) for memory window configuration and address translation.

+
+
+

Each address window consists of three 64-bit registers, BASE, MASK, and MMAP, with BASE aligned in K bytes, MASK in a format similar to the network mask high bit 1, and MMAP containing the converted address, routing, and enable control bits, as shown in the following table:

+
+ + ++++++ + + + + + + + + + + + + + + + + +
Table 12. Description of MMAP register bit field
[63:48][47:10][7:4][3:0]

Reserved

Address after translation

Window enable

Slave device number

+
+

Among them, the devices corresponding to the slave device number are shown in the following table:

+
+ + ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 13. Correspondence from the device number to the module it belongs to
Slave Device NumberDestination Device

0-3

Scache0-3

4-5

MC0-1

a

HT0_lo

b

HT0_hi

c

SE

d

MISC

e

HT1_lo

f

HT1_hi

+
+

The meaning of the window enable bits is shown in the table below:

+
+ + ++++++ + + + + + + + + + + + + + + + + +
Table 14. Space access attributes corresponding to MMAP
[7][6][5][4]

Window enable

Allow interleaved access to DDR. +Valid when the slave device number is 0, to route requests for hit window addresses as configured by the interleave_bit (CSR0x0400). +The interleave enable bit is required to be greater than 10

Allow to read blocks

Allow to fetch instructions

+
+

Note that the window configuration cannot perform address translation for Cache consistency requests, otherwise the address at the SCache will not match the address at the processor-level Cache, resulting in a Cache consistency maintenance error.

+
+
+

Window hit formula: (IN_ADDR & MASK) == BASE

+
+
+

New address conversion formula: OUT_ADDR = (IN_ADDR & ~MASK) | {MMAP[63:10], 10’h0}

+
+
+

According to the default register configuration, the CPU’s address range of 0x00000000-0x0fffffff after the chip is booted (256M) mapped to the address interval 0x00000000-0x0fffffff of the DDR. +0x10000000-0x17ffffff are mapped to the PCI_MEM space of the bridge chip. +0x18000000-0x19ffffff are mapped to the PCI_IO space of the bridge chip. +0x1a000000-0x1affffff are mapped to the bridge chip’s PCI configuration space (Type0). +0x1b000000-0x1bffffff are mapped to the bridge chip’s PCI configuration space (Type1). +0x40000000-0x7fffffff are mapped to the bridge chip’s PCI_MEM space. +Software can implement the new address space routing and translation by modifying the corresponding configuration registers.

+
+
+

In addition, when there is a read access to an illegal address due to CPU guessing execution, all 8 address windows are not hit and random data is returned to prevent the CPU from dying, etc.

+
+
+
+
+
+

4. Chip Configuration Register

+
+
+

The chip configuration registers in the Loongson3A5000 provide a mechanism for reading and writing configuration of various functions of the chip. The individual configuration registers are described in detail below.

+
+
+

The base address of each chip configuration register in this chapter is 0x1fe00000, which can also be accessed using the configuration register instruction (IOCSR).

+
+
+

CSR[A][B] in this document indicates bit B in the IOCSR register with offset address A, where B can be a range.

+
+
+

4.1. Version Register (0x0000)

+
+

The offset address is 0x0000.

+
+ + +++++++ + + + + + + + + + + + + + + + + + + +
Table 15. Version register
Bit FieldNameRead/WriteReset ValueDescription

7:0

Version

R

8’h11

Configuration register version number

+
+
+

4.2. Chip Characteristics Register (0x0008)

+
+

This register identifies a number of software-related processor features for software to view before enabling a specific function. +The offset address is 0x0008.

+
+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 16. Chip characteristics register
Bit FieldNameRead/WriteReset ValueDescription

0

Centigrade

R

1’b1

1 indicates that CSR[0x428] is valid

1

Node counter

R

1’b1

1 indicates that CSR[0x408] is valid

2

MSI

R

1’b1

1 indicates that MSI is available

3

EXT_IOI

R

1’b1

1 indicates that EXT_IOI is available

4

IPI_percore

R

1’b1

1 indicates that IPI is sent via VSR private address

5

Freq_percore

R

1’b1

1 indicates that frequency is modulated via VSR private address

6

Freq_scale

R

1’b1

1 indicates that dynamic frequency division is available

7

DVFS_v1

R

1’b1

1 indicates that dynamic frequency adjustment v1 is available

8

Tsensor

R

1’b1

1 indicates that temperature sensor is available

9

Interrupt decoding

R

1’b1

Interrupt pin decoding mode is available

10

Flat Mode

R

1’b0

Legacy compatibility mode

11

Guest Mode

WR

1’b0

KVM Virtual Machine Mode

+
+
+

4.3. Manufacturer Name Register (0x0010)

+
+

This register is used to identify the vendor name. +The offset address is 0x0010.

+
+ + +++++++ + + + + + + + + + + + + + + + + + + +
Table 17. Manufacturer name register
Bit FieldNameRead/WriteReset ValueDescription

63:0

Vendor

R

0x6e6f7367_6e6f6f4c

string “Loongson”

+
+
+

4.4. Chip Name Register (0x0020)

+
+

This register is used to identify the chip name. +The offset address is 0x0020.

+
+ + +++++++ + + + + + + + + + + + + + + + + + + +
Table 18. Chip name register
Bit FieldNameRead/WriteReset ValueDescription

63:0

ID

R

0x00003030_30354133

String “3A5000”

+
+
+

4.5. Function configuration Register (0x0180)

+
+

The offset address is 0x0180.

+
+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 19. Function configuration register
Bit FieldNameRead/WriteReset ValueDescription

0

RW

1’b0

1

RW

1’b0

3:2

RW

2’b0

Reserved

4

MC0_disable_confspace

RW

1’b0

Whether to disable MC0 DDR configuration space

5

MC0_defult_confspace

RW

1’b1

Routing all memory accesses to the configuration space

6

MCA0 clock en

RW

1’b1

MCA0 clock enable

7

MC0_resetn

RW

1’b1

MC0 software reset (active low)

8

MC0_clken

RW

1’b1

Whether to enable MC0

9

MC1_disable_confspace

RW

1’b0

Whether to disable MC1 DDR configuration space

10

MC1_defult_confspace

RW

1’b1

Routing all memory accesses to the configuration space

11

MCA1 clock en

RW

1’b1

MCA1 clock enable

12

MC1_resetn

RW

1’b1

MC1 software reset (active low)

13

MC1_clken

RW

1’b1

Whether to enable MC1

26:24

HT0_freq_scale_ctrl

RW

3’b011

HT Controller 0 frequency division

27

HT0_clken

RW

1’b1

Whether to enable HT0

30:28

HT1_freq_scale_ctrl

RW

3’b011

HT Controller 1 frequency division

31

HT1_clken

RW

1’b1

Whether to enable HT1

42:40

Node_freq_ctrl

RW

3’b111

Node Frequency Division

43

-

RW

1’b1

63:56

Cpu_version

R

2’h3D

CPU version

+
+
+

4.6. Pin Controller Driver Configuration Register (0x0188)

+
+

The offset address is 0x0188.

+
+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 20. Pin controller driver configuration register
Bit FieldNameRead/WriteReset ValueDescription

15:0

19:16

HT sideband

RW

2’b0

HT control signal driver configuration

23:20

I2C

RW

2’b0

I2C control signal driver configuration

27:24

UART

RW

2’b0

UART control signal driver configuration

31:28

SPI

RW

2’b0

SPI control signal driver configuration

35:32

GPIO

RW

2’b0

GPIO control signal driver configuration

39:36

SE UART

RW

2’b0

SE UART control signal driver configuration

43:40

SE SPI

RW

2’b0

SE SPI control signal driver configuration

47:44

SE I2C

RW

2’b0

SE I2C control signal driver configuration

51:48

SE SCI

RW

2’b0

SE SCI control signal driver configuration

55:52

SE RNG

RW

2’b0

SE RNG control signal driver configuration

59:56

SE GPIO

RW

2’b0

SE GPIO control signal driver configuration

+
+
+

4.7. Function Collection Register (0x0190)

+
+

The offset address is 0x0190.

+
+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 21. Function collection register
Bit FieldNameRead/WriteReset ValueDescription

31:0

R

Reserved

37:32

Chip_config

R

Motherboard configuration control

47:38

Sys_clkseli

R

On-board frequency multiplier configuration

55:48

Bad_ip_core

R

core7-core0 are bad or not

57:56

Bad_ip_ddr

R

2 DDR controllers are bad or not

61:60

Bad_ip_ht

R

2 HT Controllers are bad or not

+
+
+

4.8. Temperature Collection Register (0x0198)

+
+

The offset address is 0x0198.

+
+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 22. Temperature collection register
Bit FieldNameRead/WriteReset ValueDescription

15:0

R

Reserved

19:16

R

Reserved

20

dotest

R

Dotest pin status

21

iccc_en

R

Iccc_en pin status

23:22

R

Reserved

24

Thsens0_overflow

R

Temperature sensor 0 overflow

25

Thsens1_overflow

R

Temperature sensor 1 overflow

31:26

47:32

Thsens0_out

R

Temperature sensor 0 centigrade temperature

+

Node temperature=Thens0_out *731/0x4000-273

+

Temperature range: -40 degree - 125 degree

63:48

Thsens1_out

R

Temperature sensor 1 centigrade temperature

+

Node temperature=Thens0_out *731/0x4000-273

+

Temperature range: -40 degree - 125 degree

+
+
+

4.9. Frequency Configuration Register (0x01B0)

+
+

The following sets of software multiplier setting registers are used to set the operating frequency of the chip master clock and the memory controller clock when CLKSEL is configured in software control mode (refer to the CLKSEL setting method in Descriptions of Pins).

+
+
+

Among other things, the MEM CLOCK configuration supports multiple modes. +In 4x mode (mem div), MEM CLOCK should be 4x the memory controller clock; in 2x mode (mem div), MEM CLOCK should be 2x the memory controller clock; in 1x mode (mem div), MEM CLOCK should be the memory controller clock frequency .

+
+
+

The memory bus operates at 2 times the memory controller clock and the bus operates at 4 times the memory controller clock.

+
+
+

NODE CLOCK corresponds to the clock frequency of the processor core, on-chip network, and shared Cache.

+
+
+

Each clock configuration generally has three parameters, DIV_REFC, DIV_LOOPC, and DIV_OUT. +The final clock frequency is (reference clock / DIV_REFC * DIV_LOOPC) / DIV_OUT.

+
+
+

In software control mode, the default corresponding clock frequency is the frequency of the external reference clock (100MHz or 25MHz), which needs to be set in software during the processor startup. +The process of setting the individual clocks should be done as follows:

+
+
+
    +
  1. +

    Set registers other than SEL_PLL_* and SOFT_SET_PLL, i.e., these two registers are written to 0 during the setting process.

    +
    2. +
  2. +

    Set registers other than SEL_PLL_* and SOFT_SET_PLL, i.e., these two registers are written to 0 during the setting process.

    +
    3. +
+
+
+
Wait for the lock signal LOCKED_* in the register to be 1.
+
    +
  1. +

    Set SEL_PLL_* to 1, then the corresponding clock frequency will be switched to the software-set frequency.

    +
    2. +
+
+
+

The following register is the configuration register of Main CLOCK, Main Clock is used to generate the maximum operating frequency of node clock, core clock, etc. +The base address is 0x1fe00000 and the offset address is 0x1b0:

+
+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 23. Node clock software multiplier configuration register
Bit FieldNameRead/WriteReset ValueDescription

0

SEL_PLL_NODE

RW

0x0

Clock output selection

+

1: Node clock select PLL output

+

0: Node clock select SYS CLOCK

1

RW

0x0

Reserved

2

SOFT_SET_PLL

RW

0x0

Allow software to set the PLL

3

BYPASS_L1

RW

0x0

Bypass L1 PLL

7:4

-

RW

0x0

Reserved

8

VDDA_LDO_EN

RW

0x0

Enable VDDA LDO

9

VDDD_LDO_EN

RW

0x0

Enable VDDD LDO

11:10

-

12

DACPD_L2

RW

0x0

L2 clock DACPD

13

DSMPD_L2

RW

0x0

L2 clock DSMPD

15:14

RW

0x0

Reserved

16

LOCKED_L1

R

0x0

L1 PLL is locked or not

18:17

-

R

0x0

Reserved

19

PD_L1

RW

0x0

Disable L1 PLL

21:20

RW

0x0

Reserved

22

L2_SEL

RW

0x0

Select L2 clock output

25:23

RW

0x0

Reserved

31:26

L1_DIV_REFC

RW

0x1

L1 PLL input parameters

40:32

L1_DIV_LOOPC

RW

0x1

L1 PLL input parameters

41

Reserved

47:42

L1_DIV_OUT

RW

0x1

L1 PLL input parameters

53:48

L2_DIV_REFC

RW

63:54

L2_DIV_LOOPC

RW

69:64

L2_DIV_OUT

RW

95:70

-

RW

119:96

L2_FRAC

RW

122:120

VDDA_LDO_CTRL

RW

123

VDDA_LDO_BYPASS

RW

126:124

VDDD_LDO_CTRL

RW

127:124

VDDD_LDO_BYPASS

RW

Other

-

RW

Reserved

+
+

Note: PLL ouput = (clk_ref /div_refc * div_loopc) / div_out.

+
+
+

The result of clk_ref/div_refc for the PLL should be 25/50/100MHz, with 50MHz recommended. +The VCO frequency (the part in parentheses in the above equation) must be in the range 4.8GHz-6.4GHz. +This requirement also applies to memory PLLs.

+
+
+

In addition, the recommended setting for div_loopc is less than 255. +The recommended setting for div_out is 1/2/4/6 and above 6, and 3/5 is not recommended.

+
+
+

The following register is the MEM CLOCK configuration register, the MEM CLOCK clock frequency should be configured to 1/2 of the final DDR bus clock frequency. +The base address is 0x1fe00000, offset address is 0x1c0:

+
+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 24. Memory clock software multiplier configuration register
Bit FieldNameRead/WriteReset ValueDescription

[0]

SEL_MEM_PLL

RW

0x0

Clock output selection

+

1: Node clock select PLL output

+

0: Node clock select SYS CLOCK

[1]

SOFT_SET_MEM_PLL

RW

0x0

Allow software to set MEM PLL

[2]

BYPASS_MEM_PLL

RW

0x0

Bypass MEM_PLL

[3]

MEMDIV_RESETn

RW

0x1

Reset the internal frequency divider

[5:4]

MEMDIV_MODE

RW

00: 1X frequency multiplier mode

+

01: 2X frequency multiplier mode

+

10: 4X frequency multiplier mode

+

11: Reserved

[6]

LOCKED_MEM_PLL

R

0x0

MEM_PLL is locked or not

[7]

PD_MEM_PLL

RW

0x0

Disable MEM PLL

[13:8]

MEM_PLL_DIV_REFC

RW

0x1

MEM PLL input parameters

+

When the NODE clock is selected (NODE_CLOCK_SEL is 1), it is used as a frequency divider input

[23:14]

MEM_PLL_DIV_LOOPC

RW

0x41

MEM PLL input parameters

[29:24]

MEM_PLL_DIV_OUT

RW

0x0

MEM PLL input parameters

[30]

NODE_CLOCK_SEL

RW

0x0

0: use MEM_PLL as MEM clock

+

1: use NODE_CLOCK as a frequency divider input

[31]

-

[34:32]

VDDA_LDO_CTRL

RW

[35]

VDDA_LDO_BYPASS

RW

[38:36]

VDDD_LDO_CTRL

RW

[39]

VDDD_LDO_BYPASS

RW

[40]

VDDA_LDO_EN

[41]

VDDD_LDO_EN

RW

Other

RW

Reserved

+
+
+

4.10. Processor Core Frequency Division Configuration Register (0x01D0)

+
+

The following registers are used for dynamic frequency division of the processor core. +Using this register to set the frequency of the processor core, the frequency conversion operation can be done within 100ns with no additional overhead. +The base address is 0x1fe00000 and the offset address is 0x01d0.

+
+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 25. Processor core software frequency division configuration
Bit FieldNameRead/WriteReset ValueDescription

2:0

core0_freqctrl

RW

0x7

Core 0 frequency division control value

3

core0_en

RW

0x1

Core 0 clock enable

6:4

core1_freqctrl

RW

0x7

Core 1 frequency division control value

7

core1_en

RW

0x1

Core 1 clock enable

10:8

core2_freqctrl

RW

0x7

Core 2 frequency division control value

11

core2_en

RW

0x1

Core 2 clock enable

14:12

core3_freqctrl

RW

0x7

Core 3 frequency division control value

15

core3_en

RW

0x1

Core 3 clock enable

+
+

Note: The clock frequency value after software dividing is equal to the original (dividing control value + 1)/8.

+
+
+
+

4.11. Processor Core Reset Control Register (0x01D8)

+
+

The following registers are used for software-controlled reset of the processor core. +To reset, set resetn to 0, resetn_pre to 0, wait 500 microseconds, resetn_pre to 1, and reset n to 1 to complete the reset process. +The base address of this register is 0x1fe00000 and the offset address is 0x01d8.

+
+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 26. Processor core software reset control register
Bit FieldNameRead/WriteReset ValueDescription

0

Core0_resetn_pre

RW

0x1

Core 0 reset auxiliary control

1

Core0_resetn

RW

0x1

Core 0 reset

2

Core1_resetn_pre

RW

0x1

Core 1 reset auxiliary control

3

Core1_resetn

RW

0x1

Core 1 reset

4

Core2_resetn_pre

RW

0x1

Core 2 reset auxiliary control

5

Core2_resetn

RW

0x1

Core 2 reset

6

Core3_resetn_pre

RW

0x1

Core 3 reset auxiliary control

7

Core3_resetn

RW

0x1

Core 3 reset

+
+
+

4.12. Routing Configuration Register (0x0400)

+
+

The following registers are used to control some of the routing settings within the chip. +The base address is 0x1fe00000 and the offset address is 0x0400.

+
+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 27. Chip routing configuration register
Bit FieldNameRead/WriteReset ValueDescription

3:0

scid_sel

RW

0x0

Shared Cache hash bit control

7:4

Node_mask

RW

0xF

Node mask to avoid no response when guessing the address of an unused node

8

xrouter_en

RW

0x0

HT1 inter-chip routing enable control

9

disable_0x3ff0

RW

0x0

Disable routing via base address 0x3ff0_0000 of configuration register space

10

Fast_path_36_en

RW

0x0

Enable 36 fast paths (8-way)

11

Fast_path_27_en

RW

0x0

Enable 27 fast paths (8-way)

12

mcc_en

RW

0x0

MCC mode enable

14

Scahe_1MB

RW

SCache capacity cut in half

19:16

ccsd_id

RW

0x0

24

ccsd_en

RW

0x0

31:30

mc_en

RW

0x3

Enable routing control for both MCs

37:32

interleave_bit

RW

0x0

Memory hash control

39

interleave_en

RW

0x0

Memory hash enable

43:40

ht_control

R

Ht-related configuration pins

47:44

ht_reg_disable

RW

0x0

Close ht space for consistency mode to avoid routing HT space addresses to HT

60:56

Line_ag_cfg

RW

0x0

Cross-chip bandwidth balancing configuration

+
+
+

4.13. Other Function Configuration Register (0x0420)

+
+

The following registers are used to control some of the functions enabled within the chip. +The base address is 0x1fe00000 and the offset address is 0x0420.

+
+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 28. Other function configuration register
Bit FieldNameRead/WriteReset ValueDescription

0

disable_jtag

RW

0x0

Completely disable the JTAG interface

1

disable_jtag_LA464

RW

0x0

Completely disable the LA464JTAG debug interface

2

disable_LA132

RW

0x0

Completely disable LA132

3

disable_jtag_LA132

RW

0x0

Completely disable the LA132 JTAG debug interface

4

Disable_antifuse0

RW

0x0

Disable fuse

5

Disable_antifuse1

RW

0x0

Disable fuse

6

Disable_ID

RW

0x0

Disable ID modification

7

Reserved

8

resetn_LA132

RW

0x0

LA132 reset control

9

sleeping_LA132

R

0x0

LA132 go to sleep

10

soft_int_LA132

RW

0x0

LA132 inter-processor interrupt register

15:12

core_int_en_LA132

RW

0x0

LA132 I/O interrupt enable for each core

18:16

freqscale_LA132

RW

0x0

LA132 frequency division control

19

clken_LA132

RW

0x0

LA132 clock enable

20

stable_sel

RW

0x0

Stable clock selection

+

0: SYS CLOCK

+

1: NODE CLOCK

21

stable_resetn

RW

0x0

Stable clock reset control

22

freqscale_percore

RW

0x0

Enable private frequency adjustment registers for each core

23

clken_percore

RW

0x0

Enable private clock for each core

27:24

confbus_timeout

RW

0x8

Configure the bus timeout configuration. +The actual time is the power of 2.

29:28

HT_softresetn

RW

0x3

HT Controller software reset control

35:32

freqscale_mode_core

RW

0x0

Frequency adjustment mode selection for each core

+

0: (n+1)/8

+

1: 1/(n+1)

36

freqscale_mode_node

RW

0x0

Frequency adjustment mode selection for nodes

+

0: (n+1)/8

+

1: 1/(n+1)

37

freqscale_mode_LA132

RW

0x0

Frequency adjustment mode selection for LA132

+

0: (n+1)/8

+

1: 1/(n+1)

39:38

freqscale_mode_HT

RW

0x0

Frequency adjustment mode selection for each HT

+

0: (n+1)/8

+

1: 1/(n+1)

40

freqscale_mode_stable

RW

0x0

Frequency adjustment mode selection for stable clock

+

0: (n+1)/8

+

1: 1/(n+1)

43:41

Reserved

46:44

freqscale_stable

RW

0x0

Stable clock frequency adjustment register

47

clken_stable

RW

0x0

Stable clock enable

48

EXT_INT_en

RW

0x0

Extended I/O interrupt enable

49

INT_encode

RW

0x0

Enable interrupt pin encode mode

53:52

54

57:56

thsensor_sel

RW

0x0

Temperature sensor selection

62:60

Auto_scale

R

0x0

Current value auto frequency adjustment

63

Auto_scale_doing

R

0x0

Flags in effect auto frequency adjustment

+
+
+

4.14. Centigrade Temperature Register (0x0428)

+
+

The following registers are used to observe the chip internal temperature sensor values. In degrees Celsius. +The base address is 0x1fe00000 and the offset address is 0x0428. +This register is available only when CSR[0x0008][0] is valid.

+
+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 29. Temperature observation register
Bit FieldNameRead/WriteReset ValueDescription

7:0

Centigrade temperature

RO

0x0

Centigrade temperature

63:8

RW

0x0

+
+
+

4.15. SRAM Adjustment Register (0x0430)

+
+

The following registers are used to adjust the operating frequency of Sram inside the processor core. +The offset address is 0x0430.

+
+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 30. Processor core SRAM adjustment register
Bit FieldNameRead/WriteReset ValueDescription

31:0

sram_ctrl

RW

0x0

Inter-processor sram configuration register

63:32

RW

0x0

+
+
+

4.16. FUSE0 Observation Register (0x0460)

+
+

The following registers are used to observe the Fuse0 values visible to some software. +The offset address is 0x0460.

+
+ + +++++++ + + + + + + + + + + + + + + + + + + +
Table 31. FUSE0 observation register
Bit FieldNameRead/WriteReset ValueDescription

127:0

Fuse_0

RW

0x0

+
+
+

4.17. FUSE1 Observation Register (0x0470)

+
+

The following registers are used to observe the Fuse1 values visible to some software. +The offset address is 0x0470.

+
+ + +++++++ + + + + + + + + + + + + + + + + + + +
Table 32. FUSE1 observation register
Bit FieldNameRead/WriteReset ValueDescription

127:0

Fuse_1

RW

0x0

+
+
+
+
+

5. Chip Clock Division and Enable Control

+
+
+

The Loongson 3A5000 can use a single external reference clock, SYS_CLOCK. +The generation of each clock can depend on SYS_CLOCK, and the following sections describe each of these clocks.

+
+
+

The Loongson 3A5000 has separate frequency dividing mechanisms for the processor core, on-chip network and shared Cache, HT controller, and LA132 core. +In line with the 3A4000, the 3A5000 also supports 1/n divider values,It can also be accessed using the configuration register instruction (IOCSR).

+
+
+

The base address of each chip configuration register in this chapter is 0x1fe00000.

+
+
+

5.1. Introduction to Chip Module clock

+
+

The chip reference clock SYS_CLOCK usually uses a 100MHz crystal input, but a 25MHz crystal input is also available. +Different crystal frequencies need to be selected via CLKSEL[4].

+
+
+

The reference clock of the HT PHY can use the 200MHz differential reference input of each PHY in addition to the SYS CLOCK. +Use CLKSEL[8] to make the selection. +When SYS CLOCK is selected as the reference clock and a 25MHz crystal input is used, the HT PHY cannot operate at 3.2GHz.

+
+
+

The clocks used in the Loongson 3A5000 chip and their control methods are shown in the following table.

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 33. Processor internal clock description
ClockClock SourceFrequency Multiplier MethodFrequency Division ControlEnable ControlClock Description

Boot clock

SYS_CLOCK

*1

Not supported

Not supported

SPI, UART, I2C controller clock

Main clock

SYS PLL

PLL configuration

Not supported

Not supported

SYS PLL output

+

Node clock, core clock, HTcore clock, LA132 clock source

+

Optional mem clock, stable clock source

Node clock

Main clock

*1

Supported

Not supported

On-chip network, shared Cache, node clock, HT controller clock source

Core0 clock

Main clock

*1

Supported

Supported

Core0 clock

Core1 clock

Main clock

*1

Supported

Supported

Core1 clock

Core2 clock

Main clock

*1

Supported

Supported

Core2 clock

Core3 clock

Main clock

*1

Supported

Supported

Core3 clock

HTcore0 clock

Node clock

*1

Supported

Supported

HT0 controller clock, and software needs to be guaranteed to be below 1GHz after frequency division

HTcore1 clock

Node clock

*1

Supported

Supported

HT1 controller clock, and software needs to be guaranteed to be below 1GHz after frequency division

LA132 clock

Main clock

*1

Supported

Supported

LA132 clock, and software needs to be guaranteed to be below 1GHz after frequency division

Stable clock

SYS_CLOCK

*1

Supported

Supported

Processor core constant counter clock

Mem clock

MEM PLL

PLL configuration

Not supported

Supported

Memory controller clock

Main clock

/2, /4, /8

Not supported

Supported

Memory controller alternative clock

+
+
+

5.2. Processor Core Frequency Division and Enable Control

+
+

There are various modes of processor core frequency division, one is per-address access mode, and the other is processor configuration instruction access mode, which are described below. +Each processor core can be controlled separately.

+
+
+

5.2.1. Accessing by Address

+
+

The per-address access mode is compatible with the 3A3000 processor and uses the processor core software frequency divider setup register, which uses the same address for setup.

+
+
+

Using this register to set the processor core for tuning allows the frequency conversion operation to be completed in 100ns with no other additional overhead. +The base address is 0x1fe00000,It can also be accessed using the configuration register instruction (IOCSR),and the offset address is 0x01d0.

+
+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 34. Processor core software frequency division configuration
Bit FieldNameRead/WriteReset ValueDescription

2:0

core0_freqctrl

RW

0x7

Core 0 frequency division control value

3

core0_en

RW

0x1

Core 0 clock enable

6:4

core1_freqctrl

RW

0x7

Core 1 frequency division control value

7

core1_en

RW

0x1

Core 1 clock enable

10:8

core2_freqctrl

RW

0x7

Core 2 frequency division control value

11

core2_en

RW

0x1

Core 2 clock enable

14:12

core3_freqctrl

RW

0x7

Core 3 frequency division control value

15

core3_en

RW

0x1

Core 3 clock enable

+
+

Note: The clock frequency value after software dividing is equal to the original (dividing control value + 1)/8.

+
+
+

In addition to the frequency division configuration compatible with the 3A3000 processor, the clock frequency after frequency division can be adjusted from (Frequency Division Control Value + 1)/8 to 1/(Frequency Division Control Value + 1)` by setting the register in the 3A5000. +This register is located in other function configuration register. +The base address is 0x1fe00000,It can also be accessed using the configuration register instruction (IOCSR),and the offset address is 0x0420.

+
+ + +++++++ + + + + + + + + + + + + + + + + + + +
Table 35. Other function configuration register
Bit FieldNameRead/WriteReset ValueDescription

35:32

freqscale_mode_core

RW

0x0

Frequency adjustment mode selection for each core

+

0: (n+1)/8

+

1: 1/(n+1)

+
+
+

5.2.2. Accessing by Configuration Register Instructions

+
+

In addition to the legacy per-address access mode, the 3A5000 also supports access to private frequency division configuration registers using the configuration register instruction.

+
+
+

Note that the private frequency division configuration register control is mutually exclusive with the original processor core software frequency division setup register control, and only one of the two can be used. +The choice is made by using the corresponding bit on the other function configuration register. +This register has a base address of 0x1fe00000,It can also be accessed using the configuration register instruction (IOCSR), and an offset address of 0x0420.

+
+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 36. Other function configuration register
Bit FieldNameRead/WriteReset ValueDescription

22

freqscale_percore

RW

0x0

Enable private frequency adjustment registers for each core

23

clken_percore

RW

0x0

Enable private clock for each core

+
+

When freqscale_percore is set to 1, the freqscale bit in the private divider configuration register is used to set the divider for its own clock (including freqscale_mode). +When freqscale_percore is set to 1, the clken_mode bit in the private frequency division configuration register is used to set the clock enable. +Bit in the private frequency division configuration register is used to control the clock enable when clken_percore is set to 1.

+
+
+

This configuration register is defined as follows. +The offset address is 0x1050.

+
+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 37. Processor core private frequency division register
Bit FieldNameRead/WriteReset ValueDescription

4

freqscale_mode

RW

0x0

Current processor core frequency division mode selection

+

0: (n+1)/8

+

1: 1/(n+1)

3

clken

RW

0x0

Current processor core clock enable

2:0

freqscale

RW

0x0

Current processor core frequency divider configuration

+
+
+
+

5.3. Node Clock Division and Enable Control

+
+

The node clock is the clock used by the on-chip network and shared Cache, and has two different control modes, a software setting mode and a hardware automatic frequency division setting.

+
+
+

The node clock does not support full shutdown, so there is no corresponding clken control bit.

+
+
+

5.3.1. Software Configuration

+
+

The software setup method is compatible with the 3A3000 processor and uses the same address to set the node frequency division bits in the Function Setup register.

+
+
+

This register has a base address of 0x1fe00000,It can also be accessed using the configuration register instruction (IOCSR), and an offset address of 0x0180.

+
+ + +++++++ + + + + + + + + + + + + + + + + + + +
Table 38. Function configuration register
Bit FieldNameRead/WriteReset ValueDescription

42:40

Node0_freq_ctrl

RW

3’b111

Node 0 frequency division

+
+

In line with the processor core’s dividing control, the node clock can also be adjusted from (dividing control value + 1)/8 to 1/(dividing control value + 1) after dividing by setting the register. +This register is located in other function configuration register. +The base address is 0x1fe00000 and the offset address is 0x0420.

+
+ + +++++++ + + + + + + + + + + + + + + + + + + +
Table 39. Other function configuration register
Bit FieldNameRead/WriteReset ValueDescription

36

freqscale_mode_node

RW

0x0

Frequency adjustment mode selection for nodes

+

0: (n+1)/8

+

1: 1/(n+1)

+
+
+

5.3.2. Hardware Automatic Configuration

+
+

In addition to the active setting by the software, the node clock also supports the automatic frequency division setting triggered by the temperature sensor.

+
+
+

The auto-division setting is set by the software in advance for different temperatures, and the corresponding auto-division setting will be triggered when the temperature of the temperature sensor reaches the corresponding preset value.

+
+
+

In order to ensure the operation of the chip in a high-temperature environment, it can be set so that the high temperature automatic frequency reduction, so that the chip in excess of the preset range of active clock division, to achieve the effect of reducing the chip flip rate. +See 12.3 for details on how to set it up.

+
+
+
+
+

5.4. HT Controller Frequency Division and Enable Control

+
+

The frequency division mechanism of the HT controller is similar to the others. +The two HT controllers can be controlled separately. +The settings are made using the corresponding bits in the function configuration register. +Its base address is 0x1fe00000,It can also be accessed using the configuration register instruction (IOCSR), and offset address 0x0180.

+
+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 40. Function configuration register
Bit FieldNameRead/WriteReset ValueDescription

26:24

HT0_freq_scale_ctrl

RW

3’b111

HT Controller 0 frequency division

27

HT0_clken

RW

1’b1

Whether to enable HT0

30:28

HT1_freq_scale_ctrl

RW

3’b011

HT Controller 1 frequency division

31

HT1_clken

RW

1’b1

Whether to enable HT1

+
+

In line with other frequency division controls, the HT controller clock can be adjusted from (frequency division control value + 1)/8 to 1/(frequency division control value + 1) by setting the clock frequency after frequency division through a register. +This register is located in other function configuration register. +The base address is 0x1fe00000,It can also be accessed using the configuration register instruction (IOCSR), and the offset address is 0x0420.

+
+
+

Note that since the HT core clock is derived from the Node clock, it is also affected by the Node clock frequency division.

+
+ + +++++++ + + + + + + + + + + + + + + + + + + +
Table 41. Other function configuration register
Bit FieldNameRead/WriteReset ValueDescription

39:38

freqscale_mode_HT

RW

0x0

Frequency adjustment mode selection for each HT

+

0: (n+1)/8

+

1: 1/(n+1)

+
+
+

5.5. Stable Counter Frequency Ddivision and Enable Control

+
+

Stable Counter’s frequency division mechanism is similar to the others. +It is set using the corresponding bits in the other function configuration register. +Its base address is 0x1fe00000,It can also be accessed using the configuration register instruction (IOCSR), and offset address 0x0420.

+
+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 42. Other function configuration register
Bit FieldNameRead/WriteReset ValueDescription

20

stable_sel

RW

0x0

Stable clock selection

+

0: SYS CLOCK

+

1: NODE CLOCK

21

stable_resetn

RW

0x0

Stable clock reset control

+

1: set reset state

+

0: unset software reset

40

freqscale_mode_stable

RW

0x0

Frequency adjustment mode selection for stable clock

+

0: (n+1)/8

+

1: 1/(n+1)

46:44

freqscale_stable

RW

0x0

Stable clock frequency adjustment register

47

clken_stable

RW

0x0

Stable clock enable

+
+

It should be noted that after stable_reset is set to 0, only the software reset is released. +At this time, if GPIO_FUNC_en[13] is 1, the reset of the stable counter is still controlled by GPIO[13] (low valid).

+
+
+

The GPIO output enable register base address is 0x1fe00000,It can also be accessed using the configuration register instruction (IOCSR), offset address 0x0500.

+
+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 43. GPIO output enable register
Bit FieldNameRead/WriteReset ValueDescription

31:0

GPIO_OEn

RW

32’hffffffff

GPIO output enable (active low)

63:32

GPIO_FUNC_En

RW

32’hffff0000

GPIO function enable (active low)

+
+
+
+
+

6. Software Clock System

+
+
+

Several different levels of usage are defined in the Loongson 3A5000 processor for the clocks used by the system software. +Inside the processor core are the legacy counter/compare registers, the stable counter registers, and the chip-level node counter registers.

+
+
+

The following is introductions to stable counter and node counter.

+
+
+

6.1. Stable Counter

+
+

The constant clock source in the 3A5000 is called the stable counter, which is a separate master clock from the processor core’s own clock and from the node clock.

+
+
+

In the 3A5000, both the processor core clock and the node clock are derived from the master clock, but both can freely control the number of divisions (see the introduction in the previous chapter), while the clock of the stable counter is derived from the input reference clock and can also be independently divided and does not vary with the frequency of other clocks.

+
+
+

Based on this clock source, a timer and a timer are implemented. +This chapter mainly introduces the registers related to the Stable couter.

+
+
+

6.1.1. Configuration Address for Stable Timer

+
+

Using the Stable counter clock source, a monotonically increasing timer counter and a timer timer that decrements down from the set value are implemented; each processor core has its own independent Stable counter and Stable timer. +When the processor accesses the timer, it can only be accessed by rdhwr, DRDTIME and other specific instructions; when the processor accesses the timer, it can be accessed by address to load/store or by CSR configuration register instructions.

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 44. Address access method
NameOffset AddressRead/WriteDescription

Core0_timer_config

0x1060

RW

Timer configuration register for processor core 0

Core0_timer_ticks

0x1070

R

Timer remaining value for processor core 0

Core1_timer_config

0x1160

RW

Timer configuration register for processor core 1

Core1_timer_ticks

0x1170

R

Timer remaining value for processor core 1

Core2_timer_config

0x1260

RW

Timer configuration register for processor core 2

Core2_timer_ticks

0x1270

R

Timer remaining value for processor core 2

Core3_timer_config

0x1360

RW

Timer configuration register for processor core 3

Core3_timer_ticks

0x1370

R

Timer remaining value for processor core 3

+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + +
Table 45. Configuration register instruction access method
NameOffset AddressRead/WriteDescription

percore_timer_config

0x1060

RW

Timer configuration register of the current processor core

percore_timer_ticks

0x1070

R

Timer remaining value for the current processor core

+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 46. Register description
Bit FieldNameRead/WriteReset ValueDescription

timer_config

63

1

RW

0x1

Reset to 1, and should write 1

62

Periodic

RW

0x0

Cycle count enable. +When this bit is 1, the timer is automatically reset to the value of the InitVal field in timer_config after decreasing to 0

61

Enable

RW

0x0

General enable. +The timer is active when this bit is 1

47:0

InitVal

RW

0x0

The initial value for conducting the countdown

timer_ticks

63:48

0

R

0x0

Value 0

47:0

Ticks

R

0x0

The remaining value of the countdown. +When not in a cycle count, the value will stay at 48’hffff_ffff_ffff when the count is complete

+
+
+

6.1.2. Clock Control for Stable Counter

+
+

The Stable counter can optionally use either the reference clock input or the master clock and can be controlled by software dividing mechanism for dividing the frequency. +In general, it is recommended to use the reference clock input, which is able to be completely free from dynamic frequency tuning interference compared to the master clock.

+
+
+

The following is the clock control register of the Stable counter. +This register is located in the control chip other function configuration register. +The base address is 0x1fe00000,It can also be accessed using the configuration register instruction (IOCSR), and the offset address 0x0420.

+
+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 47. Other function configuration register
Bit FieldNameRead/WriteReset ValueDescription

20

stable_sel

RW

0x0

Stable clock selection

+

0: SYS CLOCK

+

1: NODE CLOCK

21

stable_resetn

RW

0x0

Stable clock reset control

+

1: set reset state

+

0: unset software reset

40

freqscale_mode_stable

RW

0x0

Frequency adjustment mode selection for stable clock

+

0: (n+1)/8

+

1: 1/(n+1)

46:44

freqscale_stable

RW

0x0

Stable clock frequency adjustment register

47

clken_stable

RW

0x0

Stable clock enable

+
+

After the BIOS has configured the Stable counter clock source, the MCSR section in each processor core needs to be updated to control the values of CPUCFG.0x4 and CPUCFG.0x5. +Referring to the description in Instruction set features implemented in 3A5000, CPUCFG.0x4 should be filled with the crystal clock frequency in Hz; CPUCFG.0x5[31:16] should be filled with the dividing factor; CPUCFG.0x5[15:0] should be filled with the multiplication factor. +The latter two should be filled in with the help of BIOS for calculation, so that the result of CCFreq*CFM/CFD is equal to the actual frequency of Stable Counter.

+
+
+
+

6.1.3. Calibration of Stable Counter

+
+

In the single-chip case, the Counter difference between each core is within 2 cycles, and no special calibration is needed. +In the multi-chip case, there are large differences between different chips, and a special hardware and software calibration mechanism is needed to keep the counter difference of each core below 100ns.

+
+
+

First, to ensure that the master clock of each chip does not deviate during use, the same crystal is used to drive SYS_CLK for all chips.

+
+
+

Second, to ensure that the Stable counter of each chip starts timing at the same moment, the hardware needs to use the multiplexing function of two GPIO pins. +Node 0 uses GPIO12 to output the reset signal, and all other nodes (including Node 0) use GPIO13 to input the reset signal (which needs to be configured for the Stable counter function). +On the motherboard a buffer device need to be used to ensure the reset timing (mainly the signal slope), the better the reset timing, the less the difference in clocks between different chips.

+
+
+

The software must reset the global Stable counter via GPIO12 before using the Stable counter. +Before resetting, need to ensure that the clock selection of each chip is consistent and that the reset of each chip has been lifted. +This work is usually done by the BIOS. +The connection scheme of the system is shown in the following figure.

+
+
+
+stable reset control for multi chip interconnection +
+
Figure 4. Stable reset control for multi-chip interconnection
+
+
+
+
+

6.2. Node Counter

+
+

The behavior of the Node counter in the Loongson 3A5000 is the same as that of the 3A4000.

+
+
+

It should be noted that the counting frequency of Node counter is exactly the same as Node clock. If you want to use Node counter as the basis for clock calculation, you should avoid inverting Node clock.

+
+
+

6.2.1. Accessing by Address

+
+

The per-address access mode is compatible with the 3A3000 processor and uses the same addresses for setup. +The base address of the configuration register is `0x1fe00000`can also be accessed using the configuration register instruction (IOCSR), as shown in the table below.

+
+ + ++++++ + + + + + + + + + + + + + + + + +
Table 48. Node counter register
NameOffset AddressRead/WriteDescription

Node counter

0x0408

R

64-bit node clock count

+
+
+
+

6.3. Summary of Clock System

+
+

The new Stable counter in Loongson 3A5000 has an advantage over the node counter and CP0counter in terms of stability, as it does not change with other clocks (node clock and core clock).

+
+
+

In terms of ease of use, the Stable counter is also easier to access, using instruction for both user and Guest states. +Stable counter is the preferred solution for software reference clock systems.

+
+
+

Node clock is more of a design for legacy compatibility and is a backup solution for the clock system. +It will be phased out in future chip designs.

+
+
+
+
+
+

7. GPIO Control

+
+
+

Up to 32 GPIOs are provided in the 3A5000 for system use, and most of them are multiplexed with other functions. +The GPIOs can also be configured as interrupt inputs and their interrupt levels can be set through register settings.

+
+
+

The base address of each chip configuration register in this chapter is 0x1fe00000.

+
+
+

7.1. Output Enable Register (0x0500)

+
+

The base address is 0x1fe00000 and the offset address is 0x0500.

+
+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 49. Output enable register
Bit FieldNameRead/WriteReset ValueDescription

31:0

GPIO_OEn

RW

32’hffffffff

GPIO output enable (active low)

63:32

GPIO_FUNC_En

RW

32’hffff0000

GPIO function enable (active low)

+
+
+

7.2. Input/Output Register (0x0508)

+
+

The base address is 0x1fe00000 and the offset address is 0x0508.

+
+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 50. Input/Output Register
Bit FieldNameRead/WriteReset ValueDescription

31:0

GPIO_O

RW

32’h0

GPIO output configuration

63:32

GPIO_I

RO

32’h0

GPIO input status

+
+
+

7.3. Interrupt Control Register (0x0510)

+
+

The base address is 0x1fe00000 and the offset address is 0x0510.

+
+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 51. Interrupt control register
Bit FieldNameRead/WriteReset ValueDescription

31:0

GPIO_INT_Pol

RW

32’h0

GPIO interrupt active level configuration

+

0 - active low

+

1 - active high

63:32

GPIO_INT_en

RW

32’h0

GPIO interrupt enable contrl (active high)

+
+
+

7.4. GPIO Pin Function Multiplexing Table

+
+

The 3A5000 has a large number of GPIO pins multiplexed with other functions, and the following list shows the pin function selection of the chip function pins.

+
+
+

It should be noted that GPIO00-GPIO15 are GPIO functions when the chip is reset, and the default state is input, not driving I/O.

+
+
+

In order to prevent the internal logic from driving the corresponding I/O, the corresponding HT0/1_Hi/Lo_Hostmode pins can be pulled down. +At this point, although the default is still the HT function at reset, it will not drive the I/O pins and will not affect external devices. +Only need to set the function to GPIO mode before using the GPIO function in software.

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 52. Table of GPIO multiplexing function
GPIO RegisterPin NameMultiplexing FunctionDefault Function

0

GPIO00

SPI_CSn1

GPIO

1

GPIO01

SPI_CSn2

GPIO

2

GPIO02

UART1_RXD

GPIO

3

GPIO03

UART1_TXD

GPIO

4

GPIO04

UART1_RTS

GPIO

5

GPIO05

UART1_CTS

GPIO

6

GPIO06

UART1_DTR

GPIO

7

GPIO07

UART1_DSR

GPIO

8

GPIO08

UART1_DCD

GPIO

9

GPIO09

UART1_RI

GPIO

10

GPIO10

-

GPIO

11

GPIO11

-

GPIO

12

GPIO12

-

GPIO

13

GPIO13

SCNT_RSTn

GPIO

14

GPIO14

PROCHOTn

GPIO

15

GPIO15

THERMTRIPn

GPIO

16

HT0_LO_POWEROK

GPIO16

HT0_LO_POWEROK

17

HT0_LO_RSTn

GPIO17

HT0_LO_RSTn

18

HT0_LO_LDT_REQn

GPIO18

HT0_LO_LDT_REQn

19

HT0_LO_LDT_STOPn

GPIO19

HT0_LO_LDT_STOPn

20

HT0_HI_POWEROK

GPIO20

HT0_HI_POWEROK

21

HT0_HI_RSTn

GPIO21

HT0_HI_RSTn

22

HT0_HI_LDT_REQn

GPIO22

HT0_HI_LDT_REQn

23

HT0_HI_LDT_STOPn

GPIO23

HT0_HI_LDT_STOPn

24

HT1_LO_POWEROK

GPIO24

HT1_LO_POWEROK

25

HT1_LO_RSTn

GPIO25

HT1_LO_RSTn

26

HT1_LO_LDT_REQn

GPIO26

HT1_LO_LDT_REQn

27

HT1_LO_LDT_STOPn

GPIO27

HT1_LO_LDT_STOPn

28

HT1_HI_POWEROK

GPIO28

HT1_HI_POWEROK

29

HT1_HI_RSTn

GPIO29

HT1_HI_RSTn

30

HT1_HI_LDT_REQn

GPIO30

HT1_HI_LDT_REQn

31

HT1_HI_LDT_STOPn

GPIO31

HT1_HI_LDT_STOPn

+
+
+

7.5. GPIO Interrupt Control

+
+

The GPIO pins in the 3A5000 can all be used as interrupt inputs.

+
+
+

GPIO00, GPIO08, GPIO16, GPIO24 share the interrupt controller’s interrupt line 0.

+
+
+

GPIO01, GPIO09, GPIO17, GPIO25 share the interrupt controller’s interrupt line 1.

+
+
+

GPIO02, GPIO10, GPIO18, GPIO26 share the interrupt controller’s interrupt line 2.

+
+
+

GPIO03, GPIO11, GPIO19, GPIO27 share the interrupt controller’s interrupt line 3.

+
+
+

GPIO04, GPIO12, GPIO20, GPIO28 share the interrupt controller’s interrupt line 4.

+
+
+

GPIO05, GPIO13, GPIO21, GPIO29 share the interrupt controller’s interrupt line 5.

+
+
+

GPIO06, GPIO14, GPIO22, GPIO30 share the interrupt controller’s interrupt line 6.

+
+
+

GPIO07, GPIO15, GPIO23, GPIO31 share the interrupt controller’s interrupt line 7.

+
+
+

The interrupt enable of each GPIO is controlled by the configuration register GPIO_INT_en and the interrupt level is controlled by GPIO_INT_POL, the registers are as follows:

+
+
+

The base address is 0x1fe00000 and the offset address is 0x0510.

+
+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 53. Interrupt control register
Bit FieldNameRead/WriteReset ValueDescription

31:0

GPIO_INT_Pol

RW

32’h0

GPIO interrupt active level configuration

+

0 - active low

+

1 - active high

63:32

GPIO_INT_en

RW

32’h0

GPIO interrupt enable contrl (active high)

+
+

When each interrupt line on the interrupt controller enables only one of the GPIOs, an interrupt can be triggered at a fixed edge (falling edge when POL is set to 0, rising edge when POL is set to 1) and logged in the interrupt controller using edge triggering.

+
+
+
+
+
+

8. LA464 Processor Core

+
+
+

LA464 is a quad-launch 64-bit high-performance processor core. +It can be used as a single core for high-end embedded and desktop applications, or as a basic processor core to form an on-chip multi-core system for server and high-performance machine applications. +The multiple LA464 cores in the Loongson 3A5000 form a distributed multi-core architecture with a shared on-chip last-level Cache through the AXI interconnect network. +The main features of LA464 are as follows:

+
+
+
    +
  • +

    Support for the Loongson autonomous instruction set (LoongArch).

    +
    • +
  • +

    Four-launch superscalar architecture with four fixed-point, two vector, and two access components.

    +
    • +
  • +

    Each vector component is 256 bits wide, and each component supports up to eight double 32-bit floating-point multiplication and addition operations.

    +
    • +
  • +

    Access components support 256-bit memory access, with 64-bit virtual addresses and 48-bit physical addresses.

    +
    • +
  • +

    support for register renaming, dynamic scheduling, transfer prediction, and other chaotic execution techniques.

    +
    • +
  • +

    64 fully-associative items plus 2048 items connected in 8-way groups, for a total of 2112 TLBs, 64 instruction TLBs, and variable page size.

    +
    • +
  • +

    First-level instruction Cache and data Cache size of 64KB each, 4-way group concatenation.

    +
    • +
  • +

    Victim Cache as a private secondary Cache, 256KB in size, 16-way group concatenation.

    +
    • +
  • +

    Supports access optimization techniques such as Non-blocking access and Load-Speculation.

    +
    • +
  • +

    Supports Cache Consistency Protocol for on-chip multi-core processors.

    +
    • +
  • +

    Supports parity check for first-level Cache and ECC check for second-level, on-chip last-level Cache.

    +
    • +
  • +

    Supports standard JTAG debugging interface for easy hardware and software debugging.

    +
    • +
+
+
+

The structure of LA464 is shown in the following figure.

+
+
+
+la464 structure +
+
Figure 5. LA464 structure
+
+
+

8.1. Instruction set features implemented in 3A5000

+
+

The functional features of the Loongson instruction set implemented in the Loongson 3A5000 can be dynamically confirmed by the Loongson instruction set attribute identification mechanism.

+
+
+

The CPUCFG instruction is a user-state instruction, which is used as CPUCFG rd, rj, where the source operand rj register holds the register number of the configuration information word to be accessed, and the returned configuration word information is written to the rd register, each configuration information word contains up to 32 bits of configuration information. +For example, bit 0 of configuration word 1 indicates whether the LA32 architecture is implemented, then this configuration information is expressed as CPUCFG.1.LA32[bit0], where 1 means that the font size of the configuration information word is 1, LA32 means that the helper name of this configuration information field is LA32, and bit 0 means that the field LA32 is located in bit 0 of the configuration word. +If the configuration information needs to be expressed in multiple bits, then the location information will be recorded in the form of bitAA:BB, which means the consecutive (AA-BB+1) bits from the AAth to the BBth bit of the configuration information word.

+
+
+

The following table gives a list of configuration information for the instruction set functions implemented in the 3A5000. +The last column, “Possible Value”, indicates a possible value to be read from this register, but does not imply that this is the value to be read from the 3A5000 processor. +Please refer to the results of the actual hardware execution of the instruction, and make subsequent software judgments based on the actual read values.

+
+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 54. List of configuration information for the instruction set functions implemented in the 3A5000

Register Number

Bit Field

Name

Description

Possible Value

0x0

31:0

PRId

Processor Identity

32’h14_c010

0x1

1:0

ARCH

2’b00 indicates implementation of simplified LA32; 2’b01 indicates implementation of LA32; 2’b10 indicates implementation of LA64. +2’b11 is reserved

2’b10

2

PGMMU

1 indicates that the MMU supports page mapping mode

1’b1

3

IOCSR

1 indicates support for the IOCSR instruction

1’b1

11:4

PALEN

The value of the supported physical address bits PALEN minus 1

8’d47

19:12

VALEN

The value of the supported vitrual address bits VALEN minus 1

8’d47

20

UAL

1 indicates support for non-aligned memory access

1’b1

21

RI

1 indicates support for the “Read Inhibit” page attribute

1’b1

22

EP

1 indicates support for “Execution Protection” page attribute

1’b1

23

RPLV

1 indicates support for RPLV page attributes

1’b1

24

HP

1 indicates support for huge page page attributes

1’b1

25

IOCSR_BRD

1 indicates a string with processor product information recorded at address 0 of the IOCSR access space

1’b1

26

MSG_INT

1 means that the external interrupt uses the message interrupt mode, otherwise it is the level interrupt line mode

1’b0

0x2

0

FP

1 means support for basic floating-point instructions

1’b1

1

FP_SP

1 indicates support for single-precision floating-point numbers

1’b1

2

FP_DP

1 indicates support for double-precision floating-point numbers

1’b1

5:03

FP_ver

The version number of the floating-point arithmetic standard. +1 is the initial version number, indicating that it is compatible with the IEEE 754-2008 standard

3’h1

6

LSX

1 indicates support for 128-bit vector extension

1’b1

7

LASX

1 indicates support for 256-bit vector expansion

1’b1

8

COMPLEX

1 indicates support for complex vector operation instructions

1’b1

14

LLFTP

1 indicates support for constant frequency counter and timer

1’b1

17:15

LLFTP_ver

Constant frequency counter and timer version number. +1 is the initial version

3’h1

21

LSPW

1 indicates support for the software page table walking instruction

1’b1

22

LAM

1 indicates support AM* atomic memory access instruction

1’b1

0x3

0

CCDMA

1 indicates support for hardware Cache coherent DMA

1’b1

1

SFB

1 indicates support for Store Fill Buffer (SFB)

1’b1

3

LLEXC

1 indicates support for LL instruction to fetch exclusive block function

1’b1

4

SCDLY

1 indicates support random delay function after SC

1’b1

5

LLDBAR

1 indicates support LL automatic with dbar function

1’b1

6

ITLBT

1 indicates that the hardware maintains the consistency between ITLB and TLB

1’b1

7

ICACHET

1 indicates that the hardware maintains the data consistency between ICache and DCache in one processor core

1’b1

10:8

SPW_LVL

The maximum number of directory levels supported by the page walk instruction

3’h4

11

SPW_HP_HF

1 indicates that the page walk instruction fills the TLB in half when it encounters a large page

1’b1

12

RVA

1 indicates that the software configuration can be used to shorten the virtual address range

1’b1

16:13

RVAMAX-1

The maximum configurable virtual address is shortened by -1

1’b1

0x5

15:00

CC_MUL

Constant frequency counter and timer and the corresponding multiplication factor of the clock used by the timer

N/A

31:16

CC_DIV

Constant frequency counter and timer and the division coefficient corresponding to the clock used by the timer

N/A

0x6

0

PMP

1 indicates support for the performance counter

1’b1

3:1

PMVER

In the performance monitor, the architecture defines the version number of the event, and 1 is the initial version

3’h1

7:4

PMNUM

Number of performance monitors minus 1

4’h3

13:08

PMBITS

Number of bits of a performance monitor minus 1

6’h3f

14

UPM

1 indicates support for reading performance counter in user mode

1’b1

0x10

0

L1 IU_Present

1 indicates that there is a first-level instruction Cache or a first-level unified Cache

1’b1

1

L1 IU Unify

1 indicates that the Cache shown by L1 IU_Present is the unified Cache

1’b0

2

L1 D Present

1 indicates there is a first-level data Cache

1’b1

3

L2 IU Present

1 indicates there is a second-level instruction Cache or a second-level unified Cache

1’b1

4

L2 IU Unitfy

1 indicates that the Cache shown by L2 IU_Present is the unified Cache

1’b1

5

L2 IU Private

1 indicates that the Cache shown by L2 IU_Present is private to each core

1’b1

6

L2 IU Inclusive

1 indicates that the Cache shown by L2 IU_Present has an inclusive relationship to the lower levels (L1)

1’b0

7

L2 D Present

1 indicates there is a secondary data Cache

1’b0

8

L2 D Private

1 indicates that the secondary data Cache is private to each core

1’b0

9

L2 D Inclusive

1 indicates that the secondary data Cache has a containment relationship to the lower level (L1)

1’b0

10

L3 IU Present

1 indicates there is a three-level instruction Cache or a three-level system Cache

1’b1

11

L3 IU Unify

1 indicates that the Cache shown by L3 IU_Present is unified Cache

1’b1

12

L3 IU Private

1 indicates that the Cache shown by L3 IU_Present is private to each core

1’b0

13

L3 IU Inclusive

1 indicates that the Cache shown by L3 IU_Present has an inclusive relationship to the lower levels (L1 and L2)

1’b1

14

L3 D Present

1 indicates there is a three-level data Cache

1’b0

15

L3 D Private

1 indicates that the three-level data Cache is private to each core

1’b0

16

L3 D Inclusive

1 indicates that the three-level data Cache has an inclusive relationship to the lower levels (L1 and 12)

1’b0

0x11

15:0

Way-1

Number of channels minus 1 (Cache corresponding to L1 IU_Present in configuration word 10)

16’h3

23:16

Index-log2

log2(number of Cache rows per channel) (Cache corresponding to L1 IU_Present in configuration word 10)

8’h8

30:24

Linesize-log2

log2(Cache line bytes) (Cache corresponding to L1 IU_Present in configuration word 10)

8’h6

0x12

15:0

Way-1

Number of channels minus 1 (Cache corresponding to L1 D Present in Configuration Word 10)

16’h3

23:16

Index-log2

log2(number of Cache rows per channel) (Cache corresponding to L1 D Present in Configuration Word 10)

8’h8

30:24

Linesize-log2

log2(Cache row bytes) (Cache corresponding to L1 D Present in configuration word 10)

8’h6

0x13

15:0

Way-1

Number of channels minus 1 (Cache corresponding to L2 IU Present in configuration word 10)

16’hf

23:16

Index-log2

log2(number of Cache rows per channel) (Cache corresponding to L2 IU Present in configuration word 10)

8’h8

30:24

Linesize-log2

log2(Cache row bytes) (Cache corresponding to L2 IU Present in configuration word 10)

8’h6

0x14

15:00

Way-1

Number of channels minus 1 (Cache corresponding to L3 IU Present in configuration word 10)

16’hf

23:16

Index-log2

log2(number of Cache rows per channel) (Cache corresponding to L3 IU Present in configuration word 10)

8’h8

30:24

Linesize-log2

log2(Cache row bytes) (Cache corresponding to L3 IU Present in configuration word 10)

8’h6

+
+
+

8.2. Access to 3A5000 Control and Status Registers

+
+

The 3A5000 supports configuration status register space access. +The CSR is accessed using a new, independent addressing space called the CSR space that does not overlap with existing register space, memory space, or JTAG space.

+
+
+

CSR read and write accesses are performed via the custom IOCSRRD.B/H/W/D and IOCSRWR. +IOCSRRD.B/H/W/D is used as IOCSRRD.B/H/W/D rd,rj, where the source operand rj register holds the address of the CSR with access, and the CSR read back is written to the rd register. +IOCSRWR.B/H/W/D is used as IOCSRWR.B/H/W/D rd,rj, where the source operand rj register holds the address of the CSR with access, and the source operand rd register holds the value of the CSR to be written. +IOCSRRD.B/H/W/D and IOCSRWR.B/H/W/D are allowed to operate in the kernel state only.

+
+
+

IOCSRRD.B/H/W/D and IOCSRWR.B/H/W/D instructions can be used instead of the original address-mapped configuration registers, i.e., the 0x1fe00000 and 0x3ff00000 spaces, as described in the relevant sections for access details.

+
+
+
+
+
+

9. Shared Cache (SCache)

+
+
+

The SCache module is a three-level Cache shared by all processor cores within the Loongson 3A5000 processor. +The main features of the SCache module include:

+
+
+
    +
  • +

    16-item Cache access queue.

    +
    • +
  • +

    Keyword priority.

    +
    • +
  • +

    Supports Cache Consistency Protocol through directories.

    +
    • +
  • +

    Can be used in on-chip multi-core architectures or directly interfaced with single-processor IP.

    +
    • +
  • +

    16-way group concatenation architecture.

    +
    • +
  • +

    Supports ECC checksum.

    +
    • +
  • +

    Supports DMA consistent read/write and prefetch reads.

    +
    • +
  • +

    Supports 16 types of shared Cache hashing.

    +
    • +
  • +

    Supports shared Cache by window lock.

    +
    • +
  • +

    Guaranteed read data return atomicity.

    +
    • +
+
+
+

The shared Cache module includes the shared Cache management module scachemanage and the shared Cache access module scacheaccess. +scachemanage is responsible for processing access requests from processors and DMAs, while the shared Cache TAG, directory and data information is stored in the scacheaccess module. +To reduce power consumption, the TAG, directory and data of the shared Cache can be accessed separately. +The shared Cache status bits and w bits are stored together with TAG, TAG is stored in TAG RAM, directory is stored in DIR RAM and data is stored in DATA RAM. +Failure request accesses the shared Cache and reads the TAG, directory of all roads at the same time and picks the directory according to TAG and reads the data according to the hit. +Replacement requests, refill requests and write back requests operate only on the TAGs, directories and data of one way.

+
+
+

To improve the performance of some specific computing tasks, a locking mechanism is added to the shared Cache. +Blocks that fall in the locked area of the Shared Cache are locked and therefore will not be replaced out of the Shared Cache (unless all 16 paths of the Shared Cache contain locked blocks).

+
+
+

The four sets of lock window registers inside the shared Cache module can be dynamically configured through the chip configuration register space, but it must be ensured that one of the 16 Shared Caches must not be locked. +In addition, when the shared Cache receives a DMA write request, if the area to be written is hit and locked in the shared Cache, then the DMA write will be written directly to the shared Cache.

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 55. Shared Cache lock window register configuration
NameAddressBit FieldDescription

Slock0_valid

0x00200

[63:63]

Valid bits for lock window 0

Slock0_addr

0x00200

[47:0]

Lock address for lock window 0

Slock0_mask

0x00240

[47:0]

Mask for lock window 0

Slock1_valid

0x00208

[63:63]

Valid bits for lock window 1

Slock1_addr

0x00208

[47:0]

Lock address for lock window 1

Slock1_mask

0x00248

[47:0]

Mask for lock window 1

Slock2_valid

0x00210

[63:63]

Valid bits for lock window 2

Slock2_addr

0x00210

[47:0]

Lock address for lock window 2

Slock2_mask

0x00250

[47:0]

Mask for lock window 2

Slock3_valid

0x00218

[63:63]

Valid bits for lock window 3

Slock3_addr

0x00218

[47:0]

Lock address for lock window 3

Slock3_mask

0x00258

[47:0]

Mask for lock window 3

+
+

For example, when an address addr causes slock0_valid && addr & slock0_mask) == (slock0_addr & slock0_mask to be 1, the address is locked by lock window 0.

+
+
+

The 4 SCache use the same configuration register with base address 0x1fe00000,It can also be accessed using the configuration register instruction (IOCSR), and offset address 0x0280.

+
+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 56. Shared Cache configuration register (SC_CONFIG)
Bit FieldNameRead/WriteReset ValueDescription

0

LRU en

RW

1’b1

SCache LRU replacement algorithm enable

16

Prefetch En

RW

1’b1

SCache prefetch function enable

22:20

Prefetch config

RW

3’h1

Stop prefetching when SCache prefetching exceeds the address range of the configured size

+

0 - 4KB

+

1 - 16KB

+

2 - 64KB

+

3 - 1MB

+

7 - Unlimited

+

(Note: Valid when SCID_SEL==0)

26:24

Prefetch lookahead

RW

3’h2

SCache prefetch size

+

0 - Reserved

+

1 - 0x100

+

2 - 0x200

+

3 - 0x300

+

4 - 0x400

+

5 - 0x500

+

6 - 0x600

+

7 - 0x700

+

(Note: Valid when SCID_SEL==0)

30:28

Sc stall dirq cycle

RW

3’h2

Number of clock cycles of SC instruction blocking dirq

+

0 - 1 cycle (nonstall)

+

1 - 16-31 cycle random

+

2 - 32-63 cycle random

+

3 - 64-127 cycle random

+

4 - 128-255 cycle random

+

Other - Invalid

31

MCC storefill en

RW

1’b0

MCC storefill function enable

34:32

35

MCC clean exclusive replace en

RW

1’b0

36

MCC clean shared replace en

RW

1’b0

+
+
+
+

10. Inter-Processor Interrupts and Communication

+
+
+

The Loongson 3A5000 implements eight inter-processor interrupt registers (IPI) for each processor core to support interrupts and communication between processor cores during multi-core BIOS boot and OS runtime.

+
+
+

Two different access modes are supported in the Loongson 3A5000, one is an address access mode compatible with processors such as the 3A3000, and the other is designed to support direct private access to the processor register space. +Separate descriptions are provided in later sections.

+
+
+

10.1. Accessing by Address

+
+

For the Loongson 3A5000, the following registers can be accessed using base address 0x1fe0_0000,It can also be accessed using the configuration register instruction (IOCSR). +Of these, base address 0x3ff0_0000 can be turned off by the disable_0x3ff0 control bit in the Routing Setup Register. +See the tables below for specific register descriptions and addresses.

+
+ + +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+

The registers related to interprocessor interrupts and their functions in the Loongson 3A5000 are described as follows:

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 58. List of inter-processor interrupt and communication registers for processor core 0
NameOffset AddressRead/WriteDescription

Core0_IPI_Status

0x1000

R

IPI_Status register of processor core 0

Core0_IPI_Enalbe

0x1004

RW

IPI_Enalbe register of processor core 0

Core0_IPI_Set

0x1008

W

IPI_Set register of processor core 0

Core0_IPI_Clear

0x100c

W

IPI_Clear register of processor core 0

Core0_MailBox0

0x1020

RW

IPI_MailBox0 register of processor core 0

Core0_MailBox1

0x1028

RW

IPI_MailBox1 register of processor core 0

Core0_MailBox2

0x1030

RW

IPI_MailBox2 register of processor core 0

Core0_MailBox3

0x1038

RW

IPI_MailBox3 register of processor core 0

+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 59. List of inter-processor interrupt and communication registers for processor core 1
NameOffset AddressRead/WriteDescription

Core1_IPI_Status

0x1100

R

IPI_Status register of processor core 1

Core1_IPI_Enalbe

0x1104

RW

IPI_Enalbe register of processor core 1

Core1_IPI_Set

0x1108

W

IPI_Set register of processor core 1

Core1_IPI_Clear

0x110c

W

IPI_Clear register of processor core 1

Core1_MailBox0

0x1120

R

IPI_MailBox0 register of processor core 1

Core1_MailBox1

0x1128

RW

IPI_MailBox1 register of processor core 1

Core1_MailBox2

0x1130

W

IPI_MailBox2 register of processor core 1

Core1_MailBox3

0x1138

W

IPI_MailBox3 register of processor core 1

+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 60. List of inter-processor interrupt and communication registers for processor core 2
NameOffset AddressRead/WriteDescription

Core2_IPI_Status

0x1200

R

IPI_Status register of processor core 2

Core2_IPI_Enalbe

0x1204

RW

IPI_Enalbe register of processor core 2

Core2_IPI_Set

0x1208

W

IPI_Set register of processor core 2

Core2_IPI_Clear

0x120c

W

IPI_Clear register of processor core 2

Core2_MailBox0

0x1220

R

IPI_MailBox0 register of processor core 2

Core2_MailBox1

0x1228

RW

IPI_MailBox1 register of processor core 2

Core2_MailBox2

0x1230

W

IPI_MailBox2 register of processor core 2

Core2_MailBox3

0x1238

W

IPI_MailBox3 register of processor core 2

+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 61. List of inter-processor interrupt and communication registers for processor core 3
NameOffset AddressRead/WriteDescription

Core3_IPI_Status

0x1300

R

IPI_Status register of processor core 3

Core3_IPI_Enalbe

0x1304

RW

IPI_Enalbe register of processor core 3

Core3_IPI_Set

0x1308

W

IPI_Set register of processor core 3

Core3_IPI_Clear

0x130c

W

IPI_Clear register of processor core 3

Core3_MailBox0

0x1320

R

IPI_MailBox0 register of processor core 3

Core3_MailBox1

0x1328

RW

IPI_MailBox1 register of processor core 3

Core3_MailBox2

0x1330

W

IPI_MailBox2 register of processor core 3

Core3_MailBox3

0x1338

W

IPI_MailBox3 register of processor core 3

+
+

The above is a list of inter-processor interrupt-related registers for a single-node multiprocessor system composed of a single Loongson 3A5000 chip. +When multiple Loongson 3A5000 chips are interconnected to form a multi-node CC-NUMA system, each node within a chip corresponds to a global system node number, and the IPI register addresses of the processor cores within the node are fixed at an offset from the base address of the node in the table above. +For example, the IPI_Status address of processor core 0 of node 0 is 0x1fe01000, while the processor address of processor 0 of node 1 is 0x10001fe01000, and so on.

+
+
+
+

10.2. Accessing by Configuration Register Instructions

+
+

In the Loongson 3A5000, a new processor core direct register access instruction has been added to provide access to configuration registers through private space. +In order to use inter-processor interrupt registers more easily, some adjustments are made to the inter-processor interrupt register definitions in this mode.

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 62. List of inter-processor interrupt and communication registers for the current processor core
NameOffset AddressRead/WriteDescription

perCore_IPI_Status

0x1000

R

IPI_Status register of the current processor core

perCore_IPI_Enalbe

0x1004

RW

IPI_Enalbe register of the current processor core

perCore_IPI_Set

0x1008

W

IPI_Set register of the current processor core

perCore_IPI_Clear

0x100c

W

IPI_Clear register of the current processor core

perCore_MailBox0

0x1020

RW

IPI_MailBox0 register of the current processor core

perCore_MailBox1

0x1028

RW

IPI_MailBox1 register of the current processor core

perCore_MailBox2

0x1030

RW

IPI_MailBox2 register of the current processor core

perCore_MailBox3

0x1038

RW

IPI_MailBox3 register of the current processor core

+
+

In order to send inter-processor interrupt requests and MailBox communication to other cores, the following registers are accessed.

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 63. Processor core inter-processor communication registers
NameOffset AddressRead/WriteDescription

IPI_Send

0x1040

WO

32-bit interrupt distribution register

+

[31]: wait for completion flag; when set to 1 it will wait for the interrupt to take effect

+

[30:26]: reserved

+

[25:16]: processor core number

+

[15:5]: reserved

+

[4:0]: interrupt vector number, corresponding to the vector in IPI_Status

Mail_Send

0x1048

WO

64-bit MailBox Cache register

+

[63:32]: MailBox data

+

[31]: wait for completion flag; when set to 1 it will wait for the write to take effect

+

[30:27]: write data mask; each bit indicates that the bytes corresponding to the 32-bit write data will not really be written to the target address, such as 1000b means write the 0-2 bytes, 0000b means write all 0-3 bytes

+

[26]: reserved

+

[25:16]: processor core number

+

[15:5]: reserved

+

[4:2]: MailBox number

+

0 - MailBox0 low 32-bit

+

1 - MailBox0 high 32-bit

+

2 - MailBox1 low 32-bit

+

3 - MailBox1 high 32-bit

+

4 - MailBox2 low 32-bit

+

5 - MailBox2 high 32-bit

+

6 - MailBox3 low 32-bit

+

7 - MailBox4 high 32-bit

+

[1:0]: reserved

FREQ_Send

0x1058

WO

32-bit frequency enable register

+

[31]: wait for completion flag; when set to 1 it will wait for the setting to take effect

+

[30:27]: write data mask; each bit indicates that the bytes corresponding to the 32-bit write data will not really be written to the target address, such as 1000b means write the 0-2 bytes, 0000b means write all 0-3 bytes

+

[26]: reserved

+

[25:16]: processor core number

+

[15:5]: reserved

+

[4:0]: write to the corresponding processor core private frequency configuration register

+

CSR[0x1050]

+
+

Note that since the Mail_Send register can only send 32 bits of data at a time, it must be split into two transmissions when sending 64 bits of data. +Therefore, the target core needs to ensure the integrity of the transport by other software means while waiting for the contents of the Mail_Box. +For example, after sending the Mail_Box data, an inter-processor interrupt is used to indicate that the transmission is complete.

+
+
+
+

10.3. Debug Support for Configuration Register Instructions

+
+

The configuration register instruction is in principle used without cross-chip access, but in order to meet the needs for debugging, etc., cross-chip access is supported here by using multiple register addresses. +It is worth noting that such registers can only be written, not read.

+
+
+

In addition to IPI_Send, Mail Send, Freq Send mentioned in the previous section, there is also an Any Send register available with the following address.

+
+ + ++++++ + + + + + + + + + + + + + + + + +
Table 64. Processor core inter-processor communication registers
NameOffset AddressRead/WriteDescription

ANY_Send

0x1158

WO

64-bit register access register

+

[63:32]: data being written

+

[31]: wait for completion flag; when set to 1 it will wait for the interrupt to take effect

+

[30:27]: write data mask; each bit indicates that the bytes corresponding to the 32-bit write data will not really be written to the target address, such as 1000b means write the 0-2 bytes, 0000b means write all 0-3 bytes

+

[26]: reserved

+

[25:16]: destination processor core number

+

[15:0]: offset address of the register to be written

+
+
+
+
+

11. I/O Interrupts

+
+
+

The Loongson 3A5000 chip supports two different interrupt methods. +The first is the legacy interrupt method, which is compatible with processors such as the 3A3000, and the second is the new extended I/O interrupt method, which is used to support the interrupt cross-chip and dynamic distribution functions of the HT controller. +The following describes each of the two interrupt methods.

+
+
+

11.1. Legacy I/O Interrupts

+
+

The legacy interrupts on the Loongson 3A5000 chip support 32 interrupt sources managed in a unified manner as shown in the figure below. +Any of the I/O interrupt sources can be configured to enable or disable, how it is triggered, and the target processor core interrupt pin to be routed. +Legacy interrupts do not support cross-chip distribution of interrupts, and can only interrupt processor cores within the same processor chip.

+
+
+
+interrupt routing of loongson 3a5000 processor +
+
Figure 6. Interrupt routing of Loongson 3A5000 processor
+
+
+

The interrupt-related configuration registers are in the form of bits to control the corresponding interrupt lines, and the interrupt control bit connections and attributes are configured in the following table.

+
+
+

The configuration of interrupt enable (Enable) has three registers: Intenset, Intenclr and Inten. +Intenset sets the interrupt enable, the interrupt corresponding to the bit written 1 in the Intenset register is enabled. +Intenclr clears the interrupt enable, the interrupt corresponding to the bit written 1 in the Intenclr register is cleared. +The Inten register reads the current status of each interrupt enable. +The edge-triggered interrupt signal is selected by the Intedge configuration register, with a write of 1 for edge-triggered and a write of 0 for level-triggered. +The interrupt handler can clear the interrupt record by using the corresponding bit of Intenclr. +Clearing the interrupt will also clear the interrupt enable.

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 65. Interrupt control register
Bit FieldRead/Write (Default Value)

Intedge

Inten

Intenset

Intenclr

Interrupt Source

0

RW (0)

R (0)

RW (0)

RW (0)

GPIO24/16/8/0/SC0

1

RW (0)

R (0)

RW (0)

RW (0)

GPIO25/17/9/1/SC1

2

RW (0)

R (0)

RW (0)

RW (0)

GPIO26/18/10/2/SC2

3

RW (0)

R (0)

RW (0)

RW (0)

GPIO27/19/11/3/SC3

4

RW (0)

R (0)

RW (0)

RW (0)

GPIO28/20/12/4

5

RW (0)

R (0)

RW (0)

RW (0)

GPIO29/21/13/5

6

RW (0)

R (0)

RW (0)

RW (0)

GPIO30/22/14/6

7

RW (0)

R (0)

RW (0)

RW (0)

GPIO31/23/15/7

8

RW (0)

R (0)

RW (0)

RW (0)

I2C0

9

RW (0)

R (0)

RW (0)

RW (0)

I2C1

10

RW (0)

R (0)

RW (0)

RW (0)

UART0

11

RW (0)

R (0)

RW (0)

RW (0)

MC0

12

RW (0)

R (0)

RW (0)

RW (0)

MC1

13

RW (0)

R (0)

RW (0)

RW (0)

SPI

14

RW (0)

R (0)

RW (0)

RW (0)

Thsens

15

RW (0)

R (0)

RW (0)

RW (0)

UART1

23:16

RW (0)

R (0)

RW (0)

RW (0)

HT0[7:0]

31:24

RW (0)

R (0)

RW (0)

RW (0)

HT1[7:0]

+
+

Similar to inter-processor interrupts, the base address of I/O interrupts can also be accessed using 0x1fe00000, or through the processor core’s dedicated register configuration instructions.

+
+
+

11.1.1. Accessing by Address

+
+

This access is compatible with that of processors such as the 3A3000, where either 0x1fe00000 or 0x3ff00000 can be used for the base address. +The 0x3ff00000 base address can be disabled via the disable_0x3ff0 control bit in the Routing Configuration Register.

+
+ + +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 66. I/O control register address
NameOffset AddressDescription

Intisr

0x1420

32-bit interrupt status register

Inten

0x1424

32-bit interrupt enable status register

Intenset

0x1428

32-bit set enable register

Intenclr

0x142c

32-bit clear enable register

Intedge

0x1434

32-bit trigger mode register

CORE0_INTISR

0x1440

32-bit interrupt status routed to CORE0

CORE1_INTISR

0x1448

32-bit interrupt status routed to CORE1

CORE2_INTISR

0x1450

32-bit interrupt status routed to CORE2

CORE3_INTISR

0x1458

32-bit interrupt status routed to CORE3

+
+

Four processor cores are integrated in the Loongson 3A5000, and the 32-bit interrupt sources described above can be software configured to select the target processor core for the desired interrupt. +Further, the interrupt sources can be routed to any of the processor cores INT0 to INT3. +Each of the 32 I/O interrupt sources corresponds to an 8-bit routing controller with the format and addresses shown in Description of the interrupt destination processor core routing register and Interrupt destination processor core routing register address. +The routing register uses a vector approach to routing, e.g., 0x48 indicates routing to INT2 of processor 3.

+
+
+

Starting with the 3A5000, the interrupt pin routing bits are added in a coded manner and are enabled by the CSR[0x420][49] bit control. +When this bit is enabled, the [7:4] bits in the table below change from a bitmap representation to a numeric encoding method. +Configurable values 0-7 indicate interrupt pins 0-7. +For example, in this mode, 0x28 indicates routing to INT2 on processor 3.

+
+ + ++++ + + + + + + + + + + + + + + + + +
Table 67. Description of the interrupt routing register
Bit FieldDescription

3:0

Processor core vector number for routing

7:4

Processor core interrupt pin vector number for routing

+ + ++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 68. Interrupt routing register address
NameOffset AddressDescriptionNameOffset AddressDescription

Entry0

0x1400

GPIO24/16/8/0

Entry16

0x1410

HT0-int0

Entry1

0x1401

GPIO25/17/9/1

Entry17

0x1411

HT0-int1

Entry2

0x1402

GPIO26/18/10/2

Entry18

0x1412

HT0-int2

Entry3

0x1403

GPIO27/19/11/3

Entry19

0x1413

HT0-int3

Entry4

0x1404

GPIO28/20/12/4

Entry20

0x1414

HT0-int4

Entry5

0x1405

GPIO29/21/13/5

Entry21

0x1415

HT0-int5

Entry6

0x1406

GPIO30/22/14/6

Entry22

0x1416

HT0-int6

Entry7

0x1407

GPIO31/23/15/7

Entry23

0x1417

HT0-int7

Entry8

0x1408

I2C0

Entry24

0x1418

HT1-int0

Entry9

0x1409

I2C1

Entry25

0x1419

HT1-int1

Entry10

0x140a

UART0

Entry26

0x141a

HT1-int2

Entry11

0x140b

MC0

Entry27

0x141b

HT1-int3

Entry12

0x140c

MC1

Entry28

0x141c

HT1-int4

Entry13

0x140d

SPI

Entry29

0x141d

HT1-int5

Entry14

0x140e

Thsens

Entry30

0x141e

HT1-int6

Entry15

0x140f

UART1

Entry31

0x141f

HT1-int7

+
+
+

11.1.2. Accessing by Configuration Register Instructions

+
+

In the Loongson 3A5000, the configuration registers can also be accessed through private space using the same access method as the configuration register instruction. +The offset address used by the instruction is the same as that accessed through the address. +In addition, for the convenience of users, a dedicated private interrupt status register is set for different current interrupt states of each core, as shown in the following table.

+
+ + +++++ + + + + + + + + + + + + + + +
Table 69. Processor core private interrupt status register
NameOffset AddressDescription

perCore_INTISR

0x1010

32-bit interrupt status routing to the current processor core

+
+
+
+

11.2. Extended I/O Interrupts

+
+

In addition to being compatible with the legacy I/O interrupt method, the 3A5000 supports extended I/O interrupts, which are used to distribute 256-bit interrupts on the HT bus directly to each processor core instead of forwarding them through the HT interrupt line, increasing the flexibility of I/O interrupt usage.

+
+
+

Before the core can use the extended I/O interrupt, it needs to enable the corresponding bit in the “Other function configuration register”. +This register has a base address of 0x1fe00000,It can also be accessed using the configuration register instruction (IOCSR), an offset address of 0x0420.

+
+ + +++++++ + + + + + + + + + + + + + + + + + + +
Table 70. Other function configuration register
Bit FieldNameRead/WriteReset ValueDescription

48

EXT_INT_en

RW

0x0

Extended I/O interrupt enable

+
+

In Extended I/O interrupt mode, HT interrupts can be forwarded directly across slices and distributed in rotation. +In the current version, up to s extended interrupt vectors can be supported.

+
+
+

11.2.1. Accessing by Address

+
+

The following are the associated extended I/O interrupt registers. +As with the other configuration registers, the base address can be used as 0x1fe00000, or can be accessed via the processor core’s dedicated register configuration instructions.

+
+ + +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 71. Extended I/O interrupt enable register
NameOffset AddressDescription

EXT_IOIen[63:0]

0x1600

Interrupt enable configuration for extended I/O interrupt [63:0]

EXT_IOIen[127:64]

0x1608

Interrupt enable configuration for extended I/O interrupt [127:64]

EXT_IOIen[191:128]

0x1610

Interrupt enable configuration for extended I/O interrupt [191:128]

EXT_IOIen[255:192]

0x1618

Interrupt enable configuration for extended I/O interrupt [255:192]

+ + +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 72. Extended I/O interrupt auto-rotation enable register
NameOffset AddressDescription

EXT_IOIbounce[63:0]

0x1680

Auto-rotation enable register for extended I/O interrupt [63:0]

EXT_IOIbounce[127:64]

0x1688

Auto-rotation enable register for extended I/O interrupt [127:64]

EXT_IOIbounce[191:128]

0x1690

Auto-rotation enable register for extended I/O interrupt [191:128]

EXT_IOIbounce[255:192]

0x1698

Auto-rotation enable register for extended I/O interrupt [255:192]

+ + +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 73. Extended I/O interrupt interrupt status register
NameOffset AddressDescription

EXT_IOIsr[63:0]

0x1700

Interrupt status for extended I/O interrupt [63:0]

EXT_IOIsr[127:64]

0x1708

Interrupt status for extended I/O interrupt [127:64]

EXT_IOIsr[191:128]

0x1710

Interrupt status for extended I/O interrupt [191:128]

EXT_IOIsr[255:192]

0x1718

Interrupt status for extended I/O interrupt [255:192]

+ + +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 74. Extended I/O interrupt status register for each processor core
NameOffset AddressDescription

CORE0_EXT_IOIsr[63:0]

0x1800

Interrupt status of extended I/O interrupt [63:0] routed to processor core 0

CORE0_EXT_IOIsr[127:64]

0x1808

Interrupt status of extended I/O interrupt [127:64] routed to processor core 0

CORE0_EXT_IOIsr[191:128]

0x1810

Interrupt status of extended I/O interrupt [191:128] routed to processor core 0

CORE0_EXT_IOIsr[255:192]

0x1818

Interrupt status of extended I/O interrupt [255:192] routed to processor core 0

CORE1_EXT_IOIsr[63:0]

0x1900

Interrupt status of extended I/O interrupt [63:0] routed to processor core 1

CORE1_EXT_IOIsr[127:64]

0x1908

Interrupt status of extended I/O interrupt [127:64] routed to processor core 1

CORE1_EXT_IOIsr[191:128]

0x1910

Interrupt status of extended I/O interrupt [191:128] routed to processor core 1

CORE1_EXT_IOIsr[255:192]

0x1918

Interrupt status of extended I/O interrupt [255:192] routed to processor core 1

CORE2_EXT_IOIsr[63:0]

0x1A00

Interrupt status of extended I/O interrupt [63:0] routed to processor core 2

CORE2_EXT_IOIsr[127:64]

0x1A08

Interrupt status of extended I/O interrupt [127:64] routed to processor core 2

CORE2_EXT_IOIsr[191:128]

0x1A10

Interrupt status of extended I/O interrupt [191:128] routed to processor core 2

CORE2_EXT_IOIsr[255:192]

0x1A18

Interrupt status of extended I/O interrupt [255:192] routed to processor core 2

CORE3_EXT_IOIsr[63:0]

0x1B00

Interrupt status of extended I/O interrupt [63:0] routed to processor core 3

CORE3_EXT_IOIsr[127:64]

0x1B08

Interrupt status of extended I/O interrupt [127:64] routed to processor core 3

CORE3_EXT_IOIsr[191:128]

0x1B10

Interrupt status of extended I/O interrupt [191:128] routed to processor core 3

CORE3_EXT_IOIsr[255:192]

0x1B18

Interrupt status of extended I/O interrupt [255:192] routed to processor core 3

+
+

Similar to legacy I/O interrupts, the 256-bit interrupt source for Extended I/O interrupts can be software-configured to select the target processor core for the desired interrupt.

+
+
+

However, the interrupt sources are not individually selected to route to any of the processor core interrupts INT0 through INT3, but rather the routing of INT interrupts is done in groups. +The following are the interrupt pin routing registers configured by group.

+
+
+

Starting with the 3A5000, the interrupt pin routing bits have been added in a coded manner and are enabled by the CSR[0x420][49] bit control. +When this bit is enabled, the [3:0] bits in the table below changes from a bitmap representation to a numeric encoding method. +Configurable values 0-7 indicate interrupt pins 0-7. +For example, in this mode, 0x2 indicates routing to INT2.

+
+ + ++++ + + + + + + + + + + + + + + + + +
Table 75. Description of the interrupt pin routing register
Bit FieldDescription

3:0

Processor core interrupt pin vector number for routing

7:4

Reserved

+ + +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 76. Interrupt routing register address
NameOffset AddressDescription

EXT_IOImap0

0x14C0

Pin routing method of EXT_IOI[31:0]

EXT_IOImap1

0x14C1

Pin routing method of EXT_IOI[63:32]

EXT_IOImap2

0x14C2

Pin routing method of EXT_IOI[95:64]

EXT_IOImap3

0x14C3

Pin routing method of EXT_IOI[127:96]

EXT_IOImap4

0x14C4

Pin routing method of EXT_IOI[159:128]

EXT_IOImap5

0x14C5

Pin routing method of EXT_IOI[191:160]

EXT_IOImap6

0x14C6

Pin routing method of EXT_IOI[223:192]

EXT_IOImap7

0x14C7

Pin routing method of EXT_IOI[255:224]

+
+

Each interrupt source additionally corresponds to an 8-bit routing controller with the format and address shown in Description of the interrupt destination processor core routing register and Interrupt destination processor core routing register address. +The [7:4] bits are used to select the real node routing vector in Interrupt destination node mapping method configuration. +The routing register uses a vector approach for routing, e.g., 0x48 indicates a route to processor core 3 of the node referred to by EXT_IOI_node_type4.

+
+ + ++++ + + + + + + + + + + + + + + + + +
Table 77. Description of the interrupt destination processor core routing register
Bit FieldDescription

3:0

Processor core vector number for routing

7:4

Selection of node mapping method of routing (as configured in Interrupt destination node mapping method configuration)

+
+

Note that when using the rotating distribution mode (corresponding to an EXT_IOIbounce of 1), rotate on the fully mapped mode of node number to processor core number. +The setting of EXT_IOIbounce should follow the associated route mapping configuration.

+
+
+

For example, when the setting in the tables above is 0x27 and the setting of EXT_IOI_node_type2 in the the tables below is 0x0013, the interrupt will rotate in turn on node 0 core 0, node 0 core 1, node 0 core 2, node 1 core 0, node 1 core 1, node 1 core 2, node 4 core 0, node 4 core 1, and node 4 core 2.

+
+
+

When using fixed distribution mode (corresponding to an EXT_IOIbounce of 0), only one bit on the bitmap of the node number is allowed to be 1, or all 0 values, corresponding to local triggering.

+
+ + +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 78. Interrupt destination processor core routing register address
NameOffset AddressDescription

EXT_IOImap_Core0

0x1C00

Processor core routing method of EXT_IOI[0]

EXT_IOImap_Core1

0x1C01

Processor core routing method of EXT_IOI[1]

EXT_IOImap_Core2

0x1C02

Processor core routing method of EXT_IOI[2]

…​…​

EXT_IOImap_Core254

0x1CFE

Processor core routing method of EXT_IOI[254]

EXT_IOImap_Core255

0x1CFF

Processor core routing method of EXT_IOI[255]

+ + +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 79. Interrupt destination node mapping method configuration
NameOffset AddressDescription

EXT_IOI_node_type0

0x14A0

Mapping vector type 0 for 16 nodes (software configuration)

EXT_IOI_node_type1

0x14A2

Mapping vector type 1 for 16 nodes (software configuration)

EXT_IOI_node_type2

0x14A4

Mapping vector type 2 for 16 nodes (software configuration)

…​…​

EXT_IOI_node_type15

0x14BE

Mapping vector type 15 for 16 nodes (software configuration)

+
+
+

11.2.2. Accessing by Configuration Register Instructions

+
+

The biggest difference when accessing using the processor core’s configuration register instructions is that access to the processor core’s interrupt status registers becomes private, and each core only needs to issue a query request to the same address to get the current core’s interrupt status.

+
+ + +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 80. Extended I/O interrupt status register for the current processor core
NameOffset AddressDescription

perCore_EXT_IOIsr[63:0]

0x1800

Interrupt status of the extended I/O interrupt [63:0] routed to the current processor core

perCore_EXT_IOIsr[127:64]

0x1808

Interrupt status of the extended I/O interrupt [127:64] routed to the current processor core

perCore_EXT_IOIsr[191:128]

0x1810

Interrupt status of the extended I/O interrupt [191:128] routed to the current processor core

perCore_EXT_IOIsr[255:192]

0x1818

Interrupt status of the extended I/O interrupt [255:192] routed to the current processor core

+
+
+

11.2.3. Extended I/O Interrupt Trigger Register

+
+

To support the dynamic distribution of extended I/O interrupts, an extended I/O interrupt trigger register is added to the configuration register to set the corresponding I/O interrupts to be set. +This register can be used for debugging or testing interrupts in normal times.

+
+
+

The description of this register is as follows:

+
+ + ++++++ + + + + + + + + + + + + + + + + +
Table 81. Extended I/O interrupt trigger register
NameOffset AddressRead/WriteDescription

EXT_IOI_send

0x1140

WO

Extended I/O interrupt setting register

+

[7:0] is the interrupt vector expected to be set

+
+
+

11.2.4. Difference in Handling Between Extended I/O Interrupts and Legacy HT Interrupts

+
+

With legacy HT interrupt processing, HT interrupts are processed internally by the HT controller and mapped directly to the 256 interrupt vectors on the HT configuration registers, and then the 256 interrupt vectors are grouped to generate 4 or 8 interrupts that are routed to the various processor cores. +Due to the legacy interrupt line connection, no cross-chip interrupts can be generated directly, so all HT I/O interrupts can only be handled directly by a single chip. +On the other hand, the interrupts distributed by the hardware within the chip are only in units of the final 4 or 8 interrupts and cannot be handled on a bit-by-bit basis, which leads to the problem of poor hardware interrupt distribution.

+
+
+

With the extended I/O interrupt method, HT interrupts are sent directly from the HT controller to the chip’s interrupt controller for processing, and the interrupt controller can directly get 256 Instead of the previous 4 or 8 interrupts, each of these 256-bit interrupts can be routed and distributed independently, and can be distributed and rotated across slices.

+
+
+

With Extended I/O interrupts, the software processing is slightly different than with legacy HT interrupts.

+
+
+

With legacy HT interrupts, the kernel looks directly at the interrupt vector of the HT controller (typically 0x90000efdfb000080) and then processes the interrupts by bit, regardless of how the routing mode is configured.

+
+
+

After using Extended I/O interrupts, the cores go directly to the Extended I/O status register (configuration space 0x1800) to read the interrupt status for processing. +Each core will only read the interrupt’s own interrupt status and process it, and there will be no interference between different cores.

+
+
+
+
+
+
+

12. Temperature Sensor

+
+
+

12.1. Real-time Temperature Collection

+
+

Two temperature sensors are integrated inside the Loongson 3A5000, which can be observed through the sampling register starting at 0x1FE00198, and can be controlled using the flexible high and low temperature interrupt alarm or auto-tuning function. +The corresponding bits of the temperature sensors in the sampling register are as follows (base address is 0x1FE00000, offset address is 0x0198):

+
+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 82. Description of temperature collection register
Bit FieldNameRead/WriteReset ValueDescription

24

Thsens0_overflow

R

Temperature sensor 0 overflow

25

Thsens1_overflow

R

Temperature sensor 1 overflow

47:32

Thsens0_out

R

Temperature sensor 0 centigrade temperature

+

Node temperature=Thens0_out *731/0x4000-273

+

Temperature range: -40 degree - 125 degree

65:48

Thsens1_out

R

Temperature sensor 1 centigrade temperature

+

Node temperature=Thens0_out *731/0x4000-273

+

Temperature range: -40 degree - 125 degree

+
+

The control registers can be set to enable over preset temperature interrupt, under preset temperature interrupt and high temperature auto down function.

+
+
+

In addition, the current centigrade temperature can be read directly using the new centigrade temperature register. +This register can also be accessed using a read operation with base address 0x1FE00000 or 0x3FF00000, or directly using a configuration register instruction with offset 0x0428. +The register is described as follows:

+
+ + ++++++ + + + + + + + + + + + + + + + + +
Table 83. Extended I/O interrupt trigger register
NameOffset AddressRead/WriteDescription

Thsens_Temperature

0x0428

R

Temperature sensor centigrade temperature

+
+
+

12.2. High/Low Temperature Interrupt Trigger

+
+

For the high and low temperature interrupt alarm function, there are 4 groups of control registers to set the threshold value. +Each group of registers contains the following three control bits:

+
+
+

GATE: Set the threshold value for high or low temperature. +When the input temperature is higher than the high temperature threshold or lower than the low temperature threshold, an interrupt will be generated. +Note that the Gate value should be set to the 16-bit value corresponding to the 0x198 register, not the centigrade temperature.

+
+
+

EN: Interrupt enable control. +The setting of this set of registers is valid only after setting 1.

+
+
+

SEL: Input temperature selection. +This register is used to configure which sensor’s temperature is selected as input. +Either 0 or 1 can be used.

+
+
+

The high temperature interrupt control register contains four sets of setting bits to control the triggering of high temperature interrupts; the low temperature interrupt control register contains four sets of setting bits to control the triggering of low temperature interrupts. +There is another set of registers for displaying the interrupt status, corresponding to the high-temperature interrupt and low-temperature interrupt, respectively, and any write operation to this register will clear the interrupt status.

+
+
+

These registers are described below, and their base addresses are 0x1fe00000,It can also be accessed using the configuration register instruction (IOCSR):

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 84. Description of high/low temperature interrupt register
RegisterAddressRead/WriteDescription

High temperature interrupt control register Thsens_int_ctrl_Hi

0x1460

RW

[7:0]: Hi_gate0: high temperature threshold 0, above which an interrupt will be generated

+

[8:8]: Hi_en0: high temperature interrupt enable 0

+

[11:10]: Hi_Sel0: select temperature sensor input source for high temperature interrupt 0

+

[23:16]: Hi_gate1: high temperature threshold 1, above which an interrupt will be generated

+

[24:24]: Hi_en1: high temperature interrupt enable 1

+

[27:26]: Hi_Sel1: select temperature sensor input source for high temperature interrupt 1

+

[39:32]: Hi_gate2: high temperature threshold 2, above which an interrupt will be generated

+

[40:40]: Hi_en2: high temperature interrupt enable 2

+

[43:42]: Hi_Sel2: select temperature sensor input source for high temperature interrupt 2

+

[55:48]: Hi_gate3: high temperature threshold 3, above which an interrupt will be generated

+

[56:56]: Hi_en3: high temperature interrupt enable 3

+

[59:58]: Hi_Sel3: select temperature sensor input source for high temperature interrupt 3

Low temperature interrupt control register Thsens_int_ctrl_Lo

0x1468

RW

[7:0]: Lo_gate0: low temperature threshold 0, below which an interrupt will be generated

+

[8:8]: Lo_en0: low temperature interrupt enable 0

+

[11:10]: Lo_Sel0: select temperature sensor input source for low temperature interrupt 0

+

[23:16]: Lo_gate1: low temperature threshold 1, below which an interrupt will be generated

+

[24:24]: Lo_en1: low temperature interrupt enable 1

+

[27:26]: Lo_Sel1: select temperature sensor input source for low temperature interrupt 1

+

[39:32]: Lo_gate2: low temperature threshold 2, below which an interrupt will be generated

+

[40:40]: Lo_en2: low temperature interrupt enable 2

+

[43:42]: Lo_Sel2: select temperature sensor input source for low temperature interrupt 2

+

[55:48]: Lo_gate3: low temperature threshold 3, below which an interrupt will be generated

+

[56:56]: Lo_en3: low temperature interrupt enable 3

+

[59:58]: Lo_Sel3: select temperature sensor input source for low temperature interrupt 3

Interrupt status register Thsens_int_status/clr

0x1470

RW

Interrupt status register; write 1 to clear the interrupt

+

[0]: high temperature interrupt trigger

+

[1]: low temperature interrupt trigger

High order bits of high temperature interrupt control register Thsens_int_up

0x1478

RW

[7:0]: Hi_gate0: high 8-bit

+

[15:8]: Hi_gate1: high 8-bit

+

[23:16]: Hi_gate2: high 8-bit

+

[31:24]: Hi_gate3: high 8-bit

+

[39:32]: Lo_gate0: high 8-bit

+

[47:40]: Lo_gate1: high 8-bit

+

[55:48]: Lo_gate2: high 8-bit

+

[63:56]: Lo_gate3: high 8-bit

+
+
+

12.3. High Temperature Automatic Underclock Configuration

+
+

In order to ensure the operation of the chip in a high temperature environment, it can be set to make the high temperature automatic frequency reduction, so that the chip is actively clocked when it exceeds the preset range to achieve the effect of reducing the chip flip rate.

+
+
+

For the high-temperature downconversion function, there are four sets of control registers to set its behavior. +Each set of registers contains the following four control bits:

+
+
+

GATE: Set the threshold value for high or low temperature. +When the input temperature is higher than the high temperature threshold or lower than the low temperature threshold, the frequency dividing operation will be triggered.

+
+
+

EN: Enable control. +The setting of this group of registers is valid only after setting 1.

+
+
+

SEL: Input temperature selection. +This register is used to configure which sensor’s temperature is selected as input.

+
+
+

FREQ: Frequency division number. +When the dividing operation is triggered, the clock is divided using the preset FREQ. +The dividing mode is controlled by freqscale_mode_node.

+
+
+

Its base address is 0x1fe00000,It can also be accessed using the configuration register instruction (IOCSR).

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + +
Table 85. Description of high-temperature underclock control register
RegisterAddressRead/WriteDescription

High-temperature underclock control register Thsens_freq_scale

0x1480

RW

The four groups of configurations are prioritized from highest to lowest

+

[7:0]: Scale_gate0: high temperature threshold 0, beyond which the frequency will be reduced

+

[8:8]: Scale_en0: high temperature underclock enable 0

+

[11:10]: Scale_Sel0: select temperature sensor input source for high temperature underclock 0

+

[14:12]: Scale_freq0: frequency division value at underclock

+

[23:16]: Scale_gate1: high temperature threshold 1, beyond which the frequency will be reduced

+

[24:24]: Scale_en1: high temperature underclock enable 1

+

[27:26]: Scale_Sel1: select temperature sensor input source for high temperature underclock 1

+

[30:28]: Scale_freq1: frequency division value at underclock

+

[39:32]: Scale_gate2: high temperature threshold 2, beyond which the frequency will be reduced

+

[40:40]: Scale_en2: high temperature underclock enable 2

+

[43:42]: Scale_Sel2: select temperature sensor input source for high temperature underclock 2

+

[46:44]: Scale_freq2: frequency division value at underclock

+

[55:48]: Scale_gate3: high temperature threshold 3, beyond which the frequency will be reduced

+

[56:56]: Scale_en3: high temperature underclock enable 3

+

[59:58]: Scale_Sel3: select temperature sensor input source for high temperature underclock 3

+

[62:60]: Scale_freq3: frequency division value at underclock

Thsens_freq_scale_up

0x1490

RW

High order bits of temperature sensor control register

+

[7:0]: Scale_Hi_gate0: high 8-bit

+

[15:8]: Scale_Hi_gate1: high 8-bit

+

[23:16]: Scale_Hi_gate2: high 8-bit

+

[31:24]: Scale_Hi_gate3: high 8-bit

+

[39:32]: Scale_Lo_gate0: high 8-bit

+

[47:40]: Scale_Lo_gate1: high 8-bit

+

[55:48]: Scale_Lo_gate2: high 8-bit

+

[63:56]: Scale_Lo_gate3: high 8-bit

+
+
+

12.4. Temperature Status Detection and Control

+
+

The pins PROCHOTn and THERMTRIPn are used for temperature status detection and control, which are multiplexed with GPIO14 and GPIO15 respectively. +PROCHOTn can be used as both input and output, while THERMTRIPn has only output function. +When PROCHOTn is used as an input, the chip is controlled by the external temperature detection circuit, and the external temperature detection circuit can set PROCHOTn to 0 when it needs to lower the chip temperature, and the chip will take down frequency measures after receiving this low level. +When PROCHOTn is an output, the chip can output high-temperature interrupts, and select one of the four interrupts set by the high-temperature interrupt control register through the prochotn_o_sel register. +Select one of the four interrupts set in the high-temperature interrupt control register as the external high-temperature interrupt.

+
+
+

THERMTRIPn as output is selected by the chip from the 4 interrupts set by the high-temperature interrupt control register through the thermtripn_o_sel register as the outgoing high-temperature interrupt.

+
+
+

Although both THERMTRIPn and PROCHOTn are external high temperature interrupts, THERMTRIPn has a higher degree of urgency than PROCHOTn. +When PROCHOTn is set, the external temperature control circuit can also take certain measures, such as increasing the fan speed. +In contrast, when THERMTRIPn is set, the external power control circuitry should take direct emergency power-off measures.

+
+
+

The specific control registers are as follows:

+
+ + ++++++ + + + + + + + + + + + + + + + + +
Table 86. Description of temperature status detection and control register
RegisterAddressRead/WriteDescription

Temperature status detection and control register Thsens_hi_ctrl

0x1498

RW

[0:0]: prochotn_oe: PROCHOTn pin output enable control, 0 for output, 1 for input

+

[5:4]: prochotn_o_sel: PROCHOTn high temperature interrupt output selection

+

[10:8]: prochotn_freq_scale: PROCHOTn frequency division value when input is valid

+

[17:16]: thermtripn_o_sel: THERMTRIPn high temperature interrupt output selection

+
+
+

12.5. Control of temperature sensors

+
+

The 3A5000 has 4 internal temperature sensors, which can be configured via registers to adjust the temperature/voltage monitoring, monitoring point configuration and monitoring frequency, etc. +The output of each temperature sensor can also be directly observed for debugging (base address is 0x1FE00000,It can also be accessed using the configuration register instruction (IOCSR), offset address of temperature sensor configuration register is 0x01580+vtsensor_id<<4, offset address of temperature sensor data register is 0x01588+vtsensor_id<<4).

+
+
+

Note that the voltage monitoring function is currently not available

+
+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 87. Description of temperature sensor configuration register
Bit FieldNameRead/WriteReset ValueDescription

0

Thsens_trigger

RW

0

Enable temperature sensor configuration. +If set, monitoring mode and monitoring point can be selected by thsens_mode and thsens_cluster; 0 is the default temperature monitoring mode and the monitoring point is configured by temp_cluster

2

Thsens_mode

RW

0

0: temperature mode; 1: voltage mode

3

Thsens_datarate

RW

0

Monitoring frequency:

+

0 - 10-20Hz

+

1 - 325-650Hz

6:4

Thsens_cluster

RW

0

Sensor monitoring point configuration: 0 is local monitoring point, 1-7 is remote monitoring point

8

Temp_valid

RW

0

Enable the temperature sensor output and replace the value of Thsens0_out and Thsens0_overflow in CSR[0x198] with the temperature monitoring value of this temperature sensor.

11:9

Temp_cluster

RW

0

Temperature sensor output monitoring point selection. +It is disabled when Thsens_trigger is enabled

+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 88. Description of temperature sensor data register
Bit FieldNameRead/WriteReset ValueDescription

3

Out_mode

R

0

Monitoring mode for sensor configuration

+

0: temperature mode; 1: voltage mode

6:4

Out_cluster

R

0

Monitoring points for sensor configuration

7

Overflow

R

0

Overflow of sensor monitoring values

29:16

Data

R

0

Sensor readout monitoring values

+
+

Calculation of the readout value:

+
+
+

Node temperature = data*731/0x4000 - 273 (temperature range -40 degrees - 125 degrees)

+
+
+

Voltage = data*1.226/0x1000

+
+
+
+
+
+

13. DDR4 SDRAM Controller Configuration

+
+
+

The Loongson 3A5000 processor’s internally integrated memory controller is designed to comply with the DDR4 SDRAM industry standard (JESD79-4).

+
+
+

13.1. Introduction to DDR4 SDRAM Controller Functions

+
+

The Loongson 3A5000 processor supports both DDP and 3DS packaging modes. +The DDP supports up to 8 CSs (implemented by 8 DDR3/DDR4 SDRAM chip select signals, i.e., 4 double-sided memory sticks) and the 3DS supports up to 4 CSs (implemented by 8 DDR4 SDRAM chip select signals, i.e., 32 logical RANKS). +A total of 22 bits of address bus (i.e., 18 bits of row address bus, 2 bits of logical Bank bus and 2 bits of logical Bank Group bus, where the row address bus is multiplexed with RASn, CASn, and Wen).

+
+
+

The Loongson 3A5000 processor can adjust the DDR4 controller parameter settings to support different memory chip types when they are specifically selected for use. +The maximum supported chip selection (CS_n) is 8, the number of logical RANKS (Chip ID) is 8, the number of row addresses (ROW) is 18, the number of column addresses (COL) is 12, the number of logical body selections (BANK) is 2 (DDR4), and the number of logical body groups (BANK Group) is 2. +The multiplexing relationship between CS_n and Chip ID can be matched, please see DDR4 SDRAM Parameter Configuration Format for details.

+
+
+

The physical address of the memory request sent by the CPU can be mapped in many different ways according to different configurations inside the controller.

+
+
+

The memory control circuitry integrated in the Loongson 3A5000 processor only accepts memory read/write requests from the processor or external devices, and is in the Slave State for all memory read/write operations.

+
+
+

The memory controller in the Loongson 3A5000 processor has the following features:

+
+
+
    +
  • +

    Fully flowing operation of commands, read and write data on the interface.

    +
    • +
  • +

    Memory command merging and sequencing to improve overall bandwidth.

    +
    • +
  • +

    Configuration register read and write ports, which can modify the basic parameters of memory devices.

    +
    • +
  • +

    Built-in dynamic delay compensation circuit (DCC) for reliable sending and receiving of data.

    +
    • +
  • +

    ECC function can detect 1-bit and 2-bit errors on the data path and can automatically correct 1-bit errors.

    +
    • +
  • +

    DDR3/4 SDRAM support and parameter configuration supports x4, x8, and x16 particles.

    +
    • +
  • +

    Controller to PHY frequency ratio of 1/2.

    +
    • +
  • +

    Support data transport rate range from 800Mbps to 3200Mbps.

    +
    • +
+
+
+
+

13.2. DDR4 SDRAM Parameter Configuration Format

+
+
+

13.2.1. Parameter List of the Memory Controller

+ + +++++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 89. Software-visible parameter list of the memory controller
Offset63:5555:4847:4039:3231:2423:1615:87:0

PHY

0x0000

version(RD)

0x0008

x4_mode

ddr3_mode

capability(RD)

0x0010

dram_init(RD)

init_start

0x0018

0x0020

preamble2

rdfifo_valid

0x0028

rdfifo_empty(RD)

Overflow(RD)

0x0030

dll_value(RD)

dll_init_done(RD)

dll_lock_mode

dll_bypass

dll_adjj_cnt

dll_increment

dll_start_point

0x0038

dll_dbl_fix

dll_close_disable

dll_ck

0x0040

dbl_ctrl_ckca

dll_dbl_ckca

0x0048

pll_ctrl_ckca

pll_lock_ckca(RD)

dll_lock_ckca(RD)

clken_ckca

clksel_ckca

0x0050

dbl_ctrl_ds_0

dll_dbl_ds_0

0x0058

pll_ctrl_ds_0

pll_lock_ds_0(RD)

dll_lock_ds_0(RD)

clken_ds_0

clksel_ds_0

0x0060

dbl_ctrl_ds_1

dll_dbl_ds_1

0x0068

pll_ctrl_ds_1

pll_lock_ds_1(RD)

dll_lock_ds_1(RD)

clken_ds_1

clksel_ds_1

0x0070

dbl_ctrl_ds_2

dll_dbl_ds_2

0x0078

pll_ctrl_ds_2

pll_lock_ds_2(RD)

dll_lock_ds_2(RD)

clken_ds_2

clksel_ds_2

0x0080

dbl_ctrl_ds_3

dll_dbl_ds_3

0x0088

pll_ctrl_ds_3

pll_lock_ds_3(RD)

dll_lock_ds_3(RD)

clken_ds_3

clksel_ds_3

0x0090

dbl_ctrl_ds_4

dll_dbl_ds_4

0x0098

pll_ctrl_ds_4

pll_lock_ds_4(RD)

dll_lock_ds_4(RD)

clken_ds_4

clksel_ds_4

0x00a0

dbl_ctrl_ds_5

dll_dbl_ds_5

0x00a8

pll_ctrl_ds_5

pll_lock_ds_5(RD)

dll_lock_ds_5(RD)

clken_ds_5

clksel_ds_5

0x00b0

dbl_ctrl_ds_6

dll_dbl_ds_6

0x00b8

pll_ctrl_ds_6

pll_lock_ds_6(RD)

dll_lock_ds_6(RD)

clken_ds_6

clksel_ds_6

0x00c0

dbl_ctrl_ds_7

dll_dbl_ds_7

0x00c8

pll_ctrl_ds_7

pll_lock_ds_7(RD)

dll_lock_ds_7(RD)

clken_ds_7

clksel_ds_7

0x00d0

dbl_ctrl_ds_8

dll_dbl_ds_8

0x00d8

pll_ctrl_ds_8

pll_lock_ds_8(RD)

dll_lock_ds_8(RD)

clken_ds_8

clksel_ds_8

0x00e0

vrefclk_inv

vref_sample

vref_num

vref_dly

dll_vref

…​…​

0x0100

dll_1xdly_0

dll_1xgen_0

dll_wrdqs_0

dll_wrdq_0

0x0108

dll_gate_0

dll_rddqs1_0

dll_rddqs0_0

0x0110

rdodt_ctrl_0

rdgate_len_0

rdgate_mode_0

rdgate_ctrl_0

dqs_oe_ctrl_0

dq_oe_ctrl_0

0x0118

dly_2x_0

redge_sel_0

rddqs_phase_0(RD)

0x0120

w_bdly0_0[31:28]

w_bdly0_0[27:24]

w_bdly0_0[23:20]

w_bdly0_0[19:16]

w_bdly0_0[15:12]

w_bdly0_0[11:8]

w_bdly0_0[7:4]

w_bdly0_0[3:0]

0x0128

w_bdly0_0[59:56]

w_bdly0_0[55:52]

w_bdly0_0[51:48]

w_bdly0_0[47:44]

w_bdly0_0[43:40]

w_bdly0_0[39:36]

w_bdly0_0[35:32]

0x0130

w_bdly1_0[24:21]

w_bdly1_0[20:18]

w_bdly1_0[17:15]

w_bdly1_0[14:12]

w_bdly1_0[11:9]

w_bdly1_0[8:6]

w_bdly1_0[5:3]

w_bdly1_0[2:0]

0x0138

w_bdly1_0[27:26]

0x0140

rg_bdly_0[7:4]

rg_bdly_0[3:0]

0x0148

0x0150

rdqsp_bdly_0[31:28]

rdqsp_bdly_0[27:24]

rdqsp_bdly_0[23:20]

rdqsp_bdly_0[19:16]

rdqsp_bdly_0[15:12]

rdqsp_bdly_0[11:8]

rdqsp_bdly_0[7:4]

rdqsp_bdly_0[3:0]

0x0158

rdqsp_bdly_0[35:32]

0x0160

rdqsn_bdly_0[31:28]

rdqsn_bdly_0[27:24]

rdqsn_bdly_0[23:20]

rdqsn_bdly_0[19:16]

rdqsn_bdly_0[15:12]

rdqsn_bdly_0[11:8]

rdqsn_bdly_0[7:4]

rdqsn_bdly_0[3:0]

0x0168

rdqsn_bdly_0[35:32]

0x0170

rdq_bdly_0[24:21]

rdq_bdly_0[20:18]

rdq_bdly_0[17:15]

rdq_bdly_0[14:12]

rdq_bdly_0[11:9]

rdq_bdly_0[8:6]

rdq_bdly_0[5:3]

rdq_bdly_0[2:0]

0x0178

rdq_bdly_0[27:26]

0x0180

dll_1xdly_1

dll_1xgen_1

dll_wrdqs_1

dll_wrdq_1

0x0188

dll_gate_1

dll_rddqs1_1

dll_rddqs0_1

0x0190

rdodt_ctrl_1

rdgate_len_1

rdgate_mode_1

rdgate_ctrl_1

dqs_oe_ctrl_1

dq_oe_ctrl_1

0x0198

dly_2x_1

redge_sel_1

rddqs_phase_1(RD)

0x01a0

w_bdly0_1[31:28]

w_bdly0_1[27:24]

w_bdly0_1[23:20]

w_bdly0_1[19:16]

w_bdly0_1[15:12]

w_bdly0_1[11:8]

w_bdly0_1[7:4]

w_bdly0_1[3:0]

0x01a8

w_bdly0_1[59:56]

w_bdly0_1[55:52]

w_bdly0_1[51:48]

w_bdly0_1[47:44]

w_bdly0_1[43:40]

w_bdly0_1[39:36]

w_bdly0_1[35:32]

0x01b0

w_bdly1_1[24:21]

w_bdly1_1[20:18]

w_bdly1_1[17:15]

w_bdly1_1[14:12]

w_bdly1_1[11:9]

w_bdly1_1[8:6]

w_bdly1_1[5:3]

w_bdly1_1[2:0]

0x01b8

w_bdly1_1[27:26]

0x01c0

rg_bdly_1[7:4]

rg_bdly_1[3:0]

0x01c8

0x01d0

rdqsp_bdly_1[31:28]

rdqsp_bdly_1[27:24]

rdqsp_bdly_1[23:20]

rdqsp_bdly_1[19:16]

rdqsp_bdly_1[15:12]

rdqsp_bdly_1[11:8]

rdqsp_bdly_1[7:4]

rdqsp_bdly_1[3:0]

0x01d8

rdqsp_bdly_1[35:32]

0x01e0

rdqsn_bdly_1[31:28]

rdqsn_bdly_1[27:24]

rdqsn_bdly_1[23:20]

rdqsn_bdly_1[19:16]

rdqsn_bdly_1[15:12]

rdqsn_bdly_1[11:8]

rdqsn_bdly_1[7:4]

rdqsn_bdly_1[3:0]

0x01e8

rdqsn_bdly_1[35:32]

0x01f0

rdq_bdly_1[24:21]

rdq_bdly_1[20:18]

rdq_bdly_1[17:15]

rdq_bdly_1[14:12]

rdq_bdly_1[11:9]

rdq_bdly_1[8:6]

rdq_bdly_1[5:3]

rdq_bdly_1[2:0]

0x01f8

rdq_bdly_1[27:26]

0x0200

dll_1xdly_2

dll_1xgen_2

dll_wrdqs_2

dll_wrdq_2

0x0208

dll_gate_2

dll_rddqs1_2

dll_rddqs0_2

0x0210

rdodt_ctrl_2

rdgate_len_2

rdgate_mode_2

rdgate_ctrl_2

dqs_oe_ctrl_2

dq_oe_ctrl_2

0x0218

dly_2x_2

redge_sel_2

rddqs_phase_2(RD)

0x0220

w_bdly0_2[31:28]

w_bdly0_2[27:24]

w_bdly0_2[23:20]

w_bdly0_2[19:16]

w_bdly0_2[15:12]

w_bdly0_2[11:8]

w_bdly0_2[7:4]

w_bdly0_2[3:0]

0x0228

w_bdly0_2[59:56]

w_bdly0_2[55:52]

w_bdly0_2[51:48]

w_bdly0_2[47:44]

w_bdly0_2[43:40]

w_bdly0_2[39:36]

w_bdly0_2[35:32]

0x0230

w_bdly1_2[24:21]

w_bdly1_2[20:18]

w_bdly1_2[17:15]

w_bdly1_2[14:12]

w_bdly1_2[11:9]

w_bdly1_2[8:6]

w_bdly1_2[5:3]

w_bdly1_2[2:0]

0x0238

w_bdly1_2[27:26]

0x0240

rg_bdly_2[7:4]

rg_bdly_2[3:0]

0x0248

0x0250

rdqsp_bdly_2[31:28]

rdqsp_bdly_2[27:24]

rdqsp_bdly_2[23:20]

rdqsp_bdly_2[19:16]

rdqsp_bdly_2[15:12]

rdqsp_bdly_2[11:8]

rdqsp_bdly_2[7:4]

rdqsp_bdly_2[3:0]

0x0258

rdqsp_bdly_2[35:32]

0x0260

rdqsn_bdly_2[31:28]

rdqsn_bdly_2[27:24]

rdqsn_bdly_2[23:20]

rdqsn_bdly_2[19:16]

rdqsn_bdly_2[15:12]

rdqsn_bdly_2[11:8]

rdqsn_bdly_2[7:4]

rdqsn_bdly_2[3:0]

0x0268

rdqsn_bdly_2[35:32]

0x0270

rdq_bdly_2[24:21]

rdq_bdly_2[20:18]

rdq_bdly_2[17:15]

rdq_bdly_2[14:12]

rdq_bdly_2[11:9]

rdq_bdly_2[8:6]

rdq_bdly_2[5:3]

rdq_bdly_2[2:0]

0x0278

rdq_bdly_2[27:26]

0x0280

dll_1xdly_3

dll_1xgen_3

dll_wrdqs_3

dll_wrdq_3

0x0288

dll_gate_3

dll_rddqs1_3

dll_rddqs0_3

0x0290

rdodt_ctrl_3

rdgate_len_3

rdgate_mode_3

rdgate_ctrl_3

dqs_oe_ctrl_3

dq_oe_ctrl_3

0x0298

dly_2x_3

redge_sel_3

rddqs_phase_3(RD)

0x02a0

w_bdly0_3[31:28]

w_bdly0_3[27:24]

w_bdly0_3[23:20]

w_bdly0_3[19:16]

w_bdly0_3[15:12]

w_bdly0_3[11:8]

w_bdly0_3[7:4]

w_bdly0_3[3:0]

0x02a8

w_bdly0_3[59:56]

w_bdly0_3[55:52]

w_bdly0_3[51:48]

w_bdly0_3[47:44]

w_bdly0_3[43:40]

w_bdly0_3[39:36]

w_bdly0_3[35:32]

0x02b0

w_bdly1_3[24:21]

w_bdly1_3[20:18]

w_bdly1_3[17:15]

w_bdly1_3[14:12]

w_bdly1_3[11:9]

w_bdly1_3[8:6]

w_bdly1_3[5:3]

w_bdly1_3[2:0]

0x02b8

w_bdly1_3[27:26]

0x02c0

rg_bdly_3[7:4]

rg_bdly_3[3:0]

0x02c8

0x02d0

rdqsp_bdly_3[31:28]

rdqsp_bdly_3[27:24]

rdqsp_bdly_3[23:20]

rdqsp_bdly_3[19:16]

rdqsp_bdly_3[15:12]

rdqsp_bdly_3[11:8]

rdqsp_bdly_3[7:4]

rdqsp_bdly_3[3:0]

0x02d8

rdqsp_bdly_3[35:32]

0x02e0

rdqsn_bdly_3[31:28]

rdqsn_bdly_3[27:24]

rdqsn_bdly_3[23:20]

rdqsn_bdly_3[19:16]

rdqsn_bdly_3[15:12]

rdqsn_bdly_3[11:8]

rdqsn_bdly_3[7:4]

rdqsn_bdly_3[3:0]

0x02e8

rdqsn_bdly_3[35:32]

0x02f0

rdq_bdly_3[24:21]

rdq_bdly_3[20:18]

rdq_bdly_3[17:15]

rdq_bdly_3[14:12]

rdq_bdly_3[11:9]

rdq_bdly_3[8:6]

rdq_bdly_3[5:3]

rdq_bdly_3[2:0]

0x02f8

rdq_bdly_3[27:26]

0x0300

dll_1xdly_4

dll_1xgen_4

dll_wrdqs_4

dll_wrdq_4

0x0308

dll_gate_4

dll_rddqs1_4

dll_rddqs0_4

0x0310

rdodt_ctrl_4

rdgate_len_4

rdgate_mode_4

rdgate_ctrl_4

dqs_oe_ctrl_4

dq_oe_ctrl_4

0x0318

dly_2x_4

redge_sel_4

rddqs_phase_4(RD)

0x0320

w_bdly0_4[31:28]

w_bdly0_4[27:24]

w_bdly0_4[23:20]

w_bdly0_4[19:16]

w_bdly0_4[15:12]

w_bdly0_4[11:8]

w_bdly0_4[7:4]

w_bdly0_4[3:0]

0x0328

w_bdly0_4[59:56]

w_bdly0_4[55:52]

w_bdly0_4[51:48]

w_bdly0_4[47:44]

w_bdly0_4[43:40]

w_bdly0_4[39:36]

w_bdly0_4[35:32]

0x0330

w_bdly1_4[24:21]

w_bdly1_4[20:18]

w_bdly1_4[17:15]

w_bdly1_4[14:12]

w_bdly1_4[11:9]

w_bdly1_4[8:6]

w_bdly1_4[5:3]

w_bdly1_4[2:0]

0x0338

w_bdly1_4[27:26]

0x0340

rg_bdly_4[7:4]

rg_bdly_4[3:0]

0x0348

0x0350

rdqsp_bdly_4[31:28]

rdqsp_bdly_4[27:24]

rdqsp_bdly_4[23:20]

rdqsp_bdly_4[19:16]

rdqsp_bdly_4[15:12]

rdqsp_bdly_4[11:8]

rdqsp_bdly_4[7:4]

rdqsp_bdly_4[3:0]

0x0358

rdqsp_bdly_4[35:32]

0x0360

rdqsn_bdly_4[31:28]

rdqsn_bdly_4[27:24]

rdqsn_bdly_4[23:20]

rdqsn_bdly_4[19:16]

rdqsn_bdly_4[15:12]

rdqsn_bdly_4[11:8]

rdqsn_bdly_4[7:4]

rdqsn_bdly_4[3:0]

0x0368

rdqsn_bdly_4[35:32]

0x0370

rdq_bdly_4[24:21]

rdq_bdly_4[20:18]

rdq_bdly_4[17:15]

rdq_bdly_4[14:12]

rdq_bdly_4[11:9]

rdq_bdly_4[8:6]

rdq_bdly_4[5:3]

rdq_bdly_4[2:0]

0x0378

rdq_bdly_4[27:26]

0x0380

dll_1xdly_5

dll_1xgen_5

dll_wrdqs_5

dll_wrdq_5

0x0388

dll_gate_5

dll_rddqs1_5

dll_rddqs0_5

0x0390

rdodt_ctrl_5

rdgate_len_5

rdgate_mode_5

rdgate_ctrl_5

dqs_oe_ctrl_5

dq_oe_ctrl_5

0x0398

dly_2x_5

redge_sel_5

rddqs_phase_5(RD)

0x03a0

w_bdly0_5[31:28]

w_bdly0_5[27:24]

w_bdly0_5[23:20]

w_bdly0_5[19:16]

w_bdly0_5[15:12]

w_bdly0_5[11:8]

w_bdly0_5[7:4]

w_bdly0_5[3:0]

0x03a8

w_bdly0_5[59:56]

w_bdly0_5[55:52]

w_bdly0_5[51:48]

w_bdly0_5[47:44]

w_bdly0_5[43:40]

w_bdly0_5[39:36]

w_bdly0_5[35:32]

0x03b0

w_bdly1_5[24:21]

w_bdly1_5[20:18]

w_bdly1_5[17:15]

w_bdly1_5[14:12]

w_bdly1_5[11:9]

w_bdly1_5[8:6]

w_bdly1_5[5:3]

w_bdly1_5[2:0]

0x03b8

w_bdly1_5[27:26]

0x03c0

rg_bdly_5[7:4]

rg_bdly_5[3:0]

0x03c8

0x03d0

rdqsp_bdly_5[31:28]

rdqsp_bdly_5[27:24]

rdqsp_bdly_5[23:20]

rdqsp_bdly_5[19:16]

rdqsp_bdly_5[15:12]

rdqsp_bdly_5[11:8]

rdqsp_bdly_5[7:4]

rdqsp_bdly_5[3:0]

0x03d8

rdqsp_bdly_5[35:32]

0x03e0

rdqsn_bdly_5[31:28]

rdqsn_bdly_5[27:24]

rdqsn_bdly_5[23:20]

rdqsn_bdly_5[19:16]

rdqsn_bdly_5[15:12]

rdqsn_bdly_5[11:8]

rdqsn_bdly_5[7:4]

rdqsn_bdly_5[3:0]

0x03e8

rdqsn_bdly_5[35:32]

0x03f0

rdq_bdly_5[24:21]

rdq_bdly_5[20:18]

rdq_bdly_5[17:15]

rdq_bdly_5[14:12]

rdq_bdly_5[11:9]

rdq_bdly_5[8:6]

rdq_bdly_5[5:3]

rdq_bdly_5[2:0]

0x03f8

rdq_bdly_5[27:26]

0x0400

dll_1xdly_6

dll_1xgen_6

dll_wrdqs_6

dll_wrdq_6

0x0408

dll_gate_6

dll_rddqs1_6

dll_rddqs0_6

0x0410

rdodt_ctrl_6

rdgate_len_6

rdgate_mode_6

rdgate_ctrl_6

dqs_oe_ctrl_6

dq_oe_ctrl_6

0x0418

dly_2x_6

redge_sel_6

rddqs_phase_6(RD)

0x0420

w_bdly0_6[31:28]

w_bdly0_6[27:24]

w_bdly0_6[23:20]

w_bdly0_6[19:16]

w_bdly0_6[15:12]

w_bdly0_6[11:8]

w_bdly0_6[7:4]

w_bdly0_6[3:0]

0x0428

w_bdly0_6[59:56]

w_bdly0_6[55:52]

w_bdly0_6[51:48]

w_bdly0_6[47:44]

w_bdly0_6[43:40]

w_bdly0_6[39:36]

w_bdly0_6[35:32]

0x0430

w_bdly1_6[24:21]

w_bdly1_6[20:18]

w_bdly1_6[17:15]

w_bdly1_6[14:12]

w_bdly1_6[11:9]

w_bdly1_6[8:6]

w_bdly1_6[5:3]

w_bdly1_6[2:0]

0x0438

w_bdly1_6[27:26]

0x0440

rg_bdly_6[7:4]

rg_bdly_6[3:0]

0x0448

0x0450

rdqsp_bdly_6[31:28]

rdqsp_bdly_6[27:24]

rdqsp_bdly_6[23:20]

rdqsp_bdly_6[19:16]

rdqsp_bdly_6[15:12]

rdqsp_bdly_6[11:8]

rdqsp_bdly_6[7:4]

rdqsp_bdly_6[3:0]

0x0458

rdqsp_bdly_6[35:32]

0x0460

rdqsn_bdly_6[31:28]

rdqsn_bdly_6[27:24]

rdqsn_bdly_6[23:20]

rdqsn_bdly_6[19:16]

rdqsn_bdly_6[15:12]

rdqsn_bdly_6[11:8]

rdqsn_bdly_6[7:4]

rdqsn_bdly_6[3:0]

0x0468

rdqsn_bdly_6[35:32]

0x0470

rdq_bdly_6[24:21]

rdq_bdly_6[20:18]

rdq_bdly_6[17:15]

rdq_bdly_6[14:12]

rdq_bdly_6[11:9]

rdq_bdly_6[8:6]

rdq_bdly_6[5:3]

rdq_bdly_6[2:0]

0x0478

rdq_bdly_6[27:26]

0x0480

dll_1xdly_7

dll_1xgen_7

dll_wrdqs_7

dll_wrdq_7

0x0488

dll_gate_7

dll_rddqs1_7

dll_rddqs0_7

0x0490

rdodt_ctrl_7

rdgate_len_7

rdgate_mode_7

rdgate_ctrl_7

dqs_oe_ctrl_7

dq_oe_ctrl_7

0x0498

dly_2x_7

redge_sel_7

rddqs_phase_7(RD)

0x04a0

w_bdly0_7[31:28]

w_bdly0_7[27:24]

w_bdly0_7[23:20]

w_bdly0_7[19:16]

w_bdly0_7[15:12]

w_bdly0_7[11:8]

w_bdly0_7[7:4]

w_bdly0_7[3:0]

0x04a8

w_bdly0_7[59:56]

w_bdly0_7[55:52]

w_bdly0_7[51:48]

w_bdly0_7[47:44]

w_bdly0_7[43:40]

w_bdly0_7[39:36]

w_bdly0_7[35:32]

0x04b0

w_bdly1_7[24:21]

w_bdly1_7[20:18]

w_bdly1_7[17:15]

w_bdly1_7[14:12]

w_bdly1_7[11:9]

w_bdly1_7[8:6]

w_bdly1_7[5:3]

w_bdly1_7[2:0]

0x04b8

w_bdly1_7[27:26]

0x04c0

rg_bdly_7[7:4]

rg_bdly_7[3:0]

0x04c8

0x04d0

rdqsp_bdly_7[31:28]

rdqsp_bdly_7[27:24]

rdqsp_bdly_7[23:20]

rdqsp_bdly_7[19:16]

rdqsp_bdly_7[15:12]

rdqsp_bdly_7[11:8]

rdqsp_bdly_7[7:4]

rdqsp_bdly_7[3:0]

0x04d8

rdqsp_bdly_7[35:32]

0x04e0

rdqsn_bdly_7[31:28]

rdqsn_bdly_7[27:24]

rdqsn_bdly_7[23:20]

rdqsn_bdly_7[19:16]

rdqsn_bdly_7[15:12]

rdqsn_bdly_7[11:8]

rdqsn_bdly_7[7:4]

rdqsn_bdly_7[3:0]

0x04e8

rdqsn_bdly_7[35:32]

0x04f0

rdq_bdly_7[24:21]

rdq_bdly_7[20:18]

rdq_bdly_7[17:15]

rdq_bdly_7[14:12]

rdq_bdly_7[11:9]

rdq_bdly_7[8:6]

rdq_bdly_7[5:3]

rdq_bdly_7[2:0]

0x04f8

rdq_bdly_7[27:26]

0x0500

dll_1xdly_8

dll_1xgen_8

dll_wrdqs_8

dll_wrdq_8

0x0508

dll_gate_8

dll_rddqs1_8

dll_rddqs0_8

0x0510

rdodt_ctrl_8

rdgate_len_8

rdgate_mode_8

rdgate_ctrl_8

dqs_oe_ctrl_8

dq_oe_ctrl_8

0x0518

dly_2x_8

redge_sel_8

rddqs_phase_8(RD)

0x0520

w_bdly0_8[31:28]

w_bdly0_8[27:24]

w_bdly0_8[23:20]

w_bdly0_8[19:16]

w_bdly0_8[15:12]

w_bdly0_8[11:8]

w_bdly0_8[7:4]

w_bdly0_8[3:0]

0x0528

w_bdly0_8[59:56]

w_bdly0_8[55:52]

w_bdly0_8[51:48]

w_bdly0_8[47:44]

w_bdly0_8[43:40]

w_bdly0_8[39:36]

w_bdly0_8[35:32]

0x0530

w_bdly1_8[24:21]

w_bdly1_8[20:18]

w_bdly1_8[17:15]

w_bdly1_8[14:12]

w_bdly1_8[11:9]

w_bdly1_8[8:6]

w_bdly1_8[5:3]

w_bdly1_8[2:0]

0x0538

w_bdly1_8[27:26]

0x0540

rg_bdly_8[7:4]

rg_bdly_8[3:0]

0x0548

0x0550

rdqsp_bdly_8[31:28]

rdqsp_bdly_8[27:24]

rdqsp_bdly_8[23:20]

rdqsp_bdly_8[19:16]

rdqsp_bdly_8[15:12]

rdqsp_bdly_8[11:8]

rdqsp_bdly_8[7:4]

rdqsp_bdly_8[3:0]

0x0558

rdqsp_bdly_8[35:32]

0x0560

rdqsn_bdly_8[31:28]

rdqsn_bdly_8[27:24]

rdqsn_bdly_8[23:20]

rdqsn_bdly_8[19:16]

rdqsn_bdly_8[15:12]

rdqsn_bdly_8[11:8]

rdqsn_bdly_8[7:4]

rdqsn_bdly_8[3:0]

0x0568

rdqsn_bdly_8[35:32]

0x0570

rdq_bdly_8[24:21]

rdq_bdly_8[20:18]

rdq_bdly_8[17:15]

rdq_bdly_8[14:12]

rdq_bdly_8[11:9]

rdq_bdly_8[8:6]

rdq_bdly_8[5:3]

rdq_bdly_8[2:0]

0x0578

rdq_bdly_8[27:26]

…​…​

0x0700

leveling_cs

tLVL_DELAY

leveling_req(WR)

leveling_mode

0x0708

leveling_done(RD)

leveling_ready(RD)

0x0710

leveling_resp_7

leveling_resp_6

leveling_resp_5

leveling_resp_4

leveling_resp_3

leveling_resp_2

leveling_resp_1

leveling_resp_0

0x0718

leveling_resp_8

0x0720

…​…​

0x0800

dfe_ctrl_ds

pad_ctrl_ds

pad_ctrl_ck

0x0808

pad_reset_po

pad_oplen_ca

pad_opdly_ca

pad_ctrl_ca

0x0810

vref_ctrl_ds_3

vref_ctrl_ds_2

vref_ctrl_ds_1

vref_ctrl_ds_0

0x0818

vref_ctrl_ds_7

vref_ctrl_ds_6

vref_ctrl_ds_5

vref_ctrl_ds_4

0x0820

vref_ctrl_ds_8

0x0828

0x0830

pad_comp_o(RD)

pad_comp_i

0x0838

CTL

0x1000

tRP

tWLDQSEN

tMOD

tXPR

tCKE

tRESET

0x1008

tODTL

0x1010

tREFretention

tRFC

tREF

0x1018

tCKESR

tXSRD

tXS

tRFC_dlr

tREF_IDLE

0x1020

tRDPDEN

tCPDED

tXPDLL

tXP

0x1028

tZQperiod

tZQCL

tZQCS

tZQ_CMD

…​…​

0x1040

tRCD

tRRD_S_slr

tRRD_L_slr

tRRD_dlr

tRAS_min

0x1048

tRTP

tWR_CRC_DM

tWR

tFAW_slr

tFAW

0x1050

tWTR_S_CRC_DM

tWTR_L_CRC_DM

tWTR_S

tWTR

tCCD_dlr

tCCD_S_slr

tCCD_L_slr

0x1058

0x1060

tPHY_WRLAT

tWL

tRDDATA

tPHY_RDLAT

tRL

0x1068

tCAL

tPL

0x1070

tW2P_sameba

tW2W_sameba

tW2R_sameba

tR2P_sameba

tR2W_sameba

tR2R_sameba

0x1078

tW2P_samebg

tW2W_samebg

tW2R_samebg

tR2P_samebg

tR2W_samebg

tR2R_samebg

0x1080

tW2P_samec

tW2W_samec

tW2R_samec

tR2P_samec

tR2W_samec

tR2R_samec

0x1088

0x1090

tW2P_samecs

tW2W_samecs

tW2R_samecs

tR2P_samecs

tR2W_samecs

tR2R_samecs

0x1098

tW2W_diffcs

tW2R_diffcs

tR2W_diffcs

tR2R_diffcs

…​…​

0x1100

cs_ref

cs_resync

cs_zqcl

cs_zq

cs_mrs

cs_enable

0x1108

cke_map

cs_map

0x1110

cs2cid

cid_map

0x1118

0x1120

mrs_done(RD)

mrs_req(WR)

pre_all_done(RD)

pre_all_req(WR)

cmd_cmd

status_cmd(RD)

cmd_req(WR)

command_mode

0x1128

cmd_cke

cmd_a

cmd_ba

cmd_bg

cmd_c

cmd_cs

0x1130

cmd_pda

0x1138

cmd_dq0

0x1140

mr_3_cs_0

mr_2_cs_0

mr_1_cs_0

mr_0_cs_0

0x1148

mr_3_cs_1

mr_2_cs_1

mr_1_cs_1

mr_0_cs_1

0x1150

mr_3_cs_2

mr_2_cs_2

mr_1_cs_2

mr_0_cs_2

0x1158

mr_3_cs_3

mr_2_cs_3

mr_1_cs_3

mr_0_cs_3

0x1160

mr_3_cs_4

mr_2_cs_4

mr_1_cs_4

mr_0_cs_4

0x1168

mr_3_cs_5

mr_2_cs_5

mr_1_cs_5

mr_0_cs_5

0x1170

mr_3_cs_6

mr_2_cs_6

mr_1_cs_6

mr_0_cs_6

0x1178

mr_3_cs_7

mr_2_cs_7

mr_1_cs_7

mr_0_cs_7

0x1180

mr_3_cs_0_ddr4

mr_2_cs_0_ddr4

mr_1_cs_0_ddr4

mr_0_cs_0_ddr4

0x1188

mr_6_cs_0_ddr4

mr_5_cs_0_ddr4

mr_4_cs_0_ddr4

0x1190

mr_3_cs_1_ddr4

mr_2_cs_1_ddr4

mr_1_cs_1_ddr4

mr_0_cs_1_ddr4

0x1198

mr_6_cs_1_ddr4

mr_5_cs_1_ddr4

mr_4_cs_1_ddr4

0x11a0

mr_3_cs_2_ddr4

mr_2_cs_2_ddr4

mr_1_cs_2_ddr4

mr_0_cs_2_ddr4

0x11a8

mr_6_cs_2_ddr4

mr_5_cs_2_ddr4

mr_4_cs_2_ddr4

0x11b0

mr_3_cs_3_ddr4

mr_2_cs_3_ddr4

mr_1_cs_3_ddr4

mr_0_cs_3_ddr4

0x11b8

mr_6_cs_3_ddr4

mr_5_cs_3_ddr4

mr_4_cs_3_ddr4

0x11c0

mr_3_cs_4_ddr4

mr_2_cs_4_ddr4

mr_1_cs_4_ddr4

mr_0_cs_4_ddr4

0x11c8

mr_6_cs_4_ddr4

mr_5_cs_4_ddr4

mr_4_cs_4_ddr4

0x11d0

mr_3_cs_5_ddr4

mr_2_cs_5_ddr4

mr_1_cs_5_ddr4

mr_0_cs_5_ddr4

0x11d8

mr_6_cs_5_ddr4

mr_5_cs_5_ddr4

mr_4_cs_5_ddr4

0x11e0

mr_3_cs_6_ddr4

mr_2_cs_6_ddr4

mr_1_cs_6_ddr4

mr_0_cs_6_ddr4

0x11e8

mr_6_cs_6_ddr4

mr_5_cs_6_ddr4

mr_4_cs_6_ddr4

0x11f0

mr_3_cs_7_ddr4

mr_2_cs_7_ddr4

mr_1_cs_7_ddr4

mr_0_cs_7_ddr4

0x11f8

mr_6_cs_7_ddr4

mr_5_cs_7_ddr4

mr_4_cs_7_ddr4

0x1200

nc16_map

nc

channel_width

ba_xor_row_offset

addr_new

cs_place

0x1208

bg_xor_row_offset

addr_mirror

0x1210

addr_base_1

addr_base_0

0x1218

0x1220

addr_mask_1

addr_mask_0

0x1228

0x1230

cs_diff

c_diff

bg_diff

ba_diff

row_diff

col_diff

0x1238

CF_confbus_timeout

0x1240

WRQthreshold

tRDQidle

wr_pkc_num

rwq_rb

retry

no_dead_inorder

placement_en

stb_en/pbuf

0x1248

tRWGNTidle

0x1250

rfifo_age

0x1258

prior_age3

prior_age2

prior_age1

prior_age0

0x1260

retry_cnt(RD)

rbuffer_max(RD)

rdfifo_depth

stat_en

0x1268

…​…​

0x1280

aw_512_align

rd_before_wr

ecc_enable

int_vector(RD)

int_trigger(RD)

int_enable

0x1288

0x1290

int_cnt_fatal(RD)

int_cnt_err(RD)

int_cnt

0x1298

ecc_cnt_cs_7(RD)

ecc_cnt_cs_6(RD)

ecc_cnt_cs_5(RD)

ecc_cnt_cs_4(RD)

ecc_cnt_cs_3(RD)

ecc_cnt_cs_2(RD)

ecc_cnt_cs_1(RD)

ecc_cnt_cs_0(RD)

0x12a0

ecc_data_dir(RD)

ecc_code_dir(RD)

ecc_code_256(RD)

ecc_code_64(RD)

0x12a8

ecc_addr(RD)

0x12b0

ecc_data[63:0](RD)

0x12b8

ecc_data[127:64] (RD)

0x12c0

ecc_data[191:128] (RD)

0x12c8

ecc_data[255:192] (RD)

…​…​

0x1300

ref_num

ref_sch_en

0x1308

Status_sref(RD)

srefresh_req

…​…​

0x1340

hardware_pd_7

hardware_pd_6

hardware_pd_5

hardware_pd_4

hardware_pd_3

hardware_pd_2

hardware_pd_1

hardware_pd_0

0x1348

power_sta_7(RD)

power_sta_6(RD)

power_sta_5(RD)

power_sta_4(RD)

power_sta_3(RD)

power_sta_2(RD)

power_sta_1(RD)

power_sta_0(RD)

0x1350

selfref_age

slowpd_age

fastpd_age

active_age

0x1358

power_up

Age_step

0x1360

tCONF_IDLE

tLPMC_IDLE

…​…​

0x1380

zq_overlap

0x1388

zq_stat_en

0x1390

zq_cnt_1(RD)

zq_cnt_0(RD)

0x1398

zq_cnt_3(RD)

zq_cnt_2(RD)

0x13a0

zq_cnt_5(RD)

zq_cnt_4(RD)

0x13a8

zq_cnt_6(RD)

zq_cnt_6(RD)

…​…​

0x13c0

odt_wr_cs_map

0x13c8

odt_wr_length

odt_wr_delay

0x13d0

odt_rd_cs_map

0x13d8

odt_rd_length

odt_rd_delay

…​…​

0x1400

tRESYNC_length

tRESYNC_delay

tRESYNC_shift

tRESYNC_max

tRESYNC_min

…​…​

0x1440

pre_predict

tm_cmdq_num

burst_length

0x1448

ca_timing

0x1450

wr/rd_dbi_en

ca_par_en

crc_en

0x1458

tCA_PAR

tWR_CRC

0x1460

bit_map_7

bit_map_6

bit_map_5

bit_map_6

bit_map_3

bit_map_2

bit_map_1

bit_map_0

0x1468

bit_map_15

bit_map_14

bit_map_13

bit_map_12

bit_map_11

bit_map_10

bit_map_9

bit_map_8

0x1470

bit_map_17

bit_map_16

0x1478

bitmap_mirror

0x1480

alertn_misc(RD)

alertn_cnt

alertn_clr

0x1488

alertn_addr(RD)

…​…​

0x1500

win0_base

0x1508

win1_base

0x1510

win2_base

0x1518

win3_base

0x1520

win4_base

0x1528

win5_base

0x1530

win6_base

0x1538

win7_base

…​…​

0x1580

win0_mask

0x1588

win1_mask

0x1590

win2_mask

0x1598

win3_mask

0x15a0

win4_mask

0x15a8

win5_mask

0x15b0

win6_mask

0x15b8

win7_mask

…​…​

0x1600

win0_mmap

0x1608

win1_mmap

0x1610

win2_mmap

0x1618

win3_mmap

0x1620

win4_mmap

0x1628

win5_mmap

0x1630

win6_mmap

0x1638

win7_mmap

…​…​

0x1700

acc_hp

acc_en

0x1708

acc_fake_b

acc_fake_a

0x1710

0x1718

0x1720

addr_base_acc_1

addr_base_acc_0

0x1728

0x1730

addr_mask_acc_1

addr_mask_acc_0

0x1738

MON

0x2000

cmd_monitor

0x2008

0x2010

cmd_fbck[63:0](RD)

0x2018

cmd_fbck[127:64] (RD)

0x2020

rw_switch_cnt(RD)

…​…​

0x2100

scheduler_mon

0x2108

0x2110

sch_cmd_num(RD)

0x2118

ba_conflict_all(RD)

0x2120

ba_conflict_last1(RD)

0x2128

ba_conflict_last2(RD)

0x2130

ba_conflict_last3(RD)

0x2138

ba_conflict_last4(RD)

0x2140

ba_conflict_last5(RD)

0x2148

ba_conflict_last6(RD)

0x2150

ba_conflict_last7(RD)

0x2158

ba_conflict_last8(RD)

0x2160

rd_conflict(RD)

0x2168

wr_conflict(RD)

0x2170

rtw_conflict(RD)

0x2178

wtr_conflict(RD)

0x2180

rd_conflict_last1(RD)

0x2188

wr_conflict_last1(RD)

0x2190

rtw_conflict_last1(RD)

0x2198

wtr_conflict_last1(RD)

0x21a0

wr_rd_turnaround(RD)

0x21a8

cs_turnaround(RD)

0x21b0

bg_conflict(RD)

…​…​

0x2300

sm_leveling

sm_init

0x2308

0x2310

sm_rank_03

sm_rank_02

sm_rank_01

sm_rank_00

0x2318

sm_rank_07

sm_rank_06

sm_rank_05

sm_rank_04

0x2320

sm_rank_11

sm_rank_10

sm_rank_09

sm_rank_08

0x2328

sm_rank_15

sm_rank_14

sm_rank_13

sm_rank_12

0x2330

sm_rank_19

sm_rank_18

sm_rank_17

sm_rank_16

0x2338

sm_rank_23

sm_rank_22

sm_rank_21

sm_rank_20

0x2340

sm_rank_27

sm_rank_26

sm_rank_25

sm_rank_24

0x2348

sm_rank_31

sm_rank_30

sm_rank_29

sm_rank_28

…​…​

TST

0x3000

lpbk_mode

lpbk_start

lpbk_en

0x3008

lpbk_correct(RD)

lpbk_counter(RD)

lpbk_error(RD)

0x3010

lpbk_data_en[63:0]

0x3018

lpbk_data_en[71:64]

0x3020

lpbk_data_mask_en

0x3028

0x3030

Lpbk_dat_w0[63:0]

0x3038

Lpbk_dat_w0[127:64]

0x3040

Lpbk_dat_w1[63:0]

0x3048

Lpbk_dat_w1[127:64]

0x3050

lpbk_ecc_mask_w0

lpbk_dat_mask_w0

lpbk_ecc_w0

0x3058

lpbk_ecc_mask_w1

lpbk_dat_mask_w1

lpbk_ecc_w1

0x3060

prbs_23

0x3068

prbs_init

…​…​

0x3100

fix_data_pattern_index

bus_width

page_size

test_engine_en

0x3108

cs_diff_tst

c_diff_tst

bg_diff_tst

ba_diff_tst

row_diff_tst

col_diff_tst

0x3120

addr_base_tst

0x3128

0x3130

user_data_pattern

0x3138

0x3140

valid_bits[63:0]

0x3148

valid_bits[71:64]

0x3150

ctrl[63:0]

0x3158

ctrl[127:64]

0x3160

obs[63:0] (RD)

0x3168

obs[127:64] (RD)

0x3170

obs[191:128] (RD)

0x3178

obs[255:192] (RD)

0x3180

obs[319:256] (RD)

0x3188

obs[383:320] (RD)

0x3190

obs[447:384] (RD)

0x3198

obs[511:448] (RD)

0x31a0

obs[575:512] (RD)

0x31a8

obs[639:576] (RD)

0x31b0

obs[671:640](RD)

…​…​

0x3200

0x3208

0x3220

tud_i0

0x3228

tud_i1

0x3230

tud_o(RD)

…​…​

0x3300

tst_300

0x3308

tst_308

0x3310

tst_310

0x3318

tst_318

0x3320

tst_320

0x3328

tst_328

0x3330

tst_330

0x3338

tst_338

0x3340

tst_340

0x3348

tst_348

0x3350

tst_350

0x3358

tst_358

0x3360

tst_360

0x3368

tst_368

0x3370

tst_370

0x3378

tst_378

+
+
+
+

13.3. Software Programming Guide

+
+

13.3.1. Initialization Operations

+
+

The initialization operation starts when the software writes 0x2 to register Init_start (0x010). +Before setting the Init_start signal, all other registers must be set to the correct values. +The DRAM initialization process in cooperation with hardware and software is as follows:

+
+
+
    +
  1. +

    Set pm_clk_sel_ckca and pm_clk_sel_ds.

    +
    2. +
  2. +

    Set pm_phy_init_start to 1 to start initializing the PHY.

    +
    3. +
+
+
+
Wait for pm_dll_lock_* or pm_pll_lock_* of all clock generation modules to become 1.
+
    +
  1. +

    Enabling all pm_clken_*.

    +
    2. +
  2. +

    Set pm_init_start to 1 to start initialization of the memory controller.

    +
    3. +
+
+
+
+

13.3.2. Control of Reset Pins

+
+
Wait for the memory controller initialization to complete, i.e., the value of pm_dram_init is the same as pm_cs_enable.
+

For simpler control of reset pins in states such as STR, special reset pin (DDR_RESETn) control can be performed via the pad_reset_po (0x808) register, and there are two main control modes:

+
+
+
    +
  1. +

    General mode, reset_ctrl[1:0] == 2’b00. +The behavior of the reset signal pins in this mode is compatible with the general control mode. +DDR_RESETn is connected directly on the motherboard to the corresponding pin on the memory slot. +The behavior of the pin is:

    +
    +
      +
    • +

      When not powered up: pin status is low.

      +
      • +
    • +

      At power-up: pin state is low.

      +
      • +
    • +

      When the controller starts initialization: pin state is high.

      +
      • +
    • +

      During normal operation: pin state is high.

      +
      +

      The timing is shown in the figure below:

      +
      +
      +
      +general mode timing +
      +
      Figure 7. General mode timing
      +
      +
      • +
    +
    +
    2. +
  2. +

    Reverse mode, reset_ctrl[1:0] == 2’b10. +In this mode, the reset signal pins are at the opposite effective level from the normal control mode when doing the actual memory control. +So the motherboard needs to connect DDR_RESETn to the corresponding pin on the memory slot through the inverter. +The pin behavior is:

    +
    +
      +
    • +

      When not powered up: the pin state is low.

      +
      • +
    • +

      At power-up: pin state is low.

      +
      • +
    • +

      When the controller starts configuration: pin state is high.

      +
      • +
    • +

      When the controller starts initialization: pin state is low.

      +
      • +
    • +

      During normal operation: pin state is low.

      +
      +

      The timing sequence is shown in the following figure:

      +
      +
      +
      +reverse mode timing +
      +
      Figure 8. Reverse mode timing
      +
      +
      • +
    +
    +
    3. +
  3. +

    Reset disable mode, pm_pad_reset_o[1:0] == 2’b01. +In this mode, the reset signal pin remains low during the whole memory operation. +So the motherboard needs to connect DDR_RESETn to the corresponding pin on the memory slot through the inverter. +The behavior of the pins is:

    +
    +
      +
    • +

      always low.

      +
      +

      The timing is shown in the following diagram:

      +
      +
      +
      Reset disable mode timing
      +

      reset disable mode timing

      +
      +
      • +
    +
    +
    4. +
+
+
+

By the latter two reset modes in conjunction, STR control can be achieved directly with the use of the memory controller’s reset signal. +When the whole system is booted from the shutdown state, use the method 2 to use the memory stick to reset normally and start working. +When the system resumes from STR, the method 3 is used to reconfigure the memory stick so that it starts working properly again without destroying the original state of the memory stick.

+
+
+
+

13.3.3. Leveling

+
+

The Leveling operation is an operation used in DDR3/4 to intelligently configure the phase relationship between various signals in the memory controller read and write operations. +It usually includes Write Leveling, Read Leveling and GateLeveling. +In this controller, only Write Leveling and Gate Leveling are implemented, and Read Leveling is not implemented. +The software needs to judge the correctness of reading and writing to achieve the functions accomplished by Read Leveling. +In addition to the DQS phase and GATE phase operated in the Leveling process, the configuration methods of Write DQ phase and Read DQ phase can be calculated based on these last confirmed phases. +In addition, the design supports a bit-deskew function to compensate the delay difference between different bits within a dataslice.

+
+
+
13.3.3.1. Write Leveling
+
+

Write Leveling is used to configure the phase relationship between the write DQS and the clock, and the software programming needs to refer to the following steps.

+
+
+
    +
  1. +

    Complete the controller initialization, see the previous subsection.

    +
    2. +
  2. +

    Set Dll_wrdqs_x (x = 0…​8) to 0x20.

    +
    3. +
  3. +

    Set Dll_wrdq_x (x = 0..8) to 0x0.

    +
    4. +
  4. +

    Set Lvl_mode to 2’b01.

    +
    5. +
  5. +

    Sample the Lvl_ready register, if it is 1, it means that the Write Leveling request can start.

    +
    6. +
  6. +

    Set Lvl_req to 1.

    +
    7. +
  7. +

    Sample the Lvl_done register, if it is 1, a Write Leveling request is complete.

    +
    8. +
  8. +

    Sample the Lvl_resp_x register, if it is 0, increments the corresponding Dll_wrdq_x[6:0] and dll_1xdly[6:0] by 1, and repeats 5-7 until Lvl_resp_x is 1, then moves to 9; if it is 1, increments the corresponding Dll_wrdq_x[6:0] and dll_1xdly[6:0] by 1 and repeat 5-7 until Lvl_resp_x is 0, then continue to increase the corresponding Dll_wrdq_x[6:0] and dll_1xdly[6:0] by 1 and repeat 5-7 until Lvl_resp_x is 1, then turn to 9.

    +
    9. +
  9. +

    Subtract 0x40 from the values of Dll_wrdq_x and dll_1xdly, at which point the values of Dll_wrdq_x and dll_1xdly should be the correct values to set.

    +
    10. +
  10. +

    Set pm_dly_2x according to the DIMM type, for the particles to the right of the 0x0 bound the corresponding pm_dly_2x value is increased by 0x010101.

    +
    11. +
  11. +

    Set Lvl_mode (0x700) to 2’b00 to exit Write Leveling mode.

    +
    12. +
+
+
+
+
13.3.3.2. Gate Leveling
+
+

Gate Leveling is used to configure the timing of the enable sample read DQS window within the controller, refer to the following steps for software programming.

+
+
+
    +
  1. +

    Complete controller initialization, see previous subsection.

    +
    2. +
  2. +

    Completing Write Leveling, see previous section.

    +
    3. +
  3. +

    Set Dll_gate_x (x = 0…​8) to 0.

    +
    4. +
  4. +

    Set Lvl_mode to 2’b10.

    +
    5. +
  5. +

    Sample the Lvl_ready register; if it is 1, the Gate Leveling request can start.

    +
    6. +
  6. +

    Set Lvl_req to 1.

    +
    7. +
  7. +

    Sample the Lvl_done register, if it is 1, a Gate Leveling request is complete.

    +
    8. +
  8. +

    Sample the Lvl_resp_x[0] register, if the first sample finds Lvl_resp_x[0] to be 1, increase the corresponding Dll_gate_x[6:0] by 1 and repeat 6-8 until the sample result is 0; otherwise proceed to the next step.

    +
    9. +
  9. +

    If the sampling result is 0, increment the corresponding Dll_gate_x[6:0] by 1 and repeat 6-9; if it is 1, the Gate Leveling operation has succeeded.

    +
    10. +
  10. +

    Set pm_rdedge_sel (11) according to the value of pm_rddqs_phase to set Dll_gate_x (x = +0…​8) minus 0x20.

    +
    11. +
  11. +

    If the value of Lvl_resp_x[7:5] and Lvl_resp_x[4:2] changes, if each increases to Burst_length/2, proceed to step 13; if it is not 4, it may be necessary to add or subtract Rd_oe_begin_x a plus or minus operation may be required for Rd_oe_begin_x, and if greater than Burst_length/2, some fine-tuning of the value of Dll_gate_x is likely to be required.

    +
    12. +
  12. +

    Set Lvl_mode (0x700) to 2’b00 to exit Gate Leveling mode.

    +
    13. +
  13. +

    This ends the Gate Leveling operation.

    +
    14. +
+
+
+
+
+

13.3.4. Power Control Configuration Flow

+
+

First set pm_pad_ctrl_ca[0] to 1, then set pm_pad_ctrl_ca[0] to 0 after memory initialization is complete. +This function is only available when CAL Mode is enabled in DDR4 mode.

+
+
+
+

13.3.5. Initiate a Separate MRS Command

+
+

In DDR3 mode, the sequence of MRS commands issued by the memory controller to the memory are:

+
+
+

MR2_CS0, MR2_CS1, MR2_CS2, MR2_CS3, MR2_CS4, MR2_CS5, MR2_CS6, MR2_CS7, MR3_CS0, MR3_CS1, MR3_CS2, MR3_CS3, MR3_CS4, MR3_CS5, MR3_CS6, MR3_CS7, MR1_CS0, MR1_CS1, MR1_CS2, MR1_CS3, MR1_CS4, MR1_CS5, MR1_CS6, MR1_CS7, MR0_CS0, MR1_CS1, MR1_CS2, MR1_CS3, MR0_CS4, MR0_CS5, MR0_CS6, MR0_CS7.

+
+
+

In addition, for DDR4 mode, the sequence of MRS commands issued by the memory controller to the memory are:

+
+
+

MR3_CS0, MR3_CS1, MR3_CS2, MR3_CS3, MR3_CS4, MR3_CS5, MR3_CS6, MR3_CS7, MR6_CS0, MR6_CS1, MR6_CS2, MR6_CS3, MR6_CS4, MR6_CS5, MR6_CS6, MR6_CS7, MR5_CS0, MR5_CS1, MR5_CS2, MR5_CS3, MR5_CS4, MR5_CS5, MR5_CS6, MR5_CS7, MR4_CS0, MR1_CS1, MR1_CS2, MR1_CS3, MR4_CS4, MR4_CS5, MR4_CS6, MR4_CS7, MR2_CS0, MR2_CS1, MR2_CS2, MR2_CS3, MR2_CS4, MR2_CS5, MR2_CS6, MR2_CS7, MR1_CS0, MR1_CS1, MR1_CS2, MR1_CS3, MR1_CS4, MR1_CS5, MR1_CS6, MR1_CS7, MR0_CS0, MR1_CS1, MR1_CS2, MR1_CS3, MR0_CS4, MR0_CS5, MR0_CS6, MR0_CS7.

+
+
+

Among them, whether the MRS command corresponding to CS is valid or not is determined by Cs_mrs. +Only when the bit corresponding to each chip select on Cs_mrs is valid, this MRS command is actually sent to DRAM. +The value of each corresponding MR is determined by the register Mr*_cs*. +These values are also used for the MRS command when initializing the memory.

+
+
+

The operation is as follows:

+
+
+
    +
  1. +

    Set the registers Cs_mrs (0x1101), Mr*_cs* (0x1140-0x11f8) to the correct values.

    +
    2. +
  2. +

    Set Command_mode (0x1120) to 1 to put the controller into command sending mode.

    +
    3. +
  3. +

    Sample Status_cmd (0x1122), if it is 1, the controller is in command sending mode and can proceed to the next operation, if it is 0, it needs to continue to wait.

    +
    4. +
+
+
+
Write Mrs_req (0x1126) to 1 to send MRS command to DRAM.
+
    +
  1. +

    sample Mrs_done (0x1127), if it is 1, it means the MRS command has been sent and can exit, if it is 0, it needs to continue to wait.

    +
    2. +
  2. +

    Set Command_mode (0x1120) to 0 to make the controller exit the command sending mode.

    +
    3. +
+
+
+
+

13.3.6. Arbitrary Operation Control Bus

+
+

The memory controller can send any combination of commands to DRAM via command send mode. +The software can set Cmd_cs, Cmd_cmd, Cmd_ba, Cmd_a (0x1128) to be sent to DRAM in command send mode.

+
+
+

The specific operation is as follows:

+
+
+
    +
  1. +

    Set registers Cmd_cs, Cmd_cmd, Cmd_ba, Cmd_a (0x1128) to the correct values.

    +
    2. +
  2. +

    Set Command_mode (0x1120) to 1 to put the controller into command sending mode;

    +
    3. +
  3. +

    Sample Status_cmd (0x1122), if it is 1, the controller is in command sending mode and can proceed to the next operation, if it is 0, it needs to continue to wait;

    +
    4. +
+
+
+
Write Cmd_req (0x1121) to 1 to send a command to DRAM.
+
    +
  1. +

    Set Command_mode (0x1120) to 0 to make the controller exit the command sending mode.

    +
    2. +
+
+
+
+

13.3.7. Control of Self-cycling Test Mode

+
+

The self-cycling test mode can be used in test mode or normal function mode, respectively. +For this purpose, this memory controller implements two separate sets of control interfaces, one for direct control by the test port in test mode and the other for configuration enable test by the register configuration module in normal function mode.

+
+
+

The multiplexing of these two sets of interfaces is controlled using port test_phy. +When test_phy is valid, the test_* port of the controller is used for control, and the self-test is fully controlled by hardware at this time; when test_phy is invalid, the parameters of pm_* programmed by software are used for control. +The specific signal meaning of using the test port can be found in the same name section of the register parameters.

+
+
+

These two sets of interfaces are basically the same in terms of control parameters, only the access point is different, here to introduce the control method of software programming. +The specific operation is as follows:

+
+
+
    +
  1. +

    Set all the parameters of the memory controller correctly.

    +
    2. +
+
+
+
Wait for the clock reset to stabilize according to the initialization process.
+
    +
  1. +

    Set register Lpbk_en to 1.

    +
    2. +
  2. +

    Set the register Lpbk_start to 1; then the self-loop test starts.

    +
    3. +
  3. +

    At this point the self-loop test has begun and the software needs to be checked frequently for errors, as follows:

    +
    4. +
  4. +

    Sample register Lpbk_error, if it is 1, it means that an error occurred, at this time the first error data and correct data through Lpbk_* and other observation registers can be observed; if this value is 0, it means that there has not been a data error.

    +
    5. +
+
+
+
+

13.3.8. Control of the Use of ECC Function

+
+

The ECC function is only available in 64-bit mode. +ecc_enable (0x1280) consists of the following 2 control bits:

+
+
+

Ecc_enable[0] controls whether to enable the ECC function, which is enabled only if this valid bit is set. +Ecc_enable[1] controls whether to report errors through the processor’s internal read response path, so that a read access with an ECC two-bit error can immediately cause an exception to occur in the processor core.

+
+
+

In addition, ECC errors can be notified to the processor core via an interrupt. +This interrupt is controlled through Int_enable. +The interrupt consists of two vectors, Int_vector[0] for an ECC error (both 1-bit and 2-bit errors) and Int_vecotr[1] for an ECC two-bit error. +Clearance of Int_vector is achieved by writing 1 to the corresponding bit.

+
+
+
+

13.3.9. Observation of Error States

+
+

After a memory controller error, the corresponding system configuration registers can be accessed to get the corresponding error information and perform simple debugging operations. +The register base address is 0x1fe00000 or 0x3ff00000, which can also be accessed using the configuration register instruction, and the registers and their corresponding bits are as follows.

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 90. Memory controller 0 error status observation register
RegisterOffset AddressRead/WriteDescription

Memory controller 0 ECC set register Mc0_ecc_set

0x0600

RW

Memory controller 0 ECC set register

+

[5:0]: MC0 int_enable, interrupt enable

+

[8]: MC0 int_trigger, interrupt trigger configuration

+

[21:16]: MC0 int_vector (RO), interrupt vector (read only)

+

[33:32]: MC0 ecc_enable, ECC-related function enable

+

[40]: MC0 rd_before_wr, write after read function enable

0x0608

RW

Reserved

Memory controller 0 ECC counter register Mc0_ecc_cnt

0x0610

RW

Memory controller 0 ECC counter register

+

[7:0]: MC0 int_cnt, configure the ECC checking trigger interrupt count threshold

+

[15:8]: MC0 int_cnt_err (RO), ECC check one bit error count (read only)

+

[23:16]: MC0 int_cnt_fatal (RO), ECC checking error count (read only)

Memory controller 0 ECC error count register Mc0_ecc_cs_cnt

0x0618

RO

Memory controller 0 ECC error count register

+

[7:0]: MC0 ecc_cnt_cs_0, statistics on the number of CS0 ECC checking errors

+

[15:8]: MC0 ecc_cnt_cs_1, statistics on the number of CS1 ECC checking errors

+

[23:16]: MC0 ecc_cnt_cs_2, statistics on the number of CS2 ECC checking errors

+

[31:24]: MC0 ecc_cnt_cs_3, statistics on the number of CS3 ECC checking errors

+

[39:32]: MC0 ecc_cnt_cs_4, statistics on the number of CS4 ECC checking errors

+

[47:40]: MC0 ecc_cnt_cs_5, statistics on the number of CS5 ECC checking errors

+

[55:48]: MC0 ecc_cnt_cs_6, statistics on the number of CS6 ECC checking errors

+

[63:56]: MC0 ecc_cnt_cs_7, statistics on the number of CS7 ECC checking errors

Memory controller 0 ECC checking register Mc0_ecc_code

0x0620

RO

Memory controller 0 ECC checking register

+

[7:0]: MC0 ecc_code_64, 64-bit ECC checking, invalid when memory directory function is enabled

+

[41:32]: MC0 ecc_code_256, 256-bit ECC checking, valid when memory directory function is enabled

+

[52:48]: MC0 ecc_code_dir, memory directory ECC checking, valid only when the memory directory function is enabled

+

[60:56]: MC0 ecc_data_dir, memory directory ECC data, valid only when the memory directory function is enabled

Memory controller 0 ECC error address register Mc0_ecc_addr

0x0628

RO

Memory controller 0 ECC error address register

+

[63:0]: MC0 ecc_addr, ECC checking error address information

Memory controller 0 ECC error data register 0 Mc0_ecc_data0

0x0630

RO

Memory controller 0 ECC error data register 0

+

[63:0]: Mc0_ecc_data0, data information in case of an ECC checking error. +64-bit ECC mode data, or 256-bit ECC mode data [63:0]

Memory controller 0 ECC error data register 1 Mc0_ecc_data1

0x0638

RO

Memory controller 0 ECC error data register 1

+

[63:0]: Mc0_ecc_data1, data information in case of an ECC checking error. +256-bit ECC mode data [127:64]

Memory controller 0 ECC error data register 2 Mc0_ecc_data2

0x0640

RO

Memory controller 0 ECC error data register 2

+

[63:0]: Mc0_ecc_data1, data information in case of an ECC checking error. +256-bit ECC mode data [191:128]

Memory controller 0 ECC error data register 3 Mc0_ecc_data3

0x0648

RO

Memory controller 0 ECC error data register 3

+

[63:0]: Mc0_ecc_data3, data information in case of an ECC checking error. +256-bit ECC mode data [255:192]

+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 91. Memory controller 1 error status observation register
RegisterOffset AddressRead/WriteDescription

Memory controller 1 ECC set register Mc1_ecc_set

0x0700

RW

Memory controller 1 ECC set register

+

[5:0]: MC1 int_enable, interrupt enable

+

[8]: MC1 int_trigger, interrupt trigger configuration

+

[21:16]: MC1 int_vector (RO), interrupt vector (read only)

+

[33:32]: MC1 ecc_enable, ECC-related function enable

+

[40]: MC1 rd_before_wr, write after read function enable

0x0708

RW

Reserved

Memory controller 1 ECC counter register Mc1_ecc_cnt

0x0710

RW

Memory controller 1 ECC counter register

+

[7:0]: MC1 int_cnt, configure the ECC checking trigger interrupt count threshold

+

[15:8]: MC1 int_cnt_err (RO), ECC check one bit error count (read only)

+

[23:16]: MC1 int_cnt_fatal (RO), ECC checking error count (read only)

Memory controller 1 ECC error count register Mc1_ecc_cs_cnt

0x0718

RO

Memory controller 1 ECC error count register

+

[7:0]: MC1 ecc_cnt_cs_0, statistics on the number of CS0 ECC checking errors

+

[15:8]: MC1 ecc_cnt_cs_1, statistics on the number of CS1 ECC checking errors

+

[23:16]: MC1 ecc_cnt_cs_2, statistics on the number of CS2 ECC checking errors

+

[31:24]: MC1 ecc_cnt_cs_3, statistics on the number of CS3 ECC checking errors

+

[39:32]: MC1 ecc_cnt_cs_4, statistics on the number of CS4 ECC checking errors

+

[47:40]: MC1 ecc_cnt_cs_5, statistics on the number of CS5 ECC checking errors

+

[55:48]: MC1 ecc_cnt_cs_6, statistics on the number of CS6 ECC checking errors

+

[63:56]: MC1 ecc_cnt_cs_7, statistics on the number of CS7 ECC checking errors

Memory controller 1 ECC checking register Mc1_ecc_code

0x0720

RO

Memory controller 1 ECC checking register

+

[7:0]: MC1 ecc_code_64, 64-bit ECC checking, invalid when memory directory function is enabled

+

[41:32]: MC1 ecc_code_256, 256-bit ECC checking, valid when memory directory function is enabled

+

[52:48]: MC1 ecc_code_dir, memory directory ECC checking, valid only when the memory directory function is enabled

+

[60:56]: MC1 ecc_data_dir, memory directory ECC data, valid only when the memory directory function is enabled

Memory controller 1 ECC error address register Mc1_ecc_addr

0x0728

RO

Memory controller 1 ECC error address register

+

[63:0]: MC1 ecc_addr, ECC checking error address information

Memory controller 1 ECC error data register 0 Mc1_ecc_data0

0x0730

RO

Memory controller 1 ECC error data register 0

+

[63:0]: Mc1_ecc_data0, data information in case of an ECC checking error. +64-bit ECC mode data, or 256-bit ECC mode data [63:0]

Memory controller 1 ECC error data register 1 Mc1_ecc_data1

0x0738

RO

Memory controller 1 ECC error data register 1

+

[63:0]: Mc1_ecc_data1, data information in case of an ECC checking error. +256-bit ECC mode data [127:64]

Memory controller 1 ECC error data register 2 Mc1_ecc_data2

0x0740

RO

Memory controller 1 ECC error data register 2

+

[63:0]: Mc1_ecc_data1, data information in case of an ECC checking error. +256-bit ECC mode data [191:128]

Memory controller 1 ECC error data register 3 Mc1_ecc_data3

0x0748

RO

Memory controller 1 ECC error data register 3

+

[63:0]: Mc1_ecc_data3, data information in case of an ECC checking error. +256-bit ECC mode data [255:192]

+
+
+
+
+
+

14. HyperTransport Controller

+
+
+

In the Loongson 3A5000, the HyperTransport bus is used to enable external device connections and multi-chip interconnections. +When used for peripheral connection, I/O Cache consistency can be freely selected by the user program (set through the address window Uncache, see Retry Count Register). +When configured to support Cache consistency mode, the I/O device access to the internal DMA is transparent to the Cache hierarchy, i.e., the hardware automatically maintains its consistency without the need for software maintenance through program Cache instructions. +When the HyperTransport bus is used for multi-chip interconnects, the HT0 controller (initial address 0x0C00_0000_0000-0x0DFF_FFFF_FFFF) can be pin-configured to support inter-chip Cache. +The HT1 controller (initial address 0x0E00_0000_0000-0x0FFF_FFFF_FFFF) can be configured in software to support interchip Cache consistency maintenance, as described in HyperTransport Multi-processor Support. +In an 8-chip interconnect fabric, the HT1_HI controller’s conformance mode is configured via the pins in CHIP_CONFIG.

+
+
+

The HyperTransport controller supports up to 16-bit width in both directions and 2.4GHz operation. +After the connection is established by automatic system initialization, the user program can change the width and operating frequency and re-initialize by modifying the corresponding configuration registers in the protocol as described in HyperTransport Hardware Configuration and Initialization.

+
+
+

The main features of the Loongson 3A5000 HyperTransport controller are as follows:

+
+
+
    +
  • +

    Support for HT1.0/HT3.0 protocol

    +
    • +
  • +

    Supports 200/400/800/1600/2000/2400/3200MHz operating frequency

    +
    • +
  • +

    HT1.0 supports length of 8 bits

    +
    • +
  • +

    HT3.0 supports length of 8/16 bits

    +
    • +
  • +

    Each HT controller (HT0/HT1) can be configured as two 8-bit HT controllers

    +
    • +
  • +

    Bus control signals (including PowerOK, Rstn, LDT_Stopn) direction can be configured

    +
    • +
  • +

    Peripheral DMA space Cache/Uncache configurable

    +
    • +
  • +

    Configurable for Cache Consistency Mode when used in multi-chip interconnects

    +
    • +
+
+
+

14.1. HyperTransport Hardware Configuration and Initialization

+
+

The HyperTransport bus consists of a transmission signal bus and control signal pins, etc. +The following table gives a description of the HyperTransport bus related pins and their functions.

+
+ + +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+

The initialization of HyperTransport starts automatically after each reset. +After a cold start the HyperTransport bus will automatically operate at the minimum frequency (200MHz) and minimum width (8-bit) and will try to perform a bus initialization handshake. +Whether the initialization is completed or not can be read from the register InitComplete (see Capability Registers). +After the initialization is complete, the width of the bus can be read from the Link Width Out and Link Width In registers (see Capability Registers). +After initialization, the user can rewrite the Link Width Out, Link Width In and Link Freq registers. +The corresponding registers of the other device can also be configured. +After the configuration is completed, a hot reset of the bus or a re-initialization operation via the HT_Ldt_Stopn signal is required to make the rewritten register values effective. +After the reinitialization, the HyperTransport bus will operate at the new frequency and width. +It is important to note that the configuration of the devices on both sides of the HyperTransport needs to correspond to each other, otherwise the HyperTransport interface will not work properly.

+
+
+
+

14.2. HyperTransport Protocol Support

+
+

The Loongson 3A5000’s HyperTransport bus supports most commands in the version 1.03/3.0 protocol and includes some extended commands in the extended conformance protocol that supports multi-chip interconnects. +The commands that can be received by the HyperTransport receiver in both of these modes are shown in the table below. +Note that atomic operation commands for the HyperTransport bus are not supported.

+
+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 93. Commands that can be received by the HyperTransport receiver
EncodeChannelCommandsStandard modeextension (consistency)

000000

-

NOP

Empty package or flow control

000001

NPC

FLUSH

No operation

x01xxx

NPC

+

or

+

PC

Write

bit 5:0 - Nonposted

+

1 - Posted

+

bit 2:0 - Byte

+

1 - Doubleword

+

bit 1: Don’t Care

+

bit 0: Don’t Care

bit 5: Must be 1, POSTED

+

bit 2:0 - Byte

+

1 - Doubleword

+

bit 1: Don’t Care

+

bit 0: Must be 1

01xxxx

NPC

Read

bit 3: Don’t Care

+

bit 2:0 - Byte

+

1 - Doubleword

+

bit 1: Don’t Care

+

bit 0: Don’t Care

bit 3: Don’t Care

+

bit 2:0 - Byte

+

1 - Doubleword

+

bit 1: Don’t Care

+

bit 0: Must be 1

110000

R

RdResponse

Read operation returns

110011

R

TgtDone

The write operation returns

110100

PC

WrCoherent

----

Write command extension

110101

PC

WrAddr

----

Write address extension

111000

R

RespCoherent

----

Read Response Extension

111001

NPC

RdCoherent

----

Read command extension

111010

PC

Broadcast

No operation

111011

NPC

RdAddr

----

Read Address Extension

111100

PC

FENCE

Guaranteed sequential relationships

111111

-

Sync/Error

Sync/Error

+
+

For the sender, the commands that will be sent out in both modes are shown in the table below.

+
+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 94. Commands that will be transported in both modes
CodeChannelCommandsStandard modeextension (consistency)

000000

-

NOP

Blanket or flow control

x01x0x

NPC

+

or

+

PC

Write

bit 5:0 - Nonposted

+

1 - Posted +bit 2:0 - Byte

+

1 - Doubleword +bit 0:Must be 0

bit 5:Must be 1, POSTED

+

bit 2:0 - Byte

+

1 - Doubleword +bit 0:Must be 1

010x0x

NPC

Read

bit 2:0 - Byte

+

1 - Doubleword

+

bit 0:Don’t Care

bit 2:0 - Byte

+

1 - Doubleword

+

bit 0:Must be 1

110000

R

RdResponse

Read operation returns

110011

R

TgtDone

The write operation returns

110100

PC

WrCoherent

----

Write command extension

110101

PC

WrAddr

----

Write address extension

111000

R

RespCoherent

----

Read Response Extension

111001

NPC

RdCoherent

----

Read command extension

111011

NPC

RdAddr

----

Read Address Extension

111111

-

Sync/Error

Will only forward

+
+
+

14.3. HyperTransport Interrupt Support

+
+

The HyperTransport controller provides 256 interrupt vectors to support Fix, Arbiter, and other types of interrupts, but does not provide support for hardware automatic EOI. +For the above two supported types of interrupts, the controller automatically writes to the interrupt register after receiving them and performs interrupt notification to the system interrupt controller according to the setting of the interrupt mask register. +See the description of the interrupt control registers in Interrupt Vector Register for specific interrupt control.

+
+
+

14.3.1. PIC Interrupts

+
+

The controller has made special support for PIC interrupts to speed up the processing of this type of interrupt.

+
+
+

A typical PIC interrupt is completed by the following steps:

+
+
+
    +
  1. +

    The PIC controller sends a PIC interrupt request to the system.

    +
    2. +
  2. +

    The system sends an interrupt vector query to the PIC controller.

    +
    3. +
  3. +

    The PIC controller sends an interrupt vector number to the system.

    +
    4. +
  4. +

    The system clears the corresponding interrupt on the PIC controller.

    +
    5. +
+
+
+

Only after all the above 4 steps are completed, the PIC controller will send the next interrupt to the system. +For the Loongson 3A5000 HyperTransport controller, the first 3 steps will be processed automatically and the PIC interrupt vector will be written to the corresponding location in the 256 interrupt vectors. +And after the software system has processed the interrupt, it needs to process step 4, which is to issue a clear interrupt to the PIC controller. +After that, the processing of the next interrupt starts.

+
+
+
+

14.3.2. Local Interrupts Handling

+
+

In the legacy interrupt handling model, all interrupts are stored by the interrupt vector inside the HT controller and then distributed through the interrupt line of the HT controller connected to the interrupt router on the chip. +In this case, HT interrupts are only available to CPU cores through a limited number of connections, and cannot be distributed across chips, so the usage scenario is rather limited.

+
+
+

In this HT interrupt mode, when performing interrupt processing, the interrupt router on the chip is transparent to the software and the core goes directly to the interrupt vector of the HT controller (typically 0x90000efdfb000080) for lookup and then per-bit processing. +At this point, regardless of how the routing mode is configured, all interrupts on the HT controller are read directly.

+
+
+
+

14.3.3. Extended Interrupts Handling

+
+

The extended I/O interrupts implemented in the 3A5000 can greatly increase the flexibility of interrupt distribution and interrupt handling.

+
+
+

In HT’s interrupt expansion mode, interrupts other than PIC interrupts are written directly to the new extended interrupt register on the chip interrupt router, and then routed or distributed according to the relevant configuration of the extended interrupt register.

+
+
+

After using the extended I/O interrupts, the HT controller is transparent to the software when processing the interrupts, and the cores read the interrupt status directly from the extended I/O status register (configuration space 0x1800) for processing, and each core only reads the interrupt status of the interrupt itself and processes it without interference between different cores.

+
+
+

Interrupt forwarding is performed on the HT controller by enabling the external interrupt transition configuration register. +As described in External Interrupt Conversion Configuration, the software needs to set HT_int_trans to the target address of the Extended I/O Interrupt Trigger Register. +The address of this register in the 3A5000 is 0x1fe01140, or 0x10000_00001140.

+
+
+

Before the kernel can use the extended interrupt processing, it needs to enable the corresponding bit in the “Other function settings register”. +This register has a base address of 0x1fe00000, It can also be accessed using the configuration register instruction (IOCSR), and an offset address of 0x0420.

+
+ + +++++++ + + + + + + + + + + + + + + + + + + +
Table 95. Other function configuration register
Bit FieldNameRead/WriteReset ValueDescription

51:48

EXT_INT_en

RW

0x0

Extended I/O interrupt enable

+
+
+
+

14.4. HyperTransport Address Windows

+
+

14.4.1. HyperTransport Space

+
+

The default address window distribution of the four HyperTransport interfaces in the Loongson 3A5000 processor is as follows.

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 96. Default address window layout of the 4 HyperTransport interfaces
Base AddressEnd AddressSizeDefinition

0x0A00_0000_0000

0x0AFF_FFFF_FFFF

1 Tbytes

HT0_LO Window

0x0B00_0000_0000

0x0BFF_FFFF_FFFF

1 Tbytes

HT0_HI Window

0x0E00_0000_0000

0x0EFF_FFFF_FFFF

1 Tbytes

HT1_LO Window

0x0F00_0000_0000

0x0FFF_FFFF_FFFF

1 Tbytes

HT1_HI Window

+
+

By default (no additional system address windows are configured), the software accesses each HyperTransport interface based on the address space described above, and can also access it from other address spaces by configuring the address windows on the cross-switch (see Address Routing Layout and Configuration). +The internal 40-bit address space of each HyperTransport interface has the address windows distributed as shown in the table below.

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 97. Address window distribution inside the HyperTransport interface of the Loongson 3 processor
Base Addressend addressSizeDefinition

0x00_0000_0000

0xFC_FFFF_FFFF

1012 Gbytes

MEM Space

0xFD_0000_0000

0xFD_F7FF_FFFF

3968 Mbytes

Reserved

0xFD_F800_0000

0xFD_F8FF_FFFF

16 Mbytes

Interrupt

0xFD_F900_0000

0xFD_F90F_FFFF

1 Mbyte

PIC Interrupt Response

0xFD_F910_0000

0xFD_F91F_FFFF

1 Mbyte

System Information

0xFD_F920_0000

0xFD_FAFF_FFFF

30 Mbytes

Reserved

0xFD_FB00_0000

0xFD_FBFF_FFFF

16 Mbytes

HT Controller Configuration Space

0xFD_FC00_0000

0xFD_FDFF_FFFF

32 Mbytes

I/O space

0xFD_FE00_0000

0xFD_FFFF_FFFF

32 Mbytes

HT Controller Configuration Space

0xFE_0000_0000

0xFF_FFFF_FFFF

8 Gbytes

Reserved

+
+
+

14.4.2. HyperTransport Controller Internal Window Configuration

+
+

The HyperTransport interface of the Loongson 3A5000 processor provides a variety of rich address windows for users to use. +The roles and functions of these address windows are described in the following table.

+
+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 98. Address window provided in the HyperTransport interface of the Loongson 3A5000 processor
Address WindowNumber of windowsAcceptance busRoleRemarks

Receive window (See Receive Address Window Configuration Register for window configuration)

3

HyperTransport

Determines whether to receive accesses issued on the HyperTransport bus.

When in master bridge mode (i.e., act_as_slave is 0 in the configuration register), only accesses falling in these address windows will be responded to by the internal bus, and other accesses will be considered as P2P accesses and re-sent back to the HyperTransport bus +When in device mode (i.e., act_as_slave is 1 in the configuration register), only accesses falling in these address windows will be received and processed by the internal bus, and other accesses will be returned with errors according to the protocol.

Post window (see POST Address Window Configuration Register for window configuration)

2

Internal Bus

Determine whether to treat internal bus write accesses to the HyperTransport bus as Post Write

External write accesses that fall in these address spaces will be treated as Post Write. +Post Write: in HyperTransport protocol, this write access does not need to wait for a write completion response, i.e., the write access completion response to the processor will be made after the controller issues this write access to the bus.

Prefetchable window (see Prefetchable Address Window Configuration Register for window configuration)

2

Internal Bus

Determines whether to receive internal Cache accesses as Fetch instructions accesses.

When the processor core is executed in a chaotic order, some guess read accesses or fetch accesses are issued to the bus, which are wrong for some I/O spaces. +By default, such accesses will be returned directly by the HT controller without accessing the HyperTransport bus. +Such accesses to the HyperTransport bus can be enabled through these windows.

Uncache window (see Uncache Address Window Configuration Register for window configuration)

2

HyperTransport

Determine whether to treat accesses on the HyperTransport bus as Uncache accesses to the internal

The I/O DMA accesses inside the Loongson 3A5000 processor will be accessed as Cache by default and will be determined by the SCache to be hit or miss, thus maintaining its I/O consistency information. +The configuration of these windows allows accesses that hit in these windows to access memory directly as Uncache, without maintaining I/O consistency information through hardware.

+
+
+
+

14.5. Configuration Register

+
+

The configuration register module is mainly used to control the configuration register access requests arriving from the AXI SLAVE side or the HT RECEIVER side, to perform external interrupt processing, and to store a large number of software-visible configuration registers used to control the various operating modes of the system.

+
+
+

First of all, the configuration registers used to control the various actions of the HT controller are accessed and stored in this module, and the access offset address of this module is 0xFD_FB00_0000 to 0xFD_FBFF_FFFF on the HT controller side. +All software visible registers in the HT controller are shown in the following table:

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 99. Software visible registers in the HT controller
Enable0x00Device IDVendor ID

0x04

Status

Command

0x08

Class Code

Revision ID

0x0c

BIST

Header Type

Latency Timer

Cache Line Size

0x10

0x14

0x18

0x1c

0x20

0x24

0x28

Cardbus CIS Pointer

0x2c

Subsystem ID

Subsystem Vendor ID

0x30

Expansion ROM Enable Address

0x34

Reserved

Capabilities Pointer

0x38

Reserved

0x3c

Bridge Control

Interrupt Pin

Interrupt Line

Cap 0 PRI

0x40

Command

Capabilities Pointer

Capability ID

0x44

Link Config 0

Link Control 0

0x48

Link Config 1

Link Control 1

0x4C

LinkFreqCap0

Link Error0/Link Freq 0

Revision ID

0x50

LinkFreqCap1

Link Error1/Link Freq 1

Feature

0x54

Error Handling

Enumeration Scratchpad

0x58

Reserved

Mem Limit Upper

Mem Enable Upper

Cap 1 Retry

0x60

Capability Type

Reserved

Capability Pointer

Capabiliter ID

0x64

Status 1

Control 1

Status 0

Control 0

0x68

Retry Count 1

Retry Count 0

CAP 3

0x6C

Capability Type

Revision ID

Capability Pointer

Capabiliter ID

CAP 4 Interrupt

0x70

Capability Type

Index

Capability Pointer

Capabiliter ID

0x74

Dataport

0x78

IntrInfo[31:0]

0x7C

IntrInfo[63:32]

Int Vector

0x80

INT Vector[31:0]

0x84

INT Vector[63:32]

0x88

INT Vector[95:64]

0x8C

INT Vector[127:96]

0x90

INT Vector[159:128]

0x94

INT Vector[191:160]

0x98

INT Vector[223:192]

0x9C

INT Vector[255:224]

0xA0

INT Enable[31:0]

0xA4

INT Enable[63:32]

0xA8

INT Enable[95:64]

0xAC

INT Enable[127:96]

0xB0

INT Enable[159:128]

0xB4

INT Enable[191:160]

0xB8

INT Enable[223:192]

0xBC

INT Enable[255:224]

CAP 5 Gen3

0xC0

Capability Type

Cap Enum/Index

Capability Pointer

Capabiliter ID

0xC4

Global Link Training

0xC8

Transmitter Configuration 0

0xCC

Receiver Configuration 0

0xD0

Link Training 0

0xD4

Frequency Extension

0xD8

Transmitter Configuration 1

0xDC

Receiver Configuration 1

0xE0

Link Training 1

0xE4

BIST Control

Enable

0x100

Device ID

Vendor ID

0x104

Status

Command

0x108

Class Code

Revision ID

0x10c

BIST

Header Type

Latency Timer

Cache Line Size

0x110

0x114

0x118

0x11c

0x120

0x124

0x128

Cardbus CIS Pointer

0x12c

Subsystem ID

Subsystem Vendor ID

0x130

Expansion ROM Enable Address

0x134

Reserved

Capabilities Pointer

0x138

Reserved

0x13c

Bridge Control

Interrupt Pin

Interrupt Line

Receive Windows

0x140

HT RX Enable 0

0x144

HT RX Mask 0

0x148

HT RX Enable 1

0x14C

HT RX Mask 1

0x150

HT RX Enable 2

0x154

HT RX Mask 2

0x158

HT RX Enable 3

0x15C

HT RX Mask 3

0x160

HT RX Enable 4

0x164

HT RX Mask 4

Header Trans

0x168

HT RX Header Trans

0x16C

HT RX EXT Header Trans

Post Windows

0x170

HT TX Post Enable 0

0x174

HT TX Post Mask 0

0x178

HT TX Post Enable 1

0x17C

HT TX Post Mask 1

Prefetchable Windows

0x180

HT TX Prefetchable Enable 0

0x184

HT TX Prefetchable Mask 0

0x188

HT TX Prefetchable Enable 1

0x18C

HT TX Prefetchable Mask 1

Uncache Windows

0x190

HT RX Uncache Enable 0

0x194

HT RX Uncache Mask 0

0x198

HT RX Uncache Enable 1

0x19C

HT RX Uncache Mask 1

0x1A0

HT RX Uncache Enable 2

0x1A4

HT RX Uncache Mask 2

0x1A8

HT RX Uncache Enable 3

0x1AC

HT RX Uncache Mask 3

P2P Windows

0x1B0

HT RX P2P Enable 0

0x1B4

HT RX P2P Mask 0

0x1B8

HT RX P2P Enable 1

0x1BC

HT RX P2P Mask 1

APP Config

0x1C0

APP Configuration 0

0x1C4

APP Configuration 1

0x1C8

RX Bus Value

0x1CC

PHY status

Buffer

0x1D0

TX Buffer 0

0x1D4

TX Buffer 1 / Rx buffer hi

0x1D8

TX Buffer turning

0x1DC

RX Buffer lo

Training

0x1E0

Training 0 Counter Short

0x1E4

Training 0 Counter Long

0x1E8

Training 1 Counter

0x1EC

Training 2 Counter

0x1F0

Training 3 Counter

PLL

0x1F4

PLL Configuration

PHY

0x1F8

I/O Configuration

0x1FC

PHY Configuration

DEBUG

0x240

HT3 DEBUG 0

0x244

HT3 DEBUG 1

0x248

HT3 DEBUG 2

0x24C

HT3 DEBUG 3

0x250

HT3 DEBUG 4

0x254

HT3 DEBUG 5

0x258

HT3 DEBUG 6

POST ID WINDOWS

0x260

HT TX POST ID WIN0

0x264

HT TX POST ID WIN1

0x268

HT TX POST ID WIN2

0x26C

HT TX POST ID WIN3

POST ID WINDOWS

0x270

INT TRANS WIN lo

0x274

INT TRANS WIN hi

+
+

The specific meaning of each register is shown in the following sections.

+
+
+

14.5.1. Bridge Control Register

+
+

Offset: 0x3C

+
+
+

Reset value: 0x00000000

+
+
+

Name: Bus reset control

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 100. Bridge control register
Bit FieldNameLengthReset ValueRead/WriteDescription

31:23

Reserved

9

0x0

Reserved

22

Reset

1

0x0

R/W

Bus reset control.

+

0 → 1: HT_RSTn set to 0, bus reset

+

1 → 0: HT_RSTn is set to 1, the bus is unreset

21:0

Reserved

22

0x0

Reserved

+
+
+

14.5.2. Capability Registers

+
+

Offset: 0x40

+
+
+

Reset value: 0x20010008

+
+
+

Name: Command, capabilities pointer, capability ID

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 101. Definition of command, capabilities pointer, capability ID registers
Bit FieldNameLengthReset ValueRead/WriteDescription

31:29

Slave/Pri

3

0x0

R

Command format is HOST/Sec

28:26

Reserved

2

0x0

R

Reserved

25:21

Unit Count

5

0x0

R/W

Provided to the software for recording the current number of Units

20:16

Unit ID

5

0x0

HOST mode: can be used to record the number of IDs used

+

SLAVE mode: record own Unit ID

+

HOST/SLAVE mode is controlled by act_as_slave register

15:08

Capabilities Pointer

8

0x60

R

Next cap register offset address

7:0

Capability ID

8

0x08

R

HyperTransport capability ID

+
+

Offset: 0x44

+
+
+

Reset value: 0x00112000

+
+
+

Name: Link config, link control

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+

Offset: 0x4C

+
+
+

Reset value: 0x80250023

+
+
+

Name: Revision ID, link freq, link error, link freq cap

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+

Offset: 0x50

+
+
+

Reset value: 0x00000002

+
+
+

Name: Feature capability

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 104. Definition of feature registers
Bit FieldNameLengthReset ValueRead/WriteDescription

31:9

Reserved

23

0x0

Reserved

8

Extended Register

1

0x0

R

No

7:4

Reserved

3

0x0

Reserved

3

Extended CTL Time

1

0x0

R

Not needed

2

CRC Test Mode

1

0x0

R

Not supported

1

LDTSTOP#

1

0x1

R

Support LDTSTOP#

0

Isochronous Mode

1

0x0

R

Not supported

+
+
+

14.5.3. Error Retry Control Register

+
+

Used for HyerTransport 3.0 mode error retransmission enable, to configure the maximum number of Short Retry, to show whether the Retry counter is flipped or not.

+
+
+

Offset: 0x64

+
+
+

Reset value: 0x00000000

+
+
+

Name: Error retry control register

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 105. Error Retry Control Register
Bit FieldNameLengthReset ValueRead/WriteDescription

31:10

Reserved

22

0x0

R

Reserved

9

Retry Count Rollover

1

0x0

R

Retry Counter count rollover

8

Reserved

1

0x0

R

Reserved

7:6

Short Retry Attempts

2

0x0

R/W

Maximum number of Short Retry allowed

5:1

Reserved

5

0x0

R

0

Link Retry Enable

1

0x0

R/W

Error reconnect function enable control

+
+
+

14.5.4. Retry Count Register

+
+

Offset: 0x68

+
+
+

Reset value: 0x00000000

+
+
+

Name: Retry count register

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 106. Retry Count Register
Bit FieldNameLengthReset ValueRead/WriteDescription

31:16

Reserved

16

0x0

R

Reserved

15:0

Retry Count

16

0x0

R

Retry count

+
+
+

14.5.5. Revision ID Register

+
+

Used to configure the controller version, configure it to a new version number and take effect via Warm Reset.

+
+
+

Offset: 0x6C

+
+
+

Reset value: 0x00200000

+
+
+

Name: Revision ID register

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 107. Revision ID Register
Bit FieldNameLengthReset ValueRead/WriteDescription

31:24

Reserved

8

0x0

R

Reserved

23:16

Revision ID

8

0x20

R/W

Revision ID control register.

+

0x20: HyperTransport 1.00.

+

0x60: HyperTransport 3.00

15:0

Reserved

16

0x0

R

Reserved

+
+
+

14.5.6. Interrupt Discovery and Configuration

+
+

Offset: 0x70

+
+
+

Reset value: 0x80000008

+
+
+

Name: Interrupt capability

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 108. Interrupt capability register
Bit FieldNameLengthReset ValueRead/WriteDescription

31:24

Capabilities Pointer

8

0x80

R

Interrupt discovery and configuration block

23:16

Index

8

0x0

R/W

Read register offset address

15:8

Capabilities Pointer

8

0x0

R

Capabilities Pointer

7:0

Capability ID

8

0x08

R

Hypertransport Capablity ID

+
+

Offset: 0x74

+
+
+

Reset value: 0x00000000 +Name: Dataport

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + +
Table 109. Interrupt dataport register
Bit FieldNameLengthReset ValueRead/WriteDescription

31:0

Dataport

32

0x0

R/W

When the previous register Index is 0x10, the result of reading and writing this register is 0xa8 register, otherwise it is 0xac

+
+

Offset: 0x78

+
+
+

Reset value: 0xF8000000

+
+
+

Name: IntrInfo[31:0]

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 110. Interrupt intrlnfo register 1
Bit FieldNameLengthReset ValueRead/WriteDescription

31:24

IntrInfo[31:24]

8

0xF8

R

Reserved

23:2

IntrInfo[23:2]

22

0x0

R/W

IntrInfo[23:2]

+

When a PIC interrupt is issued, the value of IntrInfo is used to represent the interrupt vector

1:0

Reserved

2

0x0

R

Reserved

+
+

Offset: 0x7c

+
+
+

Reset value: 0x00000000

+
+
+

Name: IntrInfo[63:32]

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + +
Table 111. Interrupt intrlnfo register 2
Bit FieldNameLengthReset ValueRead/WriteDescription

31:0

IntrInfo[63:32]

32

0x0

R

Reserved

+
+
+

14.5.7. Interrupt Vector Register

+
+

There are 256 interrupt vector registers, among which Fix, Arbiter and PIC interrupts on the HT bus are directly mapped to these 256 interrupt vectors, while other interrupts such as SMI, NMI, INIT, INTA, INTB, INTC, INTD can be mapped to any 8-bit interrupt vector through register 0x50[28:24]. +The mapping order is {INTD, INTC, INTB, INTA, 1’b0, INIT, NMI, SMI}. +The corresponding value of the interrupt vector is {Interrupt Index, internal vector [2:0]}.

+
+
+

By default, 256-bit interrupts can be distributed to 4-bit interrupt lines. +When not using interrupts from the high 8-bit HT controller, 256-bit interrupts can also be distributed to 8-bit interrupt lines by setting ht_int_8bit.

+
+
+

The 256 interrupt vectors are mapped to different interrupt lines by selecting different register configurations according to the interrupt routing method as follows:

+
+ + ++++++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 112. Interrupt vectors mapping
Number of interruptionsStrip01234567

4

+

X = [63:0]

1

[X]

[X+64]

[X+128]

[X+192]

-

-

-

-

2

[2X]

[2X+1]

[2X+128]

[2X+129]

-

-

-

-

4

[4X]

[4X+1]

[4X+2]

[4X+3]

-

-

-

-

8

+

X = [31:0]

+

Y = [63:32]

1

[X]

[Y]

[X+64]

[Y+64]

[X+128]

[Y+128]

[X+192]

[Y+192]

2

[2X]

[2Y]

[2X+1]

[2Y+1]

[2X+128]

[2Y+128]

[2X+129]

[2Y+129]

4

[4X]

[4X+32]

[4X+1]

[4X+33]

[4X+2]

[4X+34]

[4X+3]

[4X+35]

+
+

As an example of using a 4-bit interrupt line, the different mappings are as follows.

+
+
+

ht_int_stripe_1:

+
+
+

[0,1,2,3…​…​63] Corresponding to interrupted line 0 / HT HI Corresponding to interrupted line 4

+
+
+

[64,65,66,67…​…​127] Corresponding interrupt line 1 / HT HI Corresponding interrupt line 5

+
+
+

[128,129,130,131 …​…​191] corresponds to interrupted line 2 / HT HI corresponds to interrupted line 6

+
+
+

[192,193,194,195 …​…​255] corresponds to the broken line 3 / HT HI corresponds to the broken line 7

+
+
+

ht_int_stripe_2:

+
+
+

[0,2,4,6 …​…​126] corresponds to interrupt line 0 / HT HI corresponds to interrupt line 4

+
+
+

[1,3,5,7 …​…​127] corresponds to interrupt line 1 / HT HI corresponds to interrupt line 5

+
+
+

[128,130,132,134 …​…​254] corresponds to interrupted line 2 / HT HI corresponds to interrupted line 6

+
+
+

[129,131,133,135 …​…​255] corresponds to the interrupt line 3 / HT HI corresponds to the interrupt line 7

+
+
+

ht_int_stripe_4:

+
+
+

[0,4,8,12 …​…​252] corresponds to interrupt line 0 / HT HI corresponds to interrupt line 4

+
+
+

[1,5,9,13 …​…​253] corresponds to interrupt line 1 / HT HI corresponds to interrupt line 5

+
+
+

[2,6,10,14 …​…​254] corresponds to interrupted line 2 / HT HI corresponds to interrupted line 6

+
+
+

[3,7,11,15 …​…​255] corresponds to interrupted line 3 / HT HI corresponds to interrupted line 7

+
+
+

The following description of the interrupt vector corresponds to ht_int_stripe_1, the other two ways can be obtained from the above description.

+
+
+

Offset: 0x80

+
+
+

Reset value: 0x00000000

+
+
+

Name: HT bus interrupt vector register [31:0]

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + +
Table 113. HT bus interrupt vector register definition 1
Bit FieldNameLengthReset ValueRead/WriteDescription

31:0

Interrupt_case[31:0]

32

0x0

R/W

HT bus interrupt vector register [31:0] corresponds to interrupt line 0. +HT HI corresponds to interrupt line 4

+
+

Offset: 0x84

+
+
+

Reset value: 0x00000000

+
+
+

Name: HT bus interrupt vector register[63:32]

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + +
Table 114. HT bus interrupt vector register definition 2
Bit FieldNameLengthReset ValueRead/WriteDescription

31:0

Interrupt_case[63:32]

32

0x0

R/W

HT bus interrupt vector register [63:32] corresponds to interrupt line 0. +HT HI corresponds to interrupt line 4

+
+

Offset: 0x88

+
+
+

Reset value: 0x00000000

+
+
+

Name: HT Bus Interrupt Vector Register [95:64]

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + +
Table 115. HT bus interrupt vector register definition 3
Bit FieldNameLengthReset ValueRead/WriteDescription

31:0

Interrupt_case[95:64]

32

0x0

R/W

HT bus interrupt vector register [95:64] corresponds to interrupt line 1. +HT HI corresponds to interrupt line 5

+
+

Offset: 0x8c

+
+
+

Reset value: 0x00000000

+
+
+

Name: HT bus interrupt vector register [127:96]

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + +
Table 116. HT bus interrupt vector register definition 4
Bit FieldNameLengthReset ValueRead/WriteDescription

31:0

Interrupt_case[127:96]

32

0x0

R/W

HT bus interrupt vector register [127:96] corresponds to interrupt line 1. +HT HI corresponds to interrupt line 5

+
+

Offset: 0x90

+
+
+

Reset value: 0x00000000

+
+
+

Name: HT bus interrupt vector register [159:128]

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + +
Table 117. HT bus interrupt vector register definition 5
Bit FieldNameLengthReset ValueRead/WriteDescription

31:0

Interrupt_case[159:128]

32

0x0

R/W

HT bus interrupt vector register [159:128] corresponds to interrupt line 2. +HT HI corresponds to interrupt line 6

+
+

Offset: 0x94

+
+
+

Reset value: 0x00000000

+
+
+

Name: HT bus interrupt vector register [191:160]

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + +
Table 118. HT bus interrupt vector register definition 6
Bit FieldNameLengthReset ValueRead/WriteDescription

31:0

Interrupt_case[191:160]

32

0x0

R/W

HT bus interrupt vector register [191:160] corresponds to interrupt line 2. +HT HI corresponds to interrupt line 6

+
+

Offset: 0x98

+
+
+

Reset value: 0x00000000

+
+
+

Name: HT bus interrupt vector register [223:192]

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + +
Table 119. HT bus interrupt vector register definition 7
Bit FieldNameLengthReset ValueRead/WriteDescription

31:0

Interrupt_case[223:192]

32

0x0

R/W

HT bus interrupt vector register [223:192] corresponds to interrupt line 3. +HT HI corresponds to interrupt line 7

+
+

Offset: 0x9c

+
+
+

Reset value: 0x00000000

+
+
+

Name: HT bus interrupt vector register [255:224]

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + +
Table 120. HT bus interrupt vector register definition 8
Bit FieldNameLengthReset ValueRead/WriteDescription

31:0

Interrupt_case[255:224]

32

0x0

R/W

HT bus interrupt vector register [255:224] corresponds to interrupt line 3. +HT HI corresponds to interrupt line 7

+
+
+

14.5.8. Interrupt Enable Register

+
+

There are 256 interrupt enable registers, which correspond to the interrupt vector registers. +The interrupt enable register is set to 1 to turn on the corresponding interrupt, and set to 0 to mask the interrupt.

+
+
+

The 256 interrupt vectors are mapped to different interrupt lines according to the configuration of the interrupt routing registers, as follows:

+
+
+

ht_int_stripe_1:

+
+
+

[0,1,2,3…​…​63] Corresponding interrupted line 0 / HT HI Corresponding interrupted line 4

+
+
+

[64,65,66,67…​…​127] Corresponding interrupted line 1 / HT HI Corresponding interrupted line 5

+
+
+

[128,129,130,131…​…​191] Corresponding interrupted line 2 / HT HI Corresponding interrupted line 6

+
+
+

[192,193,194,195…​…​255] Corresponding interrupted line 3 / HT HI Corresponding interrupted line 7

+
+
+

ht_int_stripe_2:

+
+
+

[0,2,4,6…​…​126] Corresponding interrupted line 0 / HT HI Corresponding interrupted line 4

+
+
+

[1,3,5,7…​…​127] Corresponding interrupted line 1 / HT HI Corresponding interrupted line 5

+
+
+

[128,130,132,134…​…​254] Corresponding interrupted line 2 / HT HI Corresponding interrupted line 6

+
+
+

[129,131,133,135…​…​255] Corresponding interrupted line 3 / HT HI Corresponding interrupted line 7

+
+
+

ht_int_stripe_4:

+
+
+

[0,4,8,12…​…​252] Corresponding interrupted line 0 / HT HI Corresponding interrupted line 4

+
+
+

[1,5,9,13…​…​253] Corresponding interrupted line 1 / HT HI Corresponding interrupted line 5

+
+
+

[2,6,10,14…​…​254] Corresponding interrupted line 2 / HT HI Corresponding interrupted line 6

+
+
+

[3,7,11,15…​…​255] Corresponding interrupted line 3 / HT HI Corresponding interrupted line 7

+
+
+

The following description of the interrupt vector corresponds to ht_int_stripe_1, the other two ways can be obtained from the above description.

+
+
+

Offset: 0xa0

+
+
+

Reset value: 0x00000000

+
+
+

Name: HT Bus Interrupt Enable Register [31:0]

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + +
Table 121. HT bus interrupt enable register definition 1
Bit FieldNameLengthReset ValueRead/WriteDescription

31:0

Interrupt_mask[31:0]

32

0x0

R/W

HT bus interrupt enable register [31:0] corresponds to interrupt line 0. +HT HI corresponds to interrupt line 4

+
+

Offset: 0xa4

+
+
+

Reset value: 0x00000000

+
+
+

Name: HT Bus Interrupt Enable Register [63:32]

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + +
Table 122. HT bus interrupt enable register definition 2
Bit FieldNameLengthReset ValueRead/WriteDescription

31:0

Interrupt_mask[63:32]

32

0x0

R/W

HT bus interrupt enable register [63:32] corresponds to interrupt line 0. +HT HI corresponds to interrupt line 4

+
+

Offset: 0xa8

+
+
+

Reset value: 0x00000000

+
+
+

Name: HT Bus Interrupt Enable Register [95:64]

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + +
Table 123. HT bus interrupt enable register definition 3
Bit FieldNameLengthReset ValueRead/WriteDescription

31:0

Interrupt_mask[95:64]

32

0x0

R/W

HT bus interrupt enable register [95:64] corresponds to interrupt line 1. +HT HI corresponds to interrupt line 5

+
+

Offset: 0xac

+
+
+

Reset value: 0x00000000

+
+
+

Name: HT Bus Interrupt Enable Register [127:96]

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + +
Table 124. HT bus interrupt enable register definition 4
Bit FieldNameLengthReset ValueRead/WriteDescription

31:0

Interrupt_mask [127:96]

32

0x0

R/W

HHT bus interrupt enable register [127:96] corresponds to interrupt line 1. +HT HI corresponds to interrupt line 5

+
+

Offset: 0xb0

+
+
+

Reset value: 0x00000000

+
+
+

Name: HT Bus Interrupt Enable Register [159:128]

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + +
Table 125. HT bus interrupt enable register definition 5
Bit FieldNameLengthReset ValueRead/WriteDescription

31:0

Interrupt_mask[159:128]

32

0x0

R/W

HT bus interrupt enable register [159:128] corresponds to interrupt line 2. +HT HI corresponds to interrupt line 6

+
+

Offset: 0xb4

+
+
+

Reset value: 0x00000000

+
+
+

Name: HT Bus Interrupt Enable Register[191:160]

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + +
Table 126. HT bus interrupt enable register definition 6
Bit FieldNameLengthReset ValueRead/WriteDescription

31:0

Interrupt_mask[191:160]

32

0x0

R/W

HT bus interrupt enable register [191:160] corresponds to interrupt line 2. +HT HI corresponds to interrupt line 6

+
+

Offset: 0xb8

+
+
+

Reset value: 0x00000000

+
+
+

Name: HT Bus Interrupt Enable Register [223:192]

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + +
Table 127. HT bus interrupt enable register definition 7
Bit FieldNameLengthReset ValueRead/WriteDescription

31:0

Interrupt_mask[223:192]

32

0x0

R/W

HT bus interrupt enable register [223:192] corresponds to interrupt line 3. +HT HI corresponds to interrupt line 7

+
+

Offset: 0xbc

+
+
+

Reset value: 0x00000000

+
+
+

Name: HT Bus Interrupt Enable Register [255:224]

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + +
Table 128. HT bus interrupt enable register definition 8
Bit FieldNameLengthReset ValueRead/WriteDescription

31:0

Interrupt_mask[255:224]

32

0x0

R/W

HT bus interrupt enable register [255:224] corresponds to interrupt line 3. +HT HI corresponds to interrupt line 7

+
+
+ +
+

HyperTransport 3.0 Link initialization and link training control registers.

+
+
+

Offset: 0xD0

+
+
+

Reset value: 0x00000070

+
+
+

Name: Link train register

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+

14.5.10. Receive Address Window Configuration Register

+
+

The formula for hitting the address window in the HT controller is as follows:

+
+
+
+
hit = ( BASE & MASK ) == ( ADDR & MASK )
+addr_out_trans = TRANS_EN ? TRANS | ADDR & ~MASK : ADDR
+addr_out = Multi_node_en ?
+addr_out_trans[39:37], addr_out_trans[43:40], 3'b0,addr_out[36:0]:
+addr_out_trans
+
+
+
+

It should be noted that when configuring the address window register, the high bits of MASK should be all 1s and the low bits should be all 0 values. +The actual number of bits of 0 in MASK indicates the size of the address window.

+
+
+

The address of the receive address window is the address received on the HT bus. +HT addresses that fall within the P2P window will be forwarded back to the HT bus as P2P commands, HT addresses that fall within the normal receive window and are not in the P2P window will be sent to the CPU, and commands for other addresses will be forwarded back to the HT bus as P2P commands.

+
+
+

Offset: 0x140

+
+
+

Reset value: 0x00000000

+
+
+

Name: HT bus receive address window 0 enable (external access)

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 130. Definition of busreceive address window 0 enable (external access) register
Bit FieldNameLengthReset ValueRead/WriteDescription

31

ht_rx_image0_en

1

0x0

R/W

HT bus receives address window 0, enable signal

30

ht_rx_image0_trans_en

1

0x0

R/W

HT bus receive address window 0, map enable signal

29

ht_rx_image0_multi_node_en

1

0x0

R/W

HT bus receive address window 0, multi-node address mapping enable

+

Convert [39:37] to [46:44] of the address

28

ht_rx_image0_conf_hit_en

1

0x0

R/W

HT bus receive address window 0, protocol address hit enable.

+

Must be set to 0

25:0

ht_rx_image0_trans[49:24]

26

0x0

R/W

HT bus receive address window 0, [49:24] of the mapped address

+
+

Offset: 0x144

+
+
+

Reset value: 0x00000000

+
+
+

Name: HT bus receive address window 0 base address (external access)

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 131. Definition of HT bus receive address window 0 base address (external access) register
Bit FieldNameLengthReset ValueRead/WriteDescription

31:16

ht_rx_image0_base[39:24]

16

0x0

R/W

HT bus receive address window 0, address base address of [39:24]

15:0

ht_rx_image0_mask[39:24]

16

0x0

R/W

HT bus receive address window 0, address mask of [39:24]

+
+

Offset: 0x148

+
+
+

Reset value: 0x00000000

+
+
+

Name: HT bus receive address window 1 enable (external access)

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 132. Definition of HT bus receive address window 1 enable (external access) register
Bit FieldNameLengthReset ValueRead/WriteDescription

31

ht_rx_image1_en

1

0x0

R/W

HT bus receives address window 1, enable signal

30

ht_rx_image1_trans_en

1

0x0

R/W

HT bus receive address window 1, mapping enable signal

29

ht_rx_image1_multi_node_en

1

0x0

R/W

HT bus receive address window 1, multi-node address mapping enable.

+

Convert [39:37] to [46:44] of the address

28

ht_rx_image1_conf_hit_en

1

0x0

R/W

HT bus receive address window 1, protocol address hit enable.

+

Must be set to 0

25:0

ht_rx_image1_trans[49:24]

26

0x0

R/W

HT bus receive address window 1, [49:24] of the mapped address

+
+

Offset: 0x14c

+
+
+

Reset value: 0x00000000

+
+
+

Name: HT bus receive address window 1 base address (external access)

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 133. Definition of bus receive address window 1 base address (external access) register
Bit FieldNameLengthReset ValueRead/WriteDescription

31:16

ht_rx_image1_base[39:24]

16

0x0

R/W

HT bus receive address window 1, [39:24] of the address base address

15:0

ht_rx_image1_mask[39:24]

16

0x0

R/W

HT bus receive address window 1, address mask of [39:24]

+
+

Offset: 0x150

+
+
+

Reset value: 0x00000000

+
+
+

Name: HT bus receive address window 2 enable (External Access)

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 134. Definition of bus receive address window 2 enable (external access) register
Bit FieldNameLengthReset ValueRead/WriteDescription

31

ht_rx_image2_en

1

0x0

R/W

HT bus receives address window 2, enable signal

30

ht_rx_image2_trans_en

1

0x0

R/W

HT bus receive address window 2, mapping enable signal

29

ht_rx_image2_multi_node_en

1

0x0

R/W

HT bus receive address window 2, multi-node address mapping enable.

+

Convert [39:37] to [46:44] of the address

28

ht_rx_image2_conf_hit_en

1

0x0

R/W

HT bus receive address window 2, protocol address hit enable.

+

Must be set to 0

25:0

ht_rx_image2_trans[49:24]

26

0x0

R/W

HT bus receive address window 2, [49:24] of the mapped address

+
+

Offset: 0x154

+
+
+

Reset value: 0x00000000

+
+
+

Name: HT bus receive address window 2 base address (external access)

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 135. Definition of HT bus receive address window 2 base address (external Access) register
Bit FieldNameLengthReset ValueRead/WriteDescription

31:16

ht_rx_image2_base[39:24]

16

0x0

R/W

HT bus receive address window 2, address base address of [39:24]

15:0

ht_rx_image2_mask[39:24]

16

0x0

R/W

HT bus receive address window 2, address masked `[39:24]

+
+

Offset: 0x158

+
+
+

Reset value: 0x00000000

+
+
+

Name: HT bus receive address window 3 enable (external access)

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 136. Definition of HT bus receive address window 3 enable (external access) register
Bit FieldNameLengthReset ValueRead/WriteDescription

31

ht_rx_image3_en

1

0x0

R/W

HT bus receives address window 3, enable signal

30

ht_rx_image3_trans_en

1

0x0

R/W

HT bus receive address window 3, mapping enable signal

29

ht_rx_image3_multi_node_en

1

0x0

R/W

HT bus receive address window 3, multi-node address mapping enable.

+

Convert [39:37] to [46:44] of the address

28

ht_rx_image3_conf_hit_en

1

0x0

R/W

HT bus receive address window 3, protocol address hit enable.

+

Must be set to 0

25:0

ht_rx_image3_trans[49:24]

26

0x0

R/W

HT bus receive address window 3, [49:24] of the mapped address

+
+

Offset: 0x15C

+
+
+

Reset value: 0x00000000

+
+
+

Name: HT bus receive address window 3 base address (external access)

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 137. Definition of HT bus receive address window 3 base address (external access) register
Bit FieldNameLengthReset ValueRead/WriteDescription

31:16

ht_rx_image3_base[39:24]

16

0x0

R/W

HT bus receive address window 3, address base address of [39:24]

15:0

ht_rx_image3_mask[39:24]

16

0x0

R/W

HT bus receive address window 3, address masked [39:24]

+
+

Offset: 0x160

+
+
+

Reset value: 0x00000000

+
+
+

Name: HT bus receive address window 4 enable (external access)

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 138. Definition of HT bus receive address window 4 enable (external access) register
Bit FieldNameLengthReset ValueRead/WriteDescription

31

ht_rx_image4_en

1

0x0

R/W

HT bus receives address window 4, enable signal

30

ht_rx_image4_trans_en

1

0x0

R/W

HT bus receive address window 4, map enable signal

29

ht_rx_image4_multi_node_en

1

0x0

R/W

HT bus receive address window 4, multi-node address mapping enable.

+

Convert [39:37] to [46:44] of the address

28

ht_rx_image4_conf_hit_en

1

0x0

R/W

HT bus receive address window 4, protocol address hit enable.

+

Must be set to 0

25:0

ht_rx_image4_trans[49:24]

26

0x0

R/W

HT bus receive address window 4, [49:24] of the mapped address

+
+

Offset: 0x164

+
+
+

Reset value: 0x00000000

+
+
+

Name: HT bus receive address window 4 base address (external access)

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 139. Definition of HT bus receive address window 4 base address (external access) register
Bit FieldNameLengthReset ValueRead/WriteDescription

31:16

ht_rx_image4_base[39:24]

16

0x0

R/W

HT bus receive address window 4, address base address of [39:24]

15:0

ht_rx_image4_mask[39:24]

16

0x0

R/W

HT bus receive address window 4, address masked [39:24]

+
+
+

14.5.11. Space Conversion Configuration Register

+
+

Used to perform various transformations of the HT’s configuration space.

+
+
+

Offset: 0x168

+
+
+

Reset value: 0x00000000

+
+
+

Name: Configuration space extension address translation

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 140. Definition of configuration space extended address translation register
Bit FieldNameLengthReset ValueRead/WriteDescription

31

ht_rx_header_trans_ext

1

0x1

R/W

Adjust the converted address type1 flag bit of the configuration space (0xFD_FE000000) from 24 bits to 28 bits for unification with the EXT HEADER space

30

ht_rx_header_trans_en

1

0x1

R/W

Enable the high address ([39:24]) of the configuration space (0xFD_FE000000) to be converted

29:0

ht_rx_header_trans[53:24]

30

0xFE00

R/W

High address [53:24] after configuration space conversion (only [53:25] is actually available)

+
+

Offset: 0x16C

+
+
+

Reset value: 0x00000000

+
+
+

Name: Extended address translation

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 141. Definition of extended address translation register
Bit FieldNameLengthReset ValueRead/WriteDescription

30

ht_rx_ext_header_trans_en

1

0x0

R/W

Enables the high address ([39:28]) of the extended configuration space (0xFE_00000000) to be converted

29:0

ht_rx_ext_header_trans[53:24]

30

0x0

R/W

High address [53:24] after extended configuration space conversion (only [53:29] is actually available)

+
+
+

14.5.12. POST Address Window Configuration Register

+
+

The address window hit formula is detailed in Receive Address Window Configuration Register.

+
+
+

The address in this window is the address received on the AXI bus. +All write accesses that land in this window will be returned immediately on the AXI B channel and sent to the HT bus in the POST WRITE command format. +Write requests not in this window, on the other hand, are sent to the HT bus in NONPOST WRITE format and wait for the HT bus response before returning to the AXI bus.

+
+
+

Offset: 0x170

+
+
+

Reset value: 0x00000000

+
+
+

Name: HT bus POST address window 0 enable (internal access)

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 142. HT bus POST address window 0 enable (internal access)
Bit FieldNameLengthReset ValueRead/WriteDescription

31

ht_post0_en

1

0x0

R/W

HT bus POST address window 0, enable signal

30

ht_split0_en

1

0x0

R/W

HT access unpacking enable (corresponds to the external uncache ACC operation window of the CPU core)

29:23

Reserved

14

0x0

Reserved

15:0

ht_post0_trans[39:24]

16

0x0

R/W

HT bus POST address window 0, [39:24] of the translated address

+
+

Offset: 0x174

+
+
+

Reset value: 0x00000000

+
+
+

Name: HT bus POST address window 0 base address (internal access)

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 143. HT bus POST address window 0 base address (internal access)
Bit FieldNameLengthReset ValueRead/WriteDescription

31:16

ht_post0_base[39:24]

16

0x0

R/W

HT bus POST address Window 0, address base address of [39:24]

15:0

ht_post0_mask[39:24]

16

0x0

R/W

HT bus POST address window 0, address masked [39:24]

+
+

Offset: 0x178

+
+
+

Reset value: 0x00000000

+
+
+

Name: HT bus POST address window 1 enable (internal access)

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 144. HT bus POST address window 1 enable (internal access)
Bit FieldNameLengthReset ValueRead/WriteDescription

31

ht_post1_en

1

0x0

R/W

HT bus POST address window 1, enable signal

30

ht_split1_en

1

0x0

R/W

HT access unpacking enable (corresponds to the external uncache ACC operation window of the CPU core)

29:16

Reserved

14

0x0

Reserved

15:0

ht_post1_trans[39:24]

16

0x0

R/W

HT bus POST address window 1, [39:24] of the translated address

+
+

Offset: 0x17c

+
+
+

Reset value: 0x00000000

+
+
+

Name: HT bus POST address window 1 base address (internal access)

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 145. HT bus POST address window 1 base address (internal access)
Bit FieldNameLengthReset ValueRead/WriteDescription

31:16

ht_post1_base[39:24]

16

0x0

R/W

HT bus POST address window 1, address base address of [39:24]

15:0

ht_post1_mask[39:24]

16

0x0

R/W

HT bus POST address window 1, [39:24] of address mask

+
+
+

14.5.13. Prefetchable Address Window Configuration Register

+
+

The address window hit formula is detailed in Receive Address Window Configuration Register.

+
+
+

The address in this window is the address received on the AXI bus. +Fetch instructions and Cache accesses that land in this window are only sent to the HT bus. +Other fetch or Cache accesses will not be sent to the HT bus, but will be returned immediately, or in the case of read instructions, the corresponding number of invalid reads.

+
+
+

Offset: 0x180

+
+
+

Reset value: 0x00000000

+
+
+

Name: HT bus prefetchable address window 0 enable (Internal Access)

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 146. HT bus prefetchable address window 0 enable (internal access)
Bit FieldNameLengthReset ValueRead/WriteDescription

31

ht_prefetch0_en

1

0x0

R/W

HT bus prefetchable address window 0, enable signal

30:16

Reserved

15

0x0

R/W

Reserved

15:0

ht_prefetch0_trans[39:24]

16

0x0

R/W

HT bus prefetchable address window 0, [39:24] of the translated address

+
+

Offset: 0x184

+
+
+

Reset value: 0x00000000

+
+
+

Name: HT bus prefetchable address window 0 base address (internal access)

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 147. HT bus prefetchable address window 0 base address (internal access)
Bit FieldNameLengthReset ValueRead/WriteDescription

31:16

ht_prefetch0_base[39:24]

16

0x0

R/W

HT bus prefetches address window 0, address base address of [39:24] bits

15:0

ht_prefetch0_mask[39:24]

16

0x0

R/W

HT bus prefetchable address window 0, [39:24] of address mask

+
+

Offset: 0x188

+
+
+

Reset value: 0x00000000

+
+
+

Name: HT bus prefetchable address window 1 enable (internal access)

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 148. HT bus prefetchable address window 1 enable (internal access)
Bit FieldNameLengthReset ValueRead/WriteDescription

31

ht_prefetch1_en

1

0x0

R/W

HT bus prefetchable address window 1, enable signal

30:16

Reserved

15

0x0

Reserved

15:0

ht_prefetch1_trans[39:24]

16

0x0

R/W

HT bus prefetchable address window 1, [39:24] of the translated address

+
+

Offset: 0x18c

+
+
+

Reset value: 0x00000000

+
+
+

Name: HT bus prefetchable address window 1 base address (internal access)

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 149. HT bus prefetchable address window 1 base address (internal access)
Bit FieldNameLengthReset ValueRead/WriteDescription

31:16

ht_prefetch1_base[39:24]

16

0x0

R/W

HT bus prefetchable address window 1, address base address of [39:24]

15:0

ht_prefetch1_mask[39:24]

16

0x0

R/W

HT bus prefetchable address window 1, address masked [39:24]

+
+
+

14.5.14. Uncache Address Window Configuration Register

+
+

The address window hit formula is detailed in Receive Address Window Configuration Register.

+
+
+

The address of this window is the address received on the HT bus. +A read or write command that lands in this window will not be sent to SCache and will not invalidate the first-level Cache, but will be sent directly to memory or other address space, i.e., the read or write command in this address window will not maintain Cache consistency of the I/O. +This window is mainly for some operations that will not hit in Cache and therefore can improve the efficiency of accessing memory, such as accessing video memory.

+
+
+

Offset: 0x190

+
+
+

Reset value: 0x00000000

+
+
+

Name: HT bus uncache address window 0 enable (internal access)

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 150. HT bus uncache address window 0 enable (internal access)
Bit FieldNameLengthReset ValueRead/WriteDescription

31

ht_uncache0_en

1

0x0

R/W

HT bus uncache address window 0, enable signal

30

ht_uncache0_trans_en

1

0x0

R/W

HT bus uncache address window 0, mapping enable signal

29

ht_uncache0_multi_node_en

1

0x0

R/W

HT bus uncache receive address window 0, multi-node address mapping enable

28

ht_uncache0_conf_hit_en

1

0x0

R/W

HT bus uncache receive address window 0, protocol address hit enable

25:0

ht_uncache0_trans[49:24]

26

0x0

R/W

HT bus uncache address window 0, [49:24] of the translated address

+
+

Offset: 0x194

+
+
+

Reset value: 0x00000000

+
+
+

Name: HT bus uncache address window 0 base address (internal access)

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 151. HT bus uncache address window 0 base address (internal access)
Bit FieldNameLengthReset ValueRead/WriteDescription

31:16

ht_uncache0_base[39:24]

16

0x0

R/W

HT bus uncache address window 0, address base address of [39:24]

15:0

ht_uncache0_mask[39:24]

16

0x0

R/W

HT bus uncache address window 0, address masked [39:24]

+
+

Offset: 0x198

+
+
+

Reset value: 0x00000000

+
+
+

Name: HT bus uncache address window 1 enabled (internal access)

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 152. HT bus uncache address window 1 enable (internal access)
Bit FieldNameLengthReset ValueRead/WriteDescription

31

ht_uncache1_en

1

0x0

R/W

HT bus uncache address window 1, enable signal

30

ht_uncache1_trans_en

1

0x0

R/W

HT bus uncache address window 1, mapping enable signal

29

ht_uncache1_multi_node_en

1

0x0

R/W

HT bus uncache receive address window 1, multi-node address mapping enable

28

ht_uncache1_conf_hit_en

1

0x0

R/W

HT bus uncache receive address window 1, protocol address hit enable

25:0

ht_uncache1_trans[49:24]

26

0x0

R/W

HT bus uncache address window 1, [49:24] of the translated address

+
+

Offset: 0x19c

+
+
+

Reset value: 0x00000000

+
+
+

Name: HT bus uncache address window 1 base address (internal access)

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 153. HT bus uncache address window 1 base address (internal access)
Bit FieldNameLengthReset ValueRead/WriteDescription

31:16

ht_uncache1_base[39:24]

16

0x0

R/W

HT bus uncache address window 1, address base address of [39:24]

15:0

ht_uncache1_mask[39:24]

16

0x0

R/W

HT bus uncache address window 1, [39:24] of address mask

+
+

Offset: 0x1A0

+
+
+

Reset value: 0x00000000

+
+
+

Name: HT bus uncache address window 2 enable (internal access)

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 154. HT bus uncache address window 2 enable (internal access)
Bit FieldNameLengthReset ValueRead/WriteDescription

31

ht_uncache2_en

1

0x0

R/W

HT bus uncache address window 2, enable signal

30

ht_uncache2_trans_en

1

0x0

R/W

HT bus uncache address window 2, mapping enable signal

29

ht_uncache2_multi_node_en

1

0x0

R/W

HT bus uncache receive address window 2, multi-node address mapping enable

28

ht_uncache2_conf_hit_en

1

0x0

R/W

HT bus uncache receive address window 2, protocol address hit enable

25:0

ht_uncache2_trans[49:24]

26

0x0

R/W

HT bus uncache address window 2, [49:24] of the translated address

+
+

Offset: 0x1A4

+
+
+

Reset value: 0x00000000

+
+
+

Name: HT bus uncache address window 2 base address (internal access)

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 155. HT Bus uncache Address Window 2 Base Address (Internal Access)
Bit FieldNameLengthReset ValueRead/WriteDescription

31:16

ht_uncache2_base[39:24]

16

0x0

R/W

HT bus uncache address window 2, address base address of [39:24]

15:0

ht_uncache2_mask[39:24]

16

0x0

R/W

HT bus uncache address window 2, address masked [39:24]

+
+

Offset: 0x1A8

+
+
+

Reset value: 0x00000000

+
+
+

Name: HT bus uncache address window 3 enabled (internal access)

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 156. HT bus uncache address window 3 enable (internal access)
Bit FieldNameLengthReset ValueRead/WriteDescription

31

ht_uncache3_en

1

0x0

R/W

HT bus uncache address window 3, enable signal

30

ht_uncache3_trans_en

1

0x0

R/W

HT bus uncache address window 3, mapping enable signal

29

ht_uncache3_multi_node_en

1

0x0

R/W

HT bus uncache receive address window 3, multi-node address mapping enable

28

ht_uncache3_conf_hit_en

1

0x0

R/W

HT bus uncache receive address window 3, protocol address hit enable

25:0

ht_uncache3_trans[49:24]

26

0x0

R/W

HT bus uncache address window 3, [49:24] of the translated address

+
+

Offset: 0x1AC

+
+
+

Reset value: 0x00000000

+
+
+

Name: HT Bus uncache address window 3 base address (internal sccess)

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 157. HT Bus uncache address window 3 base address (internal access)
Bit FieldNameLengthReset ValueRead/WriteDescription

31:16

ht_uncache3_base[39:24]

16

0x0

R/W

HT bus uncache address window 3, address base address of [39:24]

15:0

ht_uncache3_mask[39:24]

16

0x0

R/W

HT bus uncache address window 3, address masked [39:24]

+
+
+

14.5.15. P2P Address Window Configuration Register

+
+

The address window hit formula is detailed in Receive Address Window Configuration Register.

+
+
+

The address of this window is the address received on the HT bus. +The read and write commands that land on the address of this window are forwarded directly back to the bus as P2P commands, and this window has the highest priority compared to the normal receive window and the uncache window.

+
+
+

Offset: 0x1B0

+
+
+

Reset value: 0x00000000

+
+
+

Name: HT bus P2P address window 0 enable (external access)

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 158. Definition of HT bus P2P address window 0 enable (external access) register
Bit FieldNameLengthReset ValueRead/WriteDescription

31

ht_rx_p2p0_en

1

0x0

R/W

HT bus P2P address window 0, enable signal

29:0

ht_rx_p2p0_trans[53:24]

30

0x0

R/W

HT bus P2P address window 0, [53:24] of the translated address

+
+

Offset: 0x1B4

+
+
+

Reset value: 0x00000000

+
+
+

Name: HT bus P2P address window 0 base address (external access)

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 159. Definition of HT bus P2P address window 0 base address (external access) register
Bit FieldNameLengthReset ValueRead/WriteDescription

31:16

ht_rx_p2p0_base[39:24]

16

0x0

R/W

HT bus P2P address window 1, address base address of [39:24]

15:0

ht_rx_p2p0_mask[39:24]

16

0x0

R/W

HT bus P2P address window 1, address masked [39:24]

+
+

Offset: 0x1B8

+
+
+

Reset value: 0x00000000

+
+
+

Name: HT bus P2P address window 1 enable (external access)

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 160. Definition of HT bus P2P address window 1 enable (external access) register
Bit FieldNameLengthReset ValueRead/WriteDescription

31

ht_rx_p2p1_en

1

0x0

R/W

HT bus P2P address window 1, enable signal

29:0

ht_rx_p2p1_trans[53:24]

30

0x0

R/W

HT bus P2P address window 1, [53:24] of the translated address

+
+

Offset: 0x1BC

+
+
+

Reset value: 0x00000000

+
+
+

Name: HT bus P2P address window 1 base address (external access)

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 161. Definition of HT bus P2P address window 1 base address (external access) register
Bit FieldNameLengthReset ValueRead/WriteDescription

31:16

ht_rx_p2p1_base[39:24]

16

0x0

R/W

HT bus P2P address window 1, address base address of [39:24]

15:0

ht_rx_p2p1_mask[39:24]

16

0x0

R/W

HT bus P2P address window 1, address masked [39:24]

+
+
+

14.5.16. Controller Parameter Configuration Register

+
+

Offset: 0x1C0

+
+
+

Reset value: 0x00904321

+
+
+

Name: APP CONFIG 0

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 162. Definition of controller parameter configuration register 0
Bit FieldNameLengthReset ValueRead/WriteDescription

31:30

Reserved

1

0x0

Reserved

29

Ldt Stop Gen

1

0x0

R/W

Putting the bus into LDT DISCONNECT mode

+

The correct way is: 0 → 1

28

Ldt Req Gen

1

0x0

R/W

Wake up HT bus from LDT DISCONNECT, set LDT_REQ_n

+

The correct way is to set 0 and then 1: 0 → 1

+

In addition, a direct read/write request to the bus can also wake up the bus automatically

27

rx sample en

1

0x0

R/W

Enable cad and ctl for sample input, displayed in the 0x1c8 register for debugging

26

Dword Write

1

0x1

R/W

For 32/64/128/256-bit MEM write access, whether to use the Dword Write command format (Byte Write method of writing will be converted to 128-bit write with MASK on reception)

25

Dword Write cfg

1

0x1

R/W

For configuration space write access, whether to use the Dword Write command format (Byte Write method of writing will be converted to 128-bit write with MASK when received)

24

Dword Write I/O

1

0x1

R/W

For I/O space write access, whether to use the Dword Write command format (Byte Write method of writing will be converted to 128-bit write with MASK when received)

23

axi aw resize

1

0x0

RW

Whether to reset the size of the 128-bit write with MASK by Mask

22

Coherent Mode

1

0x0

RW

Whether it is processor consistency mode, the initial value is determined by the ICCC_EN pin and takes effect after reset

21

Coherent_split

1

0x0

RW

Consistency mode, split all packets into 32 byte processing

20

Not Care Seqid

1

0x0

R/W

Whether the receiver does not care about HT sequential relations

19:16

Fixed Seqid

4

0x0

R/W

Configure Seqid issued by HT bus when Not Axi2Seqid is valid

15:12

Priority Nop

4

0x4

R/W

HT bus Nop flow control packet priority

11:8

Priority NPC

4

0x3

R/W

Non Post channel read/write priority

7:4

Priority RC

4

0x2

R/W

Response channel read/write priority

3:0

Priority PC

4

0x1

R/W

Post channel read/write priority

+

0x0: Highest priority

+

0xF: Lowest priority

+

For each channel priority are used according to the time change to increase the priority policy, the group memory is used to configure the initial priority of each channel

+
+

Offset: 0x1C4

+
+
+

Reset value: 0x00904321

+
+
+

Name: APP CONFIG1

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 163. Definition of controller parameter configuration register 1
Bit FieldNameLengthReset ValueRead/WriteDescription

31

tx post split en

1

0x0

R/W

Enable write unwrapping when the tx post ID window hits (all write requests that cross a 32-byte bound are split into two consecutive write requests (byte write))

30

tx wr passPW pc

1

0x0

R/W

Set the passPW bit to 1 for all outgoing Post channel write requests

29

tx wr passPW npc

1

0x0

R/W

Set the passPW bit to 1 for all outgoing Nonpost channel write requests

28

tx rd passPW

1

0x0

R/W

Set the passPW bit to 1 for all outgoing read requests

27

stop same id wr

1

0x0

R/W

When the sender encounters a write request with the same AXI ID, it stops sending until the previous request with the same ID returns.

26

stop same id rd

1

0x0

R/W

When the sender encounters a read request with the same AXI ID, it stops sending until the previous request with the same ID returns.

25

Not axi2seqid wr

1

0x0

R/W

Disable the conversion of write request AXI ID to seqid, use fixed seqid directly

24

Not axi2seqid rd

1

0x0

R/W

Disable the conversion of AXI ID to seqid for read requests, use fixed seqid directly

23:22

Reserved

2

0x0

R/W

Reserved

21

act as slave

1

0x1

R/W

Set SLAVE mode

20

Host hide

1

0x0

R/W

Disable access to the configuration register space at the receiving end

19:16

Rrequest delay

4

0x3

R/W

Used to control the random delay range of Rrequest transmission in consistency mode

+

000: 0 delay

+

001: Random delay 0-8

+

010: Random delay 8-15

+

011: Random delay 16-31

+

100: Random delay 32-63

+

101: Random Delay 64-127

+

110: Random Delay 128-255

+

111: 0 delay

15

Crc Int en

1

0x0

R/W

Enable interrupt sending on CRC error

14:12

Crc Int route

3

0x0

R/W

Interrupt pin selection in case of CRC interrupt

11

Reserved

10

ht int 8 bit

1

0x0

R/W

Use of 8 interrupted wires

9:8

ht_int_stripe

2

0x0

R/W

Corresponding to the 3 interrupt routing methods, described in the interrupt vector register

+

0x0: ht_int_stripe_1

+

0x1: ht_int_stripe_2

+

0x2: ht_int_stripe_4

4:0

Interrupt Index

5

0x0

R/W

Which interrupt vector to redirect interrupts other than standard interrupts (including SMI, NMI, INIT, INTA, INTB, INTC, INTD).

+

There are 256 interrupt vectors in total, this register represents the high 5 bits of the interrupt vector, and the internal interrupt vector is as follows.

+

000: SMI

+

001: NMI

+

010: INIT

+

011: Reservered

+

100: INTA

+

101: INTB

+

110: INTC

+

111: INTD

+
+
+

14.5.17. Receive Diagnostic Register

+
+

Offset: 0x1C8

+
+
+

Reset value: 0x00000000

+
+
+

Name: Receive diagnostic register

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 164. Receive diagnostic register
Bit FieldNameLengthReset ValueRead/WriteDescription

31:16

rx_cad_phase_0

16

0x0

R/W

Save the sampled value of input CAD[15:0]

15:8

rx_ctl_catch

8

0x0

R/W

Save the input ctl obtained by sampling.

+

(0, 2, 4, 6) corresponds to the four phases sampled by CTL0.

+

(1, 3, 5, 7) corresponds to the four phases sampled by CTL1

7:0

+
+
+

14.5.18. PHY Status Register

+
+

Used to observe the PHY-related status and debug.

+
+
+

Offset: 0x1CC

+
+
+

Reset value: 0x83308000

+
+
+

Name: PHY status register

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 165. PHY status register
Bit FieldNameLengthReset ValueRead/WriteDescription

31:29

Reserved

3

0x0

R

Reserved

28

dll locked hi

1

0x0

R

High 8 bits - bit DLL locking

27

dll locked lo

1

0x0

R

Low 8 bits - bit DLL locking

26

cdr locked hi

1

0x0

R

High 8 - bit CDR locking

25

cdr locked lo

1

0x0

R

Low 8 bits - bit CDR lock

24

phase locked

1

0x0

R

Phase Lock

23:20

phy state

4

0x0

R

PHY Status

19:17

tx training status

3

0x0

R

TX training state

16:14

rx training status

3

0x0

R

RX training status

13:8

Init done

6

0x0

R

Initialization complete

7:0

Reserved

8

R

Reserved

+
+
+

14.5.19. Transport Command Cache Size Register

+
+

The Command Send Cache Size register is used to observe the number of caches available on the transmitter for each command channel.

+
+
+

Offset: 0x1D0

+
+
+

Reset value: 0x00000000

+
+
+

Name: Command send Cache size register

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 166. Transport command Cache size register
Bit FieldNameLengthReset ValueRead/WriteDescription

31:24

B_CMD_txbuffer

8

0x0

R

Number of B channel command Cache at the transmitter

23:16

R_CMD_txbuffer

8

0x0

R

Number of R channel command Cache at the sender

15:8

NPC_CMD_txbuffer

8

0x0

R

Number of sender NPC channel command Cache

7:0

PC_CMD_txbuffer

8

0x0

R

Number of sender PC channel command Cache

+
+
+

14.5.20. Transport Data Cache Size Register

+
+

The data send Cache size register is used to observe the number of caches available on the transmitter for each data channel.

+
+
+

Offset: 0x1D4

+
+
+

Reset value: 0x00000000

+
+
+

Name: Data send buffer size register

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 167. Transport data Cache size register
Bit FieldNameLengthReset ValueRead/WriteDescription

31

Reserved

1

0x0

R

Reserved

30

rx_buffer_r_data[4]

1

0x0

R/W

Bit [4] of the read data buffer initialization information of the receive buffer

29

rx_buffer_npc_data[4]

1

0x0

R/W

Bit [4] of the npc data buffer initialization information of the receive buffer

28

rx_buffer_pc_data[4]

1

0x0

R/W

Bit [4] of the pc data buffer initialization information of the receive buffer

27

rx_buffer_b_cmd[4]

1

0x0

R/W

Bit [4] of the bresponse command buffer initialization information of the receive buffer

26

rx_buffer_r_cmd[4]

1

0x0

R/W

Bit [4] of the read command buffer initialization information of the receive buffer

25

rx_buffer_npc_cmd[4]

1

0x0

R/W

Bit [4] of the npc command buffer initialization information of the receive buffer

24

rx_buffer_pc_cmd[4]

1

0x0

R/W

Bit [4] of the initialization information of the pc command buffer of the receive buffer

23:16

R_DATA_txbuffer

8

0x0

R

Number of R channel data buffers at the transmitter

15:8

NPC_DATA_txbuffer

8

0x0

R

Number of NPC channel data buffers on the transmitter side

7:0

PC_DATA_txbuffer

8

0x0

R

Number of PC channel data buffer at the sender

+
+
+

14.5.21. Transport Cache Debug Register

+
+

The transmit buffer debug register is used to manually set the number of buffers on the transmit side of the HT controller and to adjust the number of different transmit buffers by increasing or decreasing.

+
+
+

Offset: 0x1D8

+
+
+

Reset value: 0x00000000

+
+
+

Name: Send Cache debug register

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 168. Transport Cache debug register
Bit FieldNameLengthReset ValueRead/WriteDescription

31

b_interleave

1

0x0

R/W

Consistent mode to enable interleaved transmission between channel B and other channels

30

nop_interleave

1

0x0

R/W

Enables interleaved transmission of flow control packets with other virtual channels

29

Tx_neg

1

0x0

R/W

Sender Cache debug symbols

+

0: increase the number of registers

+

1: decrease (the number of registers plus 1)

28

Tx_buff_adj_en

1

0x0

R/W

Sender Cache debug enable register

+

0 → 1: the value of this register will be incremented or decremented once

27:24

R_DATA_txadj

4

0x0

R/W

Increase or decrease the number of R channel data Cache at the transmitter.

+

When tx_neg is 0, increase the number of R_DATA_txadj.

+

When tx_neg is 1, decrease R_DATA_txadj+1

23:20

NPC_DATA_txadj

4

0x0

R/W

Increase or decrease the number of R channel data Cache at the transmitter.

+

When tx_neg is 0, increase the number of R_DATA_txadj.

+

When tx_neg is 1, decrease R_DATA_txadj + 1 number of NPC channel data Cache increment/decrement on the transmitter side

19:16

PC_DATA_txadj

4

0x0

R/W

Increase or decrease the number of PC channel data Cache at the transmitter.

+

When tx_neg is 0, increase the number of PC_DATA_txadj.

+

When tx_neg is 1, decrease PC_DATA_txadj+1

15:12

B_CMD_txadj

4

0x0

R/W

Increase or decrease the number of B channel command Cache at the transmitter.

+

When tx_neg is 0, increase the number of B_CMD_txadj.

+

When tx_neg is 1, decrease B_CMD_txadj+1

11:8

R_CMD_txadj

4

0x0

R/W

Increase or decrease the number of R channel command Cache on the transmitter side.

+

When tx_neg is 0, increase the number of R_CMD_txadj.

+

When tx_neg is 1, decrease R_CMD_txadj+1

7:4

NPC_CMD_txadj

4

0x0

R/W

Increase or decrease the number of NPC channel command/data Cache on the transmitter side.

+

When tx_neg is 0, increase the number of NPC_CMD_txadj.

+

When tx_neg is 1, decrease NPC_CMD_txadj+1

3:0

PC_CMD_txadj

4

0x0

R/W

Increase or decrease the number of PC channel command Cache on the transmitter side.

+

When tx_neg is 0, increase the number of PC_CMD_txadj.

+

When tx_neg is 1, decrease PC_CMD_txadj+1

+
+
+

14.5.22. Receive Buffer Initialization Configuration Register

+
+

Offset: 0x1DC

+
+
+

Reset value: 0x07778888

+
+
+

Name: Receive buffer initialization configuration register

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 169. Receive buffer initialization configuration register
Bit FieldNameLengthReset ValueRead/WriteDescription

27:24

rx_buffer_r_data

4

0x0

R/W

Read data buffer initialization information of the receive buffer

23:20

rx_buffer_npc_data

4

0x0

R/W

Npc data buffer initialization information of the receive buffer

19:16

rx_buffer_pc_data

4

0x0

R/W

Receive buffer initialization information for pc data buffer

15:12

rx_buffer_b_cmd

4

0x0

R/W

Receive the bresponse command buffer initialization information of the buffer

11:8

rx_buffer_r_cmd

4

0x0

R/W

Receive the read command buffer initialization information of the buffer

7:4

rx_buffer_npc_cmd

4

0x0

R/W

Npc command buffer initialization information of the receive buffer

3:0

rx_buffer_pc_cmd

4

0x0

R/W

Receive the pc command buffer initialization information of the buffer

+
+
+

14.5.23. Training 0 Timeout Short Counter Register

+
+

Used to configure the Training 0 short timing timeout threshold in HyerTransport 3.0 mode, with a counter clock frequency of 1/4 of the HyperTransport 3.0 link bus clock frequency.

+
+
+

Offset: 0x1E0

+
+
+

Reset value: 0x00000080

+
+
+

Name: Training 0 timeout short counter register

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 170. Training 0 timeout short counter register
Bit FieldNameLengthReset ValueRead/WriteDescription

31

Gen3_timing_soft

1

0x0

R/W

30:23

Retry_nop_num

8

0x0

R/W

22:0

T0 time

23

0x80

R/W

Training 0 timeout short counter register

+
+
+

14.5.24. Training 0 Timeout Long Counter Register

+
+

Used in HyerTransport 3.0 mode Training 0 long count timeout threshold with counter clock frequency 1/4 of HyperTransport 3.0 link bus clock frequency.

+
+
+

Offset: 0x1E4

+
+
+

Reset value: 0x000fffff

+
+
+

Name: Training 0 timeout count register

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + +
Table 171. Training 0 timeout long counter register
Bit FieldNameLengthReset ValueRead/WriteDescription

31:0

T0 time

32

0xfffff

R/W

Training 0 timeout long counter register

+
+
+

14.5.25. Training 1 Counter Register

+
+

For HyerTransport 3.0 mode Training 1 count threshold, the counter clock frequency is 1/4 of the HyperTransport 3.0 link bus clock frequency.

+
+
+

Offset: 0x1E8

+
+
+

Reset value: 0x0004fffff

+
+
+

Name: Training 1 counter register

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + +
Table 172. Training 1 counter register
Bit FieldNameLengthReset ValueRead/WriteDescription

31:0

T1 time

32

0x4fffff

R/W

Training 1 counter register

+
+
+

14.5.26. Training 2 Counter Register

+
+

For the Training 2 count threshold in HyerTransport 3.0 mode, the counter clock frequency is 1/4 of the HyperTransport 3.0 link bus clock frequency.

+
+
+

Offset: 0x1EC

+
+
+

Reset value: 0x0007fffff

+
+
+

Name: Training 2 counter register

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + +
Table 173. Training 2 counter register
Bit FieldNameLengthReset ValueRead/WriteDescription

31:0

T2 time

32

0x7fffff

R/W

Training 2 counter register

+
+
+

14.5.27. Training 3 Counter Register

+
+

For the Training 3 count threshold in HyerTransport 3.0 mode, the counter clock frequency is 1/4 of the HyperTransport 3.0 link bus clock frequency.

+
+
+

Offset: 0x1F0

+
+
+

Name: Training 3 counter register

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + +
Table 174. Training 3 counter register
Bit FieldNameLengthReset ValueRead/WriteDescription

31:0

T3 time

32

0x7fffff

R/W

Training 3 counter register

+
+
+

14.5.28. Software Frequency Configuration Register

+
+

The controller is used to switch to the link frequency and controller frequency supported by any protocol and PLL during operation; the specific switching method is: under the premise of enabling software configuration mode, set bit 1 of the software frequency configuration register and write the new clock-related parameters, including div_refc and div_loop, which determine the PLL output frequency, the link div_hi_div and phy_lo_div, and the controller’s divide factor core_div. +The controller will automatically reset the PLL and configure the new clock parameters by entering warm reset or LDT disconnect.

+
+
+

PHY_LINK_CLK is the HT bus frequency. +The clock frequency is calculated by the formula:

+
+
+

When using SYS_CLOCK as the reference clock input and SYS_CLOCK is 25MHz (CLKSEL[8] is 1 and CLKSEL[5] is 1), the frequency is calculated as follows:

+
+
+

HyperTransport 1.0:

+
+
+

PHY_LINK_CLK = 12.5MHz × div_loop / div_refc / phy_div

+
+
+

HyperTransport 3.0:

+
+
+

PHY_LINK_CLK = 25MHz × div_loop / div_refc / phy_div

+
+
+

In other cases, the frequency is calculated as:

+
+
+

HyperTransport 1.0:

+
+
+

PHY_LINK_CLK = 50MHz × div_loop / div_refc / phy_div

+
+
+

HyperTransport 3.0:

+
+
+

PHY_LINK_CLK = 100MHz × div_loop / div_refc / phy_div

+
+
+

The wait time for PLL re-lock is approximately 30us by default with system clk at 33M; a custom wait count limit can also be written into the register.

+
+
+

Note that in the 3A5000, HT_CORE_CLK is no longer controlled by this configuration, but by the NODE clock divider.

+
+
+

Offset: 0x1F4

+
+
+

Reset value: 0x00000000

+
+
+

Name: Software frequency configuration register

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 175. Software frequency configuration register
Bit FieldNameLengthReset ValueRead/WriteDescription

31:27

PLL relock counter

5

0x0

R/W

Counter limit configuration register, when set counter select, the counter limit is {PLL_relock_counter ,5’h1f}, otherwise the count limit is 10'3ff

26

Counter select

1

0x0

R/W

Lock Timer Custom Enable.

+

1’b0 - using the default count limit

+

1’b1 - calculated by PLL_relock_counter

25

Reserved

1

0x0

R

Reserved

24:16

Soft_div_loop

7

0x0

R/W

PLL internal frequency multiplication factor

15:12

Soft_div_refc

4

0x0

R/W

PLL internal dividing factor

11:8

Soft_phy_hi_div

4

0x0

R/W

High PHY frequency division factor

7:4

Soft_phy_lo_div

4

0x0

R/W

Low PHY frequency division factor

3

Locked

1

0x0

R

Lock Flag

2

Reserved

1

0x0

R

Reserved

1

Soft cofig enable

1

0x0

R/W

Software configuration enable bit.

+

1’b0 - disable software frequency configuration

+

1’b1 - enables software frequency configuration

0

Reserved

1

0x0

R

Reserved

+
+
+

14.5.29. PHY Impedance Matching Control Register

+
+

Used to control the impedance matching enable of the PHY and the impedance matching parameter setting of the transmitter and receiver.

+
+
+

Offset: 0x1F8

+
+
+

Reset value: 0x00000000

+
+
+

Name: PHY impedance matching control register

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 176. PHY impedance matching control register
Bit FieldNameLengthReset ValueRead/WriteDescription

31

Tx_scanin_en

1

0x0

R/W

TX impedance matching enable

30

Rx_scanin_en

1

0x0

R/W

RX impedance matching enable

27:24

Tx_scanin_ncode

4

0x0

R/W

TX impedance matching scan input ncode

23:20

Tx_scanin_pcode

4

0x0

R/W

TX impedance matching scan input pcode

19:12

Rx_scanin_code

8

0x0

R/W

RX impedance matching scan input

+
+
+

14.5.30. PHY Configuration Register

+
+

Used to configure PHY related physical parameters, when the controller is two independent 8-bit controllers, the high PHY and low PHY are controlled independently by the two controllers. +When the controller is one 16-bit controller, the configuration parameters of the high and low PHY are unified by the low controller.

+
+
+

Offset: 0x1FC

+
+
+

Reset value: 0x83308000

+
+
+

Name: PHY configuration register

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 177. PHY configuration register
Bit FieldNameLengthReset ValueRead/WriteDescription

31

Rx_ckpll_term

1

0x1

R/W

PLL to RX side on-Chip transmission line termination impedance

30

Tx_ckpll_term

1

0x0

R/W

PLL to TX side on-Chip transmission line termination impedance

29

Rx_clk_in_sel_

1

0x0

R/W

Clock PAD supply the clock selection for the data PAD, automatically selected as CLKPAD in HT1 mode:

+

1’b0 - external clock source

+

1’b1 - PLL clock

28

Rx_ckdll_sell

1

0x0

R/W

Clock selection used to lock the DLL.

+

1’b0 - PLL clock

+

1’b1 - external clock source

27:26

Rx_ctle_bitc

2

0x0

R/W

PAD EQD high frequency gain

25:24

Rx_ctle_bitr

2

0x3

R/W

PAD EQD low frequency gain

23:22

Rx_ctle_bitlim

2

0x0

R/W

PAD EQD compensation limit

21

Rx_en_ldo

1

0x1

R/W

LDO Control

+

1’b0 - LDO disable

+

1’b1 - LDO enable

20

Rx_en_by

1

0x1

R/W

BandGap control

+

1’b0 - bandGap disable

+

1’b1 - bandGap enable

19:17

Reserved

3

0x0

R

Reserved

16:12

Tx_preenmp

5

0x08

R/W

PAD pre-emphasis control signal

11:0

Reserved

12

0x0

R

Reserved

+
+
+ +
+

Used to configure whether to use the CDRlock signal provided by the PHY as the link CDR completion flag during link initialization in HyperTransport 3.0 mode. +If the lock signal is ignored, the controller is required to count and wait for a certain amount of time before the default CDR is completed.

+
+
+

Offset: 0x240

+
+
+

Reset value: 0x00000000

+
+
+

Name: Link initialization debug register

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+

14.5.32. LDT Debug Register

+
+

Software changes to the controller frequency will result in inaccurate timing of the LDT reconnect phase. +The counter needs to be configured as the time between the invalidation of the LDT signal and the start of link initialization of the controller after the software configuration of the frequency, which is based on the controller clock.

+
+
+

Offset: 0x244

+
+
+

Reset value: 0x00000000

+
+
+

Name: LDT Debug register 1

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 179. LDT debug register 1
Bit FieldNameLengthReset ValueRead/WriteDescription

31:16

Rx_wait_time

16

0x0

R/W

The RX side waits for the initial value of the counter

15:0

Tx_wait_time

16

0x0

R/W

The TX side waits for the initial value of the counter

+
+

Offset: 0x248

+
+
+

Reset value: 0x00000000

+
+
+

Name: LDT Debug register 2

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 180. LDT debug register 2
Bit FieldNameLengthReset ValueRead/WriteDescription

31:30

Reserved

16

0x0

R/W

29:0

rx lane ts 0

16

0x0

R/W

+
+

Offset: 0x24C

+
+
+

Reset value: 0x00000000

+
+
+

Name: LDT Debug register 3

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 181. LDT debug register 3
Bit FieldNameLengthReset ValueRead/WriteDescription

31:30

Reserved

16

0x0

R/W

29:0

rx lane ts 1

16

0x0

R/W

+
+

Offset: 0x250

+
+
+

Reset value: 0x00000000

+
+
+

Name: LDT Debug register 4

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 182. LDT debug register 4
Bit FieldNameLengthReset ValueRead/WriteDescription

31:30

Reserved

16

0x0

R/W

29:0

rx lane ts 2

16

0x0

R/W

+
+

Offset: 0x254

+
+
+

Reset value: 0x00000000

+
+
+

Name: LDT Debug register 5

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 183. LDT debug register 5
Bit FieldNameLengthReset ValueRead/WriteDescription

31:22

Reserved

10

0x0

R/W

21:18

wait ctl

4

0x0

R/W

17:0

phase lock

18

0x0

R/W

+
+

Offset: 0x258

+
+
+

Reset value: 0x00000000

+
+
+

Name: LDT Debug register 6

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + +
Table 184. LDT debug register 6
Bit FieldNameLengthReset ValueRead/WriteDescription

31:0

wait cad

32

0x0

R/W

+
+
+

14.5.33. HT TX POST ID Window Configuration Register

+
+

This window sends hit requests outbound through the HT POST channel by comparing the ID of the internal write request to a pre-defined window.

+
+
+

Offset: 0x260

+
+
+

Reset value: 0x00000000

+
+
+

Name: HT TX POST ID WIN0

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 185. HT TX POST ID WIN0
Bit FieldNameLengthReset ValueRead/WriteDescription

31:16

HT TX POST ID0 MASK

16

0x0

R/W

AXI ID hit requests are transmitted using the POST window, the MASK bit of the ID

15:0

HT TX POST ID0 BASE

16

0x0

R/W

AXI ID hit requests are transmitted using the POST window, the BASE bit of the ID

+
+

Offset: 0x264

+
+
+

Reset value: 0x00000000

+
+
+

Name: HT TX POST ID WIN1

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 186. HT TX POST ID WIN1
Bit FieldNameLengthReset ValueRead/WriteDescription

31:16

HT TX POST ID1 MASK

16

0x0

R/W

AXI ID hit requests are transmitted using the POST window, the MASK bit of the ID

15:0

HT TX POST ID1 BASE

16

0x0

R/W

AXI ID hit requests are transmitted using the POST window, the BASE bit of the ID

+
+

Offset: 0x268

+
+
+

Reset value: 0x00000000

+
+
+

Name: HT TX POST ID WIN2

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 187. HT TX POST ID WIN2
Bit FieldNameLengthReset ValueRead/WriteDescription

31:16

HT TX POST ID2 MASK

16

0x0

R/W

AXI ID hit requests are transmitted using the POST window, the MASK bit of the ID

15:0

HT TX POST ID2 BASE

16

0x0

R/W

AXI ID hit requests are transmitted using the POST window, the BASE bit of the ID

+
+

Offset: 0x26C

+
+
+

Reset value: 0x00000000

+
+
+

Name: HT TX POST ID WIN3

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 188. HT TX POST ID WIN3
Bit FieldNameLengthReset ValueRead/WriteDescription

31:16

HT TX POST ID3 MASK

16

0x0

R/W

AXI ID hit requests are transmitted using the POST window, the MASK bit of the ID

15:0

HT TX POST ID3 BASE

16

0x0

R/W

AXI ID hit requests are transmitted using the POST window, the BASE bit of the ID

+
+
+

14.5.34. External Interrupt Conversion Configuration

+
+

This setting converts an interrupt received by the HT into a write operation to a specific address that is written directly to the extended I/O interrupt vector inside the chip, rather than generating an interrupt inside the HT controller. +With this approach, advanced features such as direct cross-chip distribution of I/O interrupts can be used.

+
+
+

Offset: 0x270

+
+
+

Reset value: 0x00000000

+
+
+

Name: HT RX INT TRANS Lo

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 189. HT RX INT TRANS Lo
Bit FieldNameLengthReset ValueRead/WriteDescription

31:4

INT_trans_addr[31:4]

28

0x0

R/W

Low order bits of interrupt translation address

3:0

Reserved

4

0x0

R

Reserved

+
+

Offset: 0x274

+
+
+

Reset value: 0x00000000

+
+
+

Name: HT RX INT TRANS Hi

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 190. HT RX INT TRANS Hi
Bit FieldNameLengthReset ValueRead/WriteDescription

31

INT_trans_en

1

0x0

R/W

Interrupt transition enable

30

INT_trans_allow

1

0x0

R/W

Whether to allow interrupt transition

+

This bit is set for INT_trans_en or EXT_INT_en of the chip to take effect

29:26

INT_trans_cache

4

0x0

R/W

Interrupt Transition Cache Field

25:0

INT_trans_addr[58:32]

26

0x0

R/W

High order bits of interrupt translation address

+
+
+
+

14.6. Access to HyperTransport Bus Configuration Space

+
+

The protocol for the HyperTransport interface software layer is basically the same as the PCI protocol, with slightly different specific access details as the access to the configuration space is directly related to the underlying protocol. +As listed in Address window distribution inside the HyperTransport interface of the Loongson 3 processor, the address range of the HT bus configuration space is 0xFD_FE00_0000 to 0xFD_FFFF_FFFF. +For the configuration access in the HT protocol, the following format is used in the Loongson 3A5000:

+
+
+
+access to the ht protocol configuration in the loongson 3a5000 +
+
Figure 9. Access to the HT protocol configuration in the Loongson 3A5000
+
+
+
+

14.7. HyperTransport Multi-processor Support

+
+

The loongson3 processor uses the HyperTransport interface for multiprocessor interconnects and can automatically maintain consistency requests between 2-8 chips in hardware.

+
+
+

Loongson 3 Interconnect Routing

+
+
+

Loongson 3 interconnect routing has two methods, one is to use the simple X-Y routing method. +If a request is sent from 11 to 00, it is routed from 11 to 00, first in the X direction, from 11 to 10, and then in the Y direction, from 10 to 00. +When its response returns from 00 to 11, it is routed first in the X direction, from 00 to 01, and then in the Y direction, from 01 to 11. +from 00 to 01, and then the Y direction, from 01 to 11. +The other is diagonal direct access, which is achieved by connecting two diagonal chips in hardware to greatly reduce access latency, and this access requires separate enablement through software. +Due to the characteristics of this algorithm, a variety of different approaches can be used when building multi-chip interconnects.

+
+
+

Structure of Four Loongson 3 Chips Interconnected

+
+
+

The four CPUs are connected in a two-by-two ring structure. +Each CPU is connected to two adjacent chips using the two 8-bit controllers of HT0 and to the diagonal chip using HT1 HI, resulting in the interconnection structure shown below:

+
+
+
+structure of four loongson 3 chips interconnected +
+
Figure 10. Structure of four Loongson 3 chips interconnected
+
+
+

Structure of Sixteen Loongson 3 Chips Interconnected

+
+
+

The sixteen interconnects use the remaining HT1_LO after the above four interconnects (called Clusters) for interconnecting between Clusters. +The structure is as follows:

+
+
+
+structure of sixteen loongson 3 chips interconnected +
+
Figure 11. Structure of sixteen Loongson 3 chips interconnected
+
+
+

Structure of Two Loongson 3 Chips with 8-bit Interconnection

+
+
+

8-bit HT bus interconnect. +In this interconnect, only 8-bit HT interconnects can be used between the two processors. +The two chip numbers are 00 and 01 respectively, and from the routing algorithm, it can be known that both chips access each other through the same 8-bit HT bus as in the four-chip interconnect. +This is shown below:

+
+
+
+structure of two loongson 3 chips with 8 bit interconnection +
+
Figure 12. Structure of two Loongson 3 chips with 8-bit interconnection
+
+
+

However, the HT bus can be used in 16-bit mode at the widest, and the resulting connection method to maximize bandwidth should be to use a 16-bit interconnect structure. +In Loongson 3, as long as the HT0 controller is set to 16-bit mode, all commands sent to the HT0 controller will be sent to HT0_LO instead of to HT0_HI or HT0_LO respectively according to the routing table as before, so that the 16-bit bus for interconnection can be used. +So, only need to configure the 16-bit mode of CPU0 and CPU1 correctly and connect the high and low buses correctly to use the 16-bit HT bus interconnect. +This interconnection structure can also be accessed using the 8-bit HT bus protocol. +The resulting interconnection structure is as follows:

+
+
+
+structure of two loongson 3 chips with 16 bit interconnection +
+
Figure 13. Structure of two Loongson 3 chips with 16-bit interconnection
+
+
+
+
+
+

15. Low-speed I/O Controller Configuration

+
+
+

The Loongson 3 I/O controllers include a UART controller, SPI controller, I2C and GPIO registers. +These I/O controllers share an AXI port, and CPU requests are sent to the corresponding devices after address decoding.

+
+
+

15.1. UART Controller

+
+

The UART controller has the following features

+
+
+
    +
  • +

    Full duplex asynchronous data receive/send

    +
    • +
  • +

    Programmable data format

    +
    • +
  • +

    16-bit programmable clock counter

    +
    • +
  • +

    Support for receive timeout detection

    +
    • +
  • +

    Multi-interrupt system with arbitration

    +
    • +
  • +

    FIFO-only operation

    +
    • +
  • +

    Compatible with NS16550A in terms of registers and functions

    +
    • +
+
+
+

Two UART interfaces are integrated inside the chip, and the functional registers are exactly the same, only the access base address is different. +UART0 register physical address base address is 0x1FE001E0.

+
+
+

UART1 register physical address base address is 0x1FE001E8.

+
+
+

A physical address is also provided for each of the two UARTs, 0x1FE00100 (UART0) and 0x1FE00110 (UART1) respectively. +The two additional registers RFC and TFC can be accessed through this set of addresses.

+
+
+

15.1.1. Data Transport Register (DAT)

+
+

Name: Data transport register

+
+
+

Length: [7:0]

+
+
+

Offset: 0x00

+
+
+

Reset value: 0x00

+
+ + +++++++ + + + + + + + + + + + + + + + + + + +
Table 191. Data transport register
Bit FieldNameLengthRead/WriteDescription

7:0

Tx FIFO

8

W

Data transport register

+
+
+

15.1.2. Interrupt Enable Register (IER)

+
+

Name: Interrupt enable register

+
+
+

Length: [7:0]

+
+
+

Offset: 0x01

+
+
+

Reset value: 0x00

+
+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 192. Interrupt enable register
Bit FieldNameLengthRead/WriteDescription

7:4

Reserved

4

RW

Reserved

3

IME

1

RW

Modem status interrupt enable

+

0 - off, 1 - on

2

ILE

1

RW

Receiver line status interrupt enable

+

0 - off, 1 - on

1

ITxE

1

RW

Transport save register empty interrupt enable

+

0 - off, 1 - on

0

IRxE

1

RW

Receive valid data interrupt enable

+

0 - off, 1 - on

+
+
+

15.1.3. Interrupt Identity Register (IIR)

+
+

Name: Interrupt source register

+
+
+

Length: [7:0]

+
+
+

Offset: 0x02

+
+
+

Reset value: 0xc1

+
+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 193. Interrupt identity register
Bit FieldNameLengthRead/WriteDescription

7:4

Reserved

4

R

Reserved

3:1

II

3

R

Bits to indicate the interrupt source, as detailed in the following table

0

INTp

1

R

Bits to indicate the interrupt

+ + +++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 194. Table of interrupt control function
Bit 3Bit 2Bit 1PriorityInterrupt TypeInterrupt SourceInterrupt Reset Control

0

1

1

1st

Receive line status

Odd or even, overflow, frame errors, or interrupt interruptions

Read LSR

0

1

0

2nd

Valid data received

The number of characters in the FIFO reaches the level of a trigger

The number of characters in the FIFO is lower than the trigger value

1

1

0

2nd

Receive timeout

At least one character in the FIFO, but no operations, including read and write operations, during the 4-character transport time

Read receive FIFO

0

0

1

3rd

Transport save register is empty

Transport save register is empty

Write data to THR or read IIR

0

0

0

4th

Modem status

CTS, DSR, RI or DCD

Read MSR

+
+
+

15.1.4. FIFO Control Register (FCR)

+
+

Name: FIFO control register

+
+
+

Length: [7:0]

+
+
+

Offset: 0x02

+
+
+

Reset value: 0xc0

+
+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 195. FIFO control register
Bit FieldNameLengthRead/WriteDescription

7:6

TL

2

W

Receive trigger value for interrupt request from FIFO

+

00 - 1 byte

+

01 - 4 byte

+

10 - 8 byte

+

11 - 14 byte

5:3

Reserved

3

W

Reserved

2

Txset

1

W

1 indicates that clearing the contents of the transport FIFO and resetting its logic

1

Rxset

1

W

1 indicates that clearing the contents of the receiving FIFO and resetting its logic

0

Reserved

1

W

Reserved

+
+
+

15.1.5. Line Control Register (LCR)

+
+

Name: Line control register

+
+
+

Length: [7:0]

+
+
+

Offset: 0x03

+
+
+

Reset value: 0x03

+
+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 196. Line control register
Bit FieldNameLengthRead/WriteDescription

7

dlab

1

RW

Frequency division latch access bit

+

1 - access to the operating frequency divider latch

+

0 - access to the operation normal register

6

bcb

1

RW

Interrupt control bit

+

1 - at this time the output of the serial port is set to 0 (interrupted state)

+

0 - normal operation

5

spb

1

RW

Specify parity bit

+

0 - No need to specify parity bit

+

1 - If the LCR[4] bit is 1 then the transport and parity bit is 0. +If the LCR[4] bit is 0 then the transport and parity bit is 1

4

eps

1

RW

Parity bit selection

+

0 - Odd number of 1s in each character (including data and the parity bit)

+

1 - Even number of 1s in each character

3

pe

1

RW

Parity bits enable

+

0 - no parity bits

+

1 - generate parity bits on output, and determine parity bits on input

2

sb

1

RW

Define the number of bits to generate the stop bit

+

0 - 1 stop bit

+

1 - 1.5 stop bits at 5-bit character length, 2 stop bits at other lengths

1:0

bec

2

RW

Set the number of bits per character

+

00 - 5 bits

+

01 - 6 bits

+

10 - 7 bits

+

11 - 8 bits

+
+
+

15.1.6. MODEM Control Register (MCR)

+
+

Name: Modem control register

+
+
+

Length: [7:0]

+
+
+

Offset: 0x04

+
+
+

Reset value: 0x00

+
+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 197. MODEM Control Register
Bit FieldNameLengthRead/WriteDescription

7:5

Reserved

3

W

Reserved

4

Loop

1

W

Loopback mode control bit

+

0 - normal operation

+

1 - Loopback mode. +In the loopback mode, the TXD output is always 1 and the output shift register is directly connected to the input shift register. +Other connections are listed below.

+

DTR → DSR

+

RTS → CTS

+

Out1 → RI

+

Out2 → DCD

3

OUT2

1

W

Connect to DCD input in loopback mode

2

OUT1

1

W

Connect to RI input in loopback mode

1

RTSC

1

W

RTS signal control bit

0

DTRC

1

W

DTR signal control bit

+
+
+

15.1.7. Line State Register (LSR)

+
+

Name: Line status register

+
+
+

Length: [7:0]

+
+
+

Offset: 0x05

+
+
+

Reset value: 0x00

+
+ +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Bit FieldNameLengthRead/WriteDescription

7

ERROR

1

R

Error indication bit

+

1 - at least one of parity bit error, frame error or interrupted interrupt

+

0 - no errors

6

TE

1

R

Transport empty indication bit

+

1 - both the transport FIFO and the transport shift register are empty. +Clear when writing data to the transport FIFO

+

0 - data exists

5

TFE

1

R

Transport FIFO bit empty indication bit

+

1 - the current transport FIFO is empty and is cleared when writing data to the transport FIFO

+

0 - data exists

4

BI

1

R

interrupted interrupt indication bit

+

1 - when received start bit + data + parity bit + stop bit are all 0, there is an interrupted interrupt

+

0 - the interrupt is not interrupted

3

FE

1

R

Frame error indication bit

+

1 - the received data has no stop bit

+

0 - no errors

2

PE

1

R

Parity bit error indication bit

+

1 - current received data has parity error

+

0 - no parity errors

1

OE

1

R

Data overflow indication bit

+

1 - data overflow exists

+

0 - no overflow

0

DR

1

R

Receive data valid indication bit

+

0 - no data in the FIFO

+

1 - data exists in the FIFO

+
+

When reading this register, LSR[4:1] and LSR[7] are cleared to zero, LSR[6:5] is cleared when writing data to the transmit FIFO, and LSR[0] is judged for the receive FIFO.

+
+
+
+

15.1.8. MODEM State Register (MSR)

+
+

Name: Modem status register

+
+
+

Length: [7:0]

+
+
+

Offset: 0x06

+
+
+

Reset value: 0x00

+
+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 198. MODEM state register
Bit FieldNameLengthRead/WriteDescription

7

CDCD

1

R

The inverse of the DCD input, or connected to Out2 in loopback mode

6

CRI

1

R

The inverse of the RI input, or connected to OUT1 in loopback mode

5

CDSR

1

R

The inverse of the DSR input, or connected to DTR in loopback mode

4

CCTS

1

R

The inverse of the CTS input, or connected to the RTS in loopback mode

3

DDCD

1

R

DDCD indicator bit

2

TERI

1

R

RI edge detection, RI state changes from low to high

1

DDSR

1

R

DDSR indicator bit

0

DCTS

1

R

DCTS indicator bit

+
+
+

15.1.9. Receive FIFO Counter (RFC)

+
+

Name: Receive FIFO count value

+
+
+

Length: [7:0]

+
+
+

Offset: 0x08

+
+
+

Reset value: 0x00

+
+ + +++++++ + + + + + + + + + + + + + + + + + + +
Table 199. Receive FIFO counter
Bit FieldNameLengthRead/WriteDescription

7:0

RFC

8

R

Reflects the number of valid data in the current received FIFO

+
+
+

15.1.10. Transport FIFO Counter (TFC)

+
+

Name: Transport FIFO Count value

+
+
+

Length: [7:0]

+
+
+

Offset: 0x09

+
+
+

Reset value: 0x00

+
+ + +++++++ + + + + + + + + + + + + + + + + + + +
Table 200. Transport FIFO counter
Bit FieldNameLengthRead/WriteDescription

7:0

RFC

8

R

Reflects the number of valid data in the current transport FIFO

+
+
+

15.1.11. Frequency Division Latchs

+
+

Name: Frequency Divider Latch 1

+
+
+

Length: [7:0]

+
+
+

Offset: 0x00

+
+
+

Reset value: 0x00

+
+ + +++++++ + + + + + + + + + + + + + + + + + + +
Table 201. Frequency division latchs 1
Bit FieldNameLengthRead/WriteDescription

7:0

LSB

8

RW

Store the lower 8 bits of the division latch

+
+

Name: Frequency Divider Latch 2

+
+
+

Length: [7:0]

+
+
+

Offset: 0x01

+
+
+

Reset value: 0x00

+
+ + +++++++ + + + + + + + + + + + + + + + + + + +
Table 202. Frequency division latchs 2
Bit FieldNameLengthRead/WriteDescription

7:0

MSB

8

RW

Store the higher 8 bits of the division latch

+
+

Name: frequency divider latch 3

+
+
+

Length: [7:0]

+
+
+

Offset: 0x02

+
+
+

Reset value: 0x00

+
+ + +++++++ + + + + + + + + + + + + + + + + + + +
Table 203. Frequency division latchs 3
Bit FieldNameLengthRead/WriteDescription

7:0

D_DIV

8

RW

Store the decimal division value of the division latch

+
+
+

15.1.12. Use of New Registers

+
+

The new receive FIFO counter (RFC) allows the CPU to detect the number of valid data in the Receive FIFO, so that the CPU can read multiple data continuously after receiving an interrupt, improving the CPU’s ability to process UART received data.

+
+
+

Transport FIFO Counter (TFC) for the CPU to detect the number of valid data in the transport FIFO, whereby the CPU can continuously send multiple data while ensuring that the transport FIFO does not overflow, improving the CPU’s ability to process UART transport data.

+
+
+

Frequency divider latch 3 (i.e. fractional divider register) is used to solve the problem that the required baud rate cannot be obtained accurately by dividing by integers only. +The integer part of the quotient is assigned to the MSB and LSB by the divider latch, and the fractional part is assigned to the divider latch D_DIV by multiplying by 256.

+
+
+
+
+

15.2. SPI Controller

+
+

The SPI controller has the following features:

+
+
+
    +
  • +

    Full-duplex synchronous serial data transmission

    +
    • +
  • +

    Variable length byte transport support up to 4

    +
    • +
  • +

    Master mode support

    +
    • +
  • +

    Mode failure generates an error flag and issues an interrupt request

    +
    • +
  • +

    Dual buffered receivers

    +
    • +
  • +

    Polarity and phase programmable serial clock

    +
    • +
  • +

    SPI can be controlled in wait mode

    +
    • +
  • +

    Boot from SPI support

    +
    • +
  • +

    Dual/Quad mode SPI FLASH support

    +
    • +
+
+
+

The SPI controller register physical address base address is 0x1FE001F0.

+
+ +++++ + + + + + + + + + + + + + + + + + + + + + + + + +
Address NameAddress RangeSize

SPI Boot

0X1FC0_0000-0X1FD0_0000

1MByte

SPI Memory

0X1D00_0000-0X1E00_0000

16MByte

SPI Register

0X1FE0_01F0-0X1FE0_01FF

16Byte

+
+

The SPI Boot address space is the first address space accessed by the processor when the system boots up, and the 0xBFC00000 address is automatically routed to the SPI.

+
+
+

The SPI Memory space can also be accessed directly through a read request from the CPU, and its minimum 1M bytes overlap with the SPI BOOT space.

+
+
+

15.2.1. Control Register (SPCR)

+
+

Name: SPI FLASH control register

+
+
+

Length: [7:0]

+
+
+

Offset: 0x00

+
+
+

Reset value: 0x10

+
+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 204. Control register
Bit FieldNameLengthRead/WriteDescription

7

Spie

1

RW

Interrupt output enable signal (active high)

6

spe

1

RW

System operation enable signal (active high)

5

Reserved

1

RW

Reserved

4

mstr

1

RW

Master mode select bit, this bit is always 1

3

cpol

1

RW

Clock polarity bits

2

cpha

1

RW

Clock phase bit of 1 indicates opposite phase, 0 indicates same phase

1:0

spr

2

RW

sclk_o frequency division setting, need to be used with sper's `spre

+
+
+

15.2.2. State Register (SPSR)

+
+

Name: Status register

+
+
+

Length: [7:0]

+
+
+

Offset: 0x01

+
+
+

Reset value: 0x05

+
+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 205. State register
Bit FieldNameLengthRead/WriteDescription

7

spif

1

RW

Interrupt flag bit. +1 indicates an interrupt request and write 1 to clear

6

wcol

1

RW

Write register overflow flag bit. +1 indicates overflow, and write 1 to clear

5:4

Reserved

2

RW

Reserved

3

wffull

1

RW

Write register full flag. +1 indicates full

2

wfempty

1

RW

Write register empty flag. +1 indicates empty

1

rffull

1

RW

Read register full flag. +1 indicates full

0

rfempty

1

RW

Read register empty flag. +1 indicates empty

+
+
+

15.2.3. Transport Data Register (TxFIFO)

+
+

Name: Transport data register

+
+
+

Length: [7:0]

+
+
+

Offset: 0x02

+
+
+

Reset value: 0x00

+
+ + +++++++ + + + + + + + + + + + + + + + + + + +
Table 206. Transport data register
Bit FieldNameLengthRead/WriteDescription

7:0

Tx FIFO

8

W

Transport data register

+
+
+

15.2.4. External Register (SPER)

+
+

Name: External register

+
+
+

Length: [7:0]

+
+
+

Offset: 0x03

+
+
+

Reset value: 0x00

+
+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 207. External register
Bit FieldNameLengthRead/WriteDescription

7:6

icnt

2

RW

Send an interrupt request signal after how many bytes have been transported

+

00 - 1 byte

+

01 - 2 bytes

+

10 - 3 bytes

+

11 - 3 bytes

5:2

Reserved

4

RW

Reserved

1:0

spre

2

RW

Set the ratio of the frequency division together with spr

+ + +++++++++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 208. Frequency division factor
spre000000000101010110101010

spr

00

01

10

11

00

01

10

11

00

01

10

11

Frequency division factor

2

4

16

32

8

64

128

256

512

1024

2048

4096

+
+
+

15.2.5. Parameter Control Register (SFC_PARAM)

+
+

Name: SPI FLASH parameter control register

+
+
+

Length: [7:0]

+
+
+

Offset: 0x04

+
+
+

Reset value: 0x21

+
+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 209. Parameter control register
Bit FieldNameLengthRead/WriteDescription

7:4

clk_div

4

RW

Clock division number selection (the division factor is the same as the {spre, spr} combination)

3

dual_io

1

RW

Use dual I/O mode with higher priority than fast read mode

2

fast_read

1

RW

Use fast read mode

1

burst_en

1

RW

SPI FLASH supports continuous address read mode

0

memory_en

1

RW

SPI FLASH read enable, when invalid csn[0] can be controlled by software

+
+
+

15.2.6. Chip Select Control Register (SFC_SOFTCS)

+
+

Name: SPI FLASH chip select control register

+
+
+

Length: [7:0]

+
+
+

Offset: 0x05

+
+
+

Reset value: 0x00

+
+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 210. Chip select control register
Bit FieldNameLengthRead/WriteDescription

7:4

csn

4

RW

csn pin output

3:0

csen

4

RW

The cs line corresponding to the bit with 1 is controlled by the [7:4] bits

+
+
+

15.2.7. Timing Control Register (SFC_TIMING)

+
+

Name: SPI FLASH timing control register

+
+
+

Length: [7:0]

+
+
+

Offset: 0x06

+
+
+

Reset value: 0x03

+
+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 211. Timing control register
Bit FieldNameLengthRead/WriteDescription

7:4

Reserved

4

RW

Reserved

3

quad_io

1

RW

4-wire mode enable. +1 indicates valid

2

tFast

1

RW

1:0

tCSH

2

RW

The minimum invalidation time of the SPI FLASH chip select signal, calculated as the clock period T after frequency division

+

00: 1T

+

01: 2T

+

10: 4T

+

11: 8T

+
+
+

15.2.8. Custom Controller Register (CTRL)

+
+

Name: SPI FLASH custom control register

+
+
+

Length: [7:0]

+
+
+

Offset: 0x08

+
+
+

Reset value: 0x00

+
+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 212. Custom controller register
Bit FieldNameLengthRead/WriteDescription

7:4

nbyte

4

RW

Number of bytes in one transport

3:2

reserve

2

RW

Reserved

1

nbmode

1

RW

Multi-byte transport mode

0

start

1

RW

Start multi-byte transport, auto-zero when finished

+
+
+

15.2.9. Custom Command Register (CMD)

+
+

Name: SPI FLASH custom command register

+
+
+

Length: [7:0]

+
+
+

Offset: 0x09

+
+
+

Reset value: 0x00

+
+ + +++++++ + + + + + + + + + + + + + + + + + + +
Table 213. Custom command register
Bit FieldNameLengthRead/WriteDescription

7:0

cmd

8

RW

Set the command to transport to SPI FLASH

+
+
+

15.2.10. Custom Data Register 0 (BUF0)

+
+

Name: SPI FLASH custom data register 0

+
+
+

Length: [7:0]

+
+
+

Offset: 0x0a

+
+
+

Reset value: 0x00

+
+ + +++++++ + + + + + + + + + + + + + + + + + + +
Table 214. Custom data register 0
Bit FieldNameLengthRead/WriteDescription

7:0

buf0

8

RW

When transporting a write command to the SPI, this register configures the first byte of data sent; when transporting a read command to the SPI, this register stores the first data read back.

+
+
+

15.2.11. Custom Data Register 1 (BUF1)

+
+

Name: SPI FLASH custom data register 1

+
+
+

Length: [7:0]

+
+
+

Offset: 0x0b

+
+
+

Reset value: 0x00

+
+ + +++++++ + + + + + + + + + + + + + + + + + + +
Table 215. Custom data register 1
Bit FieldNameLengthRead/WriteDescription

7:0

buf1

8

RW

When transporting a write command to the SPI, this register configures the second byte of data sent; when transporting a read command to the SPI, this register stores the second data read back.

+
+
+

15.2.12. Custom Timing Register 0 (TIMER0)

+
+

Name: SPI FLASH custom timing register 0

+
+
+

Length: [7:0]

+
+
+

Offset: 0x0c

+
+
+

Reset value: 0x00

+
+ + +++++++ + + + + + + + + + + + + + + + + + + +
Table 216. Custom timing register 0
Bit FieldNameLengthRead/WriteDescription

7:0

time0

8

RW

Lower 8 bits of the time value required for the custom command

+
+
+

15.2.13. Custom Timing Register 1 (TIMER1)

+
+

Name: SPI FLASH custom timing register 1

+
+
+

Length: [7:0]

+
+
+

Offset: 0x0d

+
+
+

Reset value: 0x00

+
+ + +++++++ + + + + + + + + + + + + + + + + + + +
Table 217. Custom timing register 1
Bit FieldNameLengthRead/WriteDescription

7:0

time1

8

RW

Middle 8 bits of the time value required for the custom command

+
+
+

15.2.14. Custom Timing Register 2 (TIMER2)

+
+

Name: SPI FLASH custom timing register 2

+
+
+

Length: [7:0]

+
+
+

Offset: 0x0e

+
+
+

Reset value: 0x00

+
+ + +++++++ + + + + + + + + + + + + + + + + + + +
Table 218. Custom timing register 2
Bit FieldNameLengthRead/WriteDescription

7:0

time2

8

RW

Higher 8 bits of the time value required for the custom command

+
+
+

15.2.15. Guide to the Use of SPI Dual/Quad Mode

+
+

In addition to the legacy single-wire mode, the SPI controller also supports two operating modes, dual mode and quad mode, for booting from the SPI FLASH. +The SPI controller can be put into dual mode by setting the dual_io register, and quad mode by setting the quad_io register. +The configuration code for these two registers can be added to the first few instructions of the BIOS code, and then the controller will be pointed to the corresponding operating mode after the configuration is completed, which can improve the boot-up speed.

+
+
+

Note that some SPI FLASHs do not enable quad mode by default, or need to configure timing related parameters in quad mode (e.g.Dummy clocks). +In order to increase the applicability of SPI controller to various FLASHs, this controller adds custom registers (0x8-0xe). +The specific usage is:

+
+
+
    +
  1. +

    Setting the Custom command register (CMD) (0x9), which is the command sent to the SPI FLASH.

    +
    2. +
  2. +

    Configuring the wait time into the custom timing registers TIMER0-TIMER2 (0xc-0xe) if the SPI FLASH requires that the command sent this time takes a while to complete, otherwise these registers remain at the default value of 0.

    +
    3. +
  3. +

    If writing configuration information to the SPI FLASH, the configuration information needs to be written to the custom data registers BUF0-BUF1 (0xa-0xb); if reading configuration information to the SPI FLASH, these two registers store the read back values.

    +
    4. +
  4. +

    Configuration custom control register CTRL[7:1] where CTRL[1] (nbmode) represents that the multi-byte transport mode will be performed, and the number of bytes to be transported this time is given by CTRL[7:4] (nbyte).

    +
    5. +
  5. +

    Configure the custom control register CTRL[0] to start this transport.

    +
    6. +
+
+
+

Generally, the registers to be configured are located in the non-volatile memory of FLASH, so the above configuration is only needed once.

+
+
+
+
+

15.3. I2C Controller

+
+

This chapter gives a detailed description of the I2C and its configuration for use. +The system chip has an integrated I2C interface, which is mainly used to implement the exchange of data between two devices. +The I2C bus is a serial bus consisting of a data line SDA and a clock SCL to send and receive data. +Bi-directional transmission is performed between devices with a maximum transmission rate of 400kbps.

+
+
+

The I2C controller integrated in the Loongson 3A5000 can act as either a master or a slave device, and the two modes are switched between by configuring internal registers. +As a slave device, it is only used to read the internal temperature of the chip, and the address of the slave device is specified by register SLV_CTRL[6:0].

+
+
+

The physical address base address of the I2C0 controller register is 0x1FE00120. +The I2C1 controller register physical address base address is 0x1FE00130. +The specific internal registers are described below.

+
+
+

15.3.1. Frequency Division Latch Low-order Byte Register (PRERlo)

+
+

Name: Frequency division latch low-order byte register

+
+
+

Length: [7:0]

+
+
+

Offset: 0x00

+
+
+

Reset value: 0xff

+
+ + +++++++ + + + + + + + + + + + + + + + + + + +
Table 219. Frequency division latch low-order byte register
Bit FieldNameLengthRead/WriteDescription

7:0

PRERlo

8

RW

Store the lower 8 bits of the division latch

+
+
+

15.3.2. Frequency Division Latch High-order Byte Register (PRERhi)

+
+

Name: Frequency division latch high-order byte register

+
+
+

Length: [7:0]

+
+
+

Offset: 0x01

+
+
+

Reset value: 0xff

+
+ + +++++++ + + + + + + + + + + + + + + + + + + +
Table 220. Frequency division latch high-order byte register
Bit FieldNameLengthRead/WriteDescription

7:0

PRERhi

8

RW

Store the high 8 bits of the division latch

+
+

Assuming that the value of the divider latch is prescale, the frequency of the PCLK clock input from the LPB bus is clock_a, and the output frequency of the SCL bus is clock_s, the following relationship should be satisfied:

+
+
+

Prcescale = clock_a/(4*clock_s)-1

+
+
+
+

15.3.3. Control Register (CTR)

+
+

Name: Control register

+
+
+

Length: [7:0]

+
+
+

Offset: 0x02

+
+
+

Reset value: 0x20

+
+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 221. Control register
Bit FieldNameLengthRead/WriteDescription

7

EN

1

RW

Module operating enable bit

+

1 - normal operation mode

+

0 - operation of the division register

6

IEN

1

RW

Interrupt enable bit. +1 indicates enable interrupt

5

MST_EN

1

RW

Module master-slave selection

+

0: slave mode

+

1: master mode

4:0

Reserved

5

RW

Reserved

+
+
+

15.3.4. Transport Data Register (TXR)

+
+

Name: Transport data register

+
+
+

Length: [7:0]

+
+
+

Offset: 0x03

+
+
+

Reset value: 0x00

+
+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 222. Transport data register
Bit FieldNameLengthRead/WriteDescription

7:1

DATA

7

W

Store the next byte to be transported

0

DRW

1

W

When data is transported, this bit stores the lowest bit of the data.

+

When the address is transported, this bit indicates the read and write status

+
+
+

15.3.5. Receive Data Register (RXR)

+
+

Name: Receive data register

+
+
+

Length: [7:0]

+
+
+

Offset: 0x03

+
+
+

Reset value: 0x00

+
+ + +++++++ + + + + + + + + + + + + + + + + + + +
Table 223. Receive data register
Bit FieldNameLengthRead/WriteDescription

7:0

RXR

8

R

Store the last received byte

+
+
+

15.3.6. Command Control Register (CR)

+
+

Name: Command register

+
+
+

Length: [7:0]

+
+
+

Offset: 0x04

+
+
+

Reset value: 0x00

+
+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 224. Command control register
Bit FieldNameLengthRead/WriteDescription

7

STA

1

W

Generate the START signal

6

STO

1

W

Generate the STOP signal

5

RD

1

W

Generate the read signal

4

WR

1

W

Generate the write signal

3

ACK

1

W

Generate the response signal

2:1

Reserved

2

W

Reserved

0

IACK

1

W

Generate interrupt response signal

+
+

Both are automatically cleared by the hardware after the I2C sends data. +Read operation of these bits always reads back 0. +A bit 3 of 1 means that the controller does not send ack at the end of this transmission, and vice versa at the end.

+
+
+
+

15.3.7. State Register (SR)

+
+

Name: Status register

+
+
+

Length: [7:0]

+
+
+

Offset: 0x04

+
+
+

Reset value: 0x00

+
+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 225. State register
Bit FieldNameLengthRead/WriteDescription

7

RxACK

1

R

Receive response bit

+

1 - no receive the response bit

+

0 - receive the response bit

6

Busy

1

R

I2c bus busy flag bit

+

1 - bus is busy

+

0 - bus is free

5

AL

1

R

When the I2C core loses control of the I2C bus, this bit is 1

4:2

Reserved

3

R

Reserved

1

TIP

1

R

Indicate the process of transport

+

1 - indicate that data is being transported

+

0 - indicate that data transport is complete

0

IF

1

R

Interrupt flag bit. +When one data transport is finished, or another device initiates data transport, this bit is 1

+
+
+

15.3.8. Slave Device Controller Register (SLV_CTRL)

+
+

Name: Slave device control register

+
+
+

Length: [7:0]

+
+
+

Offset: 0x07

+
+
+

Reset value: 0x00

+
+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 226. Slave device controller register
Bit FieldNameLengthRead/WriteDescription

7

SLV_EN

1

WR

Slave mode enable, active when MST_EN is 0. +It can be used to reset the internal logic of the slave

6:0

SLV_ADDR

7

WR

Slave mode I2C address. +It can be configured via software

+
+
+
+
+
+

16. Kernel Support

+
+
+

16.1. New Feature Support

+
+

In order to use the new features provided by the 3A5000 processor in the kernel, they can be identified or enabled according to the following methods. +Only the parts that can improve system performance are described here.

+
+
+

16.1.1. Extended Interrupt Mode

+
+

In order to enable the extended interrupt mode in the kernel, set it up in the following order.

+
+
+
    +
  1. +

    Extended interrupt mode support is identified by CSR[0x8][3].

    +
    2. +
  2. +

    The external interrupt translation register of the HT controller that is expected to support extended interrupt mode needs to be configured to the correct value in PMON. +The registers are defined as follows and set to the following values:

    +
    +

    INT_trans_en = 0 //Use CSR register for enable control, CSR[0x420][48] and this register can both enable extended interrupt mode, in PMON the default does not enable this mode, by the kernel configuration CSR[0x420][48] to turn on

    +
    +
    +

    INT_trans_allow = 1 // Allow external interrupt transition function

    +
    +
    +

    INT_trans_addr = 0x1000000001140 // Extended interrupt register address, see 14.3.3.

    +
    +
    +

    INT_trans_cache = 0 //Uncache mode

    +
    +
    +

    Offset: 0x270

    +
    +
    +

    Reset value: 0x00000000

    +
    +
    +

    Name: HT RX INT TRANS Lo

    +
    + + ++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    Table 227. HT RX INT TRANS Lo
    Bit FieldNameLengthReset ValueRead/WriteDescription

    31:4

    INT_trans_addr[31:4]

    28

    0x0

    R/W

    Low order bits of interrupt translation address

    3:0

    Reserved

    4

    0x0

    R

    Reserved

    +
    +

    Offset: 0x274

    +
    +
    +

    Reset value: 0x00000000

    +
    +
    +

    Name: HT RX INT TRANS Hi

    +
    + + ++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    Table 228. HT RX INT TRANS Hi
    Bit FieldNameLengthReset ValueRead/WriteDescription

    31

    INT_trans_en

    1

    0x0

    R/W

    Interrupt transition enable

    30

    INT_trans_allow

    1

    0x0

    R/W

    Whether to allow interrupt transition

    29:26

    INT_trans_cache

    4

    0x0

    R/W

    Interrupt Transition Cache Field

    25:0

    INT_trans_addr[58:32]

    26

    0x0

    R/W

    High order bits of interrupt translation address

    +
    3. +
  3. +

    The kernel first identifies the extended interrupt mode support by CSR[0x8][3], and then enables the extended interrupt mode by register CSR[0x420][48].

    +
    +

    The base address is 0x1fe00000, It can also be accessed using the configuration register instruction (IOCSR), and the offset address is 0x0420.

    +
    + + +++++++ + + + + + + + + + + + + + + + + + + +
    Table 229. Other function configuration register
    Bit FieldNameRead/WriteReset ValueDescription

    48

    EXT_INT_en

    RW

    0x0

    Extended I/O interrupt enable

    +
    4. +
  4. +

    Set the corresponding routing and internal control for the extended interrupt mode.

    +
    5. +
+
+
+
+
+

16.2. Configuration Register Instruction Debug Support

+
+

The configuration register instruction is in principle used without cross-chip access, but in order to meet the need for debugging and other functions, cross-chip access is supported here using multiple register addresses. +It is worth noting that such registers can only be written, not read.

+
+
+

Together with the existing inter-processor interrupts and other registers that can be accessed across slices, all such registers and their addresses are listed below.

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 230. Processor core inter-processor communication registers
NameOffset AddressRead/WriteDescription

IPI_Send

0x1040

WO

32-bit interrupt distribution register

+

[31]: wait for completion flag; when set to 1 it will wait for the interrupt to take effect

+

[30:26]: reserved

+

[25:16]: processor core number

+

[15:5]: reserved

+

[4:0]: interrupt vector number, corresponding to the vector in IPI_Status

Mail_Send

0x1048

WO

64-bit MailBox Cache register

+

[63:32]: MailBox data

+

[31]: wait for completion flag; when set to 1 it will wait for the write to take effect

+

[30:27]: write data mask; each bit indicates that the bytes corresponding to the 32-bit write data will not really be written to the target address, such as 1000b means write the 0-2 bytes, 0000b means write all 0-3 bytes

+

[26]: reserved

+

[25:16]: processor core number

+

[15:5]: reserved

+

[4:2]: MailBox number

+

0 - MailBox0 low 32-bit

+

1 - MailBox0 high 32-bit

+

2 - MailBox1 low 32-bit

+

3 - MailBox1 high 32-bit

+

4 - MailBox2 low 32-bit

+

5 - MailBox2 high 32-bit

+

6 - MailBox3 low 32-bit

+

7 - MailBox4 high 32-bit

+

[1:0]: reserved

FREQ_Send

0x1058

WO

32-bit frequency enable register

+

[31]: wait for completion flag; when set to 1 it will wait for the setting to take effect

+

[30:27]: write data mask; each bit indicates that the bytes corresponding to the 32-bit write data will not really be written to the target address, such as 1000b means write the 0-2 bytes, 0000b means write all 0-3 bytes

+

[26]: reserved

+

[25:16]: processor core number

+

[15:5]: reserved

+

[4:0]: write to the corresponding processor core private frequency configuration register

+

CSR[0x1050]

ANY_Send

0x1158

WO

64-bit register access register

+

[63:32]: write data

+

[31]: wait for completion flag; when set to 1 it will wait for the interrupt to take effect

+

[30:27]: write data mask; each bit indicates that the bytes corresponding to the 32-bit write data will not really be written to the target address, such as 1000b means write the 0-2 bytes, 0000b means write all 0-3 bytes

+

[26]: reserved

+

[25:16]: destination processor core number

+

[15:0]: offset address of the register to be written

+
+
+
+
+ + +
+ + Creative Commons License + +
+ This work is licensed under a + Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License. +
+ + + + + + + + + \ No newline at end of file diff --git a/Loongson-3A5000-usermanual-EN.pdf b/Loongson-3A5000-usermanual-EN.pdf new file mode 100644 index 0000000..c2edab9 Binary files /dev/null and b/Loongson-3A5000-usermanual-EN.pdf differ diff --git a/Loongson-7A1000-usermanual-EN.html b/Loongson-7A1000-usermanual-EN.html new file mode 100644 index 0000000..f80aee7 --- /dev/null +++ b/Loongson-7A1000-usermanual-EN.html @@ -0,0 +1,24056 @@ + + + + + + + + +Loongson 7A1000 Bridge User Manual + + + + +
+
+

List of Figures

+
+
+ +
+
+
+
+

List of Tables

+
+
+ +
+
+
+
+

About this manual

+
+
+

Copyright Statement

+
+

The copyright of this document belongs to Loongson Technology Corporation Limited. +Without written permission, no company or individualmay disclose, reproduce or otherwise distribute any part of this document to third parties. +Otherwise, they will be held legally responsible.

+
+
+
+

Disclaimer

+
+

This document provides only periodic information, and the contents contained may be updated at any time without notice, depending on the actual situation of the product. +Loongson Technology Corporation Limited is not responsible for any direct or indirect damage aused by the improper use of the document.

+
+
+
+

Loongson Technology Corporation Limited

+
+

Building No.2, Loongson Industrial Park,
+Zhongguancun Environmental Protection Park, Haidian District, Beijing

+
+
+

Tel: 010-62546668

+
+
+

Fax: 010-62600826

+
+
+
+

Reading Guide

+
+

This manual describes the overall bridge architecture, clock structure, address space, configuration registers, and individual functional interfaces, primarily for BIOS and kernel developers.

+
+
+
+

Translator’s Note

+
+

These documents were translated by Yanteng Si and Feiyang Chen.

+
+
+

This is the translation of https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-7A1000-usermanual-v2.00-CN.pdf.

+
+
+

Due to the limited knowledge of the translators, there are some inevitable errors and omissions existing in this document, please feel free to correct.

+
+
+
+

License

+
+

This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License. +To view a copy of this license, visit http://creativecommons.org/licenses/by-nc-nd/4.0/ or send a letter to Creative Commons, PO Box 1866, Mountain View, CA 94042, USA.

+
+
+
+

Contributors

+
+

Since the release of the project, we have gotten several errata and content changes donated. +Here are all the people who have contributed to LoongArch Documentation as an open source project. +Thank you everyone for helping make this a better book for everyone.

+
+
+

The contributors are listed in alphabetical order.

+
+
+
+
Chao LI <lichao@loongson.cn>
+Chenghua Xu <xuchenghua@loongson.cn>
+Dandan Zhang <zhangdandan@loongson.cn>
+Feiyang Chen <chenfeiyang@loongson.cn>
+FreeFlyingSheep <fyang.168.hi@163.com>
+Konstantin Romanov <konstantinsromanov@gmail.com>
+LI Chao <lichao@loongson.cn>
+limeidan <limeidan@loongson.cn>
+liuzhensong <liuzhensong@loongson.cn>
+mengqinggang <mengqinggang@loongson.cn>
+Qi Hu <huqi@loongson.cn>
+qmuntal <quimmuntal@gmail.com>
+tangxiaolin <tangxiaolin@loongson.cn>
+WANG Xuerui <git@xen0n.name>
+wangguofeng <wangguofeng@loongson.cn>
+Wu Xiaotian <wuxiaotian@loongson.cn>
+Wu Xiaotian <yetist@gmail.com>
+Xi Ruoyao <xry111@mengyan1223.wang>
+Yang Yujie <yangyujie@alumni.sjtu.edu.cn>
+Yang Yujie <yangyujie@loongson.cn>
+Yanteng <siyanteng@loongson.cn>
+Yanteng Si <siyanteng@loongson.cn>
+
+
+
+
+
+
+

1. Introduction

+
+
+

1.1. Introduction to this Manual

+
+

1.1.1. Contents of the Chapters

+
+

Section 1 is an introduction that provides an overview of the features and functions of this bridge chip.

+
+
+

Section 2 introduces the bridge chip clock structure, describes the clock of the bridge chip, and details the clock-related hardware configuration and software usage.

+
+
+

Section 3 introduces the address space of the bridge chip, describing the entire address space of the processor (Loongson 3 processor) + bridge chip and the address space distribution inside the bridge chip.

+
+
+

Section 4 introduces the bridge chip configuration registers.

+
+
+

Section 5 introduces interrupts.

+
+
+

Section 6 describes the HPET controller.

+
+
+

Section 7 introduces the HT controller.

+
+
+

Sections 8-14 describe the low-speed interface and other internal functions of the bridge chip. These include: address space description, UART serial controller, I2C controller, PWM controller, and other internal functions. I2C controller, PWM controller, ACPI power management module, real-time clock RTC, and GPIO interface.

+
+
+

Section 15 describes the GMAC controller.

+
+
+

Section 16 describes the USB controller, including the EHCI controller and the OHCI controller.

+
+
+

Section 17 describes the Graphics Processing Unit GPU.

+
+
+

Section 18 describes the display controller DC.

+
+
+

Section 19 describes the HDA controller.

+
+
+

Section 20 describes the AC97 controller.

+
+
+

Section 21 describes the SATA controller.

+
+
+

Section 22 describes the PCIE controller.

+
+
+

Section 23 introduces the SPI controller.

+
+
+

Section 24 introduces the LPC controller.

+
+
+

Appendix 1 explains the chip pin multiplexing relationship.

+
+
+

Appendix 2 gives the software usage notes.

+
+
+
+

1.1.2. Conventions of this Manual

+
+

Note: The bit field of Reserved in the register description in the text is either a read-only attribute or a read-write attribute. Regardless of the attribute of the bit field, the software must ensure that the value of the bit field is not changed, that is, if the software needs to modify a register containing a Reserved bit field, it must ensure that the value written to the Reserved bit field is the same as the value read from the bit field.

+
+
+

For ease of presentation, the following abbreviations are used to denote the register attributes.

+
+
+

RO Read-only

+
+
+

WO Write-only

+
+
+

R/W Read-Write

+
+
+

R/WC read-write, write clear

+
+
+
+
+

1.2. Overview of the Bridge

+
+

The Loongson 7A1000 bridge chip (hereafter referred to as the bridge chip) is Loongson’s first dedicated chipset product, providing north-south bridge functionality for Loongson processors. The bridge chip is connected to the Loongson Series 3 processor via the HT high-speed bus interface and has an integrated GPU, DisplayController, DDR3 SDRAM memory controller, and PCIE, SATA, USB, GMAC, I2C, UART, GPIO, and other interfaces.

+
+
+

Main Characteristics of the Bridge Piece

+
+
+
    +
  • +

    16-bit HT 3.0 interface

    +
    • +
  • +

    Support dual-way bridge chip mode

    +
    • +
  • +

    2D/3D GPU

    +
    • +
  • +

    Display controller, supports dual DVO display

    +
    • +
  • +

    16-bit DDR3 graphics memory controller

    +
    • +
  • +

    3 x8 PCIE 2.0 interfaces, each x8 interface can be split into 2 independent x4 interfaces

    +
    • +
  • +

    2 x4 PCIE 2.0 interfaces that can be split into 6 independent x1 interfaces

    +
    • +
  • +

    3 SATA 2.0 ports

    +
    • +
  • +

    6 USB 2.0 ports

    +
    • +
  • +

    2 RGMII Gigabit LAN interfaces

    +
    • +
  • +

    HDA/AC97 configurable interface

    +
    • +
  • +

    RTC support

    +
    • +
  • +

    HPET support

    +
    • +
  • +

    UART interface

    +
    • +
  • +

    I2C interface

    +
    • +
  • +

    LPC interface

    +
    • +
  • +

    SPI interface

    +
    • +
  • +

    GPIO interface

    +
    • +
  • +

    Support ACPI specification

    +
    • +
  • +

    Support JTAG bound scan

    +
    • +
+
+
+
+

1.3. Main Functions of the Bridge

+
+

HT Interface

+
+
+

The bridge is connected to the processor via the HT interface, which is compatible with HT3.0 protocol and supports 200/400/800/1600Mhz interface frequency and 8/16-bit interface width. In addition to being used as a single bridge chip, it can also be configured as a dual bridge chip mode to support direct data transfer with both processors.

+
+
+

Graphics Processing

+
+
+

The GPU supports OpenGL ES 2.0 and OpenGL ES 1.1; OpenVG, Futuremark certified, BitBLT and Stretch BLT, rectangle fill, hardware line drawing, color font rendering, YUV color space conversion, and high quality scaling. Space conversion, high quality scaling, etc. The display controller supports dual DVO signal output and hardware cursor, gamma correction, output dithering, etc. The memory interface uses 16-bit DDR3 SDRAM interface with a maximum data rate of 1333 Mbps.

+
+
+

PCIE Interface

+
+
+

The PCIE 2.0 protocol-compliant interface contains a total of 32 data links supporting up to 5G b/s in each data direction (10G b/s in both directions) and a total of 12 PCIE controllers. 32 data links can be divided into 3 x8 interfaces and 2 x4 interfaces; each x8 interface can be configured as 2 x4 interfaces. Each x8 interface can be configured as two x4 interfaces independently; of the two x4 interfaces, one can be configured as four x1 interfaces independently, and the other as two x1 interfaces independently.

+
+
+

SATA Controllers

+
+
+

Integrated 3 SATA host controllers, each controlling 1 SATA interface, each supporting up to 3 Gb/s data rate and compatible with SATA 2.6 protocol. SATA controllers are compatible with AHCI 1.1 specification.

+
+
+

USB Controllers

+
+
+

Two USB controllers control six independent USB host interfaces, supporting up to USB 2.0 protocol with maximum transfer speeds of up to +The two USB controllers control six independent USB host interfaces, supporting up to USB 2.0 protocol and transfer speeds up to 480 Mbps, and are compatible with USB 1.1 full-speed and low-speed transfers.

+
+
+

GMAC Controller

+
+
+

Integrated two 10/100/1000Mbps adaptive Ethernet MAC controllers, compatible with IEEE 802.3, connect external GMAC PHY chip through RGMII interface, half-duplex/full-duplex adaptive, support Timestamp function, support network wake-up.

+
+
+

HDA Controller

+
+
+

Supports 16, 18 and 20-bit sampling accuracy, variable rate, sampling rate up to 192KHz, 7.1 channel surround sound output, and three audio inputs.

+
+
+

SPI Controller

+
+
+

Integrated SPI host controller, supports standard read, sequential address read, fast read, dual I/O and other read modes.

+
+
+

UART

+
+
+

Integrated 1 full-featured UART controller, full-duplex asynchronous data receive/transmit, 16-bit programmable clock counter, support receive timeout detection, configurable as 4 two-wire serial ports (TXD/RXD).

+
+
+

I2C Bus

+
+
+

Compatible with I2C standard, operates in master device mode, supports 7-bit addressing and 10-bit addressing modes.

+
+
+

PWM

+
+
+

Four PWM outputs with internal 32-bit counter, supporting pulse generation and detection.

+
+
+

HPET

+
+
+

Compatible with HPET specification, supports 64-bit counter timestamp function, 32-bit timer, 1 periodic interrupt and Supports 1 periodic interrupt and 2 non-periodic interrupts.

+
+
+

RTC

+
+
+

Timing accurate to 0.1 second, can generate 3 timing interrupts, supports timed power-on function.

+
+
+

Interrupt Controller

+
+
+

Internal integrated interrupt controller supports up to 64 interrupt sources, dual interrupt outputs, software set interrupts, configurable trigger mode, and intelligent interrupt distribution.

+
+
+

ACPI Power Management

+
+
+

Supports clock gating, PHY shutdown, USB/GMAC wake-up, and auto-start for incoming calls.

+
+
+

GPIO

+
+
+

1 dedicated GPIO pin, 56 multiplexed GPIO pins, support input interrupt function.

+
+
+
+

1.4. Structure of the Bridge

+
+
+structure of the bridge +
+
Figure 1. Structure of the Bridge
+
+
+
+
+
+

2. Bridge and System Clock

+
+
+

2.1. Bridge Clock

+
+

The bridge requires a 100Mhz clock and a 32.768 K crystal as reference clock input (and a 33Mhz clock input if using the LPC bus)

+
+ + +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 1. Bridge clock
ClockFrequencyDescription

RTC_XO

32.768KHz

32.768KHz Crystal Output

TESTCLK

-

Reserved

LPC_CLKIN

33Mhz

LPC 33Mhz reference clock, unconnected when not using LPC interface

HTCLKp/n

200Mhz

HT 200Mhz differential reference clock, unconnected

PCIE_F0_CLKINp/n

100Mhz

PCIE_F0 100Mhz differential reference clock, unconnected

PCIE_F1_CLKINp/n

100Mhz

PCIE_F1 100Mhz differential reference clock, unconnected

PCIE_H_CLKINp/n

100Mhz

PCIE_H 100Mhz differential reference clock, unconnected

PCIE_G0_CLKINp/n

100Mhz

PCIE_G0 100Mhz differential reference clock, can be left unconnected

PCIE_G1_CLKINp/n

100Mhz

PCIE_G1 100Mhz differential reference clock, unconnectable

SATA0_CLKINp/n

100Mhz

SATA0 100Mhz differential reference clock, do not connect

SATA1_CLKINp/n

100Mhz

SATA1 100Mhz differential reference clock, do not connect

SATA2_CLKINp/n

100Mhz

SATA2 100Mhz differential reference clock, do not connect

USB_XI

12Mhz

Reserved

USB_CLKIN

12Mhz

12Mhz crystal input

+
+

Note: Input clocks not provided need to be grounded through a 10Kohm resistor.

+
+ + +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 2. Birge clock output
ClockFrequencyDescription

CLKOUT33M

33.3MHz

33.3Mhz single-ended clock output. Can be used as a memory reference clock for the Loongson 3 processor.

CLKOUT100M

100Mhz

100Mhz single-ended clock output. Can be used as a reference clock for the HT for the Loongson 3 processor.

CLKOUT25M1

25Mhz

25Mhz single-ended clock output. Can be used as a core reference clock for the Loongson 3 processor.

CLKOUTFLEX1

Variable

Variable frequency single-ended clock output. Default is 100Mhz.

+
+

Note: 1. The CLKO`UT25M and CLKOUTFLEX pins can be multiplexed as GPIO functions.

+
+
+
+ +
+

The bridge chip sets a number of pins to set the bridge clock generation method, these configuration pins are mainly used as a backup design, the normal motherboard design does not need to change the value of these configuration pins except for CLKSEL[7:6] (dangling or kept as default values). Bridge clock-related configuration pins are shown in the following table:

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+

2.3. Description of Clock Function

+
+

The bridge contains multiple PLLs and clock divider modules to generate the individual clocks needed for the bridge.

+
+
+

The bridge contains 5 PLLs, each of which can provide up to 3 clock outputs. The five PLLs are used for the following purposes

+
+
+
    +
  • +

    A device PLL to generate the clocks for USB/SATA, GMAC.

    +
    • +
  • +

    A graphics PLL to generate clocks for GPU, DC, and graphics memory.

    +
    • +
  • +

    One system PLL to generate clocks for the internal bus, HDA bitclk, flex clkout.

    +
    • +
  • +

    Two PIX PLLs for generating two independent pixel clocks to support dual independent displays.

    +
    • +
+
+
+
+structure of bridge clock +
+
Figure 2. Structure of bridge clock
+
+
+
+

2.4. Description of PLL Function

+
+

The output clock frequency is calculated as follows.

+
+
+
+structure of pll +
+
Figure 3. Structure of PLL
+
+
+

clock_out = refclk / div_ref * loopc / divoutN

+
+
+

The refclk of 7A is fixed at 100MHz, and the output of the input divider (refclk / div_ref) needs to be guaranteed to be in the range of 20 In addition, it is necessary to ensure that the output of the input divider (refclk / div_ref) is in the range of 20 - 40MHz, and the frequency after frequency doubling module (refclk / div_ref * loopc) is in the range of 1.2GHz - 3.2GHz.

+
+
+

The PLL-related configuration signals and their descriptions are shown in the follow table. The locations of these configuration signals are shown in Section 4 Bridge Configuration Registers.

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+

2.5. Configuration Method of PLL

+
+

When SYS_CLKSEL[1:0] is 00b, it means the output frequency of PLL can be changed by software. In this configuration, the default clock frequency at bridge startup is the external reference clock frequency, and software configuration of the bridge clock is required during processor startup. The process of modifying the clock configuration through software is as follows:

+
+
+
    +
  1. +

    set sel_pll_out* to 0.

    +
    2. +
  2. +

    set the pll_pd signal to 1.

    +
    3. +
  3. +

    set set_pll_param to 0.

    +
    4. +
  4. +

    set the value of pll_div_ref/pll_loopc/pll_div_out*.

    +
    5. +
  5. +

    set set_pll_param to 1.

    +
    6. +
  6. +

    set the pll_pd signal to 0.

    +
    7. +
  7. +

    wait for the PLL lock signal pll_locked to change to 1.

    +
    8. +
  8. +

    set sel_pll_out* to 1.

    +
    9. +
+
+
+
+
+
+

3. Address Space

+
+
+

3.1. Overview of Loongson 3 and Loongson 7A Address Space

+
+

As a bridge for the HT interface, the bridge supports a 40-bit address space internally. Without the SWIOTLB, the Loongson3 processor + bridge supports a maximum of 1TB of memory address space. To support multi-processor systems, we use a few bits (up to 4 bits) of the bridge chip’s internal address as the destination node number for the bridge chip’s internal device DMA access. This means that the bridge chip can support a processor system with up to 16 nodes. Considering that in practice Loongson uses systems with up to 4 nodes Therefore, this section describes the maximum number of nodes supported. For a 4-node system, the address space size for a single processor node is 256GB.

+
+
+

From the CPU’s perspective - that is, the device address space accessible to the CPU - the address space of a bridge chip consists of three parts: configuration space, PCI I/O space, and PCI MEM space. The address space of a bridge chip has the same form as the address space defined by PCI.

+
+
+
    +
  1. +

    Configuration space: this address space is used to access the configuration headers of the devices inside the bridge chip (including devices extended through the PCIE bus), and its address composition conforms to the address organization form of PCI configuration access.

    +
    2. +
  2. +

    I/O space: This address space is used to access the I/O address space defined by the PCI protocol. Only PCIE has this address space in the bridge chip for accessing downstream devices of the PCIE controller through I/O type requests.

    +
    3. +
  3. +

    MEM space: All address spaces other than the above two address spaces are MEM spaces.

    +
    4. +
+
+
+

The bridge chip’s configuration space corresponds to the HT bus configuration space of the HT bus, with a size of 32MB. the bridge chip’s PCI I/O space corresponds to the HT bus I/O space, with a size of 32MB. the bridge chip’s PCI MEM space corresponds to the HT bus MEM space, with a size of 1012GB. the PCI MEM space is used to The PCI MEM space is used to access the MEM space of the bridge’s internal PCIE devices, the MEM and IO space of devices other than PCIE devices, and the bridge’s configuration register space.

+
+
+

The latter two address spaces (PCI I/O space and PCI MEM space) are part of the overall processor address space. and the system software can assign them to any location from 0 - 1TB*. When the software accesses them, it needs to map them into HT1’s address space segment via the processor’s level 1 XBAR or directly add HT1’s address space offset to that access address.

+
+
+

Note*: Except for the address segment 0x0f000000-0x0fffffff. This address segment cannot be used as a bridge device address space.

+
+
+

From the perspective of DMA accesses - that is, accesses to the address space initiated by the bridge chip’s internal devices - the address space available includes the processor’s memory space and the bridge chip’s memory space. The size of the processor’s memory space varies depending on the number of nodes in the system, and the total DMA address space is 1 TB. For a 4-node system, the DMA address space must be located within the lower 256 GB of the node address space so that the bridge can directly access the memory of up to 4 nodes. Devices within the bridge chip that can initiate DMA operations include: GPU, DC, PCIE, USB, SATA, GMAC, HDA, and AC97.

+
+
+

Both types of addresses (the bridge’s address space and the processor’s address space) are addressed in a uniform manner, i.e., the processor’s memory space, the processor’s configuration space, the bridge’s configuration access space, the I/O space, and the MEM space, are all located in the same address space and do not overlap with each other. For a single node system, this address space has a maximum size of 1TB.

+
+
+

The access addresses of the devices inside the bridge chip (PCI I/O space and PCI MEM space) are designed to be software configurable to support device discovery and management for the PCI architecture. Each device (device block) inside the bridge contains a PCI configuration header. The software accesses the configuration header to obtain information about the type of the device, the size of the address space supported, etc., and sets the address space of the device by configuring the device’s BAR register. This approach is consistent with the 780E.

+
+
+

The following is an example of a Loongson 3A+ bridge chip system to illustrate the address space allocation for the entire computer system. one way of dividing the address space for the 3A+ bridge chip is shown in the following figure.

+
+
+
+example of address space division for loongson 3 processor loongson 7a bridge +
+
Figure 4. Example of address space division for Loongson 3 processor + Loongson 7A bridge
+
+
+

Note: The address in the figure is the low address, not including the node number and high address.

+
+
+

In the address space allocation method in the figure above, the

+
+
+

0x0000,0000 - 0x0fff,ffff is the low 256MB memory space of the system.

+
+
+

0x1000,0000 - 0x17ff,fff is the fixed device address space of the bridge, which includes interrupt controller, HPET, confbus, MISC low-speed devices, and LPC. ,ffff (HT1’s MEM space)

+
+
+

0x1800,0000 - 0x19ff,ffff is the PCI I/O space of the bridge chip, the software can allocate the I/O space of the PCIE devices in the bridge chip to this address space, which is mapped to 0xefd,fc00,0000 - 0xefd,fdff through the configuration window of the first-level XBAR, ffff (I/O space of HT1).

+
+
+

0x1a00,0000 - 0x1bff,ffff is the configuration space of the bridge chip, which is used to access the configuration header of the internal device of the bridge chip, and the access method is compatible with the PCI protocol, the bit[23:8] of the address bit corresponds to the bus number, device number and func number in order, and this address is mapped to 0xefd, fe00,0000 - 0xefd,fff,fff (HT1’s bus configuration space).

+
+
+

0x1c00,0000 - 0x1dff,ffff is the LPC MEM address space of 3A.

+
+
+

0x1f00,0000 - 0x1fff,ffff is the 3A’s LPC device space.

+
+
+

0x2000,0000 - 0x2fff,ffff is the reserved space for the processor.

+
+
+

0x3000,0000 - 0x3fff,ffff is the configuration space for 3A.

+
+
+

0x4000,0000 - 0x7fff,ffff is the PCI MEM space of the bridge chip. This address is mapped to 0xe00,4000,0000 - 0xe00,7fff,fff (the MEM space of HT1) through the configuration window of level 1 XBAR.

+
+
+

0x8000,0000 - MEM_UP_LIMIT is the high memory address space of 3A.

+
+
+

MEM_UP_LIMIT - 0xfc,ffff,ffff is the PCI MEM space of the bridge. This address is mapped to 0xe00,0000,0000+MEM_UP_LIMIT - 0xefc,ffff,ffff (the MEM space of HT1) through the configuration window of Level 1 XBAR.

+
+
+
+

3.2. PCI Devices and Functions

+
+

Devices with DMA capability inside the bridge and some other devices contain a standard PCI configuration header. The devices that contain PCI configuration headers include: GPU, DC, PCIE, USB, SATA, GMAC, HDA/AC97, LPC, and SPI. the bus number, device number, and function number of each device are listed in the following table

+
+ + ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 5. Configuration header access correspondence for each device
Bus: Device: FunctionFunction Description

Bus 0:Device 0:Function 0

HT lo

Bus 0:Device 1:Function 0

HT hi

Bus 0:Device 3:Function 0

GMAC0

Bus 0:Device 3:Function 1

GMAC1

Bus 0:Device 4:Function 0

USB0 OHCI

Bus 0:Device 4:Function 1

USB0 EHCI

Bus 0:Device 5:Function 0

USB1 OHCI

Bus 0:Device 5:Function 1

USB1 EHCI

Bus 0:Device 6:Function 0

GPU

Bus 0:Device 6:Function 1

DC

Bus 0:Device 7:Function 0

HDA1

Bus 0:Device 7:Function 1

AC971

Bus 0:Device 8:Function 0

SATA0

Bus 0:Device 8:Function 1

SATA1

Bus 0:Device 8:Function 2

SATA2

Bus 0:Device 9:Function 0

PCIE_F0 Port02

Bus 0:Device 10:Function 0

PCIE_F0 Port12

Bus 0:Device 11:Function 0

PCIE_F0 Port22

Bus 0:Device 12:Function 0

PCIE_F0 Port32

Bus 0:Device 13:Function 0

PCIE_F1 Port03

Bus 0:Device 14:Function 0

PCIE_F1 Port13

Bus 0:Device 15:Function 0

PCIE_G0 port04

Bus 0:Device 16:Function 0

PCIE_G0 port14

Bus 0:Device 17:Function 0

PCIE_G1 port05

Bus 0:Device 18:Function 0

PCIE_G1 port15

Bus 0:Device 19:Function 0

PCIE_H port06

Bus 0:Device 20:Function 0

PCIE_H port16

Bus 0:Device 22:Function 0

SPI

Bus 0:Device 23:Function 0

LPC7

+
+

Notes.

+
+
+
    +
  1. +

    when hda_sel is 1, HDA controller can be discovered; when hda_sel is 0, AC97 controller can be discovered.

    +
    2. +
  2. +

    When PCIE_F0 works in x4 mode, only Port 0 is visible, Port 1-3 is not visible; when PCIE_F0 works in non-x4 mode, Port 0-3 is visible. When PCIE_F0 works in non-x4 mode, Port 0-3 is visible. 3.

    +
    3. +
  3. +

    When PCIE_F1 is operating in x4 mode, only Port 0 is visible and Port 1 is not visible; when PCIE_F1 is operating in non-x4 mode, Port 0-1 is visible. When PCIE_F1 is operating in non-x4 mode, Port 0-1 is visible. 4.

    +
    4. +
  4. +

    When PCIE_G0 is operating in x8 mode, only Port 0 is visible and Port 1 is not visible; when PCIE_G0 is operating in x4 mode, Port 0-1 is visible. mode, Port 0-1 is visible. 5.

    +
    5. +
  5. +

    When PCIE_G1 is operating in x8 mode, only Port 0 is visible and Port 1 is not visible; when PCIE_G1 is operating in x4 mode, Port 0-1 is visible. When PCIE_G1 is operating in x4 mode, Port 0-1 is visible. 6.

    +
    6. +
  6. +

    When PCIE_H is operating in x8 mode, only Port 0 is visible and Port 1 is not visible; when PCIE_H is operating in x4 mode, Port 0-1 is visible.

    +
    7. +
  7. +

    LPC(D23:F0) is only visible when LPC module is enabled.

    +
    8. +
+
+
+

When the bus number, device number, function number and address offset accessed by the configuration header are invalid, the write operation is invalid; the data obtained by the read operation is 0xFFFFFFFF.

+
+
+
+

3.3. Access Address of the PCI Configuration

+
+

The processor can access the configuration space of the bridge chip through two address spaces. One is the standard configuration access space defined by HT (0xFD_FE00_0000 - 0xFD_FFFF_FFFF) and the other is the reserved address space of HT (0xFE_0000_0000 - 0xFE_1FFF_FFFF). The configuration space size for each bridge device accessed through the HT standard configuration access space is 256 bytes; the configuration space size for each bridge device accessed through the reserved address space is 4K bytes.

+
+
+

The maximum configuration space size per device is 256 bytes when using the HT-defined standard configuration access space (0xFD_FE00_0000-0xFD_FFFF_FFFF) to access the bridge slice. The address [39:24] determines the configuration header type (0xFDFE is Type0, 0xFDFF is Type1); [23:16] indicates the Bus Number; [15:11] indicates the Device Number; [10:8] indicates the Function Number; [7:0] indicates the offset. The following diagram shows the meaning of the address segment for the CPU to access the PCI configuration space using the HT standard configuration access space

+
+
+
+standard access address of the pci configuration +
+
Figure 5. Standard access address of the PCI configuration
+
+
+

When using the HT’s reserved address space (0xFE_0000_0000 - 0xFE_1FFF_FFFF) to access bridge slices, the maximum configuration space size per device is 4K bytes. The address [39:28] determines the configuration header type (0xFE0 is Type0, 0xFE1 is Type1); [23:16] indicates the Bus Number; [15:11] indicates the Device Number; [10:8] indicates the Function Number; [27:24] and [7:0] are combined to represent the offset. The following diagram illustrates the meaning of the address segment for the CPU to access the PCI configuration space using the HT reserved address space.

+
+
+
+reserved access address of the pci configuration +
+
Figure 6. reserved access address of the PCI configuration
+
+
+

In general, it is recommended to use the HT standard configuration access space (0xFD_FE00_0000-0xFD_FFFF_FFFF) for PCI configuration header access.

+
+
+
+

3.4. Example of Bridge Device Address Space Allocation

+
+

Access to the bridge chip devices is mainly done through the PCI MEM space. The software can assign any access address for each device on the bridge chip within this address segment. The internal PCI devices of the bridge chip include: GPU/DC, GMEM, PCIE, USB, SATA, GMAC, HDA/AC97, LPC, SPI, all of which can be seen through lspci. The access addresses of these devices (except LPC) can be dynamically assigned by software. One way of allocation is as follows: by scanning the PCI bus and reading the configuration space of each device (PCI mode orientation) to get the size of MEM space and I/O space used by each device, the system software allocates the appropriate size of MEM space from the address 0x40000,0000-0x7fff,fff, and from 0x1800, 0000-0x19ff,ffff. The system software allocates the appropriate size of I/O space (PCIE devices) from 0x40000,0000-0x7fff,ffff.

+
+
+

In addition to these PCI type devices, the bridge also contains some devices that are accessed using fixed addresses, such as: interrupt controllers, HPET controllers, confbus In addition to these PCI-type devices, the bridge also contains devices that are accessed using fixed addresses, such as: interrupt controllers, HPET controllers, confbus configuration registers, MISC low-speed device blocks, and LPCs.

+
+
+

The following two tables give an example of an address allocation for a bridge chip fixed address device and a PCI device, along with their address space size and supported access types. For the access types, B indicates byte access (1byte), H indicates half-word access (2byte), W indicates word access (4byte), D indicates double-word access (8byte), Q indicates 4-word access (16byte), and C indicates cacheline access.

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 6. Bridge piece fixed address device address space
ModuleAddress spaceAddress space sizeAccess type

INT

0x1000,0000-0x1000,0fff

4K

BHW

HPET

0x1000,1000-0x1000,1fff

4K

BW

CONF REG

0x1001,0000-0x1001,ffff

64K

BHW

MISC

0x1008,0000-0x100f,ffff

512K

BW

LPC REG

0x1000,2000-0x1000,2fff

4K

W

LPC MEM

0x1200,0000-0x13ff,ffff

32M

BHWDQC

LPC I/O

0x1800,0000-0x1800,ffff

64K

B

LPC TPM

0x1801,0000-0x1801,ffff

64K

B

+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 7. Bridge chip PCI device address space allocation example
ModuleAddress spaceAddress space sizeAccess type

GPU

0x5ff4,0000-0x5ff7,ffff

256K

W

DC

0x5ff8,0000-0x5ff8,ffff

64K

W

Graphic Memory

0x4000,0000-0x4fff,ffff

256M

BHWDQC

PCIE I/O

0x1802,0000-0x19ff,ffff

32M

BHW

PCIE MEM

0x6000,0000-0x7fff,ffff

512M

BHW

SPI MEM

0x5e00,0000-0x5eff,ffff

16M

BHWDQC

USB0-EHCI

0x5fd0,0000-0x5fd0,7fff

32K

W

USB0-OHCI

0x5fd0,8000-0x5fd0,ffff

32K

W

USB1-EHCI

0x5fd1,0000-0x5fd1,7fff

32K

W

USB1-OHCI

0x5fd1,8000-0x5fd1,ffff

32K

W

SATA0

0x5fe0,0000-0x5fe0,1fff

8K

W

SATA1

0x5fe0,2000-0x5fe0,3fff

8K

W

SATA2

0x5fe0,4000-0x5fe0,5fff

8K

W

GMAC0

0x5fe1,0000-0x5fe1,7fff

32K

W

GMAC1

0x5fe1,8000-0x5fe1,ffff

32K

W

HDA

0x5fe2,0000-0x5fe2,ffff

64K

BHW

AC97

0x5fe3,0000-0x5fe3,ffff

64K

W

SPI REG

0x5ff1,1000-0x5ff1,1fff

4K

B

+
+

The size of the address space of the above devices is fixed, except for PCIE MEM and Graphic Memory, which can be changed by software.

+
+
+

The BIOS needs to modify the MASK value of the BAR register 2/3 of the GPU configuration header by accessing the bridge configuration register GMEM_BAR_MASK to configure the size of Graphic Memory. Graphic Memory size, and then the software will get the graphic memory size through PCI The software then scans through the PCI to obtain the size of the graphics memory.

+
+
+

In the case of using a PCIE external discrete graphics card, the discrete graphics memory space that comes with the discrete graphics card is located in the PCIE MEM address space and is managed as a PCIE device.

+
+
+
+
+
+

4. Bridge Configuration Register

+
+
+

The bridge chip sets up registers to configure certain features of the bridge chip that are not specific to a particular interface (PCIE, USB, etc.). These registers are arranged uniformly in the bridge’s configuration register space (not the PCI configuration access space). The address space size of the bridge configuration registers is 64KB, and the starting address (internal space of the bridge) is configured by the BIOS.

+
+
+

The bridge chip configuration registers contain the following.

+
+
+
    +
  1. +

    Bridge chip general configuration (0x0 - 0x47f).

    +
    2. +
  2. +

    PLL configuration (0x480 - 0x4cf).

    +
    3. +
  3. +

    PCIE controller and PHY configuration (0x580 - 0x617).

    +
    4. +
  4. +

    SATA controller and PHY configuration (0x740 - 0x76f).

    +
    5. +
  5. +

    Memory capacity configuration registers (0x3838 - 0x383f).

    +
    6. +
  6. +

    Bridge ID (0x3ff8 - 0x3fff).

    +
    7. +
+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 8. Bridge configuration register list
Address OffsetNameRead/WriteDescription

0x0418

HT_ROUTE

R/W

HT Routing Configuration

0x0420

FUNC_CONFIG0

R/W

General Configuration Register 0

0x0430

FUNC_CONFIG1

R/W

General Configuration Register 1

0x0440

PAD_CONFIG

R/W

PAD Multiplexing Configuration

0x0480

PLL_0

R/W

PLL0 Configuration

0x0490

PLL_1

R/W

PLL1 Configuration

0x04a0

PLL_2

R/W

PLL2 Configuration

0x04b0

PLL_PIX_0

R/W

PLL_PIX0 Configuration

0x04c0

PLL_PIX_1

R/W

PLL_PIX1 Configuration

0x04d0

FREQSCALE

R/W

Device Frequency Division Configuration

0x0580

PCIE_F0_REG

R/W

PCIE_F0 Configuration Register

0x0590

PCIE_F0_PHY

R/W

PCIE_F0 PHY Configuration Access Register

0x05a0

PCIE_F1_REG

R/W

PCIE_F1 Configuration Register

0x05b0

PCIE_F1_PHY

R/W

PCIE_F1 PHY Configuration Access Register

0x0bc0

PCIE_H_REG

R/W

PCIE_H Configuration Register

0x05d0

PCIE_H_PHY_LO

R/W

PCIE_H PHY Lo Configuration Access Register

0x05d8

PCIE_H_PHY_HI

R/W

PCIE_H PHY Hi Configuration Access Register

0x05e0

PCIE_G0_REG

R/W

PCIE_G0 Configuration Register

0x05f0

PCIE_G0_PHY_LO

R/W

PCIE_G0 PHY Lo Configuration Access Register

0x05f8

PCIE_G0_PHY_HI

R/W

PCIE_G0 PHY Hi Configuration Access Register

0x0600

PCIE_G1_REG

R/W

PCIE_G1 Configuration Register

0x0610

PCIE_G1_PHY_LO

R/W

PCIE_G1 PHY Lo Configuration Access Register

0x0618

PCIE_G1_PHY_HI

R/W

PCIE_G1 PHY Hi Configuration Access Register

0x0740

SATA0_REG

R/W

Configuration of SATA0

0x0748

SATA0_PHY

R/W

PHY configuration access register for SATA0

0x0750

SATA1_REG

R/W

SATA1 configuration

0x0758

SATA1_PHY

R/W

PHY configuration access register for SATA1

0x0760

SATA2_REG

R/W

SATA2 configuration

0x0768

SATA2_PHY

R/W

SATA2 PHY Configuration Access Register

0x3838

GMEM_BAR_MASK

R/W

Memory Capacity Configuration Register

0x3ff8

CHIP_ID

RO

Chip Version Number

+
+

4.1. HT clock enable and DMA routing configuration

+
+

Offset Address: 0418-041Bh

+
+
+

Attribute: R/W

+
+
+

Default value: 3h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 9. Table ht clock enable
Bit FieldNameRead/WriteDescription

31:2

Reserved

R/W

Reserved

1

ht_hi_clken

R/W

HT Controller 1 Clock Enable

+

0: Turn off the clock

+

1: Turn on the clock

0

ht_lo_clken

R/W

HT Controller 0 Clock Enable

+

0: Turn off the clock

+

1: Turn on the clock

+
+

Offset Address: 041C-041Fh

+
+
+

Attribute: R/W

+
+
+

Default value: 000a_a800h

+
+
+

Size: 32 bits

+
+
+

This register is used to configure the routing information for the device’s DMA accesses (i.e., the destination processor for the DMA access and the HT controller through which it passes). +Since the HT bus only supports 40-bit addresses and the processor space (and the DMA access space) supports 64-bit addresses, the addresses need to be transformed before and after passing through the HT bus in order to preserve the address routing information. This feature requires two supports:

+
+
+
    +
  1. +

    the bridge chip stores the node number information in a certain number of bits of the HT bus address;

    +
    2. +
  2. +

    on the processor side, the node information is remapped to the processor’s node bit field using the address translation function of the HT receive window.

    +
    3. +
+
+
+

The LS7A1000 implements the DMA access node number translation function, which allows the node number in the 64-bit address space issued by the device to be automatically mapped to the HT address space by configuring this register.

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 10. DMA routing configuration
Bit FieldNameRead/WriteDescription

31:16

dma_dest_ht

R/W

DMA access destination node routing configuration. There are 16 nodes, each bit corresponds to a node number. bit31-16 correspond to DMA accesses to nodes 15-0 respectively.

+

1: Routed to HT controller 1

+

0: Routed to HT controller 0

15:13

dma_node_id_offset_ma pped

R/W

Address Offset of the mapped DMA access node number in the HT address space (relative to bit32).

+

0: Position of the node number in the HT address space from bit32

+

1: Position of the node number in the HT address space from bit33

+

…​

+

7: The location of the node number in the HT address space starts at bit39

+

This register determines the maximum address range for DMA accesses to a single node. For example, when this register is configured to 0 and bit`[3:0]` is not 0, the maximum address space for DMA accesses within a single node is 2^32=4GB.

12:8

dma_node_id_offset

R/W

The address offset (relative to bit36) where the node number is located in the DMA access.

7:4

Reserved

R/W

Reserved

3:0

dma_node_id_mask

R/W

Node number mask for DMA accesses. This register determines the number of nodes that can be accessed by device DMA access.

+

0 : 1 node

+

1 : 2 nodes

+

3 : 4 nodes

+

7 : 8 nodes

+

15 : 16 nodes

+
+
+

4.2. General Configuration Register 0

+
+

Offset Address: 0420-0423h

+
+
+

Attribute: R/W

+
+
+

Default value: CCCC_3CE0h

+
+
+

Size: 32 bits

+
+
+

This register contains configuration information related to PCIE, graphics processing unit (GPU, display controller, graphics memory).

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 11. Table General Configuration Register 0 1
Bit FieldNameRead/WriteDescription

31

pcie_g1_p1_clken

R/W

Enables the port1 clock for pcie_g1

+

0: Turn off the clock

+

1: Turn on the clock

30

pcie_g1_p0_clken

R/W

Enables the port0 clock for pcie_g1

+

0: Turn off the clock

+

1: Turn on the clock

29

pcie_g1_enable

R/W

Enable pcie_g1 controller

+

0: Access is disabled

+

1: Access is allowed

28

pcie_g1_soft_reset

R/W

Software reset of pcie_g1

+

0:Remove reset

+

1: Hold reset

27

pcie_g0_p1_clken

R/W

Enables the port1 clock for pcie_g0

+

0: Turn off the clock

+

1: Turn on the clock

26

pcie_g0_p0_clken

R/W

Enables the port0 clock for pcie_g0

+

0: Turn off the clock

+

1: Turn on the clock

25

pcie_g0_enable

R/W

Enable pcie_g0 controller

+

0: Access is disabled

+

1: Access is allowed

24

pcie_g0_soft_reset

R/W

Software reset of pcie_g0

+

0:Remove reset

+

1: Hold reset

23

pcie_h_p1_clken

R/W

Enables the port1 clock for pcie_h

+

0: Turn off the clock

+

1: Turn on the clock

22

pcie_h_p0_clken

R/W

Enables the port0 clock for pcie_h

+

0: Turn off the clock

+

1: Turn on the clock

21

pcie_h_enable

R/W

Enable pcie_h controller

+

0: Access is disabled

+

1: Access is allowed

20

pcie_h_soft_reset

R/W

Software reset of pcie_h

+

0:Remove reset

+

1: Hold reset

19

pcie_f1_p1_clken

R/W

Enables the port1 clock for pcie_f1

+

0: Turn off the clock

+

1: Turn on the clock

18

pcie_f1_p0_clken

R/W

Enables the port0 clock for pcie_f1

+

0: Turn off the clock

+

1: Turn on the clock

17

pcie_f1_enable

R/W

Enable pcie_f1 controller

+

0: Access is disabled

+

1: Access is allowed

16

pcie_f1_soft_reset

R/W

Software reset of pcie_f1

+

0:Remove reset

+

1: Hold reset

15:14

Reserved

R/W

Reserved

13

pcie_f0_p3_clken

R/W

Enables the port3 clock for pcie_f0

+

0: Turn off the clock

+

1: Turn on the clock

12

pcie_f0_p2_clken

R/W

Enables the port2 clock for pcie_f0

+

0: Turn off the clock

+

1: Turn on the clock

11

pcie_f0_p1_clken

R/W

Enables the port1 clock for pcie_f0

+

0: Turn off the clock

+

1: Turn on the clock

10

pcie_f0_p0_clken

R/W

Enables the port0 clock for pcie_f0

+

0: Turn off the clock

+

1: Turn on the clock

9

pcie_f0_enable

R/W

Enable pcie_f0 controller

+

0: Access is disabled

+

1: Access is allowed

8

pcie_f0_soft_reset

R/W

Software reset of pcie_f0

+

0:Remove reset

+

1: Hold reset

7

dc_clken

R/W

Enables clocking of dc

+

0: Turn off the clock

+

1: Turn on the clock

6

gpu_clken

R/W

Enable the clock of the gpu

+

0: Turn off the clock

+

1: Turn on the clock

5

gmem_clken

R/W

Enables the clock for gmem

+

0: Turn off the clock

+

1: Turn on the clock

4:3

Reserved

R/W

Reserved

2

pcie_clksel

R/W

Clock selection for pcie.

+

0: Selects the PAD input clock

+

1: Select the internal reference clock

+

If fix_pcie_clksel is 1, then the signal is constant to 1.

1

Reserved

R/W

Reserved

0

default_route_cfg0

R/W

Read/Writeing PCIE, graphics devices using fixed addresses. 0: Configuring device addresses using the PCI configuration header

+

1: Use fixed address to access the device

+

If fix_default_route is 1, then the signal is constant to 1.

+
+

Offset Address: 0424-0427h

+
+
+

Attribute: R/W, RO

+
+
+

Default value: 0000_0000h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 12. DMA routing configuration
Bit FieldNameRead/WriteDescription

31:25

Reserved

R/W

Reserved

24

disable_gmem_confspace

R/W

Disable access to the GMEM configuration space

+

0: Access allowed

+

1: Access is prohibited

23:20

Reserved

R/W

Reserved

19

pcie_g1_p1_clk_ok

RO

pcie_g1 port 1 clock ready

+

0: No clock

+

1: clock normal

18

pcie_g1_p0_clk_ok

RO

pcie_g1 port 0 clock ready

+

0: No clock

+

1: clock normal

17

pcie_g0_p1_clk_ok

RO

pcie_g0 port 1 clock ready

+

0: No clock

+

1: clock normal

16

pcie_g0_p0_clk_ok

RO

pcie_g0 port 0 clock ready

+

0: No clock

+

1: clock normal

15

pcie_h_p1_clk_ok

RO

pcie_h port 1 clock ready

+

0: No clock

+

1: clock normal

14

pcie_h_p0_clk_ok

RO

pcie_h port 0 clock ready

+

0: No clock

+

1: clock normal

13

pcie_f1_p1_clk_ok

RO

pcie_f1 port 1 clock ready

+

0: No clock

+

1: clock normal

12

pcie_f1_p0_clk_ok

RO

pcie_f1 port 0 clock ready

+

0: No clock

+

1: clock normal

11

pcie_f0_p0_clk_ok

RO

pcie_f0 port 3 clock ready

+

0: No clock

+

1: clock normal

10

pcie_f0_p0_clk_ok

RO

pcie_f0 port 2 clock ready

+

0: No clock

+

1: clock normal

9

pcie_f0_p0_clk_ok

RO

pcie_f0 port 1 clock ready

+

0: No clock

+

1: clock normal

8

pcie_f0_p0_clk_ok

RO

pcie_f0 port 0 clock ready

+

0: No clock

+

1: clock normal

5

pcie_g1_uca_en

R/W

pcie_g1 uncache access acceleration enable

+

0: Turn off access acceleration

+

1: Turn on access acceleration

4

pcie_g0_uca_en

R/W

pcie_g0 uncache access acceleration enable

+

0: Turn off access acceleration

+

1: Turn on access acceleration

3

pcie_h_uca_en

R/W

pcie_h uncache access acceleration enable

+

0: Turn off access acceleration

+

1: Turn on access acceleration

2

pcie_f1_uca_en

R/W

pcie_f1 uncache access acceleration enable

+

0: Turn off access acceleration

+

1: Turn on access acceleration

1

pcie_f0_uca_en

R/W

pcie_f0 uncache access acceleration enable

+

0: Turn off access acceleration

+

1: Turn on access acceleration

0

graphic_uca_en

R/W

GPU/DC uncache access acceleration can be

+

0: Turn off access acceleration

+

1: Turn on access acceleration

+
+
+

4.3. General Configuration Register 1

+
+

Offset Address: 0430-0433h

+
+
+

Attribute: R/W

+
+
+

Default value: 00F9_BBF2h

+
+
+

Size: 32 bits

+
+
+

This register contains configuration information related to USB, SATA, GMAC, HDA/AC97, LPC, and SPI.

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 13. Table general configuration register 0 2
Bit FieldNameRead/WriteDescription

31

lpc_uca_en

R/W

LPC uncache acceleration enable

+

0: turn off access acceleration

+

1: Turn on access acceleration

30

spi_uca_en

R/W

SPI uncache acceleration enable

+

0: Turn off access acceleration

+

`1: Access acceleration on

29

conf_uca_en

R/W

Configuration register uncache acceleration enable

+

0: Turn off access acceleration

+

1: turn on access acceleration

28

misc_uca_en

R/W

Low-speed misc device uncache acceleration enable

+

0: turn off access acceleration

+

1: turn on access acceleration

27

aud_uca_en

R/W

HDA/AC97 uncache acceleration enable

+

0: Turn off access acceleration

+

1: Turn on access acceleration

26

gmac_uca_en

R/W

gmac uncache acceleration enable

+

0: Turn off access acceleration

+

1: Turn on access acceleration

25

sata_uca_en

R/W

sata uncache acceleration enable

+

0: turn off access acceleration

+

1: Turn on access acceleration

24

usb_uca_en

R/W

usb uncache acceleration enable

+

0: turn off access acceleration

+

1: Turn on access acceleration

23:16

Reserved

R/W

Reserved

15

usb1_clken

R/W

usb1 clock enable

+

0: No clock

+

1: clock normal

14

usb1_en

R/W

usb_1 access enable

+

0: Access disabled

+

1: Access allowed

13

usb1_phy_soft_reset

R/W

usb1 PHY software reset

+

0:Remove reset

+

1: Hold reset

12

usb1_cntl_soft_reset

R/W

usb1 controller software reset

+

0:Remove reset

+

1: Hold reset

11

usb0_clken

R/W

usb0 clock enable

+

0: No clock

+

1: clock normal

10

usb0_en

R/W

usb0 access enable

+

0: Access disabled

+

1:Access allowed

9

usb0_phy_soft_reset

R/W

usb0 PHY software reset

+

0:Remove reset

+

1: Hold reset

8

usb0_cntl_soft_reset

R/W

usb0 controller software reset

+

0:Remove reset

+

1: Hold reset

7

gmac1_clken

R/W

gmac1 clock enable

+

0: No clock

+

1: clock normal

6

gmac1_sdb_flowctrl

R/W

gmac1 flow control enable

+

0: Flow control off

+

1: Flow control on

5

gmac0_clken

R/W

gmac0 clock enable

+

0: No clock

+

1: clock normal

4

gmac0_sdb_flowctrl

R/W

gmac0 flow control enable

+

0: Flow control off

+

1: Flow control on

3:2

usb_ref_clk_sel

R/W

USB PHY Reference Clock Selection

+

00b: Use external 12MHz crystal

+

10b: Use internal reference clock

1

usb_ehci_dma64_en

R/W

Enables usb EHCI 64-bit DMA address mode

+

0: Use 32-bit DMA address mode

+

1: Use 64-bit DMA address mode

0

default_route_cfg1

R/W

Use fixed addresses to access devices such as USB, SATA, GMAC, etc.

+

0: Use the PCI configuration header to configure the device address

+

1: Use fixed address to access the device

+

If fix_default_route is 1, then the signal is constant to 1.

+
+

Note: In order to support the USB sleep-wake function, the USB reference clock must use a 12MHz external crystal.

+
+
+

Offset Address: 0430-0437h

+
+
+

Attribute: R/W

+
+
+

Default value: 1209_9900h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 14. Table general configuration register 0 3
Bit FieldNameRead/WriteDescription

28

hda_dma_64

R/W

Enables HDA64 bit DMA address mode

+

0: Use 32-bit DMA address mode

+

1: Use 64-bit DMA address mode

27

rtc_restart

R/W

RTC crystal oscillator restart

26:24

rtc_ds

R/W

RTC Crystal Oscillator Driver Configuration

19

sata2_clk_en

R/W

SATA2 clock enable

+

0: No clock

+

1: Normal clock

18

sata2_en

R/W

SATA2 access enable

+

0: Access disabled

+

1: Access allowed

16

sata2_cntl_soft_reset

R/W

SATA2 controller software reset

+

0: Remove reset

+

1: Hold reset

15

sata1_clken

R/W

SATA1 clock enable

+

0: No clock

+

1: Clock normal

14

sata1_en

R/W

SATA1 access enable

+

0: Access disabled

+

1: Access allowed

12

sata1_cntl_soft_reset

R/W

SATA1 controller software reset

+

0: Remove reset

+

`1: Hold reset

11

sata0_clken

R/W

SATA0 clock enable

+

0: No clock

+

1: Clock normal

10

sata0_en

R/W

SATA0 Access Enable

+

0: Access disabled

+

1: Access allowed

8

sata0_cntl_soft_reset

R/W

SATA0 Controller software reset

+

0: Remove reset

+

1: Hold Reset

+

7:1 Reserved R/W Reserved

0

lpc_en

R/W

LPC controller enable

+

0: Access is disabled

+

1: Access allowed

+
+
+

4.4. Pin Multiplexing Configuration Register

+
+

Offset Address: 0440-0443h

+
+
+

Attribute: R/W

+
+
+

Default value: FFFF_FFFFh

+
+
+

Size: 32 bits

+
+
+

This register contains configuration information related to pin multiplexing.

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 15. Pin multiplexing configuration register
Bit FieldNameRead/WriteDescription

31

uart3_enable

R/W

UART operating mode selection for pin UART_RI/DCD (when selected as UART mode)

+

0: use or not is determined by bit28

+

1: Operates in two-wire UART3 mode

30

uart2_enable

R/W

UART operating mode selection for pin UART_DTR/DSR (when selected as UART mode)

+

0: use or not is determined by bit28

+

1: Operates in two-wire UART2 mode

29

uart1_enable

R/W

UART operating mode selection for pin UART_RTS/CTS (when selected as UART mode)

+

0: use or not is determined by bit28

+

1: Operates in two-wire UART1 mode

28

uart0_full_func

R/W

UART operating mode selection for pin UART_TXD/RXD (when UART mode is selected)

+

0: Operates in two-wire UART0 mode

+

1: Working in full-function UART0 mode

+

When bit[31:29] is not equal to 0, regardless of the value of this bit, UART_TXD/RXD

+

operates in two-wire UART mode regardless of the value of the bit.

27

clkoutflex_sel

R/W

Operating mode selection for pin CLKOUTFLEX

+

0: working in GPIO mode

+

1: Operates in CLKOUTFLEX mode

26

clkout25m_sel

R/W

Operating mode selection for pin CLKOUT25M

+

0: working in GPIO mode

+

1: Operating in CLKOUT25M mode

25

lpc_sel

R/W

Operating mode selection for LPC pins (LPC_AD0-3/LPC_SERIRQ/LPC_FRAMEn)

+

0: working in GPIO mode

+

1: Working in LPC mode

24

uart_dtr_dsr_sel_i2 c

R/W

Operating mode selection for pin UART_DTR/DSR (determined together with bit20)

+

[bit24, bit20].

+

00b: working in GPIO mode

+

x1b: working in UART mode (decided by bit[31:28] whether to work in full function mode)

+

10b: working in I2C mode

23

uart_ri_dcd_sel_i2c

R/W

Operating mode selection for pin UART_RI/DCD (determined together with bit19)

+

[bit23, bit19].

+

00b: working in GPIO mode

+

x1b: working in UART mode (decided by bit[31:28] whether to work in full function mode)

+

10b: working in I2C mode

22

uart_txd_rxd_sel_u art

R/W

Operating mode selection for pin UART_TXD/RXD

+

0: working in GPIO mode

+

1: working in UART mode (the bit[31:28] determines whether to work in full function mode)

21

uart_rts_cts_sel_ua rt

R/W

Operating mode selection for pin UART_RTS/CTS

+

0: working in GPIO mode

+

1: working in UART mode (determined by bit[31:28] whether to work in full function mode)

20

uart_dtr_dsr_sel_u art

R/W

Operating mode selection for pin UART_DTR/DSR (determined together with bit24)

+

[bit24, bit20].

+

00b: working in GPIO mode

+

x1b: working in UART mode (decided by bit[31:28] whether to work in full function mode)

+

10b: working in I2C mode

19

uart_ri_dcd_sel_uar t

R/W

Operating mode selection for pin UART_RI/DCD (determined together with bit23)

+

[bit23, bit19].

+

00b: working in GPIO mode

+

x1b: working in UART mode (decided by bit[31:28] whether to work in full function mode)

+

10b: working in I2C mode

18

usb_oc2_sel

R/W

Operating mode selection for pin USB_OC2

+

0: working in GPIO mode

+

1: Working in USB_OC mode

17

usb_oc1_sel

R/W

Operating mode selection for pin USB_OC1

+

0: working in GPIO mode

+

1: Working in USB_OC mode

16

usb_oc0_sel

R/W

Operating mode selection for pin USB_OC0

+

0: working in GPIO mode

+

1: working in USB_OC mode

15

sata2_ledn_sel

R/W

Operating mode selection for pin SATA2_LEDn

+

0: working in GPIO mode

+

1: Operates in SATA mode

14

sata1_ledn_sel

R/W

Operating mode selection for pin SATA1_LEDn

+

0: working in GPIO mode

+

1: Operates in SATA mode

13

sata0_ledn_sel

R/W

Operating mode selection for pin SATA0_LEDn

+

0: working in GPIO mode

+

1: Operates in SATA mode

12:11

hda_ac97_sel

R/W

Operating mode selection for HDA pins. For the pins

+

HDA_BITCLK/HDA_SYNC/HDA_RESETn/HDA_SDO/HDA_SDI0, the operating mode is determined by bit`[12:11]: `00b: GPIO mode

+

10b: AC97 mode

+

x1b: HDA mode

+

For pins HDA_SDI1/HDA_SDI2, the operating mode is determined by bit[11]: 0: GPIO mode

+

1: HDA mode

10

spi_sel

R/W

Operating mode selection for pin SPI_SCK/SDI/SDO

+

0: Operates in GPIO mode

+

1: Operates in SPI mode

9:8

spi_csn_23_sel_spi

R/W

Operating mode selection for pin SPI_CSn2/3 00b: operates in GPIOmode

+

x1b: working in SPI mode

+

10b: Operating in I2C mode

7:6

spi_csn_01_sel_spi

R/W

Operating mode selection for pin SPI_CSn0/1 00b: Operates in GPIO mode

+

x1b: working in SPI mode

+

10b: Operating in I2C mode

5

i2c1_sel

R/W

Operating mode selection for pin I2C1_SCL/SDA

+

0: working in GPIO mode

+

1: Working in I2C mode

4

i2c0_sel

R/W

Operating mode selection for pin I2C0_SCL/SDA

+

0: working in GPIO mode

+

1: Working in I2C mode

3

pwm3_sel

R/W

Operating mode selection for pin PWM3

+

0: Operates in GPIO mode

+

1: Operates in PWM mode

2

pwm2_sel

R/W

Operating mode selection for pin PWM2

+

0: Operates in GPIO mode

+

1: Operates in PWM mode

1

pwm1_sel

R/W

Operating Mode Selection for Pin PWM1

+

0: Operates in GPIO mode

+

1: Operates in PWM mode

0

pwm0_sel

R/W

Operating mode selection for pin PWM0

+

0: Operates in GPIO mode

+

1: Operates in PWM mode

+
+

The multiplexing relationship between the VSB_GATEn pin and GPIO01 is configured by the internal register (PMCON_RESUME) of the power management module, see 12.3 Register Description.

+
+
+

See the chip pin multiplexing table in Appendix 1 for a cross-reference to the chip pin multiplexing table.

+
+
+
+

4.5. PLL0 Configuration Register

+
+

Please refer to Section 2.5 PLL Configuration Method for the specific usage of PLL. +This register is used to set PLL0, where output clock 1 is used to generate the 125MHz clock required by the GMAC, and output clock 0

+
+
+

is used to generate the controller clock for USB/SATA.

+
+
+

Offset Address: 0480-0483h

+
+
+

Attribute: R/W

+
+
+

Default value: 0000_0000h

+
+
+

Size: 32 bits

+
+
+

This register contains configuration information related to pin multiplexing.

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 16. PLL0 configuration register 1
Bit FieldNameRead/WriteDescription

31:30

Reserved

R/W

Reserved

29:21

pll_loopc

R/W

PLL Multiplier

20:14

pll_div_out2

R/W

PLL output clock 2 divisions

13:7

pll_div_out1

R/W

PLL output clock 1 division

6:0

pll_div_out0

R/W

PLL output clock 0 divisions

+
+

Offset Address: 0484-0487h

+
+
+

Attribute: R/W

+
+
+

Default value: 0000_0000h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 17. PLL0 configuration register 2
Bit FieldNameRead/WriteDescription

31:14

Reserved

R/W

Reserved

13

pll_pd

R/W

PLL powerdown

12

pll_bypass

R/W

PLL internal bypass

11

set_pll_param

R/W

Set PLL configuration parameters

10

sel_pll_out2

R/W

Select PLL output clock 2

9

sel_pll_out1

R/W

Select PLL output clock 1

8

sel_pll_out0

R/W

Select PLL Output Clock 0

7

pll_locked

RO

PLL Lock

6:0

pll_div_ref

R/W

PLL Input Frequency Division Number

+
+
+

4.6. PLL1 Configuration Register

+
+

Please refer to Section 2.5 PLL Configuration Method for the specific usage of PLL.

+
+
+

This register is used to set PLL1, where output clock 2 is used to generate the GPU clock, output clock 1 is used to generate the GMEM clock, and output clock 0 is used to generate the DC clock.

+
+
+

Offset Address: 0490-0493h

+
+
+

Attribute: R/W

+
+
+

Default value: 0000_0000h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 18. PLL1 configuration register 1
Bit FieldNameRead/WriteDescription

31:30

Reserved

R/W

Reserved

29:21

pll_loopc

R/W

PLL Multiplier

20:14

pll_div_out2

R/W

PLL output clock 2 divisions

13:7

pll_div_out1

R/W

PLL output clock 1 division

6:0

pll_div_out0

R/W

PLL output clock 0 divisions

+
+

Offset Address: 0494-0497h

+
+
+

Attribute: R/W

+
+
+

Default value: 0000_0000h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 19. PLL1 configuration register 2
Bit FieldNameRead/WriteDescription

31:14

Reserved

R/W

Reserved

13

pll_pd

R/W

PLL powerdown

12

pll_bypass

R/W

PLL internal bypass

11

set_pll_param

R/W

Set PLL configuration parameters

10

sel_pll_out2

R/W

Select PLL output clock 2

9

sel_pll_out1

R/W

Select PLL output clock 1

8

sel_pll_out0

R/W

Select PLL Output Clock 0

7

pll_locked

RO

PLL Lock

6:0

pll_div_ref

R/W

PLL Input Frequency Division Number

+
+
+

4.7. PLL2 Configuration Register

+
+

Please refer to Section 2.5 PLL Configuration Method for the specific usage of PLL. +This register is used to set PLL2, where output clock 2 is used to generate the CLKOUTFLEX clock, output clock 1 is used to generate the internal bus clock, and output clock 0 is used to generate the 24MHz bitclk clock required by the HDA.

+
+
+

Output Clock 1 is used to generate the internal bus clock, and Output Clock 0 is used to generate the 24MHz bitclk clock required by the HDA.

+
+
+

Address Offset: 04A0-04A3h

+
+
+

Attribute: R/W

+
+
+

Default value: 0000_0000h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 20. Pll2 configuration register 1
Bit FieldNameRead/WriteDescription

31:30

Reserved

R/W

Reserved

29:21

pll_loopc

R/W

PLL Multiplier

20:14

pll_div_out2

R/W

PLL output clock 2 divisions

13:7

pll_div_out1

R/W

PLL output clock 1 division

6:0

pll_div_out0

R/W

PLL output clock 0 divisions

+
+

Address Offset: 04A4-04A7h

+
+
+

Attribute: R/W

+
+
+

Default value: 0000_0000h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 21. Pll2 configuration register 2
Bit FieldNameRead/WriteDescription

31:14

Reserved

R/W

Reserved

13

pll_pd

R/W

PLL powerdown

12

pll_bypass

R/W

PLL internal bypass

11

set_pll_param

R/W

Set PLL configuration parameters

10

sel_pll_out2

R/W

Select PLL output clock 2

9

sel_pll_out1

R/W

Select PLL output clock 1

8

sel_pll_out0

R/W

Select PLL Output Clock 0

7

pll_locked

RO

PLL Lock

6:0

pll_div_ref

R/W

PLL Input Frequency Division Number

+
+
+

4.8. PLL_PIX_0 Configuration Register

+
+

Refer to Section 2.5 PLL Configuration Methods for the specific usage of the PLL.

+
+
+

This register is used to set PLL_PIX_0, where output clock 0 is used to generate the PIX0 clock.

+
+
+

Address Offset: 04B0-04B3h

+
+
+

Attribute: R/W

+
+
+

Default value: 0000_0000h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 22. Pll pix 0 configuration register 1
Bit FieldNameRead/WriteDescription

31:30

Reserved

R/W

Reserved

29:21

pll_loopc

R/W

PLL Multiplier

20:7

Reserved

R/W

Reserved

6:0

pll_div_out0

R/W

PLL Output Clock 0 Divider

+
+

Address Offset: 04B4-04B7h

+
+
+

Attribute: R/W

+
+
+

Default value: 0000_0000h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 23. Pll pix 0 configuration register 2
Bit FieldNameRead/WriteDescription

31:14

Reserved

R/W

Reserved

13

pll_pd

R/W

PLL powerdown

12

pll_bypass

R/W

PLL internal bypass

11

set_pll_param

R/W

Set PLL configuration parameters

10:9

Reserved

R/W

Reserved

8

sel_pll_out0

R/W

Select PLL output clock 0

7

pll_locked

RO

PLL Lock

6:0

pll_div_ref

R/W

Number of PLL input divisions

+
+
+

4.9. PLL_PIX_1 Configuration Register

+
+

Refer to Section 2.5 PLL Configuration Methods for the specific usage of the PLL. +This register is used to set PLL_PIX_1, where output clock 0 is used to generate the PIX1 clock.

+
+
+

Address Offset: 04C0-04C3h

+
+
+

Attribute: R/W

+
+
+

Default value: 0000_0000h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 24. PLL_PIX_1 Configuration Register 1
Bit FieldNameRead/WriteDescription

31:30

Reserved

R/W

Reserved

29:21

pll_loopc

R/W

PLL Multiplier

20:7

Reserved

R/W

Reserved

6:0

pll_div_out0

R/W

PLL Output Clock 0 Divider

+
+

Address Offset: 04C4-04C7h

+
+
+

Attribute: R/W

+
+
+

Default value: 0000_0000h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 25. PLL_PIX_1 Configuration Register 2
Bit FieldNameRead/WriteDescription

31:14

Reserved

R/W

Reserved

13

pll_pd

R/W

PLL powerdown

12

pll_bypass

R/W

PLL internal bypass

11

set_pll_param

R/W

Set PLL configuration parameters

10:9

Reserved

R/W

Reserved

8

sel_pll_out0

R/W

Select PLL output clock 0

7

pll_locked

RO

PLL lockout

6:0

pll_div_ref

R/W

Number of PLL input divisions

+
+
+

4.10. PCIE_F0 PHY Configuration Register

+
+

This set of registers contains the control signals for PCIE_F0 PHY.

+
+
+

Address Offset: 0588-058Bh

+
+
+

Attribute: R/W,RO

+
+
+

Default value: 0006_0000h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 26. Pcie f0 phy configuration register
Bit FieldNameRead/WriteDescription

27

cfg_x4_mode_en

R/W

Enable software to configure the operating mode of PCIE_F0 +0: the operating mode is determined by the hardware pin +1: The operating mode is determined by the software configuration (bit26)

26

cfg_x4_mode

R/W

Software configuration of PCIE_F0 operating modes

+

0: working in x1 mode

+

1: working in x4 mode

24

phy_powerdown

R/W

Set PHY into low-power mode

+
+
+

4.11. PCIE_F0 PHY Access Configuration Register

+
+

This group of registers is used to control the configuration access operation that generates the PCIE_F0 PHY internal control register. +This register controls the 4 data links of PCIE_F0.

+
+
+

Address Offset: 0590-0593h

+
+
+

Attribute: R/W

+
+
+

Default value: 0000_0000h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + +
Table 27. PCIE_F0 PHY Access Configuration Register 1
Bit FieldNameRead/WriteDescription

31:16

phy_cfg_data

R/W

PHY configuration reads and writes data.In the write operation, the data is written to this register before the write operation is executed; in the read operation, the read data returned from PHY is stored to this register.

15:0

phy_cfg_addr

R/W

PHY configures the address.

+
+

Address Offset: 0594-0597h

+
+
+

Attribute: R/W,

+
+
+

Default value: 0000_0000h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 28. PCIE_F0 PHY Access Configuration Register 2
Bit FieldNameRead/WriteDescription

31:7

Reserved

R/W

Reserved

6

phy_cfg_reset

R/W

PHY Configuration Reset, High Active

5:3

phy_cfg_state

RO

PHY Configuration Status Machine Status Indication

2

phy_cfg_done

R/W

PHY One access completion indicates the completion of reading and writing to PHY. Write completion indicates that the write data has been written to the PHY internal register, and read completion indicates that the read data has been returned to the to the phy_cfg_data register

1

phy_cfg_disable

R/W

0 - Read and write to this set of registers will trigger PHY configuration access operation

+

1 - Read or write to this set of registers does not trigger PHY configuration access operation, only a simple register read or write

0

phy_cfg_R/W

R/W

Start a read operation or a write operation.

+

0: Read operation

+

1: Write operation

+
+
+

4.12. PCIE_F1 PHY Configuration Register

+
+

This set of registers contains the control signals for PCIE_F1 PHY.

+
+
+

Address Offset: 05A8-05ABh

+
+
+

Attribute: R/W,RO

+
+
+

Default value: 0006_0000h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 29. PCIE_F1 PHY Configuration Register 1
Bit FieldNameRead/WriteDescription

27

cfg_x4_mode_en

R/W

Enable software to configure the operating mode of PCIE_F1

+

0: the operating mode is determined by the hardware pin

+

1: The operating mode is determined by the software configuration (bit26)

26

cfg_x4_mode

R/W

Software configuration of PCIE_F1 operating modes

+

0: working in x1 mode

+

1: working in x4 mode

24

phy_powerdown

R/W

Set PHY into low-power mode

+
+
+

4.13. PCIE_F1 PHY Access Configuration Register

+
+

This group of registers is used to control the configuration access operation that generates the PCIE_F1 PHY internal control register. +This register controls the 4 data links of PCIE_F1.

+
+
+

Address Offset: 05B0-05B3h

+
+
+

Attribute: R/W

+
+
+

Default value: 0000_0000h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + +
Table 30. pcie f1 phy access configuration register 1
Bit FieldNameRead/WriteDescription

31:16

phy_cfg_data

R/W

PHY configuration reads and writes data. In the write operation, the data is written to this register first, and then the write operation is performed. In the read operation, the read data returned from PHY is stored into this register.

15:0

phy_cfg_addr

R/W

PHY configuration address

+
+

Address Offset: 05B4-05B7h

+
+
+

Attribute: R/W

+
+
+

Default value: 0000_0000h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 31. pcie f1 phy access configuration register 2
Bit FieldNameRead/WriteDescription

31:7

Reserved

R/W

Reserved

6

phy_cfg_reset

R/W

PHY Configuration Reset, High Active

5:3

phy_cfg_state

RO

PHY Configuration Status Machine Status Indication

2

phy_cfg_done

R/W

The completion of one access to PHY indicates the completion of reading and writing to PHY. Write completion indicates that the written data has been written to the PHY internal register, and read completion indicates that the read data has been returned to the phy_cfg_data register

1

phy_cfg_disable

R/W

0 - Read or write to this group of registers will trigger the PHY configuration access operation

+

1 - Read or write to this set of registers does not trigger PHY configuration access operation, only a simple register read or write

0

phy_cfg_R/W

R/W

Start a read operation or a write operation.

+

0: Read operation

+

1: Write operation

+
+
+

4.14. PCIE_H PHY Configuration Register

+
+

This group of registers contains the control signals for PCIE_H PHY.

+
+
+

Address Offset: 05C8-05CBh

+
+
+

Attribute: R/W,RO

+
+
+

Default value: 0006_0000h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 32. Pcie h phy configuration register
Bit FieldNameRead/WriteDescription

27

cfg_x4_mode_en

R/W

Enable software to configure the operating mode of PCIE_H

+

0: the operating mode is determined by the hardware pins

+

1: The operating mode is determined by the software configuration (bit26)

26

cfg_x4_mode

R/W

Software configuration of PCIE_H operating modes

+

0: working in x8 mode

+

1: working in x4 mode

25

phy_powerdown_hi

R/W

Set the high four bits of PHY to enter the low-power mode

24

phy_powerdown_lo

R/W

Set PHY low four bits to enter low-power mode

+
+
+

4.15. PCIE_H PHY LO Access Configuration Register

+
+

This group of registers is used to control the configuration access operation that generates the PCIE_H PHY LO internal control register. +This register controls the the lower 4 data links (lane0-3) of PCIE_H.

+
+
+

Address Offset: 05D0-05D3h

+
+
+

Attribute: R/W

+
+
+

Default value: 0000_0000h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + +
Table 33. Pcie h phy lo access configuration register 1
Bit FieldNameRead/WriteDescription

31:16

phy_cfg_data

R/W

PHY configuration reads and writes data. In the write operation, the data is written to this register first, and then the write operation is performed. In the read operation, the read data returned from PHY is stored into this register.

15:0

phy_cfg_addr

R/W

PHY Configuration Address

+
+

Address Offset: 05D4-05D7h

+
+
+

Attribute: R/W,

+
+
+

Default value: 0000_0000h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 34. Pcie h phy lo access configuration register 2
Bit FieldNameRead/WriteDescription

31:7

Reserved

R/W

Reserved

6

phy_cfg_reset

R/W

PHY Configuration Reset, High Active

5:3

phy_cfg_state

RO

PHY Configuration Status Machine Status Indication

2

phy_cfg_done

R/W

The completion of one access to PHY indicates the completion of reading and writing to PHY. +Write completion indicates that the written data has been written to the PHY internal register, and read completion indicates that the read data has been returned to the phy_cfg_data register

1

phy_cfg_disable

R/W

0 - Read or write to this group of registers will trigger the PHY configuration access operation

+

1 - Read or write to this set of registers does not trigger PHY configuration access operation, only a simple register read or write

0

phy_cfg_R/W

R/W

Start a read operation or a write operation.

+

0: Read operation

+

1: Write operation

+
+
+

4.16. PCIE_H PHY HI Access Configuration Register

+
+

This group of registers is used to control the configuration access operation that generates the PCIE_H PHY HI internal control register. +This register controls the the high 4 data links (lane4-7) of PCIE_H.

+
+
+

Address Offset: 05D8-05DBh

+
+
+

Attribute: R/W

+
+
+

Default value: 0000_0000h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + +
Table 35. Pcie h phy hi access configuration register 1
Bit FieldNameRead/WriteDescription

31:16

phy_cfg_data

R/W

PHY configures the read and write data. In the write operation, the data is written to this register before the write operation is executed; in the read operation, the read data returned from PHY is stored to this register.

15:0

phy_cfg_addr

R/W

PHY Configuration Address

+
+

Address Offset: 05DC-05DFh

+
+
+

Attribute: R/W,

+
+
+

Default value: 0000_0000h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 36. Pcie h phy hi access configuration register 2
Bit FieldNameRead/WriteDescription

31:7

Reserved

R/W

Reserved

6

phy_cfg_reset

R/W

PHY Configuration Reset, High Active

5:3

phy_cfg_state

RO

PHY Configuration Status Machine Status Indication

2

phy_cfg_done

R/W

The completion of one access to PHY indicates the completion of reading and writing to PHY. Write completion indicates that the written data has been written to the PHY internal register, and read completion indicates that the read data has been returned to the phy_cfg_data register

1

phy_cfg_disable

R/W

0 - Read or write to this group of registers will trigger the PHY configuration access operation

+

1 - Read or write to this set of registers does not trigger PHY configuration access operation, only a simple register read or write

0

phy_cfg_R/W

R/W

Start a read operation or a write operation. +0: Read operation +1: Write operation

+
+
+

4.17. PCIE_G0 PHY Configuration Register

+
+

This set of registers contains the control signals for PCIE_G0 PHY.

+
+
+

Address Offset: 05E8-05EBh

+
+
+

Attribute: R/W,RO

+
+
+

Default value: 0006_0000h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 37. Pcie g0 phy configuration register
Bit FieldNameRead/WriteDescription

27

cfg_x4_mode_en

R/W

Enables software to configure the operating mode of PCIE_G0

+

0: the operating mode is determined by the hardware pins

+

1: The operating mode is determined by the software configuration (bit26)

26

cfg_x4_mode

R/W

Software configuration of PCIE_G0 operating modes

+

0: working in x8 mode

+

1: working in x4 mode

25

phy_powerdown_hi

R/W

Set the high four bits of PHY to enter the low-power mode

24

phy_powerdown_lo

R/W

Set PHY low four bits to enter low-power mode

+
+
+

4.18. PCIE_G0 PHY LO Access Configuration Register

+
+

This group of registers is used to control the configuration access operation that generates the PCIE_G0 PHY LO internal control register. +This register controls the the lower 4 data links (lane0-3) of PCIE_G0.

+
+
+

Address Offset: 05F0-05F3h

+
+
+

Attribute: R/W

+
+
+

Default value: 0000_0000h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + +
Table 38. Pcie g0 phy lo access configuration register 1
Bit FieldNameRead/WriteDescription

31:16

phy_cfg_data

R/W

PHY configuration reads and writes data. In the write operation, the data is written to this register first, and then the write operation is performed. In the read operation, the read data returned from PHY is stored into this register.

15:0

phy_cfg_addr

R/W

PHY Configuration Address

+
+

Address Offset: 05F4-05F7h

+
+
+

Attribute: R/W,

+
+
+

Default value: 0000_0000h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 39. Pcie g0 phy lo access configuration register 2
Bit FieldNameRead/WriteDescription

31:7

Reserved

R/W

Reserved

6

phy_cfg_reset

R/W

PHY Configuration Reset, High Active

5:3

phy_cfg_state

RO

PHY Configuration Status Machine Status Indication

2

phy_cfg_done

R/W

PHY One access completion indicates the completion of this read/write to the PHY. Write completion indicates that the write indicates that the read data has been written to the internal register of PHY, and the read completion indicates that the read data has been returned to the phy_cfg_data register.

1

phy_cfg_disable

R/W

0 - Read or write to this group of registers will trigger the PHY configuration access operation

+

1 - Read or write to this set of registers does not trigger PHY configuration access operation, only a simple register read or write

0

phy_cfg_R/W

R/W

Start a read operation or a write operation.

+

0: Read operation

+

1: Write operation

+
+
+

4.19. PCIE_G0 PHY HI Access Configuration Register

+
+

This group of registers is used to control the configuration access operation that generates the PCIE_G0 PHY HI internal control register. +This register controls the the high 4 data links (lane4-7) of PCIE_G0.

+
+
+

Address Offset: 05F8-05FBh

+
+
+

Attribute: R/W

+
+
+

Default value: 0000_0000h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + +
Table 40. Pcie g0 phy hi access configuration register 1
Bit FieldNameRead/WriteDescription

31:16

phy_cfg_data

R/W

PHY configuration reads and writes data. In the write operation, the data is written to this register first, and then the write operation is performed. In the read operation, the read data returned from PHY is stored into this register.

15:0

phy_cfg_addr

R/W

PHY configuration address

+
+

Address Offset: 05FC-05FFh

+
+
+

Attribute: R/W,

+
+
+

Default value: 0000_0000h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 41. Pcie g0 phy hi access configuration register 2
Bit FieldNameRead/WriteDescription

31:7

Reserved

R/W

Reserved

6

phy_cfg_reset

R/W

PHY Configuration Reset, High Active

5:3

phy_cfg_state

RO

PHY Configuration Status Machine Status Indication

2

phy_cfg_done

R/W

The completion of one access to PHY indicates the completion of reading and writing to PHY. Write completion indicates that the written data has been written to the PHY internal register, and read completion indicates that the read data has been returned to the to the phy_cfg_data register

1

phy_cfg_disable

R/W

0 - Read or write to this set of registers will trigger the PHY configuration access operation

+

1-Writes and writes to this set of registers do not trigger a PHY configuration access operation, only a simple register register read/write

0

phy_cfg_R/W

R/W

Start a read operation or a write operation.

+

0: Read operation

+

1: Write operation

+
+
+

4.20. PCIE_G1 PHY Configuration Register

+
+

This set of registers contains the control signals for PCIE_G1 PHY.

+
+
+

Address Offset: 0608-060Bh

+
+
+

Attribute: R/W,RO

+
+
+

Default value: 0006_0000h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 42. PCIE_G1 PHY configuration register
Bit FieldNameRead/WriteDescription

31:30

Reserved

R/W

Reserved

27

cfg_x4_mode_en

R/W

Enable software to configure the operating mode of PCIE_G1

+

0: the operating mode is determined by the hardware pins

+

1: The operating mode is determined by the software configuration (bit26)

26

cfg_x4_mode

R/W

Software configuration of PCIE_G1 operating modes

+

0: working in x8 mode

+

1: working in x4 mode

25

phy_powerdown_hi

R/W

Set the high four bits of PHY to enter the low-power mode

24

phy_powerdown_lo

R/W

Set PHY low four bits to enter low-power mode

+
+
+

4.21. PCIE_G1 PHY LO Access Configuration Register

+
+

This group of registers is used to control the configuration access operation that generates the PCIE_G1 PHY LO internal control register. +This register controls the the lower 4 data links (lane0-3) of PCIE_G1.

+
+
+

Address Offset: 0610-0613h

+
+
+

Attribute: R/W

+
+
+

Default value: 0000_0000h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + +
Table 43. PCIE_G1 PHY LO access configuration register 1
Bit FieldNameRead/WriteDescription

31:16

phy_cfg_data

R/W

PHY configuration reads and writes data. In the write operation, the data is written to this register first, and then the write operation is performed. In the read operation, the read data returned from PHY is stored into this register.

15:0

phy_cfg_addr

R/W

PHY Configuration Address

+
+

Address Offset: 0614-0617h

+
+
+

Attribute: R/W,

+
+
+

Default value: 0000_0000h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 44. PCIE_G1 PHY LO access configuration register 2
Bit FieldNameRead/WriteDescription

31:7

Reserved

R/W

Reserved

6

phy_cfg_reset

R/W

PHY Configuration Reset, High Active

5:3

phy_cfg_state

RO

PHY Configuration Status Machine Status Indication

2

phy_cfg_done

R/W

PHY One Access Complete indicates that the read or write to the PHY is complete. Write completion indicates that the write Read completion indicates that the read data has been returned to the phy_cfg_data register.

1

phy_cfg_disable

R/W

0 - Read or write to this group of registers will trigger the PHY configuration access operation

+

1 - Reading or writing to this set of registers does not trigger a PHY configuration access operation, only a simple register read or write

0

phy_cfg_R/W

R/W

+
+
+

4.22. PCIE_G1 PHY HI Access Configuration Register

+
+

This group of registers is used to control the configuration access operation that generates the PCIE_G1 PHY HI internal control register. +This register controls the high 4 data links (lane4-7) of PCIE_G1.

+
+
+

Address Offset: 0618-061Bh

+
+
+

Attribute: R/W

+
+
+

Default value: 0000_0000h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + +
Table 45. PCIE_G1 PHY HI access configuration register 1
Bit FieldNameRead/WriteDescription

31:16

phy_cfg_data

R/W

PHY configures the read and write data. In the write operation, the data is written to this register before the write operation is executed; in the read operation, the read data returned from PHY is stored to this register.

15:0

phy_cfg_addr

R/W

PHY Configuration Address

+
+

Address Offset: 061C-061Fh

+
+
+

Attribute: R/W,

+
+
+

Default value: 0000_0000h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 46. PCIE_G1 PHY HI access configuration register 2
Bit FieldNameRead/WriteDescription

31:7

Reserved

R/W

Reserved

6

phy_cfg_reset

R/W

PHY Configuration Reset, High Active

5:3

phy_cfg_state

RO

PHY Configuration Status Machine Status Indication

2

phy_cfg_done

R/W

The completion of one access to PHY indicates the completion of reading and writing to PHY. Write completion indicates that the written data has been written to the PHY internal register, and read completion indicates that the read data has been returned to the phy_cfg_data register

1

phy_cfg_disable

R/W

0 - Read or write to this group of registers will trigger the PHY configuration access operation

+

1 - Read or write to this set of registers does not trigger PHY configuration access operation, only a simple register read or write

0

phy_cfg_R/W

R/W

Start a read operation or a write operation.

+

0: Read operation

+

1: Write operation

+
+
+

4.23. SATA0 PHY Configuration Register

+
+

This register is used to configure some control parameters of SATA0 PHY.

+
+
+

Address Offset: 0740-0743h

+
+
+

Attribute: R/W

+
+
+

Default value: FF9F_0403h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 47. SATA0 PHY Configuration Register 1
Bit FieldNameRead/WriteDescription

3

Port_reset

R/W

Link Reset

2

PHY_reset

R/W

PHY Software Reset +0:Unreset +1: Hold reset

1

ref_use_pad

R/W

PHY Reference Clock Selection

+

0: Use internal reference clock

+

1: Use external reference clock

0

Reserved

R/W

Reserved

+
+

Address Offset: 0744-0747h

+
+
+

Attribute: R/W

+
+
+

Default value: 7FFF_FFFFh

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + +
Table 48. SATA0 PHY Configuration Register 2
Bit FieldNameRead/WriteDescription

31

Phy_power_down

R/W

PHY Powerdown

+
+
+

4.24. SATA0 PHY Access Configuration Register

+
+

This group of registers is used to control the generation of configuration access operations to the SATA0 PHY internal control registers.

+
+
+

Address Offset: 0748-074Bh

+
+
+

Attribute: R/W

+
+
+

Default value: 0000_0000h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + +
Table 49. SATA0 PHY Access Configuration Register 1
Bit FieldNameRead/WriteDescription

31:16

phy_cfg_data

R/W

PHY configuration reads and writes data. In the write operation, the data is written to this register first, and then the write operation is performed. In the read operation, the read data returned from PHY is stored into this register.

15:0

phy_cfg_addr

R/W

PHY configuration address

+
+

Address Offset: 074C-074Fh

+
+
+

Attribute: R/W,

+
+
+

Default value: 0000_0000h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 50. SATA0 PHY Access Configuration Register 2
Bit FieldNameRead/WriteDescription

31:7

Reserved

R/W

Reserved

6

phy_cfg_reset

R/W

PHY Configuration Reset, High Active

5:3

phy_cfg_state

RO

PHY Configuration Status Machine Status Indication

2

phy_cfg_done

R/W

The completion of one access to PHY indicates the completion of reading and writing to PHY. Write completion indicates that the written data has been written to the PHY internal register, and read completion indicates that the read data has been returned to the to the phy_cfg_data register

1

phy_cfg_disable

R/W

0 - Reading or writing to this set of registers triggers a PHY configuration access operation

+

1 - Reading or writing to this set of registers does not trigger a PHY configuration access operation, but rather acts as a read or write operation to this register

0

phy_cfg_R/W

R/W

Start a read operation or a write operation.

+

0: Read operation

+

1: Write operation

+
+
+

4.25. SATA1 PHY Configuration Register

+
+

This register is used to configure some control parameters of SATA1 PHY.

+
+
+

Address Offset: 0750-0753h

+
+
+

Attribute: R/W

+
+
+

Default value: FF9F_0403h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 51. SATA1 PHY Configuration Register 1
Bit FieldNameRead/WriteDescription

3

Port_reset

R/W

Link Reset

2

PHY_reset

R/W

PHY Software Reset

+

0: Release reset

+

1: Hold reset

1

ref_use_pad

R/W

PHY Reference Clock Selection

+

0: Use internal reference clock

+

1: Use external reference clock

0

Reserved

R/W

Reserved

+
+

Address Offset: 0754-0757h

+
+
+

Attribute: R/W

+
+
+

Default value: 7FFF_FFFFh

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + +
Table 52. SATA1 PHY Configuration Register 2
Bit FieldNameRead/WriteDescription

31

Phy_power_down

R/W

PHY Powerdown

+
+
+

4.26. SATA1 PHY Access Configuration Register

+
+

This group of registers is used to control the generation of configuration access operations to the SATA1 PHY internal control registers.

+
+
+

Address Offset: 0758-075Bh

+
+
+

Attribute: R/W

+
+
+

Default value: 0000_0000h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + +
Table 53. SATA1 PHY Access Configuration Register 1
Bit FieldNameRead/WriteDescription

31:16

phy_cfg_data

R/W

PHY configuration reads and writes data. In the write operation, the data is written to this register first, and then the write operation is performed. In the read operation, the read data returned from PHY is stored into this register.

15:0

phy_cfg_addr

R/W

PHY Configuration Address

+
+

Address Offset: 075C-075Fh

+
+
+

Attribute: R/W,

+
+
+

Default value: 0000_0000h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 54. SATA1 PHY Access Configuration Register 2
Bit FieldNameRead/WriteDescription

31:7

Reserved

R/W

Reserved

6

phy_cfg_reset

R/W

PHY Configuration Reset, High Active

5:3

phy_cfg_state

RO

PHY Configuration Status Machine Status Indication

2

phy_cfg_done

R/W

The completion of one access to PHY indicates the completion of reading and writing to PHY. Write completion indicates that the written data has been written to the PHY internal register, and read completion indicates that the read data has been returned to the to the phy_cfg_data register

1

phy_cfg_disable

R/W

0 - Reading or writing to this set of registers triggers a PHY configuration access operation

+

1 - Reading or writing to this set of registers does not trigger a PHY configuration access operation, but rather acts as a read or write operation to this register

0

phy_cfg_R/W

R/W

Start a read operation or a write operation.

+

0: Read operation

+

1: Write operation

+
+
+

4.27. SATA2 PHY Configuration Register

+
+

This register is used to configure some control parameters of SATA2 PHY.

+
+
+

Address Offset: 0760-0763h

+
+
+

Attribute: R/W

+
+
+

Default value: FF9F_0403h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 55. SATA2 PHY Configuration Register 1
Bit FieldNameRead/WriteDescription

3

Port_reset

R/W

Link Reset

2

PHY_reset

R/W

PHY Software Reset +0: Release reset +1: Hold reset

1

ref_use_pad

R/W

PHY Reference Clock Selection

+

0: Use internal reference clock

+

1: Use external reference clock

0

Reserved

R/W

Reserved

+
+

Address Offset: 0764-0767h

+
+
+

Attribute: R/W

+
+
+

Default value: 7FFF_FFFFh

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + +
Table 56. SATA2 PHY Configuration Register 2
Bit FieldNameRead/WriteDescription

31

Phy_power_down

R/W

PHY Powerdown

+
+
+

4.28. SATA2 PHY Access Configuration Register

+
+

This group of registers is used to control the generation of configuration access operations to the SATA2 PHY internal control registers.

+
+
+

Address Offset: 0768-076Bh

+
+
+

Attribute: R/W

+
+
+

Default value: 0000_0000h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + +
Table 57. SATA2 PHY Access Configuration Register 1
Bit FieldNameRead/WriteDescription

31:16

phy_cfg_data

R/W

PHY configuration reads and writes data. In the write operation, the data is written to this register first, and then the write operation is performed. In the read operation, the read data returned from PHY is stored into this register.

15:0

phy_cfg_addr

R/W

PHY Configuration Address

+
+

Address Offset: 076C-076Fh

+
+
+

Attribute: R/W,

+
+
+

Default value: 0000_0000h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 58. SATA2 PHY Access Configuration Register 2
Bit FieldNameRead/WriteDescription

31:7

Reserved

R/W

Reserved

6

phy_cfg_reset

R/W

PHY Configuration Reset, High Active

5:3

phy_cfg_state

RO

PHY Configuration Status Machine Status Indication

2

phy_cfg_done

R/W

PHY One access completion indicates the completion of this read/write to the PHY. Write completion indicates that the write indicates that the read data has been written to the internal register of PHY, and the read completion indicates that the read data has been returned to the phy_cfg_data register.

1

phy_cfg_disable

R/W

0: Reading or writing to this set of registers triggers the PHY configuration access operation

+

1: Reading or writing to this set of registers does not trigger a PHY configuration access operation, but is performed as a read or write to this register. read or write to this register

0

phy_cfg_R/W

R/W

Start a read operation or a write operation.

+

0: Read operation

+

1: Write operation

+
+
+

4.29. Memory Capacity Configuration Register

+
+

This set of registers is used to configure the capacity of the video memory. This register represents the mask of the memory BAR register, 0 means the corresponding bit of the memory BAR register is writable, 1 means not writable. +The number of 1’s represents the memory capacity. The default memory capacity is 256MB.

+
+
+

Address Offset: 3838-383Bh

+
+
+

Attribute: R/W

+
+
+

Default value: 0FFF_FFFFh

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + +
Table 59. Memory capacity configuration register 1
Bit FieldNameRead/WriteDescription

31:0

gmem_bar_mask

R/W

The lower 32 bits of the memory BAR register mask.

+

0: The corresponding bit of the memory BAR is writable

+

1: The corresponding bit of the memory BAR is not writable

+
+

Address Offset: 383C-383Fh

+
+
+

Attribute: R/W,

+
+
+

Default value: 0000_0000h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + +
Table 60. Memory capacity configuration register 2
Bit FieldNameRead/WriteDescription

31:0

gmem_bar_mask

R/W

The high 32 bits of the memory BAR register mask.

+

0: The corresponding bit of the memory BAR is writable

+

1: The corresponding bit of the memory BAR is not writable

+
+
+

4.30. Bridge Identity register

+
+

This register contains the identification ID and revision number of the bridge.

+
+
+

Address Offset: 3FF8-3FFBh

+
+
+

Attribute: RO

+
+
+

Default value: See the description in the table below

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + +
Table 61. Bridge Identity register 3
Bit FieldNameRead/WriteDescription

31:24

fix_id

RO

Bridge fixed ID (0x7A).

23:0

variable_id

RO

Bridge Variable ID.

+
+

Address Offset: 3FFC-3FFFh

+
+
+

Attribute: RO

+
+
+

Default value: See the description in the table below

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + +
Table 62. Bridge Identity register 4
Bit FieldNameRead/WriteDescription

31:24

revision_number

RO

Bridge piece revision number.

23:0

Reserved

RO

Reserved

+
+
+
+
+

5. Interrupt Controller

+
+
+

The bridge chip has an integrated advanced programmable interrupt controller. +The internal interrupt controller supports up to 64 interrupt sources and two interrupt outputs.

+
+
+

The bridge supports interrupt transmission via both interrupt lines and HT messages.

+
+
+

In the interrupt line method, the bridge’s interrupt output pins are connected to the processor’s interrupt input pins, and the processor is interrupted via the interrupt pins.

+
+
+

In the HT message method, no additional interrupt pin connection is required, and the bridge sends the interrupt vector to the processor’s HT controller register by means of an HT packet, and the processor is interrupted by the HT controller interrupt.

+
+
+

The bridge chip supports the use of only one of these two interrupt methods and is valid for all 64 interrupt sources simultaneously.

+
+
+

The bridge supports outputting dual interrupts, meaning that interrupt information can be routed to both processors. +The correspondence between interrupt sources and interrupt outputs is configurable, and this configuration is valid for both interrupt line and HT message packet interrupt modes.

+
+
+

In interrupt line interrupt mode, the interrupt lines of all interrupt-capable devices inside the bridge chip are sent directly to the bridge chip’s interrupt controller, and external PCIE devices send interrupts to the bridge chip’s internal PCIE controller via legacy interrupts. +The bridge’s interrupt controller finally interrupts the processor via the bridge’s interrupt pin signal.

+
+
+

In HT message interrupt mode, all devices inside the bridge except the PCIE send interrupt information to the interrupt controller of the bridge via the interrupt line, and the interrupt controller converts the interrupt information into HT message packets and sends them to the processor via the HT bus.

+
+
+

For PCIE devices, there are two interrupt modes, one is that the device still uses legacy interrupt and sends the interrupt information to the interrupt controller of the bridge through the interrupt line of the PCIE controller of the bridge, and the interrupt controller is responsible for converting the interrupt information into HT message packets; +the other is to enable the MSI interrupt function of the PCIE device, and the MSI interrupt message of the device passes through the PCIE controller of the bridge. +The other is to enable the MSI interrupt function of the PCIE device, and the device’s MSI interrupt messages are converted into HT packets by the conversion module inside the bridge’s PCIE controller.

+
+
+

Note that in the latter mode, the interrupt packets of the PCIE device do not support interrupt routing and can only be sent to the HT lo controller of the bridge.

+
+
+
+schematic of the interrupt system of 3a 7a +
+
Figure 7. Schematic of the interrupt system of 3A + 7A
+
+
+

The figure above illustrates the hardware modules and processes involved in interrupts using the 3A+7A computer system as an example.

+
+
+

The figure shows the process of the two interrupt methods, the upper part shows the interrupt through the interrupt line INTn0, and the lower part shows the interrupt through the HT message packet.

+
+
+

The interrupt intX from the device (except for PCIE devices operating in MSI mode) is sent to the 7A internal interrupt controller, where it is routed to the bridge pin or converted into an HT packet and sent to the 3A’s HT controller, which receives the interrupt through the external interrupt pin or HT controller interrupt, +and is routed through the interrupt to The interrupt controller of 3A receives the interrupt through external interrupt pin or HT controller interrupt and interrupts a processor core through interrupt route.

+
+
+

The address space of the bridge interrupt controller is 4KB, and the starting address (internal space of the bridge) is configured by the BIOS.

+
+
+

5.1. Interrupt Source Assignment

+
+

The internal devices of the bridge chip are connected to the interrupt controller via interrupt lines. The interrupt pin assignment of the interrupt controller is shown in the follow Table. AC97 controller and HDA controller share one interrupt pin, GPIO0-3 share one interrupt pin, and other GPIOs share one interrupt pin.

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 63. Bridge chip interrupt controller interrupt source assignment
Interrupt PinsInterrupt SourceInterrupt PinsInterrupt Source

0

-

32

pcie_f0_0

1

-

33

pcie_f0_1

2

-

34

pcie_f0_2

3

-

35

pcie_f0_3

4

-

36

pcie_f1_0

5

-

37

pcie_f1_1

6

-

38

pcie_h_lo

7

-

39

pcie_h_hi

8

uart[3:0]

40

pcie_g0_lo

9

i2c[5:0]

41

pcie_g0_hi

10

-

42

pcie_g1_lo

11

-

43

pcie_g1_hi

12

gmac0_sbd

44

toy[0]

13

gmac0_pmt

45

toy[1]

14

gmac1_sbd

46

toy[2]

15

gmac1_pmt

47

acpi_int

16

sata[0]

48

usb_0_ehci

17

sata[1]

49

usb_0_ohci

18

sata[2]

50

usb_1_ehci

19

lpc

51

usb_1_ohci

20

-

52

rtc[0]

21

-

53

rtc[1]

22

-

54

rtc[2]

23

-

55

hpet_int

24

pwm[0]

56

ac97_dma[0]

25

pwm[1]

57

ac97_dma[1]

26

pwm[2]

58

ac97/hda

27

pwm[3]

59

gpio_hi

28

dc

60

gpio[0]

29

gpu

61

gpio[1]

30

gmem

62

gpio[2]

31

thsens

63

gpio[3]

+
+
+ +
+

The bridge chip’s interrupt controller has a set of control and status registers for each interrupt source.

+
+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 64. Interrupt control and status registers
Register NameLengthRead/WriteDescriptionDefault Value

INT_MASK

1

R/W

Interrupt Mask Register.

+

0: Enable the interrupt.

+

1: Mask this interrupt.

1

HTMSI_EN

1

R/W

HT packet interrupt enable register.

+

0: Turn off the HT message packet mode.

+

1: Enable the HT message packet mode.

0

INTEDGE

1

R/W

Trigger mode setting register.

+

0: Level-triggered interrupt.

+

1: Edge-triggered interrupt.

0

INTCLR

1

WO

Edge-triggered interrupt clear register.

+

Write 1 clears the interrupt, write 0 has no effect.

N/A

AUTO_CTRL0

1

R/W

Interrupt distribution mode control register (used in conjunction with AUTO_CTRL1).

+

{AUTO_CTRL1, AUTO_CTRL0}.

+

00b: fixed distribution mode.

+

01b: rotating distribution mode.

+

10b: idle distribution mode.

+

11b: Busy distribution mode.

0

AUTO_CTRL1

1

R/W

Interrupt distribution mode control register (used in conjunction with AUTO_CTRL0).

+

{AUTO_CTRL1, AUTO_CTRL0}.

+

00b: fixed distribution mode.

+

01b: rotating distribution mode.

+

10b: idle distribution mode.

+

11b: Busy distribution mode.

0

ROUTE_ENTRY

8

R/W

Interrupt Routing Register.

+

Used to configure which processor to route this interrupt to. This register is organized in the form of a bitmap.

+

Bit0: Routed to INTn0/HT controller lo; bit1: Routed to INTn1/HT controller hi. bit7:2: Reserved.

01b

HTMSI_VECTOR

8

R/W

HT message packet interrupt vector register.

See below

INTISR_CHIP0

1

RO

Routing to the interrupt status (in service) register of INTn0.

+

0: no interrupts.

+

1: with interrupts.

0

INTISR_CHIP1

1

RO

Routing to INTn1’s interrupt status (in service) register.

+

0: no interrupts.

+

1: with interrupts.

0

INTIRR

1

RO

Interrupt request register.

+

0: no interrupt request.

+

1: Interrupt request is available.

0

INTISR

1

RO

Interrupt status (in service) register.

+

0: no interrupt is being received.

+

1: There are interrupts being received.

0

INT_POLARITY

1

R/W

Interrupt level trigger polarity selection register. For the level trigger type.

+

0: High level trigger.

+

1: Low level trigger.

0

+
+

The address distribution of the registers related to the interrupt controller is shown in the following table

+
+
+

Interrupt register address distribution

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 65. Interrupt register address distribution
Register NameAddress OffsetRead/WriteDescription

INT_ID

0x000

RO

Interrupt controller identification register

INT_MASK

0x020

R/W

Interrupt Mask Register

HTMSI_EN

0x040

R/W

HT message packet interrupt enable register

INTEDGE

0x060

R/W

Trigger mode setting register

INTCLR

0x080

WO

Edge-triggered interrupt clear register

AUTO_CTRL0

0x0c0

R/W

Interrupt distribution mode control register 0

AUTO_CTRL1

0x0e0

R/W

Interrupt distribution mode control register 1

ROUTE_ENTRY_0

0x100

R/W

Interrupt routing register [ 7- 0]

ROUTE_ENTRY_8

0x108

R/W

Interrupt routing register [15- 8]

ROUTE_ENTRY_16

0x110

R/W

Interrupt Routing Register [23-16]

ROUTE_ENTRY_24

0x118

R/W

Interrupt Routing Register [31-24]

ROUTE_ENTRY_32

0x120

R/W

Interrupt routing register [39-32]

ROUTE_ENTRY_40

0x128

R/W

Interrupt Routing Register [47-40]

ROUTE_ENTRY_48

0x130

R/W

Interrupt Routing Register [55-48]

ROUTE_ENTRY_56

0x138

R/W

Interrupt Routing Register [63-56]

HTMSI_VECTOR0

0x200

R/W

HT Interrupt Vector Register [ 7- 0]

HTMSI_VECTOR8

0x208

R/W

HT Interrupt Vector Register [15- 8]

HTMSI_VECTOR16

0x210

R/W

HT Interrupt Vector Register [23-16]

HTMSI_VECTOR24

0x218

R/W

HT Interrupt Vector Register [31-24]

HTMSI_VECTOR32

0x220

R/W

HT Interrupt Vector Register [39-32]

HTMSI_VECTOR40

0x228

R/W

HT Interrupt Vector Register [47-40]

HTMSI_VECTOR48

0x230

R/W

HT Interrupt Vector Register [55-48]

HTMSI_VECTOR56

0x238

R/W

HT Interrupt Vector Register [63-56]

INTISR_0

0x300

RO

Interrupt status (in service) register routed to INTn0

INTISR_1

0x320

RO

Interrupt status (in service) register routed to INTn1

INTIRR

0x380

RO

Interrupt request register

INTISR

0x3a0

RO

Interrupt Status (In Service) Register

INT_POLARITY

0x3e0

R/W

Interrupt trigger level selection register

+
+

Interrupt controller identification register

+
+
+

Address Offset: 000-003h

+
+
+

Attribute: RO

+
+
+

Default value: 07000000h +Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + +
Table 66. Interrupt controller identification register 1
Bit FieldNameRead/WriteDescription

31:24

id

RO

Interrupt Controller ID

23:0

Reserved

RO

Reserved

+
+

Address Offset: 004-007h

+
+
+

Attribute: RO

+
+
+

Default value: 003F0001h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 67. Interrupt controller identification register 2
Bit FieldNameRead/WriteDescription

31:24

Reserved

RO

Reserved

23:16

int_num

RO

The number of interrupt sources supported. The actual number of interrupts is equal to the value of this field plus 1.

15:8

Reserved

RO

Reserved

7:0

version

RO

Interrupt controller version number

+
+

Interrupt mask register

+
+
+

Address Offset: 020-023h

+
+
+

Attribute: R/W

+
+
+

Default value: FFFFFFFFh

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + +
Table 68. Interrupt mask register 1
Bit FieldNameRead/WriteDescription

31:0

int_mask

R/W

Low 32 bits of the interrupt mask register (bit[31:0])

+
+

Address Offset: 024-027h

+
+
+

Default value: FFFFFFFFh

+
+
+

Attribute: R/W

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + +
Table 69. Interrupt mask register 2
Bit FieldNameRead/WriteDescription

31:0

int_mask

R/W

High 32 bits of the interrupt mask register (bit[63:32])

+
+

HT interrupt message packet enable register

+
+
+

Address Offset: 040-043h

+
+
+

Default value: 00000000h

+
+
+

Attribute: R/W

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + +
Table 70. HT interrupt message packet enable register 1
Bit FieldNameRead/WriteDescription

31:0

htmsi_en

R/W

Low 32 bits (bit[31:0]) of the HT Interrupt Message Packet Enable Register

+
+

Address Offset: 044-047h

+
+
+

Default value: 00000000h

+
+
+

Attribute: R/W

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + +
Table 71. HT interrupt message packet enable register 2
Bit FieldNameRead/WriteDescription

31:0

htmsi_en

R/W

High 32 bits (bit[63:32]) of the HT Interrupt Message Packet Enable Register

+
+

Interrupt trigger control register

+
+
+

Address Offset: 060-063h

+
+
+

Attribute: R/W

+
+
+

Default value: 00000000h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + +
Table 72. Interrupt trigger control register 1
Bit FieldNameRead/WriteDescription

31:0

int_edge

R/W

Low 32 bits of the interrupt trigger control register (bit[31:0])

+
+

Address Offset: 064-067h

+
+
+

Attribute: R/W

+
+
+

Default value: 00000000h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + +
Table 73. Interrupt trigger control register 2
Bit FieldNameRead/WriteDescription

31:0

int_edge

R/W

High 32 bits of the interrupt trigger control register (bit[63:32])

+
+

Interrupt clear register

+
+
+

Address Offset: 080-083h

+
+
+

Attribute: WO

+
+
+

Default value: N/A

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + +
Table 74. Interrupt clear register 1
Bit FieldNameRead/WriteDescription

31:0

int_clear

WO

Low 32 bits of the interrupt clear register (bit`[31:0]`)

+
+

Address Offset: 084-087h

+
+
+

Attribute: WO

+
+
+

Default value: 00000000h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + +
Table 75. Interrupt clear register 2
Bit FieldNameRead/WriteDescription

31:0

int_clear

WO

High 32 bits of the interrupt clear register (bit`[63:32]`)

+
+

INT_AUTO_CTRL0 register

+
+
+

Address Offset: 0C0-0C3h

+
+
+

Attribute: R/W

+
+
+

Default value: 00000000h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + +
Table 76. INT_AUTO_CTRL0 register 1
Bit FieldNameRead/WriteDescription

31:0

int_auto_ctrl0

R/W

Low 32 bits (bit`[31:0]) of Interrupt Smart Distribution Control Register `0

+
+

Address Offset: 0C4-0C7h

+
+
+

Default value: 00000000h

+
+
+

Attribute: R/W

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + +
Table 77. INT_AUTO_CTRL0 register 2
Bit FieldNameRead/WriteDescription

31:0

int_auto_ctrl0

R/W

High 32 bits (bit`[63:32]) of Interrupt Smart Distribution Control Register `0

+
+

INT_AUTO_CTRL1 register

+
+
+

Address Offset: 0E0-0E3h

+
+
+

Default value: 00000000h

+
+
+

Attribute: R/W

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + +
Table 78. INT_AUTO_CTRL1 register 1
Bit FieldNameRead/WriteDescription

31:0

int_auto_ctrl1

R/W

Low 32 bits (bit[31:0]) of Interrupt Smart Distribution Control Register 1

+
+

Address Offset: 0E4-0E7h

+
+
+

Default value: 00000000h

+
+
+

Attribute: R/W

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + +
Table 79. INT_AUTO_CTRL1 register 2
Bit FieldNameRead/WriteDescription

31:0

int_auto_ctrl1

R/W

High 32 bits (bit`[63:32]) of Interrupt Smart Distribution Control Register `1

+
+

Interrupt routing configuration register

+
+
+

Address Offset: 100-103h

+
+
+

Attribute: R/W

+
+
+

Default value: 01010101h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + +
Table 80. Interrupt routing configuration register 1
Bit FieldNameRead/WriteDescription

31:0

Reserved

R/W

Reserved

+
+

Address Offset: 104-107h

+
+
+

Default value: 01010101h

+
+
+

Attribute: R/W

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + +
Table 81. Interrupt routing configuration register 2
Bit FieldNameRead/WriteDescription

31:0

Reserved

R/W

Reserved

+
+

Address Offset: 108-10Bh

+
+
+

Default value: 01010101h

+
+
+

Attribute: R/W

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 82. Interrupt routing configuration register 3
Bit FieldNameRead/WriteDescription

31:16

Reserved

R/W

Reserved

9:8

i2c_int_route

R/W

I2C Interrupt Routing Configuration Register

1:0

uart_int_route

R/W

UART Interrupt Routing Configuration Register

+
+

Address Offset: 10C-10Fh

+
+
+

Attribute: R/W

+
+
+

Default value: 01010101h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 83. Interrupt routing configuration register 4
Bit FieldNameRead/WriteDescription

25:24

gmac1_pmt_int_route

R/W

GMAC1_PMT Interrupt Routing Configuration Register

17:16

gmac1_sbd_int_route

R/W

GMAC1_SBD Interrupt Routing Configuration Register

9:8

gmac0_pmt_int_route

R/W

GMAC0_PMT Interrupt Routing Configuration Register

1:0

gmac0_sbd_int_route

R/W

GMAC0_SBD Interrupt Routing Configuration Register

+
+

Address Offset: 110-113h

+
+
+

Attribute: R/W

+
+
+

Default value: 01010101h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 84. Interrupt routing configuration register 5
Bit FieldNameRead/WriteDescription

25:24

lpc_int_route

R/W

LPC Interrupt Routing Configuration Register

17:16

SATA2_int_route

R/W

SATA2 Interrupt Routing Configuration Register

9:8

SATA1_int_route

R/W

SATA1 Interrupt Routing Configuration Register

1:0

SATA0_int_route

R/W

SATA0 Interrupt Routing Configuration Register

+
+

Address Offset: 114-117h

+
+
+

Attribute: R/W

+
+
+

Default value: 01010101h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + +
Table 85. Interrupt routing configuration register 6
Bit FieldNameRead/WriteDescription

31:0

Reserved

R/W

Reserved

+
+

Address Offset: 118-11Bh

+
+
+

Attribute: R/W

+
+
+

Default value: 01010101h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 86. Interrupt routing configuration register 7
Bit FieldNameRead/WriteDescription

25:24

pwm3_int_route

R/W

PWM3 Interrupt Routing Configuration Register

17:16

pwm2_int_route

R/W

PWM2 Interrupt Routing Configuration Register

9:8

pwm1_int_route

R/W

PWM1 Interrupt Routing Configuration Register

1:0

pwm0_int_route

R/W

PWM0 Interrupt Routing Configuration Register

+
+

Address Offset: 11C-11Fh

+
+
+

Attribute: R/W

+
+
+

Default value: 01010101h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 87. Interrupt routing configuration register 8
Bit FieldNameRead/WriteDescription

25:24

thsens_int_route

R/W

Thsensor Interrupt Routing Configuration Register

17:16

gpu_int_route

R/W

GPU Interrupt Routing Configuration Register

9:8

gmem_int_route

R/W

GMEM Interrupt Routing Configuration Register

1:0

dc_int_route

R/W

DC Interrupt Routing Configuration Register

+
+

Address Offset: 120-123h

+
+
+

Attribute: R/W

+
+
+

Default value: 01010101h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 88. Interrupt routing configuration register 9
Bit FieldNameRead/WriteDescription

25:24

pcie_f0_p3_int_route

R/W

PCIE_F0 Controller 3 Interrupt Routing Configuration Register

17:16

pcie_f0_p2_int_route

R/W

PCIE_F0 Controller 2 Interrupt Routing Configuration Register

9:8

pcie_f0_p1_int_route

R/W

PCIE_F0 Controller 1 Interrupt Routing Configuration Register

1:0

pcie_f0_p0_int_route

R/W

PCIE_F0 Controller 0 Interrupt Routing Configuration Register

+
+

Address Offset: 124-127h

+
+
+

Attribute: R/W

+
+
+

Default value: 01010101h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 89. Interrupt routing configuration register 10
Bit FieldNameRead/WriteDescription

25:24

pcie_h_p1_int_route

R/W

PCIE_H Controller 1 Interrupt Routing Configuration Register

17:16

pcie_h_p0_int_route

R/W

PCIE_H Controller 0 Interrupt Routing Configuration Register

9:8

pcie_f1_p1_int_route

R/W

PCIE_F1 Controller 1 Interrupt Routing Configuration Register

1:0

pcie_f1_p0_int_route

R/W

PCIE_F1 Controller 0 Interrupt Routing Configuration Register

+
+

Address Offset: 128-12Bh

+
+
+

Attribute: R/W

+
+
+

Default value: 01010101h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 90. Interrupt routing configuration register 11
Bit FieldNameRead/WriteDescription

25:24

pcie_g1_p1_int_route

R/W

PCIE_G1 Controller 1 Interrupt Routing Configuration Register

17:16

pcie_g1_p0_int_route

R/W

PCIE_G1 Controller 0 Interrupt Routing Configuration Register

9:8

pcie_g0_p1_int_route

R/W

PCIE_G0 Controller 1 Interrupt Routing Configuration Register

1:0

pcie_g0_p0_int_route

R/W

PCIE_G0 Controller 0 Interrupt Routing Configuration Register

+
+

Address Offset: 12C-12Fh

+
+
+

Attribute: R/W

+
+
+

Default value: 01010101h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 91. Interrupt routing configuration register 12
Bit FieldNameRead/WriteDescription

25:24

acpi_int_route

R/W

ACPI Interrupt Routing Configuration Register

17:16

toy2_int_route

R/W

TOY2 Interrupt Routing Configuration Register

9:8

toy1_int_route

R/W

TOY1 Interrupt Routing Configuration Register

1:0

toy0_int_route

R/W

TOY0 Interrupt Routing Configuration Register

+
+

Address Offset: 130-133h

+
+
+

Attribute: R/W

+
+
+

Default value: 01010101h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 92. Interrupt routing configuration register 13
Bit FieldNameRead/WriteDescription

25:24

usb1_ohci_int_route

R/W

USB1 OHCI Controller Interrupt Routing Configuration Register

17:16

usb1_ehci_p2_int_route

R/W

USB1 EHCI Controller Interrupt Routing Configuration Register

9:8

usb0_ohci_int_route

R/W

USB0 OHCI Controller Interrupt Routing Configuration Register

1:0

usb0_ehci_int_route

R/W

USB0 EHCI Controller Interrupt Routing Configuration Register

+
+

Address Offset: 134-137h

+
+
+

Attribute: R/W

+
+
+

Default value: 01010101h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 93. Interrupt routing configuration register 14
Bit FieldNameRead/WriteDescription

25:24

hpet_int_route

R/W

HPET Interrupt Routing Configuration Register

17:16

rtc2_int_route

R/W

RTC2 Interrupt Routing Configuration Register

9:8

rtc1_int_route

R/W

RTC1 Interrupt Routing Configuration Register

1:0

rtc0_int_route

R/W

RTC0 Interrupt Routing Configuration Register

+
+

Address Offset: 138-13Bh

+
+
+

Attribute: R/W

+
+
+

Default value: 01010101h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 94. Interrupt routing configuration register 15
Bit FieldNameRead/WriteDescription

25:24

gpio_hi_int_route

R/W

GPIO high bit (bit[56:4]) interrupt routing configuration register

17:16

ac97/hda_int_route

R/W

AC97/HDA controller interrupt routing configuration register

9:8

ac97_dma1_int_route

R/W

AC97 DMA1 Interrupt Routing Configuration Register

1:0

ac97_dma0_int_route

R/W

AC97 DMA0 Interrupt Routing Configuration Register

+
+

Address Offset: 13C-13Fh

+
+
+

Attribute: R/W

+
+
+

Default value: 01010101h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 95. Interrupt routing configuration register 16
Bit FieldNameRead/WriteDescription

25:24

gpio3_int_route

R/W

GPIO3 Interrupt Routing Configuration Register

17:16

gpio2_int_route

R/W

GPIO2 Interrupt Routing Configuration Register

9:8

gpio1_int_route

R/W

GPIO1 Interrupt Routing Configuration Register

1:0

gpio0_int_route

R/W

GPIO0 Interrupt Routing Configuration Register

+
+

HT message packet interrupt vector configuration register

+
+
+

Address Offset: 200-203h

+
+
+

Attribute: R/W

+
+
+

Default value: 03020100h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + +
Table 96. HT message packet interrupt vector configuration register 1
Bit FieldNameRead/WriteDescription

31:0

Reserved

R/W

Reserved

+
+

Address Offset: 204-207h

+
+
+

Attribute: R/W

+
+
+

Default value: 070605040h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + +
Table 97. HT message packet interrupt vector configuration register 2
Bit FieldNameRead/WriteDescription

31:0

Reserved

R/W

Reserved

+
+

Address Offset: 208-20Bh

+
+
+

Attribute: R/W

+
+
+

Default value: 0B0A0908h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 98. HT message packet interrupt vector configuration register 3
Bit FieldNameRead/WriteDescription

31:16

Reserved

R/W

Reserved

15:8

i2c_int_route

R/W

I2C HT Interrupt Vector Configuration Register

7:0

uart_int_route

R/W

UART HT interrupt vector configuration register

+
+

Address Offset: 20C-20Fh

+
+
+

Attribute: R/W

+
+
+

Default value: 0E0F0D0Ch

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 99. HT message packet interrupt vector configuration register 4
Bit FieldNameRead/WriteDescription

31:24

gmac1_pmt_int_route

R/W

GMAC1_PMT HT Interrupt Vector Configuration Register

23:16

gmac1_sbd_int_route

R/W

GMAC1_SBD HT Interrupt Vector Configuration Register

15:8

gmac0_pmt_int_route

R/W

GMAC0_PMT HT Interrupt Vector Configuration Register

7:0

gmac0_sbd_int_route

R/W

GMAC0_SBD HT Interrupt Vector Configuration Register

+
+

Address Offset: 210-213h

+
+
+

Attribute: R/W

+
+
+

Default value: 13121110h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 100. HT message packet interrupt vector configuration register 5
Bit FieldNameRead/WriteDescription

31:24

lpc_int_route

R/W

LPC HT Interrupt Vector Configuration Register

23:16

SATA2_int_route

R/W

SATA2 HT Interrupt Vector Configuration Register

15:8

SATA1_int_route

R/W

SATA1 HT Interrupt Vector Configuration Register

7:0

SATA0_int_route

R/W

SATA0 HT Interrupt Vector Configuration Register

+
+

Address Offset: 214-217h

+
+
+

Attribute: R/W

+
+
+

Default value: 17161514h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + +
Table 101. HT message packet interrupt vector configuration register 6
Bit FieldNameRead/WriteDescription

31:0

Reserved

R/W

Reserved

+
+

Address Offset: 218-21Bh

+
+
+

Attribute: R/W

+
+
+

Default value: 1B1A1918h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 102. HT message packet interrupt vector configuration register 7
Bit FieldNameRead/WriteDescription

31:24

pwm3_int_route

R/W

PWM3 HT Interrupt Vector Configuration Register

23:16

pwm2_int_route

R/W

PWM2 HT Interrupt Vector Configuration Register

15:8

pwm1_int_route

R/W

PWM1 HT Interrupt Vector Configuration Register

7:0

pwm0_int_route

R/W

PWM0 HT Interrupt Vector Configuration Register

+
+

Address Offset: 21C-21Fh

+
+
+

Attribute: R/W

+
+
+

Default value: 1E1F1D1Ch

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 103. HT message packet interrupt vector configuration register 8
Bit FieldNameRead/WriteDescription

31:24

thsens_int_route

R/W

Thsensor HT Interrupt Vector Configuration Register

23:16

gpu_int_route

R/W

GPU HT Interrupt Vector Configuration Register

15:8

gmem_int_route

R/W

GMEM HT Interrupt Vector Configuration Register

7:0

dc_int_route

R/W

DC HT Interrupt Vector Configuration Register

+
+

Address Offset: 220-223h

+
+
+

Attribute: R/W

+
+
+

Default value: 43424140h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 104. HT message packet interrupt vector configuration register 9
Bit FieldNameRead/WriteDescription

31:24

pcie_f0_p3_int_route

R/W

PCIE_F0 Controller 3 HT Interrupt Vector Configuration Register

23:16

pcie_f0_p2_int_route

R/W

PCIE_F0 Controller 2 HT Interrupt Vector Configuration Register

15:8

pcie_f0_p1_int_route

R/W

PCIE_F0 Controller 1 HT Interrupt Vector Configuration Register

7:0

pcie_f0_p0_int_route

R/W

PCIE_F0 Controller 0 HT Interrupt Vector Configuration Register

+
+

Address Offset: 224-227h

+
+
+

Attribute: R/W

+
+
+

Default value: 47464544h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 105. HT message packet interrupt vector configuration register 10
Bit FieldNameRead/WriteDescription

31:24

pcie_h_p1_int_route

R/W

PCIE_H Controller 1 HT Interrupt Vector Configuration Register

23:16

pcie_h_p0_int_route

R/W

PCIE_H Controller 0 HT Interrupt Vector Configuration Register

15:8

pcie_f1_p1_int_route

R/W

PCIE_F1 Controller 1 HT Interrupt Vector Configuration Register

7:0

pcie_f1_p0_int_route

R/W

PCIE_F1 Controller 0 HT Interrupt Vector Configuration Register

+
+

Address Offset: 228-22Bh

+
+
+

Attribute: R/W

+
+
+

Default value: 4B4A4948h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 106. HT message packet interrupt vector configuration register 11
Bit FieldNameRead/WriteDescription

31:24

pcie_g1_p1_int_route

R/W

PCIE_G1 Controller 1 HT Interrupt Vector Configuration Register

23:16

pcie_g1_p0_int_route

R/W

PCIE_G1 Controller 0 HT Interrupt Vector Configuration Register

15:8

pcie_g0_p1_int_route

R/W

PCIE_G0 Controller 1 HT Interrupt Vector Configuration Register

7:0

pcie_g0_p0_int_route

R/W

PCIE_G0 Controller 0 HT Interrupt Vector Configuration Register

+
+

Address Offset: 22C-22Fh

+
+
+

Attribute: R/W

+
+
+

Default value: 4F4E4D4Ch

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 107. HT message packet interrupt vector configuration register 12
Bit FieldNameRead/WriteDescription

31:24

acpi_int_route

R/W

ACPI HT Interrupt Vector Configuration Register

23:16

toy2_int_route

R/W

TOY2 HT Interrupt Vector Configuration Register

15:8

toy1_int_route

R/W

TOY1 HT Interrupt Vector Configuration Register

7:0

toy0_int_route

R/W

TOY0 HT Interrupt vector configuration register

+
+

Address Offset: 230-233h

+
+
+

Attribute: R/W

+
+
+

Default value: 53525150h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 108. HT message packet interrupt vector configuration register 13
Bit FieldNameRead/WriteDescription

31:24

usb1_ohci_int_route

R/W

USB1 OHCI Controller HT Interrupt Vector Configuration Register

23:16

usb1_ehci_p2_int_route

R/W

USB1 EHCI Controller HT Interrupt Vector Configuration Register

15:8

usb0_ohci_int_route

R/W

USB0 OHCI Controller HT Interrupt Vector Configuration Register

7:0

usb0_ehci_int_route

R/W

USB0 EHCI Controller HT Interrupt Vector Configuration Register

+
+

Address Offset: 234-237h

+
+
+

Attribute: R/W

+
+
+

Default value: 57565554h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 109. HT message packet interrupt vector configuration register 14
Bit FieldNameRead/WriteDescription

31:24

hpet_int_route

R/W

HPET HT Interrupt Vector Configuration Register

23:16

rtc2_int_route

R/W

RTC2 HT Interrupt Vector Configuration Register

15:8

rtc1_int_route

R/W

RTC1 HT Interrupt Vector Configuration Register

7:0

rtc0_int_route

R/W

RTC0 HT Interrupt Vector Configuration Register

+
+

Address Offset: 238-23Bh

+
+
+

Attribute: R/W

+
+
+

Default value: 5B5A5958h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 110. HT message packet interrupt vector configuration register 15
Bit FieldNameRead/WriteDescription

31:24

gpio_hi_int_route

R/W

GPIO high bit (bit[56:4]) HT interrupt vector configuration register

23:16

ac97/hda_int_route

R/W

AC97/HDA Controller HT Interrupt Vector Configuration Register

15:8

ac97_dma1_int_route

R/W

AC97 DMA1 HT Interrupt vector configuration register

7:0

ac97_dma0_int_route

R/W

AC97 DMA0 HT Interrupt vector configuration register

+
+

Address Offset: 23C-23Fh

+
+
+

Attribute: R/W

+
+
+

Default value: 5F5E5D5Ch

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 111. HT message packet interrupt vector configuration register 16
Bit FieldNameRead/WriteDescription

31:24

gpio3_int_route

R/W

GPIO3 HT Interrupt Vector Configuration Register

23:16

gpio2_int_route

R/W

GPIO2 HT Interrupt Vector Configuration Register

15:8

gpio1_int_route

R/W

GPIO1 HT Interrupt Vector Configuration Register

7:0

gpio0_int_route

R/W

GPIO0 HT Interrupt Vector Configuration Register

+
+

Interrupts routed to INTn0 are in the Service Status Register

+
+
+

Address Offset: 300-303h

+
+
+

Attribute: RO

+
+
+

Default value: 00000000h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + +
Table 112. HT message packet interrupt vector configuration register 17
Bit FieldNameRead/WriteDescription

31:0

int_isr_0

R/W

Interrupts routed to INTn0 are in the lower 32 bits of the Service Status Register (bit`[31:0]`)

+
+

Address Offset: 304-307h

+
+
+

Attribute: RO

+
+
+

Default value: 00000000h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + +
Table 113. HT message packet interrupt vector configuration register 18
Bit FieldNameRead/WriteDescription

31:0

int_isr_0

R/W

The interrupt routed to INTn0 is in the high 32 bits of the service status register (bit`[63:32]`)

+
+

Interrupts routed to INTn1 are in the service status segiste

+
+
+

Address Offset: 320-323h

+
+
+

Attribute: RO

+
+
+

Default value: 00000000h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + +
Table 114. Interrupts routed to INTn1 are in the service status segister 1
Bit FieldNameRead/WriteDescription

31:0

int_isr_1

R/W

Interrupts routed to INTn1 are in the lower 32 bits of the service status register (bit`[31:0]`)

+
+

Address Offset: 324-327h

+
+
+

Attribute: RO

+
+
+

Default value: 00000000h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + +
Table 115. Interrupts routed to INTn1 are in the service status segister 2
Bit FieldNameRead/WriteDescription

31:0

int_isr_1

R/W

The interrupt routed to INTn1 is in the high 32 bits of the service status register (bit`[63:32]`)

+
+

Interrupt request register

+
+
+

Address Offset: 380-383h

+
+
+

Attribute: RO

+
+
+

Default value: 00000000h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + +
Table 116. Interrupt request register 1
Bit FieldNameRead/WriteDescription

31:0

int_irr

R/W

Low 32 bits of the interrupt request register (bit`[31:0]`)

+
+

Address Offset: 384-387h

+
+
+

Attribute: R/W

+
+
+

Default value: 00000000h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + +
Table 117. Interrupt request register 2
Bit FieldNameRead/WriteDescription

31:0

int_irr

R/W

High 32 bits of the interrupt request register (bit`[63:32]`)

+
+

Interrupt in service status register

+
+
+

Address Offset: 3A0-3A3h

+
+
+

Attribute: RO

+
+
+

Default value: 00000000h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + +
Table 118. Interrupt in service status register 1
Bit FieldNameRead/WriteDescription

31:0

int_isr

R/W

Interrupt in the lower 32 bits of the service status register (bit`[31:0]`)

+
+

Address Offset: 3A4-3A7h

+
+
+

Attribute: R/W

+
+
+

Default value: 00000000h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + +
Table 119. Interrupt in service status register 2
Bit FieldNameRead/WriteDescription

31:0

int_isr

R/W

Interrupt in the high 32 bits of the service status register (bit`[63:32]`)

+
+

Interrupt level trigger polarity register

+
+
+

Address Offset: 3E0-3E3h

+
+
+

Attribute: R/W

+
+
+

Default value: 00000000h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + +
Table 120. Interrupt level trigger polarity register 1
Bit FieldNameRead/WriteDescription

31:0

int_polarity

R/W

Low 32 bits of the interrupt level trigger polarity register (bit`[31:0]`)

+
+

Address Offset: 3E4-3E7h

+
+
+

Attribute: R/W

+
+
+

Default value: 00000000h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + +
Table 121. Interrupt level trigger polarity register 2
Bit FieldNameRead/WriteDescription

31:0

int_polarity

R/W

High 32 bits of the interrupt level trigger +polarity register (bit`[63:32]`)

+
+
+

5.3. Device Interrupt Types

+
+

For the bridge chip, AC97 DMA interrupts are edge triggered, gpio interrupts can be configured to be level triggered or edge triggered as needed, and the rest of the interrupts are level triggered and active high.

+
+
+

For PCIE devices, one way is to use the interrupt line of the PCIE controller inside the bridge to transmit the interrupt; +the other way is to use the MSI interrupt of the PCIE device directly.

+
+
+

In the PCIE MSI interrupt method, when the PCIE controller inside the bridge receives an MSI interrupt, it converts it directly into an HT interrupt message packet to send to the HT controller. +Therefore, the software needs to be careful to distinguish the MSI interrupt vector of the PCIE device from the HT interrupt vector configured by the internal device of the bridge.

+
+
+
+

5.4. Interrupt Distribution Modes

+
+

The bridge supports dual interrupt outputs, so that different interrupt sources or multiple interrupts from the same interrupt source can be distributed between the two interrupt outputs. +The bridge chip supports interrupt hardware load balancing, which allows interrupts to be distributed between the two outputs preset by software in four modes.:

+
+
+
    +
  1. +

    Fixed distribution mode - Distribution is done according to the routing method configured in the interrupt routing configuration register. +In this mode, the routing configuration register must be one-hot encoded, meaning that an interrupt can only be routed to one interrupt output.

    +
    2. +
  2. +

    Rotating distribution mode - In this mode, each new interrupt generated is routed to the next valid interrupt output according to the route vector configuration in the Route_Entry register. +The route to the next valid interrupt output is configured in the Route_Entry register.

    +
    3. +
  3. +

    Idle distribution mode - jumps to an idle interrupt output. +In this mode, when each new interrupt is generated, it first detects if there is already an unprocessed interrupt on the next interrupt output according to the routing vector configuration in the Entry register, and if not, it is routed to that interrupt output; +if there is already an unprocessed interrupt on the next interrupt output, it continues to detect the next processor core.

    +
    4. +
  4. +

    Busy distribution mode - the current interrupt output is busy then jumps to its left (0→1→2→3) candidate interrupt output. +When each new interrupt is generated in this mode, it first detects whether there is already an unprocessed interrupt on the interrupt output of the last interrupt, and if not, continues to interrupt that interrupt output, and if there is an unprocessed interrupt, it is routed to the next interrupt output as configured in the Entry register. +It should be noted that once AUTO_CTRL0/1 has been configured, it should not be modified in the middle of the run. It is recommended that the software use fixed distribution mode.

    +
    5. +
+
+
+
+

5.5. Detailed Description of Interrupt Handling Process

+
+

In the interrupt line interrupt mode, the interrupt controller of the bridge chip receives the device interrupt and sets the corresponding interrupt output pin low according to the interrupt routing configuration. +The processor receives the interrupt through the interrupt input pin, and the processor obtains the current interrupt source routed to itself by reading the corresponding ISR (interrupt in service register) register within the bridge chip interrupt controller. +The interrupt processing process is:

+
+
+
    +
  1. +

    The interrupt controller of the bridge receives the device interrupt; (hardware)

    +
    2. +
  2. +

    The interrupt controller of the bridge chip sets the interrupt output pin low; (hardware)

    +
    3. +
  3. +

    The processor’s interrupt controller receives the interrupt pin interrupt; (hardware)

    +
    4. +
  4. +

    The processor turns off the interrupt. (software)

    +
    5. +
  5. +

    The processor reads its own interrupt controller and learns that it is an external interrupt; (software)

    +
    6. +
  6. +

    The processor reads the interrupt controller of the bridge chip to get the interrupt vector; (software)

    +
    7. +
  7. +

    The processor writes the interrupt controller of the bridge chip to mask the corresponding interrupt source; (software)

    +
    8. +
  8. +

    The processor opens the interrupt. (software)

    +
    9. +
  9. +

    The processor calls the interrupt service program to handle the interrupt; (software)

    +
    10. +
  10. +

    The processor writes the bridge chip’s interrupt controller to clear edge-triggered interrupts; (software)

    +
    11. +
  11. +

    The processor writes the bridge chip’s interrupt controller to turn on the corresponding interrupt source. (Software)

    +
    12. +
  12. +

    The processor interrupt returns. (Software)

    +
    13. +
+
+
+

In the HT message packet interrupt method, the interrupt controller and PCIE controller of the bridge receive the device interrupt and can send the interrupt vector directly to the HT controller of the processor, thus avoiding the process of the processor querying the internal interrupt vector of the bridge. The interrupt processing process is as follows.

+
+
+
    +
  1. +

    The interrupt controller of the bridge receives the device interrupt; (hardware)

    +
    2. +
  2. +

    The interrupt controller of the bridge slices sends the interrupt vector to the HT controller of the processor; (hardware)

    +
    3. +
  3. +

    The processor’s interrupt controller receives the HT interrupt; (hardware)

    +
    4. +
  4. +

    The processor turns off the interrupt. (software) 5.

    +
    5. +
  5. +

    The processor reads its own interrupt controller and learns that it is an HT interrupt; (software)

    +
    6. +
  6. +

    The processor reads its own HT controller to get the interrupt vector; (software)

    +
    7. +
  7. +

    The processor writes its own HT controller to clear the interrupt; (software)

    +
    8. +
  8. +

    The processor opens the interrupt. (software) 9.

    +
    9. +
  9. +

    The processor calls the interrupt service program to handle the interrupt; (software)

    +
    10. +
  10. +

    The processor writes the bridge chip’s interrupt controller to clear the interrupt (not required if it is an MSI interrupt issued by a PCIE device). (software)

    +
    11. +
  11. +

    The processor interrupt returns. (Software)

    +
    12. +
+
+
+

The software can configure the HT interrupt vector corresponding to the internal devices of the bridge chip.

+
+
+
+
+
+

6. HPET Controller

+
+
+

The HPET controller is compatible with standard specifications. Internally, it includes a 64-bit main counter and three 32-bit timers (comparators). Of the three timers, timer 0 supports both periodic-capable and non-periodic interrupts, while timers 1 and 2 support only non-periodic interrupts.

+
+
+

6.1. Access Address

+
+

The address space size of the HPET controller is 4KB, and the starting address (internal space of the bridge chip) is configured by the BIOS. +The physical address composition of the internal registers of the HPET controller is as follows:

+
+ + +++++ + + + + + + + + + + + + + + + + + + + +
Table 122. Access address
Address bitsCompositionRemarks

[11:08]

0

Reserved

[07:00]

REG

Internal register address

+
+

Note: The HPET controller only supports 4-byte accesses. Software that needs to use the HPET’s 64-bit master counter as a timestamp needs to be careful to handle the data rounding introduced by reading the high and low 32-bit values in two separate readings.

+
+
+
+

6.2. Description of Registers

+ + ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 123. HPET register list
Register Offset AddressDescription

000-007h

General Capabilities and ID Register

008-00Fh

Reserved

010-017h

General Configuration Register

018-01Fh

Reserved

020-027h

General Interrupt Status Register

028-0EFh

Reserved

0F0-0F7h

Main Counter Value Register

100-107h

Timer 0 Configuration and Capability Register

108-10Fh

Timer 0 Comparator Value Register

110-11Fh

Reserved

120-127h

Timer 1 Configuration and Capability Register

128-12Fh

Timer 1 Comparator Value Register

130-13Fh

Reserved

140-147h

Timer 2 Configuration and Capability Register

148-14Fh

Timer 2 Comparator Value Register

150-15Fh

Reserved

+
+

General Capabilities and ID Register

+
+
+

Address Offset: 00-07h

+
+
+

Attribute: RO

+
+
+

Default value: See description

+
+
+

Size:`8`

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 124. General capabilities and id register
Bit FieldNameDescriptionRead/Write

63:32

COUNTER_CLK_PERIOD

Timing frequency of the master timer in fps (10^-15s). +Default value: 1312D00h (20ns clock period).

RO

31:16

VENDOR_ID

Manufacturer ID. value: 0014h

RO

15:14

Reserved

Reserved

RO

13

COUNT_SIZE_CAP

The width of the master timer. This chip is a 64-bit master timer. Value: 1b.

+

0: 32 bits

+

1: 64 bits

RO

12:8

NUM_TIM_CAP

Number of timers; the value of this field indicates the number of the last timer. This chip contains 3 timers.

+

This chip contains 3 timers. Value: 2h.

RO

7:0

REV_ID

Version number; value: 02h

RO

+
+

General Configuaration Register

+
+
+

Address Offset: 10-17h

+
+
+

Attribute: RO, R/W

+
+
+

Default value: 0h

+
+
+

Size:8

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + +
Table 125. General configuaration register
Bit FieldNameDescriptionRead/Write

63:1

Reserved

Reserved

RO

0

ENABLE_CNF

HPET enable control.

+

0: the main timer stops timing and all timers are no longer generating interrupts.

+

1: the main timer counts and the timers are allowed to generate interrupts.

+
+

General Interrupt Status Register

+
+
+

Address Offset: 20-27h

+
+
+

Attribute: RO, R/WC

+
+
+

Default value: 0h

+
+
+

Size:8

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 126. General interrupt status register
Bit FieldNameDescriptionRead/Write

63:3

Reserved

Reserved

RO

2

T2_INT_STS

Timer 2 interrupt status. Same function as T0_INT_STS.

R/WC

1

T1_INT_STS

Timer 1 interrupt status. Same function as T0_INT_STS.

R/WC

0

T0_INT_STS

Timer 0 interrupt state.

+

When the timer’s interrupt trigger mode is level-triggered, this timer defaults to 0. +When the corresponding timer interrupt occurs, then the hardware will set it to 1. Once set, software writing 1 to this timer will clear it. Once it is set, software writing 1 to this timer will clear this timer. Writing 0 to this timer will be meaningless. +When the interrupt triggering mode of the timer is edge triggering mode. +Software will ignore this bit. Software usually writes 0 to this bit.

R/WC

+
+

The interrupt trigger mode of each timer is determined by the Tn_TYPE_CNF bit of the respective Configuartion and Capability register.

+
+
+

Main Counter Value Register

+
+
+

Address Offset: F0-F7h

+
+
+

Attribute: R/W

+
+
+

Default value: 0h

+
+
+

Size:`8`

+
+ + ++++++ + + + + + + + + + + + + + + + + +
Table 127. Main counter value register
Bit FieldNameDescriptionRead/Write

63:0

Main_Counter

Master timer. Modifying the value of this register is only allowed when the main timer stops timing.

R/W

+
+

Timer 0 Configuration and Capabilities Registe

+
+
+

Address Offset: 100-107h

+
+
+

Attribute: RO, R/W

+
+
+

Default value: 10h

+
+
+

Size:`8`

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 128. Timer 0 configuration and capabilities registe
Bit FieldNameDescriptionRead/Write

63:9

Reserved

Reserved

RO

8

T0_32MODE_CNF

Timer 0 32-bit mode configuration. When the timer is 64-bit, the software +writes 1 to this bit to use the timer as a 32-bit. This version of the timer does not support 64-bit, and the bit is not writable.

RO

7

Reserved

Reserved

RO

6

T0_VAL_SET_CNF

Timer 0 value setting. Only timers that can generate periodic interrupts will use this field. By writing 1 to this field, software can directly modify the periodic +The software can directly modify the accumulator for the periodic period by writing 1 to this field. Software does not need to clear 0 to this field.

R/W

5

T0_SIZE_CAP

Timer 0 Width indication.

+

0: 32-bit width

+

1: 64-bit width

RO

4

T0_PER_INT_CAP

Timer 0 Periodic interrupt indication.

+

1: the timer is capable of generating periodic interrupts.

+

0: the timer is not capable of generating periodic interrupts.

RO

3

T0_TYPE_CNF

Timer 0 cycle interrupt configuration. +If the corresponding T0_PER_INT_CAP bit is 0, then this bit is read-only and defaults to 0. +If the corresponding T0_PER_INT_CAP bit is 1, then this bit is readable and writable. It is used to enable the corresponding timer to generate periodic interrupts. +1: Enable the timer to generate periodic interrupts

+

0: Enable the timer to generate non-periodic interrupts

R/W

2

T0_INT_ENB_CNF

Enable Timer 0 to generate interrupts

R/W

1

T0_INT_TYPE_CNF

Timer 0 interrupt type configuration.

+

0: The interrupt triggering mode of the timer is edge triggered; this means that the corresponding timer will generate an edge triggered interrupt. If another interrupt is generated, then another edge will be generated. +1: The interrupt trigger mode of the timer is level triggered; this means that the corresponding timer will generate a level triggered interrupt. This interrupt will remain active +until it is cleared by software (General Interrupt Status Register).

R/W

0

Reserved

Reserved

RO

+
+

Timer 0 Comparator Value Register

+
+
+

Address Offset: 108-10Fh

+
+
+

Attribute: R/W

+
+
+

Default value: FFFFFFFFh

+
+
+

Size:`8`

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + +
Table 129. Timer 0 comparator value register
Bit FieldNameDescriptionRead/Write

63:32

Reserved

Reserved

RO

31:0

T0_Com_VAL

The value of the timer 0 comparator. +When the corresponding timer is configured in non-periodic mode. +the value of this register will be compared with the value of the main timer register. +If the value of the main timer is equal to the value of the comparator, a timing interrupt is generated (if; the corresponding interrupt enable is on). +The comparator value will not change due to the interrupt generation If the corresponding timer is configured in periodic mode. +interrupt is generated when the value of the comparator in the value field of the main timer is equal (if; the corresponding interrupt enable is turned on). +If an interrupt is generated, then the comparator value is accumulated from the last software write to the comparator. For example, when the comparator value is written to 0x0123h +then an interrupt is generated when the value of the main timer is 0x123h; the comparator value is modified by hardware to 0x246h. +When the value of the main timer reaches 0x246h, another interrupt is generated; the comparator value is modified by hardware to 0x369h. +Whenever an interrupt is generated, the comparator value will be accumulated; until the comparator value reaches the maximum (0xffffffff), then the accumulator value will continue to accumulate. For example, when the comparator value is FFFF0000h, and the last time the comparator was written by software, the value is 20000. +When the interrupt occurs, the comparator value becomes 00010000h.

R/W

+
+

Timer 1 Configuration and Capabilities Registe

+
+
+

Address Offset: 120-127h

+
+
+

Attribute: RO, R/W

+
+
+

Default value: 00h

+
+
+

Size:`8` +Timer 1 configuration and function registers. Same as Timer 0.

+
+
+

Timer 1 Comparator Value Register

+
+
+

Address Offset: 128-12Fh

+
+
+

Attribute: R/W

+
+
+

Default value: FFFFFFFFh

+
+
+

Size:`8` +Timer 1 comparator value. Same as Timer 0.

+
+
+

Timer 2 Configuration and Capabilities Registe

+
+
+

Address Offset: 140-147h

+
+
+

Attribute: RO, R/W

+
+
+

Default value: 00h

+
+
+

Size: 8

+
+
+

Timer 2 configuration and function registers. +Same as Timer 0.

+
+
+

Timer 2 Comparator Value Register

+
+
+

Address Offset: 148-14Fh

+
+
+

Attribute: R/W

+
+
+

Default value: FFFFFFFFh

+
+
+

Size:`8`

+
+
+

Timer 2 comparator value. Same as Timer 0.

+
+
+
+
+
+

7. HT Controller

+
+
+

The bridge HT interface supports a maximum bi-directional 16-bit data width and an operating frequency of 2.0 GHz. +After the connection is established by automatic system initialization, the user can change the width and operating frequency and re-initialize by modifying the corresponding configuration registers in the protocol.

+
+
+

The main features of the bridge HT interface are as follows:

+
+
+
    +
  • +

    Support HT1.0/3.0 protocol

    +
    • +
  • +

    Support 200/400/800/1600/2000 MHz operating frequency

    +
    • +
  • +

    Support 8/16 bit width

    +
    • +
  • +

    Support dual processors with bridge chip direct connection (each link can only work in 8-bit mode)

    +
    • +
+
+
+

7.1. HT User Guide

+
+

7.1.1. HT Working Mode

+
+

When chip pin HT_8x2 is configured to 0, the bridge operates in single mode, where only one processor is directly connected to the bridge via the HT bus, and only one HT controller (HT lo) is operating inside the bridge, while the other HT controller (HT hi) is not available.

+
+
+

The HT link can operate in either 8-bit or 16-bit mode, and the software can configure the data width used (the maximum available width also depends on the PCB hardware connection), when the data link is controlled by controller lo. The data link is controlled by the controller lo.

+
+
+

When the chip pin HT_8x2 is configured to 1, the bridge operates in dual mode, where two processors can be connected directly to the bridge via the HT bus, and the two HT controllers inside the bridge are operating simultaneously, controlling the low 8 bits and high 8 bits of the data link respectively. Software can control both HT controllers via the HT bus of both processors. When operating in dual mode, the software needs to configure the HT DMA routing configuration (see section 4.1 HT Clock Enable and DMA Routing Configuration) to send DMA accesses to the corresponding HT controller.

+
+
+
+

7.1.2. HT Address Space

+
+

The address space for processor accesses is described in Section 3.

+
+
+

The HT module has several internal address windows for configuring CPU accesses and DMA accesses. For CPU accesses, the bridge chip acts as the accessee and the corresponding configuration window is called the receive window; +for DMA accesses, the bridge chip acts as the access initiator and the corresponding window is called the send window.

+
+
+

The receive window consists of two types: the P2P access window and the normal access window. Accesses that fall within the P2P access window are forwarded directly back to the HT bus as P2P commands and are not sent to the internal devices of the bridge chip; +accesses that fall within the normal access window are sent to the internal devices of the bridge chip as accesses to the internal devices of the bridge chip. The P2P access window has a higher priority than the normal access window. +Accesses that do not hit in either of the two types of receive windows are forwarded directly back to the HT bus as P2P commands.

+
+
+

DMA accesses are sent out through the HT’s non-Post channel by default, and the Post send window is set internally in the bridge to send DMA accesses out through the HT’s Post channel. +That is, DMA accesses that hit in the Post send window are sent to the HT bus via the HT’s Post channel, and DMA accesses that do not hit in the Post send window are sent to the HT bus via the HT’s non-Post channel. +In general, the Post send window should not be enabled and all DMA accesses should be sent out through the HT’s non-Post channel.

+
+
+
+
+

7.2. HT Configuration Register

+
+

HT Configuration Register

+
+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 130. HT configuration register
Address OffsetAbbreviationsDescriptionDefault valueRead/Write

00h-01h

VID

Vendor ID

0014h

RO

02h-03h

DID

Device ID

7A00h

RO

04h-05h

PCICMD

PCI Command

0000h

R/W, RO

06h-07h

PCISTS

PCI Status

0010h

RO

08h

RID

Revision ID

00h

RO

09h

PI

Programming Interface

00h

RO

0Ah

SCC

Sub Class Code

00h

RO

0Bh

BCC

Base Class Code

06h

RO

0Ch

CLS

Cache Line Size

00h

RO

0Eh

HEADTYP

Header Type

80h

RO

2Ch-2Dh

SVID

Subsystem Vendor ID

0014h

RO

2Eh-2Fh

SID

Subsystem Identification

7A00h

RO

34h

CAPP

Capabilities Pointer

40h

RO

3Ch

INT_LN

Interrupt Line

00h

R/W

3Dh

INT_PN

Interrupt Pin

00h

RO

3Eh-3Fh

BCTRL

Bridge Control Register

0000h

R/W

42h-43h

DIDCMD

Device ID Command Register

0000h

R/W, RO

44h-45h

LKSC0

Link Status and Control Register 0

0020h

R/W

46h-47h

LKWDSC0

Link Width Status and Control Register 0

0000h

R/W

4Ch

HTRID

HT Revision ID

60h

RO

4Dh-4Fh

LKFREQSC0

Link Frequency Status and Control Register 0

000000h

R/W, RO

140h-147h

RXWIN0

Receive Window 0

0000F00080000000h

R/W

148h-14Fh

RXWIN1

Receive Window 1

FDFCFFFF80000000h

R/W

150h-157h

RXWIN2

Receive Window 2

0000000000000000h

R/W

158h-15Fh

RXWIN3

Receive Window 3

0000000000000000h

R/W

160h-167h

RXWIN4

Receive Window 4

0000000000000000h

R/W

170h-177h

TXPOSTWIN0

Transmit Post Window 0

0000000000000000h

R/W,RO

178h-17Fh

TXPOSTWIN1

Transmit Post Window 1

0000000000000000h

R/W,RO

1B0h-1B7h

RXP2PWIN0

Receive P2P Window 0

0000000000000000h

R/W,RO

1B8h-1BFh

RXP2PWIN1

Receive P2P Window 1

0000000000000000h

R/W,RO

1F4h-1F7h

HTPLLCTRL

HT Pll Control Register

00000000h

R/W,RO

+
+

Note: Address spaces not listed in the table indicate reservations.

+
+
+

BCTRL-HT bridge control register

+
+
+

Address Offset: 3E-3Fh

+
+
+

Attribute: R/W, RO

+
+
+

Default value: 0000h

+
+
+

Size: 16 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 131. BCTRL-HT bridge control register
Bit FieldNameRead/WriteDescription

15:7

Reserved

RO

Reserved

6

HT Reset

R/W

This bit controls the HT reset.

+

0: unreset.

+

1: Reset.

5:0

Reserved

RO

Reserved

+
+

DIDCMD - device ID command register

+
+
+

Address Offset: 42-43h

+
+
+

Attribute: R/W, RO

+
+
+

Default value: 0000h

+
+
+

Size: 16 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 132. DIDCMD-device ID command register
Bit FieldNameRead/WriteDescription

15:13

Command Format

RO

Command Format

12:10

Reserved

RO

Reserved

9:5

Unit Count

R/W

Provided to the software for recording the current number of units

4:0

Unit ID

R/W

Record the number of IDs used

+
+

LKSC0-Link status control register 0

+
+
+

Address Offset: 44-45h

+
+
+

Attribute: R/W, RO

+
+
+

Default value: 2000h

+
+
+

Size: 16 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+

LKWDSC0-Link data width status and control register

+
+
+

Address Offset: 46-47h

+
+
+

Attribute: R/W, RO

+
+
+

Default value: 0011h or 0000h

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+

LKFREQCFG0-Link frequency configuration register

+
+
+

Address Offset: 4C-4Dh

+
+
+

Attribute: R/W, RO

+
+
+

Default value: 0060h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+

Address Offset: 4E-4Fh

+
+
+

Attribute: RO

+
+
+

Default value: 0000h

+
+ + ++++++ + + + + + + + + + + + + + + + + + +
+

RXWIN - receive address window

+
+
+

Receive address window hits are sent to the internal devices of the bridge chip only when the access is hit. The receive address window includes the following fields:

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 137. RXWIN-receive address window
Bit FieldNameRead/WriteDescription

64:48

WIN_BASE

R/W

Window Base Address

47:32

WIN_MASK

R/W

Window Mask

31

WIN_EN

R/W

Window Enable

30

WIN_TRANS_EN

R/W

Window address conversion enable

29:0

WIN_TRANS

R/W

Window converted address high bit of address bit`[53:24]` +When the window is enabled, the address window hit condition is: ( ADDR & WIN_MASK ) == ( WIN_BASE & WIN_MASK ). If address translation is enabled, the output address is: (ADDR & ~WIN_MASK)

+
+

RXWIN0-Receive window register 0

+
+
+

Address Offset: 140-147h

+
+
+

Attribute: R/W

+
+
+

Default value: 0000F00080000000h

+
+
+

Size:`64` bit

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 138. RXWIN0-Receive window register 0
Bit FieldNameRead/WriteDescription

64:48

RXWIN0_BASE

R/W

Receive Window 0 Base Address

47:32

RXWIN0_MASK

R/W

Receive Window 0 Mask

31

RXWIN0_EN

R/W

Receive Window 0 Enable

30

RXWIN0_TRANS_EN

R/W

Receive Window 0 Address Conversion Enable

29:0

RXWIN0_TRANS

R/W

Receive Window 0 Converted high address, bit[53:24] of address

+
+

RXWIN1-Receive window register 1

+
+
+

Address Offset: 148-14Fh

+
+
+

Attribute: R/W

+
+
+

Default value: FDFCFFFF80000000h

+
+
+

Size: 64 bit

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 139. RXWIN1-Receive window register 1
Bit FieldNameRead/WriteDescription

64:48

RXWIN1_BASE

R/W

Receive Window 1 Base Address

47:32

RXWIN1_MASK

R/W

Receive Window 1 Mask

31

RXWIN1_EN

R/W

Receive Window 1 Enable

30

RXWIN1_TRANS_EN

R/W

Receive Window 1 Address Conversion Enable

29:0

RXWIN1_TRANS

R/W

Receive Window 1 Converted high address, bit`[53:24]` of the address

+
+

RXWIN2-Receive window register 2

+
+
+

Address Offset: 150-147h +|Attribute: R/W +Default value: 0000000000000000h +|Size: 64 bit

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 140. RXWIN2-Receive window register 2
Bit FieldNameRead/WriteDescription

64:48

RXWIN2_BASE

R/W

Receive Window 2 Base Address

47:32

RXWIN2_MASK

R/W

Receive Window 2 Mask

31

RXWIN2_EN

R/W

Receive Window 2 Enable

30

RXWIN2_TRANS_EN

R/W

Receive Window 2 Address Conversion Enable

29:0

RXWIN2_TRANS

R/W

Receive Window 2 Converted High Address, bit`[53:24]` of the address

+
+

RXWIN3-Receive window register 3

+
+
+

Address Offset: 158-14Fh

+
+
+

Attribute: R/W

+
+
+

Default value: 0000000000000000h

+
+
+

Size: 64 bit

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 141. RXWIN3-Receive window register 3
Bit FieldNameRead/WriteDescription

64:48

RXWIN3_BASE

R/W

Receive Window 3 Base Address

47:32

RXWIN3_MASK

R/W

Receive Window 3 Mask

31

RXWIN3_EN

R/W

Receive Window 3 Enable

30

RXWIN3_TRANS_EN

R/W

Receive Window 3 Address Conversion Enable

29:0

RXWIN3_TRANS

R/W

Receive Window 3 Converted High Address, bit`[53:24]` of the address

+
+

RXWIN4-Receive window register 4

+
+
+

Address Offset: 160-147h

+
+
+

Attribute: R/W

+
+
+

Default value: 0000000000000000h

+
+
+

Size: 64 bit

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 142. RXWIN4-Receive window register 4
Bit FieldNameRead/WriteDescription

64:48

RXWIN4_BASE

R/W

Receive Window 4 Base Address

47:32

RXWIN4_MASK

R/W

Receive Window 4 Mask

31

RXWIN4_EN

R/W

Receive Window 4 Enable

30

RXWIN4_TRANS_EN

R/W

Receive Window 4 Address Conversion Enable

29:0

RXWIN4_TRANS

R/W

Receive Window 4 Converted High Address, bit`[53:24]` of the address

+
+

TXPOSTWIN - quick send window

+
+
+

Visits hit by the Quick Send window give a direct response, thus speeding up the request for the request initiator. The Quick Send window includes the following fields:

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 143. TXPOSTWIN - quick send window
Bit FieldNameRead/WriteDescription

64:48

WIN_BASE

R/W

Window Base Address

47:32

WIN_MASK

R/W

Window Mask

31

WIN_EN

R/W

Window Enable

30:0

Reserved

RO

Reserved

+
+

When the window is enabled, the address window hit condition is: ( ADDR & WIN_MASK ) == ( WIN_BASE & WIN_MASK ). Note: ADDR here refers to the high 16 bits of the address (bit`[39:24], the address sent to the HT bus is only 40 bits). +For example, `1111111100000000b,1100000000000000b are all legal configurations, while The number of zeros in MASK indicates the size of the address window.

+
+
+

TXPOSTWIN0-Quick send window register 0

+
+
+

Address Offset: 170-177h

+
+
+

Attribute: R/W,RO

+
+
+

Default value: 0000000000000000h

+
+
+

Size:`64` bit

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 144. TXPOSTWIN0-Quick send window register 0
Bit FieldNameRead/WriteDescription

64:48

TXPOSTWIN0_BASE

R/W

Quick Send Window 0 Base Address

47:32

TXPOSTWIN0_MASK

R/W

Fast Send Window 0 Mask

31

TXPOSTWIN0_EN

R/W

Fast Send Window 0 Enable

30:0

Reserved

RO

Reserved

+
+

TXPOSTWIN1 - Quick send window register 1

+
+
+

Address Offset: 178-17Fh

+
+
+

Attribute: R/W,RO

+
+
+

Default value: 000000000000000h

+
+
+

Size: 64 bit

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 145. TXPOSTWIN1-Quick send window register 1
Bit FieldNameRead/WriteDescription

64:48

TXPOSTWIN1_BASE

R/W

Quick Send Window 1 Base Address

47:32

TXPOSTWIN1_MASK

R/W

Fast Send Window 1 Mask

31

TXPOSTWIN1_EN

R/W

Fast Send Window 1 Enable

30:0

Reserved

RO

Reserved

+
+

RXP2PWIN-P2P receive window

+
+
+

Accesses hit by the P2P receive window are sent directly back to the HT bus as P2P commands. the P2P receive window has a higher priority than the normal receive window. the P2P receive window includes the following fields.

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 146. RXP2PWIN-P2P receive window
Bit FieldNameRead/WriteDescription

64:48

WIN_BASE

R/W

Window Base Address

47:32

WIN_MASK

R/W

Window Mask

31

WIN_EN

R/W

Window Enable

30:0

Reserved

RO

Reserved

+
+

When the window is enabled, the address window hit condition is: ( ADDR & WIN_MASK ) == ( WIN_BASE & WIN_MASK ). Note: ADDR here refers to the high 16 bits of the address (bit[39:24], the address sent to the HT bus is only 40 bits).

+
+
+

For example, 1111111100000000b,1100000000000000b are legal configurations, while 1011111100000000b,11010000000000b are not. +The number of zeros in MASK indicates the size of the address window.

+
+
+

RXP2PWIN0-P2P receive window 0

+
+
+

Address Offset: 180-187h

+
+
+

Attribute: R/W,RO

+
+
+

Default value: 00000`00000000000h

+
+
+

Size: 64 bit

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 147. RXP2PWIN0-P2P receive window 0
Bit FieldNameRead/WriteDescription

64:48

RXP2PWIN0_BASE

R/W

P2P Receive Window 0 Base Address

47:32

RXP2PWIN0_MASK

R/W

P2P receive window 0 mask

31

RXP2PWIN0_EN

R/W

P2P receive window 0 enable

30:0

Reserved

RO

Reserved

+
+

RXP2PWIN0-P2P receive window 1

+
+
+

Address Offset: 188-18Fh

+
+
+

Attribute: R/W,RO

+
+
+

Default value: 000000000000000h

+
+
+

Size: 64 bit

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 148. RXP2PWIN1-P2P receive window 1
Bit FieldNameRead/WriteDescription

64:48

RXP2PWIN1_BASE

R/W

P2P Receive Window 1 Base Address

47:32

RXP2PWIN1_MASK

R/W

P2P receive window 1 mask

31

RXP2PWIN1_EN

R/W

P2P receive window 1 enable

30:0

Reserved

RO

Reserved

+
+

Htpllctrl-ht pll control register

+
+
+

This register is used to enable the software configuration of the HT’s PLL, which is used to modify the frequency of the HT PHY and controller.

+
+
+

Address Offset: 1F4-1F7h

+
+
+

Attribute: R/W,RO

+
+
+

Default value: 00000000h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 149. Htpllctrl-ht pll control register
Bit FieldNameRead/WriteDescription

31:26

Reserved

R/W

Reserved

25:22

pll_div_phy_lo

R/W

PHY low output crossover

21:18

pll_div_phy_hi

R/W

PHY high output crossover

17:16

pll_div_refc

R/W

HT PLL input frequency division

15:9

pll_loopc

R/W

HT PLL Multiplier

8:5

pll_div_ctrl

R/W

Controller output divider

4

Reserved

RO

Reserved

3

pll locked

RO

PLL lock

2

Controller bypass

R/W

Controller clock bypass mode

1

pll config enable

R/W

PLL Configuration Enable

0

Reserved

RO

0: Disable PLL configuration

+
+
+
+
+

8. MISC Low-speed Devices

+
+
+

MISC low speed devices include: UART, I2C, PWM, ACPI, RTC, and GPIO. these devices run at a fixed frequency of 50MHz.

+
+
+

8.1. MISC Low-speed Devices Configuration Register

+
+

The address space size of the MISC low-speed device block is 512KB, and the starting address (internal space of the bridge chip) is configured by the BIOS.

+
+
+
+

8.2. Internal Device Address Routing

+
+

Multiple devices within the MISC low-speed device block are distinguished by the bits [18:16] of the address bits, and different devices support only specific types of access. The device routing and supported access types are shown in the following table.

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 150. MISC Low-speed device address routing and access types
bit[18:16]01256

Device

UART

I2C

PWM

ACPI/RTC

GPIO

Read/Write

B

B

W

W

B

+
+

For UART, I2C, PWM, and ACPI/RTC, they require further routing due to the inclusion of multiple controllers. The internal routing of these device blocks is shown in the fllow table The number of routing address bits required varies from one device block to another.

+
+ + +++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 151. MISC Low-speed device address routing
012345

UART(bit[9:8])

UART0

UART1

UART2

UART3

-

-

I2C(bit[10:8])

I2C0

I2C1

I2C2

I2C3

I2C4

I2C5

PWM(bit[9:8])

PWM0

PWM1

PWM2

PWM3

-

-

ACPI/RTC(bit[8])

ACPI

RTC

-

-

-

-

+
+

These low-speed devices are described separately in subsequent sections.

+
+
+
+
+
+

9. UART Controller

+
+
+

The integrated UART controller of the bridge chip complies with the RS232 standard and the controller is designed to be compatible with the 16550A. +The internal clock frequency of the UART controller is 50 MHz and the maximum baud rate supported by the UART bus is 460800.

+
+
+

The bridge chip integrates four UART controllers, which are arranged in the UART module. +In addition, UART1, UART2 and UART3 can only work in two-wire UART mode, and UART0 can work in full-function UART mode or two-wire UART mode. +In addition, UART can be multiplexed as GPIO function and some UART pins can be multiplexed as I2C function. +The pin multiplexing configuration registers related to UART are described in Section 4.4.

+
+ + ++++++ + + + + + + + + + + + + + + + + + +
Table 152. UART function reuse

UART_TXD/RXD

UART_RTS/CTS

UART_DTR/DSR

UART_RI/DCD

UART0

UART0

UART1

UART2

UART3

+
+

9.1. Access Address

+
+

The access base address of the UART controller is the base address of the MISC low-speed device block plus offset 0x0. Note: The UART module supports byte access only.

+
+
+

The 4 UART controllers are distinguished by bit [9:8], and the internal physical address division of the UART module is shown in the following table.

+
+ + +++++ + + + + + + + + + + + + + + + + + + + + + + + + +
Table 153. Module physical address composition
Address bitCompositionRemarks

[15:10]

0

Reserved

[09:08]

UART number

0x0 - 0x3 for each UART controller

[07:00]

REG

internal register address

+
+
+

9.2. Description of Registers

+
+

Data register (DAT)

+
+
+

Offset: 0x00

+
+
+

Reset value: 0x00

+
+ + ++++++ + + + + + + + + + + + + + + + + +
Table 154. UART function reuse
Bit FieldNameLengthRead/Write

Description

7:0

Tx FIFO

8

+
+

Interrupt enable register (IER)

+
+
+

Offset: 0x01

+
+
+

Reset value: 0x00

+
+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 155. Interrupt enable register (IER)
Bit FieldNameLengthRead/WriteDescription

7:4

Reserved

4

R/W

Reserved

3

IME

1

R/W

Modem Status Interrupt Enable

+

0: off

+

1: On

2

ILE

1

R/W

Receiver line status interrupt enable

+

0: off

+

1: Open

1

ITxE

1

R/W

Transmission save register is air break enable

+

0: off

+

1: open

0

IRxE

1

R/W

Receive valid data interrupt enable

+

0: off

+

1: Open

+
+

Interrupt identification register (IIR)

+
+
+

Offset: 0x02

+
+
+

Reset value: 0xc1

+
+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 156. Interrupt identification register (IIR)
Bit FieldNameLengthRead/WriteDescription

7:4

Reserved

4

R

Reserved

3:1

II

3

R

Interrupt source indication bits, see the following table for details

0

INTp

1

R

Interrupt bits

+
+

Interrupt control menu

+
+ + +++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 157. Interrupt control menu
Bit 3Bit 2Bit 1PriorityInterrupt TypeInterrupt SourceInterrupt Reset Control

0

1

1

1st

Receive line status

parity, overflow or frame errors.

Read LSR

0

1

0

2nd

Valid data received

or interrupt interrupt

The number of characters in the FIFO is lower than the value of the trigger

1

1

0

2nd

Receive timeout

The number of characters in the FIFO reaches the level of a trigger

Read the receive FIFO

0

0

1

3rd

Transmission save register is empty

There is at least one character in the FIFO, but no operation, including read and write operations, within 4 characters

Write data to THR or multi-IIR

0

0

0

4th

Modem Status

Transfer save register is empty

Read MSR

+
+

FIFO control register (FCR)

+
+
+

Offset: 0x02

+
+
+

Reset value: 0xc0

+
+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 158. FIFO control register (FCR)
Bit FieldNameLengthRead/WriteDescription

7:6

TL

2

W

Receive trigger value for interrupt request from FIFO

+

00b: 1 byte

+

01b: 4 bytes

+

10b: 8 bytes

+

11b: 14 bytes

5:3

Reserved

3

W

Reserved

2

Txset

1

W

Clears the contents of the transmit FIFO and resets its logic

1

Rxset

1

W

Clears the contents of the receive FIFO and resets its logic

0

Reserved

1

W

Reserved

+
+

Line control register (LCR)

+
+
+

Offset: 0x03

+
+
+

Reset value: 0x03

+
+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 159. Line control register (LCR)
Bit FieldNameLengthRead/WriteDescription

7

dlab

1

R/W

Crossover latch access bits

+

1: Access to operate the divider latch.

+

0: Access to operate the normal register.

6

bcb

1

R/W

Interrupt control bit

+

1: The output of the serial port is set to 0 (interrupt state) at this time.

+

0: Normal operation.

5

spb

1

R/W

Specify the parity bit

+

0: No parity bit is specified.

+

1: If the LCR[4] bit is 1, the transmit and check parity bit is 0. If the LCR[4] bit is 0, the transmit and check parity bit is 1. If the LCR[4] bit is 0, then the transmit and check parity bit is 1.

4

eps

1

R/W

Parity Bit Selection

+

0: Odd number of 1’s per character (including data and parity bits).

+

1: Even 1’s in each character.

3

pe

1

R/W

Parity bit enable

+

0: No parity bit.

+

1: Parity bit is generated at output, and parity bit is judged at input.

2

sb

1

R/W

Define the number of bits to generate stop bits

+

0: 1 stop bit.

+

1: 1.5 stop bits at 5-bit character length, 2 stop bits at other lengths.

1:0

bec

2

R/W

Set the number of bits per character

+

00b: 5 bits.

+

01b: 6 bits.

+

10b: 7 bits.

+

11b: 8 bits.

+
+

MODEM control register (MCR)

+
+
+

Offset:`0x04`

+
+
+

Reset value:`0x00`

+
+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 160. MODEM control register (MCR)
Bit FieldNameLengthRead/WriteDescription

7:5

Reserved

3

W

Reserved

4

Loop

1

W

Loopback mode control bits

+

0: Normal operation.

+

1: Loopback mode.

+

In loopback mode, the TXD output is always 1 and the output shift register is connected directly to the input shift register. Other connections are as follows: DTR - DSR +RTS - CTS Out1 - RI +Out2 - DCD

3

OUT2

1

W

Connects to the DCD input in loopback mode

2

OUT1

1

W

Connects to the RI input in loopback mode

1

RTSC

1

W

RTS signal control bit

0

DTRC

1

W

DTR signal control bit

+
+

Line status register (LSR)

+
+
+

Offset:`0x05`

+
+
+

Reset value:`0x00`

+
+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 161. Line status register (LSR)
Bit FieldNameLengthRead/WriteDescription

7

ERROR

1

R

Error indication bit

+

0: No errors.

+

1: At least one of parity bit error, frame error or interrupt interrupt. +one.

6

TE

1

R

Transfer to empty indicates bit

+

0: Data is available.

+

1: Both the transmit FIFO and the transmit shift register are empty. Clear when writing data to the transfer +FIFO is cleared when writing data to the FIFO.

5

TFE

1

R

Transfer FIFO bit null indicates bit

+

0: Data is available.

+

1: The current transmit FIFO is empty and is cleared when writing data to the transmit FIFO.

4

BI

1

R

Interrupt interrupt indication bit

+

0: No interrupt.

+

1: Received Start bit + data + parity bit + stop bit are +0, i.e., there is an interrupt interrupt .

3

FE

1

R

Frame error indication bits +0: There are no errors. +1: The received data has no stop bit.

2

PE

1

R

Parity bit error indication bit

+

0: There is no parity error.

+

1: There is a parity error in the current received data.

1

OE

1

R

Data overflow indication bit

+

0: No overflow.

+

1: There is data overflow.

0

DR

1

R

Receive data valid indication bit

+

0: No data in the FIFO.

+

1: There is data in the FIFO.

+
+

When reading this register, LSR[4:1] and LSR[7] are cleared to zero, LSR[6:5] is cleared when writing data to the transmit FIFO, and LSR[0] is judged for the receive FIFO.

+
+
+

MODEM status register (MSR)

+
+
+

Offset: 0x06

+
+
+

Reset value: 0x00

+
+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 162. MODEM status register (MSR)
Bit FieldNameLengthRead/WriteDescription

7

CDCD

1

R

The inverse of the DCD input value, or to Out2 in loopback mode

6

CRI

1

R

The inverse of the RI input value, or to OUT1 in loopback mode

5

CDSR

1

R

The inverse of the DSR input value, or to DTR in loopback mode

4

CCTS

1

R

The inverse of the CTS input value, or to RTS in loopback mode

3

DDCD

1

R

DDCD indication bit

2

TERI

1

R

RI edge detection, RI state changes from low to high

1

DDSR

1

R

DDSR indication bit

0

DCTS

1

R

DCTS indication bit

+
+

Frequency divider latch

+
+
+

Offset: 0x00

+
+
+

Reset value: 0x00

+
+ + +++++++ + + + + + + + + + + + + + + + + + + +
Table 163. Frequency divider latch 1
Bit FieldNameLengthRead/WriteDescription

7:0

LSB

8

R/W

Store the lower 8 bits of the divider latch

+
+

Offset:0x01

+
+
+

Reset value:0x00

+
+ + +++++++ + + + + + + + + + + + + + + + + + + +
Table 164. Frequency divider latch 2
Bit FieldNameLengthRead/WriteDescription

7:0

MSB

8

R/W

Store the high 8 bits of the divider latch

+
+

The value of the crossover latch {MSB,LSB} is calculated as 50MHz/16/baud rate. For example, if you want to configure a serial port baud rate of 115200, the value of the divider latch = 50,000,000/16/115,200 ≈ 27.

+
+
+
+
+
+

10. I2C Controller

+
+
+

A total of 6 I2C controllers are integrated into the bridge, and the I2C controllers operate at 50MHz. +The maximum transfer rate supported by the I2C bus is 400kbps.

+
+
+

10.1. Access Address and Pin Multiplexing

+
+

The base address of accessing the I2C controller is the base address of the MISC low-speed device block plus an offset of 0x10000.

+
+
+

Note: The I2C module only supports access by 1 byte.

+
+
+

The physical address composition of the I2C module internal registers is as follows.

+
+ + +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 165. The physical address composition of the I2C module internal registers
Address bitsCompositionNote

[15:11]

0

Reserved

[10:8]

I2C controller number

0x0-0x5 represent I2C0-I2C5 respectively

[7:3]

0

Reserved

[2:0]

REG

Internal registers address

+
+

For I2C modules, the corresponding pins should be set to the corresponding functions when used. +The pin settings related to I2C are described in Pin Multiplexing Configuration Register.

+
+
+
+

10.2. Description of I2C Controller Register

+
+

Frequency Division Latch Low-order Byte Register (PRERlo)

+
+
+

Offset: 0x00

+
+
+

Reset value: 0xff

+
+ + +++++++ + + + + + + + + + + + + + + + + + + +
Table 166. Frequency division latch low-order byte register
Bit FieldNameLengthRead/WriteDescription

7:0

PRERlo

8

R/W

Store the lower 8 bits of the division latch

+
+

Frequency Division Latch High-order Byte Register (PRERhi)

+
+
+

Offset: 0x01

+
+
+

Reset value: 0xff

+
+ + +++++++ + + + + + + + + + + + + + + + + + + +
Table 167. Frequency division latch high-order byte register
Bit FieldNameLengthRead/WriteDescription

7:0

PRERhi

8

RW

Store the high 8 bits of the division latch

+
+

Assuming that the value of the divider latch is Prescaler and the frequency of the I2C controller is 50MHz, if the clock frequency of the I2C bus is needed clock_s, then Prescaler should be equal to: 50M/(5*clock_s) - 1.

+
+
+

Control Register (CTR)

+
+
+

Offset: 0x02

+
+
+

Reset value: 0x00

+
+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 168. Control register
Bit FieldNameLengthRead/WriteDescription

7

EN

1

R/W

Module enable bit

+

0: Module disable

+

1: Module enable

6

IEN

1

R/W

Interrupt enable bit

+

0: Interrupt disable

+

1: Interrupt enable

5:0

Reserved

6

R/W

Reserved

+
+

Transport Data Register (TXR)

+
+
+

Offset: 0x03

+
+
+

Reset value: 0x00

+
+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 169. Transport data register
Bit FieldNameLengthRead/WriteDescription

7:1

DATA[7:1]/ADDR

7

W

When transporting data, the data to be sent (bit[7:1]) is stored.

+

When transporting the address, the address of the I2C slave device is stored

0

DATA[0]/RW

1

W

When transporting data, stores the data to be sent (bit[0]).

+

When transporting the address, the read and write status is stored.

+

0: Write

+

1: Read

+
+

Receive Data Register (RXR)

+
+
+

Offset: 0x03

+
+
+

Reset value: 0x00

+
+ + +++++++ + + + + + + + + + + + + + + + + + + +
Table 170. Receive data register
Bit FieldNameLengthRead/WriteDescription

7:0

RXR

8

R

Store received data

+
+

Command Control Register (CR)

+
+
+

Offset: 0x04

+
+
+

Reset value: 0x00

+
+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 171. Command control register
Bit FieldNameLengthRead/WriteDescription

7

STA

1

W

Generate the START signal

6

STO

1

W

Generate the STOP signal

5

RD

1

W

Generate the read signal

4

WR

1

W

Generate the write signal

3

ACK

1

W

Generate the response signal

+

0: The controller sends ack at the end of this transmission

+

1: The controller does not send ack at the end of this transmission

2:1

Reserved

2

W

Reserved

0

IACK

1

W

Generate interrupt response signal. +Software writes 1 to this bit to clear the interrupt.

+
+

State Register (SR)

+
+
+

Offset: 0x04

+
+
+

Reset value: 0x00

+
+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 172. State register
Bit FieldNameLengthRead/WriteDescription

7

RxACK

1

R

Receive response bit

+

1 - no receive the response bit

+

0 - receive the response bit

6

Busy

1

R

I2c bus busy flag bit

+

1 - bus is busy

+

0 - bus is free

5

AL

1

R

When the I2C core loses control of the I2C bus, this bit is 1

4:2

Reserved

3

R

Reserved

1

TIP

1

R

Indicate the process of transport

+

1 - indicate that data is being transported

+

0 - indicate that data transport is complete

0

IF

1

R

Interrupt flag bit. +When one data transport is finished, or another device initiates data transport, this bit is 1

+
+
+
+
+

11. PWM Controller

+
+
+

A four-way pulse width output/counter controller (PWM) is implemented in the bridge. +The four PWMs The four PWMs work and control in exactly the same way. +Each PWM pin can be used as either a pulse output signal or a pulse width measurement input signal. +The PMW controller clock is 50MHz, and the count and reference registers are 32-bit length.

+
+
+

11.1. Access Address and Pin Multiplexing

+
+

The base address of accessing the PWM controller is the base address of the MISC low-speed device block plus an offset of 0x20000.

+
+
+

Note: The PWM module only supports access by 4 bytes.

+
+
+

The physical address composition of the PWM controller internal registers is as follows.

+
+ + +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 173. The physical address composition of the PWM controller internal registers
Address bitsCompositionNote

[15:10]

0

Reserved

[9:8]

PWM number

0x0-0x3 represent PWM0-PWM3 respectively

[7:4]

0

Reserved

[3:0]

REG

Internal registers address

+
+

For PMM modules, the corresponding pins should be set to the corresponding functions when used. +The pin settings related to PMM are described in Pin Multiplexing Configuration Register.

+
+
+
+

11.2. Description of Registers

+
+

There are three registers per controller, which are described as follows.

+
+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 174. List of PWM registers
NameAddressLengthRead/WriteDescription

low_buffer

Base + 0x4

32

R/W

Low pulse width register

full_buffer

Base + 0x8

32

R/W

Pulse period width register

CTRL

Base + 0xC

11

R/W

Control register

+
+

PWM Control Register Configuration

+
+ +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Bit FieldNameRead/WriteReset ValueDescription

0

EN

R/W

0

PWM enable bit

+

1: PWM enable

+

0: PWM disable

2:1

Reserved

R/W

0

Reserved

3

OE

R/W

0

Pin pulse output enable control bit (active low). +When set to 1, the PWM can be used as a periodic interrupt generation module without changing the value of the PWM pin (held at 0)

+

0: Pulse output enable

+

1: Pulse output disable

4

SINGLE

R/W

0

Single pulse control bit, valid for non-measurement mode

+

1: Pulse is generated only once

+

0: Pulse is generated continuously

5

INTE

R/W

0

Interrupt enable bit. +In the non-measurement mode, an interrupt is generated for every pulse period measured. +In the measurement mode, an interrupt is generated when the input pulse period is greater than 0xFFFF_FFF9.

+

1: Interrupt is generated

+

0: No interrupt is generated

6

INT

R/W

0

Interrupt status bit. +Write 1 to this bit to clear the interrupt

+

1: The interrupt is generated

+

0: No interrupt

7

RST

R/W

0

Counter reset

+

1: Reset

+

0: Normal work

8

CAPTE

R/W

0

Measurement pulse enable

+

1: Measurement pulse mode

+

0: Non-measurement pulse mode (or pulse output mode in general)

9

INVERT

R/W

0

Output invert enable, valid for non-measurement mode

+

1: Invert the signal after the pulse is output (period starts at high level)

+

0: Keeps the pulse at the original output (period starts at low level)

10

DZONE

R/W

0

Anti dead zones function enable, valid for non-measurement mode

+

1: This PWM enables the anti dead zones function

+

0: This PWM disables the anti dead zones function

+
+
+

11.3. Description of Functions

+
+

11.3.1. Pulse Width Modulation Function

+
+

The low_buffer and full_buffer registers are used to configure the low level of the periodic signal and the length of the total period of the PWM output in the clock period of the PWM module (20ns), respectively. +For example, to generate a low pulse width of 50 times the PWM module clock period and a high pulse width of 90 times the PWM module clock period, you should configure the value 50 in the low_buffer and (50+90)=140 in the full_buffer.

+
+
+

The pulse width register value should be written before the CTRL control register. +Before writing a new number to the pulse width register, you should clear the EN bit in the control register and then set the EN bit to 1 after writing the new number.

+
+
+

If 0 is written to both buffer registers, the output is always low. +If writing 0 to low_buffer and 1 to full_buffer, the output is always high. +If the value written to low_buffer is not less than the value of full_buffer, the output is low.

+
+
+
+

11.3.2. Pulse Measurement Function

+
+

After setting the CTRL control register, the PWM continuously samples the input signal level. +When a down-jump of the input pulse signal is detected, the internal counter starts counting from 1, and when an up-jump is detected, the counter value is shifted to the low_buffer register and continues to accumulate, and when a down-jump is detected again, the counter value is shifted to the full_buffer register. +For example, if the input pulse is 50 times the low pulse width of the system clock and 90 times the high pulse width, the final value read in the low_buffer is 50, and the value read in the full_buffer register is (50+90)=140.

+
+
+

It should be noted that the pulse to be measured should be a periodic signal, and the pulse period should not exceed the range that the 32-bit counter can measure. +If there is a pulse with a pulse period longer than 0xFFFF_FFF9, the INT bit of the control register will be set to 1, indicating that the pulse to be measured is out of the measurement range.

+
+
+
+

11.3.3. Anti Dead Zones Function

+
+

Multiple PWMs are equipped with an anti dead zones function between them, which prevents multiple pulse outputs from jumping at the same time. +To use the anti dead zones function, the multiple PWMs of the anti dead zones function must be numbered from 0 and be consecutive, and their anti dead zones functions must all be enabled. +In other words, one of PWM0/1, PWM0/1/2 and PWM0/1/2/3 must be used when using the anti dead zones function.

+
+
+

For PWM_0, PWM_1, PWM_2, and PWM_3, their priority is 0> 1 > 2 > 3. +If they jump at the same time, PWM_1 will jump only after PWM_0 jumps (the lower priority signal is “erased” by one clock cycle), and so on. +This priority is fixed and cannot be changed.

+
+
+

A typical anti dead zones example is as follows (PWM_* is the output when the anti dead zones function is disabled, and PWM_*' is the output when the anti dead zones function is enabled).

+
+
+
+anti dead zones function +
+
Figure 8. Anti dead zones function
+
+
+
+
+
+
+

12. Power Management Module (ACPI Support)

+
+
+

Bridge power management module provides system power management functions. +It supports Advanced Configuration and Power Interface, Version 4.0a (ACPI) to provide the corresponding power management functions.

+
+
+
    +
  • +

    System hibernation and wake-up, support for ACPI S3 (suspend to RAM), ACPI S4 (suspend to disk), ACPI S5 (soft off), and support for power failure detection and automatic system recovery. +It also supports multiple wake-up methods (USB, GMAC, power switch, etc.)

    +
    • +
  • +

    System clock control, module clock gating, multiple ways to adjust the frequency.

    +
    • +
  • +

    It integrates a watchdog with a maximum timing time of about 82s.

    +
    • +
+
+
+

12.1. Access Address

+
+

The base address of accessing the power management module is the base address of the MISC low-speed device block plus an offset of 0x50000.

+
+
+

Note: The PWM module only supports access by 4 bytes.

+
+
+

The physical address composition of the ACPI module internal registers is as follows.

+
+ + +++++ + + + + + + + + + + + + + + + + + + + +
Table 175. The physical address composition of the ACPI controller internal registers
Address bitsCompositionNote

[15:8]

0

Reserved

[7:0]

REG

Internal registers address

+
+
+

12.2. Power Level

+ + ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 176. Description of ACPI status
G0/S0Work all. +The system works all in this mode

G1/S1

Not supported at the moment

G1/S3

Suspend to RAM (STR). +Context saving to memory

G1/S4

Suspend to Disk (STD). +Save to hard disk, except wake-up circuit all power down

G2/S5

Soft off. +Only the wake-up circuit is powered on

G3

Mechanical off. +All power supply failures

+
+
+

12.3. Description of Registers

+
+

This section describes the power management related registers. +The register voltage field indicates the voltage field to which this bit of the register belongs.

+
+
+

PMCON_SOC: SOC General PM Configuration Register

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 177. SOC general PM configuration register

Address Offset

Voltage Field

Attribute

0x00

SOC

R/W, RO

Bit Field

Description

25

PWRBTN_LVL - RO

+

This bit indicates the current PWRBTNn signal status.

24

PWRTYP - RO

+

This bit indicates the power supply mode.

+

1: AC (Adapter)

+

0: Battery

23:0

Reserved

+
+

PMCON_RESUME : RESUME General PM Configuration Register

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 178. RESUME general PM configuration register

Address Offset

Voltage Field

Attribute

0x04

RESUME

R/W, RO, R/WC

Bit Field

Description

31:14

Reserved

13

VSB_GATEn_EN - R/W

+

Enables or disables the VSB_GATEn function.

+

0: off; 1: enable.

+

If RSMRSTn is active, this bit is 1. +This bit is configured by the system after re-powering. +If the motherboard uses the VSB_GATEn pin as the power management control signal, the system software must write 1 to this bit.

12:11

VSB_GATEn_DLY - R/W

+

Used to control the duration of the VSB_GATEn signal relative to S3n from S0 to S3 and S3 to S0 (the time advanced when sleeping and the time delayed when waking up).

+

2’b00: 31.25ms advance at hibernation and 125ms delay at wake-up.

+

2’b01: 62.5ms advance at hibernation, 250ms delay at wake-up.

+

2’b10: 125ms advance on hibernation and 500ms delay on wake-up.

+

2’b11: 250ms ahead of hibernation and 1s behind wake-up.

+

This field is 2’b0 if RSMRSTn is valid, and is configured by the system after re-powering.

10:8

Reserved

7

USB_GMAC_OK - R/W

+

If RSMRSTn is valid, this bit is 0, indicating that USB and GMAC are not configured and cannot wake up the system. +The system will configure this bit after re-powering.

6

CTT_STS - R/WC

+

The system enters the G2/S5 state when a temperature trip occurs in the S0 state, and this bit is used to detect the logged event status after re-powering the system.

5

CTT_EN - R/W

+

Enable the temperature trip protection mechanism.

4

LID_OPEN - RO

+

Display status detection bit.

+

1: Display is on.

+

0: Display is off.

3

Reserved

2

SRS (System Reset Status) - R/WC

+

0: SYS_RESETn has not been pressed

+

1: SYS_RESETn has been pressed. +This bit should be checked after system reset and clear it accordingly.

1

PWROK_FLR (PWROK Failure) - R/WC

+

When the system is in the S0 state, the PWROK signal becomes invalid and this bit is set to 1. +Software writes 1 to clear this bit.

0

DRAM_INIT - R/W

+

This bit does not affect the hardware function, PMON will set this bit to 1 before DRAM initialization, and write 0 to this bit after finishing DRAM initialization, software can use this bit to check if DRAM initialization has been interrupted.

+
+

PMCON_RTC : RTC General PM Configuration Register

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 179. RTC general PM configuration register

Address Offset

Voltage Field

Attribute

0x08

RTC

R/W, R/WC

Bit Field

Description

31:9

Reserved

8

WOL_EN - R/W

+

Controls whether the SLPLANn signal is active when the system is in the low-power state. +When the system is in the operating state, SLPLANn is held high.

+

0: SLPLANn is not valid.

+

1: SLPLANn is pulled low if the system is powered by the power supply. +If the system is powered by the battery, WOL_BAT_EN determines whether SLPLANn is pulled low.

7

WOL_BAT_EN - R/W

+

When the system enters a low-power state and is battery powered and WOL_EN is high.

+

0: SLPLANn is invalid.

+

1: SLPLANn is pulled low.

6:5

S3_ASSERTION_WIDTH - R/W

+

The 2 bits represent the minimum time interval between when the S3n signal is valid and when it is invalid again.

+

11: 1s

+

10: 125ms

+

01: 1ms

+

00: 60us

4:3

S4_ASSERTION_WIDTH - R/W

+

The 2 bits represent the minimum time interval between when the S4n signal is valid and when it is invalid again.

+

11: 4s

+

10: 2s

+

01: 1s

+

00: 125us

2

S4_ASSERTION_EN - R/W

+

0: The interval between valid and re-invalidation of the S4n signal is several RTC periods.

+

1: The interval between valid and re-invalidation of the S4n signal is determined by S4_ASSERTION_WIDTH.

1

PWR_FLR (Power Failure) - R/WC

+

This bit is in the RTC domain and can only be reset by RTC_RSTn.

+

1 indicates that a power failure has occurred in the system (entering the G3 state), i.e., all power supplies except RTC have failed (RSMRSTn has been active). +The software clears this bit by writing 1.

0

AFTERG3_EN - R/W

+

This bit determines the action of the system after it enters the G3 state and the power is restored.

+

0: The system will automatically revert to the S0 state after power is restored.

+

1: The system will revert to the S5 state, or if the system was in the S4 state when the power failure occurred, the system will revert to the S4 state after power is restored.

+

This bit will be set to 1 by the power button override and thermal trip events.

+
+

PM1_STS : Power Management 1 Status Register

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 180. Power Management 1 Status Register

Address Offset

Voltage Field

Attribute

0x0C

RESUME/RTC/SOC

R/WC

Bit Field

Description

Voltage Field

31:16

Reserved

15

WAK_STS (Wake Status) - R/WC

+

0: Software writes 1 to clear this bit.

+

1: Hardware writes 1 to this bit if the system is woken up from any of the sleep states by a wakeup event.

Resume

14

PCIEXP_WAKE_STS - R/WC

+

1: PCIE wake-up event occurs

+

0: Software write 1 to clear the bit

Resume

13:12

Reserved

11

PRBTNOR_STS (Power Button Override Status) - R/WC

+

0: Software writes 1 to clear this bit.

+

1: When power button override occurs, this bit is set to 1, the system enters G2/S5 unconditionally state, while setting AFTERG3_EN to 1.

RTC

10

RTC_STS (RTC Status) - R/WC

+

0: Software writes 1 to clear this bit.

+

1: This bit is 1 when the RTC generates an alarm. +Also when RTC_EN is valid, this bit generates a wake-up event.

Resume

9

Reserved

8

PWRBTN_STS (Power Button Status) - R/WC

+

0: Software writes 1 to clear this bit. +Thermal trip will clear this bit.

+

1: This bit will be set to 1 when PWRBTNn is pressed and held for more than 16ms (less than 4s). +In the S0 state, an interrupt is generated when both PWRBTN_EN and PWRBTN_STS are active. +During any sleep state from S3-S5, the system will resume if PWRBTN_STS is set.

Resume

7:1

Reserved

0

TMROF_STS (PM Timer Overflow Status) - R/WC +0: Software writes 1 to clear this bit.

+

1: When the highest bit of the 24-bit counter (20ns per clock cycle) is inverted, this bit is set to 1. +The timer function is recommended to be done with HPET.

SOC

+
+

PM1_EN: Power Management 1 Enable Register

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 181. Power management 1 enable register

Address Offset

Voltage Field

Attribute

0x10

RESUME/RTC/SOC

R/W

Bit Field

Description

Voltage Field

31:15

Reserved

14

PCIEXP_WAKE_DIS - R/W

+

When this bit is set, no PCIE wake-up event is generated, but the value of this bit does not affect the value of PCIEXP_WAKE_STS.

resume

13:11

Reserved

10

RTC_EN (RTC Event Enable) - R/W

+

RTC wake-up and interrupt enable.

rtc

9

Reserved

8

PWRBTN_EN (Power Button Enable) - R/W

+

PWRBTN interrupt event generation enable, this bit does not affect PWRBTN wake-up event generation.

resume

7:1

Reserved

0

TMROF_EN (PM Timer Overflow Enable) - R/W

+

If this bit is set, TMROF_STS will generate an interrupt.

SOC

+
+

PM1_CNT: Power Management 1 Control Register

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 182. Power management 1 control register

Address Offset

Voltage Field

Attribute

0x14

RESUME/RTC/SOC

R/W

Bit Field

Description

Voltage Field

31:14

Reserved

13

SLP_EN (Sleep Enable) - R/W

+

Writing 1 to this bit will cause the system to enter the SLP_TYP declared hibernation state, and this bit will automatically revert to 0 upon entering the associated hibernation state.

resume

12:10

SLP_TYP (Sleep Type) - R/W

+

This 3 bits indicate the hibernation state of the system.

+

000: S0 state.

+

001: Reserved.

+

010: Reserved.

+

011: Reserved.

+

100: Reserved.

+

101: Suspend-to-RAM. +S3n signal is valid, enter S3 state.

+

110: Suspend-to-Disk. +S3n, S4n signals are valid, enter S4 state.

+

111: Soft Off. +S3n, S4n, S5n signals are valid, enter S5 state.

rtc

9:1

Reserved

0

INT_EN - R/W

+

Interrupt enable switch to enable the generation of interrupt signals for the power management controller.

SOC

+
+

PM1_TMR: Power Management 1 Timer

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + +
Table 183. Power management 1 timer

Address Offset

Voltage Field

Attribute

0x18

SOC

RO

Bit Field

Description

31:24

Reserved

23:0

TMR_VAL (Timer Value) - RO

+

Counter counts with a period of 8ns. +When the 23 bit is inverted, the TNROF_STS bit is set. +HPET is recommended.

+
+

GPE0_STS: General Purpose Event0 Status Register

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 184. General purpose event0 status register

Address Offset

Voltage Field

Attribute

0x28

RESUME

R/WC

Bit Field

Description

31:16

Reserved

15:10

USB[5:0]_STS - R/WC

+

Only the bit 10 is meaningful, the 15:11 bits are meaningless for now.

+

0: Software writes 1 to clear this bit.

+

1: These bits are set when a USB wake event occurs, and when the USBx_EN bit is valid, a wake event or interrupt is generated.

9

Reserved

8

RI_STS - R/WC

+

0: Software writes 1 to clear this bit.

+

1: This bit is set when the RIn signal is valid.

7

BATLOW_STS - R/WC

+

0: Software writes 1 to clear this bit.

+

1: This bit is set when the BATLOWn signal is active.

+

If BATLOW_EN is valid, an interrupt will be generated when BATLOW_STS is set. +This bit does not generate a wake-up event.

6

GMAC1_STS - R/WC

+

0: Software writes 1 to clear this bit.

+

1: These bits are set when a wake event occurs in GMAC1 and generate a wake event or interrupt when the GMAC1_EN bit is valid.

5

GMAC0_STS - R/WC

+

0: Software writes 1 to clear this bit.

+

1: These bits are set when a wake event occurs in GMAC0 and generate a wake event or interrupt when the GMAC0_EN bit is valid.

4

LID_STS - R/WC

+

0: Software writes 1 to clear this bit.

+

1: When the LID_EN bit is valid, a wake-up event is generated.

3

CTW_STS - R/WC

+

Thermal warning is generated.

2

CTA_STS - R/WC

+

Thermal alert is generated.

1

PWRSWITCH_STS - R/WC

+

The PWRTYP changes when the power supply status changes. +This bit generates an interrupt.

0

Reserved

+
+

GPE0_EN: General Purpose Event0 Enable Register

+
+ + ++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 185. General purpose event0 enable register

Address Offset

Voltage Field

Attribute

0x2C

RESUME/RTC

R/W

Bit Field

Description

Voltage Field

31:16

Reserved

15:10

USB[5 :0]_EN - R/W

+

0: Invalid.

+

1: Enable USBx_STS to wake-up event that will generate an interrupt signal when returning to S0.

9

Reserved

8

RI_EN - R/W

+

0: Invalid.

+

1: Enable RIn_STS wake-up event that will generate an interrupt signal when returning to S0.

RTC

7

BATLOW_EN - R/W

+

0: Invalid.

+

1: Enable BATLOWn interrupt event.

RTC

6

GMAC1_EN - R/W

+

0: Invalid.

+

1: Enable GMAC1_STS wake-up event, which will generate an interrupt signal when returning to S0.

RTC

5

GMAC0_EN - R/W

+

0: Invalid.

+

1: Enable GMAC0_STS wake-up event, which will generate an interrupt signal when returning to S0.

4

LID_EN - R/W

+

0: Invalid.

+

1: Enable LID_STS wake-up event, and an interrupt signal will be generated when S0 state.

3

CTW_EN - R/W

+

Enable THERMAL WARNING interrupt.

2

CTA_EN - R/W

+

Enable THERMAL ALERT interrupt.

1

PWRSWITCH_EN - R/W

+

Enable PWRSWITCH_STS interrupt.

0

LID_POL - R/W

+

This bit sets the polarity of the LID.

+
+

RST_CNT: Reset Control Register

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 186. Reset control register

Address Offset

Voltage Field

Attribute

0x30

SOC

R/W

Bit Field

Description

31:2

Reserved

1

WD_EN - R/W

+

Watch dog function enable.

0

OS_RST - R/W

+

Software writes this bit to reset the system.

+
+

WD_SET : Watch Dog Set Register

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + +
Table 187. Watch dog set register

Address Offset

Voltage Field

Attribute

0x34

SOC

WO

Bit Field

Description

31:1

Reserved

0

When WD_EN is 1, writing this bit will refill the internal watch dog counter with the value of WD_Timer. +Note that the watch dog counter operates at 50MHz.

+
+

WD_Timer: Watch Dog Timer Register

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + +
Table 188. Watch dog timer register

Address Offset

Voltage Field

Attribute

0x38

SOC

R/W

Bit Field

Description

31:0

The value of this register is the watch dog refill value, and the reset value is all 1s.

+
+

GEN_RTC_1: General RTC Register 1

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + +
Table 189. General RTC register 1

Address Offset

Voltage Field

Attribute

0x50

RTC

R/W

Bit Field

Description

31:0

RTC general purpose register.

+
+

GEN_RTC_2: General RTC Register 2

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + +
Table 190. General RTC register 2

Address Offset

Voltage Field

Attribute

0x54

RTC

R/W

Bit Field

Description

31:0

RTC general purpose register.

+
+
+
+
+

13. RTC

+
+
+

The Real Time Clock (RTC) unit can be configured when the motherboard is powered up, and when the motherboard is powered down, the unit still operates and can run normally on the on-board battery power alone. +The RTC unit operates with only a few microamps of current.

+
+
+

The RTC contains an oscillator, which in combination with an external 32.768KHZ crystal generates the operating clock. +This clock is used for time information maintenance and is used to maintain time information and to generate various timing and counting interrupts.

+
+
+

The RTC module contains two counters, the TOY (Time of Year) counter and the RTC counter. +The TOY counter counts in years, months, hours, minutes and seconds with an accuracy of 0.1s. +The RTC counter counts at 32.768KHz and is 32-bit length.

+
+
+

13.1. Access Address

+
+

The base address of accessing the RTC module is the base address of the MISC low-speed device block plus an offset of 0x50100.

+
+
+

Note: The RTC module only supports access by 4 bytes.

+
+
+

The physical address composition of the RTC module internal registers is as follows.

+
+ + +++++ + + + + + + + + + + + + + + + + + + + + + + + + +
Table 191. The physical address composition of the RTC module internal registers
Address bitsCompositionNote

[15:9]

0

Reserved

[8]

1

Reserved

[7:0]

REG

Internal registers address

+
+
+

13.2. Description of Registers

+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 192. List of RTC registers
NameOffset addressLengthRead/WriteDescription

sys_toytrim

0x20

32

R/W

Software must initialize it to 0

sys_toywrite0

0x24

32

WO

TOY low 32 bits input

sys_toywrite1

0x28

32

WO

TOY high 32 bits input

sys_toyread0

0x2C

32

RO

TOY low 32 bits output

sys_toyread1

0x30

32

RO

TOY high 32 bits output

sys_toymatch0

0x34

32

R/W

TOY timer interrupt 0

sys_toymatch1

0x38

32

R/W

TOY timer interrupt 1

sys_toymatch2

0x3C

32

R/W

TOY timer interrupt 2

sys_rtcctrl

0x40

32

R/W

TOY and RTC control registers

+

Software must initialize them

sys_rtctrim

0x60

32

R/W

Software must initialize it to 0

sys_rtcwrite0

0x64

32

WO

RTC timer counter input

sys_rtcread0

0x68

32

RO

RTC timer counter output

sys_rtcmatch0

0x6C

32

R/W

RTC clock timer interrupt 0

sys_rtcmatch1

0x70

32

R/W

RTC clock timer interrupt 1

sys_rtcmatch2

0x74

32

R/W

RTC clock timer interrupt 2

+
+

13.2.1. SYS_TOYWRITE0

+
+

Address Offset: 24-27h

+
+
+

Attribute: WO

+
+
+

Default value: N/A

+
+
+

Size: 4

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 193. SYS_TOYWRITE0
Bit FieldNameRead/WriteDescription

31:26

TOY_MONTH

WO

Month, range 1-12

25:21

TOY_DAY

WO

Day, range 1-31

20:16

TOY_HOUR

WO

Hour, range 0-23

15:10

TOY_MIN

WO

Minute, range 0-59

9:4

TOY_SEC

WO

Second, range 0-59

3:0

TOY_MILLISEC

WO

0.1 Second, range 0-9

+
+
+

13.2.2. SYS_TOYWRITE1

+
+

Address Offset: 28-2Bh

+
+
+

Attribute: WO

+
+
+

Default value: N/A

+
+
+

Size: 4

+
+ + ++++++ + + + + + + + + + + + + + + + + +
Table 194. SYS_TOYWRITE1
Bit FieldNameRead/WriteDescription

31:0

TOY_YEAR

WO

Year, range 0-16383

+
+
+

13.2.3. SYS_TOYREAD0

+
+

Address Offset: 2C-2Fh

+
+
+

Attribute: RO

+
+
+

Default value: 00000000h

+
+
+

Size: 4

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 195. SYS_TOYREAD0
Bit FieldNameRead/WriteDescription

31:26

TOY_MONTH

RO

Month, range 1-12

25:21

TOY_DAY

RO

Day, range 1-31

20:16

TOY_HOUR

RO

Hour, range 0-23

15:10

TOY_MIN

RO

Minute, range 0-59

9:4

TOY_SEC

RO

Second, range 0-59

3:0

TOY_MILLISEC

RO

0.1 Second, range 0-9

+
+
+

13.2.4. SYS_TOYREAD1

+
+

Address Offset: 30-33h

+
+
+

Attribute: RO

+
+
+

Default value: 00000000h

+
+
+

Size: 4

+
+ + ++++++ + + + + + + + + + + + + + + + + +
Table 196. SYS_TOYREAD1
Bit FieldNameRead/WriteDescription

31:0

TOY_YEAR

RO

Year, range 0-16383

+
+
+

13.2.5. SYS_TOYMATCH0

+
+

Address Offset: 34-37h

+
+
+

Attribute: R/W

+
+
+

Default value: 00000000h

+
+
+

Size: 4

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 197. SYS_TOYMATCH0
Bit FieldNameRead/WriteDescription

31:26

YEAR

R/W

Year, range 0-16383

25:22

MONTH

R/W

Month, range 1-12

21:17

DAY

R/W

Day, range 1-31

16:12

HOUR

R/W

Hour, range 0-23

11:6

MIN

R/W

Minute, range 0-59

5:0

SEC

R/W

Second, range 0-59

+
+
+

13.2.6. SYS_TOYMATCH1

+
+

Address Offset: 38-3Bh

+
+
+

Attribute: R/W

+
+
+

Default value: 00000000h

+
+
+

Size: 4

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 198. SYS_TOYMATCH1
Bit FieldNameRead/WriteDescription

31:26

YEAR

R/W

Year, range 0-16383

25:22

MONTH

R/W

Month, range 1-12

21:17

DAY

R/W

Day, range 1-31

16:12

HOUR

R/W

Hour, range 0-23

11:6

MIN

R/W

Minute, range 0-59

5:0

SEC

R/W

Second, range 0-59

+
+
+

13.2.7. SYS_TOYMATCH2

+
+

Address Offset: 3C-3Fh

+
+
+

Attribute: R/W

+
+
+

Default value: 00000000h

+
+
+

Size: 4

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 199. SYS_TOYMATCH2
Bit FieldNameRead/WriteDescription

31:26

YEAR

R/W

Year, range 0-16383

25:22

MONTH

R/W

Month, range 1-12

21:17

DAY

R/W

Day, range 1-31

16:12

HOUR

R/W

Hour, range 0-23

11:6

MIN

R/W

Minute, range 0-59

5:0

SEC

R/W

Second, range 0-59

+
+
+

13.2.8. SYS_RTCCTRL

+
+

Address Offset: 40-43h

+
+
+

Attribute: RO, R/W

+
+
+

Default value: 00000000h

+
+
+

Size: 4

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 200. SYS_RTCCTRL
Bit FieldNameRead/WriteDescription

31:24

Reserved

RO

Reserved

23

ERS

RO

REN (bit 13) write status

22:21

Reserved

RO

Reserved

20

RTS

RO

Sys_rtctrim write status

19

RM2

RO

Sys_rtcmatch2 write status

18

RM2

RO

Sys_rtcmatch2 write status

17

RM0

RO

Sys_rtcmatch0 write status

16

RS

RO

Sys_rtcwrite write status

15:14

Reserved

RO

Reserved

13

REN

R/W

RTC enable (active high).

+

Needs to be initialized to 1

12

Reserved

RO

Reserved

11

TEN

R/W

TOY enable (active high).

+

Needs to be initialized to 1

10:9

Reserved

RO

Reserved

8

EO

R/W

0: 32.768k crystal oscillation disable

+

1: 32.768k crystal oscillation enable

7:6

Reserved

RO

Reserved

5

Status

RO

32K crystal oscillation work state.

+

0: 32.768k crystal oscillation not work

+

1: 32.768k crystal oscillation working properly

4

Reserved

RO

Reserved

3

TM2

RO

Sys_toymatch2 write state

2

TM1

RO

Sys_toymatch1 write state

1

TM0

RO

Sys_toymatch0 write state

0

TS

RO

Sys_toywrite write state

+
+
+

13.2.9. SYS_RTCWRITE

+
+

Address Offset: 64-67h

+
+
+

Attribute: WO

+
+
+

Default value: N/A

+
+
+

Size: 4

+
+ + ++++++ + + + + + + + + + + + + + + + + +
Table 201. SYS_RTCWRITE
Bit FieldNameRead/WriteDescription

31:0

RTCWRITE

WO

RTC counter input register

+
+
+

13.2.10. SYS_RTCREAD

+
+

Address Offset: 68-6Bh

+
+
+

Attribute: RO

+
+
+

Default value: 00000000h

+
+
+

Size: 4

+
+ + ++++++ + + + + + + + + + + + + + + + + +
Table 202. SYS_RTCREAD
Bit FieldNameRead/WriteDescription

31:0

RTCREAD

RO

RTC counter output register

+
+
+

13.2.11. SYS_RTCMATCH0

+
+

Address Offset: 6C-6Fh

+
+
+

Attribute: R/W

+
+
+

Default value: 00000000h

+
+
+

Size: 4

+
+ + ++++++ + + + + + + + + + + + + + + + + +
Table 203. SYS_RTCMATCH0
Bit FieldNameRead/WriteDescription

31:0

RTCMATCH0

R/W

RTC timer comparison register 0

+
+
+

13.2.12. SYS_RTCMATCH1

+
+

Address Offset: 70-73h

+
+
+

Attribute: R/W

+
+
+

Default value: 00000000h

+
+
+

Size: 4

+
+ + ++++++ + + + + + + + + + + + + + + + + +
Table 204. SYS_RTCMATCH1
Bit FieldNameRead/WriteDescription

31:0

RTCMATCH1

R/W

RTC timer comparison register 1

+
+
+

13.2.13. SYS_RTCMATCH2

+
+

Address Offset: 74-77h

+
+
+

Attribute: R/W

+
+
+

Default value: 00000000h

+
+
+

Size: 4

+
+ + ++++++ + + + + + + + + + + + + + + + + +
Table 205. SYS_RTCMATCH2
Bit FieldNameRead/WriteDescription

31:0

RTCMATCH2

R/W

RTC timer comparison register 2

+
+
+
+
+
+

14. GPIO

+
+
+

The bridge chip has 57 GPIO pins, GPIO00 is a dedicated GPIO pin, and the remaining 56 are multiplexed with other functions. +Each GPIO pin is controlled by a set of control registers, including: GPIO direction control (GPIO_OEN), GPIO output (GPIO_O), GPIO input (GPIO_I), and GPIO input interrupt enable control (GPIO_INT_EN).

+
+ + +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 206. GPIO control register
RegisterSize (bit)Description

GPIO_OEN

1

GPIO output enable (active low).

GPIO_O

1

GPIO output.

GPIO_I

1

GPIO input.

GPIO_INT_EN

1

GPIO interrupt enable.

+
+

14.1. Access Address

+
+

The base address of accessing the GPIO module is the base address of the MISC low-speed device block plus an offset of 0x60000.

+
+
+

Note: The GPIO module only supports access by 1 byte.

+
+
+

The bridge chip provides two ways to control the GPIO pins. +One is to control each GPIO pin by bit and the other is to control each GPIO pin by byte. +The bridge chip does this by providing two address spaces to map the GPIO control registers. +One is a per-bit mapping and the other is a per-byte indexing of each bit of the control register. +Correspondingly, the GPIO internal address space is divided into two parts.

+
+
+

The latter way is recommended for the GPIO controller pins.

+
+
+

The physical address composition of the GPIO module internal registers is as follows.

+
+ + ++++ + + + + + + + + + + + + + + + + +
Table 207. The physical address composition of the GPIO module internal registers
Address spaceDescription

0x800-0xC00

Address of byte control register

0x0-0x40

Address of bit control register

+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 208. Address of GPIO bit control configuration register
Address OffsetRegisterSize (bit)Description

0x00

GPIO_OEN

57

GPIO output enable (active low). +Each bit controls one GPIO pin.

0x10

GPIO_O

57

GPIO output. +Each bit controls one GPIO pin.

0x20

GPIO_I

57

GPIO input. +Each bit controls one GPIO pin.

0x30

GPIO_INT_EN

57

GPIO interrupt enable. +Each bit controls one GPIO pin.

+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 209. Address of GPIO byte control configuration register
Address OffsetRegisterSize (bit)Description

0x800

GPIO_OEN

57

GPIO output enable (active low). +Each byte controls one GPIO pin, bit 0 is valid.

0x900

GPIO_O

57

GPIO output. +Each byte controls one GPIO pin, bit 0 is valid.

0xA00

GPIO_I

57

GPIO input. +Each byte controls one GPIO pin, bit 0 is valid.

0xB00

GPIO_INT_EN

57

GPIO interrupt enable. +Each byte controls one GPIO pin, bit 0 is valid.

+
+

For example, the output input direction of GPIO03 can be controlled either by bit[3] with offset address 0x0 (taking care not to affect other bits) or by a byte with offset address 0x803 (only bit[0] is valid).

+
+
+
+

14.2. Description of Registers

+
+

GPIO Direction Control

+
+
+

Address Offset: 00-03h

+
+
+

Attribute: R/W

+
+
+

Default value: FFFFFFF0h

+
+
+

Size: 4

+
+ + ++++++ + + + + + + + + + + + + + + + + +
Table 210. GPIO direction control
Bit FieldNameRead/WriteDescription

31:0

GPIO_OEN

R/W

Corresponds to the direction control of GPIO[31:0].

+

0: Output

+

1: Input

+
+

Address Offset: 04-07h

+
+
+

Attribute: R/W

+
+
+

Default value: FFFFFFFFh

+
+
+

Size: 4

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + +
Table 211. GPIO direction control
Bit FieldNameRead/WriteDescription

31:26

Reserved

R/W

Reserved.

25:0

GPIO_OEN

R/W

Corresponds to the direction control of GPIO[57:32].

+

0: Output

+

1: Input

+
+

GPIO Output

+
+
+

Address Offset: 00-03h

+
+
+

Attribute: R/W

+
+
+

Default value: 0000000Fh

+
+
+

Size: 4

+
+ + ++++++ + + + + + + + + + + + + + + + + +
Table 212. GPIO output
Bit FieldNameRead/WriteDescription

31:0

GPIO_O

R/W

Corresponds to the output of GPIO[31:0].

+
+

Address Offset: 04-07h

+
+
+

Attribute: R/W

+
+
+

Default value: 00000000h

+
+
+

Size: 4

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + +
Table 213. GPIO output
Bit FieldNameRead/WriteDescription

31:26

Reserved

R/W

Reserved.

25:0

GPIO_O

R/W

Corresponds to the output of GPIO[57:32].

+
+

GPIO Input

+
+
+

Address Offset: 00-03h

+
+
+

Attribute: RO

+
+
+

Default value: N/A

+
+
+

Size: 4

+
+ + ++++++ + + + + + + + + + + + + + + + + +
Table 214. GPIO input
Bit FieldNameRead/WriteDescription

31:0

GPIO_I

RO

Corresponds to the input of GPIO[31:0].

+
+

Address Offset: 04-07h

+
+
+

Attribute: RO

+
+
+

Default value: 00000000h

+
+
+

Size: 4

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + +
Table 215. GPIO input
Bit FieldNameRead/WriteDescription

31:26

Reserved

R/W

Reserved.

25:0

GPIO_I

RO

Corresponds to the input of GPIO[57:32].

+
+

GPIO Interrupt Enable

+
+
+

Address Offset: 00-03h

+
+
+

Attribute: R/W

+
+
+

Default value: 00000000h

+
+
+

Size: 4

+
+ + ++++++ + + + + + + + + + + + + + + + + +
Table 216. GPIO interrupt enable
Bit FieldNameRead/WriteDescription

31:0

GPIO_OEN

R/W

Corresponds to the interrupt enable of GPIO[31:0].

+

0: Disable interrupt

+

1: Enable interrput

+
+

Address Offset: 04-07h

+
+
+

Attribute: R/W

+
+
+

Default value: 00000000h

+
+
+

Size: 4

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + +
Table 217. GPIO interrupt enable
Bit FieldNameRead/WriteDescription

31:26

Reserved

R/W

Reserved.

25:0

GPIO_OEN

R/W

Corresponds to the interrupt enable of GPIO[57:32].

+

0: Disable interrupt

+

1: Enable interrput

+
+
+
+
+

15. GMAC Controller (D3:F0, D3:F1)

+
+
+

The bridge integrates two GMAC controllers, which have the same functions.

+
+
+

Note: See Notes on the Use of the Software for software enablement of 64-bit DMA for the GMAC controllers.

+
+
+

15.1. GMAC Configuration Register (D3:F0, D3:F1)

+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 218. GMAC controller configuration registers
Address OffsetAbbreviationDescriptionDefault valueRead/Write

00h-01h

VID

Vendor ID

0014h

RO

02h-03h

DID

Device ID

7A03h

RO

04h-05h

PCICMD

PCI Command

0000h

R/W, RO

08h

RID

Revision ID

00h

RO

09h

PI

Programming Interface

00h

RO

0Ah

SCC

Sub Class Code

00h

RO

0Bh

BCC

Base Class Code

02h

RO

0Ch

CLS

Cache Line Size

00h

RO

0Eh

HEADTYP

Header Type

80h

RO

10h-17h

CNL_BAR

Control Block Base Address Register

0000000000000004h

R/W, RO

2Ch-2Dh

SVID

Subsystem Vendor ID

0000h

RO

2Eh-2Fh

SID

Subsystem Identification

0000h

RO

3Ch

INT_LN

Interrupt Line

00h

R/W

3Dh

INT_PN

Interrupt Pin

01h

RO

+
+

Note: Address space not listed in the table indicates reserved.

+
+
+

Registers that differ slightly from the PCI configuration header specification and their descriptions are listed below.

+
+
+

PCICMD - PCI Command Register (GMAC - D3:F0, D3:F1)

+
+
+

Address Offset: 04-05h

+
+
+

Attribute: R/W, RO

+
+
+

Default value: 0000h

+
+
+

Size: 16 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 219. PCI command register
Bit FieldNameRead/WriteDescription

15:2

Reserved

RO

Reserved.

1

Memory Space Enable

R/W

This bit is used to control whether access to the GMAC control registers is enabled.

+

0: Disable access.

+

1: Enable access to the GMAC control registers. +The BAR register must be configured before this bit can be configured to 1.

0

Reserved

RO

Reserved.

+
+

CNL_BAR - Control Base Address Register

+
+
+

This register is used to configure the base address of the control registers of the GMAC controller.

+
+
+

Address Offset: 10-13h

+
+
+

Attribute: R/W, RO

+
+
+

Default value: 00000004h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 220. Control base address register
Bit FieldNameRead/WriteDescription

31:15

Base Address

RW

The software writes to this register field the low address of the base address allocated to the GMAC control register.

14:4

Memory Size

RO

The address space size of GMAC control register is 32KB.

3

Prefetchable Memory

RO

Set to 0 to indicate that it is not prefetchable.

2:1

Memory Type

RO

Set to 10b to indicate 64-bit BAR.

0

Memory/ I/O Space

RO

Set to 0 to indicate Memory space BAR.

+
+

Address Offset: 14-17h

+
+
+

Attribute: R/W

+
+
+

Default value: 00000000h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + +
Table 221. Control base address register
Bit FieldNameRead/WriteDescription

31:0

Base Address

RW

The software writes to this register field the high 32-bit address of the base address allocated to the GMAC control register.

+
+
+
+
+

16. USB Controller (D4:F0/1, D5:F0/1)

+
+
+

The bridge contains two USB controllers, each containing three ports.

+
+
+

The USB ports of the bridge have the following features.

+
+
+
    +
  • +

    Compatible with USB Rev 1.1, USB Rev 2.0 protocols

    +
    • +
  • +

    Compatible with OHCI Rev 1.0, EHCI Rev 1.0 protocols

    +
    • +
  • +

    Supports LS (Low Speed), FS (Full Speed) and HS (High Speed) USB devices

    +
    • +
  • +

    Works in Host mode, OTG mode is not supported

    +
    • +
+
+
+

Each USB controller module of the bridge includes an EHCI controller and an OHCI controller, with each EHCI controller and OHCI controller supporting 3 ports. +The EHCI controller is used by default, and control is transferred to the OHCI controller only when the hooked up device is a full-speed or low-speed device. +When a full-speed or low-speed device is unplugged, control is returned to the EHCI controller.

+
+
+

Note: The Memory Space Enable control for the OHCI and EHCI device headers of USB devices requires special handling, see Notes on the Use of the Software.

+
+
+

16.1. EHCI Controller

+
+

16.1.1. EHCI Configuration Register (D4:F1, D5:F1)

+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 222. USB-EHCI controller configuration registers
Address OffsetAbbreviationDescriptionDefault valueRead/Write

00h-01h

VID

Vendor ID

0014h

RO

02h-03h

DID

Device ID

7A14h

RO

04h-05h

PCICMD

PCI Command

0000h

R/W, RO

08h

RID

Revision ID

00h

RO

09h

PI

Programming Interface

20h

RO

0Ah

SCC

Sub Class Code

03h

RO

0Bh

BCC

Base Class Code

0Ch

RO

0Ch

CLS

Cache Line Size

00h

RO

0Eh

HEADTYP

Header Type

80h

RO

10h-17h

CNL_BAR

Control Block Base Address Register

0000000000000004h

R/W, RO

2Ch-2Dh

SVID

Subsystem Vendor ID

0000h

RO

2Eh-2Fh

SID

Subsystem Identification

0000h

RO

3Ch

INT_LN

Interrupt Line

00h

R/W

3Dh

INT_PN

Interrupt Pin

01h

RO

+
+

Note: Address space not listed in the table indicates reserved.

+
+
+

Registers that differ slightly from the PCI configuration header specification and their descriptions are listed below.

+
+
+

PCICMD - PCI Command Register (USB EHCI - D4:F1, D5:F1)

+
+
+

Address Offset: 04-05h

+
+
+

Attribute: R/W, RO

+
+
+

Default value: 0000h

+
+
+

Size: 16 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 223. PCI command register
Bit FieldNameRead/WriteDescription

15:2

Reserved

RO

Reserved.

1

Memory Space Enable

R/W

This bit is used to control whether access to the USB EHCI control registers is enabled.

+

0: Disable access.

+

1: Enable access to the USB EHCI control registers. +The BAR register must be configured before this bit can be configured to 1.

+

In rev. 00, this bit controls the Memory Space Enable of the OHCI. +The Memory Space Enable of the EHCI is controlled by the corresponding bit of the OHCI controller.

0

Reserved

RO

Reserved.

+
+

CNL_BAR - Control Base Address Register

+
+
+

This register is used to configure the base address of the control registers of the EHCI controller.

+
+
+

Address Offset: 10-13h

+
+
+

Attribute: R/W, RO

+
+
+

Default value: 00000004h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 224. Control base address register
Bit FieldNameRead/WriteDescription

31:15

Base Address

RW

The software writes to this register field the low address of the base address allocated to the EHCI control register.

14:4

Memory Size

RO

The address space size of EHCI control register is 32KB.

3

Prefetchable Memory

RO

Set to 0 to indicate that it is not prefetchable.

2:1

Memory Type

RO

Set to 10b to indicate 64-bit BAR.

0

Memory/ I/O Space

RO

Set to 0 to indicate Memory space BAR.

+
+

Address Offset: 14-17h

+
+
+

Attribute: R/W

+
+
+

Default value: 00000000h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + +
Table 225. Control base address register
Bit FieldNameRead/WriteDescription

31:0

Base Address

RW

Software writes to this register field the high 32-bit address of the base address allocated to the EHCI control register.

+
+

The bridge’s USB host controller is compatible with the EHCI Rev 1.0 protocol. +Refer to the Enhanced Host Controller Interface Rev 1.0 Specification for details of the Capability register and Operational register.

+
+
+
+
+

16.2. OHCI Controller

+
+

16.2.1. OHCI Configuration Register (D4:F0, D5:F0)

+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 226. USB-OHCI controller configuration registers
Address OffsetAbbreviationDescriptionDefault valueRead/Write

00h-01h

VID

Vendor ID

0014h

RO

02h-03h

DID

Device ID

7A24h

RO

04h-05h

PCICMD

PCI Command

0000h

R/W, RO

08h

RID

Revision ID

00h

RO

09h

PI

Programming Interface

10h

RO

0Ah

SCC

Sub Class Code

03h

RO

0Bh

BCC

Base Class Code

0Ch

RO

0Ch

CLS

Cache Line Size

00h

RO

0Eh

HEADTYP

Header Type

80h

RO

10h-17h

CNL_BAR

Control Block Base Address Register

0000000000000004h

R/W, RO

2Ch-2Dh

SVID

Subsystem Vendor ID

0000h

RO

2Eh-2Fh

SID

Subsystem Identification

0000h

RO

3Ch

INT_LN

Interrupt Line

00h

R/W

3Dh

INT_PN

Interrupt Pin

01h

RO

+
+

Note: Address space not listed in the table indicates reserved.

+
+
+

Registers that differ slightly from the PCI configuration header specification and their descriptions are listed below.

+
+
+

PCICMD - PCI Command Register (USB OHCI - D4:F0, D5:F0)

+
+
+

Address Offset: 04-05h

+
+
+

Attribute: R/W, RO

+
+
+

Default value: 0000h

+
+
+

Size: 16 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 227. PCI command register
Bit FieldNameRead/WriteDescription

15:2

Reserved

RO

Reserved.

1

Memory Space Enable

R/W

This bit is used to control whether access to the USB OHCI control registers is enabled.

+

0: Disable access.

+

1: Enable access to the USB OHCI control registers. +The BAR register must be configured before this bit can be configured to 1.

+

In rev. 00, this bit controls the Memory Space Enable of the EHCI. +The Memory Space Enable of the OHCI is controlled by the corresponding bit of the EHCI controller.

0

Reserved

RO

Reserved.

+
+

CNL_BAR - Control Base Address Register

+
+
+

This register is used to configure the base address of the control registers of the OHCI controller.

+
+
+

Address Offset: 10-13h

+
+
+

Attribute: R/W, RO

+
+
+

Default value: 00000004h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 228. Control base address register
Bit FieldNameRead/WriteDescription

31:15

Base Address

RW

The software writes to this register field the low address of the base address allocated to the OHCI control register.

14:4

Memory Size

RO

The address space size of OHCI control register is 32KB.

3

Prefetchable Memory

RO

Set to 0 to indicate that it is not prefetchable.

2:1

Memory Type

RO

Set to 10b to indicate 64-bit BAR.

0

Memory/ I/O Space

RO

Set to 0 to indicate Memory space BAR.

+
+

Address Offset: 14-17h

+
+
+

Attribute: R/W

+
+
+

Default value: 00000000h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + +
Table 229. Control base address register
Bit FieldNameRead/WriteDescription

31:0

Base Address

RW

Software writes to this register field the high 32-bit address of the base address allocated to the OHCI control register.

+
+

The bridge’s USB host controller is compatible with the OHCI Rev 1.0 protocol. +Refer to the Open Host Controller Interface Rev 1.0 Specification for details of the operational registers.

+
+
+
+
+
+
+

17. Graphics Processor (D6:F0)

+
+
+

17.1. GPU Configuration Register (D6:F0)

+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 230. GPU controller configuration registers
Address OffsetAbbreviationDescriptionDefault valueRead/Write

00h-01h

VID

Vendor ID

0014h

RO

02h-03h

DID

Device ID

7A15h

RO

04h-05h

PCICMD

PCI Command

0000h

R/W, RO

08h

RID

Revision ID

00h

RO

09h

PI

Programming Interface

00h

RO

0Ah

SCC

Sub Class Code

02h

RO

0Bh

BCC

Base Class Code

03h

RO

0Ch

CLS

Cache Line Size

00h

RO

0Eh

HEADTYP

Header Type

80h

RO

10h-17h

CNL_BAR

Control Block Base Address Register

0000000000000004h

R/W, RO

18h-1Fh

GMEM_BAR

Graphic Memory Base Address Register

0000000000000004h

R/W, RO

27h-20h

RSV_BAR

Reserved Base Address Register

0000000000000004h

R/W, RO

2Ch-2Dh

SVID

Subsystem Vendor ID

0000h

RO

2Eh-2Fh

SID

Subsystem Identification

0000h

RO

3Ch

INT_LN

Interrupt Line

00h

R/W

3Dh

INT_PN

Interrupt Pin

01h

RO

+
+

Note: Address space not listed in the table indicates reserved.

+
+
+

Registers that differ slightly from the PCI configuration header specification and their descriptions are listed below.

+
+
+

PCICMD - PCI Command Register (GPU - D6:F0)

+
+
+

Address Offset: 04-05h

+
+
+

Attribute: R/W, RO

+
+
+

Default value: 0000h

+
+
+

Size: 16 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 231. PCI command register
Bit FieldNameRead/WriteDescription

15:2

Reserved

RO

Reserved.

1

Memory Space Enable

R/W

This bit is used to control whether access to the GPU control registers is enabled.

+

0: Disable access.

+

1: Enable access to the GMAC control registers and GMEN space. +The BAR register must be configured before this bit can be configured to 1.

0

Reserved

RO

Reserved.

+
+

CNL_BAR - Control Base Address Register

+
+
+

This register is used to configure the base address of the control registers of the GMAC controller.

+
+
+

Address Offset: 10-13h

+
+
+

Attribute: R/W, RO

+
+
+

Default value: 00000004h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 232. Control base address register
Bit FieldNameRead/WriteDescription

31:18

Base Address

RW

Software writes to this register field the low address of the base address allocated to the GPU control register.

17:4

Memory Size

RO

The address space size of the GPU control registers is 32KB.

3

Prefetchable Memory

RO

Set to 0 to indicate that it is not prefetchable.

2:1

Memory Type

RO

Set to 10b to indicate 64-bit BAR.

0

Memory/ I/O Space

RO

Set to 0 to indicate Memory space BAR.

+
+

Address Offset: 14-17h

+
+
+

Attribute: R/W

+
+
+

Default value: 00000000h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + +
Table 233. Control base address register
Bit FieldNameRead/WriteDescription

31:0

Base Address

RW

Software writes to this register field the high 32-bit address of the base address allocated to the GPU control register.

+
+

GMEM_BAR - Video Memory Base Address Register

+
+
+

This register is used to configure the base address of the video memory.

+
+
+

Address Offset: 18-1Bh

+
+
+

Attribute: R/W, RO

+
+
+

Default value: 00000004h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 234. Video memory base address register
Bit FieldNameRead/WriteDescription

31:X

Base Address

RW

The software writes to this register field the low bit of the base address allocated to the video memory.

X:4

Memory Size

RO

The memory size is configured by the BIOS. +The maximum is not more than 512MB.

3

Prefetchable Memory

RO

Set to 0 to indicate that it is not prefetchable.

2:1

Memory Type

RO

Set to 10b to indicate 64-bit BAR.

0

Memory/ I/O Space

RO

Set to 0 to indicate Memory space BAR.

+
+

Address Offset: 1C-1Fh

+
+
+

Attribute: R/W

+
+
+

Default value: 00000000h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + +
Table 235. Video memory base address register
Bit FieldNameRead/WriteDescription

31:0

Base Address

RW

The software writes to this register field the high 32-bit address allocated to the base address of the video memory.

+
+

RSV_BAR - Reserved Window Base Address Register

+
+
+

This register is used to configure the base address of the reserved registers of the GPU controller.

+
+
+

Address Offset: 20-23h

+
+
+

Attribute: R/W, RO

+
+
+

Default value: 00000004h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 236. Reserved window base address register
Bit FieldNameRead/WriteDescription

31:18

Base Address

RW

The software writes to this register field the low address of the base address allocated to the GPU reserved register.

17:4

Memory Size

RO

The address space size of the GPU reserved registers is 256B.

3

Prefetchable Memory

RO

Set to 0 to indicate that it is not prefetchable.

2:1

Memory Type

RO

Set to 10b to indicate 64-bit BAR.

0

Memory/ I/O Space

RO

Set to 0 to indicate Memory space BAR.

+
+

Address Offset: 24-27h

+
+
+

Attribute: R/W

+
+
+

Default value: 00000000h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + +
Table 237. Reserved window base address register
Bit FieldNameRead/WriteDescription

31:0

Base Address

RW

The software writes to this register field the high 32-bit address of the base address allocated to the GPU reserved register.

+
+
+

17.2. DDR3 Memory Interface

+
+

The bridge chip’s integrated memory interface complies with the DDR3 SDRAM standard (JESD79-3).

+
+
+

The bridge supports 1 chip select, 16 row addresses, 15 column addresses, and 3 logical body addresses.

+
+
+

The bridge chip’s memory controller has the following characteristics.

+
+
+
    +
  • +

    Full-flow operation of commands, read and write data on the interface

    +
    • +
  • +

    Memory command merging and sorting to improve the overall bandwidth

    +
    • +
  • +

    Basic parameters of memory devices can be modified

    +
    • +
  • +

    Supports 133-667MHz clock frequency

    +
    • +
+
+
+

Access Address

+
+
+

The DDR3 memory controller consists of two address spaces: the memory space for video memory controller configuration register and the memory space for the video memory. +These two address spaces share the same address space (the video memory address space, the address space allocated to GMEM_BAR). +The final access to the memory address space is determined by the parameter disable_gmem_confspace — bit 3 of general configuration register 0 of the bridge configuration register addr_0x420[3].

+
+
+

When the configuration parameter disable_gmem_confspace = 0, all accesses to the memory are configuration register accesses. +When the configuration parameter disable_gmem_confspace = 1, the accesses to the memory are normal memory read and write accesses.

+
+
+
+
+
+

18. Display Controller (D6:F1)

+
+
+

The features supported by the display controller of the bridge include the following.

+
+
+
    +
  • +

    Dual DVO interface displays

    +
    • +
  • +

    Each display supports up to 1920x1080@60Hz

    +
    • +
  • +

    Two hardware cursors modes: Monochrome, ARGB8888

    +
    • +
  • +

    Four color depths: RGB444, RGB555, RGB565, RGB888

    +
    • +
  • +

    Output dithering and gamma correction

    +
    • +
  • +

    Switchable dual routability frame buffer

    +
    • +
  • +

    Interrupt and soft reset

    +
    • +
+
+
+

18.1. DC Configuration Register (D6:F1)

+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 238. DC controller configuration registers
Address OffsetAbbreviationDescriptionDefault valueRead/Write

00h-01h

VID

Vendor ID

0014h

RO

02h-03h

DID

Device ID

7A06h

RO

04h-05h

PCICMD

PCI Command

0000h

R/W, RO

08h

RID

Revision ID

00h

RO

09h

PI

Programming Interface

00h

RO

0Ah

SCC

Sub Class Code

03h

RO

0Bh

BCC

Base Class Code

0Ch

RO

0Ch

CLS

Cache Line Size

00h

RO

0Eh

HEADTYP

Header Type

80h

RO

10h-17h

CNL_BAR

Control Block Base Address Register

0000000000000004h

R/W, RO

2Ch-2Dh

SVID

Subsystem Vendor ID

0000h

RO

2Eh-2Fh

SID

Subsystem Identification

0000h

RO

3Ch

INT_LN

Interrupt Line

00h

R/W

3Dh

INT_PN

Interrupt Pin

01h

RO

+
+

Note: Address space not listed in the table indicates reserved.

+
+
+

Registers that differ slightly from the PCI configuration header specification and their descriptions are listed below.

+
+
+

PCICMD - PCI Command Register (DC - D6:F1)

+
+
+

Address Offset: 04-05h

+
+
+

Attribute: R/W, RO

+
+
+

Default value: 0000h

+
+
+

Size: 16 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 239. PCI command register
Bit FieldNameRead/WriteDescription

15:2

Reserved

RO

Reserved.

1

Memory Space Enable

R/W

This bit is used to control whether access to the DC control registers is enabled.

+

0: Disable access.

+

1: Enable access to the DC control registers. +The BAR register must be configured before this bit can be configured to 1.

0

Reserved

RO

Reserved.

+
+

CNL_BAR - Control Base Address Register

+
+
+

This register is used to configure the base address of the control registers of the GMAC controller.

+
+
+

Address Offset: 10-13h

+
+
+

Attribute: R/W, RO

+
+
+

Default value: 00000004h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 240. Control base address register
Bit FieldNameRead/WriteDescription

31:16

Base Address

RW

The software writes to this register field the low address of the base address assigned to the DC control register.

15:4

Memory Size

RO

The address space size of DC control register is 64KB.

3

Prefetchable Memory

RO

Set to 0 to indicate that it is not prefetchable.

2:1

Memory Type

RO

Set to 10b to indicate 64-bit BAR.

0

Memory/ I/O Space

RO

Set to 0 to indicate Memory space BAR.

+
+

Address Offset: 14-17h

+
+
+

Attribute: R/W

+
+
+

Default value: 00000000h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + +
Table 241. Control base address register
Bit FieldNameRead/WriteDescription

31:0

Base Address

RW

Software writes to this register field the high 32-bit address of the base address assigned to the DC control register.

+
+
+

18.2. DC Control Register

+
+

18.2.1. Display Detection Register

+
+

The 7A bridge contains two sets of I2C bus pins specifically for display detection. +These two sets of I2C bus pins need to be emulated by software using GPIO pins. +These two sets of GPIO pins differ from the GPIO pins in the MISC in that their control registers are placed in the control register space of the DC. +The I2C bus of DVO0 is controlled by bit[1:0] of the GPIO register, and the I2C bus of DVO1 is controlled by bit[3:2] of the GPIO register. +The correspondence between I2C pins and GPIO registers is shown in the following table.

+
+ + ++++ + + + + + + + + + + + + + + + + + + + + + + + + +
Table 242. Correspondence between the I2C pins of the DVO and the control registers
Pin NameGPIO control bit

DVO0_SDA

0

DVO0_SCL

1

DVO1_SDA

2

DVO1_SCL

3

+
+

Each GPIO control bit is controlled by three registers. +The addresses of the GPIO control registers are shown in the following table.

+
+ + ++++++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 243. DVO’s I2C pin control register address

Register Name

Address Offset

Read/Write

Description

Reset Value

GPIO_OUT

0x1650

WO

Output register

0h

GPIO_IN

0x1650

RO

Input register

N/A

GPIO_EN

0x1660

R/W

GPIO direction control register

0h

GPIO_OUT

Bit

Description

Initial Value

DVO0_SDA_OUT

0

Control the output value of the DVO0_SDA pin (write only)

0

DVO0_SCL_OUT

1

Control the output value of the DVO0_SCL pin (write only)

0

DVO1_SDA_OUT

2

Control the output value of the DVO1_SDA pin (write only)

0

DVO1_SCL_OUT

3

Control the output value of the DVO1_SCL pin (write only)

0

GPIO_IN

Bit

Description

Initial Value

DVO0_SDA_IN

0

Control the input value of the DVO0_SDA pin (read only)

N/A

DVO0_SCL_IN

1

Control the input value of the DVO0_SCL pin (write only)

N/A

DVO1_SDA_IN

2

Control the input value of the DVO1_SDA pin (write only)

N/A

DVO1_SCL_IN

3

Control the input value of the DVO1_SCL pin (write only)

N/A

GPIO_EN

Bit

Description

Initial Value

DVO0_SDA_EN

0

Control the direction of the DVO0_SDA pin (read/write)

0

DVO0_SCL_EN

1

Control the direction of the DVO0_SCL pin (read/write)

0

DVO1_SDA_EN

2

Control the direction of the DVO1_SDA pin (read/write)

0

DVO1_SCL_EN

3

Control the direction of the DVO1_SCL pin (read/write)

0

+
+
+
+
+
+

19. HDA Controller (D7:F0)

+
+
+

The HDA controller is compatible with High Definition Audio Specification Revision 1.0a.

+
+
+

See PLL1 Configuration Register for HDA-related pin setup registers.

+
+
+

19.1. HDA Configuration Register (D7:F0)

+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 244. HDA controller configuration registers
Address OffsetAbbreviationDescriptionDefault valueRead/Write

00h-01h

VID

Vendor ID

0014h

RO

02h-03h

DID

Device ID

7A07h

RO

04h-05h

PCICMD

PCI Command

0000h

R/W, RO

08h

RID

Revision ID

00h

RO

09h

PI

Programming Interface

00h

RO

0Ah

SCC

Sub Class Code

03h

RO

0Bh

BCC

Base Class Code

04h

RO

0Ch

CLS

Cache Line Size

00h

RO

0Eh

HEADTYP

Header Type

00h

RO

10h-17h

CNL_BAR

Control Block Base Address Register

0000000000000004h

R/W, RO

2Ch-2Dh

SVID

Subsystem Vendor ID

0000h

RO

2Eh-2Fh

SID

Subsystem Identification

0000h

RO

3Ch

INT_LN

Interrupt Line

00h

R/W

3Dh

INT_PN

Interrupt Pin

01h

RO

+
+

Note:

+
+
+
    +
  1. +

    The HDA configuration header is only visible when the relevant pin is configured for HDA mode.

    +
    2. +
  2. +

    Address space not listed in the table indicates reserved.

    +
    3. +
+
+
+

Registers that differ slightly from the PCI configuration header specification and their descriptions are listed below.

+
+
+

PCICMD - PCI Command Register (HDA - D7:F0)

+
+
+

Address Offset: 04-05h

+
+
+

Attribute: R/W, RO

+
+
+

Default value: 0000h

+
+
+

Size: 16 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 245. PCI command register
Bit FieldNameRead/WriteDescription

15:2

Reserved

RO

Reserved.

1

Memory Space Enable

R/W

This bit is used to control whether access to the HDA control registers is enabled.

+

0: Disable access.

+

1: Enable access to the HDA control registers. +The BAR register must be configured before this bit can be configured to 1.

0

Reserved

RO

Reserved.

+
+

CNL_BAR - Control Base Address Register

+
+
+

This register is used to configure the base address of the HDA controller’s control registers.

+
+
+

Address Offset: 10-13h

+
+
+

Attribute: R/W, RO

+
+
+

Default value: 00000004h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 246. Control base address register
Bit FieldNameRead/WriteDescription

31:16

Base Address

RW

Software writes to this register field the low address of the base address assigned to the HDA control register.

15:4

Memory Size

RO

The HDA control register has an address space size of 64KB.

3

Prefetchable Memory

RO

Set to 0 to indicate that it is not prefetchable.

2:1

Memory Type

RO

Set to 10b to indicate 64-bit BAR.

0

Memory/ I/O Space

RO

Set to 0 to indicate Memory space BAR.

+
+

Address Offset: 14-17h

+
+
+

Attribute: R/W

+
+
+

Default value: 00000000h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + +
Table 247. Control base address register
Bit FieldNameRead/WriteDescription

31:0

Base Address

RW

The software writes to this register field the high 32-bit address assigned to the base address of the HDA control register.

+
+
+

19.2. Description of HDA Control Register

+
+

The HDA control registers are designed in full accordance with the HD audio Rev 1.0 specification. +The following table lists the main register parameters.[1] +Refer to the HD audio Rev 1.0 manual for details.

+
+
+
+
+
+

20. AC97 Controller (D7:F1)

+
+
+

20.1. AC97 Configuration Register (D7:F1)

+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 248. AC97 controller configuration registers
Address OffsetAbbreviationDescriptionDefault valueRead/Write

00h-01h

VID

Vendor ID

0014h

RO

02h-03h

DID

Device ID

7A17h

RO

04h-05h

PCICMD

PCI Command

0000h

R/W, RO

08h

RID

Revision ID

00h

RO

09h

PI

Programming Interface

00h

RO

0Ah

SCC

Sub Class Code

01h

RO

0Bh

BCC

Base Class Code

04h

RO

0Ch

CLS

Cache Line Size

00h

RO

0Eh

HEADTYP

Header Type

00h

RO

10h-17h

CNL_BAR

Control Block Base Address Register

0000000000000004h

R/W, RO

2Ch-2Dh

SVID

Subsystem Vendor ID

0000h

RO

2Eh-2Fh

SID

Subsystem Identification

0000h

RO

3Ch

INT_LN

Interrupt Line

00h

R/W

3Dh

INT_PN

Interrupt Pin

01h

RO

+
+

Note:

+
+
+
    +
  1. +

    The AC97 configuration header is only visible when the relevant pin is configured for AC97 mode.

    +
    2. +
  2. +

    Address space not listed in the table indicates reserved.

    +
    3. +
+
+
+

Registers that differ slightly from the PCI configuration header specification and their descriptions are listed below.

+
+
+

PCICMD - PCI Command Register (AC97 - D7:F1)

+
+
+

Address Offset: 04-05h

+
+
+

Attribute: R/W, RO

+
+
+

Default value: 0000h

+
+
+

Size: 16 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 249. PCI command register
Bit FieldNameRead/WriteDescription

15:2

Reserved

RO

Reserved.

1

Memory Space Enable

R/W

This bit is used to control whether access to the AC97 control registers is enabled.

+

0: Disable access.

+

1: Enable access to the AC97 control registers. +The BAR register must be configured before this bit can be configured to 1.

0

Reserved

RO

Reserved.

+
+

CNL_BAR - Control Base Address Register

+
+
+

This register is used to configure the base address of the control registers of the AC97 control register.

+
+
+

Address Offset: 10-13h

+
+
+

Attribute: R/W, RO

+
+
+

Default value: 00000004h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 250. Control base address register
Bit FieldNameRead/WriteDescription

31:16

Base Address

RW

The software writes to this register field the low address of the base address allocated to the AC97 control register.

15:4

Memory Size

RO

The address space size of AC97 control register is 64KB.

3

Prefetchable Memory

RO

Set to 0 to indicate that it is not prefetchable.

2:1

Memory Type

RO

Set to 10b to indicate 64-bit BAR.

0

Memory/ I/O Space

RO

Set to 0 to indicate Memory space BAR.

+
+

Address Offset: 14-17h

+
+
+

Attribute: R/W

+
+
+

Default value: 00000000h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + +
Table 251. Control base address register
Bit FieldNameRead/WriteDescription

31:0

Base Address

RW

The software writes to this register field the high 32-bit address of the base address allocated to the AC97 control register.

+
+
+

20.2. AC97 Controller Register

+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 252. List of AC97 control registers
Address OffsetAbbreviationDescriptionDefault ValueRead/Write

00h-01h

VID

Vendor ID

0014h

RO

02h-03h

DID

Device ID

7A17h

RO

04h-05h

PCICMD

PCI Command

0000h

R/W, RO

08h

RID

Revision ID

00h

RO

09h

PI

Programming Interface

00h

RO

0Ah

SCC

Sub Class Code

01h

RO

0Bh

BCC

Base Class Code

04h

RO

0Ch

CLS

Cache Line Size

00h

RO

0Eh

HEADTYP

Header Type

00h

RO

10h-17h

CNL_BAR

Control Block Base Address Register

0000000000000004h

R/W, RO

2Ch-2Dh

SVID

Subsystem Vendor ID

0000h

RO

2Eh-2Fh

SID

Subsystem Identification

0000h

RO

3Ch

INT_LN

Interrupt Line

00h

R/W

3Dh

INT_PN

Interrupt Pin

01h

RO

+
+

CSR Register

+
+
+

Offset address: 0x00

+
+
+

Reset value: 0x00000000

+
+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 253. CSR register
Bit FieldNameLengthRead/WriteDescription

31:2

Reserved

30

RO

Reserved.

1

RESUME

1

R/W

Hanging. +Read this bit to return the current state of the AC97 subsystem.

+

1: AC97 subsystem hanged

+

0: Normal operating state

+

Writing 1 to this bit in the pending state will start the recovery operation.

0

RST_FORCE

1

W

AC97 cold boot.

+

Writing 1 will cause the AC97 Codec to cold boot.

+
+

OCC Register

+
+
+

Offset address: 0x04

+
+
+

Reset value: 0x00004141

+
+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 254. OCC register
Bit FieldNameLengthRead/WriteDescription

31:24

Reserved

10

R/W

Reserved.

23:16

Reserved

10

R/W

Reserved.

15:10

OC1_CFG_R

10

R/W

Output channel 1: Right channel configuration.

7:0

OC0_CFG_L

10

R/W

Output channel 0: Left channel configuration.

+
+

ICC Register

+
+
+

Offset address: 0x10

+
+
+

Reset value: 0x00410000

+
+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 255. ICC register
Bit FieldNameLengthRead/WriteDescription

31:24

Reserved

10

R/W

Reserved.

23:16

IC_CFG_MIC

10

R/W

Input channel 2: MIC channel configuration.

15:10

Reserved

10

R/W

Reserved.

7:0

Reserved

10

R/W

Reserved.

+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 256. Description of the sound channel format
Bit FieldNameLengthRead/WriteDescription

7

Reserved

1

R/W

Reserved.

6

DMA_EN

1

R/W

DMA enable.

+

1: DMA enable.

+

0: DMA disable.

5:4

FIFO_THRES

2

R/W

+

FIFO threshold

+
+ +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + +

5:4

Output channel

Input channel

00

FIFO 1/4 empty

FIFO 1/4 full

01

FIFO 1/2 empty

FIFO 1/2 full

10

FIFO 3/4 empty

FIFO 3/4 full

11

FIFO empty

FIFO full

3:2

SW

2

R/W

Number of sampling bits

+

00: 10 bits

+

10: 16 bits

1

VSR

1

R/W

Sampling rate

+

1: Variable sampling rate

+

0: Fixed sampling rate (410KHz)

0

CH_EN

1

R/W

Channel enable

+

1: Channel enable

+

0: Channel disable (or go to energy-saving state)

+
+

Codec Register Access Command

+
+
+

Offset address: 0x110

+
+
+

Reset value: 0x00000000

+
+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 257. Codec register access command
Bit FieldNameLengthRead/WriteDescription

31

CODEC_WR

1

R/W

Read/write selection

+

1: Read. +When reading data, first set CODEC_WR to read mode, and set the register address you want to access in CODEC_ADR. +Wait until the return data completes interrupt and then read the CODEC_DAT register to read the value.

+

0: Write.

30:23

Reserved

10

R

Reserved.

22:16

CODEC_ADR

7

R/W

Codec register address

15:0

CODEC_DAT

16

R/W

Codec register data

+
+

Interrupt Status Register/Interrupt Mask Register

+
+
+

Offset address: 0x54/510

+
+
+

Reset value: 0x00000000

+
+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 258. Interrupt Status Register/Interrupt Mask Register
Bit FieldNameLengthRead/WriteDescription

31

IC_FULL

1

R/W

Input channel 2: FIFO full

30

IC_TH_INT

1

R/W

Input channel 2: FIFO reaches threshold

29:10

Reserved

22

R/W

Reserved.

7

OC1_FULL

1

R/W

Output channel 1: FIFO full

6

OC1_EMPTY

1

R/W

Output channel 1: FIFO empty

5

OC1_ TH_INT

1

R/W

Output channel 1: FIFO reaches threshold

4

OC0_FULL

1

R/W

Output channel 0: FIFO full

3

OC0_EMPTY

1

R/W

Output channel 0: FIFO empty

2

OC0_ TH_INT

1

R/W

Output channel 0: FIFO reaches threshold

1

CW_DONE

1

R/W

Codec register write complete

0

CR_DONE

1

R/W

Codec register read complete

+
+

Interrupt Status/Clear Register

+
+
+

Offset address: 0x5c

+
+
+

Reset value: 0x00000000

+
+ + +++++++ + + + + + + + + + + + + + + + + + + +
Table 259. Interrupt status/clear register
Bit FieldNameLengthRead/WriteDescription

31:0

INT_CLR

32

RO

After masking the interrupt status register, a read of this register will clear all interrupt status in register 0x54.

+
+

OC Interrupt Clear Register

+
+
+

Offset address: 0x60

+
+
+

Reset value: 0x00000000

+
+ + +++++++ + + + + + + + + + + + + + + + + + + +
Table 260. OC interrupt clear register
Bit FieldNameLengthRead/WriteDescription

31:0

INT_OC_CLR

32

RO

A read operation of this register will clear the bits[7:2] corresponding to the interrupt status of all output channels in register 0x54.

+
+

IC Interrupt Clear Register

+
+
+

Offset address: 0x64

+
+
+

Reset value: 0x00000000

+
+ + +++++++ + + + + + + + + + + + + + + + + + + +
Table 261. IC interrupt clear register
Bit FieldNameLengthRead/WriteDescription

31:0

INT_IC_CLR

32

RO

A read operation of this register will clear the bits[31:30] corresponding to the interrupt status of all input channels in register 0x54.

+
+

CODEC WRITE Interrupt Clear Register

+
+
+

Offset address: 0x610

+
+
+

Reset value: 0x00000000

+
+ + +++++++ + + + + + + + + + + + + + + + + + + +
Table 262. CODEC WRITE interrupt clear register
Bit FieldNameLengthRead/WriteDescription

31:0

INT_CW_CLR

32

RO

A read operation of this register will clear the bit[1] in register 0x54.

+
+

CODEC READ Interrupt Clear Register

+
+
+

Offset address: 0x6c

+
+
+

Reset value: 00000000h

+
+ + +++++++ + + + + + + + + + + + + + + + + + + +
Table 263. CODEC READ interrupt clear register
Bit FieldNameLengthRead/WriteDescription

31:0

INT_CR_CLR

32

RO

A read operation of this register will clear the bit[0] in register 0x54.

+
+

DMA Command Register

+
+
+

This register is used to control the internal DMA controller of the AC97. +The DMA controller is described in detail in the following section.

+
+
+

Offset address: 0x100

+
+
+

Reset value: 00000000h

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 264. DMA command register
Bit FieldNameRead/WriteDescription

63:5

ask_addr

R/W

bit[63:5] of the DMA descriptor address, the lower 5 bits are 0.

5

Reserved

R/W

Reserved.

4

dma_stop

R/W

Stop DMA operation. +The DMA controller stops when it has completed reading or writing the current data.

3

dma_start

R/W

Start DMA operation. +The DMA controller reads the descriptor address (ask_addr) and then clears some bits to zero.

2

ask_valid

R/W

The DMA working register is written back to the memory pointed to by (ask_addr) and cleared to zero when finished.

1

Reserved

R/W

Reserved.

0

dma_64bit

R/W

DMA controller 64-bit address support.

+
+
+

20.3. DMA Controller

+
+

20.3.1. Description of DMA Controller Structure

+
+

The bridge contains 2 DMA controllers for data migration between memory and AC97, which can save resources and improve the efficiency of system data transfer. +This saves resources and improves the efficiency of system data transfer.

+
+
+

The process of transporting data by DMA consists of three stages.

+
+
+
    +
  1. +

    Pre-processing before transport: The CPU configures the registers related to the DMA descriptor.

    +
    2. +
  2. +

    Data transport: done automatically under the control of the DMA controller.

    +
    3. +
  3. +

    End-of-transport processing: sending an interrupt request.

    +
    4. +
+
+
+

This DMA controller is limited to data handling in words (4-byte).

+
+
+

The DMA controller supports 64-bit address space, which is mainly controlled by dma_64bit. +When this bit is set to 1, it means that the DMA controller works in 64-bit address space, and vice versa for 32-bit address space. +In 64-bit address mode, it is necessary to extend DMA_ORDER_ADDR and DMA_SADDR to 64-bit registers.

+
+
+
+

20.3.2. DMA Descriptor

+
+

DMA_ORDER_ADDR_LOW

+
+
+

Offset address: 0x0

+
+
+

Reset value: 0x00000000

+
+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 265. DMA_ORDER_ADDR_LOW
Bit FieldNameLengthRead/WriteDescription

31:1

dma_order_addr

31

R/W

Memory internal next descriptor address register (low 32 bits).

0

Dma_order_en

1

R/W

Whether the descriptor is a valid signal.

+
+

Description: Store the address of the next DMA descriptor. +dma_order_en is the enable bit of the next DMA descriptor. +If this bit is 1, the next descriptor is valid; if this bit is 0, the next descriptor is invalid and no operation is performed. +When the DMA descriptor is configured, this register holds the address of the next descriptor. After the DMA operation is performed, the dma_order_en signal is used to determine whether to start the next DMA operation. +In 64-bit address mode, this register stores the low 32-bit address.

+
+
+

DMA_SADDR

+
+
+

Offset address: 0x4

+
+
+

Reset value: 0x00000000

+
+ + +++++++ + + + + + + + + + + + + + + + + + + +
Table 266. DMA_SADDR
Bit FieldNameLengthRead/WriteDescription

31:0

dma_saddr

32

R/W

System memory address for DMA operations (low 32 bits).

+
+

Description: DMA operations are divided into Memory Read and Memory Write. +Memory Read: reads data from memory, saves it in the DMA controller’s cache, and then writes it to the AC97 device; this register specifies the address of the read memory. +Memory Write: Read data from AC97 device is saved in the DMA cache, and when the data in the DMA cache exceeds a certain number, it is written to the memory, and this register specifies the address of the write memory. +In 64-bit address mode, this register stores the low 32-bit address.

+
+
+

DMA_DADDR

+
+
+

Offset address: 0x8

+
+
+

Reset value: 0x00000000

+
+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 267. DMA_DADDR
Bit FieldNameLengthRead/WriteDescription

31

AC97_wr_en

1

R/W

AC97 write enable. +1: Indicate a write operation.

30

AC97_mode

1

R/W

0: mono

+

1: 2 stero

29:28

AC97_wr_mode

2

R/W

AC97 write mode.

+

0: 1-byte

+

1: 2-byte

+

2: 4-byte

27:0

dma_daddr

28

R/W

AC97 device address for DMA operation.

+
+

DMA_LENGTH

+
+
+

Offset address: 0xc

+
+
+

Reset value: 0x00000000

+
+ + +++++++ + + + + + + + + + + + + + + + + + + +
Table 268. DMA_LENGTH
Bit FieldNameLengthRead/WriteDescription

31:0

dma_length

32

R/W

Transport data length register.

+
+

Description: Represents the length of a piece of content to be carried, in words. +When the length of the word has been carried, the next step is started, i.e. the next loop. +When a new loop is started, the length of data is carried again. +When step becomes 1, the single DMA descriptor operation ends and the next descriptor is read.

+
+
+

DMA_STEP_LENGTH

+
+
+

Offset address: 0x10

+
+
+

Reset value: 0x00000000

+
+ + +++++++ + + + + + + + + + + + + + + + + + + +
Table 269. DMA_STEP_LENGTH
Bit FieldNameLengthRead/WriteDescription

31:0

dma_step_length

32

R/W

Data transport interval length register.

+
+

Description: The length of the interval between two blocks of memory data being carried, the interval between the end address of the previous step and the start address of the next step.

+
+
+

DMA_STEP_TIMES

+
+
+

Offset address: 0x14

+
+
+

Reset value: 0x00000000

+
+ + +++++++ + + + + + + + + + + + + + + + + + + +
Table 270. DMA_STEP_TIMES
Bit FieldNameLengthRead/WriteDescription

31:0

dma_step_times

32

R/W

Data transport cycle count register.

+
+

Description: The number of cycles indicates the number of blocks to be carried in a single DMA operation. +If you want to carry only one consecutive block, the value of the cycle count register can be assigned to 1.

+
+
+

DMA_CMD

+
+
+

Offset address: 0x18

+
+
+

Reset value: 0x00000000

+
+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 271. DMA_CMD
Bit FieldNameLengthRead/WriteDescription

14:13

Dma_cmd

2

R/W

Source and destination address generation method.

12

dma_r_w

1

R/W

DMA operation type, 1 is read ddr2 write device, 0 is read device write ddr2.

11:8

dma_write_state

4

R/W

DMA write data status.

7:4

dma_read_state

4

R/W

DMA read data status.

3

dma_trans_over

1

R/W

The DMA has executed all the configured descriptor operations.

2

dma_single_trans_over

1

R/W

The DMA has executed a descriptor operation.

1

dma_int

1

R/W

DMA interrupt signal.

0

dma_int_mask

1

R/W

Whether DMA interrupts are masked.

+
+

Description: dma_single_trans_over=1 means the end of one DMA operation, when length=0 and step_times=1, the descriptor of the next DMA operation will be taken. +The descriptor address of the next DMA operation is stored in the DMA_ORDER_ADDR register. +If dma_order_en=0 in the DMA_ORDER_ADDR register, then dma_trans_over=1 and the whole dma operation is finished and there are no new descriptors to read. +If dma_order_en=1, then dma_trans_over is set to 0 and the next dma descriptor is read. +dma_int is the interrupt of the DMA, which occurs after a configured DMA operation if there is no interrupt mask. +The CPU can set it low directly after processing the interrupt, or it can wait until the DMA makes its next transfer. +dma_int_mask is the interrupt mask for the corresponding dma_int. +dma_read_state describes the current read state of the DMA. +dma_write_state describes the current write state of the DMA.

+
+
+

The DMA write state (WRITE_STATE[3:0]) describes that the DMA includes the following write states.

+
+ + +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 272. DMA write state
Write_state[3:0]Description

Write_idle

4’h0

Write state is in idle state

W_ddr_wait

4’h1

Dma determines that it needs to perform a read device write memory operation and initiates a write memory request, but the memory is not ready to respond to the request, so dma keeps waiting for a response from the memory

Write_ddr

4’h2

Memory has received a dma write request, but has not yet finished executing the write operation

Write_ddr_end

4’h3

The memory receives the dma write request and completes the write operation, at which point the dma is in the write memory operation complete state

Write_dma_wait

4’h4

Dma sends a request to write the dma status register back to memory and waits for memory to receive the request

Write_dma

4’h5

Memory receives a write dma status request, but the operation is not yet complete

Write_dma_end

4’h6

Memory completes write dma status operation

Write_step_end

4’h7

Dma completes a length length operation (i.e. completes a step)

+
+

The DMA read state (READ_STATE[3:0]) describes that the DMA includes the following read states.

+
+ + +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 273. DMA read state
Read_state[3:0]Description

Read_idle

4’h0

Read state is in idle state

Read_ready

4’h1

After receiving the start signal to start the dma operation, enter the ready state and start reading the descriptor

Get_order

4’h2

Issue a read descriptor request to memory and wait for a memory answer

Read_order

4’h3

Memory receives a read descriptor request and is performing a read operation

Finish_order_end

4’h4

Memory read out dma descriptor

R_ddr_wait

4’h5

Dma sends a read data request to memory and waits for a memory answer

Read_ddr

4’h6

Memory receives dma read data request and is performing read data operation

Read_ddr_end

4’h7

Memory completes a read data request from dma

Read_dev

4’h8

Dma enters read device status

Read_dev_end

4’h9

The device returns read data, ending the read device request

Read_step_end

4’ha

End a step operation, step times minus 1

+
+

DMA_ORDER_ADDR_HIGH

+
+
+

Offset address: 0x20

+
+
+

Reset value: 0x00000000

+
+ + +++++++ + + + + + + + + + + + + + + + + + + +
Table 274. DMA_ORDER_ADDR_HIGH
Bit FieldNameLengthRead/WriteDescription

31:0

dma_order_addr

32

R/W

Memory internal next descriptor address register (high 32 bits)

+
+

DMA_SADDR_HIGH

+
+
+

Offset address: 0x24

+
+
+

Reset value: 0x00000000

+
+ + +++++++ + + + + + + + + + + + + + + + + + + +
Table 275. DMA_SADDR_HIGH
Bit FieldNameLengthRead/WriteDescription

31:0

dma_saddr

32

R/W

Memory address for DMA operation (high 32 bits)

+
+
+
+
+
+

21. SATA Controller (D8:F0/1/2)

+
+
+

The features of SATA are as follows.

+
+
+
    +
  • +

    Supports SATA Generation 1 at 1.5Gbps and SATA Generation 2 at 3Gbps

    +
    • +
  • +

    Compatible with Serial ATA 2.6 specification and AHCI 1.1 specification

    +
    • +
+
+
+

21.1. SATA Configuration Register (D8:F0/1/2)

+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 276. SATA controller configuration registers
Address OffsetAbbreviationDescriptionDefault valueRead/Write

00h-01h

VID

Vendor ID

0014h

RO

02h-03h

DID

Device ID

7A08h

RO

04h-05h

PCICMD

PCI Command

0000h

R/W, RO

08h

RID

Revision ID

00h

RO

09h

PI

Programming Interface

01h

RO

0Ah

SCC

Sub Class Code

06h

RO

0Bh

BCC

Base Class Code

01h

RO

0Ch

CLS

Cache Line Size

00h

RO

0Eh

HEADTYP

Header Type

80h

RO

10h-17h

CNL_BAR

Control Base Address Register

0000000000000004h

R/W, RO

2Ch-2Dh

SVID

Subsystem Vendor ID

0000h

RO

2Eh-2Fh

SID

Subsystem Identification

0000h

RO

3Ch

INT_LN

Interrupt Line

00h

R/W

3Dh

INT_PN

Interrupt Pin

01h

RO

+
+

Note: Address space not listed in the table indicates reserved.

+
+
+

Registers that differ slightly from the PCI configuration header specification and their descriptions are listed below.

+
+
+

PCICMD - PCI Command Register (SATA - D8:F0/1/2)

+
+
+

Address Offset: 04-05h

+
+
+

Attribute: R/W, RO

+
+
+

Default value: 0000h

+
+
+

Size: 16 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 277. PCI command register
Bit FieldNameRead/WriteDescription

15:2

Reserved

RO

Reserved.

1

Memory Space Enable

R/W

This bit is used to control whether access to the SATA control registers is enabled.

+

0: Disable access.

+

1: Enable access to the SATA control registers. +The BAR register must be configured before this bit can be configured to 1.

0

Reserved

RO

Reserved.

+
+

CNL_BAR - Control Base Address Register

+
+
+

This register is used to configure the base address of the control registers of the SATA controller.

+
+
+

Address Offset: 10-13h

+
+
+

Attribute: R/W, RO

+
+
+

Default value: 00000004h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 278. Control base address register
Bit FieldNameRead/WriteDescription

31:13

Base Address

RW

The software writes to this register field the low address of the base address allocated to the SATA control register.

12:4

Memory Size

RO

The address space size of SATA control register is 8KB.

3

Prefetchable Memory

RO

Set to 0 to indicate that it is not prefetchable.

2:1

Memory Type

RO

Set to 10b to indicate 64-bit BAR.

0

Memory/ I/O Space

RO

Set to 0 to indicate Memory space BAR.

+
+

Address Offset: 14-17h

+
+
+

Attribute: R/W

+
+
+

Default value: 00000000h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + +
Table 279. Control base address register
Bit FieldNameRead/WriteDescription

31:0

Base Address

RW

The software writes to this register field the high 32-bit address of the base address allocated to the SATA control register.

+
+
+

21.2. Description of SATA Control Register

+
+

The base address of SATA is given by BAR0 of SATA and the register definition is identical to the protocol standard definition.

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 280. List of SATA control registers
Address OffsetLengthNameDescription

0x000

32

CAP

HBA characteristic register

0x004

32

GHC

Global HBA control register

0x008

32

IS

Interrupt status register

0x00c

32

PI

Port register

0x010

32

VS

AHCI version register

0x014

32

CCC_CTL

Command completion merge control register

0x018

32

CCC_PORTS

Command completion merge port register

0x024

32

CAP2

HBA characteristic expansion register

0x0A0

32

BISTAFR

BIST active FIS

0x0A4

32

BISTCR

BIST control register

0x0A8

32

BISTCTR

BIST FIS count register

0x0AC

32

BISTSR

BIST status register

0x0B0

32

BISTDECR

BIST double word error count register

0x0BC

32

OOBR

OOB register

0x0E0

32

TIMER1MS

1ms count register

0x0E8

32

GPARAM1R

Global parameter register 1

0x0EC

32

GPARAM2R

Global parameter register 2

0x0F0

32

PPARAMR

Port parameter register

0x0F4

32

TESTR

Test register

0x0F8

32

VERIONR

Version register

0x0FC

32

IDR

ID register

0x100

32

P0_CLB

Command list base address low 32 bits

0x104

32

P0_CLBU

Command list base address high 32 bits

0x108

32

P0_FB

FIS base address low 32 bits

0x10c

32

P0_FBU

FIS base address high 32 bits

0x110

32

P0_IS

Interrupt status register

0x114

32

P0_IE

Interrupt enable register

0x118

32

P0_CMD

Command register

0x120

32

P0_TFD

Task file data register

0x124

32

P0_SIG

Signature register

0x128

32

P0_SSTS

SATA status register

0x12C

32

P0_SCTL

SATA control register

0x130

32

P0_SERR

SATA error register

0x134

32

P0_SACT

SATA active register

0x138

32

P0_CI

Command send register

0x13C

32

P0_SNTF

SATA command notification register

0x170

32

P0_DMACR

DMA control register

0x178

32

P0_PHYCR

PHY control register

0x17C

32

P0_PHYSR

PHY status register

0x180

32

P1_CLB

Command list base address low 32 bits

0x184

32

P1_CLBU

Command list base address high 32 bits

0x188

32

P1_FB

FIS base address low 32 bits

0x18c

32

P1_FBU

FIS base address high 32 bits

0x190

32

P1_IS

Interrupt status register

0x194

32

P1_IE

Interrupt enable register

0x108

32

P1_CMD

Command register

0x1a0

32

P1_TFD

Task file data register

0x1a4

32

P1_SIG

Signature register

0x1a8

32

P1_SSTS

SATA status register

0x1aC

32

P1_SCTL

SATA control register

0x1b0

32

P1_SERR

SATA error register

0x1b4

32

P1_SACT

SATA active register

0x1b8

32

P1_CI

Command send register

0x1bC

32

P1_SNTF

SATA command notification register

0x1f0

32

P1_DMACR

DMA control register

0x1f8

32

P1_PHYCR

PHY control register

0x1fC

32

P1s_PHYSR

PHY status register

+
+
+
+
+

22. PCIE Controller (D9:F0, D10:F0, D11:F0, D12:F0, D13:F0, D14:F0, D15:F0, D16:F0, D17:F0, D18:F0, D19:F0, D20:F0)

+
+
+

The PCIEs of the bridge chip are divided into 5 groups: PCIE_F0, PCIE_F1, PCIE_H, PCIE_G0, PCIE_G1, with a total of 32 lanes. +Each group of PCIE interfaces has its own corresponding control port. +The bridge contains 12 PCIE control ports (ports), namely port 0, port 1, port 2, port 3 of PCIE_F0, port 0, port 1 of PCIE_F1, port 0, port 1 of PCIE_G0, port 0, port 1 of PCIE_G1, port 0, port 1 of PCIE_H, port 1 of PCIE_H. +Each port corresponds to a PCIE controller, and each PCIE controller contains a TYPE1 type PCI configuration header.

+
+
+

PCIE_F0 includes 4 lanes and can be used as one x4 PCIE or 4 x1 PCIEs. +Among them, port 0 controls lane0 in non x4 mode, port 0 controls lane0, and lane0-3 in x4 mode. +In non-x4 mode, port 1 controls lane1, port In non-x4 mode, port 1 controls lane1, port 2 controls lane2, and port 3 controls lane3.

+
+
+

PCIE_F1 includes 4 lanes, which can be used as one x4 PCIE or 2 x1 PCIEs. +Among them, port 0 controls lane0 in non lane0 in non-x4 mode and lane0-3 in x4 mode. +In non-x4 mode, port 1 controls lane1, lane2 and lane3 are not available.

+
+
+

PCIE_H includes 8 lanes and can be used as one x8 PCIE or 2 x4 PCIEs. +Among them, port 0 controls lane0-3 in non port 0 controls lane0-3 in non-x8 mode and lane0-7 in x8 mode. +In non-x8 mode, port 1 controls lane4-7.

+
+
+

PCIE_G0 includes 8 lanes, which can be used as one x8 PCIE or two x4 PCIEs. +Among them, port 0 controls lane4-7 in Port 0 controls lane0-3 in non-x8 mode and lane0-7 in x8 mode. +In non-x8 mode, port 1 controls lane4-7.

+
+
+

PCIE_G1 includes 8 lanes, which can be used as one x8 PCIE or two x4 PCIEs. +Among them, port 0 controls lane4-7 in port 0 controls lane0-3 in non-x8 mode and lane0-7 in x8 mode. +In non-x8 mode, port 1 controls lane4-7.

+
+
+

The PCIE controller of the bridge chip can be used only as RC, not as EP.

+
+
+

The configuration methods supported by PCIE and the corresponding control ports are shown in the tables below.

+
+ + ++++++ + + + + + + + + + + + + + + + + + +
Table 281. Configuration methods and control ports supported by PCIE_F0

lane0

lane1

lane2

lane3

x4 (P0)

x1 (P0)

x1 (P1)

x1 (P2)

x1 (P3)

+ + ++++++ + + + + + + + + + + + + + + + + + +
Table 282. Configuration methods and control ports supported by PCIE_F1

lane0

lane1

lane2

lane3

x4 (P0)

x1 (P0)

x1 (P1)

+ + ++++++++++ + + + + + + + + + + + + + + + + + + + +
Table 283. Configuration methods and control ports supported by PCIE_G0, PCIE_G1 and PCIE_H

lane0

lane1

lane2

lane3

lane4

lane5

lane6

lane7

x8 (P0)

x4 (P0)

x4 (P1)

+
+

22.1. PCI Configuration Register

+
+

The following table lists the configuration header defaults for PCIE ports, the Device ID may be different for different ports, all other fields are the same.

+
+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 284. PCIE controller configuration registers
Address OffsetAbbreviationDescriptionDefault valueRead/Write

00h-01h

VID

Vendor ID

0014h

RO

02h-03h

DID

Device ID

See description of registers

RO

04h-05h

PCICMD

PCI Command

0000h

R/W, RO

06h-07h

PCISTS

PCI Status

0010h

RO

08h

RID

Revision ID

01h

RO

09h

PI

Programming Interface

00h

RO

0Ah

SCC

Sub Class Code

04h

RO

0Bh

BCC

Base Class Code

06h

RO

0Ch

CLS

Cache Line Size

00h

RO

0Dh

PLT

Primary Latency Timer

00h

RO

0Eh

HEADTYP

Header Type

01h

RO

10h-17h

CNL_BAR

Control Block Base Address Register

0000000000000004h

R/W, RO

18h

PBNUM

Primary Bus Number

00h

R/W

19h

SBNUM

Secondary Bus Number

00h

R/W

1Ah

SUBNUM

Subordinate Bus Number

00h

R/W

1Bh

SLT

Secondary Latency Timer

00h

RO

1Ch

IOBASE

I/O Base

01h

R/W

1Dh

IOLMT

I/O Limit

01h

R/W

1Eh-1Fh

SSTS

Secondary Status

0000h

RO

20h-21h

MBASE

Memory Base

0000h

R/W

22h-23h

MLMT

Memory Limit

0000h

R/W

25h-24h

PMBASE

Prefetchable Memory Base

0000h

R/W

27h-26h

PMLMT

Prefetchable Memory Limit

0000h

R/W

28h-2Bh

PMBU32

Prefetchable Memory Base Upper 32 Bits

00000000h

R/W

2Ch-2Fh

PMLU32

Prefetchable Memory Limit Upper 32 Bits

00000000h

R/W

30h-31h

IOBU

I/O Base Upper 16 Bits

0000h

R/W

32h-33h

IOLMTU

I/O Limit Upper 16 Bits

0000h

R/W

34h

CAPP

Capabilities Pointer

40h

RO

3Ch

INT_LN

Interrupt Line

FFh

R/W

3Dh

INT_PN

Interrupt Pin

01h

RO

3Eh-3Fh

BCTRL

Bridge Control Register

0000h

R/W

+
+

Note: Address space not listed in the table indicates reserved.

+
+
+

Registers that differ slightly from the PCI configuration header specification and their descriptions are listed below.

+
+
+

DID - Device Identity Register (PCIE)

+
+
+

Address Offset: 02-03h

+
+
+

Attribute: RO

+
+
+

Default value: See description

+
+
+

Size: 16 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + +
Table 285. Device identity register
Bit FieldNameRead/WriteDescription

15:0

DID

RO

PCIE device identity register. +The corresponding DID of each PCIE port is shown in the following table.

+ + +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 286. Table of DID of PCIE port
PCI Device NumberDescriptionDevice Identity Register

D9:F0

PCIE_F0 port 0

7A19h

D10:F0

PCIE_F0 port 1

7A09h

D11:F0

PCIE_F0 port 2

7A09h

D12:F0

PCIE_F0 port 3

7A09h

D13:F0

PCIE_F1 port 0

7A19h

D14:F0

PCIE_F1 port 1

7A09h

D15:F0

PCIE_G0 port 0

7A29h

D16:F0

PCIE_G0 port 1

7A19h

D17:F0

PCIE_G1 port 0

7A29h

D18:F0

PCIE_G1 port 1

7A19h

D19:F0

PCIE_H port 0

7A29h

D20:F0

PCIE_H port 1

7A19h

+
+

Note:

+
+
+
    +
  1. +

    The correct value of the subclass code for all PCIE controllers integrated in the bridge should be 0x04 for the PCI-to-PCI bridge, but this bridge incorrectly implements this value as 0x00 (for the Host bridge). +The software needs to ignore this bit field and still handle the bridge-integrated PCIE controllers as PCI-to-PCI bridges, see Notes on the Use of the Software.

    +
    2. +
  2. +

    Only one device (Device 0) can be mounted on the bus below all PCIE controllers integrated in the bridge, but when the software scans the PCIE bus for non-Device 0 devices, this PCIE controller will return the information of Device 0, causing Device 0 to be discovered repeatedly. +Therefore, the software must not actively scan for non-Device 0 devices below the PCIE controller, see Notes on the Use of the Software.

    +
    3. +
+
+
+
+

22.2. Address Space Division

+
+

The PCIE controller in the bridge has a standard PCIE configuration header, so the internal registers of the PCIE controller and the address space of its downstream devices are managed by the information in its configuration header. +The address-related registers in the configuration header are determined during the PCI device scan.

+
+
+

Because the bridge’s PCIE controller can only operate in RC mode, its configuration header is of type TYPE1.

+
+
+

Each PCIE port acts as a separate device in the bridge slice, and each port contains a PCIE configuration header. +When the PCIE is operating in X4 mode, the port software for the other X1 is not visible, and the other X1 ports are only accessible when the PCIE is operating in X1 mode.

+
+
+

For each PCIE port, the address space can be divided into the following parts.

+
+
+

Configuration header address space: This part of the space corresponds to the configuration header of the PCIE and is accessed through configuration requests up to 4KB. +See Access Address of the PCI Configuration for accessing address space above 256B.

+
+
+

Configuration Access Address Space: This portion of the address space is used to access the PCIE controller’s downstream device configuration header information via configuration requests. +Depending on the Bus number of the downstream device, it is up to the PCIE controller to decide whether to send a TYPE0 type or TYPE1 type configuration access.

+
+
+

The addresses of the above two address spaces are calculated from the configuration address space base address, BUS number, device number, function number, and register offset address, and can be accessed by word.

+
+
+

PCIE controller internal register space: This part of the address space is used to access the internal registers of the PCIE controller. +These registers are used to control the behavior and characteristics of the PCIE controller and belong to two address spaces with the PCIE configuration header space. +This address space is of type MEM, 64-bit address space, 4KB in size, with a base address equal to the value of 64-bit BAR0, which is assigned by the PCI scan software during initialization.

+
+
+

MEM address space: This part of the address space contains all the MEM address space of the devices downstream of the PCIE controller. +For the 32-bit address space, this is determined by the memory base and memory limit of the PCIE configuration header. +For the 64-bit address space, this is determined by the prefetchable memory base (combined upper 32 bits) and prefetchable memory limit (combined upper 32 bits) of the PCIE configuration header. +This address space is enabled and controlled by the command register bit1 of the PCIE configuration header.

+
+
+

I/O address space: This part of the address space contains all the I/O address space of the devices downstream of the PCIE controller. +It is determined by the IO base (combined upper 16 bits) and IO limit (combined upper 16 bits) of the PCIE configuration header. +This address space is enabled and controlled by the command register bit0 of the PCIE configuration header.

+
+
+

For the MEM address space and I/O address space, if there is no device connected downstream of an X1 port in X1 operation mode, the MEM and I/O address space can be disabled by setting bit0 and bit1 of the command register to 0.

+
+
+

PCIE Controller Enable

+
+
+

General configuration register 0 of the bridge configuration register contains the enable bits for the PCIE controller. +It needs to be enabled when using the corresponding PCIE controller in order to access all address spaces of that controller and downstream devices, including configuration access to the controller.

+
+
+
+

22.3. Special Notes

+
+

PCIE Capability

+
+
+

The maximum MPS (Max Payload Size) and MRRS (Max Read Request Size) supported by the integrated PCIE controller of the bridge are both 256 bytes. +The MPS setting can be set under the BIOS through the PCI negotiation mechanism. +Since there is no negotiation mechanism for MRRS, BIOS developers need to set the MRRS value of the device to a value no larger than 256 bytes.

+
+
+

PCIE MSI

+
+
+

On 3A+7A systems, the destination address for PCI MSI interrupts is 0xfdf8000000 or 0x2ff00000. +The bridge converts the MSI message packets sent by the device to these two address segments into HT interrupt message packets and sends them to the processor.

+
+
+

PCIE Controller Performance

+
+
+

The PCIE controllers integrated in the bridge are x8, x4, and x1. +The P0 control port of PCIE_G0/G1/H is the x8 controller, the P0 port of PCIE_F0/F1 and the P1 port of PCIE_G0/G1/H are the x4 controllers, and the P1/P2/P3 port of PCIE_F0 and the P1 port of PCIE_F1 are the x1 controllers.

+
+
+

These three controllers have different numbers of internal flow-controlled buffers, with x8, x4, and x1 controllers decreasing in order, so for some high-bandwidth PCIE devices, using a controller with a larger number of flow-controlled buffers for the same data width will result in a performance improvement. +Therefore, it is recommended to give preference to controllers with larger number of flow control buffers.

+
+
+
+
+
+

23. SPI Controller (D22:F0)

+
+
+

23.1. SPI Configuration Register (D22:F0)

+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 287. SPI controller configuration registers
Address OffsetAbbreviationDescriptionDefault valueRead/Write

00h-01h

VID

Vendor ID

0014h

RO

02h-03h

DID

Device ID

7A0Bh

RO

04h-05h

PCICMD

PCI Command

0000h

R/W, RO

08h

RID

Revision ID

00h

RO

09h

PI

Programming Interface

00h

RO

0Ah

SCC

Sub Class Code

08h

RO

0Bh

BCC

Base Class Code

80h

RO

0Ch

CLS

Cache Line Size

00h

RO

0Eh

HEADTYP

Header Type

00h

RO

10h-17h

CBAR

Control Base Address Register

0000000000000004h

R/W, RO

18h-1Fh

MBAR

Memory Base Address Register

0000000000000004h

R/W, RO

2Ch-2Dh

SVID

Subsystem Vendor ID

0000h

RO

2Eh-2Fh

SID

Subsystem Identification

0000h

RO

3Ch

INT_LN

Interrupt Line

00h

R/W

3Dh

INT_PN

Interrupt Pin

01h

RO

+
+

Note: Address space not listed in the table indicates reserved.

+
+
+

Registers that differ slightly from the PCI configuration header specification and their descriptions are listed below.

+
+
+

PCICMD - PCI Command Register (SPI - D22:F0)

+
+
+

Address Offset: 04-05h

+
+
+

Attribute: R/W, RO

+
+
+

Default value: 0000h

+
+
+

Size: 16 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 288. PCI command register
Bit FieldNameRead/WriteDescription

15:2

Reserved

RO

Reserved.

1

Memory Space Enable

R/W

This bit is used to control whether access to the SPI control registers and SPI memory space is enabled.

+

0: Disable access.

+

1: Enable access to the SPI control registers and SPI memory space. +The BAR register must be configured before this bit can be configured to 1.

0

Reserved

RO

Reserved.

+
+

The SPI controller consists of two address spaces: the control register space and the memory space.

+
+
+

CNL_BAR - Control Base Address Register

+
+
+

This register is used to configure the base address of the control registers of the SPI controler.

+
+
+

Address Offset: 10-13h

+
+
+

Attribute: R/W, RO

+
+
+

Default value: 00000004h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 289. Control base address register
Bit FieldNameRead/WriteDescription

31:12

Base Address

RW

The software writes to this register field the low address of the base address allocated to the SPI controller.

11:4

Memory Size

RO

The address space size of SPI controller is 4KB.

3

Prefetchable Memory

RO

Set to 0 to indicate that it is not prefetchable.

2:1

Memory Type

RO

Set to 10b to indicate 64-bit BAR.

0

Memory/ I/O Space

RO

Set to 0 to indicate Memory space BAR.

+
+

Address Offset: 14-17h

+
+
+

Attribute: R/W

+
+
+

Default value: 00000000h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + +
Table 290. Control base address register
Bit FieldNameRead/WriteDescription

31:0

Base Address

RW

The software writes to this register field the high 32-bit address of the base address allocated to the SPI controller.

+
+

MBAR - MEM Space Base Address Register

+
+
+

This register is used to configure the MEM space base address of the SPI controller.

+
+
+

Address Offset: 18-1Bh

+
+
+

Attribute: R/W, RO

+
+
+

Default value: 00000004h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 291. MEM space base address register
Bit FieldNameRead/WriteDescription

31:24

Base Address

RW

The software writes to this register field the bit[31:24] of the base address allocated to the SPI MEM space.

23:4

Memory Size

RO

The SPI MEM space size is 16MB.

3

Prefetchable Memory

RO

Set to 0 to indicate that it is not prefetchable.

2:1

Memory Type

RO

Set to 10b to indicate 64-bit BAR.

0

Memory/ I/O Space

RO

Set to 0 to indicate Memory space BAR.

+
+

Address Offset: 1C-1Fh

+
+
+

Attribute: R/W

+
+
+

Default value: 00000000h

+
+
+

Size: 32 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + +
Table 292. MEM space base address register
Bit FieldNameRead/WriteDescription

31:0

Base Address

RW

The software writes to this register field the high 32-bit address of the base address allocated to the SPI MEM space.

+
+
+

23.2. SPI Control Register

+ + +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 293. List of SPI control registers
Address OffsetNameDescription

0

SPCR

Control register

1

SPSR

Status register

2

TxFIFO/RxFIFO

Data register

3

SPER

External register

4

SFC_PARAM

Parameter control register

5

SFC_SOFTCS

Chip select control register

6

SFC_TIMING

Timing control register

+
+

Control Register (SPCR)

+
+
+

Offset address: 0x0

+
+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 294. Control register
Bit FieldNameRead/WriteInitial ValueDescription

7

spie

R/W

0

Interrupt output enable signal (active high)

6

spe

R/W

0

System operation enable signal (active high)

5

Reserved

RO

0

Reserved

4

mstr

RO

1

master mode select bit. +This bit is always held 1

3

cpol

R/W

0

Clock polarity bits

2

cpha

R/W

0

Clock phase. +1 is opposite phase, and 0 is same

1:0

spr

R/W

0

sclk_o frequency division configuration. +It need to be used with sper's `spre

+
+

Status Register (SPSR)

+
+
+

Offset address: 0x1

+
+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 295. Status register
Bit FieldNameRead/WriteInitial ValueDescription

7

spif

R/W

0

Interrupt flag. +1 indicates an interrupt request, write 1 to clear

6

wcol

R/W

0

Write register overflow flag bit. +1 indicates overflowed, write 1 to clear

5:4

Reserved

RO

0

Reserved

3

wffull

RO

0

Write register full. +1 indicates full

2

wfempty

RO

1

Write register empty. +1 indicates empty

1

rffull

RO

0

Read register full. +1 indicates full

0

rfempty

RO

1

Read register empty. +1 indicates empty

+
+

Data Register (TxFIFO/RxFIFO)

+
+
+

Offset address: 0x2

+
+ + +++++++ + + + + + + + + + + + + + + + + + + +
Table 296. Data register
Bit FieldNameRead/WriteInitial ValueDescription

7:0

TxFIFO RxFIFO

W RO

-

Data transporting port.

+

Data receiving port

+
+

External Register (SPER)

+
+
+

Offset address: 0x3

+
+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 297. External register
Bit FieldNameRead/WriteInitial ValueDescription

7:6

icnt

R/W

0

Bytes transferred before sending an interrupt.

+

00: 1

+

01: 2

+

10: 3

+

11: 4

5:3

-

-

-

Reserved

2

mode

R/W

0

SPI interface mode control

+

0: Sampling and transporting timing are simultaneous

+

1: Sampling and transporting timing staggered by half a cycle

1:0

spre

R/W

0

Set the ratio of the frequency division together with spr

+ + +++++++++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 298. SPI Frequency Division Factor

spre

+

spr

00

+

00

00

+

01

00

+

10

00

+

11

01

+

00

01

+

01

01

+

10

01

+

11

10

+

00

10

+

01

10

+

10

10

+

11

Frequency Division Factor

2

4

16

32

8

64

128

256

512

1024

2048

4096

+
+

Parameter Control Register (SFC_PARAM)

+
+
+

Offset address: 0x4

+
+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 299. Parameter control register
Bit FieldNameRead/WriteInitial ValueDescription

7:4

clk_div

R/W

2

Clock division number selection.

+

The frequency division factor is the same as the combination of {spre, spr}

3

dual_io

R/W

0

Dual I/O mode with higher priority than fast read

2

fast_read

R/W

0

Fast Read Mode

1

burst_en

R/W

0

SPI flash supports sequential address read mode

0

memory_en

R/W

1

SPI flash read enable. +When disabled, csn[0] can be controlled by software

+
+

Chip Select Control Register (SFC_SOFTCS)

+
+
+

Offset address: 0x5

+
+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 300. Chip select control register
Bit FieldNameRead/WriteInitial ValueDescription

7:4

csn

R/W

0

csn pin output value

3:0

csen

R/W

0

When the bit is 1, the csn line of the corresponding bit is controlled by 7:4 bits

+
+

Timing Control Register (SFC_TIMING)

+
+
+

Offset address: 0x6

+
+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 301. Timing control register
Bit FieldNameRead/WriteInitial ValueDescription

7:3

-

-

-

Reserved

2

tFAST

R/W

0

SPI flash read sampling mode

+

0: Rising edge sampling, half SPI cycle interval

+

1: Rising edge sampling with one SPI cycle interval

1:0

tCSH

R/W

3

The minimum invalidation time of the SPI Flash’s chip select signal, in terms of the clock period after frequency division.

+

Calculation of T

+

00: 1T

+

01: 2T

+

10: 4T

+

11: 8T

+
+
+

23.3. SPI Software Programming Guide

+
+

Read and Write Operations of the SPI Host Controller

+
+
+

Module Initialization

+
+
+
    +
  1. +

    Stop SPI controller operation, write 0 to the spe bit of control register spcr.

    +
    2. +
  2. +

    Reset the status register spsr and write 1100_0000b to the register.

    +
    3. +
  3. +

    Set the external register sper, including the interrupt request condition sper[7:6] and the dividing factor sper[1:0], refer to the register description for details.

    +
    4. +
  4. +

    Configure SPI timing, including cpol, cpha of spcr and mode of sper. +mode is 1 for standard SPI implementation and 0 for compatible mode.

    +
    5. +
  5. +

    Configure interrupt enable, spie bit of spcr.

    +
    6. +
  6. +

    Start the SPI controller and write 1 to the spe bit of the control register spcr.

    +
    7. +
+
+
+

Send/transport Operations of the Module

+
+
+
    +
  1. +

    Write data to the data transport register.

    +
    2. +
  2. +

    Since transporting and receiving occur simultaneously, the SPI slave device must perform a readout operation even if no valid data is sent.

    +
    3. +
+
+
+

Interrupt Handling

+
+
+
    +
  1. +

    Receive the interrupt request.

    +
    2. +
  2. +

    Read the value of status register spsr, if spsr[2] is 1, it means data transport is completed, if spsr[0] is 1, it means data has been received.

    +
    3. +
  3. +

    Read or write the data transport register.

    +
    4. +
  4. +

    Write 1 to the spif bit of status register spsr to clear the controller’s interrupt request.

    +
    5. +
+
+
+

Hardware SPI Flash Read

+
+
+

Initialization

+
+
+
    +
  1. +

    Write 1 to the memory_en bit of SFC_PARAM.

    +
    2. +
  2. +

    Set the read parameters (clock division, sequential address read, fast read, dual I/O, tCSH, etc.). These parameters are reset to the most conservative values.

    +
    3. +
+
+
+

Changing Parameters

+
+
+

If the SPI Flash used supports higher frequencies or offers enhanced features, modifying the corresponding parameters can greatly speed up the Flash access speed. +The parameter modification does not require turning off the SPI Flash read enable (memory_en). +Refer to the description of registers for details.

+
+
+
+
+
+

24. LPC Controller (D23:F0)

+
+
+

The LPC controller has the following features.

+
+
+
    +
  • +

    Compliant with LPC1.1 specification

    +
    • +
  • +

    Supports LPC access timeout counter

    +
    • +
  • +

    Supports Memory Read/Write access type

    +
    • +
  • +

    Supports Firmware Memory Read/Write access type (single byte)

    +
    • +
  • +

    Support I/O read/write access type

    +
    • +
  • +

    Support TPM I/O read/write access type

    +
    • +
  • +

    Support Memory access type address conversion

    +
    • +
  • +

    Support Serial IRQ specification, support 17 interrupt sources

    +
    • +
+
+
+

24.1. LPC Configuration Register (D23:F0)

+ + +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 302. LPC controller configuration registers
Address OffsetAbbreviationDescriptionDefault valueRead/Write

00h-01h

VID

Vendor ID

0014h

RO

02h-03h

DID

Device ID

7A0Ch

RO

04h-05h

PCICMD

PCI Command

0001h

R/W, RO

08h

RID

Revision ID

00h

RO

09h

PI

Programming Interface

00h

RO

0Ah

SCC

Sub Class Code

01h

RO

0Bh

BCC

Base Class Code

06h

RO

0Ch

CLS

Cache Line Size

00h

RO

0Eh

HEADTYP

Header Type

00h

RO

10h-17h

FIXCREG*

Fixed Control Register

0000000010002004h

RO

18h-1Fh

FIXMREG*

Fixed Memory Register

0000000012000004h

RO

20h-27h

FIXIOREG*

Fixed I/O Register

000000FDFC000001h

RO

2Ch-2Dh

SVID

Subsystem Vendor ID

0000h

RO

2Eh-2Fh

SID

Subsystem Identification

0000h

RO

3Ch

INT_LN

Interrupt Line

00h

R/W

3Dh

INT_PN

Interrupt Pin

01h

RO

+
+

Note: Address space not listed in the table indicates reserved.

+
+
+

* See the subsequent FIXCREG/FIXMREG/FIXIOREG and Appendix 2 for more information.

+
+
+

Registers that differ slightly from the PCI configuration header specification and their descriptions are listed below.

+
+
+

PCICMD - PCI Command Register (LPC - D23:F0)

+
+
+

Address Offset: 04-05h

+
+
+

Attribute: R/W, RO

+
+
+

Default value: 0000h

+
+
+

Size: 16 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 303. PCI command register
Bit FieldNameRead/WriteDescription

15:2

Reserved

RO

Reserved.

1

Memory Space Enable

R/W

This bit is used to control whether access to the LPC control registers and MEM space is enabled.

+

0: Disable access.

+

1: Enable access to the LPC control registers and MEM space

0

I/O Space Enable

R/W

This bit is used to control whether access to the LPC I/O space is enabled. +The address of the LPC I/O space is fixed starting from address 0 of the I/O space.

+

0: Disable access.

+

1: Enable access to the LPC I/O space.

+
+

FIXCREG - Fixed Control Register

+
+
+

This register is not used as the BAR of the LPC configuration header.

+
+
+

Address Offset: 10-17h

+
+
+

Attribute: RO

+
+
+

Default value: 0000000010002004h

+
+
+

Size: 64 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + +
Table 304. Fixed control register
Bit FieldNameRead/WriteDescription

63:0

Reserved

RO

Reserved.

+
+

FIXMREG - Fixed MEM Register

+
+
+

This register is not used as the BAR of the LPC configuration header.

+
+
+

Address Offset: 18-1Fh

+
+
+

Attribute: RO

+
+
+

Default value: 0000000012000004h

+
+
+

Size: 64 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + +
Table 305. Fixed MEM register
Bit FieldNameRead/WriteDescription

63:0

Reserved

RO

Reserved.

+
+

FIXIOREG - Fixed I/O Register

+
+
+

This register is not used as the BAR of the LPC configuration header.

+
+
+

Address Offset: 20-27h

+
+
+

Attribute: RO

+
+
+

Default value: 000000FDFC000001h

+
+
+

Size: 64 bits

+
+ + ++++++ + + + + + + + + + + + + + + + + +
Table 306. Fixed I/O register
Bit FieldNameRead/WriteDescription

63:0

Reserved

RO

Reserved.

+
+

The addresses of FIXCREG, FIXMREG, and FIXIOREG are the same as the BAR registers of the PCI configuration header, but these registers are not used as the BAR registers of the LPC configuration header. +Software can work around this hardware bug by modifying the PCI configuration read function so that the upper layer software is not affected. See Notes on the Use of the Software for more details.

+
+
+
+

24.2. LPC Access Address

+
+

The LPC controller consists of three address spaces: the control register space, the MEM space, and the I/O space.

+
+
+

The LPC control register space is used to configure the LPC controller, which is located in the fixed device address space of the bridge chip, starting at 0x1000,2000, with a size of 4KB.

+
+
+

The LPC MEM space is used to access the Memory/Firmware Memory devices mounted on the LPC bus. +The LPC MEM space is located in the fixed device address space of the bridge chip starting at 0x1200,0000 and is 32MB in size. +Processor accesses to the LPC MEM space are converted to LPC protocol Memory accesses and sent to the LPC bus. +Which type of Memory access is issued by the LPC controller is determined by the LPC controller’s control registers. +Addresses sent by the processor to this address space can be address converted. +The converted address is set by the LPC controller’s configuration register (LPC_MEM_TRANS).

+
+
+
+

24.3. LPC Interrupt

+
+

The LPC controller internally includes two types of interrupts: SIRQ interrupts and access timeout interrupts. +The LPC controller supports a total of 17 SIRQ interrupts, corresponding to the bits[16:0] of the interrupt-related register. +The access timeout interrupt corresponds to the bit[17] of the interrupt-related register.

+
+
+

The SIRQ interrupt is a level-triggered interrupt, and the value of the trigger level can be configured by the register. +The software should configure the trigger level of the SIRQ interrupt before enabling the SIRQ interrupt of the LPC controller. +The SIRQ interrupt does not need to be cleared by software.

+
+
+

The access timeout interrupt is edge-triggered, so if an LPC access timeout interrupt occurs, the software needs to write bit[17] of the interrupt clear register to clear the interrupt.

+
+
+
+

24.4. LPC Control Register

+
+

Control Register 0

+
+
+

Address Offset: 00-03h

+
+
+

Attribute: R/W

+
+
+

Default value: 0000FFFFh

+
+
+

Size: 4

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 307. Control register 0
Bit FieldNameRead/WriteDescription

31

SIRQ_EN

R/W

SIRQ interrupt enable control.

23

LPC_MEM_TRANS_EN

R/W

LPC Memory space address translation enable.

22:16

LPC_MEM_TRANS

R/W

The high 7-bit address (bit[31:25]) of the LPC Memory space after address translation.

15:0

LPC_SYNC_TIMEOUT

R/W

Threshold for LPC access timeout (minimum value 64).

+
+

Control Register 1

+
+
+

Address Offset: 04-07h

+
+
+

Attribute: R/W

+
+
+

Default value: 00000000h

+
+
+

Size: 4

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + +
Table 308. Control register 1
Bit FieldNameRead/WriteDescription

31

FIRMWARE_TYPE

R/W

LPC Memory space Firmware Memory access type configuration.

17:0

LPC_INT_EN

R/W

LPC interrupt enable, each bit corresponds to an interrupt source. +For each interrupt source:

+

0: Disable interrupt.

+

1: Enable interrupt.

+
+

LPC Interrupt Status Register

+
+
+

Address Offset: 08-0Bh

+
+
+

Attribute: R/W

+
+
+

Default value: 00000000h

+
+
+

Size: 4

+
+ + ++++++ + + + + + + + + + + + + + + + + +
Table 309. LPC interrupt status register
Bit FieldNameRead/WriteDescription

17:0

LPC_INT_SRC

RO

LPC Interrupt source indication, each bit corresponds to an interrupt source. +For each interrupt source:

+

0: Disable interrupt.

+

1: Enable interrupt.

+
+

LPC Interrupt Clear Register

+
+
+

Address Offset: 0C-0Fh

+
+
+

Attribute: WO

+
+
+

Default value: 00000000h

+
+
+

Size: 4

+
+ + ++++++ + + + + + + + + + + + + + + + + +
Table 310. LPC interrupt clear register
Bit FieldNameRead/WriteDescription

17

LPC_TIMEOUT_INT_CLEAR

WO

LPC access timeout interrupt clear (write 1 to clear). +Bit 17 corresponds to LPC access timeout interrupt. +Write 1 to clear, write 0 to be invalid.

+
+

LPC SIRQ Interrupt Polarity Register

+
+
+

Address Offset: 10-13h

+
+
+

Attribute: R/W

+
+
+

Default value: 0000FFFBh

+
+
+

Size: 4

+
+ + ++++++ + + + + + + + + + + + + + + + + +
Table 311. LPC SIRQ interrupt polarity register
Bit FieldNameRead/WriteDescription

16:0

SIRQ_INT_POLARITY

R/W

LPC SIRQ interrupt polarity register, each bit corresponds to an interrupt source. +For each interrupt source:

+

0: Low level trigger.

+

1: High level trigger.

+
+
+
+
+

Appendix A: Table of Pin Multiplexing

+
+
+

The chip pins are multiplexed as shown in the following table.

+
+ + ++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 312. Table of chip pin function multiplexing

Function 0 (Default)

Function 1

Function 2

Function 3

VSB_GATEn

GPIO01

CLKOUT25M

GPIO02

CLKOUTFLEX

GPIO03

PWM0

GPIO04

PWM1

GPIO05

PWM2

GPIO06

PWM3

GPIO07

I2C0_SCL

GPIO08

I2C0_SDA

GPIO09

I2C1_SCL

GPIO10

I2C1_SDA

GPIO11

SPI_CSn0

GPIO12

I2C4_SCL

SPI_CSn1

GPIO13

I2C4_SDA

SPI_CSn2

GPIO14

I2C5_SCL

SPI_CSn3

GPIO15

I2C5_SDA

SPI_SDI

GPIO16

SPI_SDO

GPIO17

SPI_SCK

GPIO18

HDA_BITCLK

GPIO19

AC97_BITCLK

HDA_SYNC

GPIO20

AC97_SYNC

HDA_RESETn

GPIO21

AC97_RSTn

HDA_SDO

GPIO22

AC97_SDO

HDA_SDI0

GPIO23

AC97_SDI

HDA_SDI1

GPIO24

HDA_SDI2

GPIO25

SATA0_LEDn

GPIO26

SATA1_LEDn

GPIO27

SATA2_LEDn

GPIO28

USB_OC_0

GPIO29

USB_OC_1

GPIO30

USB_OC_2

GPIO31

UART3_RXD

GPIO32

UART_DCD

I2C2_SCL

UART3_TXD

GPIO33

UART_RI

I2C2_SDA

UART2_RXD

GPIO34

UART_DSR

I2C3_SCL

UART2_TXD

GPIO35

UART_DTR

I2C3_SDA

UART1_RXD

GPIO36

UART_CTS

UART1_TXD

GPIO37

UART_RTS

UART0_RXD

GPIO38

UART_RXD

UART0_TXD

GPIO39

UART_TXD

LPC_AD0

GPIO40

LPC_AD1

GPIO41

LPC_AD2

GPIO42

LPC_AD3

GPIO43

LPC_SERIRQ

GPIO44

LPC_FRAMEn

GPIO45

SYS_CLKSEL0

GPIO46

SYS_CLKSEL1

GPIO47

SYS_CLKSEL2

GPIO48

SYS_CLKSEL3

GPIO49

SYS_CLKSEL4

GPIO50

SYS_CLKSEL5

GPIO51

SYS_CLKSEL6

GPIO52

SYS_CLKSEL7

GPIO53

SYS_PCIEBRGMODE

GPIO54

HT_8x2

GPIO55

SYS_CLKSEL8

GPIO56

+
+

Note: All signals of HDA and LPC can only be multiplexed as a whole, and each pin cannot be controlled individually. +For example, if the AC97 function is enabled, pin HDA_SDI1/2 cannot be used as other functions.

+
+
+
+
+

Appendix B: Notes on the Use of the Software

+
+
+

Currently, there are five[2] problems that need to be fixed by the software for the bridge piece.

+
+
+
    +
  1. +

    PCI device scanning problem

    +
    +

    The correct value of the subclass code of the PCI device header of the PCIE bridge integrated in the bridge chip should be 0x04 (for PCI type bridge), but this bridge chip will now be 0x00 (for Host type bridge).

    +
    +
    +

    Solution: When the read configuration header access is found, if the access address is bus 0 of the device 9 to 20 and the address is 0x8, directly return 0x06040001, and not return the hardware read value.

    +
    +
    2. +
  2. +

    PCI device scanning problem

    +
    +

    For the PCIE bridge integrated in the bridge chip, when scanning the lower bus, when scanning the non-0 device, it should return an invalid value, but this bridge chip will return the configuration header of the 0 device, causing the 0 device to be found repeatedly.

    +
    +
    +

    Solution: For PCIE bridges integrated in the bridge, the lower bus only scans for device 0 and no other device number is scanned.

    +
    +
    3. +
  3. +

    PCI device scanning problem

    +
    +

    The Memory Space Enable control bits of the PCI configuration headers of the OHCI (Function 0) and EHCI (Function 1) controllers of the USB devices (Device 4 and Device 5) are reversed. +That is, the Memory Space Enable bit of EHCI controls the Mem space enable of OHCI, while the Memory Space Enable bit of OHCI controls the Mem space enable of EHCI.

    +
    +
    +

    Solution: Fix by software.

    +
    +
    4. +
  4. +

    GMAC DMA64 problem

    +
    +

    In 64-bit DMA mode, the high 32-bit register (0x1094) of the GMAC’s transmit descriptor base address can only be read, but not written.

    +
    +
    +

    Solution: Write to the high 32-bit register (0x1094) by writing the following addresses {0x10a8[31:8], 0x1068[7:0]}.

    +
    +
    5. +
  5. +

    LPC FIXIOREG problem

    +
    +

    The FIXCREG/FIXMREG/FIXIOREG of the LPC is used as an internal reserved register and is not used as a BAR in the PCI configuration header, but the hardware implementation incorrectly places its address in the location of the PCI configuration header BAR. +The software should treat the BAR register location of the LPC as an invalid BAR, but needs to enable I/O and MEM space access for the LPC.

    +
    +
    +

    Solution: In the PCI configuration read access function, when the device found to be read is LPC (B0:D23:F0) and the address is equal to the address of BAR0/1/2/3/4/5 (0x10 to 0x27), return data 0 directly.

    +
    +
    6. +
  6. +

    Concurrent access of DC control registers problem

    +
    +

    The DC’s control registers do not support simultaneous write accesses by multiple processors, regardless of whether the destination registers for these write accesses are the same. +That is, only one processor can write to the DC’s control register space at any given time.

    +
    +
    +

    Solution: The kernel prevents multiple processors from writing to the DC control register space at the same time by adding a lock.

    +
    +
    7. +
+
+
+
+
+
+
+
+1. Translator’s note: The original table is missing. +
+
+2. Translator’s note: Maybe six. +
+
+ + +
+ + Creative Commons License + +
+ This work is licensed under a + Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License. +
+ + + + + + + + + \ No newline at end of file diff --git a/Loongson-7A1000-usermanual-EN.pdf b/Loongson-7A1000-usermanual-EN.pdf new file mode 100644 index 0000000..0f968d1 Binary files /dev/null and b/Loongson-7A1000-usermanual-EN.pdf differ diff --git a/README-CN.html b/README-CN.html new file mode 100644 index 0000000..b59e771 --- /dev/null +++ b/README-CN.html @@ -0,0 +1,433 @@ + + + + + + + + +龙芯架构文档 + + + + +
+
+

简介

+
+
+

这是龙芯架构文档。

+
+
+
    +
  • +

    您可以在 这里 找到在线文档。

    +
    • +
  • +

    您可以在 这里 找到所有历史版本。

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因为文档中存在过长的表格，而且 HTML 版本的主题更易定制，所以 HTML 版本比 PDF 版本更好阅读。 +为了方便下载，每个 HTML 页面都嵌入了 CSS 和图像。

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文档

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    龙芯架构参考手册 - 卷一：基础架构： 该手册介绍了龙芯架构中基础架构部分的内容。

    +
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    • +
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    龙芯架构参考手册 - 卷二：向量指令扩展： 该手册介绍了龙芯架构中向量指令扩展（SIMD 和 高级 SIMD 扩展）部分的内容。（待定）

    +
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    • +

      原始文档 。

      +
      • +
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    龙芯架构参考手册 - 卷三：虚拟化及二进制翻译扩展：该手册介绍了龙芯架构中虚拟化及二进制翻译扩展部分的内容。（待定）

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      原始文档 。

      +
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    龙芯 3A5000/3B5000 处理器寄存器使用手册 - 多核处理架构、寄存器描述与系统软件编程指南：该手册介绍了龙芯 3A5000/3B5000 多核处理器架构与寄存器描述。

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    龙芯 7A1000 桥片用户手册：该手册介绍了桥片总体架构、时钟结构、地址空间、配置寄存器以及各个功能接口，主要供 BIOS 和内核开发人员使用。

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  • +

    龙芯架构 ELF psABI：该手册介绍了龙芯架构 ELF psABI。

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    龙芯架构工具链约定：该手册介绍了龙芯架构工具链的命令行界面和操作系统相关惯例。

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    • +
  • +

    龙芯架构 SMBIOS 规范：该文档定义了龙芯架构处理器附加信息，是 SMBIOS 结构 type 44 的补充。本文档仅提供 英文版。

    +
    + +
    +
    • +
+
+
+
+
+

开始

+
+
+

我们 强烈建议 您在 Linux/UNIX 或 macOS 上开发。 +如果您想在 Windows 上开发, 先参阅 在 Windows 上开发 。

+
+
+
    +
  1. +

    确保 Ruby 开发环境 已经安装。

    +
    2. +
  2. +

    安装 bunlder：

    +
    +
    +
    gem install bundler
    +
    +
    +
    3. +
  3. +

    克隆该项目：

    +
    +
    +
    git clone https://github.com/loongson/LoongArch-Documentation
    +
    +
    +
    4. +
  4. +

    进入项目仓库，并使用 bundle 命令安装 gems 到该项目（这会花一些时间，期间大约 20MB 的数据会被下载）：

    +
    +
    +
    cd LoongArch-Documentation
+bundle config set --local path .bundle/gems
+bundle
    +
    +
    +
    5. +
  5. +

    现在您可以生产文档了。

    +
    +
      +
    • +

      把 AsciiDoc 转换成 HTML 和 PDF：

      +
      +
      +
      bundle exec rake book:all
      +
      +
      +
      • +
    • +

      只把 AsciiDoc 转换成 HTML：

      +
      +
      +
      bundle exec rake book:html
      +
      +
      +
      • +
    • +

      只把 AsciiDoc 转换成 PDF：

      +
      +
      +
      bundle exec rake book:pdf
      +
      +
      +
      • +
    • +

      把特定的 book.adoc 转换成 HTML：

      +
      +
      +
      bundle exec rake book:html['book.adoc']
      +
      +
      +
      • +
    • +

      把特定的 book.adoc 转换成 PDF：

      +
      +
      +
      bundle exec rake book:pdf['book.adoc']
      +
      +
      +
      • +
    +
    +
    6. +
+
+
+
+
+

贡献

+
+
+

感谢您花时间为该项目作贡献！

+
+
+

您可以直接创建一个 issue 或发起一个 pull request。 +如果您提交了一个 pull request，在成功渲染后，您可以在 这里 看到预览版本。

+
+
+

编写文档时请遵循 风格指南 。

+
+
+

HTML 版本的文档会被自动部署，而 PDF 版本的文档则由手动发布。 +如果您在 release 页面 上的文档中发现问题，请复查它是否依然在该仓库中存在。 +这个问题可能已经被更正，而修改的内容还未发布。

+
+
+

gh-pages 分支是由 Github Actions 自动生成的，用于给 Github Pages 来发布项目网站。 +所以您不应该直接修改该分支。

+
+
+
+
+

引用

+
+
+ +
+
+
+
+

问题解决

+
+
+

在 Windows 上开发

+
+

一些文件的路径过长，超过了 Windows API 的 260 个字符的限制，这可能导致一些奇怪的问题。

+
+
+

在 Windows 10 1607 版本或更新的版本中，这些问题能被解决。 +如果您使用了一个早期的版本，或者您不想进行一些额外的操作，您可以考虑使用 Docker，具体细节参考 在 Docker 上开发 。

+
+
+
    +
  1. +

    启用 长路径支持。

    +
    2. +
  2. +

    使用最新的 Git 。 +用 Git Bash 执行所有命令。 +运行 git config --global core.longpaths true 来修改全局配置或在仓库中运行 git config core.longpaths true 来修改本地配置。

    +
    3. +
  3. +

    使用最新的 JRuby 来替代 Ruby。

    +
    4. +
+
+
+

剩余部分和 开始 部分的一样，但 JRuby 运行起来要慢得多，而且在运行命令时可能会伴随 cmd 弹窗。

+
+
+
+

在 Docker 上开发

+
+

我们假设您知道如何使用 Docker 进行开发。 +如果您不知道，请参考 官方教程 。

+
+
+

您可能会觉得官方的 Docker 容器 很有用。

+
+
+
+
+
+

许可证

+
+
+

This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License. +To view a copy of this license, visit http://creativecommons.org/licenses/by-nc-nd/4.0/ or send a letter to Creative Commons, PO Box 1866, Mountain View, CA 94042, USA.

+
+
+
+
+

贡献者

+
+
+

自从该项目发布，我们已经收到了一些纠错和贡献的内容修改。 +下面列出所有为开源项目 LoongArch Documentation 作贡献的人。 +感谢每一个帮助完善该项目的人。

+
+
+

贡献者按字母顺序列出：

+
+
+
+
Chao LI <lichao@loongson.cn>
+Chenghua Xu <xuchenghua@loongson.cn>
+Dandan Zhang <zhangdandan@loongson.cn>
+Feiyang Chen <chenfeiyang@loongson.cn>
+FreeFlyingSheep <fyang.168.hi@163.com>
+Konstantin Romanov <konstantinsromanov@gmail.com>
+LI Chao <lichao@loongson.cn>
+limeidan <limeidan@loongson.cn>
+liuzhensong <liuzhensong@loongson.cn>
+mengqinggang <mengqinggang@loongson.cn>
+Qi Hu <huqi@loongson.cn>
+qmuntal <quimmuntal@gmail.com>
+tangxiaolin <tangxiaolin@loongson.cn>
+WANG Xuerui <git@xen0n.name>
+wangguofeng <wangguofeng@loongson.cn>
+Wu Xiaotian <wuxiaotian@loongson.cn>
+Wu Xiaotian <yetist@gmail.com>
+Xi Ruoyao <xry111@mengyan1223.wang>
+Yang Yujie <yangyujie@alumni.sjtu.edu.cn>
+Yang Yujie <yangyujie@loongson.cn>
+Yanteng <siyanteng@loongson.cn>
+Yanteng Si <siyanteng@loongson.cn>
+
+
+
+
+
+ + +
+ + Creative Commons License + +
+ This work is licensed under a + Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License. +
+ + + + + + + + + \ No newline at end of file diff --git a/README-CN.pdf b/README-CN.pdf new file mode 100644 index 0000000..3e06ed5 Binary files /dev/null and b/README-CN.pdf differ diff --git a/README-EN.html b/README-EN.html new file mode 100644 index 0000000..716ced5 --- /dev/null +++ b/README-EN.html @@ -0,0 +1,475 @@ + + + + + + + + +LoongArch Documentation + + + + +
+
+

Introduction

+
+
+

The documentation for LoongArch.

+
+
+
    +
  • +

    You can find documents online here.

    +
    • +
  • +

    You can find all historical versions here.

    +
    • +
+
+
+

The HTML versions are more readable than the PDF versions, not only because there exist tables of excessive length, but also because the theme of HTML versions is easier to customize. +To make it easier to download, each HTML page contains embedded CSS and images.

+
+
+
+
+

Documents

+
+
+
    +
  • +

    LoongArch Reference Manual - Volume 1: Basic Architecture: This manual describes the basic part of the LoongArch architecture.

    +
    + +
    +
    • +
  • +

    LoongArch Reference Manual - Volume 2: Vector Extensions: This manual describes the vector extensions (SIMD and Advanced SIMD Extensions) of the LoongArch architecture. (TBD)

    +
    +
      +
    • +

      HTML version.

      +
      • +
    • +

      PDF version.

      +
      • +
    • +

      Original document.

      +
      • +
    +
    +
    • +
  • +

    LoongArch Reference Manual - Volume 3: Virtualization and Binary Translation Extensions: This manual describes the virtualization and binary translation extensions of the LoongArch architecture. (TBD)

    +
    +
      +
    • +

      HTML version.

      +
      • +
    • +

      PDF version.

      +
      • +
    • +

      Original document.

      +
      • +
    +
    +
    • +
  • +

    Loongson 3A5000/3B5000 Processor Reference Manual - Multicore Processor Architecture, Register Descriptions and System Software Programming Guide: This manual introduces the Loongson 3A5000/3B5000 multicore processor architecture and register descriptions.

    +
    + +
    +
    • +
  • +

    Loongson 7A1000 Bridge User Manual: This manual describes the overall bridge architecture, clock structure, address space, configuration registers, and individual functional interfaces, primarily for BIOS and kernel developers.

    +
    + +
    +
    • +
  • +

    LoongArch ELF psABI: This manual describes the LoongArch ELF psABI.

    +
    + +
    +
    • +
  • +

    LoongArch toolchain conventions: This document describes the command-line interface and relevant OS conventions of LoongArch toolchains.

    +
    + +
    +
    • +
  • +

    LoongArch Processor SMBIOS Spec: This document introduces additional information about LoongArch in SMBIOS.

    +
    + +
    +
    • +
+
+
+
+
+

Translator’s Note

+
+
+

Due to the limited knowledge of the translators, there are some inevitable errors and omissions existing in this document, please feel free to correct.

+
+
+

P.S. Since the academic level of the original authors is extraordinary high, words and phrases in the original documents are so profound that the translators with limited knowledge could not express them accurately even if they tried their best.

+
+
+
+
+

Getting Started

+
+
+

We strongly recommend that you develop on Linux/UNIX or macOS. +If you want to develop on Windows, see Developing on Windows first.

+
+
+
    +
  1. +

    Make sure the Ruby development environment is installed.

    +
    2. +
  2. +

    Install bunlder:

    +
    +
    +
    gem install bundler
    +
    +
    +
    3. +
  3. +

    Clone this project:

    +
    +
    +
    git clone https://github.com/loongson/LoongArch-Documentation
    +
    +
    +
    4. +
  4. +

    Enter the project repo and install the gems into the project using the bundle command (this will take a while, during which time about 20MB of data will be downloaded):

    +
    +
    +
    cd LoongArch-Documentation
+bundle config set --local path .bundle/gems
+bundle
    +
    +
    +
    5. +
  5. +

    Now you can generate the documents.

    +
    +
      +
    • +

      Convert AsciiDoc to both HTML and PDF:

      +
      +
      +
      bundle exec rake book:all
      +
      +
      +
      • +
    • +

      Convert AsciiDoc to HTML only:

      +
      +
      +
      bundle exec rake book:html
      +
      +
      +
      • +
    • +

      Convert AsciiDoc to PDF only:

      +
      +
      +
      bundle exec rake book:pdf
      +
      +
      +
      • +
    • +

      Convert specified book.adoc to HTML:

      +
      +
      +
      bundle exec rake book:html['book.adoc']
      +
      +
      +
      • +
    • +

      Convert specified book.adoc to PDF:

      +
      +
      +
      bundle exec rake book:pdf['book.adoc']
      +
      +
      +
      • +
    +
    +
    6. +
+
+
+
+
+

Contributing

+
+
+

Thank you for taking the time to contribute!

+
+
+

You can create an issue or submit a pull request directly. +If you submit a pull request, you can see the preview version here after successful rendering.

+
+
+

Please follow the Style Guide when writing documents.

+
+
+

The HTML versions of documents will be deployed automatically, while the PDF versions will be published manually. +If you find an issue in the documents as found on the release page, please cross-check that it is still present in this repo. +The issue may have already been corrected, but the changes have not been published yet.

+
+
+

Branch gh-pages is generated by Github Actions, which is used to publish a project site by Github Pages. +So you should not modify this branch directly.

+
+
+
+
+

References

+
+
+ +
+
+
+
+

Troubleshooting

+
+
+

Developing on Windows

+
+

Some of the file paths are so long that they exceed the 260-character limit of the Windows API, which can cause some strange problems.

+
+
+

In Windows 10 version 1607 and later, these problems can be solved. +If you are using an earlier version, or if you don’t want to do some extra operations, you might consider using Docker, refer to Developing on Docker for more details.

+
+
+
    +
  1. +

    Enable long paths.

    +
    2. +
  2. +

    Use the latest Git. +Execute all commands with Git Bash. +Run git config --global core.longpaths true to modify the global configuration or run git config core.longpaths true in the repo to modify the local configuration.

    +
    3. +
  3. +

    Use the latest JRuby instead of Ruby.

    +
    4. +
+
+
+

The rest is the same as in Getting Started, but JRuby runs much slower and may have cmd popups when running commands.

+
+
+
+

Developing on Docker

+
+

We assume you know how to develop with Docker. +If you don’t, please refer to the official tutorial.

+
+
+

You may find the official Docker container useful.

+
+
+
+
+
+

License

+
+
+

This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License. +To view a copy of this license, visit http://creativecommons.org/licenses/by-nc-nd/4.0/ or send a letter to Creative Commons, PO Box 1866, Mountain View, CA 94042, USA.

+
+
+
+
+

Contributors

+
+
+

Since the release of the project, we have gotten several errata and content changes donated. +Here are all the people who have contributed to LoongArch Documentation as an open source project. +Thank you everyone for helping make this project better.

+
+
+

The contributors are listed in alphabetical order:

+
+
+
+
Chao LI <lichao@loongson.cn>
+Chenghua Xu <xuchenghua@loongson.cn>
+Dandan Zhang <zhangdandan@loongson.cn>
+Feiyang Chen <chenfeiyang@loongson.cn>
+FreeFlyingSheep <fyang.168.hi@163.com>
+Konstantin Romanov <konstantinsromanov@gmail.com>
+LI Chao <lichao@loongson.cn>
+limeidan <limeidan@loongson.cn>
+liuzhensong <liuzhensong@loongson.cn>
+mengqinggang <mengqinggang@loongson.cn>
+Qi Hu <huqi@loongson.cn>
+qmuntal <quimmuntal@gmail.com>
+tangxiaolin <tangxiaolin@loongson.cn>
+WANG Xuerui <git@xen0n.name>
+wangguofeng <wangguofeng@loongson.cn>
+Wu Xiaotian <wuxiaotian@loongson.cn>
+Wu Xiaotian <yetist@gmail.com>
+Xi Ruoyao <xry111@mengyan1223.wang>
+Yang Yujie <yangyujie@alumni.sjtu.edu.cn>
+Yang Yujie <yangyujie@loongson.cn>
+Yanteng <siyanteng@loongson.cn>
+Yanteng Si <siyanteng@loongson.cn>
+
+
+
+
+
+ + +
+ + Creative Commons License + +
+ This work is licensed under a + Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License. +
+ + + + + + + + + \ No newline at end of file diff --git a/README-EN.pdf b/README-EN.pdf new file mode 100644 index 0000000..b182148 Binary files /dev/null and b/README-EN.pdf differ diff --git a/index.html b/index.html new file mode 100644 index 0000000..8cef42c --- /dev/null +++ b/index.html @@ -0,0 +1,85 @@ + + + + + + + + +LoongArch Documentation | 龙芯架构文档 + + + + +
+
+
+
+ +
+
+
+
+ + +
+ + Creative Commons License + +
+ This work is licensed under a + Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License. +
+ + + + + + + + + \ No newline at end of file diff --git a/index.pdf b/index.pdf new file mode 100644 index 0000000..e1c8316 Binary files /dev/null and b/index.pdf differ diff --git a/style-guide-CN.html b/style-guide-CN.html new file mode 100644 index 0000000..0ec39c5 --- /dev/null +++ b/style-guide-CN.html @@ -0,0 +1,227 @@ + + + + + + + +风格指南 + + + + +
+
+

项目布局

+
+
+
+
.
+|-- contributors.txt            # 贡献者
+|-- docs                        # 文档目录
+|   |-- index.adoc              # Github Pages 上的主页
+|   |-- Document1               # 小节（级别 0）目录
+|   |   |-- section1            # 小节（级别 1）目录
+|   |   |   |-- section1-1.adoc # 小节（级别 2）
+|   |   |   `-- ...
+|   |   |-- section1.adoc       # 小节（级别 1）
+|   |   `-- ...
+|   |-- Document1.adoc          # 小节（级别 0）
+|   |-- README-CN.adoc          # 中文版 README
+|   |-- README-EN.adoc          # 英文版 README
+|   `-- ...
+|-- fonts                       # 字体目录
+|-- Gemfile
+|-- images                      # 图像目录
+|   |-- Document1               # Document1 的图像目录
+|   `-- ...
+|-- LICENSE                     # 许可证
+|-- public                      # 输出目录
+|-- Rakefile
+|-- README.adoc                 # README
+|-- themes                      # 主题目录
+|   |-- docinfo-footer.html
+|   |-- html.css                # HTML 主题
+|   `-- pdf.yml                 # PDF 主题
+`-- ...
+
+
+
+

文件名全部使用小写字母，用 “-” 来替代空格。 +英文/中文文档以 “EN”/“CN” 结尾。 +文件命名和目录结构应该和标题级别保持一致。

+
+
+
+
= 文档标题（级别 0）
+
+== 级别 1 小节标题
+
+=== 级别 2 小节标题
+
+...
+
+
+
+
+
+

小节

+
+
+

在写小节标题时大写每个单词的首字母。

+
+
+

自定义的 ID 必须以英文字母开头，且内容只包含小写字母、阿拉伯数字和 “-”。 +把自定义的小节 ID（[[id]]）放到小节标题上面：

+
+
+
+
[[section-id]]
+== 小节标题
+
+参考 <<section-id,小节标题>> 。
+
+
+
+

如果有很多重复的标题，不要使用自动生成的小节 ID。

+
+
+
+
+

HTML 实体

+
+
+

Asciidoctor PDF 不支持所有命名的 HTML 实体（例如 &times;），所以您必须在这里使用实体编号（例如 &#215;）。

+
+
+
+
+

表格

+
+
+

用以下格式来画表格（表格标题仅首字母大写）：

+
+
+
+
[[table-id]]
+.表格标题
+[%header,cols="3*1"]
+|===
+|列 1
+|列 2
+|列 3
+
+|列 1，行 2 的单元格
+|列 2，行 2 的单元格
+|列 3，行 2 的单元格
+
+|列 1，行 3 的单元格
+|列 2，行 3 的单元格
+|列 3，行 3 的单元格
+|===
+
+
+ + +++++ + + + + + + + + + + + + + + + + + + + +
Table 1. 表格标题
列 1列 2列 3

列 1，行 2 的单元格

列 2，行 2 的单元格

列 3，行 2 的单元格

列 1，行 3 的单元格

列 2，行 3 的单元格

列 3，行 3 的单元格

+
+
+
+

目录

+
+
+

我们推荐您使用工具而不是手动维护“表目录”和“图目录”。

+
+
+

Golang AsciiDoc Tools 仓库可能有有用的工具。

+
+
+
+
+ + +
+ + Creative Commons License + +
+ This work is licensed under a + Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License. +
+ + + + + + + + + \ No newline at end of file diff --git a/style-guide-CN.pdf b/style-guide-CN.pdf new file mode 100644 index 0000000..89c2317 Binary files /dev/null and b/style-guide-CN.pdf differ diff --git a/style-guide-EN.html b/style-guide-EN.html new file mode 100644 index 0000000..8b52d69 --- /dev/null +++ b/style-guide-EN.html @@ -0,0 +1,227 @@ + + + + + + + +Style Guide + + + + +
+
+

Project layout

+
+
+
+
.
+|-- contributors.txt            # Contributors
+|-- docs                        # Documents dir
+|   |-- index.adoc              # Homepage on Github Pages
+|   |-- Document1               # Section's (Level 0) dir
+|   |   |-- section1            # Section's (Level 1) dir
+|   |   |   |-- section1-1.adoc # Section (Level 2)
+|   |   |   `-- ...
+|   |   |-- section1.adoc       # Section (Level 1)
+|   |   `-- ...
+|   |-- Document1.adoc          # Section (Level 0)
+|   |-- README-CN.adoc          # README in Chinese
+|   |-- README-EN.adoc          # README in English
+|   `-- ...
+|-- fonts                       # Fonts dir
+|-- Gemfile
+|-- images                      # Images dir
+|   |-- Document1               # Document1's image dir
+|   `-- ...
+|-- LICENSE                     # License
+|-- public                      # Output dir
+|-- Rakefile
+|-- README.adoc                 # README
+|-- themes                      # Themes dir
+|   |-- docinfo-footer.html
+|   |-- html.css                # HTML theme
+|   `-- pdf.yml                 # PDF theme
+`-- ...
+
+
+
+

File names are all lowercase, with “-” instead of spaces. +The file name of the document in English/Chinese ends with “EN”/“CN”. +File naming and folder structure should be consistent in the title level.

+
+
+
+
= Document Title (Level 0)
+
+== Level 1 Section Title
+
+=== Level 2 Section Title
+
+...
+
+
+
+
+
+

Section

+
+
+

Capitalize the first letter of each word when writing a section title.

+
+
+

Custom IDs must start with a letter and contain only lowercase letters and Arabic numerals and “-”. +Put the custom section ID ([[id]]) above the section title:

+
+
+
+
[[section-id]]
+== Section Title
+
+Refer to <<section-id,Section Title>>.
+
+
+
+

Do not use autogenerated section IDs if there are many duplicate titles.

+
+
+
+
+

HTML Entities

+
+
+

Asciidoctor PDF doesn’t support all named HTML entities (e.g. &times;), so you have to use entity numbers (e.g. &#215;) here.

+
+
+
+
+

Tables

+
+
+

Use the following format to write a table (capitalize only the first letter of the table title):

+
+
+
+
[[table-id]]
+.Table title
+[%header,cols="3*1"]
+|===
+|Column 1
+|Column 2
+|Column 3
+
+|Cell in column 1, row 2
+|Cell in column 2, row 2
+|Cell in column 3, row 2
+
+|Cell in column 1, row 3
+|Cell in column 2, row 3
+|Cell in column 3, row 3
+|===
+
+
+ + +++++ + + + + + + + + + + + + + + + + + + + +
Table 1. Table title
Column 1Column 2Column 3

Cell in column 1, row 2

Cell in column 2, row 2

Cell in column 3, row 2

Cell in column 1, row 3

Cell in column 2, row 3

Cell in column 3, row 3

+
+
+
+

Table of Contents

+
+
+

We recommend that you use tools rather than maintaining the “List of Tables” and the “List of Figures” manually.

+
+
+

See Golang AsciiDoc Tools for tools that may be useful.

+
+
+
+
+ + +
+ + Creative Commons License + +
+ This work is licensed under a + Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International License. +
+ + + + + + + + + \ No newline at end of file diff --git a/style-guide-EN.pdf b/style-guide-EN.pdf new file mode 100644 index 0000000..4372ef5 Binary files /dev/null and b/style-guide-EN.pdf differ