Bug or limitation when using "separately" to match regex expresion

[pevhall]

I'm trying to configure luochen1990/rainbow to work for VHDL files types..

To do this I'm using the "separately" option. However I've noticed that "separately" won't match on the following regex: \<\(else\|elsif\)\> I'm trying to match on the whole word "else" or the whole work "elsif".

My vimrc has the following setting:

    let g:rainbow_active = 1 "0 if you want to enable it later via :RainbowToggle
        let g:rainbow_conf = {
      \    'guifgs'  : ['RoyalBlue1', 'SeaGreen3', 'Orange', 'IndianRed', 'Magenta'],
      \    'ctermfgs': ['Blue', 'Cyan', 'Green', 'Red', 'Magenta'] ,
      \    'operators': '_,_',
      \    'separately': {
      \       '*': {},
      \       'vhdl' : {'parentheses': ['start=/(/ end=/)/ fold',  
      \                                 'start=/^\s*for\>/ end=/\<end loop\>/ fold', 
      \                                 'start=/^\s*if\>/ step=/\<\(else\|elsif\)\>/ end=/\<end if\>/ fold', 
      \                                 'start=/\<generate$/ step=/\<begin\>/ end=/\<end generate\>/ fold',  
      \                                 'start=/^\s*process\>/ step=/\<begin\>/ end=/\<end process\>/ fold']}
      \   }
      \ }

And this is an snip it from a test.vhd file I'm using the plugin on:

  process(clk_i)
    variable rand_fb_v : std_logic ;
  begin
    if rising_edge(clk_i) then
      if load_i = '1' then
        rand      <= load_val_i;
        rand_fb_v := load_val_i(0);
      elsif en_i = '1' then
        rand(WIDTH_g-1 downto 1) <= rand(WIDTH_g-2 downto 0);
        --an error below here might be cause from Vivado not probaly checking
        -- the assert in the get_lfsr_taps funciton above.
        if TAPS(4) = -1 and TAPS(3) = -1 then

          rand_fb_v := rand(TAPS(2)-1) xor
                       rand(TAPS(1)-1) ;
        else
          rand_fb_v := rand(TAPS(4)-1) xor
                       rand(TAPS(3)-1) xor
                       rand(TAPS(2)-1) xor
                       rand(TAPS(1)-1) ;
        end if;
        rand(0) <= rand_fb_v;
      end if;
      rand_fb <= rand_fb_v;
    end if;
  end process;

My issue is only the "else" whole word is matched/highlighted not the "eslif".

Should this work? Am I doing something wrong? Or is it a known limitation?

Thanks luochen1990 for you work. I have found your plugin very useful.

[luochen1990]

I find there is such a rule for vhdl builtin syntax:

vhdlStatement  xxx inout restrict_guarantee failure block range map view body downto others return fairness force of strong
                   shared guarded port entity vmode pure unaffected all protected alias open access property assume loop on
                   begin to signal use release end when constant with context procedure impure warning after wait label vprop
                   library register exit component default new file group then cover reject generic array elsif postponed
                   function record report select sequence null configuration bus generate for case note type parameter until
                   assert out transport disconnect severity while units linkage in attribute error next is literal inertial
                   variable process subtype assume_guarantee buffer vunit restrict package architecture
                   match /\<\(if\|else\)\>/
                   links to Statement

which means, "elsif" is defined as keyword in vim's default syntax files for VHDL. and rainbow step is defined as syntax match, which has a lower priority than syntax keyword....

maybe one solution is, syn clear vhdlStatement in the after option of rainbow, but this can cause other issues.
another solution is try to use some other VHDL syntax plugins, and hoping it has less confliction rules with your rainbow configuration... but there is no promise...