-
Notifications
You must be signed in to change notification settings - Fork 0
/
Copy pathSTORM_SoC_basic_map.mrp
380 lines (345 loc) · 26.1 KB
/
STORM_SoC_basic_map.mrp
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
Release 14.7 Map P.20131013 (lin64)
Xilinx Mapping Report File for Design 'STORM_SoC_basic'
Design Information
------------------
Command Line : map -intstyle ise -p xc6slx9-ftg256-3 -w -logic_opt off -ol
high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off
-pr off -lc off -power off -o STORM_SoC_basic_map.ncd STORM_SoC_basic.ngd
STORM_SoC_basic.pcf
Target Device : xc6slx9
Target Package : ftg256
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Mon Feb 23 19:59:37 2015
Design Summary
--------------
Number of errors: 0
Number of warnings: 16
Slice Logic Utilization:
Number of Slice Registers: 3,886 out of 11,440 33%
Number used as Flip Flops: 3,885
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 1
Number of Slice LUTs: 5,275 out of 5,720 92%
Number used as logic: 5,157 out of 5,720 90%
Number using O6 output only: 4,285
Number using O5 output only: 253
Number using O5 and O6: 619
Number used as ROM: 0
Number used as Memory: 70 out of 1,440 4%
Number used as Dual Port RAM: 68
Number using O6 output only: 4
Number using O5 output only: 0
Number using O5 and O6: 64
Number used as Single Port RAM: 0
Number used as Shift Register: 2
Number using O6 output only: 2
Number using O5 output only: 0
Number using O5 and O6: 0
Number used exclusively as route-thrus: 48
Number with same-slice register load: 11
Number with same-slice carry load: 37
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 1,426 out of 1,430 99%
Number of MUXCYs used: 824 out of 2,860 28%
Number of LUT Flip Flop pairs used: 5,531
Number with an unused Flip Flop: 1,822 out of 5,531 32%
Number with an unused LUT: 256 out of 5,531 4%
Number of fully used LUT-FF pairs: 3,453 out of 5,531 62%
Number of unique control sets: 130
Number of slice register sites lost
to control set restrictions: 341 out of 11,440 2%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 74 out of 186 39%
Number of LOCed IOBs: 66 out of 74 89%
IOB Flip Flops: 38
Specific Feature Utilization:
Number of RAMB16BWERs: 20 out of 32 62%
Number of RAMB8BWERs: 8 out of 64 12%
Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0%
Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
Number of BUFG/BUFGMUXs: 1 out of 16 6%
Number used as BUFGs: 1
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 0 out of 4 0%
Number of ILOGIC2/ISERDES2s: 16 out of 200 8%
Number used as ILOGIC2s: 16
Number used as ISERDES2s: 0
Number of IODELAY2/IODRP2/IODRP2_MCBs: 16 out of 200 8%
Number used as IODELAY2s: 16
Number used as IODRP2s: 0
Number used as IODRP2_MCBs: 0
Number of OLOGIC2/OSERDES2s: 22 out of 200 11%
Number used as OLOGIC2s: 22
Number used as OSERDES2s: 0
Number of BSCANs: 0 out of 4 0%
Number of BUFHs: 0 out of 128 0%
Number of BUFPLLs: 0 out of 8 0%
Number of BUFPLL_MCBs: 0 out of 4 0%
Number of DSP48A1s: 3 out of 16 18%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 0 out of 2 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 0 out of 2 0%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 4.42
Peak Memory Usage: 801 MB
Total REAL time to MAP completion: 1 mins 39 secs
Total CPU time to MAP completion: 1 mins 38 secs
Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group and Partition Summary
Section 10 - Timing Report
Section 11 - Configuration String Information
Section 12 - Control Set Information
Section 13 - Utilization by Hierarchy
Section 1 - Errors
------------------
Section 2 - Warnings
--------------------
WARNING:PhysDesignRules:367 - The signal
<STORM_TOP_INST/PROCESSOR_CORE/Register_File/Mram_REG_FILE21_RAMD_D1_O> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<STORM_TOP_INST/PROCESSOR_CORE/Register_File/Mram_REG_FILE22_RAMD_D1_O> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<STORM_TOP_INST/PROCESSOR_CORE/Register_File/Mram_REG_FILE4_RAMD_D1_O> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<STORM_TOP_INST/PROCESSOR_CORE/Register_File/Mram_REG_FILE6_RAMD_D1_O> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<STORM_TOP_INST/PROCESSOR_CORE/Register_File/Mram_REG_FILE24_RAMD_D1_O> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<STORM_TOP_INST/PROCESSOR_CORE/Register_File/Mram_REG_FILE1_RAMD_D1_O> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<STORM_TOP_INST/PROCESSOR_CORE/Register_File/Mram_REG_FILE11_RAMD_D1_O> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<STORM_TOP_INST/PROCESSOR_CORE/Register_File/Mram_REG_FILE13_RAMD_D1_O> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<STORM_TOP_INST/PROCESSOR_CORE/Register_File/Mram_REG_FILE25_RAMD_D1_O> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<STORM_TOP_INST/PROCESSOR_CORE/Register_File/Mram_REG_FILE12_RAMD_D1_O> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<STORM_TOP_INST/PROCESSOR_CORE/Register_File/Mram_REG_FILE15_RAMD_D1_O> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<STORM_TOP_INST/PROCESSOR_CORE/Register_File/Mram_REG_FILE14_RAMD_D1_O> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<STORM_TOP_INST/PROCESSOR_CORE/Register_File/Mram_REG_FILE3_RAMD_D1_O> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<STORM_TOP_INST/PROCESSOR_CORE/Register_File/Mram_REG_FILE23_RAMD_D1_O> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal
<STORM_TOP_INST/PROCESSOR_CORE/Register_File/Mram_REG_FILE5_RAMD_D1_O> is
incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:2410 - This design is using one or more 9K Block RAMs
(RAMB8BWER). 9K Block RAM initialization data, both user defined and
default, may be incorrect and should not be used. For more information,
please reference Xilinx Answer Record 39999.
Section 3 - Informational
-------------------------
INFO:LIT:243 - Logical network
STORM_TOP_INST/PROCESSOR_CORE/Register_File/Mram_REG_FILE261/SPO has no load.
INFO:LIT:395 - The above info message is repeated 5 more times for the following
(max. 5 shown):
STORM_TOP_INST/PROCESSOR_CORE/Register_File/Mram_REG_FILE72/SPO,
STORM_TOP_INST/PROCESSOR_CORE/Register_File/Mram_REG_FILE262/SPO,
STORM_TOP_INST/PROCESSOR_CORE/Register_File/Mram_REG_FILE71/SPO,
STORM_TOP_INST/PROCESSOR_CORE/Register_File/Mram_REG_FILE162/SPO,
STORM_TOP_INST/PROCESSOR_CORE/Register_File/Mram_REG_FILE161/SPO
To see the details of these info messages, please use the -detail switch.
INFO:MapLib:562 - No environment variables are currently set.
INFO:MapLib:159 - Net Timing constraints on signal CLK_I are pushed forward
through input buffer.
INFO:LIT:244 - All of the single ended outputs in this design are using slew
rate limited output drivers. The delay on speed critical single ended outputs
can be dramatically reduced by designating them as fast outputs.
INFO:Pack:1716 - Initializing temperature to 85.000 Celsius. (default - Range:
0.000 to 85.000 Celsius)
INFO:Pack:1720 - Initializing voltage to 1.140 Volts. (default - Range: 1.140 to
1.260 Volts)
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
INFO:Place:834 - Only a subset of IOs are locked. Out of 74 IOs, 66 are locked
and 8 are not locked. If you would like to print the names of these IOs,
please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1.
INFO:Pack:1650 - Map created a placed design.
Section 4 - Removed Logic Summary
---------------------------------
17 block(s) removed
2 block(s) optimized away
Section 5 - Removed Logic
-------------------------
The trimmed logic report below shows the logic removed from your design due to
sourceless or loadless signals, and VCC or ground connections. If the removal
of a signal or symbol results in the subsequent removal of an additional signal
or symbol, the message explaining that second removal will be indented. This
indentation will be repeated as a chain of related logic is removed.
To quickly locate the original cause for the removal of a chain of logic, look
above the place where that logic is listed in the trimming report, then locate
the lines that are least indented (begin at the leftmost edge).
Loadless block "SYSCON_CLK/DCM_SP_inst" (DCM_SP) removed.
Unused block "SDRAM/ctrl/iob_dq_g[0].iob_dq_iob/OBUFT" (TRI) removed.
Unused block "SDRAM/ctrl/iob_dq_g[10].iob_dq_iob/OBUFT" (TRI) removed.
Unused block "SDRAM/ctrl/iob_dq_g[11].iob_dq_iob/OBUFT" (TRI) removed.
Unused block "SDRAM/ctrl/iob_dq_g[12].iob_dq_iob/OBUFT" (TRI) removed.
Unused block "SDRAM/ctrl/iob_dq_g[13].iob_dq_iob/OBUFT" (TRI) removed.
Unused block "SDRAM/ctrl/iob_dq_g[14].iob_dq_iob/OBUFT" (TRI) removed.
Unused block "SDRAM/ctrl/iob_dq_g[15].iob_dq_iob/OBUFT" (TRI) removed.
Unused block "SDRAM/ctrl/iob_dq_g[1].iob_dq_iob/OBUFT" (TRI) removed.
Unused block "SDRAM/ctrl/iob_dq_g[2].iob_dq_iob/OBUFT" (TRI) removed.
Unused block "SDRAM/ctrl/iob_dq_g[3].iob_dq_iob/OBUFT" (TRI) removed.
Unused block "SDRAM/ctrl/iob_dq_g[4].iob_dq_iob/OBUFT" (TRI) removed.
Unused block "SDRAM/ctrl/iob_dq_g[5].iob_dq_iob/OBUFT" (TRI) removed.
Unused block "SDRAM/ctrl/iob_dq_g[6].iob_dq_iob/OBUFT" (TRI) removed.
Unused block "SDRAM/ctrl/iob_dq_g[7].iob_dq_iob/OBUFT" (TRI) removed.
Unused block "SDRAM/ctrl/iob_dq_g[8].iob_dq_iob/OBUFT" (TRI) removed.
Unused block "SDRAM/ctrl/iob_dq_g[9].iob_dq_iob/OBUFT" (TRI) removed.
Optimized Block(s):
TYPE BLOCK
GND XST_GND
VCC XST_VCC
To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.
Section 6 - IOB Properties
--------------------------
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
| IOB Name | Type | Direction | IO Standard | Diff | Drive | Slew | Reg (s) | Resistor | IOB |
| | | | | Term | Strength | Rate | | | Delay |
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
| BOOT_CONFIG_I<0> | IOB | INPUT | LVTTL | | | | | PULLUP | |
| BOOT_CONFIG_I<1> | IOB | INPUT | LVTTL | | | | | PULLUP | |
| BOOT_CONFIG_I<2> | IOB | INPUT | LVTTL | | | | | PULLUP | |
| BOOT_CONFIG_I<3> | IOB | INPUT | LVTTL | | | | | PULLUP | |
| CLK_I | IOB | INPUT | LVCMOS25 | | | | | | |
| GP_INPUT_I<0> | IOB | INPUT | LVCMOS25 | | | | | | |
| GP_INPUT_I<1> | IOB | INPUT | LVCMOS25 | | | | | | |
| GP_INPUT_I<2> | IOB | INPUT | LVCMOS25 | | | | | | |
| GP_INPUT_I<3> | IOB | INPUT | LVCMOS25 | | | | | | |
| GP_INPUT_I<4> | IOB | INPUT | LVCMOS25 | | | | | | |
| GP_INPUT_I<5> | IOB | INPUT | LVCMOS25 | | | | | | |
| GP_INPUT_I<6> | IOB | INPUT | LVCMOS25 | | | | | | |
| GP_INPUT_I<7> | IOB | INPUT | LVCMOS25 | | | | | | |
| GP_OUTPUT_O<0> | IOB | OUTPUT | LVTTL | | 8 | SLOW | | | |
| GP_OUTPUT_O<1> | IOB | OUTPUT | LVTTL | | 8 | SLOW | | | |
| GP_OUTPUT_O<2> | IOB | OUTPUT | LVTTL | | 8 | SLOW | | | |
| GP_OUTPUT_O<3> | IOB | OUTPUT | LVTTL | | 8 | SLOW | | | |
| GP_OUTPUT_O<4> | IOB | OUTPUT | LVTTL | | 8 | SLOW | | | |
| GP_OUTPUT_O<5> | IOB | OUTPUT | LVTTL | | 8 | SLOW | | | |
| GP_OUTPUT_O<6> | IOB | OUTPUT | LVTTL | | 8 | SLOW | | | |
| GP_OUTPUT_O<7> | IOB | OUTPUT | LVTTL | | 8 | SLOW | | | |
| I2C_SCL_IO | IOB | BIDIR | LVTTL | | 12 | SLOW | | PULLUP | |
| I2C_SDA_IO | IOB | BIDIR | LVTTL | | 12 | SLOW | | PULLUP | |
| LED_BAR_O<0> | IOB | OUTPUT | LVTTL | | 8 | SLOW | | | |
| LED_BAR_O<1> | IOB | OUTPUT | LVTTL | | 8 | SLOW | | | |
| LED_BAR_O<2> | IOB | OUTPUT | LVTTL | | 8 | SLOW | | | |
| LED_BAR_O<3> | IOB | OUTPUT | LVTTL | | 8 | SLOW | | | |
| LED_BAR_O<4> | IOB | OUTPUT | LVTTL | | 8 | SLOW | | | |
| LED_BAR_O<5> | IOB | OUTPUT | LVTTL | | 8 | SLOW | | | |
| LED_BAR_O<6> | IOB | OUTPUT | LVTTL | | 8 | SLOW | | | |
| LED_BAR_O<7> | IOB | OUTPUT | LVTTL | | 8 | SLOW | | | |
| RST_I | IOB | INPUT | LVTTL | | | | | PULLUP | |
| SDRAM_ADDR<0> | IOB | OUTPUT | LVTTL | | 12 | SLOW | OFF | | |
| SDRAM_ADDR<1> | IOB | OUTPUT | LVTTL | | 12 | SLOW | OFF | | |
| SDRAM_ADDR<2> | IOB | OUTPUT | LVTTL | | 12 | SLOW | OFF | | |
| SDRAM_ADDR<3> | IOB | OUTPUT | LVTTL | | 12 | SLOW | OFF | | |
| SDRAM_ADDR<4> | IOB | OUTPUT | LVTTL | | 12 | SLOW | OFF | | |
| SDRAM_ADDR<5> | IOB | OUTPUT | LVTTL | | 12 | SLOW | OFF | | |
| SDRAM_ADDR<6> | IOB | OUTPUT | LVTTL | | 12 | SLOW | OFF | | |
| SDRAM_ADDR<7> | IOB | OUTPUT | LVTTL | | 12 | SLOW | OFF | | |
| SDRAM_ADDR<8> | IOB | OUTPUT | LVTTL | | 12 | SLOW | OFF | | |
| SDRAM_ADDR<9> | IOB | OUTPUT | LVTTL | | 12 | SLOW | OFF | | |
| SDRAM_ADDR<10> | IOB | OUTPUT | LVTTL | | 12 | SLOW | OFF | | |
| SDRAM_ADDR<11> | IOB | OUTPUT | LVTTL | | 12 | SLOW | OFF | | |
| SDRAM_ADDR<12> | IOB | OUTPUT | LVTTL | | 12 | SLOW | OFF | | |
| SDRAM_BA<0> | IOB | OUTPUT | LVTTL | | 12 | SLOW | OFF | | |
| SDRAM_BA<1> | IOB | OUTPUT | LVTTL | | 12 | SLOW | OFF | | |
| SDRAM_CAS | IOB | OUTPUT | LVTTL | | 12 | SLOW | OFF | | |
| SDRAM_CKE | IOB | OUTPUT | LVTTL | | 12 | SLOW | OFF | | |
| SDRAM_CLK | IOB | OUTPUT | LVTTL | | 12 | SLOW | ODDR | | |
| SDRAM_CS | IOB | OUTPUT | LVTTL | | 12 | SLOW | | | |
| SDRAM_DATA<0> | IOB | INPUT | LVTTL | | | | IFF | | DEFAULT |
| SDRAM_DATA<1> | IOB | INPUT | LVTTL | | | | IFF | | DEFAULT |
| SDRAM_DATA<2> | IOB | INPUT | LVTTL | | | | IFF | | DEFAULT |
| SDRAM_DATA<3> | IOB | INPUT | LVTTL | | | | IFF | | DEFAULT |
| SDRAM_DATA<4> | IOB | INPUT | LVTTL | | | | IFF | | DEFAULT |
| SDRAM_DATA<5> | IOB | INPUT | LVTTL | | | | IFF | | DEFAULT |
| SDRAM_DATA<6> | IOB | INPUT | LVTTL | | | | IFF | | DEFAULT |
| SDRAM_DATA<7> | IOB | INPUT | LVTTL | | | | IFF | | DEFAULT |
| SDRAM_DATA<8> | IOB | INPUT | LVTTL | | | | IFF | | DEFAULT |
| SDRAM_DATA<9> | IOB | INPUT | LVTTL | | | | IFF | | DEFAULT |
| SDRAM_DATA<10> | IOB | INPUT | LVTTL | | | | IFF | | DEFAULT |
| SDRAM_DATA<11> | IOB | INPUT | LVTTL | | | | IFF | | DEFAULT |
| SDRAM_DATA<12> | IOB | INPUT | LVTTL | | | | IFF | | DEFAULT |
| SDRAM_DATA<13> | IOB | INPUT | LVTTL | | | | IFF | | DEFAULT |
| SDRAM_DATA<14> | IOB | INPUT | LVTTL | | | | IFF | | DEFAULT |
| SDRAM_DATA<15> | IOB | INPUT | LVTTL | | | | IFF | | DEFAULT |
| SDRAM_DQM<0> | IOB | OUTPUT | LVTTL | | 12 | SLOW | OFF | | |
| SDRAM_DQM<1> | IOB | OUTPUT | LVTTL | | 12 | SLOW | OFF | | |
| SDRAM_RAS | IOB | OUTPUT | LVTTL | | 12 | SLOW | OFF | | |
| SDRAM_WE | IOB | OUTPUT | LVTTL | | 12 | SLOW | OFF | | |
| START_I | IOB | INPUT | LVTTL | | | | | PULLUP | |
| UART0_RXD_I | IOB | INPUT | LVTTL | | | | | | |
| UART0_TXD_O | IOB | OUTPUT | LVTTL | | 12 | SLOW | | | |
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
Section 7 - RPMs
----------------
Section 8 - Guide Report
------------------------
Guide not run on this design.
Section 9 - Area Group and Partition Summary
--------------------------------------------
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Area Group Information
----------------------
No area groups were found in this design.
----------------------
Section 10 - Timing Report
--------------------------
A logic-level (pre-route) timing report can be generated by using Xilinx static
timing analysis tools, Timing Analyzer (GUI) or TRCE (command line), with the
mapped NCD and PCF files. Please note that this timing report will be generated
using estimated delay information. For accurate numbers, please generate a
timing report with the post Place and Route NCD file.
For more information about the Timing Analyzer, consult the Xilinx Timing
Analyzer Reference Manual; for more information about TRCE, consult the Xilinx
Command Line Tools User Guide "TRACE" chapter.
Section 11 - Configuration String Details
-----------------------------------------
Use the "-detail" map option to print out Configuration Strings
Section 12 - Control Set Information
------------------------------------
Use the "-detail" map option to print out Control Set Information.
Section 13 - Utilization by Hierarchy
-------------------------------------
Use the "-detail" map option to print out the Utilization by Hierarchy section.