This repository has been archived by the owner on Oct 15, 2018. It is now read-only.

FiveStagePipeline

A MIPS32 5-Stage Pipeline CPU design from ground up.

Prefix

CS_ : Control Signal
PR_ : Pipeline Register
OP_ : MIPS Instruction
ALU_ : ALU Operation
FUNC_ : R-type Instruction func field
INST_TYPE_ : Just for display on LCD

planning to support those simple MIPS32 instructions