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simd_x86.h
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simd_x86.h
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/* SPDX-License-Identifier: GPL-3.0-or-later WITH GCC-exception-3.1 */
/* Copyright © 2023-2024 GSI Helmholtzzentrum fuer Schwerionenforschung GmbH
* Matthias Kretz <[email protected]>
*/
#ifndef PROTOTYPE_SIMD_X86_H_
#define PROTOTYPE_SIMD_X86_H_
#include "simd_converter.h"
#include "simd_builtin.h"
#include "x86_detail.h"
#include <x86intrin.h>
namespace std
{
template <int _Width>
struct _Avx512Abi
#if not __AVX512F__
{
struct _IsValidAbiTag
: false_type
{};
template <typename>
struct _IsValidSizeFor
: false_type
{};
template <typename>
using _IsValid = false_type;
static constexpr __detail::_SimdSizeType _S_size = 0;
static constexpr __detail::_SimdSizeType _S_full_size = 0;
static constexpr bool _S_is_partial = false;
template <typename _Tp>
struct __traits
: __detail::_InvalidTraits
{};
};
#else
: _VecAbi<_Width>
{
using _SimdSizeType = __detail::_SimdSizeType;
static constexpr _SimdSizeType _S_size = _Width;
static constexpr _SimdSizeType _S_full_size = std::__bit_ceil(_Width);
static constexpr bool _S_is_partial = _S_full_size > _S_size;
using _MaskInteger = typename __detail::__make_unsigned_int<
std::min(8, std::max(8, _S_full_size) / __CHAR_BIT__)>::type;
template <typename _Tp>
struct __traits
: __detail::_InvalidTraits
{};
template <typename _Tp>
requires (_VecAbi<_Width>::template _IsValid<_Tp>::value)
struct __traits<_Tp>
{
// conversions to _Avx512Abi should always be implicit
template <typename _FromAbi>
static constexpr bool _S_explicit_mask_conversion = false;
using _Impl = __detail::_ImplBuiltin<_Avx512Abi>;
using _SimdImpl = _Impl;
using _MaskImpl = _Impl;
static constexpr _SimdSizeType _S_size = _Width;
static constexpr _SimdSizeType _S_full_size = std::__bit_ceil(_Width);
static constexpr bool _S_is_partial = _S_full_size > _S_size;
using _SimdMember = _VecAbi<_Width>::template _SimdMember<_Tp>;
using _MaskMember = _MaskInteger;
static constexpr size_t _S_simd_align = alignof(_SimdMember);
static constexpr size_t _S_mask_align = alignof(_MaskMember);
template <typename _Arg>
static constexpr bool _S_is_simd_ctor_arg
= std::is_same_v<_Arg, _SimdMember>
or std::is_same_v<_Arg, __detail::__x86_intrin_t<_SimdMember>>;
template <typename _Arg>
static constexpr bool _S_is_mask_ctor_arg
= std::is_same_v<_Arg, _MaskMember>;
template <typename _To>
requires _S_is_simd_ctor_arg<_To>
_GLIBCXX_SIMD_INTRINSIC static constexpr _To
_S_simd_conversion(_SimdMember __x)
{ return __builtin_bit_cast(_To, __x); }
template <typename _From>
requires _S_is_simd_ctor_arg<_From>
_GLIBCXX_SIMD_INTRINSIC static constexpr _SimdMember
_S_simd_construction(_From __x)
{ return __builtin_bit_cast(_SimdMember, __x); }
template <typename _To>
requires _S_is_mask_ctor_arg<_To>
_GLIBCXX_SIMD_INTRINSIC static constexpr _To
_S_mask_conversion(_MaskMember __x)
{ return __x; }
template <typename _From>
requires _S_is_mask_ctor_arg<_From>
_GLIBCXX_SIMD_INTRINSIC static constexpr _MaskMember
_S_mask_construction(_From __x)
{ return __x; }
};
using _Impl = __detail::_ImplBuiltin<_Avx512Abi>;
using _SimdImpl = _Impl;
using _MaskImpl = _Impl;
template <__detail::__vectorizable _Up>
using _Rebind = std::conditional_t<
_Avx512Abi<_S_size>::template _IsValid<_Up>::value,
_Avx512Abi<_S_size>, __detail::__deduce_t<_Up, _S_size>>;
template <typename _Tp>
using _SimdMember = __traits<_Tp>::_SimdMember;
template <typename>
using _MaskMember = _MaskInteger;
static constexpr bool _S_mask_is_partial = _S_size < 8 or not std::__has_single_bit(_S_size);
// The template argument exists because _VecAbi::_S_implicit_mask needs it. And _ImplBuiltin
// below needs to work generically for _VecAbi and _Avx512Abi.
template <__detail::__vectorizable>
static constexpr _MaskInteger _S_implicit_mask
= _S_mask_is_partial ? _MaskInteger((1ULL << _S_size) - 1) : ~_MaskInteger();
_GLIBCXX_SIMD_INTRINSIC static constexpr _MaskInteger
_S_masked(_MaskInteger __x)
{
if constexpr (_S_mask_is_partial)
// _S_mask_is_partial implies _S_size < 64
return __x & _MaskInteger((1ULL << _S_size) - 1);
else
return __x;
}
using _VecAbi<_Width>::_S_masked;
template <__detail::__vec_builtin _TV>
_GLIBCXX_SIMD_INTRINSIC static constexpr auto
__make_padding_nonzero(_TV __x)
{
using _Tp = __detail::__value_type_of<_TV>;
if constexpr (not _S_is_partial)
return __x;
else
return _Impl::_S_select(_S_implicit_mask<_Tp>, __x,
_Impl::_S_broadcast(_Tp(1)));
}
};
#endif
}
#if __x86_64__ or __i386__
namespace std::__detail
{
template <typename _Abi, auto _Flags>
struct _SimdMaskTraits<sizeof(float), _Abi, _Flags>
: _SimdTraits<conditional_t<_Flags._M_have_avx and not _Flags._M_have_avx2,
float, __mask_integer_from<sizeof(float)>>, _Abi, _Flags>
{};
template <typename _Abi, auto _Flags>
struct _SimdMaskTraits<sizeof(double), _Abi, _Flags>
: _SimdTraits<conditional_t<_Flags._M_have_avx and not _Flags._M_have_avx2,
double, __mask_integer_from<sizeof(double)>>, _Abi, _Flags>
{};
enum class _X86Round
{
_ToNearestInt = 0x00,
_ToNegInf = 0x01,
_ToPosInf = 0x02,
_ToZero = 0x03,
_CurDirection = 0x04,
_RaiseException = 0x00,
_NoException = 0x08,
_Nint = _ToNearestInt | _RaiseException,
_Floor = _ToNegInf | _RaiseException,
_Ceil = _ToPosInf | _RaiseException,
_Trunc = _ToZero | _RaiseException,
_Rint = _CurDirection | _RaiseException,
_NearbyInt = _CurDirection | _NoException,
};
template <typename _Abi, auto _Flags>
struct _ImplBuiltin : _ImplBuiltinBase<_Abi>
{
using _Base = _ImplBuiltinBase<_Abi>;
template <typename _Tp>
using _SimdMember = typename _Abi::template _SimdMember<_Tp>;
// _Tp can be a __vec_builtin or __arithmetic type
template <typename _Tp>
using _MaskMember = typename _Abi::template _MaskMember<__value_type_of<_Tp>>;
static constexpr _SimdSizeType _S_size = _Abi::_S_size;
static constexpr _SimdSizeType _S_full_size = _Abi::_S_full_size;
static constexpr bool _S_is_partial = _Abi::_S_is_partial;
static constexpr bool _S_use_bitmasks = is_same_v<_Abi, _Avx512Abi<_S_size>>;
using _MaskInteger = typename __detail::__make_unsigned_int<
std::min(8, std::max(8, _S_full_size) / __CHAR_BIT__)>::type;
template <__vec_builtin _TV>
_GLIBCXX_SIMD_INTRINSIC static constexpr _MaskInteger
_S_to_bitmask(_TV __k)
{ return _S_to_bits(__k)._M_to_bits(); }
template <integral _Tp>
_GLIBCXX_SIMD_INTRINSIC static constexpr _Tp
_S_to_bitmask(_Tp __k)
{ return __k; }
template <typename _Tp>
_GLIBCXX_SIMD_INTRINSIC static constexpr _MaskMember<_Tp>
_S_load(const bool* __mem)
{
if constexpr (_S_use_bitmasks)
{
if (__builtin_is_constant_evaluated())
{
return _GLIBCXX_SIMD_INT_PACK(_S_size, _Is, {
return ((_MaskMember<_Tp>(__mem[_Is]) << _Is) | ...);
});
}
else
{
using _BV = __vec_builtin_type_bytes<__make_signed_int_t<bool>,
_S_full_size * sizeof(bool)>;
_BV __bools = {};
__builtin_memcpy(&__bools, __mem, _S_size * sizeof(bool));
return _S_not_equal_to(__bools, _BV());
}
}
else
return _Base::template _S_load<_Tp>(__mem);
}
using _Base::_S_load;
template <__vec_builtin _TV, typename _Up>
static inline _TV
_S_masked_load(_TV __merge, _MaskMember<_TV> __k, const _Up* __mem)
{
using _Tp = __value_type_of<_TV>;
constexpr bool __no_conversion = is_same_v<_Tp, _Up>;
constexpr bool __bitwise_conversion = sizeof(_Tp) == sizeof(_Up)
and is_integral_v<_Tp> == is_integral_v<_Up>;
if constexpr (__no_conversion or __bitwise_conversion)
{
[[maybe_unused]] const auto __intrin = __to_x86_intrin(__merge);
const auto __kk = _S_to_bitmask(__k);
#define _GLIBCXX_SIMD_MASK_LOAD(type, type2, bits) \
__merge = reinterpret_cast<_TV>(__builtin_ia32_loaddqu##type##i##bits##_mask( \
reinterpret_cast<const type2*>(__mem), \
reinterpret_cast<__vec_builtin_type<type2, bits / 8>>(__merge), __kk))
#define _GLIBCXX_SIMD_MASK_LOAD_FLT(type, type2, bits) \
__merge = reinterpret_cast<_TV>(__builtin_ia32_loadup##type##i##bits##_mask( \
reinterpret_cast<const type2*>(__mem), \
reinterpret_cast<__vec_builtin_type<type2, bits / 8>>(__merge), __kk))
if constexpr (_Flags._M_have_avx512bw and _Flags._M_have_avx512vl
and sizeof(_Tp) == 1)
{
if constexpr (sizeof(__intrin) == 16)
_GLIBCXX_SIMD_MASK_LOAD(q, char, 128);
else if constexpr (sizeof(__merge) == 32)
_GLIBCXX_SIMD_MASK_LOAD(q, char, 256);
else if constexpr (sizeof(__merge) == 64)
_GLIBCXX_SIMD_MASK_LOAD(q, char, 512);
else
__assert_unreachable<_Tp>();
}
else if constexpr (_Flags._M_have_avx512bw and _Flags._M_have_avx512vl
and sizeof(_Tp) == 2)
{
if constexpr (sizeof(__intrin) == 16)
_GLIBCXX_SIMD_MASK_LOAD(h, short, 128);
else if constexpr (sizeof(__intrin) == 32)
_GLIBCXX_SIMD_MASK_LOAD(h, short, 256);
else if constexpr (sizeof(__intrin) == 64)
_GLIBCXX_SIMD_MASK_LOAD(h, short, 512);
else
__assert_unreachable<_Tp>();
}
else if constexpr (_Flags._M_have_avx512vl and sizeof(_Tp) == 4
and is_integral_v<_Up>)
{
if constexpr (sizeof(__intrin) == 16)
_GLIBCXX_SIMD_MASK_LOAD(s, int, 128);
else if constexpr (sizeof(__intrin) == 32)
_GLIBCXX_SIMD_MASK_LOAD(s, int, 256);
else if constexpr (sizeof(__intrin) == 64)
_GLIBCXX_SIMD_MASK_LOAD(s, int, 512);
else
__assert_unreachable<_Tp>();
}
else if constexpr (_Flags._M_have_avx512vl and sizeof(_Tp) == 4
and is_floating_point_v<_Up>)
{
if constexpr (sizeof(__intrin) == 16)
_GLIBCXX_SIMD_MASK_LOAD_FLT(s, float, 128);
else if constexpr (sizeof(__intrin) == 32)
_GLIBCXX_SIMD_MASK_LOAD_FLT(s, float, 256);
else if constexpr (sizeof(__intrin) == 64)
_GLIBCXX_SIMD_MASK_LOAD_FLT(s, float, 512);
else
__assert_unreachable<_Tp>();
}
else if constexpr (_Flags._M_have_avx2 and sizeof(_Tp) == 4 and is_integral_v<_Up>)
{
static_assert(_S_use_bitmasks == false);
static_assert(sizeof(__intrin) == 16 or sizeof(__intrin) == 32);
__merge = __vec_or(__vec_andnot(reinterpret_cast<_TV>(__k), __merge),
reinterpret_cast<_TV>(__maskload_epi32(__mem, __k)));
}
else if constexpr (_Flags._M_have_avx and sizeof(_Tp) == 4)
{
static_assert(sizeof(__intrin) == 16 or sizeof(__intrin) == 32);
__merge = __vec_or(__vec_andnot(reinterpret_cast<_TV>(__k), __merge),
reinterpret_cast<_TV>(__maskload_ps(__mem, __k)));
}
else if constexpr (_Flags._M_have_avx512vl and sizeof(_Tp) == 8
and is_integral_v<_Up>)
{
if constexpr (sizeof(__intrin) == 16)
_GLIBCXX_SIMD_MASK_LOAD(d, long long, 128);
else if constexpr (sizeof(__intrin) == 32)
_GLIBCXX_SIMD_MASK_LOAD(d, long long, 256);
else if constexpr (sizeof(__intrin) == 64)
_GLIBCXX_SIMD_MASK_LOAD(d, long long, 512);
else
__assert_unreachable<_Tp>();
}
else if constexpr (_Flags._M_have_avx512vl and sizeof(_Tp) == 8
and is_floating_point_v<_Up>)
{
if constexpr (sizeof(__intrin) == 16)
_GLIBCXX_SIMD_MASK_LOAD_FLT(d, double, 128);
else if constexpr (sizeof(__intrin) == 32)
_GLIBCXX_SIMD_MASK_LOAD_FLT(d, double, 256);
else if constexpr (sizeof(__intrin) == 64)
_GLIBCXX_SIMD_MASK_LOAD_FLT(d, double, 512);
else
__assert_unreachable<_Tp>();
}
else if constexpr (_Flags._M_have_avx2 and sizeof(_Tp) == 8 and is_integral_v<_Up>)
{
static_assert(sizeof(__intrin) == 16 or sizeof(__intrin) == 32);
__merge = __vec_or(__vec_andnot(reinterpret_cast<_TV>(__k), __merge),
reinterpret_cast<_TV>(__maskload_epi64( __mem, __k)));
}
else if constexpr (_Flags._M_have_avx and sizeof(_Tp) == 8)
{
static_assert(sizeof(__intrin) == 16 or sizeof(__intrin) == 32);
__merge = __vec_or(__vec_andnot(reinterpret_cast<_TV>(__k), __merge),
reinterpret_cast<_TV>(__maskload_pd(__mem, __k)));
}
else
_S_bit_iteration(_S_to_bits(__k),
[&] [[__gnu__::__always_inline__]] (auto __i) {
__merge[__i] = static_cast<_Tp>(__mem[__i]);
});
}
/* Very uncertain, that the following improves anything. Needs benchmarking
* before it's activated.
else if constexpr (sizeof(_Up) <= 8 and // no long double
!__converts_via_decomposition_v<
_Up, _Tp,
sizeof(__merge)> // conversion via decomposition
// is better handled via the
// bit_iteration fallback below
)
{
// TODO: copy pattern from _S_masked_store, which doesn't resort to
// fixed_size
using _Ap = simd_abi::deduce_t<_Up, _Np>;
using _ATraits = _SimdTraits<_Up, _Ap>;
using _AImpl = typename _ATraits::_SimdImpl;
typename _ATraits::_SimdMember __uncvted{};
typename _ATraits::_MaskMember __kk = _Ap::_Impl::template _S_convert<_Up>(__k);
__uncvted = _AImpl::_S_masked_load(__uncvted, __kk, __mem);
_SimdConverter<_Up, _Ap, _Tp, _Abi> __converter;
_Base::_S_masked_assign(__k, __merge, __converter(__uncvted));
}
*/
else
__merge = _Base::_S_masked_load(__merge, __k, __mem);
return __merge;
}
// Returns: __k ? __a : __b
// Requires: _TV to be a __vec_builtin_type matching valuetype for the bitmask __k
template <integral _Kp, __vec_builtin _TV>
_GLIBCXX_SIMD_INTRINSIC static constexpr _TV
_S_select_bitmask(const _Kp __k, const _TV __a, const _TV __b)
{
using _Tp = __value_type_of<_TV>;
static_assert(sizeof(_Tp) <= 8);
if (__builtin_is_constant_evaluated()
or (__builtin_constant_p(__k) and __builtin_constant_p(__a)
and __builtin_constant_p(__b)))
{
const _TV __r = _GLIBCXX_SIMD_INT_PACK(_S_size, _Is, {
return _TV{(((__k >> _Is) & 1) == 1 ? __vec_get(__a, _Is)
: __vec_get(__b, _Is))...};
});
if (__builtin_is_constant_evaluated() or __builtin_constant_p(__r))
return __r;
}
if (__builtin_constant_p(__k) and (__k & _Abi::template _S_implicit_mask<_Tp>) == 0)
return __b;
if (__builtin_constant_p(__k) and (__k & _Abi::template _S_implicit_mask<_Tp>)
== _Abi::template _S_implicit_mask<_Tp>)
return __a;
#ifdef __clang__
return _S_convert_mask<__mask_vec_from<_TV>>(_BitMask<_S_size>(__k)) ? __a : __b;
#else
using _IntT = __x86_builtin_int_t<_Tp>;
using _IntV = __vec_builtin_type_bytes<_IntT, sizeof(__b)>;
[[maybe_unused]] const auto __aa = reinterpret_cast<_IntV>(__b);
[[maybe_unused]] const auto __bb = reinterpret_cast<_IntV>(__a);
if constexpr (sizeof(_TV) == 64)
{
if constexpr (sizeof(_Tp) == 1)
return reinterpret_cast<_TV>(__builtin_ia32_blendmb_512_mask(__aa, __bb, __k));
else if constexpr (sizeof(_Tp) == 2)
return reinterpret_cast<_TV>(__builtin_ia32_blendmw_512_mask(__aa, __bb, __k));
else if constexpr (sizeof(_Tp) == 4 and is_floating_point_v<_Tp>)
return __builtin_ia32_blendmps_512_mask(__b, __a, __k);
else if constexpr (sizeof(_Tp) == 4)
return reinterpret_cast<_TV>(__builtin_ia32_blendmd_512_mask(__aa, __bb, __k));
else if constexpr (sizeof(_Tp) == 8 and is_floating_point_v<_Tp>)
return __builtin_ia32_blendmpd_512_mask(__b, __a, __k);
else if constexpr (sizeof(_Tp) == 8)
return reinterpret_cast<_TV>(__builtin_ia32_blendmq_512_mask(__aa, __bb, __k));
else
__assert_unreachable<_TV>();
}
else if constexpr (sizeof(_TV) == 32)
{
if constexpr (sizeof(_Tp) == 1)
return reinterpret_cast<_TV>(__builtin_ia32_blendmb_256_mask(__aa, __bb, __k));
else if constexpr (sizeof(_Tp) == 2)
return reinterpret_cast<_TV>(__builtin_ia32_blendmw_256_mask(__aa, __bb, __k));
else if constexpr (sizeof(_Tp) == 4 and is_floating_point_v<_Tp>)
return __builtin_ia32_blendmps_256_mask(__b, __a, __k);
else if constexpr (sizeof(_Tp) == 4)
return reinterpret_cast<_TV>(__builtin_ia32_blendmd_256_mask(__aa, __bb, __k));
else if constexpr (sizeof(_Tp) == 8 and is_floating_point_v<_Tp>)
return __builtin_ia32_blendmpd_256_mask(__b, __a, __k);
else if constexpr (sizeof(_Tp) == 8)
return reinterpret_cast<_TV>(__builtin_ia32_blendmq_256_mask(__aa, __bb, __k));
else
__assert_unreachable<_TV>();
}
else if constexpr (sizeof(_TV) == 16)
{
if constexpr (sizeof(_Tp) == 1)
return reinterpret_cast<_TV>(__builtin_ia32_blendmb_128_mask(__aa, __bb, __k));
else if constexpr (sizeof(_Tp) == 2)
return reinterpret_cast<_TV>(__builtin_ia32_blendmw_128_mask(__aa, __bb, __k));
else if constexpr (sizeof(_Tp) == 4 and is_floating_point_v<_Tp>)
return __builtin_ia32_blendmps_128_mask(__b, __a, __k);
else if constexpr (sizeof(_Tp) == 4)
return reinterpret_cast<_TV>(__builtin_ia32_blendmd_128_mask(__aa, __bb, __k));
else if constexpr (sizeof(_Tp) == 8 and is_floating_point_v<_Tp>)
return __builtin_ia32_blendmpd_128_mask(__b, __a, __k);
else if constexpr (sizeof(_Tp) == 8)
return reinterpret_cast<_TV>(__builtin_ia32_blendmq_128_mask(__aa, __bb, __k));
else
__assert_unreachable<_TV>();
}
else if constexpr (sizeof(_TV) < 16)
return __vec_bitcast_trunc<_TV>(_S_select_bitmask(__k, __vec_zero_pad_to_16(__a),
__vec_zero_pad_to_16(__b)));
else
__assert_unreachable<_TV>();
#endif
}
template <integral _Kp, __vec_builtin _TV>
_GLIBCXX_SIMD_INTRINSIC static constexpr _TV
_S_select(const _Kp __k, const _TV __a, const _TV __b)
{ return _S_select_bitmask(__k, __a, __b); }
template <__vec_builtin _TV>
_GLIBCXX_SIMD_INTRINSIC static _TV
_S_select_on_msb(const _MaskMember<_TV> __k, const _TV __a, const _TV __b)
{
using _Tp = __value_type_of<_TV>;
static_assert(not _Flags._M_have_avx512f, "really? If yes, you need to implement it.");
static_assert(sizeof(_TV) <= 32);
static_assert(is_signed_v<__value_type_of<_MaskMember<_TV>>>);
const auto __ia = reinterpret_cast<_MaskMember<_TV>>(__a);
const auto __ib = reinterpret_cast<_MaskMember<_TV>>(__b);
if (_Base::_S_is_constprop_all_of(__k))
return __a;
else if (_Base::_S_is_constprop_none_of(__k))
return __b;
else if (__builtin_constant_p(__ia) and _GLIBCXX_SIMD_INT_PACK(_S_size, _Is, {
return ((__ia[_Is] == 0) and ...);
}))
return __vec_andnot(reinterpret_cast<_TV>(__k), __b);
else if (__builtin_constant_p(__ib) and _GLIBCXX_SIMD_INT_PACK(_S_size, _Is, {
return ((__ib[_Is] == 0) and ...);
}))
return __vec_and(reinterpret_cast<_TV>(__k), __a);
else if constexpr (_Flags._M_have_sse4_1) // for vblend
{
using _IV = __vec_builtin_type_bytes<char, sizeof(_TV)>;
// duplicate msb to high bit of low byte for sizeof(_Tp) == 2 (or rather to all bits)
const _IV __ki = reinterpret_cast<_IV>(sizeof(_Tp) == 2 ? __k < 0 : __k);
const _IV __ai = reinterpret_cast<_IV>(__a);
const _IV __bi = reinterpret_cast<_IV>(__b);
if constexpr (sizeof(_Tp) == 4 and sizeof(_TV) == 32 and _Flags._M_have_avx)
return __builtin_ia32_blendvps256(__b, __a, __k);
else if constexpr (sizeof(_Tp) == 8 and sizeof(_TV) == 32 and _Flags._M_have_avx)
return __builtin_ia32_blendvpd256(__b, __a, __k);
else if constexpr (sizeof(_Tp) == 4 and sizeof(_TV) == 16)
return __builtin_ia32_blendvps(__b, __a, __k);
else if constexpr (sizeof(_Tp) == 8 and sizeof(_TV) == 16)
return __builtin_ia32_blendvpd(__b, __a, __k);
else if constexpr (sizeof(_TV) == 32 and _Flags._M_have_avx2)
return reinterpret_cast<_TV>(__builtin_ia32_pblendvb256(__bi, __ai, __ki));
else if constexpr (sizeof(_TV) == 16)
return reinterpret_cast<_TV>(__builtin_ia32_pblendvb128(__bi, __ai, __ki));
}
else
return __k < 0 ? __a : __b;
}
/**
* Pre-condition: \p __k is a mask (all bits either 0 or 1)
*/
template <__vec_builtin _TV>
requires (not integral<_MaskMember<_TV>>)
_GLIBCXX_SIMD_INTRINSIC static _TV
_S_select(const _MaskMember<_TV> __k, const _TV __a, const _TV __b)
{
const auto __ia = reinterpret_cast<_MaskMember<_TV>>(__a);
const auto __ib = reinterpret_cast<_MaskMember<_TV>>(__b);
using _Tp = __value_type_of<_TV>;
if (_Base::_S_is_constprop_all_of(__k))
return __a;
else if (_Base::_S_is_constprop_none_of(__k))
return __b;
else if (__builtin_constant_p(__ia) and _GLIBCXX_SIMD_INT_PACK(_S_size, _Is, {
return ((__ia[_Is] == 0) and ...);
}))
return __vec_andnot(reinterpret_cast<_TV>(__k), __b);
else if (__builtin_constant_p(__ib) and _GLIBCXX_SIMD_INT_PACK(_S_size, _Is, {
return ((__ib[_Is] == 0) and ...);
}))
return __vec_and(reinterpret_cast<_TV>(__k), __a);
else if constexpr (_Flags._M_have_sse4_1)
{
static_assert(sizeof(_TV) == 16 or sizeof(_TV) == 32);
if constexpr (is_integral_v<_Tp>)
{
using _IV = __vec_builtin_type_bytes<char, sizeof(_TV)>;
const _IV __ki = reinterpret_cast<_IV>(__k);
const _IV __ai = reinterpret_cast<_IV>(__a);
const _IV __bi = reinterpret_cast<_IV>(__b);
if (sizeof(_Tp) != 1 and _GLIBCXX_SIMD_INT_PACK(_S_size, _Is, {
return ((__k[_Is] != -1 and __k[_Is] != 0) or ...);
}))
__invoke_ub("Undefined behavior: invalid mask value(s)");
else if constexpr (sizeof(_TV) == 32 and _Flags._M_have_avx2)
return reinterpret_cast<_TV>(__builtin_ia32_pblendvb256(__bi, __ai, __ki));
else if constexpr (sizeof(_TV) == 16)
return reinterpret_cast<_TV>(__builtin_ia32_pblendvb128(__bi, __ai, __ki));
else
__assert_unreachable<_TV>();
}
else if constexpr (sizeof(_Tp) == 4 and sizeof(_TV) == 32)
return __builtin_ia32_blendvps256(__b, __a, __k);
else if constexpr (sizeof(_Tp) == 4 and sizeof(_TV) == 16)
return __builtin_ia32_blendvps(__b, __a, __k);
else if constexpr (sizeof(_Tp) == 8 and sizeof(_TV) == 32)
return __builtin_ia32_blendvpd256(__b, __a, __k);
else if constexpr (sizeof(_Tp) == 8 and sizeof(_TV) == 16)
return __builtin_ia32_blendvpd(__b, __a, __k);
else
__assert_unreachable<_TV>();
}
else if (_GLIBCXX_SIMD_INT_PACK(_S_size, _Is, {
return ((__k[_Is] != -1 and __k[_Is] != 0) or ...);
}))
__invoke_ub("Undefined behavior: invalid mask value(s)");
else
return __k ? __a : __b;
}
template <__vec_builtin _TV>
_GLIBCXX_SIMD_INTRINSIC static constexpr void
_S_masked_assign(_MaskMember<_TV> __k, _TV& __lhs, __type_identity_t<_TV> __rhs)
{
if constexpr (_S_use_bitmasks)
__lhs = _S_select(__k, __rhs, __lhs);
else
_Base::_S_masked_assign(__k, __lhs, __rhs);
}
template <__vec_builtin _TV>
_GLIBCXX_SIMD_INTRINSIC static constexpr void
_S_masked_assign(_MaskMember<_TV> __k, _TV& __lhs,
__type_identity_t<__value_type_of<_TV>> __rhs)
{
using _Tp = __value_type_of<_TV>;
if constexpr (_S_use_bitmasks)
__lhs = _S_select_bitmask(__k, __vec_broadcast<_S_size>(__rhs), __lhs);
else if (_Base::_S_is_constprop_none_of(__k))
return;
else if (_Base::_S_is_constprop_all_of(__k))
__lhs = __vec_broadcast<_S_size>(__rhs);
else if constexpr (sizeof(_Tp) == 1 and is_integral_v<_Tp>
and sizeof(_TV) >= 8 and sizeof(_TV) <= 32)
{
// x86 has no byte-sized SIMD shift, so use `psignb` when available, otherwise use a
// single `and`, instead of calling the _Base impl which shifts.
if (_Base::_S_is_constprop_all_equal(__lhs, 0))
{
if constexpr ((_Flags._M_have_ssse3 and sizeof(_TV) <= 16)
or (_Flags._M_have_avx2 and sizeof(_TV) == 32))
{
if (__builtin_constant_p(__rhs) and __rhs == 1)
{
// like simd_mask::operator+ / mask conversion to _SimdType
const auto __ki = __vec_bitcast<__x86_builtin_int_t<_Tp>>(__k);
if constexpr (sizeof(_TV) == 32)
__lhs = reinterpret_cast<_TV>(__builtin_ia32_psignb256(__ki, __ki));
else
{
auto __k16 = __vec_zero_pad_to_16(__ki);
__lhs = __vec_bitcast_trunc<_TV>(
__builtin_ia32_psignb128(__k16, __k16));
}
}
else
__lhs = __vec_and(reinterpret_cast<_TV>(__k),
__vec_broadcast<_S_size>(__rhs));
}
else
__lhs = __vec_and(reinterpret_cast<_TV>(__k),
__vec_broadcast<_S_size>(__rhs));
}
else
_Base::_S_masked_assign(__k, __lhs, __rhs);
}
else
_Base::_S_masked_assign(__k, __lhs, __rhs);
}
template <unsigned_integral _Kp, size_t _Np, bool _Sanitized>
_GLIBCXX_SIMD_INTRINSIC static constexpr _Kp
_S_convert_mask(_BitMask<_Np, _Sanitized> __x)
{
static_assert(is_same_v<_Kp, typename _Abi::_MaskInteger>);
return __x._M_to_unsanitized_bits();
}
template <__vec_builtin _TV, size_t _Np, bool _Sanitized>
_GLIBCXX_SIMD_INTRINSIC static constexpr _TV
_S_convert_mask(_BitMask<_Np, _Sanitized> __x)
{
using _Tp = __value_type_of<_TV>;
static_assert(is_same_v<_Tp, __mask_integer_from<sizeof(_Tp)>>);
const _MaskInteger __k = __x._M_to_unsanitized_bits();
constexpr bool __bwvl = _Flags._M_have_avx512bw and _Flags._M_have_avx512vl;
constexpr bool __dqvl = _Flags._M_have_avx512dq and _Flags._M_have_avx512vl;
if (__builtin_is_constant_evaluated() or __builtin_constant_p(__k))
{
const _TV __r = _Base::template _S_convert_mask<_TV>(__x);
if (__builtin_is_constant_evaluated() or __builtin_constant_p(__r))
return __r;
}
if constexpr (__vec_builtin_sizeof<_TV, 1, 64> and _Flags._M_have_avx512bw)
return __builtin_ia32_cvtmask2b512(__k);
else if constexpr (__vec_builtin_sizeof<_TV, 1, 32> and __bwvl)
return __builtin_ia32_cvtmask2b256(__k);
else if constexpr (__vec_builtin_sizeof<_TV, 1> and __bwvl)
return __vec_bitcast_trunc<_TV>(__builtin_ia32_cvtmask2b128(__k));
else if constexpr (__vec_builtin_sizeof<_TV, 2, 64> and _Flags._M_have_avx512bw)
return __builtin_ia32_cvtmask2w512(__k);
else if constexpr (__vec_builtin_sizeof<_TV, 2, 32> and __bwvl)
return __builtin_ia32_cvtmask2w256(__k);
else if constexpr (__vec_builtin_sizeof<_TV, 2> and __bwvl)
return __vec_bitcast_trunc<_TV>(__builtin_ia32_cvtmask2w128(__k));
else if constexpr (__vec_builtin_sizeof<_TV, 4, 64> and _Flags._M_have_avx512dq)
return __builtin_ia32_cvtmask2d512(__k);
else if constexpr (__vec_builtin_sizeof<_TV, 4, 32> and __dqvl)
return __builtin_ia32_cvtmask2d256(__k);
else if constexpr (__vec_builtin_sizeof<_TV, 4> and __dqvl)
return __vec_bitcast_trunc<_TV>(__builtin_ia32_cvtmask2d128(__k));
else if constexpr (__vec_builtin_sizeof<_TV, 8, 64> and _Flags._M_have_avx512dq)
return __builtin_ia32_cvtmask2q512(__k);
else if constexpr (__vec_builtin_sizeof<_TV, 8, 32> and __dqvl)
return __builtin_ia32_cvtmask2q256(__k);
else if constexpr (__vec_builtin_sizeof<_TV, 8> and __dqvl)
return __vec_bitcast_trunc<_TV>(__builtin_ia32_cvtmask2q128(__k));
else
return _Base::template _S_convert_mask<_TV>(__x);
}
using _Base::_S_convert_mask;
#ifndef __clang__
template <__vec_builtin _TV>
_GLIBCXX_SIMD_INTRINSIC static constexpr _TV
_S_multiplies(_TV __x, _TV __y)
{
using _Tp = __value_type_of<_TV>;
if (__builtin_is_constant_evaluated() or __builtin_constant_p(__x)
or __builtin_constant_p(__y))
return __x * __y;
else if constexpr (sizeof(_Tp) == 1)
{
if constexpr (sizeof(_TV) == 2)
{
const auto __xs = reinterpret_cast<short>(__x);
const auto __ys = reinterpret_cast<short>(__y);
return reinterpret_cast<__vec_builtin_type<_Tp, 2>>(
short(((__xs * __ys) & 0xff) | ((__xs >> 8) * (__ys & 0xff00))));
}
else if constexpr (sizeof(_TV) == 4 and _S_size == 3)
{
const auto __xi = reinterpret_cast<int>(__x);
const auto __yi = reinterpret_cast<int>(__y);
return reinterpret_cast<__vec_builtin_type<_Tp, 3>>(
((__xi * __yi) & 0xff)
| (((__xi >> 8) * (__yi & 0xff00)) & 0xff00)
| ((__xi >> 16) * (__yi & 0xff0000)));
}
else if constexpr (sizeof(_TV) == 4)
{
const auto __xi = reinterpret_cast<int>(__x);
const auto __yi = reinterpret_cast<int>(__y);
return reinterpret_cast<__vec_builtin_type<_Tp, 4>>(
((__xi * __yi) & 0xff)
| (((__xi >> 8) * (__yi & 0xff00)) & 0xff00)
| (((__xi >> 16) * (__yi & 0xff0000)) & 0xff0000)
| ((__xi >> 24) * (__yi & 0xff000000u)));
}
else if constexpr (sizeof(_TV) == 8 and _Flags._M_have_sse4_1 and is_signed_v<_Tp>)
{
auto __x16 = __builtin_ia32_pmovsxbw128(reinterpret_cast<__v16char>(
__vec_zero_pad_to_16(__x)));
auto __y16 = __builtin_ia32_pmovsxbw128(reinterpret_cast<__v16char>(
__vec_zero_pad_to_16(__y)));
static_assert(same_as<decltype(__x16), __vec_builtin_type<short, 8>>);
return __vec_convert<_TV>(__x16 * __y16);
}
else if constexpr (sizeof(_TV) == 8 and _Flags._M_have_sse4_1 and is_unsigned_v<_Tp>)
{
auto __x16 = __builtin_ia32_pmovzxbw128(reinterpret_cast<__v16char>(
__vec_zero_pad_to_16(__x)));
auto __y16 = __builtin_ia32_pmovzxbw128(reinterpret_cast<__v16char>(
__vec_zero_pad_to_16(__y)));
static_assert(same_as<decltype(__x16), __vec_builtin_type<short, 8>>);
return __vec_convert<_TV>(__x16 * __y16);
}
else
{
// codegen of `x*y` is suboptimal (as of GCC 13.1)
constexpr int _Np = _S_full_size / 2;
using _ShortW = __vec_builtin_type<short, _Np>;
const _ShortW __even = __vec_bitcast<short, _Np>(__x)
* __vec_bitcast<short, _Np>(__y);
const _ShortW __high_byte = _ShortW() - 256;
const _ShortW __odd
= (__vec_bitcast<short, _Np>(__x) >> 8)
* (__vec_bitcast<short, _Np>(__y) & __high_byte);
if constexpr (_Flags._M_have_avx512bw and sizeof(_TV) > 2)
return _S_select_bitmask(0xaaaa'aaaa'aaaa'aaaaLL,
__vec_bitcast<_Tp>(__odd), __vec_bitcast<_Tp>(__even));
else if constexpr (_Flags._M_have_sse4_1 and sizeof(_TV) > 2)
return reinterpret_cast<_TV>(__high_byte ? __odd : __even);
else
return reinterpret_cast<_TV>(__vec_or(__vec_andnot(__high_byte, __even), __odd));
}
}
else
return _Base::_S_multiplies(__x, __y);
}
#endif
// integer division not optimized (PR90993)
#ifndef __clang__
template <__vec_builtin _TV>
_GLIBCXX_SIMD_INTRINSIC static _TV
_S_fp_div(_TV __x, _TV __y)
{
#if __RECIPROCAL_MATH__
// If -freciprocal-math is active, using the `/` operator is
// incorrect because it may be translated to an imprecise
// multiplication with reciprocal. We need to use inline
// assembly to force a real division.
using _Tp = __value_type_of<_TV>;
static_assert(is_floating_point_v<_Tp>);
_TV __r;
if constexpr (_Flags._M_have_avx) // -mno-sse2avx is irrelevant because once -mavx is given, GCC
{ // emits VEX encoded vdivp[sd]
if constexpr (sizeof(_Tp) == 8)
asm("vdivpd\t{%2, %1, %0|%0, %1, %2}" : "=x"(__r) : "x"(__x), "x"(__y));
else
asm("vdivps\t{%2, %1, %0|%0, %1, %2}" : "=x"(__r) : "x"(__x), "x"(__y));
}
else
{
__r = __x;
if constexpr (sizeof(_Tp) == 8)
asm("divpd\t{%1, %0|%0, %1}" : "=x"(__r) : "x"(__y));
else
asm("divps\t{%1, %0|%0, %1}" : "=x"(__r) : "x"(__y));
}
return __r;
#else
return __x / __y;
#endif
}
template <__vec_builtin _TV>
_GLIBCXX_SIMD_INTRINSIC static constexpr _TV
_S_divides(_TV __x, _TV __y)
{
using _Tp = __value_type_of<_TV>;
if (not __builtin_is_constant_evaluated() and not __builtin_constant_p(__y))
{
if constexpr (is_integral_v<_Tp> and sizeof(_Tp) <= 4)
{ // use divps - codegen of `x/y` is suboptimal (as of GCC 9.0.1)
// Note that using floating-point division is likely to raise the
// *Inexact* exception flag and thus appears like an invalid
// "as-if" transformation. However, C++ doesn't specify how the
// fpenv can be observed and points to C. C says that function
// calls are assumed to potentially raise fp exceptions, unless
// documented otherwise. Consequently, operator/, which is a
// function call, may raise fp exceptions.
//const struct _CsrGuard
//{
// const unsigned _M_data = _mm_getcsr();
// _CsrGuard()
// { _mm_setcsr(0x9f80); } // turn off FP exceptions and flush-to-zero
// ~_CsrGuard() { _mm_setcsr(_M_data); }
//} __csr;
using _Float = conditional_t<sizeof(_Tp) == 4, double, float>;
constexpr int __n_intermediate
= std::min(_S_full_size, (_Flags._M_have_avx512f
? 64 : _Flags._M_have_avx ? 32 : 16)
/ int(sizeof(_Float)));
using _FloatV = __vec_builtin_type<_Float, __n_intermediate>;
constexpr int __n_floatv = __div_roundup(_S_size, __n_intermediate);
const auto __xf = __vec_convert_all<_FloatV, __n_floatv>(__x);
const auto __yf = __vec_convert_all<_FloatV, __n_floatv>(
_Abi::__make_padding_nonzero(__y));
return _GLIBCXX_SIMD_INT_PACK(__n_floatv, _Is, {
return __vec_convert<_TV>(_S_fp_div(__xf[_Is], __yf[_Is])...);
});
}
/* 64-bit int division is potentially optimizable via double division if
* the value in __x is small enough and the conversion between
* int<->double is efficient enough:
else if constexpr (is_integral_v<_Tp> and is_unsigned_v<_Tp> and sizeof(_Tp) == 8)
{
if constexpr (_Flags._M_have_sse4_1 and sizeof(__x) == 16)
{
if (_mm_test_all_zeros(__x, __m128i{0xffe0'0000'0000'0000ull,
0xffe0'0000'0000'0000ull}))
{
__x | 0x __vector_convert<__m128d>(__x)
}
}
}
*/
}
return _Base::_S_divides(__x, __y);
}
template <__vec_builtin _TV>
_GLIBCXX_SIMD_INTRINSIC static constexpr _TV
_S_modulus(_TV __x, _TV __y)
{
if (__builtin_is_constant_evaluated() or __builtin_constant_p(__y)
or sizeof(__value_type_of<_TV>) >= 8)
return _Base::_S_modulus(__x, __y);
else
return _Base::_S_minus(__x, _S_multiplies(__y, _S_divides(__x, __y)));
}
#else
using _Base::_S_divides;
using _Base::_S_modulus;
#endif
template <unsigned_integral _Tp>
_GLIBCXX_SIMD_INTRINSIC static constexpr _Tp
_S_bit_and(_Tp __x, _Tp __y)
{ return __x & __y; }
using _Base::_S_bit_and;
template <unsigned_integral _Tp>
_GLIBCXX_SIMD_INTRINSIC static constexpr _Tp
_S_bit_or(_Tp __x, _Tp __y)
{ return __x | __y; }
using _Base::_S_bit_or;
template <unsigned_integral _Tp>
_GLIBCXX_SIMD_INTRINSIC static constexpr _Tp
_S_bit_xor(_Tp __x, _Tp __y)
{ return __x ^ __y; }
using _Base::_S_bit_xor;
// Notes on UB. C++2a [expr.shift] says:
// -1- [...] The operands shall be of integral or unscoped enumeration type
// and integral promotions are performed. The type of the result is that
// of the promoted left operand. The behavior is undefined if the right
// operand is negative, or greater than or equal to the width of the
// promoted left operand.
// -2- The value of E1 << E2 is the unique value congruent to E1×2^E2 modulo
// 2^N, where N is the width of the type of the result.
//
// C++17 [expr.shift] says:
// -2- The value of E1 << E2 is E1 left-shifted E2 bit positions; vacated
// bits are zero-filled. If E1 has an unsigned type, the value of the
// result is E1 × 2^E2 , reduced modulo one more than the maximum value
// representable in the result type. Otherwise, if E1 has a signed type
// and non-negative value, and E1 × 2^E2 is representable in the
// corresponding unsigned type of the result type, then that value,
// converted to the result type, is the resulting value; otherwise, the
// behavior is undefined.
//
// Consequences:
// With C++2a signed and unsigned types have the same UB
// characteristics:
// - left shift is not UB for 0 <= RHS < max(32, #bits(T))
//
// Even, with C++17 there's little room for optimizations because the standard requires all
// shifts to happen on promoted integrals (i.e. int). Thus, short and char shifts must assume
// shifts affect bits of neighboring values.
#if not defined _GLIBCXX_SIMD_NO_SHIFT_OPT and not defined __clang__
template <__vec_builtin _TV>
_GLIBCXX_SIMD_INTRINSIC static constexpr _TV
_S_bit_shift_left(_TV __x, int __y)
{
using _Tp = __value_type_of<_TV>;