From 0eb7170a5f31aa44b6590b706d0daf0c50a49a27 Mon Sep 17 00:00:00 2001
From: Fiscarelli
Date: Mon, 24 May 2021 10:13:01 -0400
Subject: [PATCH] CEP Release v3.3
---
README.md | 8 +-
RELEASE_NOTES.md | 10 +
cosim/Makefile | 2 +-
cosim/README.md | 53 +-
cosim/bareMetalTests/Makefile | 3 +
cosim/bareMetalTests/bootViaScratch/Makefile | 32 +
.../bootViaScratch/c_dispatch.cc | 126 ++
.../bootViaScratch/c_dispatch.h | 23 +
.../bareMetalTests/bootViaScratch/c_module.cc | 84 ++
.../bareMetalTests/bootViaScratch/c_module.h | 18 +
cosim/bareMetalTests/bootViaScratch/imp.h | 49 +
.../bootViaScratch/riscv_wrapper.cc | 80 ++
cosim/bareMetalTests/clintIntr/Makefile | 32 +
cosim/bareMetalTests/clintIntr/c_dispatch.cc | 126 ++
cosim/bareMetalTests/clintIntr/c_dispatch.h | 23 +
cosim/bareMetalTests/clintIntr/c_module.cc | 84 ++
cosim/bareMetalTests/clintIntr/c_module.h | 18 +
.../bareMetalTests/clintIntr/riscv_wrapper.cc | 175 +++
.../bareMetalTests/clintIntr/riscv_wrapper.h | 45 +
.../bareMetalTests/miscTests/riscv_wrapper.cc | 4 +-
cosim/bareMetalTests/plicPrioIntr/Makefile | 32 +
.../bareMetalTests/plicPrioIntr/c_dispatch.cc | 126 ++
.../bareMetalTests/plicPrioIntr/c_dispatch.h | 23 +
cosim/bareMetalTests/plicPrioIntr/c_module.cc | 84 ++
cosim/bareMetalTests/plicPrioIntr/c_module.h | 18 +
.../plicPrioIntr/riscv_wrapper.cc | 64 +
.../bareMetalTests/srotMemTest/c_dispatch.cc | 2 +-
.../srotMemTest/riscv_wrapper.cc | 9 +-
cosim/bfmTests/Makefile | 2 +
cosim/bfmTests/fragmentors/c_module.cc | 4 +-
cosim/bfmTests/multiThread/Makefile | 31 +
cosim/bfmTests/multiThread/c_dispatch.cc | 112 ++
cosim/bfmTests/multiThread/c_dispatch.h | 23 +
cosim/bfmTests/multiThread/c_module.cc | 94 ++
.../multiThread/c_module.h} | 11 +-
cosim/bfmTests/multiThread/imp.h | 49 +
cosim/bfmTests/plicPrioIntr/Makefile | 31 +
cosim/bfmTests/plicPrioIntr/c_dispatch.cc | 107 ++
cosim/bfmTests/plicPrioIntr/c_dispatch.h | 23 +
cosim/bfmTests/plicPrioIntr/c_module.cc | 86 ++
cosim/bfmTests/plicPrioIntr/c_module.h | 18 +
cosim/bfmTests/regTest/c_module.cc | 3 +-
cosim/bfmTests/srotErrorTest/c_module.cc | 2 +-
cosim/bin/mkDepend.pl | 14 +-
cosim/cadence.make | 8 +-
cosim/cadence_cov.ccf | 71 +-
cosim/cep_buildChips.make | 24 +-
cosim/common.make | 5 +
cosim/drivers/bootbare/Makefile | 49 -
cosim/drivers/bootbare/bootbare.c | 55 -
cosim/drivers/bootbare/head.S | 31 -
cosim/drivers/bootbare/include/bits.h | 36 -
cosim/drivers/bootbare/include/const.h | 18 -
.../drivers/bootbare/include/devices/clint.h | 14 -
cosim/drivers/bootbare/include/devices/gpio.h | 24 -
cosim/drivers/bootbare/include/devices/plic.h | 31 -
cosim/drivers/bootbare/include/devices/spi.h | 79 --
cosim/drivers/bootbare/include/devices/uart.h | 28 -
cosim/drivers/bootbare/include/platform.h | 99 --
.../bootbare/include/riscv_test_defaults.h | 81 --
cosim/drivers/bootbare/include/sections.h | 17 -
cosim/drivers/bootbare/include/smp.h | 142 ---
cosim/drivers/bootbare/linker/memory.lds | 14 -
cosim/drivers/bootbare/linker/sdboot.elf.lds | 79 --
cosim/drivers/cep_tests/CEP.h | 4 +-
cosim/drivers/cep_tests/cep_aes.cc | 2 +-
cosim/drivers/cep_tests/cep_apis.cc | 8 +-
cosim/drivers/cep_tests/cep_crypto.cc | 2 +-
cosim/drivers/cep_tests/cep_des3.cc | 2 +-
cosim/drivers/cep_tests/cep_dft.cc | 19 +-
cosim/drivers/cep_tests/cep_dft.h | 4 +-
cosim/drivers/cep_tests/cep_gps.cc | 2 +-
cosim/drivers/cep_tests/cep_srot.cc | 73 +-
cosim/drivers/cep_tests/cep_srot.h | 6 +-
cosim/drivers/diag/cepAccessTest.cc | 2 +-
cosim/drivers/diag/cepCsrTest.cc | 31 +-
cosim/drivers/diag/cepGpioTest.cc | 47 +
cosim/drivers/diag/cepGpioTest.h | 1 +
cosim/drivers/diag/cepMacroMix.cc | 8 -
cosim/drivers/diag/cepMaskromTest.cc | 14 +-
cosim/drivers/diag/cepMultiThread.cc | 340 ++++++
cosim/drivers/diag/cepMultiThread.h | 28 +
cosim/drivers/diag/cepPlicTest.cc | 115 +-
cosim/drivers/diag/cepPlicTest.h | 3 +
cosim/drivers/diag/cepSpiTest.cc | 7 +-
cosim/drivers/diag/cepSpiTest.h | 1 +
cosim/drivers/diag/cepSrotMemTest.cc | 2 +-
cosim/drivers/diag/cepUartTest.cc | 13 +-
cosim/drivers/linux/Makefile | 12 +-
cosim/drivers/linux/cep_diag.cc | 8 +-
cosim/drivers/linux/cep_diag.mk | 2 +-
cosim/drivers/linux/cep_exports.cc | 53 +
cosim/drivers/linux/cep_exports.h | 109 +-
cosim/drivers/linux/cep_io.h | 48 +-
cosim/drivers/linux/cep_run.cc | 38 +-
cosim/drivers/linux/cep_run.h | 4 +
cosim/drivers/linux/cep_vars.cc | 1 +
cosim/drivers/linux/cep_vars.h | 3 +-
cosim/drivers/linux/strace/Config.in | 8 +
cosim/drivers/linux/strace/README | 9 +
cosim/drivers/linux/strace/strace.mk | 26 +
cosim/drivers/vectors/aes_playback.h | 2 +-
cosim/drivers/vectors/aes_stimulus.txt.gz | Bin 26312 -> 26312 bytes
cosim/drivers/vectors/des3_playback.h | 310 ++---
cosim/drivers/vectors/des3_stimulus.txt.gz | Bin 200916 -> 187831 bytes
cosim/drivers/vectors/dft_playback.h | 794 ++++++------
cosim/drivers/vectors/dft_stimulus.txt.gz | Bin 15755 -> 15013 bytes
cosim/drivers/vectors/fir_playback.h | 2 +-
cosim/drivers/vectors/fir_stimulus.txt.gz | Bin 7543 -> 7543 bytes
cosim/drivers/vectors/gps_playback.h | 2 +-
cosim/drivers/vectors/gps_stimulus.txt.gz | Bin 43965 -> 43965 bytes
cosim/drivers/vectors/idft_stimulus.txt.gz | Bin 16412 -> 16234 bytes
cosim/drivers/vectors/iir_playback.h | 506 ++++----
cosim/drivers/vectors/iir_stimulus.txt.gz | Bin 16969 -> 13892 bytes
cosim/drivers/vectors/md5_playback.h | 2 +-
cosim/drivers/vectors/md5_stimulus.txt.gz | Bin 194426 -> 194426 bytes
cosim/drivers/vectors/rsa_playback.h | 1070 ++++++++---------
cosim/drivers/vectors/rsa_stimulus.txt.gz | Bin 507646 -> 500610 bytes
cosim/drivers/vectors/sha256_playback.h | 1048 ++++++++--------
cosim/drivers/vectors/sha256_stimulus.txt.gz | Bin 88166 -> 82519 bytes
cosim/dvt/behav_models/cep_driver.v | 42 +-
cosim/dvt/cep_adrMap.incl | 50 +-
cosim/dvt/cep_tb.v | 104 +-
cosim/dvt/dump_control.incl | 2 +-
cosim/dvt/sys_common.incl | 19 +-
cosim/dvt/v2c_cmds.incl | 5 +
cosim/dvt/v2c_top.v | 20 +-
cosim/isaTests/Makefile | 21 +-
cosim/isaTests/common.make | 3 +
cosim/isaTests/config.v | 1 +
cosim/isaTests/dtmTest/Makefile | 49 +
cosim/isaTests/dtmTest/c_dispatch.cc | 181 +++
cosim/isaTests/dtmTest/c_dispatch.h | 23 +
cosim/isaTests/dtmTest/c_module.cc | 92 ++
cosim/isaTests/dtmTest/c_module.h | 18 +
cosim/isaTests/dtmTest/dtm.cfg | 56 +
cosim/isaTests/dtmTest/riscv_wrapper.cc | 75 ++
cosim/pli/dpi_bitbang.cc | 203 ++++
cosim/pli/dpi_bitbang.h | 25 +
cosim/share/portable_io.h | 2 +-
cosim/vBareTest/Makefile | 2 +-
cosim/vBareTest/dTLB/c_dispatch.cc | 2 +-
doc/version3.2.jpg | Bin 8692 -> 0 bytes
doc/version3.3.jpg | Bin 0 -> 8923 bytes
hdl_cores/freedom/bootrom/sdboot/Makefile | 20 +-
hdl_cores/freedom/bootrom/sdboot/common.h | 11 +
hdl_cores/freedom/bootrom/sdboot/head.S | 22 +
.../freedom/bootrom/sdboot/include/platform.h | 2 +-
.../freedom/bootrom/sdboot/linker/memory.lds | 11 +-
hdl_cores/freedom/bootrom/sdboot/sd.c | 5 +-
hdl_cores/freedom/bootrom/sdboot/xExeHacked.c | 101 ++
hdl_cores/freedom/common.mk | 21 +-
.../src/main/scala/cep_addresses.scala | 4 +-
.../src/main/scala/cep_registers.scala | 8 +-
.../main/scala/unleashed/DevKitConfigs.scala | 4 +-
.../scala/unleashed/DevKitFPGADesign.scala | 11 +-
hdl_cores/llki/llki_pkg.sv | 29 +-
hdl_cores/llki/llki_pp_wrapper.sv | 6 +-
hdl_cores/llki/srot_wrapper.sv | 22 +-
.../TL_level_sim/supports/insertLLKI.pl | 56 -
.../TL_level_sim/sv_vectors/aes_playback.h | 2 +-
.../TL_level_sim/sv_vectors/des3_playback.h | 310 ++---
.../TL_level_sim/sv_vectors/dft_playback.h | 794 ++++++------
.../TL_level_sim/sv_vectors/fir_playback.h | 2 +-
.../TL_level_sim/sv_vectors/gps_playback.h | 2 +-
.../TL_level_sim/sv_vectors/idft_playback.h | 794 ++++++------
.../TL_level_sim/sv_vectors/iir_playback.h | 506 ++++----
.../TL_level_sim/sv_vectors/md5_playback.h | 2 +-
.../TL_level_sim/sv_vectors/rsa_playback.h | 1070 ++++++++---------
.../TL_level_sim/sv_vectors/sha256_playback.h | 1048 ++++++++--------
unit_simulation/aes_sim/aes_stimulus.txt.gz | Bin 26312 -> 26312 bytes
unit_simulation/des3_sim/des3_stimulus.txt.gz | Bin 200916 -> 187831 bytes
unit_simulation/dft_sim/dft_stimulus.txt.gz | Bin 15755 -> 15013 bytes
unit_simulation/fir_sim/fir_stimulus.txt.gz | Bin 7543 -> 7543 bytes
unit_simulation/gps_sim/gps_stimulus.txt.gz | Bin 43965 -> 43965 bytes
unit_simulation/idft_sim/idft_stimulus.txt.gz | Bin 16412 -> 16234 bytes
unit_simulation/iir_sim/iir_stimulus.txt.gz | Bin 16969 -> 13892 bytes
unit_simulation/md5_sim/md5_stimulus.txt.gz | Bin 194426 -> 194426 bytes
unit_simulation/rsa_sim/rsa_stimulus.txt.gz | Bin 507646 -> 500610 bytes
.../sha256_sim/sha256_stimulus.txt.gz | Bin 88166 -> 82519 bytes
180 files changed, 8168 insertions(+), 5349 deletions(-)
create mode 100644 cosim/bareMetalTests/bootViaScratch/Makefile
create mode 100644 cosim/bareMetalTests/bootViaScratch/c_dispatch.cc
create mode 100644 cosim/bareMetalTests/bootViaScratch/c_dispatch.h
create mode 100644 cosim/bareMetalTests/bootViaScratch/c_module.cc
create mode 100644 cosim/bareMetalTests/bootViaScratch/c_module.h
create mode 100644 cosim/bareMetalTests/bootViaScratch/imp.h
create mode 100644 cosim/bareMetalTests/bootViaScratch/riscv_wrapper.cc
create mode 100644 cosim/bareMetalTests/clintIntr/Makefile
create mode 100644 cosim/bareMetalTests/clintIntr/c_dispatch.cc
create mode 100644 cosim/bareMetalTests/clintIntr/c_dispatch.h
create mode 100644 cosim/bareMetalTests/clintIntr/c_module.cc
create mode 100644 cosim/bareMetalTests/clintIntr/c_module.h
create mode 100644 cosim/bareMetalTests/clintIntr/riscv_wrapper.cc
create mode 100644 cosim/bareMetalTests/clintIntr/riscv_wrapper.h
create mode 100644 cosim/bareMetalTests/plicPrioIntr/Makefile
create mode 100644 cosim/bareMetalTests/plicPrioIntr/c_dispatch.cc
create mode 100644 cosim/bareMetalTests/plicPrioIntr/c_dispatch.h
create mode 100644 cosim/bareMetalTests/plicPrioIntr/c_module.cc
create mode 100644 cosim/bareMetalTests/plicPrioIntr/c_module.h
create mode 100644 cosim/bareMetalTests/plicPrioIntr/riscv_wrapper.cc
create mode 100644 cosim/bfmTests/multiThread/Makefile
create mode 100644 cosim/bfmTests/multiThread/c_dispatch.cc
create mode 100644 cosim/bfmTests/multiThread/c_dispatch.h
create mode 100644 cosim/bfmTests/multiThread/c_module.cc
rename cosim/{drivers/bootbare/common.h => bfmTests/multiThread/c_module.h} (70%)
create mode 100644 cosim/bfmTests/multiThread/imp.h
create mode 100644 cosim/bfmTests/plicPrioIntr/Makefile
create mode 100644 cosim/bfmTests/plicPrioIntr/c_dispatch.cc
create mode 100644 cosim/bfmTests/plicPrioIntr/c_dispatch.h
create mode 100644 cosim/bfmTests/plicPrioIntr/c_module.cc
create mode 100644 cosim/bfmTests/plicPrioIntr/c_module.h
delete mode 100644 cosim/drivers/bootbare/Makefile
delete mode 100644 cosim/drivers/bootbare/bootbare.c
delete mode 100644 cosim/drivers/bootbare/head.S
delete mode 100644 cosim/drivers/bootbare/include/bits.h
delete mode 100644 cosim/drivers/bootbare/include/const.h
delete mode 100644 cosim/drivers/bootbare/include/devices/clint.h
delete mode 100644 cosim/drivers/bootbare/include/devices/gpio.h
delete mode 100644 cosim/drivers/bootbare/include/devices/plic.h
delete mode 100644 cosim/drivers/bootbare/include/devices/spi.h
delete mode 100644 cosim/drivers/bootbare/include/devices/uart.h
delete mode 100644 cosim/drivers/bootbare/include/platform.h
delete mode 100644 cosim/drivers/bootbare/include/riscv_test_defaults.h
delete mode 100644 cosim/drivers/bootbare/include/sections.h
delete mode 100644 cosim/drivers/bootbare/include/smp.h
delete mode 100644 cosim/drivers/bootbare/linker/memory.lds
delete mode 100644 cosim/drivers/bootbare/linker/sdboot.elf.lds
create mode 100644 cosim/drivers/diag/cepMultiThread.cc
create mode 100644 cosim/drivers/diag/cepMultiThread.h
create mode 100644 cosim/drivers/linux/strace/Config.in
create mode 100644 cosim/drivers/linux/strace/README
create mode 100644 cosim/drivers/linux/strace/strace.mk
create mode 100644 cosim/isaTests/dtmTest/Makefile
create mode 100644 cosim/isaTests/dtmTest/c_dispatch.cc
create mode 100644 cosim/isaTests/dtmTest/c_dispatch.h
create mode 100644 cosim/isaTests/dtmTest/c_module.cc
create mode 100644 cosim/isaTests/dtmTest/c_module.h
create mode 100644 cosim/isaTests/dtmTest/dtm.cfg
create mode 100644 cosim/isaTests/dtmTest/riscv_wrapper.cc
create mode 100644 cosim/pli/dpi_bitbang.cc
create mode 100644 cosim/pli/dpi_bitbang.h
delete mode 100644 doc/version3.2.jpg
create mode 100644 doc/version3.3.jpg
create mode 100644 hdl_cores/freedom/bootrom/sdboot/xExeHacked.c
delete mode 100755 unit_simulation/TL_level_sim/supports/insertLLKI.pl
diff --git a/README.md b/README.md
index 821a3f7..ff2cbb4 100644
--- a/README.md
+++ b/README.md
@@ -8,7 +8,7 @@
-
+
Copyright 2021 Massachusetts Institute of Technology
@@ -25,7 +25,7 @@ For CEP v3.1+, the full LLKI has been added. This includes the Surrogate Root o
### Please check the [Release Notes](./RELEASE_NOTES.md) to understand what has changed and a list of known issues.
-
+
@@ -341,7 +341,7 @@ You should see the following logo/text appear:
./+++++++++++oo+++: +oo++o++++o+o+oo+oo.- `s+++s`-
.--:---:-:-::-::` -::::::::::::::::::. :::::.
- Common Evaluation Platform v3.20
+ Common Evaluation Platform v3.30
Copyright 2021 Massachusetts Institute of Technology
Built upon the SiFive Freedom U500 Platform using
@@ -364,7 +364,7 @@ At the command prompt, you can run the CEP diagnostics by commanding `cep_diag`.
A partial output should be similar to:
```sh
-*** CEP Tag=CEPTest CEP HW VERSION = v3.20 was built on Apr 15 2021 09:22:15 ***
+*** CEP Tag=CEPTest CEP HW VERSION = v3.30 was built on Apr 15 2021 09:22:15 ***
CEP FPGA Physical: cepReg/ddr3/other/sys -> Virtual=0x0000000700000000, 0x0000000800000000, 0x0000000600000000, 0x0000000c00000000 ScratchPad=0x0000002000800000
gSkipInit=0/0
gverbose=0/0
diff --git a/RELEASE_NOTES.md b/RELEASE_NOTES.md
index 4a90792..8d3dd0d 100644
--- a/RELEASE_NOTES.md
+++ b/RELEASE_NOTES.md
@@ -121,4 +121,14 @@ v3.2 - (16 April 2021)
* Linux tests updated and expanded
* New tests added to cosim focused on LLKI and Scratchpad RAM
+v3.3 - (19 May 2021)
+* Increased capacity for LLKI key size including larger KeyRAM (2048 64-bit words)
+* Added Cosim JTAG/OpenOCD
+* Stability fixes for cep_diag under Linux
+* Virtual Address TLB test suite is added to regression (not 100% complete)
+* Expanded cep_diag
+* New simulation ONLY interrupt tests for CLINT and PLIC modules (on going)
+* Re-capture vectors for unit sim due to changes in LLKI key size
+* Bootrom size is increased to 32K bytes (8kx32) to accomodate new built-in test (execute codes out of bootrom without main memory)
+
#### Return to the root CEP [README](./README.md)
\ No newline at end of file
diff --git a/cosim/Makefile b/cosim/Makefile
index 408aef0..69cc624 100644
--- a/cosim/Makefile
+++ b/cosim/Makefile
@@ -34,7 +34,7 @@ SIM_DIR = ${DUT_TOP_DIR}/${COSIM_NAME}
TEST_GROUP = bareMetalTests \
bfmTests \
isaTests \
-
+ vBareTest \
runAll:
make cleanAll
diff --git a/cosim/README.md b/cosim/README.md
index 6cc819a..31c394b 100644
--- a/cosim/README.md
+++ b/cosim/README.md
@@ -16,6 +16,7 @@ Several environments are supported:
* Linux Mode (tests run on xilinx VC707 development card). Build and installation instructions can be found in: [../README.md](../README.md)
* Benchmarking on Linux (TBA)
* Cycle-accurate and translation-level accurate unit level simulations.
+* JTAG support to inferace with Openocd tool (via bitbang adapter) for Open On-Chip debugger (version 3.3 or later)
## Benefits: ##
@@ -53,7 +54,7 @@ Assuming you already have the CEP-master (version 2.0 or later) sandbox pulled f
isaTests/rv64mi-p-access
isaTests/rv64ud-p-ldst
```
- NOTE: All tests (including the above failed tests) are now passing with version 2.8 or later under Linux machine..
+ **NOTE**: All tests (including the above failed tests) are now passing with version 2.8 or later under Linux machine..
## Verify environment settings and tools: ##
@@ -330,10 +331,11 @@ During simulation, you will notice each of the core will print out its PC (Progr
Also, there are riscv_wrapper.dump (created from objdump to help track the PC), riscv_wrapper.elf (to preload to main memory) and riscv_wrapper.hex files are created by Make under each test directory.
+**Note**: for version 3.3 or later, directory **.../cosim/drivers/bootbare** is removed and the official bootrom generation Makefile is adjusted to also produce the bootrom image for simulation.
## Building ISA tests for simulation ##
-As of version 2.7 or later, ISA (Instruction-Set-Architecture) tests are added to simulation to improve overall chip coverages.
+For version 2.7 or later, ISA (Instruction-Set-Architecture) tests are added to simulation to improve overall chip coverages.
**All ISA tests are re-used from https://github.com/riscv/riscv-tests.git repository**.
@@ -401,7 +403,7 @@ And now you are ready to do the build as follows
cd /software/riscv-tests
autoconf
./configure
- make isa <-- only need to make ISA, without argument benchmark tests will be included (benchmarks have NOT be ported)
+ make isa <-- only need to make ISA, without argument benchmark tests will also be included (benchmarks have NOT been ported)
```
The make command above will compile **mostly** assembly tests in the directory **isa** under it. These are the ones will be re-used to run in our simulation. **NOTE**: only RV64*-p/v-* tests are used since the cores are 64-bit cores.
@@ -419,6 +421,43 @@ Next step is to port and prepare those ISA tests above for simulation.
And we are now done for this ISA porting.
+## About JTAG/Debug port testing and Openocd ##
+
+To test JTAG port in simulation, openocd tool is needed. The Makefile will check for the present of such tool before any jtag related test is allowed to run.
+
+This JTAG port is connected to the CEP's DTM (DebugTransportModule). It is used to facilitate debugging via GDB. Openocd acts as transport layer between the internal DTM and GDB.
+
+A short description of what openocd is about:
+
+```
+OpenOCD provides on-chip programming and debugging support with a
+layered architecture of JTAG interface and TAP support including:
+
+- (X)SVF playback to facilitate automated boundary scan and FPGA/CPLD
+ programming;
+- debug target support (e.g. ARM, MIPS): single-stepping,
+ breakpoints/watchpoints, gprof profiling, etc;
+- flash chip drivers (e.g. CFI, NAND, internal flash);
+- embedded TCL interpreter for easy scripting.
+```
+
+To support simulation, DPI & remote-bitbang must be enable when building openocd tool.
+
+Download openocd via this link: **https://github.com/riscv/riscv-openocd**
+
+And follow the README file in there to build the tool or for more details how to use the tool. Instructions are cut/paste below for quick reference:
+
+```
+To build OpenOCD, use the following sequence of commands:
+
+ ./bootstrap (when building from the git repository)
+ ./configure -enable-remote-bitbang --enable-jtag_dpi [options]
+ make
+ sudo make install
+```
+
+To see how this works, run this test: **<...>/cosim/isaTests/dtmTest**
+
## How to add your new test for regression ##
Open ../Makefile (one level up where your test directory is located).
@@ -494,3 +533,11 @@ make CADENCE=1 mergeAll <-- merge all coverage data and report in HTLM format
* By default, under each test directory, one file will be created **if and only if** it is not yet there: **vsim.do**. It is used when **vsim** command is called to control the wave capturing.. If there is a need to override, users are free to modify and change it to anyway to fit the needs. Makefile will not overwrite it as long as it is there.
* Under bare metal mode, some of main memory locations are used as mailbox to help RISCV core tracking and printing. See .**../cosim/dvt/cep_adrMap.incl** file. **NOTE**: there is also a file under .../cosim/include/cep_adrMap.h This file is auto-generated from the cep_adrMap.incl mentioned. Therefore, any modification should be made to the cep_adrMap.incl file.
+
+* Below is the short-cut to quickly build cep_diag application for Linux:
+
+```
+cd <...>/cosim/drivers/linux
+make buildMe
+```
+
diff --git a/cosim/bareMetalTests/Makefile b/cosim/bareMetalTests/Makefile
index 31c67d2..63b6cfd 100644
--- a/cosim/bareMetalTests/Makefile
+++ b/cosim/bareMetalTests/Makefile
@@ -66,6 +66,9 @@ BARE_TEST_LIST = \
fragmemter \
csrTest \
srotMemTest \
+ bootViaScratch \
+ clintIntr \
+ plicPrioIntr \
TESTINFO_LIST := $(sort $(foreach t,${TALUS_TEST_LIST},${BLD_DIR}/${t}/testInfo.txt))
diff --git a/cosim/bareMetalTests/bootViaScratch/Makefile b/cosim/bareMetalTests/bootViaScratch/Makefile
new file mode 100644
index 0000000..d47240f
--- /dev/null
+++ b/cosim/bareMetalTests/bootViaScratch/Makefile
@@ -0,0 +1,32 @@
+#//************************************************************************
+#// Copyright 2021 Massachusetts Institute of Technology
+#// SPDX short identifier: BSD-2-Clause
+#//
+#// File Name:
+#// Program: Common Evaluation Platform (CEP)
+#// Description:
+#// Notes:
+#//
+#//************************************************************************
+#
+#
+#
+COSIM_NAME = $(shell cd ../..; basename `pwd`)
+DUT_TOP_DIR = $(shell cd ../../..; pwd | ./${COSIM_NAME}/bin/strip_net.pl )
+BLD_DIR = $(shell cd ..; pwd | ../bin/strip_net.pl )
+TEST_SUITE = $(shell basename ${BLD_DIR})
+TEST_DIR = $(shell cd .; pwd | ../../bin/strip_net.pl )
+TEST_NAME = $(shell basename `pwd`)
+SIM_DIR = ${DUT_TOP_DIR}/${COSIM_NAME}
+
+
+#
+# Top target!!!
+#
+all: .vrun_flag riscv_wrapper.elf
+
+#
+# override anything here before calling the common file
+#
+include ${BLD_DIR}/common.make
+
diff --git a/cosim/bareMetalTests/bootViaScratch/c_dispatch.cc b/cosim/bareMetalTests/bootViaScratch/c_dispatch.cc
new file mode 100644
index 0000000..8682f1f
--- /dev/null
+++ b/cosim/bareMetalTests/bootViaScratch/c_dispatch.cc
@@ -0,0 +1,126 @@
+//************************************************************************
+// Copyright 2021 Massachusetts Institute of Technology
+// SPDX short identifier: BSD-2-Clause
+//
+// File Name:
+// Program: Common Evaluation Platform (CEP)
+// Description:
+// Notes:
+//
+//************************************************************************
+#include
+#include "v2c_cmds.h"
+#include "access.h"
+#include "c_dispatch.h"
+#include "c_module.h"
+#include "cep_apis.h"
+#include "cep_adrMap.h"
+#include "simPio.h"
+/*
+ * main
+ */
+int main(int argc, char *argv[])
+{
+
+ /* ===================================== */
+ /* SETUP SECTION FOR SIMULATION */
+ /* ===================================== */
+ unsigned long seed;
+ sscanf(argv[1],"0x%x",&seed);
+ printf("Seed = 0x%x\n",seed);
+ int errCnt = 0;
+ int verbose = 0x1f;
+
+ /* ===================================== */
+ /* spawn all the paralle threads */
+ /* ===================================== */
+ int activeSlot=0; // only 1 board
+ //
+ // ============================
+ // fork all the tests here
+ // ============================
+ //
+ shPthread thr;
+ //
+ // max number of cores not include the system thread
+ //
+ int maxHost = MAX_CORES; // number of cores/threads
+ //
+ // each bit is to turn on the given core (bit0 = core0, bit1=core1, etc..)
+ //
+ long unsigned int mask = 0xF;
+ //
+ // Set the active CPU mask before spawn the threads...
+ //
+ thr.SetActiveMask(mask);
+ //
+ // c_module is the threead to run
+ //
+ for (int i=0;i
+#include "random48.h"
+
+#include "cep_adrMap.h"
+#include "cep_apis.h"
+#include "simdiag_global.h"
+#include "cepregression.h"
+#include "simPio.h"
+
+//
+void *c_module(void *arg) {
+
+
+ // ======================================
+ // Set up
+ // ======================================
+ pthread_parm_t *tParm = (pthread_parm_t *)arg;
+ int errCnt = 0;
+ int slotId = tParm->slotId;
+ int cpuId = tParm->cpuId;
+ int verbose = tParm->verbose;
+ Int32U seed = tParm->seed;
+ int restart = tParm->restart;
+ int offset = GET_OFFSET(slotId,cpuId);
+ GlobalShMemory.getSlotCpuId(offset,&slotId,&cpuId);
+ //printf("offset=%x seed=%x verbose=%x GlobalShMemory=%x\n",offset,seed, verbose,(unsigned long) &GlobalShMemory);
+ // notify I am Alive!!!
+ shIpc *ptr = GlobalShMemory.getIpcPtr(offset);
+ ptr->SetAliveStatus();
+ sleep(1);
+
+ // ======================================
+ // Test is Here
+ // ======================================
+ simPio pio;
+ pio.MaybeAThread(); // chec
+ pio.EnableShIpc(1);
+ pio.SetVerbose(verbose);
+
+ //
+ // ======================================
+ // Test starts here
+ // ======================================
+ // MUST
+ // wait until Calibration is done..
+ //int calibDone = calibrate_ddr3(50);
+ int calibDone = is_program_loaded(50);
+
+ //
+ errCnt += check_bare_status(cpuId,500);
+ //
+ pio.RunClk(100);
+ //
+ // ======================================
+ // Exit
+ // ======================================
+cleanup:
+ if (errCnt != 0) {
+ LOGI("======== TEST FAIL ========== %x\n",errCnt);
+ } else {
+ LOGI("======== TEST PASS ========== \n");
+ }
+ // shIpc *ptr = GlobalShMemory.getIpcPtr(offset);
+ ptr->SetError(errCnt);
+ ptr->SetThreadDone();
+ pthread_exit(NULL);
+ return ((void *)NULL);
+}
+
diff --git a/cosim/bareMetalTests/bootViaScratch/c_module.h b/cosim/bareMetalTests/bootViaScratch/c_module.h
new file mode 100644
index 0000000..3e5bb5c
--- /dev/null
+++ b/cosim/bareMetalTests/bootViaScratch/c_module.h
@@ -0,0 +1,18 @@
+//************************************************************************
+// Copyright 2021 Massachusetts Institute of Technology
+// SPDX short identifier: BSD-2-Clause
+//
+// File Name:
+// Program: Common Evaluation Platform (CEP)
+// Description:
+// Notes:
+//
+//************************************************************************
+#ifndef c_module_H
+#define c_module_H
+
+#include "shPthread.h"
+
+void *c_module(void *); /* thread routine */
+
+#endif
diff --git a/cosim/bareMetalTests/bootViaScratch/imp.h b/cosim/bareMetalTests/bootViaScratch/imp.h
new file mode 100644
index 0000000..e3509dd
--- /dev/null
+++ b/cosim/bareMetalTests/bootViaScratch/imp.h
@@ -0,0 +1,49 @@
+/***********************************************
+ DO NOT MODIFY THE CONTENTS OF THIS FILE.
+ This header file has been auto-generated by xmelab.
+ This should be included in user'c C file to
+ facilitate the calling of imported tasks and functions.
+************************************************/
+
+#include "svdpi.h"
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+typedef struct {
+ int _a0;
+ int _a1;
+ int _a2;
+ unsigned int _a3;
+ unsigned int _a4;
+ unsigned int _a5;
+ unsigned long long _a6;
+ unsigned long long _a7[32];
+ char _a8[256];
+ char _a9[256];
+ } v2c_top__mailBox;
+
+
+typedef struct {
+ int _a0;
+ int _a1;
+ int _a2;
+ unsigned int _a3;
+ unsigned int _a4;
+ unsigned int _a5;
+ unsigned long long _a6;
+ unsigned long long _a7[32];
+ char _a8[256];
+ char _a9[256];
+ } cep_driver__mailBox;
+
+
+extern void send_v2c_mail (int _a1, int _a2, v2c_top__mailBox *_a3);
+
+extern void get_v2c_mail (int _a1, int _a2, v2c_top__mailBox *_a3);
+
+#ifdef __cplusplus
+ }
+#endif
+
diff --git a/cosim/bareMetalTests/bootViaScratch/riscv_wrapper.cc b/cosim/bareMetalTests/bootViaScratch/riscv_wrapper.cc
new file mode 100644
index 0000000..53fc7c0
--- /dev/null
+++ b/cosim/bareMetalTests/bootViaScratch/riscv_wrapper.cc
@@ -0,0 +1,80 @@
+//************************************************************************
+// Copyright 2021 Massachusetts Institute of Technology
+// SPDX short identifier: BSD-2-Clause
+//
+// File Name:
+// Program: Common Evaluation Platform (CEP)
+// Description:
+// Notes:
+//
+//************************************************************************
+//
+// For bareMetal mode ONLY
+//
+#ifdef BARE_MODE
+#include "cep_adrMap.h"
+#include "cep_apis.h"
+
+#include "portable_io.h"
+#include "cepRegTest.h"
+
+
+//#define printf(...) { return 0; }
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//int main(void)
+void thread_entry(int cid, int nc)
+{
+ //
+ int errCnt = 0;
+ int testId[4] = {0x00,0x11,0x22,0x33};
+ int coreId = read_csr(mhartid);
+ //
+ set_printf(0);
+
+ //
+ //
+ set_cur_status(CEP_RUNNING_STATUS);
+ //if (!errCnt) { errCnt = cepRegTest_runTest(coreId,64, revCheck, coreId*(0x100), 0); }
+
+ //
+ // Written by core0 during boot
+ // so read them here to verify core0 did go thru the boot sequrce via scratchpad.
+ //
+ uint64_t rdDat;
+ uint64_t wrDat = scratchpad_know_pattern;
+ //
+ for (int i=0;i<8;i++) {
+ DUT_READ32_64(scratchpad_base_addr + (i*0x100),rdDat);
+ if (rdDat != wrDat) {
+ errCnt++;
+ break;
+ }
+ wrDat++;
+ }
+ //
+ //
+ // Done
+ //
+ set_status(errCnt,testId[coreId]);
+ /*
+ if (errCnt) {
+ set_pass();
+ } else {
+ set_fail();
+ }
+ */
+ //
+ // Stuck here forever...
+ //
+ exit(errCnt);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/cosim/bareMetalTests/clintIntr/Makefile b/cosim/bareMetalTests/clintIntr/Makefile
new file mode 100644
index 0000000..d47240f
--- /dev/null
+++ b/cosim/bareMetalTests/clintIntr/Makefile
@@ -0,0 +1,32 @@
+#//************************************************************************
+#// Copyright 2021 Massachusetts Institute of Technology
+#// SPDX short identifier: BSD-2-Clause
+#//
+#// File Name:
+#// Program: Common Evaluation Platform (CEP)
+#// Description:
+#// Notes:
+#//
+#//************************************************************************
+#
+#
+#
+COSIM_NAME = $(shell cd ../..; basename `pwd`)
+DUT_TOP_DIR = $(shell cd ../../..; pwd | ./${COSIM_NAME}/bin/strip_net.pl )
+BLD_DIR = $(shell cd ..; pwd | ../bin/strip_net.pl )
+TEST_SUITE = $(shell basename ${BLD_DIR})
+TEST_DIR = $(shell cd .; pwd | ../../bin/strip_net.pl )
+TEST_NAME = $(shell basename `pwd`)
+SIM_DIR = ${DUT_TOP_DIR}/${COSIM_NAME}
+
+
+#
+# Top target!!!
+#
+all: .vrun_flag riscv_wrapper.elf
+
+#
+# override anything here before calling the common file
+#
+include ${BLD_DIR}/common.make
+
diff --git a/cosim/bareMetalTests/clintIntr/c_dispatch.cc b/cosim/bareMetalTests/clintIntr/c_dispatch.cc
new file mode 100644
index 0000000..605262d
--- /dev/null
+++ b/cosim/bareMetalTests/clintIntr/c_dispatch.cc
@@ -0,0 +1,126 @@
+//************************************************************************
+// Copyright 2021 Massachusetts Institute of Technology
+// SPDX short identifier: BSD-2-Clause
+//
+// File Name:
+// Program: Common Evaluation Platform (CEP)
+// Description:
+// Notes:
+//
+//************************************************************************
+#include
+#include "v2c_cmds.h"
+#include "access.h"
+#include "c_dispatch.h"
+#include "c_module.h"
+#include "cep_apis.h"
+#include "cep_adrMap.h"
+#include "simPio.h"
+/*
+ * main
+ */
+int main(int argc, char *argv[])
+{
+
+ /* ===================================== */
+ /* SETUP SECTION FOR SIMULATION */
+ /* ===================================== */
+ unsigned long seed;
+ sscanf(argv[1],"0x%x",&seed);
+ printf("Seed = 0x%x\n",seed);
+ int errCnt = 0;
+ int verbose = 0x1f;
+
+ /* ===================================== */
+ /* spawn all the paralle threads */
+ /* ===================================== */
+ int activeSlot=0; // only 1 board
+ //
+ // ============================
+ // fork all the tests here
+ // ============================
+ //
+ shPthread thr;
+ //
+ // max number of cores not include the system thread
+ //
+ int maxHost = MAX_CORES; // number of cores/threads
+ //
+ // each bit is to turn on the given core (bit0 = core0, bit1=core1, etc..)
+ //
+ long unsigned int mask = 0xf;
+ //
+ // Set the active CPU mask before spawn the threads...
+ //
+ thr.SetActiveMask(mask);
+ //
+ // c_module is the threead to run
+ //
+ for (int i=0;i
+#include "random48.h"
+
+#include "cep_adrMap.h"
+#include "cep_apis.h"
+#include "simdiag_global.h"
+#include "cepregression.h"
+#include "simPio.h"
+
+//
+void *c_module(void *arg) {
+
+
+ // ======================================
+ // Set up
+ // ======================================
+ pthread_parm_t *tParm = (pthread_parm_t *)arg;
+ int errCnt = 0;
+ int slotId = tParm->slotId;
+ int cpuId = tParm->cpuId;
+ int verbose = tParm->verbose;
+ Int32U seed = tParm->seed;
+ int restart = tParm->restart;
+ int offset = GET_OFFSET(slotId,cpuId);
+ GlobalShMemory.getSlotCpuId(offset,&slotId,&cpuId);
+ //printf("offset=%x seed=%x verbose=%x GlobalShMemory=%x\n",offset,seed, verbose,(unsigned long) &GlobalShMemory);
+ // notify I am Alive!!!
+ shIpc *ptr = GlobalShMemory.getIpcPtr(offset);
+ ptr->SetAliveStatus();
+ sleep(1);
+
+ // ======================================
+ // Test is Here
+ // ======================================
+ simPio pio;
+ pio.MaybeAThread(); // chec
+ pio.EnableShIpc(1);
+ pio.SetVerbose(verbose);
+
+ //
+ // ======================================
+ // Test starts here
+ // ======================================
+ // MUST
+ // wait until Calibration is done..
+ //int calibDone = calibrate_ddr3(50);
+ int calibDone = is_program_loaded(50);
+
+ //
+ errCnt += check_bare_status(cpuId,500);
+ //
+ pio.RunClk(100);
+ //
+ // ======================================
+ // Exit
+ // ======================================
+cleanup:
+ if (errCnt != 0) {
+ LOGI("======== TEST FAIL ========== %x\n",errCnt);
+ } else {
+ LOGI("======== TEST PASS ========== \n");
+ }
+ // shIpc *ptr = GlobalShMemory.getIpcPtr(offset);
+ ptr->SetError(errCnt);
+ ptr->SetThreadDone();
+ pthread_exit(NULL);
+ return ((void *)NULL);
+}
+
diff --git a/cosim/bareMetalTests/clintIntr/c_module.h b/cosim/bareMetalTests/clintIntr/c_module.h
new file mode 100644
index 0000000..3e5bb5c
--- /dev/null
+++ b/cosim/bareMetalTests/clintIntr/c_module.h
@@ -0,0 +1,18 @@
+//************************************************************************
+// Copyright 2021 Massachusetts Institute of Technology
+// SPDX short identifier: BSD-2-Clause
+//
+// File Name:
+// Program: Common Evaluation Platform (CEP)
+// Description:
+// Notes:
+//
+//************************************************************************
+#ifndef c_module_H
+#define c_module_H
+
+#include "shPthread.h"
+
+void *c_module(void *); /* thread routine */
+
+#endif
diff --git a/cosim/bareMetalTests/clintIntr/riscv_wrapper.cc b/cosim/bareMetalTests/clintIntr/riscv_wrapper.cc
new file mode 100644
index 0000000..3bf32d7
--- /dev/null
+++ b/cosim/bareMetalTests/clintIntr/riscv_wrapper.cc
@@ -0,0 +1,175 @@
+//************************************************************************
+// Copyright 2021 Massachusetts Institute of Technology
+// SPDX short identifier: BSD-2-Clause
+//
+// File Name:
+// Program: Common Evaluation Platform (CEP)
+// Description:
+// Notes:
+//
+//************************************************************************
+//
+// For bareMetal mode ONLY
+//
+#ifdef BARE_MODE
+#include "cep_adrMap.h"
+#include "cep_apis.h"
+#include "portable_io.h"
+
+#include "cepRegTest.h"
+#include "cepregression.h"
+
+#include "riscv_wrapper.h"
+
+//
+// =================================
+// Interrupt stuffs
+// =================================
+//
+volatile unsigned interrupt_count[NHARTS];
+volatile unsigned local[NHARTS];
+
+void *timerIntr(unsigned hartid, unsigned long long mcause, void *mepc, void *sp)
+{
+ //unsigned delta = 0x100;
+ set_csr(mie, 0);
+ //
+ interrupt_count[hartid] |= 1 << (mcause & 0x1f); // set the bit
+ // wait til clear
+ while (read_csr(mip) & MIP_MTIP) {
+ MTIMECMP[hartid] = (uint64_t)(-1); // clear
+ }
+ // save mcause to my sratch register
+ DUT_WRITE32_64(reg_base_addr + cep_scratch0_reg + (hartid * 8), mcause);
+ //
+ return mepc;
+}
+
+void *swIntr(unsigned hartid, unsigned long long mcause, void *mepc, void *sp)
+{
+ set_csr(mie, 0);
+ MSIP_OFFS[hartid] = 0; // clear??
+ //
+ interrupt_count[hartid] |= 1 << (mcause & 0x1f); // set the bit
+ //
+ // Clear the interrup
+ //
+ //
+ // save mcause to my sratch register
+ //
+ DUT_WRITE32_64(reg_base_addr + cep_scratch0_reg + (hartid * 8), mcause);
+ //
+ // jump pass ecall!!!
+ //
+ //return (mepc + 4); // if use ecall
+ return mepc;
+}
+
+trap_handler_t trap_handler[NHARTS] = {NULL,NULL,NULL,NULL}; // timerIntr,timerIntr,timerIntr,timerIntr};
+
+int set_trap_handler(trap_handler_t handler)
+{
+ int errCnt = 0;
+ unsigned hartid = read_csr(mhartid);
+ errCnt = trap_handler[hartid] == NULL ? 0 : 1;
+ trap_handler[hartid] = handler;
+ return errCnt;
+}
+
+void enable_timer_interrupts()
+{
+ set_csr(mie, MIP_MTIP);
+ set_csr(mstatus, MSTATUS_MIE);
+ return;
+}
+
+void enable_sw_interrupts()
+{
+ set_csr(mie, MIP_MSIP);
+ set_csr(mstatus, MSTATUS_MIE);
+ return;
+}
+
+void handle_trap(unsigned long long mcause, void *mepc, void *sp)
+{
+ unsigned hartid = read_csr(mhartid);
+ if (trap_handler[hartid]) {
+ (*trap_handler[hartid])(hartid, mcause, mepc, sp);
+ return;
+ }
+
+ while (1)
+ ;
+}
+
+//
+// Main
+//
+void thread_entry(int cid, int nc)
+{
+ //
+ int errCnt = 0;
+ //
+ set_printf(0);
+ set_cur_status(CEP_RUNNING_STATUS);
+ //
+ unsigned hartid = read_csr(mhartid);
+ MTIMECMP[hartid] = (uint64_t)(-1);
+ interrupt_count[hartid] = 0;
+ local[hartid] = 0;
+
+ //
+ // ==================================
+ // First do the timer interrupt
+ // ==================================
+ //
+ local[hartid] += set_trap_handler((trap_handler_t)timerIntr);
+ // one less then current => interrupt
+ MTIMECMP[hartid] = MTIME - 1;
+ enable_timer_interrupts();
+ //
+ // stuck until got it
+ //
+ while ((interrupt_count[hartid] & (1 << IRQ_M_TIMER)) == 0) {
+ local[hartid]++;
+ if (local[hartid] & 0x8000) {
+ errCnt++;
+ break;
+ }
+ }
+ if (errCnt) goto done;
+ //
+ // ==================================
+ // Next is SW interrupt via ecall
+ // ==================================
+ //
+ local[hartid] += set_trap_handler((trap_handler_t)swIntr);
+ enable_sw_interrupts();
+ // execute an ecall to cause an SW interrupt = IRQ_M_EXT
+ //asm volatile ("ecall;"); // cause IRQ_M_EXT
+ MSIP_OFFS[hartid] = 1; // to create a software interrupt
+ //
+ // stuck here until interrupt
+ //
+ //while ((interrupt_count[hartid] & (1 << IRQ_M_EXT)) == 0) {
+ while ((interrupt_count[hartid] & (1 << IRQ_M_SOFT)) == 0) {
+ local[hartid]++;
+ if (local[hartid] & 0x8000) {
+ errCnt++;
+ break;
+ }
+ }
+ //
+ // Done
+ //
+ done:
+ set_status(errCnt,hartid);
+
+ //
+ // Stuck here forever...
+ //
+
+ exit(errCnt);
+}
+
+#endif
diff --git a/cosim/bareMetalTests/clintIntr/riscv_wrapper.h b/cosim/bareMetalTests/clintIntr/riscv_wrapper.h
new file mode 100644
index 0000000..0d4a912
--- /dev/null
+++ b/cosim/bareMetalTests/clintIntr/riscv_wrapper.h
@@ -0,0 +1,45 @@
+//************************************************************************
+// Copyright 2021 Massachusetts Institute of Technology
+// SPDX short identifier: BSD-2-Clause
+//
+// File Name:
+// Program: Common Evaluation Platform (CEP)
+// Description:
+// Notes:
+//
+//************************************************************************
+#ifndef riscv_wrapper_H
+#define riscv_wrapper_H
+
+#define NHARTS 4
+
+#define MTIME (*(volatile long long *)(0x02000000 + 0xbff8))
+#define MTIMECMP ((volatile long long *)(0x02000000 + 0x4000))
+
+// Write 32-bit ONLY
+#define MSIP_OFFS ((volatile uint32_t *)(0x02000000))
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef void* (*trap_handler_t)(unsigned hartid, unsigned long long mcause, void *mepc,
+ void *sp);
+
+ void thread_entry(int cid, int nc);
+ int set_trap_handler(trap_handler_t handler);
+ void enable_timer_interrupts();
+ void enable_sw_interrupts();
+ void handle_trap(unsigned long long mcause, void *mepc, void *sp);
+ //
+ // Timerupt handler
+ //
+ void *timerIntr(unsigned hartid, unsigned long long mcause, void *mepc, void *sp);
+ void *swIntr(unsigned hartid, unsigned long long mcause, void *mepc, void *sp);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/cosim/bareMetalTests/miscTests/riscv_wrapper.cc b/cosim/bareMetalTests/miscTests/riscv_wrapper.cc
index 0a6a045..b12ba20 100644
--- a/cosim/bareMetalTests/miscTests/riscv_wrapper.cc
+++ b/cosim/bareMetalTests/miscTests/riscv_wrapper.cc
@@ -36,10 +36,10 @@ void thread_entry(int cid, int nc)
set_printf(0);
switch (cpuId) {
- case 0 : errCnt += cepUartTest_runTest(cpuId,0x10, 0); break;
+ case 3 : errCnt += cepUartTest_runTest(cpuId,0x10, 0); break;
case 1 : errCnt += cepSpiTest_runTest(cpuId,0x20, 0); break;
case 2 : errCnt += cepGpioTest_runTest(cpuId,0x30,0); break;
- case 3 : errCnt += cepMaskromTest_runTest(cpuId,0x40,0); break;
+ case 0 : errCnt += cepMaskromTest_runTest(cpuId,0x40,0); break;
}
//
diff --git a/cosim/bareMetalTests/plicPrioIntr/Makefile b/cosim/bareMetalTests/plicPrioIntr/Makefile
new file mode 100644
index 0000000..d47240f
--- /dev/null
+++ b/cosim/bareMetalTests/plicPrioIntr/Makefile
@@ -0,0 +1,32 @@
+#//************************************************************************
+#// Copyright 2021 Massachusetts Institute of Technology
+#// SPDX short identifier: BSD-2-Clause
+#//
+#// File Name:
+#// Program: Common Evaluation Platform (CEP)
+#// Description:
+#// Notes:
+#//
+#//************************************************************************
+#
+#
+#
+COSIM_NAME = $(shell cd ../..; basename `pwd`)
+DUT_TOP_DIR = $(shell cd ../../..; pwd | ./${COSIM_NAME}/bin/strip_net.pl )
+BLD_DIR = $(shell cd ..; pwd | ../bin/strip_net.pl )
+TEST_SUITE = $(shell basename ${BLD_DIR})
+TEST_DIR = $(shell cd .; pwd | ../../bin/strip_net.pl )
+TEST_NAME = $(shell basename `pwd`)
+SIM_DIR = ${DUT_TOP_DIR}/${COSIM_NAME}
+
+
+#
+# Top target!!!
+#
+all: .vrun_flag riscv_wrapper.elf
+
+#
+# override anything here before calling the common file
+#
+include ${BLD_DIR}/common.make
+
diff --git a/cosim/bareMetalTests/plicPrioIntr/c_dispatch.cc b/cosim/bareMetalTests/plicPrioIntr/c_dispatch.cc
new file mode 100644
index 0000000..605262d
--- /dev/null
+++ b/cosim/bareMetalTests/plicPrioIntr/c_dispatch.cc
@@ -0,0 +1,126 @@
+//************************************************************************
+// Copyright 2021 Massachusetts Institute of Technology
+// SPDX short identifier: BSD-2-Clause
+//
+// File Name:
+// Program: Common Evaluation Platform (CEP)
+// Description:
+// Notes:
+//
+//************************************************************************
+#include
+#include "v2c_cmds.h"
+#include "access.h"
+#include "c_dispatch.h"
+#include "c_module.h"
+#include "cep_apis.h"
+#include "cep_adrMap.h"
+#include "simPio.h"
+/*
+ * main
+ */
+int main(int argc, char *argv[])
+{
+
+ /* ===================================== */
+ /* SETUP SECTION FOR SIMULATION */
+ /* ===================================== */
+ unsigned long seed;
+ sscanf(argv[1],"0x%x",&seed);
+ printf("Seed = 0x%x\n",seed);
+ int errCnt = 0;
+ int verbose = 0x1f;
+
+ /* ===================================== */
+ /* spawn all the paralle threads */
+ /* ===================================== */
+ int activeSlot=0; // only 1 board
+ //
+ // ============================
+ // fork all the tests here
+ // ============================
+ //
+ shPthread thr;
+ //
+ // max number of cores not include the system thread
+ //
+ int maxHost = MAX_CORES; // number of cores/threads
+ //
+ // each bit is to turn on the given core (bit0 = core0, bit1=core1, etc..)
+ //
+ long unsigned int mask = 0xf;
+ //
+ // Set the active CPU mask before spawn the threads...
+ //
+ thr.SetActiveMask(mask);
+ //
+ // c_module is the threead to run
+ //
+ for (int i=0;i
+#include "random48.h"
+
+#include "cep_adrMap.h"
+#include "cep_apis.h"
+#include "simdiag_global.h"
+#include "cepregression.h"
+#include "simPio.h"
+
+//
+void *c_module(void *arg) {
+
+
+ // ======================================
+ // Set up
+ // ======================================
+ pthread_parm_t *tParm = (pthread_parm_t *)arg;
+ int errCnt = 0;
+ int slotId = tParm->slotId;
+ int cpuId = tParm->cpuId;
+ int verbose = tParm->verbose;
+ Int32U seed = tParm->seed;
+ int restart = tParm->restart;
+ int offset = GET_OFFSET(slotId,cpuId);
+ GlobalShMemory.getSlotCpuId(offset,&slotId,&cpuId);
+ //printf("offset=%x seed=%x verbose=%x GlobalShMemory=%x\n",offset,seed, verbose,(unsigned long) &GlobalShMemory);
+ // notify I am Alive!!!
+ shIpc *ptr = GlobalShMemory.getIpcPtr(offset);
+ ptr->SetAliveStatus();
+ sleep(1);
+
+ // ======================================
+ // Test is Here
+ // ======================================
+ simPio pio;
+ pio.MaybeAThread(); // chec
+ pio.EnableShIpc(1);
+ pio.SetVerbose(verbose);
+
+ //
+ // ======================================
+ // Test starts here
+ // ======================================
+ // MUST
+ // wait until Calibration is done..
+ //int calibDone = calibrate_ddr3(50);
+ int calibDone = is_program_loaded(50);
+
+ //
+ errCnt += check_bare_status(cpuId,500);
+ //
+ pio.RunClk(100);
+ //
+ // ======================================
+ // Exit
+ // ======================================
+cleanup:
+ if (errCnt != 0) {
+ LOGI("======== TEST FAIL ========== %x\n",errCnt);
+ } else {
+ LOGI("======== TEST PASS ========== \n");
+ }
+ // shIpc *ptr = GlobalShMemory.getIpcPtr(offset);
+ ptr->SetError(errCnt);
+ ptr->SetThreadDone();
+ pthread_exit(NULL);
+ return ((void *)NULL);
+}
+
diff --git a/cosim/bareMetalTests/plicPrioIntr/c_module.h b/cosim/bareMetalTests/plicPrioIntr/c_module.h
new file mode 100644
index 0000000..3e5bb5c
--- /dev/null
+++ b/cosim/bareMetalTests/plicPrioIntr/c_module.h
@@ -0,0 +1,18 @@
+//************************************************************************
+// Copyright 2021 Massachusetts Institute of Technology
+// SPDX short identifier: BSD-2-Clause
+//
+// File Name:
+// Program: Common Evaluation Platform (CEP)
+// Description:
+// Notes:
+//
+//************************************************************************
+#ifndef c_module_H
+#define c_module_H
+
+#include "shPthread.h"
+
+void *c_module(void *); /* thread routine */
+
+#endif
diff --git a/cosim/bareMetalTests/plicPrioIntr/riscv_wrapper.cc b/cosim/bareMetalTests/plicPrioIntr/riscv_wrapper.cc
new file mode 100644
index 0000000..1ee2183
--- /dev/null
+++ b/cosim/bareMetalTests/plicPrioIntr/riscv_wrapper.cc
@@ -0,0 +1,64 @@
+//************************************************************************
+// Copyright 2021 Massachusetts Institute of Technology
+// SPDX short identifier: BSD-2-Clause
+//
+// File Name:
+// Program: Common Evaluation Platform (CEP)
+// Description:
+// Notes:
+//
+//************************************************************************
+//
+// For bareMetal mode ONLY
+//
+#ifdef BARE_MODE
+#include "cep_adrMap.h"
+#include "cep_apis.h"
+
+#include "cepPlicTest.h"
+
+
+//#define printf(...) { return 0; }
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//int main(void)
+void thread_entry(int cid, int nc)
+{
+ //
+ int errCnt = 0;
+ int testId[4] = {0x00,0x11,0x22,0x33};
+ int coreId = read_csr(mhartid);
+ int revCheck = 1;
+ //
+ set_printf(0);
+
+ //
+ //
+ set_cur_status(CEP_RUNNING_STATUS);
+ if (!errCnt) { errCnt = cepPlicTest_prioIntrTest(coreId, 0); }
+ //
+ //
+ // Done
+ //
+ set_status(errCnt,testId[coreId]);
+ /*
+ if (errCnt) {
+ set_pass();
+ } else {
+ set_fail();
+ }
+ */
+ //
+ // Stuck here forever...
+ //
+ exit(errCnt);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/cosim/bareMetalTests/srotMemTest/c_dispatch.cc b/cosim/bareMetalTests/srotMemTest/c_dispatch.cc
index 03a8693..a874473 100644
--- a/cosim/bareMetalTests/srotMemTest/c_dispatch.cc
+++ b/cosim/bareMetalTests/srotMemTest/c_dispatch.cc
@@ -48,7 +48,7 @@ int main(int argc, char *argv[])
//
// each bit is to turn on the given core (bit0 = core0, bit1=core1, etc..)
//
- long unsigned int mask = (1 << (seed&0x3));
+ long unsigned int mask = 0xf; // (1 << (seed&0x3));
//
// Set the active CPU mask before spawn the threads...
//
diff --git a/cosim/bareMetalTests/srotMemTest/riscv_wrapper.cc b/cosim/bareMetalTests/srotMemTest/riscv_wrapper.cc
index b98382c..b4dde50 100644
--- a/cosim/bareMetalTests/srotMemTest/riscv_wrapper.cc
+++ b/cosim/bareMetalTests/srotMemTest/riscv_wrapper.cc
@@ -50,13 +50,14 @@ void thread_entry(int cid, int nc)
//
//
//
+ // each core use 1/4
for (int i=0;i<2;i++) {
if (i == 0) {
- adrWidth = 8; // 256 locations
- mem_base = srot_base_addr + SROT_KEYRAM_ADDR;
+ adrWidth = 8-2; // 256 locations/4
+ mem_base = srot_base_addr + SROT_KEYRAM_ADDR + (coreId << 6) ;
} else {
- adrWidth = 6; // 32 locations
- mem_base = srot_base_addr + SROT_KEYINDEXRAM_ADDR;
+ adrWidth = 6-2; // 64 locations/4
+ mem_base = srot_base_addr + SROT_KEYINDEXRAM_ADDR + (coreId << 4);
}
if (!errCnt) { errCnt = cepMemTest_runTest(coreId,mem_base,adrWidth,dataWidth ,seed, verbose, full); }
}
diff --git a/cosim/bfmTests/Makefile b/cosim/bfmTests/Makefile
index 9c97b07..a37e1e6 100644
--- a/cosim/bfmTests/Makefile
+++ b/cosim/bfmTests/Makefile
@@ -64,6 +64,8 @@ BFM_TEST_LIST = \
srotKeyTest \
scratchpadTest \
srotErrorTest \
+ multiThread \
+ plicPrioIntr \
diff --git a/cosim/bfmTests/fragmentors/c_module.cc b/cosim/bfmTests/fragmentors/c_module.cc
index 577e5d6..9eeff84 100644
--- a/cosim/bfmTests/fragmentors/c_module.cc
+++ b/cosim/bfmTests/fragmentors/c_module.cc
@@ -92,7 +92,9 @@ void *c_module(void *arg) {
case 2 :
// MaskRom
- errCnt += cepFragmentorTest_verifyMaskRom(cpuId, bootrom_base_addr, "../../drivers/bootbare/bootbare.bin", 8, seed,verbose);
+ // errCnt += cepFragmentorTest_verifyMaskRom(cpuId, bootrom_base_addr, "../../drivers/bootbare/bootbare.bin", 8, seed,verbose);
+ errCnt += cepFragmentorTest_verifyMaskRom(cpuId, bootrom_base_addr, "../../../hdl_cores/freedom/builds/vc707-u500devkit/sdboot_fpga_sim.bin", 8, seed,verbose);
+
// MD5
errCnt += cepFragmentorTest_baseTest(cpuId, md5_base_addr + 0x0100, 16, 8, (uint64_t) 0, seed, verbose); // HOLE!!
errCnt += cepFragmentorTest_baseTest(cpuId, md5_base_addr + 0x10, 2, 2, (uint64_t)-1, seed, verbose);
diff --git a/cosim/bfmTests/multiThread/Makefile b/cosim/bfmTests/multiThread/Makefile
new file mode 100644
index 0000000..bf3e9c7
--- /dev/null
+++ b/cosim/bfmTests/multiThread/Makefile
@@ -0,0 +1,31 @@
+#//************************************************************************
+#// Copyright 2021 Massachusetts Institute of Technology
+#// SPDX License Identifier: MIT
+#//
+#// File Name:
+#// Program: Common Evaluation Platform (CEP)
+#// Description:
+#// Notes:
+#//
+#//************************************************************************
+#
+#
+#
+COSIM_NAME = $(shell cd ../..; basename `pwd`)
+DUT_TOP_DIR = $(shell cd ../../..; pwd | ./${COSIM_NAME}/bin/strip_net.pl )
+BLD_DIR = $(shell cd ..; pwd | ../bin/strip_net.pl )
+TEST_SUITE = $(shell basename ${BLD_DIR})
+TEST_DIR = $(shell cd .; pwd | ../../bin/strip_net.pl )
+TEST_NAME = $(shell basename `pwd`)
+SIM_DIR = ${DUT_TOP_DIR}/${COSIM_NAME}
+
+#
+# Top target!!!
+#
+all: .vrun_flag
+
+#
+# override anything here before calling the common file
+#
+include ${BLD_DIR}/common.make
+
diff --git a/cosim/bfmTests/multiThread/c_dispatch.cc b/cosim/bfmTests/multiThread/c_dispatch.cc
new file mode 100644
index 0000000..e42b9a9
--- /dev/null
+++ b/cosim/bfmTests/multiThread/c_dispatch.cc
@@ -0,0 +1,112 @@
+//************************************************************************
+// Copyright 2021 Massachusetts Institute of Technology
+// SPDX License Identifier: MIT
+//
+// File Name:
+// Program: Common Evaluation Platform (CEP)
+// Description:
+// Notes:
+//
+//************************************************************************
+#include
+#include "v2c_cmds.h"
+#include "access.h"
+#include "c_dispatch.h"
+#include "c_module.h"
+#include "cep_apis.h"
+#include "cep_adrMap.h"
+#include "cepregression.h"
+#include "simPio.h"
+/*
+ * main
+ */
+int main(int argc, char *argv[])
+{
+
+ /* ===================================== */
+ /* SETUP SECTION FOR SIMULATION */
+ /* ===================================== */
+ unsigned long seed;
+ sscanf(argv[1],"0x%x",&seed);
+ printf("Seed = 0x%x\n",seed);
+ int errCnt = 0;
+ int verbose = 0x1f;
+
+ /* ===================================== */
+ /* spawn all the paralle threads */
+ /* ===================================== */
+ int activeSlot=0; // only 1 board
+ //
+ // ============================
+ // fork all the tests here
+ // ============================
+ //
+ shPthread thr;
+ //
+ // max number of cores not include the system thread
+ //
+ int maxHost = MAX_CORES; // number of cores/threads
+ //
+ // each bit is to turn on the given core (bit0 = core0, bit1=core1, etc..)
+ //
+ long unsigned int mask = 0xf;
+ //
+ // Set the active CPU mask before spawn the threads...
+ //
+ thr.SetActiveMask(mask);
+ //
+ // c_module is the threead to run
+ //
+ initConfig();
+ for (int i=0;i
+#include "random48.h"
+
+#include "CEP.h"
+#include "cep_apis.h"
+#include "simdiag_global.h"
+#include "cepMultiThread.h"
+
+//
+void *c_module(void *arg) {
+
+
+ // ======================================
+ // Set up
+ // ======================================
+ pthread_parm_t *tParm = (pthread_parm_t *)arg;
+ int errCnt = 0;
+ int slotId = tParm->slotId;
+ int cpuId = tParm->cpuId;
+ int verbose = tParm->verbose;
+ Int32U seed = tParm->seed;
+ int restart = tParm->restart;
+ int offset = GET_OFFSET(slotId,cpuId);
+ GlobalShMemory.getSlotCpuId(offset,&slotId,&cpuId);
+ //printf("offset=%x seed=%x verbose=%x GlobalShMemory=%x\n",offset,seed, verbose,(unsigned long) &GlobalShMemory);
+ // notify I am Alive!!!
+ shIpc *ptr = GlobalShMemory.getIpcPtr(offset);
+ ptr->SetAliveStatus();
+ sleep(1);
+
+ // ======================================
+ // Test is Here
+ // ======================================
+ simPio pio;
+ pio.MaybeAThread(); // chec
+ pio.EnableShIpc(1);
+ pio.SetVerbose(verbose);
+
+ //
+ // ======================================
+ // Test starts here
+ // ======================================
+ // MUST
+ // wait until Calibration is done..
+ int calibDone = calibrate_ddr3(50);
+ //pio.RunClk(1000);
+ //
+ int coreMask = seed; // seed is used as cpuActiveMask from c_displatch
+ int cryptoMask = ((1<<10)-1) & ~(1 << RSA_BASE_K);
+ //
+ int maxTest = 10;
+ int maxLoop = 2;
+ uint64_t testLockBuf = 0x90000000;
+
+ if (!errCnt) {
+ errCnt += cepMultiThread_setup(cpuId, testLockBuf, maxTest, coreMask, verbose) ;
+ }
+ // LOGI(" errCnt=%d\n",errCnt);
+ if (!errCnt) { errCnt += cepMultiThread_runThr(cpuId, testLockBuf, cryptoMask, maxTest, maxLoop,seed, verbose); }
+ //
+ //
+ pio.RunClk(100);
+ //
+ // ======================================
+ // Exit
+ // ======================================
+cleanup:
+ if (errCnt != 0) {
+ LOGI("======== TEST FAIL ========== %x\n",errCnt);
+ } else {
+ LOGI("======== TEST PASS ========== \n");
+ }
+ // shIpc *ptr = GlobalShMemory.getIpcPtr(offset);
+ ptr->SetError(errCnt);
+ ptr->SetThreadDone();
+ pthread_exit(NULL);
+ return ((void *)NULL);
+}
+
diff --git a/cosim/drivers/bootbare/common.h b/cosim/bfmTests/multiThread/c_module.h
similarity index 70%
rename from cosim/drivers/bootbare/common.h
rename to cosim/bfmTests/multiThread/c_module.h
index e45552b..c4e93df 100644
--- a/cosim/drivers/bootbare/common.h
+++ b/cosim/bfmTests/multiThread/c_module.h
@@ -1,5 +1,6 @@
//************************************************************************
// Copyright 2021 Massachusetts Institute of Technology
+// SPDX License Identifier: MIT
//
// File Name:
// Program: Common Evaluation Platform (CEP)
@@ -7,13 +8,11 @@
// Notes:
//
//************************************************************************
+#ifndef c_module_H
+#define c_module_H
-#ifndef _SDBOOT_COMMON_H
-#define _SDBOOT_COMMON_H
-
-#ifndef PAYLOAD_DEST
- #define PAYLOAD_DEST MEMORY_MEM_ADDR
-#endif
+#include "shPthread.h"
+void *c_module(void *); /* thread routine */
#endif
diff --git a/cosim/bfmTests/multiThread/imp.h b/cosim/bfmTests/multiThread/imp.h
new file mode 100644
index 0000000..e3509dd
--- /dev/null
+++ b/cosim/bfmTests/multiThread/imp.h
@@ -0,0 +1,49 @@
+/***********************************************
+ DO NOT MODIFY THE CONTENTS OF THIS FILE.
+ This header file has been auto-generated by xmelab.
+ This should be included in user'c C file to
+ facilitate the calling of imported tasks and functions.
+************************************************/
+
+#include "svdpi.h"
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+typedef struct {
+ int _a0;
+ int _a1;
+ int _a2;
+ unsigned int _a3;
+ unsigned int _a4;
+ unsigned int _a5;
+ unsigned long long _a6;
+ unsigned long long _a7[32];
+ char _a8[256];
+ char _a9[256];
+ } v2c_top__mailBox;
+
+
+typedef struct {
+ int _a0;
+ int _a1;
+ int _a2;
+ unsigned int _a3;
+ unsigned int _a4;
+ unsigned int _a5;
+ unsigned long long _a6;
+ unsigned long long _a7[32];
+ char _a8[256];
+ char _a9[256];
+ } cep_driver__mailBox;
+
+
+extern void send_v2c_mail (int _a1, int _a2, v2c_top__mailBox *_a3);
+
+extern void get_v2c_mail (int _a1, int _a2, v2c_top__mailBox *_a3);
+
+#ifdef __cplusplus
+ }
+#endif
+
diff --git a/cosim/bfmTests/plicPrioIntr/Makefile b/cosim/bfmTests/plicPrioIntr/Makefile
new file mode 100644
index 0000000..80b6fe9
--- /dev/null
+++ b/cosim/bfmTests/plicPrioIntr/Makefile
@@ -0,0 +1,31 @@
+#//************************************************************************
+#// Copyright 2021 Massachusetts Institute of Technology
+#// SPDX short identifier: BSD-2-Clause
+#//
+#// File Name:
+#// Program: Common Evaluation Platform (CEP)
+#// Description:
+#// Notes:
+#//
+#//************************************************************************
+#
+#
+#
+COSIM_NAME = $(shell cd ../..; basename `pwd`)
+DUT_TOP_DIR = $(shell cd ../../..; pwd | ./${COSIM_NAME}/bin/strip_net.pl )
+BLD_DIR = $(shell cd ..; pwd | ../bin/strip_net.pl )
+TEST_SUITE = $(shell basename ${BLD_DIR})
+TEST_DIR = $(shell cd .; pwd | ../../bin/strip_net.pl )
+TEST_NAME = $(shell basename `pwd`)
+SIM_DIR = ${DUT_TOP_DIR}/${COSIM_NAME}
+
+#
+# Top target!!!
+#
+all: .vrun_flag
+
+#
+# override anything here before calling the common file
+#
+include ${BLD_DIR}/common.make
+
diff --git a/cosim/bfmTests/plicPrioIntr/c_dispatch.cc b/cosim/bfmTests/plicPrioIntr/c_dispatch.cc
new file mode 100644
index 0000000..2f7f0f7
--- /dev/null
+++ b/cosim/bfmTests/plicPrioIntr/c_dispatch.cc
@@ -0,0 +1,107 @@
+//************************************************************************
+// Copyright 2021 Massachusetts Institute of Technology
+// SPDX short identifier: BSD-2-Clause
+//
+// File Name:
+// Program: Common Evaluation Platform (CEP)
+// Description:
+// Notes:
+//
+//************************************************************************
+#include
+#include "v2c_cmds.h"
+#include "access.h"
+#include "c_dispatch.h"
+#include "c_module.h"
+#include "cep_adrMap.h"
+#include "cep_apis.h"
+#include "simPio.h"
+/*
+ * main
+ */
+int main(int argc, char *argv[])
+{
+
+ /* ===================================== */
+ /* SETUP SECTION FOR SIMULATION */
+ /* ===================================== */
+ unsigned long seed;
+ sscanf(argv[1],"0x%x",&seed);
+ printf("Seed = 0x%x\n",seed);
+ int errCnt = 0;
+ int verbose = 0x1f;
+
+ /* ===================================== */
+ /* spawn all the paralle threads */
+ /* ===================================== */
+ int activeSlot=0; // only 1 board
+ //
+ // ============================
+ // fork all the tests here
+ // ============================
+ //
+ shPthread thr;
+ //
+ // max number of cores not include the system thread
+ //
+ int maxHost = MAX_CORES; // number of cores/threads
+ //
+ // each bit is to turn on the given core (bit0 = core0, bit1=core1, etc..)
+ //
+ long unsigned int mask = 0xf;
+ //
+ // Set the active CPU mask before spawn the threads...
+ //
+ thr.SetActiveMask(mask);
+ //
+ // c_module is the threead to run
+ //
+ for (int i=0;i
+#include "random48.h"
+
+#include "cep_adrMap.h"
+#include "cep_apis.h"
+#include "simdiag_global.h"
+#include "cepPlicTest.h"
+
+//
+void *c_module(void *arg) {
+
+
+ // ======================================
+ // Set up
+ // ======================================
+ pthread_parm_t *tParm = (pthread_parm_t *)arg;
+ int errCnt = 0;
+ int slotId = tParm->slotId;
+ int cpuId = tParm->cpuId;
+ int verbose = tParm->verbose;
+ Int32U seed = tParm->seed;
+ int restart = tParm->restart;
+ int offset = GET_OFFSET(slotId,cpuId);
+ GlobalShMemory.getSlotCpuId(offset,&slotId,&cpuId);
+ //printf("offset=%x seed=%x verbose=%x GlobalShMemory=%x\n",offset,seed, verbose,(unsigned long) &GlobalShMemory);
+ // notify I am Alive!!!
+ shIpc *ptr = GlobalShMemory.getIpcPtr(offset);
+ ptr->SetAliveStatus();
+ sleep(1);
+
+ // ======================================
+ // Test is Here
+ // ======================================
+ simPio pio;
+ pio.MaybeAThread(); // chec
+ pio.EnableShIpc(1);
+ pio.SetVerbose(verbose);
+
+ //
+ // ======================================
+ // Test starts here
+ // ======================================
+ // MUST
+ // wait until Calibration is done..
+ //int calibDone = calibrate_ddr3(50);
+ pio.RunClk(500);
+
+ //
+#if 1
+ if (!errCnt) { errCnt = cepPlicTest_prioIntrTest(cpuId,verbose); }
+#endif
+ //
+ //
+ pio.RunClk(100);
+ //
+ // ======================================
+ // Exit
+ // ======================================
+cleanup:
+ if (errCnt != 0) {
+ LOGI("======== TEST FAIL ========== %x\n",errCnt);
+ } else {
+ LOGI("======== TEST PASS ========== \n");
+ }
+ // shIpc *ptr = GlobalShMemory.getIpcPtr(offset);
+ ptr->SetError(errCnt);
+ ptr->SetThreadDone();
+ pthread_exit(NULL);
+ return ((void *)NULL);
+}
+
diff --git a/cosim/bfmTests/plicPrioIntr/c_module.h b/cosim/bfmTests/plicPrioIntr/c_module.h
new file mode 100644
index 0000000..3e5bb5c
--- /dev/null
+++ b/cosim/bfmTests/plicPrioIntr/c_module.h
@@ -0,0 +1,18 @@
+//************************************************************************
+// Copyright 2021 Massachusetts Institute of Technology
+// SPDX short identifier: BSD-2-Clause
+//
+// File Name:
+// Program: Common Evaluation Platform (CEP)
+// Description:
+// Notes:
+//
+//************************************************************************
+#ifndef c_module_H
+#define c_module_H
+
+#include "shPthread.h"
+
+void *c_module(void *); /* thread routine */
+
+#endif
diff --git a/cosim/bfmTests/regTest/c_module.cc b/cosim/bfmTests/regTest/c_module.cc
index 82a81df..6b390fd 100644
--- a/cosim/bfmTests/regTest/c_module.cc
+++ b/cosim/bfmTests/regTest/c_module.cc
@@ -91,7 +91,8 @@ void *c_module(void *arg) {
#endif
//
//
- pio.RunClk(100);
+ pio.RunClk(100);
+
//
// ======================================
// Exit
diff --git a/cosim/bfmTests/srotErrorTest/c_module.cc b/cosim/bfmTests/srotErrorTest/c_module.cc
index 736b47c..b1a68b0 100644
--- a/cosim/bfmTests/srotErrorTest/c_module.cc
+++ b/cosim/bfmTests/srotErrorTest/c_module.cc
@@ -72,7 +72,7 @@ void *c_module(void *arg) {
for (int i = 0; i < 4; i++) {
if (errCnt) break;
LOGI("======== LLKI_ErrorTest Loop #%d, ErrCnt= %d ========\n", i, errCnt);
- errCnt += cepSpiTest_runTest(cpuId,seed, verbose);
+ //errCnt += cepSpiTest_runTest(cpuId,seed, verbose);
errCnt += srot.LLKI_ErrorTest(cpuId);
}
diff --git a/cosim/bin/mkDepend.pl b/cosim/bin/mkDepend.pl
index 794a3d0..849c17c 100755
--- a/cosim/bin/mkDepend.pl
+++ b/cosim/bin/mkDepend.pl
@@ -132,11 +132,19 @@ sub parse_log_file {
@tmp = split(/[:=\t\n ]+/,$_);
for ($i=0;$i<=$#tmp;$i++) {
if (-f $tmp[$i] && !($tmp[$i] =~ /searchPaths_build/)) {
- if ($tmp[$i] =~ /\.vhd/) {
- $vhdl_list{$tmp[$i]} = 1;
+ $testName = basename($tmp[$i]);
+ # add build_dir if single !!
+ if ($testName eq $tmp[$i]) {
+ print "Adding fullpath to $tmp[$i]\n";
+ $testName = "$build_dir/$testName";
+ } else {
+ $testName = $tmp[$i];
+ }
+ if ($testName =~ /\.vhd/) {
+ $vhdl_list{$testName} = 1;
$vhdl_empty = 0;
} else {
- $vc_list{$tmp[$i]} = 1;
+ $vc_list{$testName} = 1;
$vc_empty = 0;
}
print "Got $tmp[0]\n" if $DBG;
diff --git a/cosim/cadence.make b/cosim/cadence.make
index df43393..3e6252e 100644
--- a/cosim/cadence.make
+++ b/cosim/cadence.make
@@ -17,12 +17,12 @@
export VMGR_VERSION ?= VMANAGERAGILE20.06.001
export XCELIUM_VERSION ?= XCELIUMAGILE20.09.001
-export VMGR_PATH ?= /brewhouse/cad4/x86_64/Cadence/${VMGR_VERSION}
-export XCELIUM_INSTALL ?= /brewhouse/cad4/x86_64/Cadence/${XCELIUM_VERSION}
+export VMGR_PATH = /brewhouse/cad4/x86_64/Cadence/${VMGR_VERSION}
+export XCELIUM_INSTALL = /brewhouse/cad4/x86_64/Cadence/${XCELIUM_VERSION}
-export IMC_INSTALL ?= ${VMGR_PATH}
-export MDV_XLM_HOME ?= ${XCELIUM_INSTALL}
+export IMC_INSTALL = ${VMGR_PATH}
+export MDV_XLM_HOME = ${XCELIUM_INSTALL}
#
# Add to PATH if they are not there yet
#
diff --git a/cosim/cadence_cov.ccf b/cosim/cadence_cov.ccf
index b25d0ee..d74fff3 100644
--- a/cosim/cadence_cov.ccf
+++ b/cosim/cadence_cov.ccf
@@ -1,18 +1,53 @@
-select_functional -imm_asrt_class_package
-set_covergroup -new_instance_reporting
-set_expr_coverable_statements -procassign -contassign
-set_expr_coverable_operators -relational -conditional -logical_not
-set_refinement_resilience
-#
-# need to see all nets in toggle, tony D.
-#set_toggle_portsonly
-#
-set_libcell_scoring
-#
-# From Amit 04/12/2021
-#
-set_glitch_strobe 166 ps
-set_toggle_strobe 166 ps
-set_toggle_scoring -regeot
-#
-select_coverage -block -expr -toggle -fsm -instance cep_tb.fpga.topDesign.topMod...
+#
+# From Cadence 05/11/21
+#
+
+# enable code and FSM coverage
+select_coverage -block -expr -toggle -fsm -instance cep_tb.fpga.topDesign.topMod...
+
+# remove instances in the hierarchy without any coverage
+deselect_coverage -remove_empty_instances
+
+# Specific options for coverage merging, refinements
+set_code_fine_grained_merging
+set_refinement_resilience
+
+# Specific options for finer granularity/control in coverage scoring
+set_libcell_scoring -enable_vy
+set_assign_scoring
+set_branch_scoring
+set_com -log
+set_glitch_strobe 166 ps
+
+# expression specific options
+set_expr_scoring -control -struct
+set_expr_coverable_operators -bitwise -relational -conditional -reduction -logical_not
+set_expr_coverable_statements -all
+
+
+# toggle specific options
+#set_toggle_portsonly # limit to ports only
+#set_toggle_smart_refinement # enable toggle smart refinement / exclusions
+set_toggle_scoring -sv_mda
+#set_toggle_scoring -sv_mda 16 # reduces most of warnings but toggle coverage space large
+#set_toggle_scoring -sv_mda 18 # covers all warnings but toggle coverage space very large
+set_toggle_scoring -sv_enum enable_mda
+set_toggle_scoring -sv_enum -sv_struct_with_enum
+set_toggle_strobe 166 ps
+set_toggle_scoring -regeot
+
+# FSM specific options
+set_fsm_scoring -hold_transition
+set_fsm_reset_scoring
+
+# functional coverage
+select_functional -imm_asrt_class_package
+set_covergroup -per_instance_default_one
+
+# Optimizations
+#set_optimize -vlog_prune_on
+set_optimize -top_expr_non_scorable
+set_optimize -prune_covergroup
+
+#**************************
+
diff --git a/cosim/cep_buildChips.make b/cosim/cep_buildChips.make
index 36fe12d..4075ef0 100644
--- a/cosim/cep_buildChips.make
+++ b/cosim/cep_buildChips.make
@@ -92,9 +92,9 @@ RISCV_BARE_LDFLAG += -static -nostdlib -nostartfiles -lgcc -DBARE_MODE
RISCV_BARE_LDFILE = ${BARE_SRC_DIR}/link.ld
RISCV_BARE_CRTFILE = ${BARE_SRC_DIR}/crt.S
-RISCV_BARE_SOURCE_LIST = ${SIM_DIR}/drivers/cep_tests
-RISC_BARE_OBJECTS_LIST := $(subst .cc,.bobj,${RISCV_BARE_SOURCE_LIST})
-RISC_BARE_OBJECTS := $(foreach t,${RISC_BARE_OBJECTS_LIST}, ${BARE_OBJ_DIR}/${t})
+# .C-style ONLY
+RISC_BARE_SRC_LIST := $(subst .c,.bobj,$(notdir $(wildcard ${BARE_SRC_DIR}/*.c)))
+RISC_BARE_OBJECTS := $(foreach t,${RISC_BARE_SRC_LIST}, ${BARE_OBJ_DIR}/${t})
CEP_SRC_FILES = $(wildcard ${SIM_DIR}/drivers/cep_tests/*.cc)
CEP_BARE_OBJECTS := $(subst .cc,.bobj,${CEP_SRC_FILES})
@@ -102,10 +102,14 @@ CEP_BARE_OBJECTS := $(subst .cc,.bobj,${CEP_SRC_FILES})
#
# Bare metal booloader
#
-RICSV_BARE_BOOT_DIR := ${SIM_DIR}/drivers/bootbare
-RISCV_BARE_BOOT_ROM := bootbare.hex
+#RICSV_BARE_BOOT_DIR := ${SIM_DIR}/drivers/bootbare
+#RISCV_BARE_BOOT_ROM := bootbare.hex
-%.hex: %.c
+# use the one build during verilog generation
+RICSV_BARE_BOOT_DIR := ${DUT_TOP_DIR}/hdl_cores/freedom/builds/vc707-u500devkit
+RISCV_BARE_BOOT_ROM := sdboot_fpga_sim.hex
+
+%.hex: ${INC_DIR}/cep_adrMap.h %.c
(cd ${RICSV_BARE_BOOT_DIR}; make clean; make;)
CEP_DIAG_FILES = $(wildcard ${SIM_DIR}/drivers/diag/*.cc)
@@ -119,12 +123,10 @@ CEP_BARE_DIAG_OBJECTS := $(subst .cc,.bobj,${CEP_DIAG_FILES})
${BARE_OBJ_DIR}/crt.bobj: ${RISCV_BARE_CRTFILE}
$(RISCV_GCC) $(RISCV_BARE_CFLAG) -c $< -o $@
-${BARE_OBJ_DIR}/syscalls.bobj: ${BARE_OBJ_DIR}/syscalls.c
- $(RISCV_GCC) $(RISCV_BARE_CFLAG) -c $< -o $@
-
-${BARE_OBJ_DIR}/bare_malloc.bobj: ${BARE_OBJ_DIR}/bare_malloc.c
+${BARE_OBJ_DIR}/%.bobj: ${BARE_OBJ_DIR}/%.c
$(RISCV_GCC) $(RISCV_BARE_CFLAG) -c $< -o $@
+
riscv_wrapper.bobj: riscv_wrapper.cc
$(RISCV_GCC) $(RISCV_BARE_CFLAG) -c $< -o $@
@@ -148,7 +150,7 @@ riscv_wrapper.elf: riscv_virt.S riscv_wrapper.cc ${RISCV_VIRT_CFILES}
${RISCV_HEXDUMP} -C riscv_wrapper.elf > riscv_wrapper.hex
${BIN_DIR}/createPassFail.pl riscv_wrapper.dump PassFail.hex
else
-riscv_wrapper.elf: riscv_wrapper.bobj ${BARE_OBJ_DIR}/crt.bobj ${BARE_OBJ_DIR}/syscalls.bobj ${BARE_OBJ_DIR}/bare_malloc.bobj ${CEP_BARE_OBJECTS} ${CEP_BARE_DIAG_OBJECTS}
+riscv_wrapper.elf: riscv_wrapper.bobj ${BARE_OBJ_DIR}/crt.bobj ${RISC_BARE_OBJECTS} ${CEP_BARE_OBJECTS} ${CEP_BARE_DIAG_OBJECTS}
$(RISCV_GCC) -T ${RISCV_BARE_LDFILE} ${RISCV_BARE_LDFLAG} $^ -o $@
${RISCV_OBJDUMP} -S -C -d -l -x riscv_wrapper.elf > riscv_wrapper.dump
${RISCV_HEXDUMP} -C riscv_wrapper.elf > riscv_wrapper.hex
diff --git a/cosim/common.make b/cosim/common.make
index 54b284c..125e443 100644
--- a/cosim/common.make
+++ b/cosim/common.make
@@ -130,6 +130,7 @@ CHECK_FLAG = ${BLD_DIR}/.is_checked
CUR_CONFIG = .CONFIG_${DUT_VENDOR}_${DUT_SIM_MODE}
SIM_DEPEND_TARGET = .${WORK_NAME}_dependList
+
#
# -------------------------------------------
# Some derived switches
@@ -186,6 +187,10 @@ DUT_VLOG_ARGS += +cover=sbceft +define+COVERAGE
DUT_VOPT_ARGS += +cover=sbceft
endif
+ifeq (${NOWAVE},1)
+DUT_VLOG_ARGS += +define+NOWAVE
+endif
+
# Use our gcc instead of builtin form questa
DUT_VSIM_ARGS += -cpppath ${GCC}
diff --git a/cosim/drivers/bootbare/Makefile b/cosim/drivers/bootbare/Makefile
deleted file mode 100644
index 8185ff7..0000000
--- a/cosim/drivers/bootbare/Makefile
+++ /dev/null
@@ -1,49 +0,0 @@
-#//************************************************************************
-#// Copyright 2021 Massachusetts Institute of Technology
-#//
-#// File Name:
-#// Program: Common Evaluation Platform (CEP)
-#// Description:
-#// Notes:
-#//
-#//************************************************************************
-
-# RISCV environment variable must be set
-
-CC=$(RISCV)/bin/riscv64-unknown-elf-gcc
-OBJCOPY=$(RISCV)/bin/riscv64-unknown-elf-objcopy
-OBJDMP=$(RISCV)/bin/riscv64-unknown-elf-objdump
-CFLAGS=-march=rv64imac -mcmodel=medany -O2 -std=gnu11 -Wall -nostartfiles
-CFLAGS+= -fno-common -g -DENTROPY=0 -mabi=lp64 -DNONSMP_HART=0
-CFLAGS+= -I ./include -I.
-LFLAGS=-static -nostdlib -L ./linker -T sdboot.elf.lds
-
-export CONFIG_PROJECT := sifive.freedom.unleashed
-export CONFIG := DevKitU500FPGADesign_WithDevKit50MHz
-
-#
-# OR can be passed in from top
-#
-#BUILD_DIR := /home/aduong/CEP/CEP-master/hdl_cores/freedom/builds/vc707-u500devkit
-BUILD_DIR := ../../../hdl_cores/freedom/builds/vc707-u500devkit
-
-dts := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).dts
-dtb := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).dtb
-clk := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).tl_clock.h
-
-all: head.S bootbare.c
- $(CC) $(CFLAGS) -include $(clk) -DDEVICE_TREE='"$(dtb)"' $(LFLAGS) -o bootbare.elf head.S bootbare.c
- $(OBJCOPY) -O binary bootbare.elf bootbare.bin
- ${OBJDMP} -S bootbare.elf > bootbare.dump
- od -t x4 -An -w4 -v bootbare.bin > bootbare.hex
-
-$(clk): $(dts)
- awk '/tlclk {/ && !f{f=1; next}; f && match($$0, /^.*clock-frequency.*<(.*)>.*/, arr) { print "#define TL_CLK " arr[1] "UL"}' $< > $@.tmp
- mv $@.tmp $@
-
-$(dtb): $(dts)
- dtc -I dts -O dtb -o $@ $<
-
-.PHONY: clean
-clean::
- rm -rf *.bin *.hex *.elf
diff --git a/cosim/drivers/bootbare/bootbare.c b/cosim/drivers/bootbare/bootbare.c
deleted file mode 100644
index 581aeba..0000000
--- a/cosim/drivers/bootbare/bootbare.c
+++ /dev/null
@@ -1,55 +0,0 @@
-//************************************************************************
-// Copyright 2021 Massachusetts Institute of Technology
-// SPDX License Identifier: MIT
-//
-// File Name:
-// Program: Common Evaluation Platform (CEP)
-// Description:
-// Notes:
-//
-//************************************************************************
-
-// See LICENSE for license details.
-#include
-
-#include
-
-#include "common.h"
-
-#define DEBUG
-//#include "kprintf.h"
-
-#define MAX_CORES 8
-
-#define PAYLOAD_SIZE (26 << 11)
-
-#ifndef TL_CLK
-#error Must define TL_CLK
-#endif
-
-#define F_CLK TL_CLK
-
-
-int main(void)
-{
- /*
- REG32(uart, UART_REG_TXCTRL) = UART_TXEN;
-
- print_greeting();
- kputs("INIT");
- sd_poweron();
- if (sd_cmd0() ||
- sd_cmd8() ||
- sd_acmd41() ||
- sd_cmd58() ||
- sd_cmd16() ||
- copy()) {
- kputs("ERROR");
- return 1;
- }
-
- kputs("BOOT");
- */
- __asm__ __volatile__ ("fence.i" : : : "memory");
- return 0;
-}
diff --git a/cosim/drivers/bootbare/head.S b/cosim/drivers/bootbare/head.S
deleted file mode 100644
index 24c92aa..0000000
--- a/cosim/drivers/bootbare/head.S
+++ /dev/null
@@ -1,31 +0,0 @@
-#//************************************************************************
-#// Copyright 2021 Massachusetts Institute of Technology
-#//
-#// File Name:
-#// Program: Common Evaluation Platform (CEP)
-#// Description:
-#// Notes:
-#//
-#//************************************************************************
-
-// See LICENSE for license details.
-#include
-#include
-#include "common.h"
-
- .section .text.init
- .option norvc
- .globl _prog_start
-_prog_start:
- smp_pause(s1, s2)
- li sp, (PAYLOAD_DEST + 0x7fff000)
- call main
- smp_resume(s1, s2)
- csrr a0, mhartid
- la a1, dtb
- li s1, PAYLOAD_DEST
- jr s1
-
- .section .rodata
-dtb:
- .incbin DEVICE_TREE
diff --git a/cosim/drivers/bootbare/include/bits.h b/cosim/drivers/bootbare/include/bits.h
deleted file mode 100644
index bfe656f..0000000
--- a/cosim/drivers/bootbare/include/bits.h
+++ /dev/null
@@ -1,36 +0,0 @@
-// See LICENSE for license details.
-#ifndef _RISCV_BITS_H
-#define _RISCV_BITS_H
-
-#define likely(x) __builtin_expect((x), 1)
-#define unlikely(x) __builtin_expect((x), 0)
-
-#define ROUNDUP(a, b) ((((a)-1)/(b)+1)*(b))
-#define ROUNDDOWN(a, b) ((a)/(b)*(b))
-
-#define MAX(a, b) ((a) > (b) ? (a) : (b))
-#define MIN(a, b) ((a) < (b) ? (a) : (b))
-#define CLAMP(a, lo, hi) MIN(MAX(a, lo), hi)
-
-#define EXTRACT_FIELD(val, which) (((val) & (which)) / ((which) & ~((which)-1)))
-#define INSERT_FIELD(val, which, fieldval) (((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1))))
-
-#define STR(x) XSTR(x)
-#define XSTR(x) #x
-
-#if __riscv_xlen == 64
-# define SLL32 sllw
-# define STORE sd
-# define LOAD ld
-# define LWU lwu
-# define LOG_REGBYTES 3
-#else
-# define SLL32 sll
-# define STORE sw
-# define LOAD lw
-# define LWU lw
-# define LOG_REGBYTES 2
-#endif
-#define REGBYTES (1 << LOG_REGBYTES)
-
-#endif
diff --git a/cosim/drivers/bootbare/include/const.h b/cosim/drivers/bootbare/include/const.h
deleted file mode 100644
index 8dcffbb..0000000
--- a/cosim/drivers/bootbare/include/const.h
+++ /dev/null
@@ -1,18 +0,0 @@
-// See LICENSE for license details.
-/* Derived from */
-
-#ifndef _SIFIVE_CONST_H
-#define _SIFIVE_CONST_H
-
-#ifdef __ASSEMBLER__
-#define _AC(X,Y) X
-#define _AT(T,X) X
-#else
-#define _AC(X,Y) (X##Y)
-#define _AT(T,X) ((T)(X))
-#endif /* !__ASSEMBLER__*/
-
-#define _BITUL(x) (_AC(1,UL) << (x))
-#define _BITULL(x) (_AC(1,ULL) << (x))
-
-#endif /* _SIFIVE_CONST_H */
diff --git a/cosim/drivers/bootbare/include/devices/clint.h b/cosim/drivers/bootbare/include/devices/clint.h
deleted file mode 100644
index c2b05ba..0000000
--- a/cosim/drivers/bootbare/include/devices/clint.h
+++ /dev/null
@@ -1,14 +0,0 @@
-// See LICENSE for license details.
-
-#ifndef _SIFIVE_CLINT_H
-#define _SIFIVE_CLINT_H
-
-
-#define CLINT_MSIP 0x0000
-#define CLINT_MSIP_size 0x4
-#define CLINT_MTIMECMP 0x4000
-#define CLINT_MTIMECMP_size 0x8
-#define CLINT_MTIME 0xBFF8
-#define CLINT_MTIME_size 0x8
-
-#endif /* _SIFIVE_CLINT_H */
diff --git a/cosim/drivers/bootbare/include/devices/gpio.h b/cosim/drivers/bootbare/include/devices/gpio.h
deleted file mode 100644
index f7f0acb..0000000
--- a/cosim/drivers/bootbare/include/devices/gpio.h
+++ /dev/null
@@ -1,24 +0,0 @@
-// See LICENSE for license details.
-
-#ifndef _SIFIVE_GPIO_H
-#define _SIFIVE_GPIO_H
-
-#define GPIO_INPUT_VAL (0x00)
-#define GPIO_INPUT_EN (0x04)
-#define GPIO_OUTPUT_EN (0x08)
-#define GPIO_OUTPUT_VAL (0x0C)
-#define GPIO_PULLUP_EN (0x10)
-#define GPIO_DRIVE (0x14)
-#define GPIO_RISE_IE (0x18)
-#define GPIO_RISE_IP (0x1C)
-#define GPIO_FALL_IE (0x20)
-#define GPIO_FALL_IP (0x24)
-#define GPIO_HIGH_IE (0x28)
-#define GPIO_HIGH_IP (0x2C)
-#define GPIO_LOW_IE (0x30)
-#define GPIO_LOW_IP (0x34)
-#define GPIO_IOF_EN (0x38)
-#define GPIO_IOF_SEL (0x3C)
-#define GPIO_OUTPUT_XOR (0x40)
-
-#endif /* _SIFIVE_GPIO_H */
diff --git a/cosim/drivers/bootbare/include/devices/plic.h b/cosim/drivers/bootbare/include/devices/plic.h
deleted file mode 100644
index 4d5b2d8..0000000
--- a/cosim/drivers/bootbare/include/devices/plic.h
+++ /dev/null
@@ -1,31 +0,0 @@
-// See LICENSE for license details.
-
-#ifndef PLIC_H
-#define PLIC_H
-
-#include
-
-// 32 bits per source
-#define PLIC_PRIORITY_OFFSET _AC(0x0000,UL)
-#define PLIC_PRIORITY_SHIFT_PER_SOURCE 2
-// 1 bit per source (1 address)
-#define PLIC_PENDING_OFFSET _AC(0x1000,UL)
-#define PLIC_PENDING_SHIFT_PER_SOURCE 0
-
-//0x80 per target
-#define PLIC_ENABLE_OFFSET _AC(0x2000,UL)
-#define PLIC_ENABLE_SHIFT_PER_TARGET 7
-
-
-#define PLIC_THRESHOLD_OFFSET _AC(0x200000,UL)
-#define PLIC_CLAIM_OFFSET _AC(0x200004,UL)
-#define PLIC_THRESHOLD_SHIFT_PER_TARGET 12
-#define PLIC_CLAIM_SHIFT_PER_TARGET 12
-
-#define PLIC_MAX_SOURCE 1023
-#define PLIC_SOURCE_MASK 0x3FF
-
-#define PLIC_MAX_TARGET 15871
-#define PLIC_TARGET_MASK 0x3FFF
-
-#endif /* PLIC_H */
diff --git a/cosim/drivers/bootbare/include/devices/spi.h b/cosim/drivers/bootbare/include/devices/spi.h
deleted file mode 100644
index 7118572..0000000
--- a/cosim/drivers/bootbare/include/devices/spi.h
+++ /dev/null
@@ -1,79 +0,0 @@
-// See LICENSE for license details.
-
-#ifndef _SIFIVE_SPI_H
-#define _SIFIVE_SPI_H
-
-/* Register offsets */
-
-#define SPI_REG_SCKDIV 0x00
-#define SPI_REG_SCKMODE 0x04
-#define SPI_REG_CSID 0x10
-#define SPI_REG_CSDEF 0x14
-#define SPI_REG_CSMODE 0x18
-
-#define SPI_REG_DCSSCK 0x28
-#define SPI_REG_DSCKCS 0x2a
-#define SPI_REG_DINTERCS 0x2c
-#define SPI_REG_DINTERXFR 0x2e
-
-#define SPI_REG_FMT 0x40
-#define SPI_REG_TXFIFO 0x48
-#define SPI_REG_RXFIFO 0x4c
-#define SPI_REG_TXCTRL 0x50
-#define SPI_REG_RXCTRL 0x54
-
-#define SPI_REG_FCTRL 0x60
-#define SPI_REG_FFMT 0x64
-
-#define SPI_REG_IE 0x70
-#define SPI_REG_IP 0x74
-
-/* Fields */
-
-#define SPI_SCK_POL 0x1
-#define SPI_SCK_PHA 0x2
-
-#define SPI_FMT_PROTO(x) ((x) & 0x3)
-#define SPI_FMT_ENDIAN(x) (((x) & 0x1) << 2)
-#define SPI_FMT_DIR(x) (((x) & 0x1) << 3)
-#define SPI_FMT_LEN(x) (((x) & 0xf) << 16)
-
-/* TXCTRL register */
-#define SPI_TXWM(x) ((x) & 0xffff)
-/* RXCTRL register */
-#define SPI_RXWM(x) ((x) & 0xffff)
-
-#define SPI_IP_TXWM 0x1
-#define SPI_IP_RXWM 0x2
-
-#define SPI_FCTRL_EN 0x1
-
-#define SPI_INSN_CMD_EN 0x1
-#define SPI_INSN_ADDR_LEN(x) (((x) & 0x7) << 1)
-#define SPI_INSN_PAD_CNT(x) (((x) & 0xf) << 4)
-#define SPI_INSN_CMD_PROTO(x) (((x) & 0x3) << 8)
-#define SPI_INSN_ADDR_PROTO(x) (((x) & 0x3) << 10)
-#define SPI_INSN_DATA_PROTO(x) (((x) & 0x3) << 12)
-#define SPI_INSN_CMD_CODE(x) (((x) & 0xff) << 16)
-#define SPI_INSN_PAD_CODE(x) (((x) & 0xff) << 24)
-
-#define SPI_TXFIFO_FULL (1 << 31)
-#define SPI_RXFIFO_EMPTY (1 << 31)
-
-/* Values */
-
-#define SPI_CSMODE_AUTO 0
-#define SPI_CSMODE_HOLD 2
-#define SPI_CSMODE_OFF 3
-
-#define SPI_DIR_RX 0
-#define SPI_DIR_TX 1
-
-#define SPI_PROTO_S 0
-#define SPI_PROTO_D 1
-#define SPI_PROTO_Q 2
-
-#define SPI_ENDIAN_MSB 0
-#define SPI_ENDIAN_LSB 1
-
-#endif /* _SIFIVE_SPI_H */
diff --git a/cosim/drivers/bootbare/include/devices/uart.h b/cosim/drivers/bootbare/include/devices/uart.h
deleted file mode 100644
index aecfd91..0000000
--- a/cosim/drivers/bootbare/include/devices/uart.h
+++ /dev/null
@@ -1,28 +0,0 @@
-// See LICENSE for license details.
-
-#ifndef _SIFIVE_UART_H
-#define _SIFIVE_UART_H
-
-/* Register offsets */
-#define UART_REG_TXFIFO 0x00
-#define UART_REG_RXFIFO 0x04
-#define UART_REG_TXCTRL 0x08
-#define UART_REG_RXCTRL 0x0c
-#define UART_REG_IE 0x10
-#define UART_REG_IP 0x14
-#define UART_REG_DIV 0x18
-
-/* TXCTRL register */
-#define UART_TXEN 0x1
-#define UART_TXNSTOP 0x2
-#define UART_TXWM(x) (((x) & 0xffff) << 16)
-
-/* RXCTRL register */
-#define UART_RXEN 0x1
-#define UART_RXWM(x) (((x) & 0xffff) << 16)
-
-/* IP register */
-#define UART_IP_TXWM 0x1
-#define UART_IP_RXWM 0x2
-
-#endif /* _SIFIVE_UART_H */
diff --git a/cosim/drivers/bootbare/include/platform.h b/cosim/drivers/bootbare/include/platform.h
deleted file mode 100644
index fcb1156..0000000
--- a/cosim/drivers/bootbare/include/platform.h
+++ /dev/null
@@ -1,99 +0,0 @@
-// See LICENSE for license details.
-
-#ifndef _SIFIVE_PLATFORM_H
-#define _SIFIVE_PLATFORM_H
-
-#include "const.h"
-#include "riscv_test_defaults.h"
-#include "devices/clint.h"
-#include "devices/gpio.h"
-#include "devices/plic.h"
-#include "devices/spi.h"
-#include "devices/uart.h"
-
- // Some things missing from the official encoding.h
-#if __riscv_xlen == 32
- #define MCAUSE_INT 0x80000000UL
- #define MCAUSE_CAUSE 0x7FFFFFFFUL
-#else
- #define MCAUSE_INT 0x8000000000000000UL
- #define MCAUSE_CAUSE 0x7FFFFFFFFFFFFFFFUL
-#endif
-
-/****************************************************************************
- * Platform definitions
- *****************************************************************************/
-
-// CPU info
-#define NUM_CORES 1
-#define GLOBAL_INT_SIZE 15
-#define GLOBAL_INT_MAX_PRIORITY 7
-
-// Memory map
-#define AXI_PCIE_HOST_1_00_A_CTRL_ADDR _AC(0x50000000,UL)
-#define AXI_PCIE_HOST_1_00_A_CTRL_SIZE _AC(0x4000000,UL)
-#define CLINT_CTRL_ADDR _AC(0x2000000,UL)
-#define CLINT_CTRL_SIZE _AC(0x10000,UL)
-#define DEBUG_CTRL_ADDR _AC(0x0,UL)
-#define DEBUG_CTRL_SIZE _AC(0x1000,UL)
-#define ERROR_MEM_ADDR _AC(0x3000,UL)
-#define ERROR_MEM_SIZE _AC(0x1000,UL)
-#define GPIO_CTRL_ADDR _AC(0x64002000,UL)
-#define GPIO_CTRL_SIZE _AC(0x1000,UL)
-#define MASKROM_MEM_ADDR _AC(0x10000,UL)
-#define MASKROM_MEM_SIZE _AC(0x4000,UL)
-#define MEMORY_MEM_ADDR _AC(0x80000000,UL)
-#define MEMORY_MEM_SIZE _AC(0x40000000,UL)
-#define PLIC_CTRL_ADDR _AC(0xc000000,UL)
-#define PLIC_CTRL_SIZE _AC(0x4000000,UL)
-#define SPI_CTRL_ADDR _AC(0x64001000,UL)
-#define SPI_CTRL_SIZE _AC(0x1000,UL)
-#define TEST_CTRL_ADDR _AC(0x4000,UL)
-#define TEST_CTRL_SIZE _AC(0x1000,UL)
-#define UART_CTRL_ADDR _AC(0x64000000,UL)
-#define UART_CTRL_SIZE _AC(0x1000,UL)
-
-// IOF masks
-
-
-// Interrupt numbers
-#define UART_INT_BASE 1
-#define SPI_INT_BASE 2
-#define GPIO_INT_BASE 3
-#define AXI_PCIE_HOST_1_00_A_INT_BASE 7
-
-// Helper functions
-#define _REG64(p, i) (*(volatile uint64_t *)((p) + (i)))
-#define _REG32(p, i) (*(volatile uint32_t *)((p) + (i)))
-#define _REG16(p, i) (*(volatile uint16_t *)((p) + (i)))
-// Bulk set bits in `reg` to either 0 or 1.
-// E.g. SET_BITS(MY_REG, 0x00000007, 0) would generate MY_REG &= ~0x7
-// E.g. SET_BITS(MY_REG, 0x00000007, 1) would generate MY_REG |= 0x7
-#define SET_BITS(reg, mask, value) if ((value) == 0) { (reg) &= ~(mask); } else { (reg) |= (mask); }
-#define AXI_PCIE_HOST_1_00_A_REG(offset) _REG32(AXI_PCIE_HOST_1_00_A_CTRL_ADDR, offset)
-#define CLINT_REG(offset) _REG32(CLINT_CTRL_ADDR, offset)
-#define DEBUG_REG(offset) _REG32(DEBUG_CTRL_ADDR, offset)
-#define ERROR_REG(offset) _REG32(ERROR_CTRL_ADDR, offset)
-#define GPIO_REG(offset) _REG32(GPIO_CTRL_ADDR, offset)
-#define MASKROM_REG(offset) _REG32(MASKROM_CTRL_ADDR, offset)
-#define MEMORY_REG(offset) _REG32(MEMORY_CTRL_ADDR, offset)
-#define PLIC_REG(offset) _REG32(PLIC_CTRL_ADDR, offset)
-#define SPI_REG(offset) _REG32(SPI_CTRL_ADDR, offset)
-#define TEST_REG(offset) _REG32(TEST_CTRL_ADDR, offset)
-#define UART_REG(offset) _REG32(UART_CTRL_ADDR, offset)
-#define AXI_PCIE_HOST_1_00_A_REG64(offset) _REG64(AXI_PCIE_HOST_1_00_A_CTRL_ADDR, offset)
-#define CLINT_REG64(offset) _REG64(CLINT_CTRL_ADDR, offset)
-#define DEBUG_REG64(offset) _REG64(DEBUG_CTRL_ADDR, offset)
-#define ERROR_REG64(offset) _REG64(ERROR_CTRL_ADDR, offset)
-#define GPIO_REG64(offset) _REG64(GPIO_CTRL_ADDR, offset)
-#define MASKROM_REG64(offset) _REG64(MASKROM_CTRL_ADDR, offset)
-#define MEMORY_REG64(offset) _REG64(MEMORY_CTRL_ADDR, offset)
-#define PLIC_REG64(offset) _REG64(PLIC_CTRL_ADDR, offset)
-#define SPI_REG64(offset) _REG64(SPI_CTRL_ADDR, offset)
-#define TEST_REG64(offset) _REG64(TEST_CTRL_ADDR, offset)
-#define UART_REG64(offset) _REG64(UART_CTRL_ADDR, offset)
-
-// Misc
-
-
-#endif /* _SIFIVE_PLATFORM_H */
diff --git a/cosim/drivers/bootbare/include/riscv_test_defaults.h b/cosim/drivers/bootbare/include/riscv_test_defaults.h
deleted file mode 100644
index a2dea3d..0000000
--- a/cosim/drivers/bootbare/include/riscv_test_defaults.h
+++ /dev/null
@@ -1,81 +0,0 @@
-// See LICENSE for license details.
-#ifndef _RISCV_TEST_DEFAULTS_H
-#define _RISCV_TEST_DEFAULTS_H
-
-#define TESTNUM x28
-#define TESTBASE 0x4000
-
-#define RVTEST_RV32U \
- .macro init; \
- .endm
-
-#define RVTEST_RV64U \
- .macro init; \
- .endm
-
-#define RVTEST_RV32UF \
- .macro init; \
- /* If FPU exists, initialize FCSR. */ \
- csrr t0, misa; \
- andi t0, t0, 1 << ('F' - 'A'); \
- beqz t0, 1f; \
- /* Enable FPU if it exists. */ \
- li t0, MSTATUS_FS; \
- csrs mstatus, t0; \
- fssr x0; \
-1: ; \
- .endm
-
-#define RVTEST_RV64UF \
- .macro init; \
- /* If FPU exists, initialize FCSR. */ \
- csrr t0, misa; \
- andi t0, t0, 1 << ('F' - 'A'); \
- beqz t0, 1f; \
- /* Enable FPU if it exists. */ \
- li t0, MSTATUS_FS; \
- csrs mstatus, t0; \
- fssr x0; \
-1: ; \
- .endm
-
-#define RVTEST_CODE_BEGIN \
- .section .text.init; \
- .globl _prog_start; \
-_prog_start: \
- init;
-
-#define RVTEST_CODE_END \
- unimp
-
-#define RVTEST_PASS \
- fence; \
- li t0, TESTBASE; \
- li t1, 0x5555; \
- sw t1, 0(t0); \
-1: \
- j 1b;
-
-#define RVTEST_FAIL \
- li t0, TESTBASE; \
- li t1, 0x3333; \
- slli a0, a0, 16; \
- add a0, a0, t1; \
- sw a0, 0(t0); \
-1: \
- j 1b;
-
-#define EXTRA_DATA
-
-#define RVTEST_DATA_BEGIN \
- EXTRA_DATA \
- .align 4; .global begin_signature; begin_signature:
-
-#define RVTEST_DATA_END \
- _msg_init: .asciz "RUN\r\n"; \
- _msg_pass: .asciz "PASS"; \
- _msg_fail: .asciz "FAIL "; \
- _msg_end: .asciz "\r\n"; \
- .align 4; .global end_signature; end_signature:
-
-#endif /* _RISCV_TEST_DEFAULTS_H */
diff --git a/cosim/drivers/bootbare/include/sections.h b/cosim/drivers/bootbare/include/sections.h
deleted file mode 100644
index 6e1f051..0000000
--- a/cosim/drivers/bootbare/include/sections.h
+++ /dev/null
@@ -1,17 +0,0 @@
-// See LICENSE for license details.
-#ifndef _SECTIONS_H
-#define _SECTIONS_H
-
-extern unsigned char _rom[];
-extern unsigned char _rom_end[];
-
-extern unsigned char _ram[];
-extern unsigned char _ram_end[];
-
-extern unsigned char _ftext[];
-extern unsigned char _etext[];
-extern unsigned char _fbss[];
-extern unsigned char _ebss[];
-extern unsigned char _end[];
-
-#endif /* _SECTIONS_H */
diff --git a/cosim/drivers/bootbare/include/smp.h b/cosim/drivers/bootbare/include/smp.h
deleted file mode 100644
index 145ceb3..0000000
--- a/cosim/drivers/bootbare/include/smp.h
+++ /dev/null
@@ -1,142 +0,0 @@
-#ifndef SIFIVE_SMP
-#define SIFIVE_SMP
-#include "platform.h"
-
-// The maximum number of HARTs this code supports
-#ifndef MAX_HARTS
-#define MAX_HARTS 32
-#endif
-#define CLINT_END_HART_IPI CLINT_CTRL_ADDR + (MAX_HARTS*4)
-#define CLINT1_END_HART_IPI CLINT1_CTRL_ADDR + (MAX_HARTS*4)
-
-// The hart that non-SMP tests should run on
-#ifndef NONSMP_HART
-#define NONSMP_HART 0
-#endif
-
-/* If your test cannot handle multiple-threads, use this:
- * smp_disable(reg1)
- */
-#define smp_disable(reg1, reg2) \
- csrr reg1, mhartid ;\
- li reg2, NONSMP_HART ;\
- beq reg1, reg2, hart0_entry ;\
-42: ;\
- wfi ;\
- j 42b ;\
-hart0_entry:
-
-/* If your test needs to temporarily block multiple-threads, do this:
- * smp_pause(reg1, reg2)
- * ... single-threaded work ...
- * smp_resume(reg1, reg2)
- * ... multi-threaded work ...
- */
-
-#define smp_pause(reg1, reg2) \
- li reg2, 0x8 ;\
- csrw mie, reg2 ;\
- li reg1, NONSMP_HART ;\
- csrr reg2, mhartid ;\
- bne reg1, reg2, 42f
-
-#ifdef CLINT1_CTRL_ADDR
-// If a second CLINT exists, then make sure we:
-// 1) Trigger a software interrupt on all harts of both CLINTs.
-// 2) Locate your own hart's software interrupt pending register and clear it.
-// 3) Wait for all harts on both CLINTs to clear their software interrupt
-// pending register.
-// WARNING: This code makes these assumptions, which are only true for Fadu as
-// of now:
-// 1) hart0 uses CLINT0 at offset 0
-// 2) hart2 uses CLINT1 at offset 0
-// 3) hart3 uses CLINT1 at offset 1
-// 4) There are no other harts or CLINTs in the system.
-#define smp_resume(reg1, reg2) \
- /* Trigger software interrupt on CLINT0 */ \
- li reg1, CLINT_CTRL_ADDR ;\
-41: ;\
- li reg2, 1 ;\
- sw reg2, 0(reg1) ;\
- addi reg1, reg1, 4 ;\
- li reg2, CLINT_END_HART_IPI ;\
- blt reg1, reg2, 41b ;\
- /* Trigger software interrupt on CLINT1 */ \
- li reg1, CLINT1_CTRL_ADDR ;\
-41: ;\
- li reg2, 1 ;\
- sw reg2, 0(reg1) ;\
- addi reg1, reg1, 4 ;\
- li reg2, CLINT1_END_HART_IPI ;\
- blt reg1, reg2, 41b ;\
- /* Wait to receive software interrupt */ \
-42: ;\
- wfi ;\
- csrr reg2, mip ;\
- andi reg2, reg2, 0x8 ;\
- beqz reg2, 42b ;\
- /* Clear own software interrupt bit */ \
- csrr reg2, mhartid ;\
- bnez reg2, 41f; \
- /* hart0 case: Use CLINT0 */ \
- li reg1, CLINT_CTRL_ADDR ;\
- slli reg2, reg2, 2 ;\
- add reg2, reg2, reg1 ;\
- sw zero, 0(reg2) ;\
- j 42f; \
-41: \
- /* hart 2, 3 case: Use CLINT1 and remap hart IDs to 0 and 1 */ \
- li reg1, CLINT1_CTRL_ADDR ;\
- addi reg2, reg2, -2; \
- slli reg2, reg2, 2 ;\
- add reg2, reg2, reg1 ;\
- sw zero, 0(reg2) ; \
-42: \
- /* Wait for all software interrupt bits to be cleared on CLINT0 */ \
- li reg1, CLINT_CTRL_ADDR ;\
-41: ;\
- lw reg2, 0(reg1) ;\
- bnez reg2, 41b ;\
- addi reg1, reg1, 4 ;\
- li reg2, CLINT_END_HART_IPI ;\
- blt reg1, reg2, 41b; \
- /* Wait for all software interrupt bits to be cleared on CLINT1 */ \
- li reg1, CLINT1_CTRL_ADDR ;\
-41: ;\
- lw reg2, 0(reg1) ;\
- bnez reg2, 41b ;\
- addi reg1, reg1, 4 ;\
- li reg2, CLINT1_END_HART_IPI ;\
- blt reg1, reg2, 41b; \
- /* End smp_resume() */
-
-#else
-
-#define smp_resume(reg1, reg2) \
- li reg1, CLINT_CTRL_ADDR ;\
-41: ;\
- li reg2, 1 ;\
- sw reg2, 0(reg1) ;\
- addi reg1, reg1, 4 ;\
- li reg2, CLINT_END_HART_IPI ;\
- blt reg1, reg2, 41b ;\
-42: ;\
- wfi ;\
- csrr reg2, mip ;\
- andi reg2, reg2, 0x8 ;\
- beqz reg2, 42b ;\
- li reg1, CLINT_CTRL_ADDR ;\
- csrr reg2, mhartid ;\
- slli reg2, reg2, 2 ;\
- add reg2, reg2, reg1 ;\
- sw zero, 0(reg2) ;\
-41: ;\
- lw reg2, 0(reg1) ;\
- bnez reg2, 41b ;\
- addi reg1, reg1, 4 ;\
- li reg2, CLINT_END_HART_IPI ;\
- blt reg1, reg2, 41b
-
-#endif /* ifdef CLINT1_CTRL_ADDR */
-
-#endif
diff --git a/cosim/drivers/bootbare/linker/memory.lds b/cosim/drivers/bootbare/linker/memory.lds
deleted file mode 100644
index f5cdc07..0000000
--- a/cosim/drivers/bootbare/linker/memory.lds
+++ /dev/null
@@ -1,14 +0,0 @@
-MEMORY
-{
- debug_ctrl (rwx) : ORIGIN = 0x0, LENGTH = 0x1000
- error_mem (rw) : ORIGIN = 0x3000, LENGTH = 0x1000
- test_ctrl (rw) : ORIGIN = 0x4000, LENGTH = 0x1000
- maskrom_mem (rx) : ORIGIN = 0x10000, LENGTH = 0x4000
- clint_ctrl (rw) : ORIGIN = 0x2000000, LENGTH = 0x10000
- plic_ctrl (rw) : ORIGIN = 0xc000000, LENGTH = 0x4000000
- axi_pcie_host_1_00_a_ctrl (rw) : ORIGIN = 0x50000000, LENGTH = 0x4000000
- uart_ctrl (rw) : ORIGIN = 0x54000000, LENGTH = 0x1000
- spi_ctrl (rw) : ORIGIN = 0x54001000, LENGTH = 0x1000
- gpio_ctrl (rw) : ORIGIN = 0x54002000, LENGTH = 0x1000
- memory_mem (rwx) : ORIGIN = 0x80000000, LENGTH = 0x40000000
-}
diff --git a/cosim/drivers/bootbare/linker/sdboot.elf.lds b/cosim/drivers/bootbare/linker/sdboot.elf.lds
deleted file mode 100644
index deb76da..0000000
--- a/cosim/drivers/bootbare/linker/sdboot.elf.lds
+++ /dev/null
@@ -1,79 +0,0 @@
-OUTPUT_ARCH("riscv")
-ENTRY(_prog_start)
-
-INCLUDE memory.lds
-
-PHDRS
-{
- text PT_LOAD;
- data PT_LOAD;
- bss PT_LOAD;
-}
-
-SECTIONS
-{
- PROVIDE(_ram = ORIGIN(memory_mem));
- PROVIDE(_ram_end = _ram + LENGTH(memory_mem));
-
- .text ALIGN((ORIGIN(maskrom_mem) + 0x0), 8) : AT(ALIGN((ORIGIN(maskrom_mem) + 0x0), 8)) {
- PROVIDE(_ftext = .);
- *(.text.init)
- *(.text.unlikely .text.unlikely.*)
- *(.text .text.* .gnu.linkonce.t.*)
- PROVIDE(_etext = .);
- . += 0x40; /* to create a gap between .text and .data b/c ifetch can fetch ahead from .data */
- } >maskrom_mem :text
-
- .eh_frame ALIGN((ADDR(.text) + SIZEOF(.text)), 8) : AT(ALIGN((LOADADDR(.text) + SIZEOF(.text)), 8)) {
- *(.eh_frame)
- } >maskrom_mem :text
-
- .rodata ALIGN((ADDR(.eh_frame) + SIZEOF(.eh_frame)), 8) : AT(ALIGN((LOADADDR(.eh_frame) + SIZEOF(.eh_frame)), 8)) ALIGN_WITH_INPUT {
- *(.rodata .rodata.* .gnu.linkonce.r.*)
- } >maskrom_mem :data
-
- .srodata ALIGN((ADDR(.rodata) + SIZEOF(.rodata)), 8) : AT(ALIGN((LOADADDR(.rodata) + SIZEOF(.rodata)), 8)) ALIGN_WITH_INPUT {
- *(.srodata.cst16)
- *(.srodata.cst8)
- *(.srodata.cst4)
- *(.srodata.cst2)
- *(.srodata.*)
- } >maskrom_mem :data
-
- .data ALIGN((ADDR(.srodata) + SIZEOF(.srodata)), 8) : AT(ALIGN((LOADADDR(.srodata) + SIZEOF(.srodata)), 8)) ALIGN_WITH_INPUT {
- *(.data .data.* .gnu.linkonce.d.*)
- *(.tohost) /* TODO: Support sections that aren't explicitly listed in this linker script */
- } >maskrom_mem :data
-
- .sdata ALIGN((ADDR(.data) + SIZEOF(.data)), 8) : AT(ALIGN((LOADADDR(.data) + SIZEOF(.data)), 8)) ALIGN_WITH_INPUT {
- *(.sdata .sdata.* .gnu.linkonce.s.*)
- } >maskrom_mem :data
-
- PROVIDE(_data = ADDR(.rodata));
- PROVIDE(_data_lma = LOADADDR(.rodata));
- PROVIDE(_edata = .);
-
- .bss ALIGN((ORIGIN(memory_mem) + 0x0), 8) : AT(ALIGN((ORIGIN(memory_mem) + 0x0), 8)) ALIGN(8) {
- PROVIDE(_fbss = .);
- PROVIDE(__global_pointer$ = . + 0x7C0);
- *(.sbss .sbss.* .gnu.linkonce.sb.*)
- *(.bss .bss.* .gnu.linkonce.b.*)
- . = ALIGN(8);
- PROVIDE(_ebss = .);
- } >memory_mem :bss
-
- PROVIDE(_end = .);
-
- /*
- * heap_stack_region_usable_end: (ORIGIN(memory_mem) + LENGTH(memory_mem))
- * heap_stack_min_size: 4096
- * heap_stack_max_size: 1048576
- */
- PROVIDE(_sp = ALIGN(MIN((ORIGIN(memory_mem) + LENGTH(memory_mem)), _ebss + 1048576) - 7, 8));
- PROVIDE(_heap_end = _sp - 2048);
-
- /* This section is a noop and is only used for the ASSERT */
- .stack : {
- ASSERT(_sp >= (_ebss + 4096), "Error: No room left for the heap and stack");
- }
-}
diff --git a/cosim/drivers/cep_tests/CEP.h b/cosim/drivers/cep_tests/CEP.h
index 8d763e2..04c2857 100644
--- a/cosim/drivers/cep_tests/CEP.h
+++ b/cosim/drivers/cep_tests/CEP.h
@@ -252,10 +252,10 @@
// Note: Other LLKI related constants/definitions may be found in cep_crypto.h
// ------------------------------------------------------------------------------------------------------------
const uint32_t SROT_KEYINDEXRAM_ADDR = 0x00000100; // Offset from SROT_BASE_K
- const uint32_t SROT_KEYINDEXRAM_SIZE = 0x00000020;
+ const uint32_t SROT_KEYINDEXRAM_SIZE = 0x00000020; // 32 64-bit words
const uint32_t SROT_KEYRAM_ADDR = 0x00000200; // Offset from SROT_BASE_K
// Note: This cannot be less than SROT_KEYINDEXRAM_ADDR + (SROT_KEYINDEXRAM_SIZE * 8)!!!
- const uint32_t SROT_KEYRAM_SIZE = 0x00000100;
+ const uint32_t SROT_KEYRAM_SIZE = 0x00000800; // 2048 64-bit words
// Reminder: data width is 64-bits
const uint32_t SROT_CTRLSTS_ADDR = 0x00000000;
diff --git a/cosim/drivers/cep_tests/cep_aes.cc b/cosim/drivers/cep_tests/cep_aes.cc
index 018cec2..a3cbb28 100644
--- a/cosim/drivers/cep_tests/cep_aes.cc
+++ b/cosim/drivers/cep_tests/cep_aes.cc
@@ -80,7 +80,7 @@ int cep_aes::openssl_aes192_ecb_encryption
//
//
if (verbose) {
- LOGI("%s: INFO inLen=%d outlen=%d\n",__FUNCTION__,
+ LOGI("%s: inLen=%d outlen=%d\n",__FUNCTION__,
length,*outlen);
/*
EVP_CIPHER_CTX_key_length(&ctx),
diff --git a/cosim/drivers/cep_tests/cep_apis.cc b/cosim/drivers/cep_tests/cep_apis.cc
index ad3660b..c61ca19 100644
--- a/cosim/drivers/cep_tests/cep_apis.cc
+++ b/cosim/drivers/cep_tests/cep_apis.cc
@@ -355,8 +355,8 @@ int check_bare_status(int coreId,int maxTimeOut) {
//
void set_cur_status(int status) {
#ifdef BARE_MODE
- int i=0, coreId;
- uint64_t d64, offS, myOffs;
+ int coreId;
+ uint64_t d64, offS;
//
// which core???
//
@@ -381,7 +381,7 @@ void set_pass(void) {
void set_fail(void) {
#ifdef BARE_MODE
- uint64_t d64, offS, myOffs;
+ uint64_t d64, offS;
d64 = CEP_BAD_STATUS;
offS = reg_base_addr + cep_core0_status;
*(volatile uint64_t *)(offS) = d64;
@@ -539,7 +539,7 @@ int cep_get_lock(int myId, int lockNum, int timeOut) {
break;
}
timeOut--;
- DUT_RUNCLK(100);
+ USEC_SLEEP(100);
} while (timeOut > 0);
if (timeOut <= 0) {
LOGE("%s: ERROR: timeout\n",__FUNCTION__);
diff --git a/cosim/drivers/cep_tests/cep_crypto.cc b/cosim/drivers/cep_tests/cep_crypto.cc
index 32c25ea..76a22b3 100644
--- a/cosim/drivers/cep_tests/cep_crypto.cc
+++ b/cosim/drivers/cep_tests/cep_crypto.cc
@@ -100,7 +100,7 @@ int cep_crypto::CheckPlainText(void) {
void cep_crypto::PrintMe(const char *name, uint8_t *buf, int size) {
//if (GetVerbose()==0) return;
//
- char str[128];
+ char str[256];
//printf("Printing packet\n");
// print every 32 bytes??
int bC = 0;
diff --git a/cosim/drivers/cep_tests/cep_des3.cc b/cosim/drivers/cep_tests/cep_des3.cc
index 309ba1f..4f0d64d 100644
--- a/cosim/drivers/cep_tests/cep_des3.cc
+++ b/cosim/drivers/cep_tests/cep_des3.cc
@@ -87,7 +87,7 @@ int cep_des3::prepare_des3_key_N_text
}
//
if (verbose) {
- printf("%s: INFO inLen=%d outlen=%d kL=%d bL=%d\n",__FUNCTION__,
+ LOGI("%s: inLen=%d outlen=%d kL=%d bL=%d\n",__FUNCTION__,
length,*outlen,
EVP_CIPHER_CTX_key_length(&ctx),
EVP_CIPHER_CTX_block_size(&ctx)
diff --git a/cosim/drivers/cep_tests/cep_dft.cc b/cosim/drivers/cep_tests/cep_dft.cc
index b81d2d4..a09707d 100644
--- a/cosim/drivers/cep_tests/cep_dft.cc
+++ b/cosim/drivers/cep_tests/cep_dft.cc
@@ -193,7 +193,7 @@ int cep_dft::dft_waitTilDone(int maxTO) {
#endif
}
-int cep_dft::dft_CheckSamples(int startIdx,int samCnt) {
+int cep_dft::dft_CheckSamples(int lpCnt, int startIdx,int samCnt) {
if (GetVerbose(2)) { LOGI("%s\n",__FUNCTION__); }
//
double repsilon,rdiff;
@@ -212,7 +212,7 @@ int cep_dft::dft_CheckSamples(int startIdx,int samCnt) {
if (rdiff > repsilon) { // || (idiff > iepsilon)) {
if (GetExpErr()==0) {
- LOGE("%s: dft i=%d Exp=%.5f/%.5f Act=%.5f/%.5f : diff=%.5f/%.5f > Epsilon=%.5f/%.5f\n",__FUNCTION__,i,
+ LOGE("%s: dft lp=%d i=%d Exp=%.5f/%.5f Act=%.5f/%.5f : diff=%.5f/%.5f > Epsilon=%.5f/%.5f\n",__FUNCTION__,lpCnt ,i,
mRexp[i],mIexp[i], mRact[i],mIact[i],
rdiff,idiff,repsilon,iepsilon);
}
@@ -287,7 +287,7 @@ int cep_dft::idft_waitTilDone(int maxTO) {
#endif
}
-int cep_dft::idft_CheckSamples(int startIdx,int samCnt) {
+int cep_dft::idft_CheckSamples(int lpCnt, int startIdx,int samCnt) {
if (GetVerbose(2)) { LOGI("%s\n",__FUNCTION__); }
//
double repsilon,rdiff;
@@ -307,7 +307,7 @@ int cep_dft::idft_CheckSamples(int startIdx,int samCnt) {
// FIXME: dont know why only the real part are good
if (rdiff > repsilon) {
if (!GetExpErr()) {
- LOGE("%s: idft i=%d Exp=%.5f/%.5f Act=%.5f/%.5f : diff=%.5f/%.5f > Epsilon=%.5f/%.5f\n",__FUNCTION__,i,
+ LOGE("%s: idft lp=%d i=%d Exp=%.5f/%.5f Act=%.5f/%.5f : diff=%.5f/%.5f > Epsilon=%.5f/%.5f\n",__FUNCTION__,lpCnt, i,
mRexp[i],mIexp[i], mRact[i],mIact[i],
rdiff,idiff,repsilon,iepsilon);
}
@@ -341,7 +341,7 @@ int cep_dft::RunDftTest(int maxLoop) {
//
//
int skipFirstSample = 0;
- Random48_srand48(GetSeed());
+
for (int i=0;i>16) & 0xFFFF;
for (int j=0; j < MAX_DFT_SAMPLES; j++) {
@@ -420,7 +423,7 @@ int cep_dft::RunDftTest(int maxLoop) {
PrintMe("DFT-act",mRact,mIact,MAX_DFT_SAMPLES);
}
//adjust_float(mRact, mIact, MAX_DFT_SAMPLES);
- mErrCnt += dft_CheckSamples(skipFirstSample,MAX_DFT_SAMPLES);
+ mErrCnt += dft_CheckSamples(i,skipFirstSample,MAX_DFT_SAMPLES);
}
}
@@ -448,7 +451,7 @@ int cep_dft::RunDftTest(int maxLoop) {
PrintMe("IDFT-act",mRact,mIact,MAX_DFT_SAMPLES);
}
//adjust_float(mRAin, mIAin, MAX_DFT_SAMPLES);
- mErrCnt += idft_CheckSamples(skipFirstSample,MAX_DFT_SAMPLES);
+ mErrCnt += idft_CheckSamples(i,skipFirstSample,MAX_DFT_SAMPLES);
}
}
#endif
diff --git a/cosim/drivers/cep_tests/cep_dft.h b/cosim/drivers/cep_tests/cep_dft.h
index 81fa9c7..56ec783 100644
--- a/cosim/drivers/cep_tests/cep_dft.h
+++ b/cosim/drivers/cep_tests/cep_dft.h
@@ -42,13 +42,13 @@ class cep_dft : public cep_crypto {
void dft_getY(double *rbuf, double *ibuf, int len) ;
void dft_Start(void) ;
int dft_waitTilDone(int maxTO);
- int dft_CheckSamples(int startIdx,int samCnt) ;
+ int dft_CheckSamples(int lpCnt, int startIdx,int samCnt) ;
//
void idft_setX(double *rbuf, double *ibuf, int len) ;
void idft_getY(double *rbuf, double *ibuf, int len) ;
void idft_Start(void) ;
int idft_waitTilDone(int maxTO);
- int idft_CheckSamples(int startIdx,int samCnt) ;
+ int idft_CheckSamples(int lpCnt, int startIdx,int samCnt) ;
//
double mRin[MAX_DFT_SAMPLES];
double mIin[MAX_DFT_SAMPLES];
diff --git a/cosim/drivers/cep_tests/cep_gps.cc b/cosim/drivers/cep_tests/cep_gps.cc
index 97a9d25..9dccf09 100644
--- a/cosim/drivers/cep_tests/cep_gps.cc
+++ b/cosim/drivers/cep_tests/cep_gps.cc
@@ -229,10 +229,10 @@ void cep_gps::ResetCA_code()
int cep_gps::GetCA_code(int svNum)
{
int CACode = 0;
- int chip=0;
//
#if defined(BARE_MODE)
#else
+ int chip=0;
//
if (GetVerbose(2)) {
LOGI("G1=0x%04x G2=0x%04x\n",
diff --git a/cosim/drivers/cep_tests/cep_srot.cc b/cosim/drivers/cep_tests/cep_srot.cc
index 516b0af..98720d2 100644
--- a/cosim/drivers/cep_tests/cep_srot.cc
+++ b/cosim/drivers/cep_tests/cep_srot.cc
@@ -183,9 +183,9 @@ int cep_srot::EnableLLKI (uint8_t KeyIndex)
cep_writeNcapture(SROT_BASE_K, SROT_LLKIC2_SENDRECV_ADDR, llkic2_pack(
LLKI_MID_C2LOADKEYREQ, // Message ID
0x00, // Status (unused)
- 0x01, // Message Length
+ 0x0001, // Message Length
KeyIndex, // Key Index
- 0xDEADBEEF));
+ 0xDEADBE)); // rsvd1
// Poll the response waiting bit
cep_readNspin(SROT_BASE_K, SROT_CTRLSTS_ADDR, SROT_CTRLSTS_RESP_WAITING_MASK, SROT_CTRLSTS_RESP_WAITING_MASK, 100);
@@ -223,9 +223,9 @@ int cep_srot::DisableLLKI (uint8_t KeyIndex)
cep_writeNcapture(SROT_BASE_K, SROT_LLKIC2_SENDRECV_ADDR, llkic2_pack(
LLKI_MID_C2CLEARKEYREQ, // Message ID
0x00, // Status (unused)
- 0x01, // Message Length
+ 0x0001, // Message Length
KeyIndex, // Key Index
- 0xDEADBEEF));
+ 0xDEADBE)); // rsvd1
// Poll the response waiting bit
cep_readNspin(SROT_BASE_K, SROT_CTRLSTS_ADDR, SROT_CTRLSTS_RESP_WAITING_MASK, SROT_CTRLSTS_RESP_WAITING_MASK, 100);
@@ -474,7 +474,6 @@ int cep_srot::LLKI_ErrorTest(int cpuId) {
// --------------------------------------------------------------------------------------------------------
// Load some Key Indexes - Some good, some bad
// --------------------------------------------------------------------------------------------------------
- // Load some good keys and indexes
errCnt += LoadLLKIKey(0 , AES_BASE_K, 0, 1, AES_MOCK_TSS_KEY, INVERT_ALL_BITS);
errCnt += LoadLLKIKey(1 , AES_BASE_K, 2, 6, GPS_MOCK_TSS_KEY, INVERT_ALL_BITS);
@@ -484,24 +483,24 @@ int cep_srot::LLKI_ErrorTest(int cpuId) {
// Load a Key Index with a bad pointer pair (low pointer > high pointer)
cep_writeNcapture(SROT_BASE_K, SROT_KEYINDEXRAM_ADDR + 2*8, key_index_pack(
- 2, // low pointer
- 1, // high pointer
- AES_BASE_K, // core index
- 0x1)); // Valid
+ 2, // low pointer
+ 1, // high pointer
+ AES_BASE_K, // core index
+ 0x1)); // Valid
// Load a Key Index with a bad pointer pair (pointer exceeds key ram size)
cep_writeNcapture(SROT_BASE_K, SROT_KEYINDEXRAM_ADDR + 3*8, key_index_pack(
- 0, // low pointer
- 256, // high pointer
- AES_BASE_K, // core index
- 0x1)); // Valid
+ 0, // low pointer
+ SROT_KEYRAM_SIZE, // high pointer
+ AES_BASE_K, // core index
+ 0x1)); // Valid
// Load a Key Index with a bad core index
cep_writeNcapture(SROT_BASE_K, SROT_KEYINDEXRAM_ADDR + 4*8, key_index_pack(
- 0, // low pointer
- 1, // high pointer
- 31, // core index
- 0x1)); // Valid
+ 0, // low pointer
+ 1, // high pointer
+ 31, // core index
+ 0x1)); // Valid
// --------------------------------------------------------------------------------------------------------
@@ -515,9 +514,9 @@ int cep_srot::LLKI_ErrorTest(int cpuId) {
cep_writeNcapture(SROT_BASE_K, SROT_LLKIC2_SENDRECV_ADDR, llkic2_pack(
LLKI_MID_C2LOADKEYREQ, // Message ID
0x00, // Status (unused)
- 0x01, // Message Length
+ 0x0001, // Message Length
0, // Key Index
- 0xDEADBEEF));
+ 0xDEADBE)); // rsvd1
// Poll the response waiting bit
cep_readNspin(SROT_BASE_K, SROT_CTRLSTS_ADDR, SROT_CTRLSTS_RESP_WAITING_MASK, SROT_CTRLSTS_RESP_WAITING_MASK, 100);
@@ -538,9 +537,9 @@ int cep_srot::LLKI_ErrorTest(int cpuId) {
cep_writeNcapture(SROT_BASE_K, SROT_LLKIC2_SENDRECV_ADDR, llkic2_pack(
LLKI_MID_C2LOADKEYREQ, // Message ID
0x00, // Status (unused)
- 0x01, // Message Length
+ 0x0001, // Message Length
1, // Key Index
- 0xDEADBEEF));
+ 0xDEADBE)); // rsvd1
// Poll the response waiting bit
cep_readNspin(SROT_BASE_K, SROT_CTRLSTS_ADDR, SROT_CTRLSTS_RESP_WAITING_MASK, SROT_CTRLSTS_RESP_WAITING_MASK, 100);
@@ -557,9 +556,9 @@ int cep_srot::LLKI_ErrorTest(int cpuId) {
cep_writeNcapture(SROT_BASE_K, SROT_LLKIC2_SENDRECV_ADDR, llkic2_pack(
0xFF, // Bad Message ID
0x00, // Status (unused)
- 0x01, // Message Length
+ 0x0001, // Message Length
0, // Key Index
- 0xDEADBEEF));
+ 0xDEADBE)); // rsvd1
// Poll the response waiting bit
cep_readNspin(SROT_BASE_K, SROT_CTRLSTS_ADDR, SROT_CTRLSTS_RESP_WAITING_MASK, SROT_CTRLSTS_RESP_WAITING_MASK, 100);
@@ -576,16 +575,16 @@ int cep_srot::LLKI_ErrorTest(int cpuId) {
cep_writeNcapture(SROT_BASE_K, SROT_LLKIC2_SENDRECV_ADDR, llkic2_pack(
LLKI_MID_C2LOADKEYREQ, // Message ID
0x00, // Status (unused)
- 0x02, // BAD Message Length
+ 0x0002, // BAD Message Length
0, // Key Index
- 0xDEADBEEF));
+ 0xDEADBE)); // rsvd1
// Poll the response waiting bit
cep_readNspin(SROT_BASE_K, SROT_CTRLSTS_ADDR, SROT_CTRLSTS_RESP_WAITING_MASK, SROT_CTRLSTS_RESP_WAITING_MASK, 100);
// Compare expected and received responses
status = llkic2_extract_status(cep_readNcapture(SROT_BASE_K, SROT_LLKIC2_SENDRECV_ADDR));
- CHECK_RESPONSE(status, LLKI_STATUS_BAD_MSG_LEN, GetVerbose());
+ CHECK_RESPONSE(status, LLKI_STATUS_BAD_MSG_LEN, GetVerbose());
// --------------------------------------------------------------------------------------------------------
@@ -595,9 +594,9 @@ int cep_srot::LLKI_ErrorTest(int cpuId) {
cep_writeNcapture(SROT_BASE_K, SROT_LLKIC2_SENDRECV_ADDR, llkic2_pack(
LLKI_MID_C2LOADKEYREQ, // Message ID
0x00, // Status (unused)
- 0x01, // Message Length
+ 0x0001, // Message Length
32, // Key Index
- 0xDEADBEEF));
+ 0xDEADBE)); // rsvd1
// Poll the response waiting bit
cep_readNspin(SROT_BASE_K, SROT_CTRLSTS_ADDR, SROT_CTRLSTS_RESP_WAITING_MASK, SROT_CTRLSTS_RESP_WAITING_MASK, 100);
@@ -614,9 +613,9 @@ int cep_srot::LLKI_ErrorTest(int cpuId) {
cep_writeNcapture(SROT_BASE_K, SROT_LLKIC2_SENDRECV_ADDR, llkic2_pack(
LLKI_MID_C2LOADKEYREQ, // Message ID
0x00, // Status (unused)
- 0x01, // Message Length
+ 0x0001, // Message Length
31, // Key Index
- 0xDEADBEEF));
+ 0xDEADBE)); // rsvd1
// Poll the response waiting bit
cep_readNspin(SROT_BASE_K, SROT_CTRLSTS_ADDR, SROT_CTRLSTS_RESP_WAITING_MASK, SROT_CTRLSTS_RESP_WAITING_MASK, 100);
@@ -633,16 +632,16 @@ int cep_srot::LLKI_ErrorTest(int cpuId) {
cep_writeNcapture(SROT_BASE_K, SROT_LLKIC2_SENDRECV_ADDR, llkic2_pack(
LLKI_MID_C2LOADKEYREQ, // Message ID
0x00, // Status (unused)
- 0x01, // Message Length
+ 0x0001, // Message Length
2, // Key Index
- 0xDEADBEEF));
+ 0xDEADBE)); // rsvd1
// Poll the response waiting bit
cep_readNspin(SROT_BASE_K, SROT_CTRLSTS_ADDR, SROT_CTRLSTS_RESP_WAITING_MASK, SROT_CTRLSTS_RESP_WAITING_MASK, 100);
// Compare expected and received responses
status = llkic2_extract_status(cep_readNcapture(SROT_BASE_K, SROT_LLKIC2_SENDRECV_ADDR));
- CHECK_RESPONSE(status, LLKI_STATUS_BAD_POINTER_PAIR, GetVerbose());
+ CHECK_RESPONSE(status, LLKI_STATUS_BAD_POINTER_PAIR, GetVerbose());
// --------------------------------------------------------------------------------------------------------
@@ -652,9 +651,9 @@ int cep_srot::LLKI_ErrorTest(int cpuId) {
cep_writeNcapture(SROT_BASE_K, SROT_LLKIC2_SENDRECV_ADDR, llkic2_pack(
LLKI_MID_C2LOADKEYREQ, // Message ID
0x00, // Status (unused)
- 0x01, // Message Length
+ 0x0001, // Message Length
3, // Key Index
- 0xDEADBEEF));
+ 0xDEADBE)); // rsvd1
// Poll the response waiting bit
cep_readNspin(SROT_BASE_K, SROT_CTRLSTS_ADDR, SROT_CTRLSTS_RESP_WAITING_MASK, SROT_CTRLSTS_RESP_WAITING_MASK, 100);
@@ -671,9 +670,9 @@ int cep_srot::LLKI_ErrorTest(int cpuId) {
cep_writeNcapture(SROT_BASE_K, SROT_LLKIC2_SENDRECV_ADDR, llkic2_pack(
LLKI_MID_C2LOADKEYREQ, // Message ID
0x00, // Status (unused)
- 0x01, // Message Length
+ 0x0001, // Message Length
4, // Key Index
- 0xDEADBEEF));
+ 0xDEADBE)); // rsvd1
// Poll the response waiting bit
cep_readNspin(SROT_BASE_K, SROT_CTRLSTS_ADDR, SROT_CTRLSTS_RESP_WAITING_MASK, SROT_CTRLSTS_RESP_WAITING_MASK, 100);
diff --git a/cosim/drivers/cep_tests/cep_srot.h b/cosim/drivers/cep_tests/cep_srot.h
index 3c03cee..dd5b8f1 100644
--- a/cosim/drivers/cep_tests/cep_srot.h
+++ b/cosim/drivers/cep_tests/cep_srot.h
@@ -66,9 +66,9 @@ const uint8_t LLKI_KEYINDEX_VALID = 0x80;
#define llkic2_pack(msg_id, status, msg_len, key_index, rsvd1) \
(((uint64_t)msg_id << 0) & 0x00000000000000FF) | \
(((uint64_t)status << 8) & 0x000000000000FF00) | \
- (((uint64_t)msg_len << 16) & 0x0000000000FF0000) | \
- (((uint64_t)key_index << 24) & 0x00000000FF000000) | \
- (((uint64_t)rsvd1 << 32) & 0xFFFFFFFF00000000)
+ (((uint64_t)msg_len << 16) & 0x00000000FFFF0000) | \
+ (((uint64_t)key_index << 32) & 0x000000FF00000000) | \
+ (((uint64_t)rsvd1 << 40) & 0xFFFFFF0000000000)
// Packing macro for creating a Key Index entry
#define key_index_pack(low_pointer, high_pointer, core_index, valid) \
diff --git a/cosim/drivers/diag/cepAccessTest.cc b/cosim/drivers/diag/cepAccessTest.cc
index 4e8ac96..3959e7f 100644
--- a/cosim/drivers/diag/cepAccessTest.cc
+++ b/cosim/drivers/diag/cepAccessTest.cc
@@ -43,7 +43,7 @@ int cepAccessTest_runSingle(int cpuId, uint32_t adr, uint64_t pat, int modeSuppo
uint32_t wdat32, rdat32;
uint16_t wdat16, rdat16;
uint8_t wdat8, rdat8;
- uint64_t act;
+ uint64_t act=0;
//
// 64 read/write -bits
//
diff --git a/cosim/drivers/diag/cepCsrTest.cc b/cosim/drivers/diag/cepCsrTest.cc
index 1f3b2e1..5584608 100644
--- a/cosim/drivers/diag/cepCsrTest.cc
+++ b/cosim/drivers/diag/cepCsrTest.cc
@@ -45,6 +45,29 @@ int cepCsrTest_runTest(int cpuId, int accessSize,int revCheck,int seed, int verb
int errCnt = 0;
#if (BARE_MODE || LINUX_MODE)
+ uint64_t dat64;
+
+#if 1
+ uint64_t saveCustom;
+ //
+ // testing custom CSR @0x7c1
+ //
+ asm volatile ("csrr %0,0x7c1" : "=r"(saveCustom));
+ DUT_WRITE32_64(reg_base_addr + cep_scratch0_reg,saveCustom); // to observe
+ if (saveCustom != 0x208) errCnt++;
+ if (errCnt) goto apiDone;
+ //
+ dat64 = 0; // (uint64_t)-1;
+ asm volatile ("csrw 0x7c1,%0" : : "r"(dat64));
+ //
+ asm volatile ("csrr %0,0x7c1" : "=r"(dat64));
+ DUT_WRITE32_64(reg_base_addr + cep_scratch0_reg,dat64); // to observe
+ if (dat64 != 0) errCnt++;
+ if (errCnt) goto apiDone;
+ // put back
+ asm volatile ("csrw 0x7c1,%0" : : "r"(saveCustom));
+#endif
+
//
//
regBaseTest_t *regp; //
@@ -83,7 +106,6 @@ int cepCsrTest_runTest(int cpuId, int accessSize,int revCheck,int seed, int verb
(*regp->AddROReg_p)(regp, CSR_MIMPID, 0x0000000020181004, (uint64_t)(-1));
(*regp->AddROReg_p)(regp, CSR_MHARTID, cpuId, (uint64_t)(-1));
#ifdef SIM_ENV_ONLY
- uint64_t dat64;
//
// working
@@ -115,9 +137,15 @@ int cepCsrTest_runTest(int cpuId, int accessSize,int revCheck,int seed, int verb
(*regp->AddAReg_p)(regp, CSR_SIE,(uint64_t)(-1));
(*regp->AddAReg_p)(regp, CSR_SEPC,(uint64_t)(-1));
*/
+
//
// now do it
errCnt = (*regp->doRegTest_p)(regp);
+
+ //
+ // custom
+ //
+
//
// These to toggle PMP_mask all bit to 1
//
@@ -209,6 +237,7 @@ int cepCsrTest_runTest(int cpuId, int accessSize,int revCheck,int seed, int verb
cepCsrTest_DELETE(regp);
#endif
//
+ apiDone:
return errCnt;
}
diff --git a/cosim/drivers/diag/cepGpioTest.cc b/cosim/drivers/diag/cepGpioTest.cc
index 28e844e..3462563 100644
--- a/cosim/drivers/diag/cepGpioTest.cc
+++ b/cosim/drivers/diag/cepGpioTest.cc
@@ -112,6 +112,53 @@ int cepGpioTest_runRegTest(int cpuId, int accessSize,int seed, int verbose) {
return errCnt;
}
+//
+int cepGpioTest_intrTest(int cpuId, int seed, int verbose) {
+ int errCnt = 0;
+ uint32_t rdat32, wdat32, offs;
+ // setup
+ DUT_WRITE32_32(gpio_base_addr + gpio_iof_en , 0x00); // no IOF
+ DUT_WRITE32_32(gpio_base_addr + gpio_pue , 0x00); // no internal pull up
+ DUT_WRITE32_32(gpio_base_addr + gpio_output_en , 0xFF);
+ DUT_WRITE32_32(gpio_base_addr + gpio_input_en , 0xFF);
+ DUT_WRITE32_32(gpio_base_addr + gpio_high_ie , 0xFF);
+ //
+ // Each GPIO
+ //
+ for (int i=0;i<8;i++) {
+ // walking 1
+ wdat32 = 1 << i;
+ DUT_WRITE32_32(gpio_base_addr + gpio_port_output, wdat32);
+ // loop back
+ offs = gpio_base_addr + gpio_pin;
+ //
+ DUT_READ32_32 (offs, rdat32);
+ if (rdat32 != wdat32) {
+ LOGE("ERROR: Mismatch offs=0x%08x i=%d exp=0x%08x act=0x%08x\n",offs,i,wdat32,rdat32);
+ errCnt++;
+ break;
+ }
+ else if (verbose) {
+ LOGI("OK: offs=0x%08x i=%d exp=0x%08x act=0x%08x\n",offs,i,wdat32,rdat32);
+ }
+ // check pending
+ offs = gpio_base_addr + gpio_high_ip;
+ //
+ DUT_READ32_32 (offs, rdat32);
+ if (rdat32 != wdat32) {
+ LOGE("ERROR: Mismatch offs=0x%08x i=%d exp=0x%08x act=0x%08x\n",offs,i,wdat32,rdat32);
+ errCnt++;
+ break;
+ }
+ else if (verbose) {
+ LOGI("OK: offs=0x%08x i=%d exp=0x%08x act=0x%08x\n",offs,i,wdat32,rdat32);
+ }
+
+ }
+ return errCnt;
+}
+
+
int cepGpioTest_runTest(int cpuId, int seed, int verbose) {
int errCnt = 0;
if (!errCnt) { errCnt += cepGpioTest_runRegTest(cpuId,32, seed, verbose); }
diff --git a/cosim/drivers/diag/cepGpioTest.h b/cosim/drivers/diag/cepGpioTest.h
index b8e03e7..1dda7da 100644
--- a/cosim/drivers/diag/cepGpioTest.h
+++ b/cosim/drivers/diag/cepGpioTest.h
@@ -36,5 +36,6 @@ uint64_t cepGpioTest_ReadEntry(regBaseTest_t *me, uint32_t adr);
//
int cepGpioTest_runTest(int cpuId, int seed, int verbose);
int cepGpioTest_runRegTest(int cpuId, int accessSize,int seed, int verbose);
+int cepGpioTest_intrTest(int cpuId, int seed, int verbose);
#endif
diff --git a/cosim/drivers/diag/cepMacroMix.cc b/cosim/drivers/diag/cepMacroMix.cc
index 4eec89d..39422ee 100644
--- a/cosim/drivers/diag/cepMacroMix.cc
+++ b/cosim/drivers/diag/cepMacroMix.cc
@@ -68,14 +68,6 @@ int cepMacroMix_runTest(int cpuId, int mask, int cryptoMask, int seed, int verbo
//
// ONly if in the cryptoMask
//
-
-
-
-
-
-
-
-
//
int captureOn = 0;
#ifdef CAPTURE_CMD_SEQUENCE
diff --git a/cosim/drivers/diag/cepMaskromTest.cc b/cosim/drivers/diag/cepMaskromTest.cc
index 17676f1..217ceef 100644
--- a/cosim/drivers/diag/cepMaskromTest.cc
+++ b/cosim/drivers/diag/cepMaskromTest.cc
@@ -27,8 +27,6 @@
// The test itself
// =============================
//
-
-
int cepMaskromTest_runTest(int cpuId, int seed, int verbose) {
int errCnt = 0;
//
@@ -38,15 +36,23 @@ int cepMaskromTest_runTest(int cpuId, int seed, int verbose) {
uint16_t dat16, edat16;
uint8_t dat8, edat8;
+#ifdef SIM_ENV_ONLY
+ uint32_t known_pat1 = bootrom_known_pat1;
+ uint32_t known_pat0 = bootrom_known_pat0;
+ //
+ // Read ONLY
+ //
+ offs = bootrom_base_addr + ((1 << 15)-8); // bottom of 32k bytes
+#else
// from bootbare.hex
uint32_t known_pat1 = 0x00800913; // location 0
uint32_t known_pat0 = 0x30491073; // location 4
-
//
// Read ONLY
//
offs = bootrom_base_addr; // + ((1<<13)-8);
-
+#endif
+
// 64-bit
DUT_READ32_64(offs, dat64);
diff --git a/cosim/drivers/diag/cepMultiThread.cc b/cosim/drivers/diag/cepMultiThread.cc
new file mode 100644
index 0000000..f7c0095
--- /dev/null
+++ b/cosim/drivers/diag/cepMultiThread.cc
@@ -0,0 +1,340 @@
+//************************************************************************
+// Copyright 2021 Massachusetts Institute of Technology
+// SPDX License Identifier: MIT
+//
+// File Name:
+// Program: Common Evaluation Platform (CEP)
+// Description:
+// Notes:
+//
+//************************************************************************
+
+
+#include "simdiag_global.h"
+#include "cep_adrMap.h"
+#include "cepMultiThread.h"
+
+#include "cep_apis.h"
+#include "portable_io.h"
+
+#include "cepregression.h"
+
+#ifdef BARE_MODE
+
+#else
+#include "simPio.h"
+#endif
+
+#include "CEP.h"
+#include "cep_aes.h"
+#include "cep_des3.h"
+#include "cep_md5.h"
+#include "cep_sha256.h"
+#include "cep_gps.h"
+#include "cep_fir.h"
+#include "cep_iir.h"
+#include "cep_dft.h"
+#include "cep_rsa.h"
+#include "cep_srot.h"
+
+//
+// 1. Allocate N number of words in Cache, each word associates with 1 unique macro test (aes, des3,...)
+// 2. All are intially cleared to zero indicate the macro test is not running by any one...
+// 3. M number of threads will be spawn and allow to float, thread's ID must be != 0, each will try to to run all macro tests one-by-one
+// after it get the lock via LRSC on one of those above.
+//
+
+//#define USE_ATOMIC
+
+//
+// return test# (0 - N) , thrId MUST != 0, return -1 if fails
+//
+int cepMultiThread_findATest2Run(int thrId, uint64_t testLockPtr, int doneMask, int maxTest, int verbose)
+{
+ //
+#ifndef BARE_MODE
+ int maxLoop = 2000;
+ while (maxLoop > 0) {
+ for (int i=0;i
+#ifdef __cplusplus
+extern "C" {
+#endif
+ int cepMultiThread_findATest2Run(int thrId, uint64_t testLockPtr, int doneMask, int maxTest, int verbose);
+ int cepMultiThread_releaseTestLock(int thrId, int testId,uint64_t testLockPtr);
+ int cepMultiThread_setup(int cpuId, uint64_t testLockPtr,int maxTest, int coreMask, int verbose);
+ int cepMultiThread_runThr(int thrId, uint64_t testLockPtr, int cryptoMask, int maxTest, int maxLoop,int seed, int verbose);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/cosim/drivers/diag/cepPlicTest.cc b/cosim/drivers/diag/cepPlicTest.cc
index 45b1c77..2cd07a9 100644
--- a/cosim/drivers/diag/cepPlicTest.cc
+++ b/cosim/drivers/diag/cepPlicTest.cc
@@ -13,7 +13,9 @@
#include "simdiag_global.h"
#include "cep_adrMap.h"
#include "cepPlicTest.h"
-
+#include "cepUartTest.h"
+#include "cepSpiTest.h"
+//
#include "cep_apis.h"
#include "portable_io.h"
@@ -68,26 +70,19 @@ int cepPlicTest_runRegTest(int cpuId, int accessSize,int seed, int verbose) {
// start adding register to test
//
// there are 127 of them , split into 4 regions one per core
-#if 1
// pick one to run
if (cpuId == 0) {
- int maxReg = 7; // ONly ?? are implemented!!
- for (int i=1;iAddAReg_p)(regp, plic_base_addr + (plic_source1_prio_offset-4) + (cpuId*maxReg*4) + (i*4), 0x7); // only 3 bits
- }
+ int maxReg = 10; // uart,spi,gpio[7:0], no 0
+ for (int i=1;i<=maxReg;i++) {
+ (*regp->AddAReg_p)(regp, plic_base_addr + (plic_source0_prio_offset) + (i*4), 0x7); // only 3 bits
+ }
}
-#else
- int start = (cpuId == 0) ? 1 : 0;
- int maxReg = 8; // 128/4 = 32 each except 0
- uint32_t offs;
- for (int i=start;iAddAReg_p)(regp, plic_base_addr + (plic_source1_prio_offset-4) + (cpuId*maxReg*4) + (i*4), 0x7); // only 3 bits
+ // each hart has 2 context
+ for (int c=0;c<2;c++) {
+ int ctx = (cpuId*2) + c;
+ (*regp->AddAReg_p)(regp, plic_base_addr + plic_hart0_m_mode_ien_start + (plic_mode_ien_size_offset*ctx), 0x7FE); // only 10 sources, no 0
+ (*regp->AddAReg_p)(regp, plic_base_addr + plic_hart0_m_mode_prio_thresh + (plic_prio_thresh_size_offset*ctx), 0x7); // only 3 bits
}
-#endif
- (*regp->AddAReg_p)(regp, plic_base_addr + plic_hart0_m_mode_ien_start + (plic_mode_ien_size_offset*cpuId), 0x3E); // only 5 bits
- (*regp->AddAReg_p)(regp, plic_base_addr + plic_hart0_m_mode_prio_thresh + (plic_prio_thresh_size_offset*cpuId), 0x7); // only 3 bits
//
// add a hole in 4K
//
@@ -110,3 +105,89 @@ int cepPlicTest_runTest(int cpuId, int seed, int verbose) {
//
return errCnt;
}
+
+
+//
+// PLIC priority interrupt test
+//
+int cepPlicTest_prioIntrTest(int coreId, int verbose)
+{
+ int errCnt = 0;
+ uint32_t offS, dat32;
+ int startSrc = 1; // uart(1),spi(2),GPIO (3-10)
+ int endSrc = 10;
+ char txStr[] = "MITLL";
+ //
+ // setup
+ //
+ uint32_t enableMask = 0;
+ for (int i=startSrc;i<= endSrc;i++) {
+ enableMask |= (1 << i);
+ }
+ //
+ // set the threshold to 0,2,4,6
+ // each Hart will have 2 context? M-mode and S-mode
+ //
+ for (int ctx=0;ctx<2;ctx++) {
+ offS = plic_base_addr + plic_hart0_m_mode_prio_thresh + (plic_prio_thresh_size_offset*((coreId*2)+ctx));
+ dat32 = 0;
+ DUT_WRITE32_32(offS, dat32);
+ }
+ // prio from 0 to 7
+ // NOTE: if prio=0, there will be no interrupt but the internal pending bit is still set.. CHECKME!!!!
+ int prio = 7;
+ for (int i=startSrc;i<= endSrc;i++) {
+ DUT_WRITE32_32(plic_base_addr + plic_source0_prio_offset + i*4, prio); // start with 1 for core0
+ prio--;
+ if (prio < 1) prio = 1; // min
+ }
+ //
+ // get the lock
+ //
+ int actSrc = 0;
+ if (cep_get_lock(coreId, 1, 5000)) { // use lock 1
+ for (int c=0;c<2;c++) {
+ int ctx = (coreId*2) + c;
+ //
+ // set enable
+ //
+ offS = plic_base_addr + plic_hart0_m_mode_ien_start + (plic_mode_ien_size_offset*ctx);
+ DUT_WRITE32_32(offS, enableMask);
+ //
+ // pulse the interrupt
+ //
+ errCnt += cepUartTest_runTxRxTest(coreId,32-1, &txStr[coreId], 1, 0, verbose);
+ errCnt += cepSpiRdWrTest(coreId,1, 0, verbose);
+ //
+ DUT_WRITE32_32(gpio_base_addr + gpio_low_ie, 0xff); // gpio[7:0]
+ DUT_WRITE32_32(gpio_base_addr + gpio_low_ie, 0x0);
+ //
+ // check claim
+ //
+ for (int expSrc=startSrc; expSrc <= endSrc;expSrc++) {
+ // read my claim
+ DUT_READ32_32(plic_base_addr + (plic_prio_thresh_size_offset*ctx) + plic_hart0_m_mode_claim_done,actSrc);
+ if (actSrc != expSrc) {
+ LOGE("ERROR: ctx=%d mismatch expSrc=%d actSrc=%d\n",ctx,expSrc, actSrc);
+ errCnt++;
+ break;
+ }
+ else if (verbose) {
+ LOGI("OK: ctx=%d expSrc=%d actSrc=%d\n",ctx,expSrc, actSrc);
+ }
+ // I am done with my claim
+ DUT_WRITE32_32(plic_base_addr + (plic_prio_thresh_size_offset*ctx) + plic_hart0_m_mode_claim_done,actSrc);
+ }
+ // clear enable
+ offS = plic_base_addr + plic_hart0_m_mode_ien_start + (plic_mode_ien_size_offset*ctx);
+ DUT_WRITE32_32(offS, 0);
+ if (errCnt) break;
+ }
+ cep_release_lock(coreId, 1);
+ } else {
+ errCnt++;
+ }
+ //
+ return errCnt;
+}
+
diff --git a/cosim/drivers/diag/cepPlicTest.h b/cosim/drivers/diag/cepPlicTest.h
index f22828e..22cb473 100644
--- a/cosim/drivers/diag/cepPlicTest.h
+++ b/cosim/drivers/diag/cepPlicTest.h
@@ -38,4 +38,7 @@ int cepPlicTest_runTest(int cpuId, int seed, int verbose);
int cepPlicTest_runRegTest(int cpuId, int accessSize,int seed, int verbose);
+//int cepPlicTest_intrTest(int coreId, int verbose);
+int cepPlicTest_prioIntrTest(int coreId, int verbose);
+
#endif
diff --git a/cosim/drivers/diag/cepSpiTest.cc b/cosim/drivers/diag/cepSpiTest.cc
index f0917f7..cc8ff58 100644
--- a/cosim/drivers/diag/cepSpiTest.cc
+++ b/cosim/drivers/diag/cepSpiTest.cc
@@ -132,7 +132,7 @@ int cep_setup_spi(int csId, int mode, int divisor, int En)
// Run read/write test
//
// assuming SPI is loopback MOSI -> MISO
-int cepSpiRdWrTest(int csId, int seed, int verbose) {
+int cepSpiRdWrTest(int cpuId, int maxChar, int seed, int verbose) {
int errCnt = 0;
int dat;
if (verbose) {
@@ -148,7 +148,7 @@ int cepSpiRdWrTest(int csId, int seed, int verbose) {
//
// write to txFIFO and should get back what we write via rxfifo
//
- for (int i=0;i<16;i++) {
+ for (int i=0;i 7) dat = ~dat & 0xFF;
DUT_WRITE32_32(spi_base_addr + spi_txfifo, dat);
@@ -178,6 +178,7 @@ int cepSpiRdWrTest(int csId, int seed, int verbose) {
} while (to > 0);
if (errCnt != 0) break;
}
+ DUT_WRITE32_32(spi_base_addr + spi_ie, 0x0); // turn off interrupt
return errCnt;
}
@@ -188,7 +189,7 @@ int cepSpiTest_runTest(int cpuId, int seed, int verbose) {
if (!errCnt) { errCnt += cepSpiTest_runRegTest(cpuId,32, seed, verbose); }
#ifdef SIM_ENV_ONLY
//
- if (!errCnt) { errCnt += cepSpiRdWrTest(0, seed, verbose); }
+ if (!errCnt) { errCnt += cepSpiRdWrTest(cpuId, 16, seed, verbose); }
#endif
return errCnt;
diff --git a/cosim/drivers/diag/cepSpiTest.h b/cosim/drivers/diag/cepSpiTest.h
index 52fb53e..a6df052 100644
--- a/cosim/drivers/diag/cepSpiTest.h
+++ b/cosim/drivers/diag/cepSpiTest.h
@@ -36,5 +36,6 @@ uint64_t cepSpiTest_ReadEntry(regBaseTest_t *me, uint32_t adr);
//
int cepSpiTest_runTest(int cpuId, int seed, int verbose);
int cepSpiTest_runRegTest(int cpuId, int accessSize,int seed, int verbose);
+int cepSpiRdWrTest(int cpuId, int maxChar, int seed, int verbose);
#endif
diff --git a/cosim/drivers/diag/cepSrotMemTest.cc b/cosim/drivers/diag/cepSrotMemTest.cc
index 6060fa2..f0485fd 100644
--- a/cosim/drivers/diag/cepSrotMemTest.cc
+++ b/cosim/drivers/diag/cepSrotMemTest.cc
@@ -43,7 +43,7 @@ int cepSrotMemTest_runTest(int cpuId, int seed, int verbose) {
//
for (int i=0;i<2;i++) {
if (i == 0) {
- adrWidth = 8; // 256 locations
+ adrWidth = 11; // 2048 locations
mem_base = srot_base_addr + SROT_KEYRAM_ADDR;
} else {
adrWidth = 6; // 32 locations
diff --git a/cosim/drivers/diag/cepUartTest.cc b/cosim/drivers/diag/cepUartTest.cc
index ee81875..d797e04 100644
--- a/cosim/drivers/diag/cepUartTest.cc
+++ b/cosim/drivers/diag/cepUartTest.cc
@@ -117,11 +117,14 @@ int cepUartTest_runTxRxTest(int cpuId, int divisor, char *txStr, int txLen, int
rxDat = (char)(tmp & 0xff);
// check
if (rxDat != txStr[ri]) {
- LOGE("%s: mismatch char ri=%d act=0x%x exp=0x%x\n",__FUNCTION__,rxDat,txStr[ri]);
+ LOGE("%s: mismatch char ri=%d act=0x%x exp=0x%x\n",__FUNCTION__,ri,rxDat,txStr[ri]);
errCnt++;
+ ri++;
break;
- } else if (verbose) {
- LOGI("%s: OK char ri=%d act=0x%x exp=0x%x\n",__FUNCTION__,ri,rxDat,txStr[ri]);
+ } else {
+ if (verbose) {
+ LOGI("%s: OK char ri=%d act=0x%x exp=0x%x\n",__FUNCTION__,ri,rxDat,txStr[ri]);
+ }
ri++;
}
}
@@ -131,8 +134,8 @@ int cepUartTest_runTxRxTest(int cpuId, int divisor, char *txStr, int txLen, int
}
// disable
DUT_WRITE32_32(uart_base_addr + uart_txctrl,0);
- DUT_WRITE32_32(uart_base_addr + uart_rxctrl,0);
- DUT_WRITE32_32(uart_base_addr + uart_ie,0);
+ DUT_WRITE32_32(uart_base_addr + uart_rxctrl,0);
+ DUT_WRITE32_32(uart_base_addr + uart_ie,0);
return errCnt;
}
diff --git a/cosim/drivers/linux/Makefile b/cosim/drivers/linux/Makefile
index b04c3ad..c4ac566 100644
--- a/cosim/drivers/linux/Makefile
+++ b/cosim/drivers/linux/Makefile
@@ -23,8 +23,8 @@ SOE = 0
# So force it to use g++ instead
#
MY_CC = $(patsubst %gcc, %g++, $(CC))
-CFLAGS += -g -Wall -I . -DLINUX_MODE -DCEP_SOE=$(SOE) -DRISCV_CPU -DBIG_ENDIAN
-CFLAGS += -std=c++11
+CFLAGS += -g -Wall -I . -DLINUX_MODE -DCEP_SOE=$(SOE) -DRISCV_CPU -DBIG_ENDIAN -DUSE_ATOMIC
+CFLAGS += -std=c++17
# -static will crash for mutithread
LFLAGS = -lpthread
@@ -139,3 +139,11 @@ clean:
rm -f *.o
rm -f $(TARGET)
+#
+# This target just to rebuild the cep_diag. Assuming everything else already being built via ../README.md file
+#
+#
+buildMe:
+ make install
+ (cd ${FREEDOM_U_SDK_DIR}/work/buildroot_initramfs; rm -rf build/cep_diag*; make)
+ (cd ${FREEDOM_U_SDK_DIR}; make -j8 BOARD=vc707devkit_nopci all)
diff --git a/cosim/drivers/linux/cep_diag.cc b/cosim/drivers/linux/cep_diag.cc
index a8cae15..0be1ef0 100644
--- a/cosim/drivers/linux/cep_diag.cc
+++ b/cosim/drivers/linux/cep_diag.cc
@@ -37,6 +37,7 @@
#include "cep_dbg.h"
#include "cep_diag.h"
#include "cep_exports.h"
+#include "cep_version.h"
// Macro to properly format the version register
#define MAJOR_VERSION(n) (int)((n >> 48) & 0xFF)
@@ -149,10 +150,11 @@ void lnx_mem_write(u_int32_t offs,u_int64_t pData) { do_write(offs,pData); }
// =======================================
//
static void Print_CepBuildDate(void) {
- printf("\n*** CEP Tag=%s CEP HW VERSION = v%x.%x was built on %s %s ***\n",
- CEP_TAG, MAJOR_VERSION(lnx_cep_read(CEP_VERSION_REG)), MINOR_VERSION(lnx_cep_read(CEP_VERSION_REG)),__DATE__,__TIME__);
+ printf("\n*** CEP SW=0x%x.%x HW VERSION = v%x.%x was built on %s %s ***\n",
+ CEP_MAJOR_VERSION,CEP_MINOR_VERSION,
+ MAJOR_VERSION(lnx_cep_read(CEP_VERSION_REG)), MINOR_VERSION(lnx_cep_read(CEP_VERSION_REG)),__DATE__,__TIME__);
// do the read and print
- printf(" CEP FPGA Physical: cepReg/ddr3/other/sys -> Virtual=0x%016lx, 0x%016lx, 0x%016lx, 0x%016lx ScratchPad=0x%016lx\n",
+ printf(" CEP FPGA Physical: cepReg/ddr3/other/sys -> Virtual=0x%lx, 0x%lx, 0x%lx, 0x%lx\n ScratchPad=0x%lx\n",
(u_int64_t)_cepMap.mem,
(u_int64_t)_ddr3Map.mem,
(u_int64_t)_otherMap.mem,
diff --git a/cosim/drivers/linux/cep_diag.mk b/cosim/drivers/linux/cep_diag.mk
index dfa9ffd..6e230c2 100644
--- a/cosim/drivers/linux/cep_diag.mk
+++ b/cosim/drivers/linux/cep_diag.mk
@@ -6,7 +6,7 @@
# Description: Buildroot mk file for CEP Regression Suite
#************************************************************************
-CEP_DIAG_VERSION = 2.0.0
+CEP_DIAG_VERSION = 3.3
CEP_DIAG_SITE = ./package/cep_diag/src
CEP_DIAG_SITE_METHOD = local
diff --git a/cosim/drivers/linux/cep_exports.cc b/cosim/drivers/linux/cep_exports.cc
index cad0851..0f5230b 100644
--- a/cosim/drivers/linux/cep_exports.cc
+++ b/cosim/drivers/linux/cep_exports.cc
@@ -279,6 +279,23 @@ int run_cepPlicTest(void) {
return errCnt;
}
+#if 0
+// priority interrupt test
+static void cepPlicPrioIntrTest_thr(int id) {
+ int errCnt = thr_waitTilLock(id, 5);
+ errCnt += cepPlicTest_prioIntrTest(id, GET_VAR_VALUE(verbose));
+ cep_set_thr_errCnt(errCnt);
+}
+
+int run_cepPlicPrioIntrTest(void) {
+ int errCnt = 0;
+ //
+ cep_set_thr_function(cepPlicPrioIntrTest_thr);
+ errCnt = run_multiThreads(GET_VAR_VALUE(coreMask));
+ return errCnt;
+ }
+#endif
+
//
// ********************
// cepSrotMemTest (single)
@@ -958,3 +975,39 @@ int run_cepSrotErrTest(void) {
return errCnt;
}
+//
+// ********************
+// CEP MultiThread
+// ********************
+//
+#include "cepMultiThread.h"
+u_int64_t testLockBuf=0;
+//
+static void cepMultiThread_thr(int id) {
+ int errCnt = 0;
+ int maxTest = 10;
+ // RSA takes too long!!!
+ int cryptoMask = ((1 << maxTest) -1) & ~(1 << RSA_BASE_K) & GET_VAR_VALUE(testMask);
+ int maxLoop = 5;
+ errCnt += cepMultiThread_runThr(id, testLockBuf, cryptoMask, maxTest, maxLoop, GET_VAR_VALUE(seed), GET_VAR_VALUE(verbose));
+ cep_set_mthr_errCnt(id,errCnt);
+}
+
+int run_cepMultiThread(void) {
+ int errCnt = 0;
+ //
+ cep_set_thr_function(cepMultiThread_thr);
+ int maxTest = 10;
+#ifdef USE_ATOMIC
+ testLockBuf = (u_int64_t)getScratchPtr(); // virtual
+ clearScratchPtr();
+#else
+ testLockBuf = (u_int64_t)(ddr3_base_adr) + ((u_int64_t)getScratchPtr() & (u_int64_t)(ddr3_base_size-1)); // physical
+#endif
+ errCnt += cepMultiThread_setup(0, testLockBuf, maxTest, 1, GET_VAR_VALUE(verbose)) ;
+ //
+ if (!errCnt) { errCnt = run_multiThreadFloats(GET_VAR_VALUE(maxThreads)); }
+ return errCnt;
+ }
+
+
diff --git a/cosim/drivers/linux/cep_exports.h b/cosim/drivers/linux/cep_exports.h
index ff0663e..9f04f88 100644
--- a/cosim/drivers/linux/cep_exports.h
+++ b/cosim/drivers/linux/cep_exports.h
@@ -29,59 +29,62 @@
#ifdef __cplusplus
extern "C" {
#endif
- //
- // Common/Utils
- //
- int run_threadTest(void);
- //
- // CEP
- //
- int cep_aWrite(void);
- int cep_aRead(void);
- int run_cepRegTest(void);
- int run_cepLockTest(void);
- int run_cepMultiLock(void);
- int run_ddr3Test(void);
- int run_cepAllMacros(void);
- int run_cepMacroMix(void);
- // misc
- int run_cepGpioTest(void);
- int run_cepSrotMemTest(void);
- int run_cepSrotMaxKeyTest(void);
- int run_cepMacroBadKey(void);
- int run_smemTest(void);
- int run_cepLockfreeAtomic(void);
- int run_cepLrscOps(void);
- int run_cepClintTest(void);
- int run_cepPlicTest(void);
- int run_cepAccessTest(void);
- int run_cepAtomicTest(void);
- int run_cepSpiTest(void);
- int run_cepMaskromTest(void);
- // int run_cepCsrTest(void);
- int run_cepSrotErrTest(void);
- //
- int run_cep_AES (void);
- int run_cep_DES3 (void);
- int run_cep_DFT (void);
- int run_cep_FIR (void);
- int run_cep_IIR (void);
- int run_cep_GPS (void);
- int run_cep_MD5 (void);
- int run_cep_RSA (void);
- int run_cep_SHA256 (void);
- //
- // DDR3
- //
- int ddr3_aWrite(void);
- int ddr3_aRead(void);
-
- //
- // cores
- //
- int run_dcacheCoherency(void);
- int run_icacheCoherency(void);
- int run_cacheFlush(void);
+ //
+ // Common/Utils
+ //
+ int run_threadTest(void);
+ //
+ // CEP
+ //
+ int cep_aWrite(void);
+ int cep_aRead(void);
+ int run_cepRegTest(void);
+ int run_cepLockTest(void);
+ int run_cepMultiLock(void);
+ int run_ddr3Test(void);
+ int run_cepAllMacros(void);
+ int run_cepMacroMix(void);
+ // misc
+ int run_cepGpioTest(void);
+ int run_cepSrotMemTest(void);
+ int run_cepSrotMaxKeyTest(void);
+ int run_cepMacroBadKey(void);
+ int run_smemTest(void);
+ int run_cepLockfreeAtomic(void);
+ int run_cepLrscOps(void);
+ int run_cepClintTest(void);
+ int run_cepPlicTest(void);
+ int run_cepAccessTest(void);
+ int run_cepAtomicTest(void);
+ int run_cepSpiTest(void);
+ int run_cepMaskromTest(void);
+ // int run_cepCsrTest(void);
+ int run_cepSrotErrTest(void);
+ //
+ //int run_cepPlicPrioIntrTest(void);
+ //
+ int run_cep_AES (void);
+ int run_cep_DES3 (void);
+ int run_cep_DFT (void);
+ int run_cep_FIR (void);
+ int run_cep_IIR (void);
+ int run_cep_GPS (void);
+ int run_cep_MD5 (void);
+ int run_cep_RSA (void);
+ int run_cep_SHA256 (void);
+ int run_cepMultiThread(void);
+ //
+ // DDR3
+ //
+ int ddr3_aWrite(void);
+ int ddr3_aRead(void);
+
+ //
+ // cores
+ //
+ int run_dcacheCoherency(void);
+ int run_icacheCoherency(void);
+ int run_cacheFlush(void);
#ifdef __cplusplus
}
#endif
diff --git a/cosim/drivers/linux/cep_io.h b/cosim/drivers/linux/cep_io.h
index 1230154..3343296 100644
--- a/cosim/drivers/linux/cep_io.h
+++ b/cosim/drivers/linux/cep_io.h
@@ -21,37 +21,29 @@
//#include
extern std::mutex iomutex;
-#define THR_LOGI(format, ...) { \
- char _gstr[1024], _tstr[32]; \
- sprintf(_tstr,"C%d:",sched_getcpu()); \
- snprintf(_gstr,sizeof(_gstr),format, ##__VA_ARGS__); \
- std::lock_guard iolock(iomutex); \
- printf("%s %s", _tstr, _gstr); \
- }
+#define THR_LOGI(format, ...) { \
+ std::scoped_lock iolock(iomutex); \
+ printf("C%d: ",sched_getcpu()); \
+ printf(format, ##__VA_ARGS__);fflush(NULL); \
+ }
-#define THR_LOGE(format, ...) { \
- char _gstr[1024], _tstr[32]; \
- sprintf(_tstr,"C%d: ** ERROR ** ",sched_getcpu()); \
- snprintf(_gstr,sizeof(_gstr),format, ##__VA_ARGS__); \
- std::lock_guard iolock(iomutex); \
- printf("%s %s", _tstr, _gstr); \
- }
+#define THR_LOGE(format, ...) { \
+ std::scoped_lock iolock(iomutex); \
+ printf("C%d: ** ERROR ** ",sched_getcpu()); \
+ printf(format, ##__VA_ARGS__); fflush(NULL); \
+ }
-#define THR_LOGW(format, ...) { \
- char _gstr[1024], _tstr[32]; \
- sprintf(_tstr,"C%d: ** WARNING ** ",sched_getcpu()); \
- snprintf(_gstr,sizeof(_gstr),format, ##__VA_ARGS__); \
- std::lock_guard iolock(iomutex); \
- printf("%s %s", _tstr, _gstr); \
- }
+#define THR_LOGW(format, ...) { \
+ std::scoped_lock iolock(iomutex); \
+ printf("C%d: ** WARNING ** ",sched_getcpu()); \
+ printf(format, ##__VA_ARGS__);fflush(NULL); \
+ }
-#define THR_LOGF(format, ...) { \
- char _gstr[1024], _tstr[32]; \
- sprintf(_tstr,"C%d: ** FATAL ** ",sched_getcpu()); \
- snprintf(_gstr,sizeof(_gstr),format, ##__VA_ARGS__); \
- std::lock_guard iolock(iomutex); \
- printf("%s %s", _tstr, _gstr); \
- }
+#define THR_LOGF(format, ...) { \
+ std::scoped_lock iolock(iomutex); \
+ printf(_tstr,"C%d: ** FATAL ** ",sched_getcpu()); \
+ printf(format, ##__VA_ARGS__); fflush(NULL); \
+ }
//#define DELAY(a) mdelay(a)
diff --git a/cosim/drivers/linux/cep_run.cc b/cosim/drivers/linux/cep_run.cc
index 6695f8f..30b1689 100644
--- a/cosim/drivers/linux/cep_run.cc
+++ b/cosim/drivers/linux/cep_run.cc
@@ -577,7 +577,8 @@ int cep_init_run(void)
CEP_ADD_RUN(3,cepSrotErrTest, 0xFFFFFFFF, run_cepSrotErrTest, NULL, NULL, "CEP SRoT Error Test (single core) ");
//CEP_ADD_RUN(3,cepCsrTest, 0xFFFFFFFF, run_cepCsrTest, NULL, NULL, "CEP SPI test (all cores) ");
- CEP_ADD_RUN(4,cepPlicTest, 0xFFFFFFFF, run_cepPlicTest, NULL, NULL, "CEP PLIC register test (all cores)");
+ CEP_ADD_RUN(4,cepPlicTest, 0xFFFFFFFF, run_cepPlicTest, NULL, NULL, "CEP PLIC register test (all cores)");
+//CEP_ADD_RUN(4,cepPlicPrioIntrTest,0xFFFFFFFF, run_cepPlicPrioIntrTest,NULL,NULL, "CEP PLIC priority Interrupt test (all cores)");
CEP_ADD_RUN(4,cepClintTest, 0xFFFFFFFF, run_cepClintTest, NULL, NULL, "CEP CLINT register test (all cores)");
CEP_ADD_RUN(4,cepRegTest, 0xFFFFFFFF, run_cepRegTest, NULL, NULL, "CEP register tests on all cores");
CEP_ADD_RUN(4,cepLockTest, 0xFFFFFFFF, run_cepLockTest, NULL, NULL, "CEP single lock test (all cores)");
@@ -602,6 +603,7 @@ int cep_init_run(void)
CEP_ADD_RUN(6,cep_MD5 , 0xFFFFFFFF, run_cep_MD5 , NULL, NULL, "CEP MD5 test (single core)");
CEP_ADD_RUN(6,cep_RSA , 0xFFFFFFFF, run_cep_RSA , NULL, NULL, "CEP RSA test (single core)");
CEP_ADD_RUN(6,cep_SHA256 , 0xFFFFFFFF, run_cep_SHA256 , NULL, NULL, "CEP SHA256 test (single core)");
+ CEP_ADD_RUN(6,cepMultiThread , 0xFFFFFFFF, run_cepMultiThread , NULL, NULL, "CEP multi-thread per core (all cores)");
//
//
// must do this
@@ -795,11 +797,15 @@ int cep_index2testId(int index) {
//
//
//
-int _thr_errCnt[MAX_CORES];
+#define MAX_THREADS 128
+int _thr_errCnt[MAX_THREADS];
void cep_set_thr_errCnt(int value) {
int cpu= sched_getcpu();
_thr_errCnt[cpu] = value;
}
+void cep_set_mthr_errCnt(int thrId,int value) {
+ _thr_errCnt[thrId] = value;
+}
int cep_get_thr_errCnt(void) {
int cpu= sched_getcpu();
return _thr_errCnt[cpu];
@@ -836,12 +842,13 @@ int run_multiThreads(int coreMask) { // , cep_thread_funct_t funct) {
int errCnt = 0;
constexpr unsigned num_threads = MAX_CORES;
// A mutex ensures orderly access to std::cout from multiple threads.
- //std::mutex iomutex;
+ std::mutex liomutex;
std::vector threads(num_threads);
for (unsigned i = 0; i < num_threads; ++i) {
if ((1 << i) & coreMask) {
_thr_errCnt[i] = 0; // clear the error
threads[i] = std::thread(cep_get_thr_function(), i);
+ std::this_thread::sleep_for(std::chrono::milliseconds(20)); // ?? need to??
//
// Create a cpu_set_t object representing a set of CPUs. Clear it and mark
// only CPU i as set.
@@ -851,8 +858,13 @@ int run_multiThreads(int coreMask) { // , cep_thread_funct_t funct) {
CPU_SET(i, &cpuset);
int rc = pthread_setaffinity_np(threads[i].native_handle(), sizeof(cpu_set_t), &cpuset);
if (rc != 0) {
+ std::lock_guard iolock(liomutex);
std::cerr << "Error calling pthread_setaffinity_np: " << rc << "\n";
+#if 0
+ // perhaps the htread already finish?? when use with strace
+ _thr_errCnt[i]++;
errCnt++;
+#endif
}
}
}
@@ -876,3 +888,23 @@ int run_multiThreads(int coreMask) { // , cep_thread_funct_t funct) {
return errCnt;
}
+int run_multiThreadFloats(int num_threads) {
+ int errCnt = 0;
+ // A mutex ensures orderly access to std::cout from multiple threads.
+ //std::mutex iomutex;
+ std::vector threads(num_threads);
+ for (int i = 0; i < num_threads; ++i) {
+ _thr_errCnt[i] = 0; // clear the error
+ threads[i] = std::thread(cep_get_thr_function(), i); // thrId > 0
+ std::this_thread::sleep_for(std::chrono::milliseconds(20)); // ?? need to??
+ }
+ for (int i = 0; i < num_threads; ++i) {
+ //if (threads[i].joinable()) {
+ threads[i].join();
+ //}
+ // get error
+ if (_thr_errCnt[i]) { errCnt++; }
+
+ }
+ return errCnt;
+}
diff --git a/cosim/drivers/linux/cep_run.h b/cosim/drivers/linux/cep_run.h
index ef3e649..99545b7 100644
--- a/cosim/drivers/linux/cep_run.h
+++ b/cosim/drivers/linux/cep_run.h
@@ -106,6 +106,7 @@ typedef enum {
RUN_cepMaskromTest,
// RUN_cepCsrTest,
RUN_cepSrotErrTest,
+// RUN_cepPlicPrioIntrTest,
//
RUN_cepMacroMix , // multi-threaded
RUN_cep_AES ,
@@ -117,6 +118,7 @@ typedef enum {
RUN_cep_MD5 ,
RUN_cep_RSA ,
RUN_cep_SHA256 ,
+ RUN_cepMultiThread,
//
RUN_ddr3Test ,
RUN_dcacheCoherency,
@@ -192,8 +194,10 @@ extern "C" {
void cep_set_thr_function(cep_thread_funct_t funct);
cep_thread_funct_t cep_get_thr_function(void);
void cep_set_thr_errCnt(int value);
+ void cep_set_mthr_errCnt(int thrId,int value);
int cep_get_thr_errCnt(void);
int run_multiThreads(int coreMask); // , cep_thread_funct_t funct);
+ int run_multiThreadFloats(int num_threads);
int thr_waitTilLock(int id, int maxTO);
// =============================
diff --git a/cosim/drivers/linux/cep_vars.cc b/cosim/drivers/linux/cep_vars.cc
index da58149..da910c3 100644
--- a/cosim/drivers/linux/cep_vars.cc
+++ b/cosim/drivers/linux/cep_vars.cc
@@ -134,6 +134,7 @@ int cep_init_vars(void)
CEP_ADD_VAR(curErrCnt, 1, 0, NULL, "current error count");
CEP_ADD_VAR(lockSeed, 1, 0, NULL, "1=seed is locked, 0=seed is random");
CEP_ADD_VAR(maxErr, 1, 1, NULL, "max number of errors before stop test");
+ CEP_ADD_VAR(maxThreads, 1,32, NULL, "max number of threads");
CEP_ADD_VAR(regress, 1, 0, NULL, "1=regress mode on, 0=off");
CEP_ADD_VAR(quit, 1, 0, NULL, "1=quit cep_test");
CEP_ADD_VAR(seed, 1, 0, NULL, "random seed uses for every test");
diff --git a/cosim/drivers/linux/cep_vars.h b/cosim/drivers/linux/cep_vars.h
index 4d2d759..07e3f91 100644
--- a/cosim/drivers/linux/cep_vars.h
+++ b/cosim/drivers/linux/cep_vars.h
@@ -76,7 +76,8 @@ typedef enum {
VAR_lockSeed,
VAR_loop,
VAR_mloop,
- VAR_maxErr,
+ VAR_maxErr,
+ VAR_maxThreads,
VAR_prompt,
VAR_quit,
VAR_regress,
diff --git a/cosim/drivers/linux/strace/Config.in b/cosim/drivers/linux/strace/Config.in
new file mode 100644
index 0000000..ac6fa65
--- /dev/null
+++ b/cosim/drivers/linux/strace/Config.in
@@ -0,0 +1,8 @@
+config BR2_PACKAGE_STRACE
+ bool "strace"
+ help
+ A useful diagnostic, instructional, and debugging tool.
+ Allows you to track what system calls a program makes
+ while it is running.
+
+ http://strace.io/files/5.11
diff --git a/cosim/drivers/linux/strace/README b/cosim/drivers/linux/strace/README
new file mode 100644
index 0000000..abbcde3
--- /dev/null
+++ b/cosim/drivers/linux/strace/README
@@ -0,0 +1,9 @@
+# This directory is the latest strace for RISCV. 5.11
+
+The released version 4.11 under software/freedom-u-sdk/buildroot/package/strace is old and NOT supported. And it is no longer reside where it is supposed to be.
+
+To enable the build, remove the old directory and replace with this new one and add a line to :
+
+software/freedom-u-sdk/conf/buildroot_initramfs_config
+
+as such : BR2_PACKAGE_STRACE=y
diff --git a/cosim/drivers/linux/strace/strace.mk b/cosim/drivers/linux/strace/strace.mk
new file mode 100644
index 0000000..2bf0ec1
--- /dev/null
+++ b/cosim/drivers/linux/strace/strace.mk
@@ -0,0 +1,26 @@
+################################################################################
+#
+# strace
+#
+################################################################################
+
+#STRACE_VERSION = 4.11
+#STRACE_SOURCE = strace-$(STRACE_VERSION).tar.xz
+#STRACE_SITE = http://downloads.sourceforge.net/project/strace/strace/$(STRACE_VERSION)
+STRACE_VERSION = 5.11
+STRACE_SOURCE = strace-$(STRACE_VERSION).tar.xz
+STRACE_SITE = http://strace.io/files/$(STRACE_VERSION)
+STRACE_LICENSE = BSD-3c
+STRACE_LICENSE_FILES = COPYING
+
+STRACE_CONF_ENV = \
+ ac_cv_header_linux_if_packet_h=yes \
+ ac_cv_header_linux_netlink_h=yes
+
+define STRACE_REMOVE_STRACE_GRAPH
+ rm -f $(TARGET_DIR)/usr/bin/strace-graph
+endef
+
+STRACE_POST_INSTALL_TARGET_HOOKS += STRACE_REMOVE_STRACE_GRAPH
+
+$(eval $(autotools-package))
diff --git a/cosim/drivers/vectors/aes_playback.h b/cosim/drivers/vectors/aes_playback.h
index 965bf60..02e474a 100644
--- a/cosim/drivers/vectors/aes_playback.h
+++ b/cosim/drivers/vectors/aes_playback.h
@@ -3,7 +3,7 @@
//
// This file is auto-generated for test: aes. Do not modify!!!
//
-// Generated on: Apr 13 2021 10:26:26
+// Generated on: May 19 2021 14:35:16
//************************************************************************
#ifndef aes_playback_H
#define aes_playback_H
diff --git a/cosim/drivers/vectors/aes_stimulus.txt.gz b/cosim/drivers/vectors/aes_stimulus.txt.gz
index 6dc991a46ed360dba51f632f676f898e070515a8..e94ea2a357573b6f02484560ed46be54d12bf934 100644
GIT binary patch
delta 18
acmX?cmhr?{Mt1pb4i43rr5o7~rU3v&jt27p
delta 18
acmX?cmhr?{Mt1pb4vxarr5o7~rU3v*j0au-
diff --git a/cosim/drivers/vectors/des3_playback.h b/cosim/drivers/vectors/des3_playback.h
index 04766d7..6d401ba 100644
--- a/cosim/drivers/vectors/des3_playback.h
+++ b/cosim/drivers/vectors/des3_playback.h
@@ -3,7 +3,7 @@
//
// This file is auto-generated for test: des3. Do not modify!!!
//
-// Generated on: Apr 13 2021 10:26:26
+// Generated on: May 19 2021 14:35:16
//************************************************************************
#ifndef des3_playback_H
#define des3_playback_H
@@ -1945,335 +1945,335 @@ uint64_t des3_playback[] = {
, RDSPIN_CMD, 0x70040030, 0x0000000000000001, 0xffffffffffffffff, 0x32 // 1919
, RDnCMP_CMD, 0x70040038, 0x1718191a1b1c1d1e // 1920
, WRITE__CMD, 0x70040008, 0x0000000000000000 // 1921
- , WRITE__CMD, 0x70040010, 0xc5cff024f5594b1c // 1922
- , WRITE__CMD, 0x70040018, 0x00bfb09841f3d701 // 1923
- , WRITE__CMD, 0x70040020, 0x00bcab27b6aa27f2 // 1924
- , WRITE__CMD, 0x70040028, 0x00da08ff26019995 // 1925
+ , WRITE__CMD, 0x70040010, 0xffffff7fffffff7f // 1922
+ , WRITE__CMD, 0x70040018, 0x00fffffbffffffbf // 1923
+ , WRITE__CMD, 0x70040020, 0x00fffffbffffffbf // 1924
+ , WRITE__CMD, 0x70040028, 0x00fffffbffffffbf // 1925
, WRITE__CMD, 0x70040000, 0x0000000000000001 // 1926
, WRITE__CMD, 0x70040000, 0x0000000000000000 // 1927
, RDSPIN_CMD, 0x70040030, 0x0000000000000001, 0xffffffffffffffff, 0x32 // 1928
- , RDnCMP_CMD, 0x70040038, 0xfd5f8081e9d4d522 // 1929
+ , RDnCMP_CMD, 0x70040038, 0x6a5b3868f637f87b // 1929
, WRITE__CMD, 0x70040008, 0x0000000000000001 // 1930
- , WRITE__CMD, 0x70040010, 0xfd5f8081e9d4d522 // 1931
+ , WRITE__CMD, 0x70040010, 0x6a5b3868f637f87b // 1931
, WRITE__CMD, 0x70040000, 0x0000000000000001 // 1932
, WRITE__CMD, 0x70040000, 0x0000000000000000 // 1933
, RDSPIN_CMD, 0x70040030, 0x0000000000000001, 0xffffffffffffffff, 0x32 // 1934
- , RDnCMP_CMD, 0x70040038, 0xc5cff024f5594b1c // 1935
+ , RDnCMP_CMD, 0x70040038, 0xffffff7fffffff7f // 1935
, WRITE__CMD, 0x70040008, 0x0000000000000001 // 1936
- , WRITE__CMD, 0x70040010, 0xc79e10013a3f15ee // 1937
- , WRITE__CMD, 0x70040018, 0x00796ecf4aca81f5 // 1938
- , WRITE__CMD, 0x70040020, 0x00c343a80c6d5479 // 1939
- , WRITE__CMD, 0x70040028, 0x00f2c05e3d7e78e2 // 1940
+ , WRITE__CMD, 0x70040010, 0xffffff7fffffff7f // 1937
+ , WRITE__CMD, 0x70040018, 0x00fffffbffffffbf // 1938
+ , WRITE__CMD, 0x70040020, 0x00fffffbffffffbf // 1939
+ , WRITE__CMD, 0x70040028, 0x00fffffbffffffbf // 1940
, WRITE__CMD, 0x70040000, 0x0000000000000001 // 1941
, WRITE__CMD, 0x70040000, 0x0000000000000000 // 1942
, RDSPIN_CMD, 0x70040030, 0x0000000000000001, 0xffffffffffffffff, 0x32 // 1943
- , RDnCMP_CMD, 0x70040038, 0x0074347314123891 // 1944
+ , RDnCMP_CMD, 0x70040038, 0x8248d3fc80a6d3ce // 1944
, WRITE__CMD, 0x70040008, 0x0000000000000000 // 1945
- , WRITE__CMD, 0x70040010, 0x0074347314123891 // 1946
+ , WRITE__CMD, 0x70040010, 0x8248d3fc80a6d3ce // 1946
, WRITE__CMD, 0x70040000, 0x0000000000000001 // 1947
, WRITE__CMD, 0x70040000, 0x0000000000000000 // 1948
, RDSPIN_CMD, 0x70040030, 0x0000000000000001, 0xffffffffffffffff, 0x32 // 1949
- , RDnCMP_CMD, 0x70040038, 0xc79e10013a3f15ee // 1950
+ , RDnCMP_CMD, 0x70040038, 0xffffff7fffffff7f // 1950
, WRITE__CMD, 0x70040008, 0x0000000000000000 // 1951
- , WRITE__CMD, 0x70040010, 0x4b52700d30885f1f // 1952
- , WRITE__CMD, 0x70040018, 0x00b378116c4ac999 // 1953
- , WRITE__CMD, 0x70040020, 0x00e4ce80cb267af5 // 1954
- , WRITE__CMD, 0x70040028, 0x006e1f38921d8c60 // 1955
+ , WRITE__CMD, 0x70040010, 0xffffff7fffffff7f // 1952
+ , WRITE__CMD, 0x70040018, 0x00fffffbffffffbf // 1953
+ , WRITE__CMD, 0x70040020, 0x00fffffbffffffbf // 1954
+ , WRITE__CMD, 0x70040028, 0x00fffffbffffffbf // 1955
, WRITE__CMD, 0x70040000, 0x0000000000000001 // 1956
, WRITE__CMD, 0x70040000, 0x0000000000000000 // 1957
, RDSPIN_CMD, 0x70040030, 0x0000000000000001, 0xffffffffffffffff, 0x32 // 1958
- , RDnCMP_CMD, 0x70040038, 0xcd63552acc7cbebf // 1959
+ , RDnCMP_CMD, 0x70040038, 0x6a5b3868f637f87b // 1959
, WRITE__CMD, 0x70040008, 0x0000000000000001 // 1960
- , WRITE__CMD, 0x70040010, 0xcd63552acc7cbebf // 1961
+ , WRITE__CMD, 0x70040010, 0x6a5b3868f637f87b // 1961
, WRITE__CMD, 0x70040000, 0x0000000000000001 // 1962
, WRITE__CMD, 0x70040000, 0x0000000000000000 // 1963
, RDSPIN_CMD, 0x70040030, 0x0000000000000001, 0xffffffffffffffff, 0x32 // 1964
- , RDnCMP_CMD, 0x70040038, 0x4b52700d30885f1f // 1965
+ , RDnCMP_CMD, 0x70040038, 0xffffff7fffffff7f // 1965
, WRITE__CMD, 0x70040008, 0x0000000000000001 // 1966
- , WRITE__CMD, 0x70040010, 0x75429efd58706705 // 1967
- , WRITE__CMD, 0x70040018, 0x00936f07be83cde4 // 1968
- , WRITE__CMD, 0x70040020, 0x00f2eeb802845377 // 1969
- , WRITE__CMD, 0x70040028, 0x00521e3138fb7c89 // 1970
+ , WRITE__CMD, 0x70040010, 0xffffff7fffffff7f // 1967
+ , WRITE__CMD, 0x70040018, 0x00fffffbffffffbf // 1968
+ , WRITE__CMD, 0x70040020, 0x00fffffbffffffbf // 1969
+ , WRITE__CMD, 0x70040028, 0x00fffffbffffffbf // 1970
, WRITE__CMD, 0x70040000, 0x0000000000000001 // 1971
, WRITE__CMD, 0x70040000, 0x0000000000000000 // 1972
, RDSPIN_CMD, 0x70040030, 0x0000000000000001, 0xffffffffffffffff, 0x32 // 1973
- , RDnCMP_CMD, 0x70040038, 0x633fa731c9c3a509 // 1974
+ , RDnCMP_CMD, 0x70040038, 0x8248d3fc80a6d3ce // 1974
, WRITE__CMD, 0x70040008, 0x0000000000000000 // 1975
- , WRITE__CMD, 0x70040010, 0x633fa731c9c3a509 // 1976
+ , WRITE__CMD, 0x70040010, 0x8248d3fc80a6d3ce // 1976
, WRITE__CMD, 0x70040000, 0x0000000000000001 // 1977
, WRITE__CMD, 0x70040000, 0x0000000000000000 // 1978
, RDSPIN_CMD, 0x70040030, 0x0000000000000001, 0xffffffffffffffff, 0x32 // 1979
- , RDnCMP_CMD, 0x70040038, 0x75429efd58706705 // 1980
+ , RDnCMP_CMD, 0x70040038, 0xffffff7fffffff7f // 1980
, WRITE__CMD, 0x70040008, 0x0000000000000000 // 1981
- , WRITE__CMD, 0x70040010, 0xcf85240b8a3bdd2c // 1982
- , WRITE__CMD, 0x70040018, 0x0027eaf5dbb331e1 // 1983
- , WRITE__CMD, 0x70040020, 0x00afef6088ac1277 // 1984
- , WRITE__CMD, 0x70040028, 0x0085c3417c385474 // 1985
+ , WRITE__CMD, 0x70040010, 0xffffff7fffffff7f // 1982
+ , WRITE__CMD, 0x70040018, 0x00fffffbffffffbf // 1983
+ , WRITE__CMD, 0x70040020, 0x00fffffbffffffbf // 1984
+ , WRITE__CMD, 0x70040028, 0x00fffffbffffffbf // 1985
, WRITE__CMD, 0x70040000, 0x0000000000000001 // 1986
, WRITE__CMD, 0x70040000, 0x0000000000000000 // 1987
, RDSPIN_CMD, 0x70040030, 0x0000000000000001, 0xffffffffffffffff, 0x32 // 1988
- , RDnCMP_CMD, 0x70040038, 0xd9a91fde527bf193 // 1989
+ , RDnCMP_CMD, 0x70040038, 0x6a5b3868f637f87b // 1989
, WRITE__CMD, 0x70040008, 0x0000000000000001 // 1990
- , WRITE__CMD, 0x70040010, 0xd9a91fde527bf193 // 1991
+ , WRITE__CMD, 0x70040010, 0x6a5b3868f637f87b // 1991
, WRITE__CMD, 0x70040000, 0x0000000000000001 // 1992
, WRITE__CMD, 0x70040000, 0x0000000000000000 // 1993
, RDSPIN_CMD, 0x70040030, 0x0000000000000001, 0xffffffffffffffff, 0x32 // 1994
- , RDnCMP_CMD, 0x70040038, 0xcf85240b8a3bdd2c // 1995
+ , RDnCMP_CMD, 0x70040038, 0xffffff7fffffff7f // 1995
, WRITE__CMD, 0x70040008, 0x0000000000000001 // 1996
- , WRITE__CMD, 0x70040010, 0xcd6fcf188f8c2cd3 // 1997
- , WRITE__CMD, 0x70040018, 0x003ca11f9d5e7d72 // 1998
- , WRITE__CMD, 0x70040020, 0x00a5c05f45a67c90 // 1999
- , WRITE__CMD, 0x70040028, 0x00571ddfa8d20ffe // 2000
+ , WRITE__CMD, 0x70040010, 0xffffff7fffffff7f // 1997
+ , WRITE__CMD, 0x70040018, 0x00fffffbffffffbf // 1998
+ , WRITE__CMD, 0x70040020, 0x00fffffbffffffbf // 1999
+ , WRITE__CMD, 0x70040028, 0x00fffffbffffffbf // 2000
, WRITE__CMD, 0x70040000, 0x0000000000000001 // 2001
, WRITE__CMD, 0x70040000, 0x0000000000000000 // 2002
, RDSPIN_CMD, 0x70040030, 0x0000000000000001, 0xffffffffffffffff, 0x32 // 2003
- , RDnCMP_CMD, 0x70040038, 0x422f23eca990ee83 // 2004
+ , RDnCMP_CMD, 0x70040038, 0x8248d3fc80a6d3ce // 2004
, WRITE__CMD, 0x70040008, 0x0000000000000000 // 2005
- , WRITE__CMD, 0x70040010, 0x422f23eca990ee83 // 2006
+ , WRITE__CMD, 0x70040010, 0x8248d3fc80a6d3ce // 2006
, WRITE__CMD, 0x70040000, 0x0000000000000001 // 2007
, WRITE__CMD, 0x70040000, 0x0000000000000000 // 2008
, RDSPIN_CMD, 0x70040030, 0x0000000000000001, 0xffffffffffffffff, 0x32 // 2009
- , RDnCMP_CMD, 0x70040038, 0xcd6fcf188f8c2cd3 // 2010
+ , RDnCMP_CMD, 0x70040038, 0xffffff7fffffff7f // 2010
, WRITE__CMD, 0x70040008, 0x0000000000000000 // 2011
- , WRITE__CMD, 0x70040010, 0xc200b800ec4d8928 // 2012
- , WRITE__CMD, 0x70040018, 0x008ddd971169b09b // 2013
- , WRITE__CMD, 0x70040020, 0x0075e15f4738f9ff // 2014
- , WRITE__CMD, 0x70040028, 0x008ff35fe3283465 // 2015
+ , WRITE__CMD, 0x70040010, 0xffffff7fffffff7f // 2012
+ , WRITE__CMD, 0x70040018, 0x00fffffbffffffbf // 2013
+ , WRITE__CMD, 0x70040020, 0x00fffffbffffffbf // 2014
+ , WRITE__CMD, 0x70040028, 0x00fffffbffffffbf // 2015
, WRITE__CMD, 0x70040000, 0x0000000000000001 // 2016
, WRITE__CMD, 0x70040000, 0x0000000000000000 // 2017
, RDSPIN_CMD, 0x70040030, 0x0000000000000001, 0xffffffffffffffff, 0x32 // 2018
- , RDnCMP_CMD, 0x70040038, 0x8bb99ad043348ff0 // 2019
+ , RDnCMP_CMD, 0x70040038, 0x6a5b3868f637f87b // 2019
, WRITE__CMD, 0x70040008, 0x0000000000000001 // 2020
- , WRITE__CMD, 0x70040010, 0x8bb99ad043348ff0 // 2021
+ , WRITE__CMD, 0x70040010, 0x6a5b3868f637f87b // 2021
, WRITE__CMD, 0x70040000, 0x0000000000000001 // 2022
, WRITE__CMD, 0x70040000, 0x0000000000000000 // 2023
, RDSPIN_CMD, 0x70040030, 0x0000000000000001, 0xffffffffffffffff, 0x32 // 2024
- , RDnCMP_CMD, 0x70040038, 0xc200b800ec4d8928 // 2025
+ , RDnCMP_CMD, 0x70040038, 0xffffff7fffffff7f // 2025
, WRITE__CMD, 0x70040008, 0x0000000000000001 // 2026
- , WRITE__CMD, 0x70040010, 0x7af8f2c9067d64de // 2027
- , WRITE__CMD, 0x70040018, 0x000946514392fc81 // 2028
- , WRITE__CMD, 0x70040020, 0x002009415b604e62 // 2029
- , WRITE__CMD, 0x70040028, 0x001994d6f280d968 // 2030
+ , WRITE__CMD, 0x70040010, 0xffffff7fffffff7f // 2027
+ , WRITE__CMD, 0x70040018, 0x00fffffbffffffbf // 2028
+ , WRITE__CMD, 0x70040020, 0x00fffffbffffffbf // 2029
+ , WRITE__CMD, 0x70040028, 0x00fffffbffffffbf // 2030
, WRITE__CMD, 0x70040000, 0x0000000000000001 // 2031
, WRITE__CMD, 0x70040000, 0x0000000000000000 // 2032
, RDSPIN_CMD, 0x70040030, 0x0000000000000001, 0xffffffffffffffff, 0x32 // 2033
- , RDnCMP_CMD, 0x70040038, 0x7995eca3130c9598 // 2034
+ , RDnCMP_CMD, 0x70040038, 0x8248d3fc80a6d3ce // 2034
, WRITE__CMD, 0x70040008, 0x0000000000000000 // 2035
- , WRITE__CMD, 0x70040010, 0x7995eca3130c9598 // 2036
+ , WRITE__CMD, 0x70040010, 0x8248d3fc80a6d3ce // 2036
, WRITE__CMD, 0x70040000, 0x0000000000000001 // 2037
, WRITE__CMD, 0x70040000, 0x0000000000000000 // 2038
, RDSPIN_CMD, 0x70040030, 0x0000000000000001, 0xffffffffffffffff, 0x32 // 2039
- , RDnCMP_CMD, 0x70040038, 0x7af8f2c9067d64de // 2040
+ , RDnCMP_CMD, 0x70040038, 0xffffff7fffffff7f // 2040
, WRITE__CMD, 0x70040008, 0x0000000000000000 // 2041
- , WRITE__CMD, 0x70040010, 0xda3cf5c3d225df2f // 2042
- , WRITE__CMD, 0x70040018, 0x00c222f628ee9291 // 2043
- , WRITE__CMD, 0x70040020, 0x005d7988261eab12 // 2044
- , WRITE__CMD, 0x70040028, 0x0030bf576125230e // 2045
+ , WRITE__CMD, 0x70040010, 0xffffff7fffffff7f // 2042
+ , WRITE__CMD, 0x70040018, 0x00fffffbffffffbf // 2043
+ , WRITE__CMD, 0x70040020, 0x00fffffbffffffbf // 2044
+ , WRITE__CMD, 0x70040028, 0x00fffffbffffffbf // 2045
, WRITE__CMD, 0x70040000, 0x0000000000000001 // 2046
, WRITE__CMD, 0x70040000, 0x0000000000000000 // 2047
, RDSPIN_CMD, 0x70040030, 0x0000000000000001, 0xffffffffffffffff, 0x32 // 2048
- , RDnCMP_CMD, 0x70040038, 0x2c1dab7faa69f8d0 // 2049
+ , RDnCMP_CMD, 0x70040038, 0x6a5b3868f637f87b // 2049
, WRITE__CMD, 0x70040008, 0x0000000000000001 // 2050
- , WRITE__CMD, 0x70040010, 0x2c1dab7faa69f8d0 // 2051
+ , WRITE__CMD, 0x70040010, 0x6a5b3868f637f87b // 2051
, WRITE__CMD, 0x70040000, 0x0000000000000001 // 2052
, WRITE__CMD, 0x70040000, 0x0000000000000000 // 2053
, RDSPIN_CMD, 0x70040030, 0x0000000000000001, 0xffffffffffffffff, 0x32 // 2054
- , RDnCMP_CMD, 0x70040038, 0xda3cf5c3d225df2f // 2055
+ , RDnCMP_CMD, 0x70040038, 0xffffff7fffffff7f // 2055
, WRITE__CMD, 0x70040008, 0x0000000000000001 // 2056
- , WRITE__CMD, 0x70040010, 0x008f10d34d077630 // 2057
- , WRITE__CMD, 0x70040018, 0x008c25a721572c1a // 2058
- , WRITE__CMD, 0x70040020, 0x00d90b56b8b7c1ff // 2059
- , WRITE__CMD, 0x70040028, 0x00b5d79042efdbe2 // 2060
+ , WRITE__CMD, 0x70040010, 0xffffff7fffffff7f // 2057
+ , WRITE__CMD, 0x70040018, 0x00fffffbffffffbf // 2058
+ , WRITE__CMD, 0x70040020, 0x00fffffbffffffbf // 2059
+ , WRITE__CMD, 0x70040028, 0x00fffffbffffffbf // 2060
, WRITE__CMD, 0x70040000, 0x0000000000000001 // 2061
, WRITE__CMD, 0x70040000, 0x0000000000000000 // 2062
, RDSPIN_CMD, 0x70040030, 0x0000000000000001, 0xffffffffffffffff, 0x32 // 2063
- , RDnCMP_CMD, 0x70040038, 0x618b2af2028942af // 2064
+ , RDnCMP_CMD, 0x70040038, 0x8248d3fc80a6d3ce // 2064
, WRITE__CMD, 0x70040008, 0x0000000000000000 // 2065
- , WRITE__CMD, 0x70040010, 0x618b2af2028942af // 2066
+ , WRITE__CMD, 0x70040010, 0x8248d3fc80a6d3ce // 2066
, WRITE__CMD, 0x70040000, 0x0000000000000001 // 2067
, WRITE__CMD, 0x70040000, 0x0000000000000000 // 2068
, RDSPIN_CMD, 0x70040030, 0x0000000000000001, 0xffffffffffffffff, 0x32 // 2069
- , RDnCMP_CMD, 0x70040038, 0x008f10d34d077630 // 2070
+ , RDnCMP_CMD, 0x70040038, 0xffffff7fffffff7f // 2070
, WRITE__CMD, 0x70040008, 0x0000000000000000 // 2071
- , WRITE__CMD, 0x70040010, 0x91723f13d9ffc5f9 // 2072
- , WRITE__CMD, 0x70040018, 0x008f877864000ffc // 2073
- , WRITE__CMD, 0x70040020, 0x00d21f06a166c602 // 2074
- , WRITE__CMD, 0x70040028, 0x006232f7749ceef4 // 2075
+ , WRITE__CMD, 0x70040010, 0xffffff7fffffff7f // 2072
+ , WRITE__CMD, 0x70040018, 0x00fffffbffffffbf // 2073
+ , WRITE__CMD, 0x70040020, 0x00fffffbffffffbf // 2074
+ , WRITE__CMD, 0x70040028, 0x00fffffbffffffbf // 2075
, WRITE__CMD, 0x70040000, 0x0000000000000001 // 2076
, WRITE__CMD, 0x70040000, 0x0000000000000000 // 2077
, RDSPIN_CMD, 0x70040030, 0x0000000000000001, 0xffffffffffffffff, 0x32 // 2078
- , RDnCMP_CMD, 0x70040038, 0xcf1410b3d0efeba7 // 2079
+ , RDnCMP_CMD, 0x70040038, 0x6a5b3868f637f87b // 2079
, WRITE__CMD, 0x70040008, 0x0000000000000001 // 2080
- , WRITE__CMD, 0x70040010, 0xcf1410b3d0efeba7 // 2081
+ , WRITE__CMD, 0x70040010, 0x6a5b3868f637f87b // 2081
, WRITE__CMD, 0x70040000, 0x0000000000000001 // 2082
, WRITE__CMD, 0x70040000, 0x0000000000000000 // 2083
, RDSPIN_CMD, 0x70040030, 0x0000000000000001, 0xffffffffffffffff, 0x32 // 2084
- , RDnCMP_CMD, 0x70040038, 0x91723f13d9ffc5f9 // 2085
+ , RDnCMP_CMD, 0x70040038, 0xffffff7fffffff7f // 2085
, WRITE__CMD, 0x70040008, 0x0000000000000001 // 2086
- , WRITE__CMD, 0x70040010, 0x8df3cf0c22133700 // 2087
- , WRITE__CMD, 0x70040018, 0x00389f86951edf71 // 2088
- , WRITE__CMD, 0x70040020, 0x00b644b9370d5df2 // 2089
- , WRITE__CMD, 0x70040028, 0x00f9ea062652db6b // 2090
+ , WRITE__CMD, 0x70040010, 0xffffff7fffffff7f // 2087
+ , WRITE__CMD, 0x70040018, 0x00fffffbffffffbf // 2088
+ , WRITE__CMD, 0x70040020, 0x00fffffbffffffbf // 2089
+ , WRITE__CMD, 0x70040028, 0x00fffffbffffffbf // 2090
, WRITE__CMD, 0x70040000, 0x0000000000000001 // 2091
, WRITE__CMD, 0x70040000, 0x0000000000000000 // 2092
, RDSPIN_CMD, 0x70040030, 0x0000000000000001, 0xffffffffffffffff, 0x32 // 2093
- , RDnCMP_CMD, 0x70040038, 0xa8f8bf83c894bf51 // 2094
+ , RDnCMP_CMD, 0x70040038, 0x8248d3fc80a6d3ce // 2094
, WRITE__CMD, 0x70040008, 0x0000000000000000 // 2095
- , WRITE__CMD, 0x70040010, 0xa8f8bf83c894bf51 // 2096
+ , WRITE__CMD, 0x70040010, 0x8248d3fc80a6d3ce // 2096
, WRITE__CMD, 0x70040000, 0x0000000000000001 // 2097
, WRITE__CMD, 0x70040000, 0x0000000000000000 // 2098
, RDSPIN_CMD, 0x70040030, 0x0000000000000001, 0xffffffffffffffff, 0x32 // 2099
- , RDnCMP_CMD, 0x70040038, 0x8df3cf0c22133700 // 2100
+ , RDnCMP_CMD, 0x70040038, 0xffffff7fffffff7f // 2100
, WRITE__CMD, 0x70040008, 0x0000000000000000 // 2101
- , WRITE__CMD, 0x70040010, 0x7d5973da02fa58dd // 2102
- , WRITE__CMD, 0x70040018, 0x003eb906845827e4 // 2103
- , WRITE__CMD, 0x70040020, 0x00e9f5702850886d // 2104
- , WRITE__CMD, 0x70040028, 0x0000e7e0b5fed01a // 2105
+ , WRITE__CMD, 0x70040010, 0xffffff7fffffff7f // 2102
+ , WRITE__CMD, 0x70040018, 0x00fffffbffffffbf // 2103
+ , WRITE__CMD, 0x70040020, 0x00fffffbffffffbf // 2104
+ , WRITE__CMD, 0x70040028, 0x00fffffbffffffbf // 2105
, WRITE__CMD, 0x70040000, 0x0000000000000001 // 2106
, WRITE__CMD, 0x70040000, 0x0000000000000000 // 2107
, RDSPIN_CMD, 0x70040030, 0x0000000000000001, 0xffffffffffffffff, 0x32 // 2108
- , RDnCMP_CMD, 0x70040038, 0xb155057db25e12d2 // 2109
+ , RDnCMP_CMD, 0x70040038, 0x6a5b3868f637f87b // 2109
, WRITE__CMD, 0x70040008, 0x0000000000000001 // 2110
- , WRITE__CMD, 0x70040010, 0xb155057db25e12d2 // 2111
+ , WRITE__CMD, 0x70040010, 0x6a5b3868f637f87b // 2111
, WRITE__CMD, 0x70040000, 0x0000000000000001 // 2112
, WRITE__CMD, 0x70040000, 0x0000000000000000 // 2113
, RDSPIN_CMD, 0x70040030, 0x0000000000000001, 0xffffffffffffffff, 0x32 // 2114
- , RDnCMP_CMD, 0x70040038, 0x7d5973da02fa58dd // 2115
+ , RDnCMP_CMD, 0x70040038, 0xffffff7fffffff7f // 2115
, WRITE__CMD, 0x70040008, 0x0000000000000001 // 2116
- , WRITE__CMD, 0x70040010, 0xe6f81bf3fc459bf8 // 2117
- , WRITE__CMD, 0x70040018, 0x00194527fda406e7 // 2118
- , WRITE__CMD, 0x70040020, 0x00cdba980e43f66a // 2119
- , WRITE__CMD, 0x70040028, 0x004ad39fcd90ce77 // 2120
+ , WRITE__CMD, 0x70040010, 0xffffff7fffffff7f // 2117
+ , WRITE__CMD, 0x70040018, 0x00fffffbffffffbf // 2118
+ , WRITE__CMD, 0x70040020, 0x00fffffbffffffbf // 2119
+ , WRITE__CMD, 0x70040028, 0x00fffffbffffffbf // 2120
, WRITE__CMD, 0x70040000, 0x0000000000000001 // 2121
, WRITE__CMD, 0x70040000, 0x0000000000000000 // 2122
, RDSPIN_CMD, 0x70040030, 0x0000000000000001, 0xffffffffffffffff, 0x32 // 2123
- , RDnCMP_CMD, 0x70040038, 0x55191eceb5837ad1 // 2124
+ , RDnCMP_CMD, 0x70040038, 0x8248d3fc80a6d3ce // 2124
, WRITE__CMD, 0x70040008, 0x0000000000000000 // 2125
- , WRITE__CMD, 0x70040010, 0x55191eceb5837ad1 // 2126
+ , WRITE__CMD, 0x70040010, 0x8248d3fc80a6d3ce // 2126
, WRITE__CMD, 0x70040000, 0x0000000000000001 // 2127
, WRITE__CMD, 0x70040000, 0x0000000000000000 // 2128
, RDSPIN_CMD, 0x70040030, 0x0000000000000001, 0xffffffffffffffff, 0x32 // 2129
- , RDnCMP_CMD, 0x70040038, 0xe6f81bf3fc459bf8 // 2130
+ , RDnCMP_CMD, 0x70040038, 0xffffff7fffffff7f // 2130
, WRITE__CMD, 0x70040008, 0x0000000000000000 // 2131
- , WRITE__CMD, 0x70040010, 0xc38e37ee3a4112ff // 2132
- , WRITE__CMD, 0x70040018, 0x005b6f287217e97f // 2133
- , WRITE__CMD, 0x70040020, 0x00d837674126577a // 2134
- , WRITE__CMD, 0x70040028, 0x00708819046bd075 // 2135
+ , WRITE__CMD, 0x70040010, 0xffffff7fffffff7f // 2132
+ , WRITE__CMD, 0x70040018, 0x00fffffbffffffbf // 2133
+ , WRITE__CMD, 0x70040020, 0x00fffffbffffffbf // 2134
+ , WRITE__CMD, 0x70040028, 0x00fffffbffffffbf // 2135
, WRITE__CMD, 0x70040000, 0x0000000000000001 // 2136
, WRITE__CMD, 0x70040000, 0x0000000000000000 // 2137
, RDSPIN_CMD, 0x70040030, 0x0000000000000001, 0xffffffffffffffff, 0x32 // 2138
- , RDnCMP_CMD, 0x70040038, 0x44408795047f8286 // 2139
+ , RDnCMP_CMD, 0x70040038, 0x6a5b3868f637f87b // 2139
, WRITE__CMD, 0x70040008, 0x0000000000000001 // 2140
- , WRITE__CMD, 0x70040010, 0x44408795047f8286 // 2141
+ , WRITE__CMD, 0x70040010, 0x6a5b3868f637f87b // 2141
, WRITE__CMD, 0x70040000, 0x0000000000000001 // 2142
, WRITE__CMD, 0x70040000, 0x0000000000000000 // 2143
, RDSPIN_CMD, 0x70040030, 0x0000000000000001, 0xffffffffffffffff, 0x32 // 2144
- , RDnCMP_CMD, 0x70040038, 0xc38e37ee3a4112ff // 2145
+ , RDnCMP_CMD, 0x70040038, 0xffffff7fffffff7f // 2145
, WRITE__CMD, 0x70040008, 0x0000000000000001 // 2146
- , WRITE__CMD, 0x70040010, 0xd2397018cd105932 // 2147
- , WRITE__CMD, 0x70040018, 0x003ca20764a5b2fb // 2148
- , WRITE__CMD, 0x70040020, 0x00be03ce04f75eee // 2149
- , WRITE__CMD, 0x70040028, 0x00c69481b6661ce8 // 2150
+ , WRITE__CMD, 0x70040010, 0xffffff7fffffff7f // 2147
+ , WRITE__CMD, 0x70040018, 0x00fffffbffffffbf // 2148
+ , WRITE__CMD, 0x70040020, 0x00fffffbffffffbf // 2149
+ , WRITE__CMD, 0x70040028, 0x00fffffbffffffbf // 2150
, WRITE__CMD, 0x70040000, 0x0000000000000001 // 2151
, WRITE__CMD, 0x70040000, 0x0000000000000000 // 2152
, RDSPIN_CMD, 0x70040030, 0x0000000000000001, 0xffffffffffffffff, 0x32 // 2153
- , RDnCMP_CMD, 0x70040038, 0x606d5c3243e17317 // 2154
+ , RDnCMP_CMD, 0x70040038, 0x8248d3fc80a6d3ce // 2154
, WRITE__CMD, 0x70040008, 0x0000000000000000 // 2155
- , WRITE__CMD, 0x70040010, 0x606d5c3243e17317 // 2156
+ , WRITE__CMD, 0x70040010, 0x8248d3fc80a6d3ce // 2156
, WRITE__CMD, 0x70040000, 0x0000000000000001 // 2157
, WRITE__CMD, 0x70040000, 0x0000000000000000 // 2158
, RDSPIN_CMD, 0x70040030, 0x0000000000000001, 0xffffffffffffffff, 0x32 // 2159
- , RDnCMP_CMD, 0x70040038, 0xd2397018cd105932 // 2160
+ , RDnCMP_CMD, 0x70040038, 0xffffff7fffffff7f // 2160
, WRITE__CMD, 0x70040008, 0x0000000000000000 // 2161
- , WRITE__CMD, 0x70040010, 0x63ad4aed3ddb3d05 // 2162
- , WRITE__CMD, 0x70040018, 0x007572c61032869c // 2163
- , WRITE__CMD, 0x70040020, 0x00bfc12e4936d71e // 2164
- , WRITE__CMD, 0x70040028, 0x00730b37f6951c13 // 2165
+ , WRITE__CMD, 0x70040010, 0xffffff7fffffff7f // 2162
+ , WRITE__CMD, 0x70040018, 0x00fffffbffffffbf // 2163
+ , WRITE__CMD, 0x70040020, 0x00fffffbffffffbf // 2164
+ , WRITE__CMD, 0x70040028, 0x00fffffbffffffbf // 2165
, WRITE__CMD, 0x70040000, 0x0000000000000001 // 2166
, WRITE__CMD, 0x70040000, 0x0000000000000000 // 2167
, RDSPIN_CMD, 0x70040030, 0x0000000000000001, 0xffffffffffffffff, 0x32 // 2168
- , RDnCMP_CMD, 0x70040038, 0x8566bdd72c6504b7 // 2169
+ , RDnCMP_CMD, 0x70040038, 0x6a5b3868f637f87b // 2169
, WRITE__CMD, 0x70040008, 0x0000000000000001 // 2170
- , WRITE__CMD, 0x70040010, 0x8566bdd72c6504b7 // 2171
+ , WRITE__CMD, 0x70040010, 0x6a5b3868f637f87b // 2171
, WRITE__CMD, 0x70040000, 0x0000000000000001 // 2172
, WRITE__CMD, 0x70040000, 0x0000000000000000 // 2173
, RDSPIN_CMD, 0x70040030, 0x0000000000000001, 0xffffffffffffffff, 0x32 // 2174
- , RDnCMP_CMD, 0x70040038, 0x63ad4aed3ddb3d05 // 2175
+ , RDnCMP_CMD, 0x70040038, 0xffffff7fffffff7f // 2175
, WRITE__CMD, 0x70040008, 0x0000000000000001 // 2176
- , WRITE__CMD, 0x70040010, 0x948bca11612ad7cf // 2177
- , WRITE__CMD, 0x70040018, 0x00233a062e11bf91 // 2178
- , WRITE__CMD, 0x70040020, 0x0035176152335892 // 2179
- , WRITE__CMD, 0x70040028, 0x00907cd763f1c380 // 2180
+ , WRITE__CMD, 0x70040010, 0xffffff7fffffff7f // 2177
+ , WRITE__CMD, 0x70040018, 0x00fffffbffffffbf // 2178
+ , WRITE__CMD, 0x70040020, 0x00fffffbffffffbf // 2179
+ , WRITE__CMD, 0x70040028, 0x00fffffbffffffbf // 2180
, WRITE__CMD, 0x70040000, 0x0000000000000001 // 2181
, WRITE__CMD, 0x70040000, 0x0000000000000000 // 2182
, RDSPIN_CMD, 0x70040030, 0x0000000000000001, 0xffffffffffffffff, 0x32 // 2183
- , RDnCMP_CMD, 0x70040038, 0xa2dd80cfc67d79c1 // 2184
+ , RDnCMP_CMD, 0x70040038, 0x8248d3fc80a6d3ce // 2184
, WRITE__CMD, 0x70040008, 0x0000000000000000 // 2185
- , WRITE__CMD, 0x70040010, 0xa2dd80cfc67d79c1 // 2186
+ , WRITE__CMD, 0x70040010, 0x8248d3fc80a6d3ce // 2186
, WRITE__CMD, 0x70040000, 0x0000000000000001 // 2187
, WRITE__CMD, 0x70040000, 0x0000000000000000 // 2188
, RDSPIN_CMD, 0x70040030, 0x0000000000000001, 0xffffffffffffffff, 0x32 // 2189
- , RDnCMP_CMD, 0x70040038, 0x948bca11612ad7cf // 2190
+ , RDnCMP_CMD, 0x70040038, 0xffffff7fffffff7f // 2190
, WRITE__CMD, 0x70040008, 0x0000000000000000 // 2191
- , WRITE__CMD, 0x70040010, 0x1f5898bb0c0102cc // 2192
- , WRITE__CMD, 0x70040018, 0x001e87f7de749992 // 2193
- , WRITE__CMD, 0x70040020, 0x00994686b7ebb963 // 2194
- , WRITE__CMD, 0x70040028, 0x00c80abfe5d59e6e // 2195
+ , WRITE__CMD, 0x70040010, 0xffffff7fffffff7f // 2192
+ , WRITE__CMD, 0x70040018, 0x00fffffbffffffbf // 2193
+ , WRITE__CMD, 0x70040020, 0x00fffffbffffffbf // 2194
+ , WRITE__CMD, 0x70040028, 0x00fffffbffffffbf // 2195
, WRITE__CMD, 0x70040000, 0x0000000000000001 // 2196
, WRITE__CMD, 0x70040000, 0x0000000000000000 // 2197
, RDSPIN_CMD, 0x70040030, 0x0000000000000001, 0xffffffffffffffff, 0x32 // 2198
- , RDnCMP_CMD, 0x70040038, 0x833eca1cc826814e // 2199
+ , RDnCMP_CMD, 0x70040038, 0x6a5b3868f637f87b // 2199
, WRITE__CMD, 0x70040008, 0x0000000000000001 // 2200
- , WRITE__CMD, 0x70040010, 0x833eca1cc826814e // 2201
+ , WRITE__CMD, 0x70040010, 0x6a5b3868f637f87b // 2201
, WRITE__CMD, 0x70040000, 0x0000000000000001 // 2202
, WRITE__CMD, 0x70040000, 0x0000000000000000 // 2203
, RDSPIN_CMD, 0x70040030, 0x0000000000000001, 0xffffffffffffffff, 0x32 // 2204
- , RDnCMP_CMD, 0x70040038, 0x1f5898bb0c0102cc // 2205
+ , RDnCMP_CMD, 0x70040038, 0xffffff7fffffff7f // 2205
, WRITE__CMD, 0x70040008, 0x0000000000000001 // 2206
- , WRITE__CMD, 0x70040010, 0x4ee0a4df67cc0423 // 2207
- , WRITE__CMD, 0x70040018, 0x00dce996c840c86b // 2208
- , WRITE__CMD, 0x70040020, 0x008d7db7ff2c5bec // 2209
- , WRITE__CMD, 0x70040028, 0x00645456a3721574 // 2210
+ , WRITE__CMD, 0x70040010, 0xffffff7fffffff7f // 2207
+ , WRITE__CMD, 0x70040018, 0x00fffffbffffffbf // 2208
+ , WRITE__CMD, 0x70040020, 0x00fffffbffffffbf // 2209
+ , WRITE__CMD, 0x70040028, 0x00fffffbffffffbf // 2210
, WRITE__CMD, 0x70040000, 0x0000000000000001 // 2211
, WRITE__CMD, 0x70040000, 0x0000000000000000 // 2212
, RDSPIN_CMD, 0x70040030, 0x0000000000000001, 0xffffffffffffffff, 0x32 // 2213
- , RDnCMP_CMD, 0x70040038, 0x4a9af705a3ee4616 // 2214
+ , RDnCMP_CMD, 0x70040038, 0x8248d3fc80a6d3ce // 2214
, WRITE__CMD, 0x70040008, 0x0000000000000000 // 2215
- , WRITE__CMD, 0x70040010, 0x4a9af705a3ee4616 // 2216
+ , WRITE__CMD, 0x70040010, 0x8248d3fc80a6d3ce // 2216
, WRITE__CMD, 0x70040000, 0x0000000000000001 // 2217
, WRITE__CMD, 0x70040000, 0x0000000000000000 // 2218
, RDSPIN_CMD, 0x70040030, 0x0000000000000001, 0xffffffffffffffff, 0x32 // 2219
- , RDnCMP_CMD, 0x70040038, 0x4ee0a4df67cc0423 // 2220
+ , RDnCMP_CMD, 0x70040038, 0xffffff7fffffff7f // 2220
, WRITE__CMD, 0x70040008, 0x0000000000000000 // 2221
- , WRITE__CMD, 0x70040010, 0x4a386adde3feddd0 // 2222
- , WRITE__CMD, 0x70040018, 0x00313705f384c117 // 2223
- , WRITE__CMD, 0x70040020, 0x0098e54f85765a7d // 2224
- , WRITE__CMD, 0x70040028, 0x00ddc69721911d16 // 2225
+ , WRITE__CMD, 0x70040010, 0xffffff7fffffff7f // 2222
+ , WRITE__CMD, 0x70040018, 0x00fffffbffffffbf // 2223
+ , WRITE__CMD, 0x70040020, 0x00fffffbffffffbf // 2224
+ , WRITE__CMD, 0x70040028, 0x00fffffbffffffbf // 2225
, WRITE__CMD, 0x70040000, 0x0000000000000001 // 2226
, WRITE__CMD, 0x70040000, 0x0000000000000000 // 2227
, RDSPIN_CMD, 0x70040030, 0x0000000000000001, 0xffffffffffffffff, 0x32 // 2228
- , RDnCMP_CMD, 0x70040038, 0x90406a21187ecbd1 // 2229
+ , RDnCMP_CMD, 0x70040038, 0x6a5b3868f637f87b // 2229
, WRITE__CMD, 0x70040008, 0x0000000000000001 // 2230
- , WRITE__CMD, 0x70040010, 0x90406a21187ecbd1 // 2231
+ , WRITE__CMD, 0x70040010, 0x6a5b3868f637f87b // 2231
, WRITE__CMD, 0x70040000, 0x0000000000000001 // 2232
, WRITE__CMD, 0x70040000, 0x0000000000000000 // 2233
, RDSPIN_CMD, 0x70040030, 0x0000000000000001, 0xffffffffffffffff, 0x32 // 2234
- , RDnCMP_CMD, 0x70040038, 0x4a386adde3feddd0 // 2235
+ , RDnCMP_CMD, 0x70040038, 0xffffff7fffffff7f // 2235
, WRITE__CMD, 0x70040008, 0x0000000000000001 // 2236
- , WRITE__CMD, 0x70040010, 0xa820f3c268acfc12 // 2237
- , WRITE__CMD, 0x70040018, 0x0040c85f22918405 // 2238
- , WRITE__CMD, 0x70040020, 0x00b3bd7fb4d85e76 // 2239
- , WRITE__CMD, 0x70040028, 0x00bfdc4f46571974 // 2240
+ , WRITE__CMD, 0x70040010, 0xffffff7fffffff7f // 2237
+ , WRITE__CMD, 0x70040018, 0x00fffffbffffffbf // 2238
+ , WRITE__CMD, 0x70040020, 0x00fffffbffffffbf // 2239
+ , WRITE__CMD, 0x70040028, 0x00fffffbffffffbf // 2240
, WRITE__CMD, 0x70040000, 0x0000000000000001 // 2241
, WRITE__CMD, 0x70040000, 0x0000000000000000 // 2242
, RDSPIN_CMD, 0x70040030, 0x0000000000000001, 0xffffffffffffffff, 0x32 // 2243
- , RDnCMP_CMD, 0x70040038, 0x2661353bd5f6d1db // 2244
+ , RDnCMP_CMD, 0x70040038, 0x8248d3fc80a6d3ce // 2244
, WRITE__CMD, 0x70040008, 0x0000000000000000 // 2245
- , WRITE__CMD, 0x70040010, 0x2661353bd5f6d1db // 2246
+ , WRITE__CMD, 0x70040010, 0x8248d3fc80a6d3ce // 2246
, WRITE__CMD, 0x70040000, 0x0000000000000001 // 2247
, WRITE__CMD, 0x70040000, 0x0000000000000000 // 2248
, RDSPIN_CMD, 0x70040030, 0x0000000000000001, 0xffffffffffffffff, 0x32 // 2249
- , RDnCMP_CMD, 0x70040038, 0xa820f3c268acfc12 // 2250
+ , RDnCMP_CMD, 0x70040038, 0xffffff7fffffff7f // 2250
};
#define des3_adrBase 0x0070040000
diff --git a/cosim/drivers/vectors/des3_stimulus.txt.gz b/cosim/drivers/vectors/des3_stimulus.txt.gz
index e12e974ec456f4fdcc30d9c3a74478ca369d3f49..296c9f19cad5a3402f989f7354131989d2ff81e1 100644
GIT binary patch
delta 19984
zcmche3pkVi|NlFmRFaBHlT@OEghFFQrKrfMoVKJAl2giQ?oS7FkVT0cwj`utsf1!H
z#Slhesb;b3*@3q@?yPxmp9`}m^4M+9KS+>=wmB&@wU34fxcGs`UKZ+xq4M;+X@9w~A7@IuNy*W8DvF*_4{*=~q
zc7b2w3ySVSNjmcsJ#O2!S*wt4k`6m-8jEm{d_U$cny?(vUq5w
z>fcP;Vbo~ea0`1q$UKYb%Rgx!l5&~in;qvYZrxFq-*%dow{~Um#0azSiMsRJfptZO
zEdE?%wC0kBE36Lt-pIrjf9V=2JR$4kAMi;yA>61+q3w5Fa&K(qnAMrU6bO3(y;+E2
z5yzv^i`Omq;Ivto&!3Hi+U6DByMNT$_h6s$*p-5!Pj7$!LtUR8e=#VYdn*v73EMrA51LS&uSA_QWV$`7^tc?ap5q!h`J{xxMx3BgMF7r-QeXo^e-sot~X^
zqBvd{c7sZBi?(x9iuZSF`BG$)-fXjU)m(m96H1u``g>8*Ek`>}{g*)|LEA_()$T$efrk;xk6p|8;}m70Mn
z`0C^ghfSzyrw0pA^JkBKuQxNf?c1VUw*To!p5ID4m$O_#Smn#M)An=so_?66OvYPP
z9W^*|p)|Q~g7d7~Rl{Y4j)wt@Wl-oj64!_z-{}(J-82fnRuaFge;Z0t7&})mO~+;2
zUhyI;69W}M>!S>(E>!6V4l^1}+;>j#;epk>^_Yp7XeCOm{a&ke{A1$b%Fwk>mih~p
zpFuQ<3ecC6PffAQZao`M5M0JKUe#K@fSTyGf3RzEz?|2kIdLWbpAp5l*!-~2u;FuA
zRR$4Nr(NTz+>+4x2Lhci+^R&K8S-Ox+r0ag(Y5S^d8JF<>$a>(?;7#ns=GU?^w`ZFGyNf1r()HY
zk8W#imXGTaP03B9-!{*kqLUGNOj9^1y0hDIDRi(6;zoF+_rS{I?<<OPCeZn}ho5j|ei3bos99JJN;hJ2~IvQrv3xb^=RXHfh5n
zpV_M;9rAhR7D26cdlB|ejow`pI%2MAS~p|{$7}gK>Z18qEnc|)V7cr3rpBA3cOMD@
zHYn|CW>CrR9J7f#?H0<1cOmaV+dir{N8P`DLFkU@s6MeRYh=b_9#VGg&T^##T0wDL
zm?LZ6Klx
z?ru5_HknTZ;@nZj-8J&j&6%q7me|MB*R?ZbP>A;D&nxdW{d4Wn`IdIWO{aPvxIAAm
zshqFybX#`9%QE0W&F1qDxGkIY-Qx^d1+6xMT%i4d)xmp|aJydr@a;uQ7@V89_e&;A
zzi(=yzeLgGu~8ZuA587W8cud`pqRUerc)8G7wXG4hmKRIGAB5*SC~J-$5OvgLmI=(
z(@%6hr`o+?bRpB|PL{5R8p~^N-UeLGs`V>}coTx5;)n;h$E_^}U9U+axhS2vt$lL4
z4mtF6b(!C*YQ8q{P%)TWAkIGby(%?faqep@wt+pd{L;E*uGv9e0v_+%Mrg$PlzPzf
z_o;I(3OfiW@4U;N?a3NxZ|bqw8X&>n|AYsM&cm{6zs6;cNPLmiolcIPO-|YIcm-~r
zk&i*>P$a){qLICO*+A=~w6mj3Jlk%EYm|llMk}$Ph_e7aKF}DcvS{bv=u!gvIc@0V
zx!$}_5QEV}Y$1=UPCXsC!+U}k#9LY9{#EZ*&9_MVrXdU7T}IOa8Ed7s0KO4JpU7C_
zRIAVV{F>#DXV1I4B*T5<{YE-(q{m@J4i~c9J>xYWYcwADt?c%bf;R6AVc08N7vq(d
z<;t7WPqq$G1;{WB*^FzN^Os)a&DWf0uWI-_AL8%v8Sg40_9zs+yJJwiXJTzc-0dKN
zDBNY?3IioOlZHW27LKyR>1)W)MsX?pz9?LmD>ZJuj$>Q5eDPMJkNcLNta0$zaI|o%W4|65gGy
z0U4V#Zm(aL?hJJ@ip(sJZh2+!`k=4?TXVg0v0oW&zH3=oCwgl`lV|HL
zuh-w^yFH5{lvVX;%rexOzrU&HCAmWuSUO}vzT2?EU`)oi{5sIQWmlZMp&&m>Q$;;z
z^OmyOu924(Ym%PgPd+<=LhdZl}0za-J9{IpQ7~nL958r`y*9p<1W|EyN6J;uHwb0buGl8
zgLw;1i=1%W8=`0R#kkMLHV3O19M0I;>JpW&jK>s?73P%3_MPjFGpJN5Itabh;KIU&
zhx*xfn+}DwvKiSZay+ze+ENI0hudD98oQ1Re;9jzyrRQco79?lR=8)6N%1}{}Qt94i__
zjT?ZxR^-b$QvH*tqPvuYSyeu$6I&{F2$|>t$kXxax6oH|b(2UU4Ut-UHsO@t&M?EI
z(~l-j8oduf>M2b61W?qx*xIkJ1#0CtVL{GSieGE`QB+mT$d<*b%x=Q&eJbH+W02sYlusB
zeX!f(xSS$fX3YQ&XHXxYqFR$}O^gnufqo)8}c`!R-XM)Zh
zHe0TtTZQ51ymQ97mPS=132)|$?)mnhOo1|ZC&>qYxzct$wQGFtbnDS2PhT7>SNqm@
z2RY8YJ)%F&e(08YGp9N1J-T4gwK9h{CI=x3V?Ani;`7GO#k+d2!mqC4>GlRbODgp?
zDo4}$pgFONZMQ7^5J2$Tc_X}`jpN1!FJx*+_!ImKs8Y)Kns2pM@eNZqvpWM{k8AH8gkl{>n~H}<
zWzYrqaPu;q^1Bg3llevrUU2)Fk3;qa1KcF2lF7uT1->|PRQ1(hSS?OiTtC0uYaz7=
zixDIreYw8(-L_|qgZ%FdWY(VAew^U)9M5LqBLpR0vqu5R$WEz~XM&UH3p^FguQIof
zq~Gujt#~WAtw5i>M2-dx7Y}V795q2dw}?pGmzB`mdon5XmcoGi(|dI%ANYQ8Mp1Uq
zo9}mNpJzY6FBExb4woR8CXOdgZXtKf6n9O$mW%#;Zwt~$IpC~O=BBF;KKr4DAjL16*Cj-#^k0hRV+65z4Sma8Rzjf4IP=*UMRQxI+L%TwkS{PvpfMQ_P%dWY^pF(7{5pN#eez-5pOfsbxksb^XXl*
z$}Vd>woE6m#b~qLiSj$2tJ>z`_?VW0rl%qHo*pP7_27%U6-9|w<}3Fl~y
zI8FJ*b;silRLbR2sjRggmQMoFtDtBm^O1_$^FxY?E?(flmrR(Q%O&Y%A-}Rm7;k@j
z;SNZU#)D9rEZ}b|N5Ta4JTeM6-4@o)5s{c8F+rmuf{_Fn+e^%$RV>=%`!7Wkn1Jna
z_pQ&4jos`TF;Lo%b}Vu$mTF=^5RUyVcrb>&YZd&Rxps{Z5PA
za&>%?$YXaSzdJ7uXngkVEPO!QxTDBu0)bn7-@0}UHrma5*l+$5Rr5N#
z(u**aKCxEGx&2aIaAh(#6RE4Rw>0t9)$c|u$STjL>)Sl&P)3)?6djjvY}?Yl!HJ2F
zuQtqk)IFnF1XMCt#Um>3D$1rAKw3}s$K4S|&1Mg2*syMEwEV#B{Xx~TdnhdBqn^5+
zCiBwiVMx-0oyij%<2_r~H
z^~sn6GdZq?@{&MB)$mIuSt)!jl?HhalU|5I)`f++2)Skg0XQGW=Z16IcTTc%#BJTJ
zoc6axZ$%+@xXR;0TPk8~W>4?Ew`lc@PrC)s05n&Dmgc?3W#*c}M0u`u9%V(_Ldu!z;H
z9X`ps>~C>Tv-TJi8~VOb?UO=s$cxZRCBch&WNHlUNxNJ`&>r5jnHG07Er-LxjH(qj
z1U?MCR3-q|W8gPo9z2I`jLw|L&)k4{uoVKYl!(+T6*deIz|z=I1uX03;j{4dmh@X3
zA$7Fe`Eg}eA-D#095Uc!uEmJXiZeSaMtk66?oH|O3yh;Uv)>*PXEN=@nSDaBSaur~
z$*$7={f)&MYeRYe{002}RS2CCp($#gWS#~Vg_%AH5O#ev!a2NWD|vj9%kn$$mT_cb
zV06)^g!`)DjX5DpHyThntXHb!W7vi(@JU;f*-Ok>Q=5o9!~$9U^H(7~^Y1aCZ^NL*
zZZ&I{ev)o{KJS^e=7k;Zff%;|!;=yCFW)dmEV0eF!ftWqHhiNvE4Wdt
zP9<=l8wg~J82bHK?`JYoP~s+_0X~8yWCPi^k^A1$f`DQp)G8Ft1jb4ikE1eI|DpM9
z5@AltONIAafiB3sQuSL7{}&p+tX8RTriBm-!J=LR)&rX0@{;9-D4=(rA+WjTaUT3w
zNp^#!WH+$EJ2%u{fps4Ub_dY322HIp9@Q+)YSDZc%6lm!M5uj|99Mz6e1hjdZ@^a~
zevIGr$9|UFw@@9D-sxW=Z)@)XH~tw`GV;FLle`-Hd}^BAu<@ZV9R=s?MHi@PM%;au
zrxm(h+!Bn*2}xfhXO|=A_;JkB$m)aY6W4mht+*ElyWY519Iq`MJui~xOu2$@t6fLHd3k-0l6-hlz
zzImU11}*3#sUU*JRhZ0Dv)V#rcV1#+MfLIv%6A~JXW0Xp2<`D`{raz8a*V9)Wv}1g
zxR~BF`XuRGNby8>*W(XR;r!dLd97VMnPU%j#IJfND^a!opvFuz)!F5=vWhJBB+$
zNT?BD+r;jHu_B98;w581+L;f;*7s3B)Ygy#Ffd?Z5+i&6K}h&v+3+KN)5c>HtF@^`
ztP!b~36mt|^;6E!AHwc!(IhZrbdU!~yFUDfkHYGc3X-||uBIOMByU|pCSpQ?xkDVg9@+}Uy
z2(nq+S5JujQ_X!XV28l!t_<@M5}vpT2|3^^Lrq9}{m1=E6b@B}h>QL{Nx#p%7&IJ!
z9}B9Vhak4ccsPsoUQ;0;Yh+}T-<~H4umZx`om!&g{jl+zJ^@&
zGGf+mZ1DAZzE202x4Og&r!=dIm|y*NnQ=RPwned=zU>Z3ZP9raV>=4!&r@=^YX4z=
zL+P99mP-$wu1JS>uaj&a&My(TTOEBNJlH4a2=e1A)kI`S0r;%C?!kF~YN0Nkw7U
z8QJpr%i`lJIlPVjUWp$VRxK;2e0IFXt0T2DrxEUujiAjD_kt)Fe%pCzIduoagDk(U18VPbmp<}Q0nmBx|D(o#NW3y|-XEBvA@R{?5b6(VkeK(9GV322
zmvRYg-Yf>=OXwxov!#F{RIdOS0^IgenP|<=rNoYd+mnXJ1;OEa(mt!ohRo4^{mLmrip#(D-MvGh59tQfy*z7Y#IpJN+l
zqMxPNJc#}Fl7&rz^f~kB-AL>CF+PJj`NfvGrtzm!t<(m|VxN9qz>#(I6?!hK3aVux
ze6ZdI%Y6*2+tIRd{?tqa*Gx%&jn6xqAtE`Sd#G*v%xdclC&O@u&m88{lJWvv{R
zrf*agk$onj(~(3X-^IHIrhsS%C_
z!Is?(yxU&Nz&eeDwNlHL2=X~%&kq(!0D9l`9`^1c0>Oek6PkwyZmji_&!ucF#q25q
zc;ycQms+;Oz2WOk3!nV4QT||jV9$ra=78zrrW(NVZHTNIyIVd2fOlM
z_Nh&2kC?Z0sw`r*g_7H|KJ+mOWB|2^LR
z8@Hih8Z`_9dW#0Z9x1nkOE^q&h+t9zv+kfLW^e^-F-?$C^
zTf8l%v=w)k%at6TLRzfpsux`iV$V6PpCI&nFBgsb<=Sr_s}bg{xROqO5K}G!Z2BZmqiu~J`XF-w88*JKaAy(#MW7w;Or@6w%D5UOl*xuF~v&^#XjO+fgy1E
zoQooXCy3No+&}_h2ME?g7F4kT90(4t{SgsD@G5R(3Cu2%y0crxh7RX}$3U#|D>9TU
z{>VjOW`PUNd2M_~^PgbOwT=b#Bn;;Jurb{r6ub%k=T`iWOKnJ={b!{a&d%Hb{Y(~v
zEWr;|gfql%B8#5MJ-ksjJ}Qm{-v38>sKEv$=kL<97}NZpi6OO!+=C5k`|Bi}DCHx?
zOk^MX@lqtdN?X1z`4tT53hI$ios-`lqanO0cIei?Q_WRx{MD}pw?17ecPU}
z=%a|p{jQcbEcdk*D?6VOwXu@CFJV6zO^%Dwta0tEB%(T{ds{Dy9bH6*t*7gNsuX`?Ca?}mYbQv|mT|H*MaTOs{q%k4$6=}nss6^kZb~&{8Ci6<7@R~`$f*hJcC_&9Hizw{8B*c=a^3|?q
zkdt5O-z*GI_pUN~RL>p?&3J*>rY*mEiN~oFI8KQGZR1X-5hHK*TMAntb+XOLcZ$jo
zyM%(Mv9;BhQZ*L?XM{LuMwr6mlf++!*9swmnGlXsIM%h|tSSPC3-$jaPT@uJQGbNO
z=Zo1449u-$3SR(63|uH!^uI@hQY`28@P9^!FQi&N^9*(1kC58M@EY_Z>6XOX(gKr3
z@Mh2a3(M<)Fn6Vf!D+ZO|NDK+mb5mrzLsxzeo<;s+jf>i6gEj2
z$=Ub);JL#%QsmZr9?zN>_cfNV#BFW-nItz99yKSMxG_p8^hp@Vzd560UKa>{7YZ2#
z)dXl2PAzh~qT@zO(`p)p&BorL5oNK=^6d1Uo?xt~-)XP^Rja3tT|tm&8*jTt!8N11
zN;y=Fd2ZZRmu%EA{t#zmU?#1hI^fxy4v`YbV$3ual9WgBA*F77crE~h^1Uh
zmFD09Qv#S(Oi!j(9+SO;W`A+;WnaLsjlX@q$P?-&>Qu
zs6T*cw`ax)v)aYo%IugGh&8u%s~ay5;D()##|Oi*K1BJUic|a=k=7^-nEd$V92HziR7#
zE+poGTD)7SnLL+^N)C2$wmB5O#_hpWI0m0RU3Hm{%J~ZcXIZj(oC0~j?=$eK-NBF$
zTjV|ZI&!+A%(8ikS#(f+rl_j~p~!GzVq2HgTQW*Cbv
zPbZB>&K~FTj4X6;sUy9vU<+~*QZH_Zv7)|Z->(cVuR8dT<>R=3b8iMA&I-T%S0emN
z`9;+%1Qm0&Kg7Ru>eT``B-A@A&tT4;=d(YTRF^hT{$e4fq%8vbzSr(@T{naVZ@
z<`V&k2s3`B!VKjh@gJ?cFPs_z1czus1dA={?1=k#lKv(1Uo8{{N#(^8VA{BfMD21h7t2oA%gaSEW3KO!5+
zPXwAyVgJ>@Y*#oy5&%O_M@t%*KVts_EZX+}bZu>xcaW62{`f_}&Mw*vL)aupP;fLB
zRKAC)Op%DXV}JJAUEdQg!eUpNb@V||n;toY{5ryPSBDb+cJsA#VFC;8(tRlWCukd$3rIT_T2Lc
zq$zFVwY#s5!fA@uxK|hi;*{&!h5Ck*h>{jM!=l*kgn5`%a*WeMFT5~NwE7h(XRF_E
z)+7kN>py+T|Awvn)`RZ?;R+J3)O7r8_O4aB7-cGzdk9T78p~GAzjrU5$>BZqUs^3^
zmVNFPL&*Eo-Tb&?&7`GY0f@m%?MklZiH;A#F}Q-$(H%4>cg=i|zbgmz=ceuN3rGxX
zp!#B=@{UCgb50GKCNMd|)cHFKLu5TsE7k!+e=vDHIVKXr4{4%nSs0e+ow;>7=j&53
zPw=p_aQPd5yg5QO;sTGS;)$e9ti;!RK}T0FX;1FjT`kMv@R(>izCt!XQ2^d}K)vB!dTj
zodbv;dM&o*flmOqOTPj%oM7zU2K`55_&-9E3Z%AN^?_!%ml@-ySiR1)y9+dW7;WXG
z$djCaB>-FT>_9mL?_0Y`L~LN}5x%{t4zl8Klfb?jYu?YD;9VpKBN+Rh
z8?+{VvPl{7wVlC7)*&Ox(r{o4*1JZurS35^WYxH7Fjcg*ry8f)H5P&t+_PL|!HSxt
zEcSMC2ojQe!m3_6d(n3Zia6P(PkWa
zgyQg|iL|rRc;#nfT>{ZCjzE{WBHs4D+n2^dz#B{YfA?*EAN%0pVUwEQb0;v2{3=v0
zNq!=b^!b{Ur(Eq50M3YtJvmqsks4uDJ#ZI~I*=7hh++We@(r9p(
zU`W`s0x|WH|A5Ik)qCTva0>oKmN6}(DP(Mr5{iqMt+aDO$CDoOfeNvpqsysE>s?O`
zr0O1h4bPqg?C`z1OPhliz?rzM-@$64+-BF!*8-bOX3JGFz1TUWUnRpQYiqjcW4$4B
z{F4YMj>GlMyaT@b{I0(a8t>v=shxaNQvN=(KcDx~TGOKaG*{g%J|r59qKpLkow<^m
zH!Yw(6pKW)?|_1YlePKLEe;Oo92$dIW2p#rEVMEe?c?0)M7goGh|nC`okfXWlTLI0Zi}LDgeq4|&ZykYQ+COraU-|2bPpLm
z6P~&2gN6R-SM%G42peR%CsB}`Ib9EQ6AMoeMGW>$D1vdiwb09X+)Xsw0;JPEm%SR?yJV06okv
zys)r#AaZ!v#2P~ab0_^^1jTx}1ygKe$Q0jY0Po&QMg4B|KtSBT=S~czg;tUH3tU(2bSbs)Kk^lr
zs((+iNGeJxz(_z`(jg55c3o(6M1mqc{QtIp`QM=l^v7=hPc~6wSMAYJ^MboRdn;XZ
z;+0}>V6=)5qRQ_#j~sHEmx|_k?A^0EW5(v)A}!^tPL1U%h`?g+VJoh{8G$WmjawcZxmcZ3w3CqaEV8O<
z#++~mdqzexny3<~b4KrIk@!PfYfo8h31m5?ZSkxq7k$AHG}nZYt8DC85WGI^PLXrK
zQ0C>5<9+9C4d@q%3{9WZI_C>jM#=0F8vdEH?L2K_DHysUf}ty@#d-|d&gKS*-8$VT
zQFkV@dc_C(Garhz@1ypL-TXy+#BP15;+LFSv3>AZk4P4Q3>@xwe`U5TKKmjh7I=aq
z;VRG=0VnxT@E8N>OnO)HrCVkb^3Wd(dKeFhIo|0$I&&F*3&w}l2Nq0=JDLUD^SsL;
z7V(-}kI6m>eP5jUNkOrSpn*Bwku^GVRvVR?$(uIaB2M#p0_qT{qwPzN%>4dL@UkV!
zmN)GR#Iyd-6YQ(tH6OesINNvyUW#mbWQGi#rElHTNLY^Y!a`QUjJN0ZD%s-1gC4YETp7
z$jU%3ag7aALgL3npzEiib_r>rxNyqm`56Uf9@_9|$~iEaLR_C-FMepw=b!x?Lf>W{9Exmj-@%*U%;l(L
za|?=X5Crmz3w6mx@!!V-jlfKy6(QVt(WpMeqcDh++LxFjnlcN^9T`!wA8*LUJ{!Js
zW)(XoAMFo@Qw$Cj^)o_4q5T6_-*SUkrm>Y>d=vb+yxku|P>J7AB$Q9;y3GfYUU9jB
zRjzHpwk6L(bgW~J^m5rZ!x{IKYmR(!uj$}_pvr#hDwKV2ju4bJCU*h~6*U?$hal{B
z(%~hU?7Zuyiwh`DD_K20H8Plx7m%q-o49lWbn*v5C%+31)I738NT`O#Q{1dDV0j43
zD-vsGY2FY~Pa^BY_rddyV#o>!siv4Au|(dIr~ECLOC?9lmThYX16Z=Mh$3;ODO3Yg
zC{;J~Q|Bj+q)Ck;t+U$XFtD?oY+f>dLBAXbE`}dg)STrGjGM6R_a2
z+3uuw?_eDxZAtIGi|V_9#BT!a9>IW1U736c{$~`ByyQ}|7`ttyT82ga4(bqqD@r$v
z4+2PiewlTg=EOO%n;-T`DDNU4b%(z(ktKA8(7N~N#_%uf$E@P}k1Y|%
z1O2WMJ9rGHyE>
zlG;UW=GyedCN;(toZu>MOK?!s2K|o(B@Yld9^O&2(O%;~MfDC;nU>g(xwNK&w_a;c
zr?WeRA2;rib9UHk=IkdDeaL2T_r@i7p1IEKhIc`i`tEHzS*HG{5MZW|nRg_;blH7}
z4jViM@@6H4Hr=T>^rE|eU41NqOfqmdlWXu$eakHh5%*+&Wy}Y(EV93gvu?olwzIuE
zF|whC_r?((PC4+2DBO)Vf`)>tRdc-|^?7rvd4bsL{`B!CoLvHmL1CIN2UCS%^`X8g
z%0$gkfBb&%fe@)Vz+y6xbq7Md{i|H@!bZum6>Kc{JOA*pG@&-iRHpMm*sWj2cy$Rb1naf`pCp%}0u
zdr$o=9^q+^n(GzO~`XDTT5-Nk}AX^(ZxF>2g7vL4@IzAdt8l}jW<7RzTZY$
zO1X9(cJcH#b~^{=^LXZQlbZ%E-=LLyz*&!V}aAQ(|lhLirV3Z)40
zL*DDVvdR^X1tx}G3eT)iNRWWXbD&}gk^DvzMT;M%E3s&aSO1v5nuP~O4Wr63ZYH><
zB?gH1=H$Z)1;u&=;O57Xwm;}bPxgs)8~m_waK(3${c?r<09;}#9>5Q5*G%i4PvmCt
z{T5BBf6D+gg6(@7xW|KrW6)~^*wz+&td|7BpkH^)^$wEk<=<=qqlqvd3GN!?gR{_%
z+1WOp&QB2pQ?HKjM8Uw8HxBB_pmE8n-V;9B(djfsLJq~PS>xn*t3@>v!;V>o-=Ffb
z>|M~kFZ{YgbQUn`)*b!Z=z3tHu+bC6O48H{Z|R3dgyURvqE@`3-!iitnk$LX_{nuo
zg-Y4dS)4%F#dB+{4w#)I@wB3O@s32F!!U|sVRe9fUuYw`z;8SxRE^}{Kt`aOJnov^7?6+qXNk+_!s=abFu4=YNp;Bo8UkV
zb;dUvSXPFTG*?SF+&s@Q(3N6Jf23s$rJ=)V+ia$l|6Z=P!|Y;Vq8D`JtPTe
zd>|j~iJZl-?Ao8nzF!f%KRXYqEGZl>q8_pcNdxoX&%P8Myc^AHW%6X4&YX{5^-`8m
zG@PgAc{Hx1%5&sTRae8~;P!!u064=menL0hqE7rR8C3^38wedd>w5@nq4@U)u^Y1$
zC0+p@FhmIvBVlb5AcRmK2t)!Mzvx4OEVF@2g#mN3IU}O{h
z2b==}fgQX4w_txCcR+1&qphr
zs~98Y=e
z%mMSy>j#B~2zEj~I&LcyQEhW_$)r$lqO-6k(!bs>QF}r(%r+Sh9Gd>P*$u6Mz4}#|
zK+dDS2_f7f%9r+qdVP+Zz%W0M9;%go{TgtPPNf
z0$5tZf5vmL|0W>u2ASo*g
zP`W=L`&hjKC|Dnm9)r5`7pK1uvW)wqM%9DB1!qb2OY&?`fI?SB0CbapUpoQVhYQH=
zup<%!w-0umDqM(7I@aj%B=^e5}is(G2*hC8j~p0{qAfk44#|!h(aVrFLQVneddOF*9bFB
zBi66`Ic+*_G7vjAWa-JHc1=u|Jb%(qqq*)f)6b)x(Cthr;VqiIf57pEv9Z4q8uLB5
z5Lorn3>L&2nY7v$-Iu4Vi*W+%eN&JO{}qq0Q-;r<)VDalxV>44o#001ICN?0MXoS4
zNTD8VH1Wu`T~?FFz@7_kT3M>5?3Pk<>f!k+7MhCbFiv|rkbu==gcA+z-#%G#8hsP>
zhp5leS!@xtmeArw?UwYqzkSC&IZq#37+*>?;gD48s7J&C-7Ib?RHGvp#Kf%=B?-N!tG8&ImX
zW)Svd`dL-w#+WY!=DuXnxUab5?}OcW`Cj_e(-<_+0U9j{IYt
zYIO#5RqtZD$Kw%6^O6Uw`s>__EOr}iZ5)LgiEQ<_a*Z3N^AZY$I*iR7Vz;}qSR)CP
zBF>Ym_S`cW(3-Sb7DE9D0qYDph%|Cld{xmwWu;S9|=9FS6@&)rA>)Vi9
znqD4eW6|ll@wexA<8ATHov$>VsvYlAd>Xhtng<`_sC0YN;J
z3=0}fyxFBie%B%Q>uXn*+OW)g#E9hUu1JNvt3Z4kV@Y)l+ii&BK{Gi>y22dJ9?8+n
zX|g=&7mK@ssW1oGE%{Pp+?kkJ61qF=k{0F~W_6VUIQ{b-B}Uf-mxB>(nf{RvD_SScDnfOm;^PHw
zqrI%W4>I6RN@O&V;oJbjkX7T6II2)^F3&wbDJe3O-!MKta!QC4zirCdBmA~w!_E>*
Jl#9WX{{`{fbc+B0
delta 32876
zcmZ^~2{e>(`#)SMibP6MmQaag%ib`d$QIexnWU^qk{HI^A$yFnW*f@B?@I
zvkfNuGR7D)W?uC?@9+Kp&Uydme9xKtd+wQg&dhw~vs~A8*VMBNWt?T=k2rlAUgYV|
z6vTAAis{6KXrShLy$SDGeJzf8xg?`ME!2?LKM@mg#&YUWrnrQ`lPb08S(eL8_7K@|
z=4vY6WR6xy+85WGuWEZR@HHTY>{{Nvk!8=2{V4%H?^b=
zUR+$bv~sH7nMKik3WDC{COi>j8{cKx{UBP@-WO*V#h;GBGs&{+%w5cr@9?3*_QEcj
z89LtW&Up5i@R>bA#`KkpQtGG!Wao9nBC5aA$9mJ!EoS(PK>TwLJ`(B6j$?!SscwNY
zND4)l<2K+d;}A|++^34i{dE33!fiMFW{Tf&VZLI-I?i%@R9s301T-Da9r`5ZCbo1-!b2A=7BngI^S=pZF7fi?s~(;
zrx?tvr*ioLKuZL%l%F*51Du|q*4njJQ8PS12MA>6%|BTJCM}X?I`nn&aV*Ko|4mY5
zQuy6@iQT|jbXWcVx0=G361-puq)2Zt1b`hK()IWdiqlvUYH2a4VCZ?dWj^hA+WwYO
zml)bIAF(k*V3ZKae{^B^=NAS-<+|vsBuJ=hG
ze2Rn*0WX>~uY7KSTp@m#B*>$7?DN0fc;k|oH?mHiz`}$)=5F2>nx5Z7V{r0W&PTU9|
zT`r1pPfs`Y<>IIo_un_!eN}rRwm%6wSuFxdjOlJW
zLD1PYPgb88DM>SmIeqIFT;_qa5mnv*RC(y$aPon=f5pP9>Mngmv&!8!x*99jWz?Pd
zM;)5tptJz6_Zf4e9?phc93jxFRiKa13N^K5*u@KagU)*W8T#nOJB5BOhfLW4t~
zQ6!JUStrPVC!oi9<{eqUZ7WuXg5*_ZivE6ToUV=bdcsAs1
z_x_?x$qVO!$Xw6F#A>3nK1`CGL($>pZj#(#*UT1E0CWD}d*gS9&1r;up?kTk*s;(2
z_(({RKeJ5Ueb;0xDHikM^wU}f2Y2W?9a}>3AYFby$
z{*LR3=StW>)pK^D%-`_tQ!1@(aTY$2FJjKTA~>OTmR^on3T&HvD#gzD@qkZhEVZA1
zc<~
zAn2sLvB?+z^{WZ1sX86E_Y9`1v!pj4oQ+w(5qv#HBXFX;?9kskveoH|Q6RXPU}2}m
z;Rd+3o>p~-G}Ss6WI)9>@+aYYc%QEYOJygn99v)Q=PyBOtYp~OJFZ3(N_!jtG?cvn
z9BnS>`2dwe@*RQchKaY{eoWCu+gToyiAu{t3!0SK1akQH6VKtY+&$z^tmz4PMfrUzcJ}bP4
z&GMTD``$qOGS}wQwYt?}1K!6|isHRflVd{c`C(9$$6uKJ&jK#6No?+jZ(iL-plL^s
zJG5jF^$lnr2Pzs*vVXm}yj91)aT{kv33PqEDW`TqiMZ=vbhul-b`p}PHxZ2*wZMsuT@6vh+wm>
z=9uDk#3wfuv9Qzu$FK%l{TCEvyrP6^i=>`aXQdn#iF_l9ZlqfTOFi|S#@hjj4?UmH
z5&bTZ@ck-46l&1eLi_5u`{l|gGK?CVU8DhbiiRa%w*u&Tzk=_s#WW}L;}0Q-W)}3P
zoSf6Bs%GsD5RKL%S(TsL>YV#s8BE;XAJQZ|_FHV)7e~znZCCAA7!@!1zUG*rHm5N5%wl5}(2&-d`qeB2iBr!K0;~DLGe#
zzW!sN)EoGb5hgmUA-CgB$Au=rwAol07`(`968o)giwR8`&;e&w-h&{4g`cQdS$3D(
zfUxBu@*`UvbBU0+@uD|%t->_9Ank#f(h`~6JQ}uEkoKIjc>Q3t=_yKC@Jig{Z4UK5
zexyU)gN2htwkcARJKJ~>jWPx1u1eLEwOYS{`_U%grT3Ozc>ad-U=h>zBO2<`WNRcz
zo60kXXtT?|Bf0FMJbnA%?&yY%(U~Vwz?a_D)#c}HN9?cPgCQD1UpUM8K6IQ`*+eyz
zL(^01A91wA8P<1}_%_ZQ;7IBJSAq-*M*PL%Oem8AzEG}Szu@pM1{=@2ebvhwuP;_!
z`7eFOHJC+M@UO}&{o6|eM;Jw;R)h2jZ(7bpDzll&O^uX*7FqK@)Dh22Bn@VRcUf=@
zox=i=FE3AQ+o{Z4MW4C;)!M_l?T`SQcH81fzvL<|)RX3DB|(VI;WqV}fTVj1O#P+P
zyS8~lG270lhm-KHm`w@dyzYy)!je-XR-mP#$McK@MGApyy?`Ci43S=v`C?|Y!ehH6
zg9SxOcN=C4W>3QNFu1{=kvRs|=9#?wsOka96WqNVqj(&yqR?QhR{H{SCJKy=TXW?o
z`J|ImcSH`qTs|`2ohqr0?~^}Vg?Iz2<{vDqBQz>iu&Z^Nj#5T<^Iu_54(I2u0AKXC
zZw*4(()V|2
z&UQef{pC!jpTO6L)LMGbn@+`>Dv#Tgmfh*n+Yw*Ke*_uh!&D^
z4|{q@uGHvcg)`<*neF@^2Fo!25yHXCr#Ei>u<-k6iy^XP`4G^OUgmvRTQZLALStv3HWb2ZO9&ZO;)wZxNx8zJ|`ZprmxHD$krq)5P0
z**~C*Gy!iaD68GCuIGdzLg5vv=%a>5X(h-$8MA&N_B^kh$t4yT&!o?142@4ZO)&b2
z#GN>srgg5htSn~rXLo)JWH;dmDD~9RkpX4ZSCoS?42{Wd`MzG9_tHBB2#zkAK9pqj
z#vtM7HUA5^lzQ*i|3NE2!V&*cC~0P4E&+E4r#nIXL3sf;o2#pB^a*F5xBP(U1T>?t
zH9(+n%JX$=B;;5e7{TTpsAF-zl14#Ks)i1Qu!PzC~L~m{ZXXr={&jFhJ}4OnW28w
zS<$VD3yhDnz8y=|N2q?NT89}Taa~825`-^`=`ZU9lTRtH@2EpcxpGZCdU!^KCl*7{
zlHje&t-uXYm=_;GW*TBy|W1aeu*VGEfD9bxKdN=Ns>o6ZT
z5HRRY*)^|biC=K#-TZKL&2#3z@j7g$2Di}&sbk9mz0Qv-u7miXH=h+8t-aFT@HJy6$j7FGIg_tXf^IbMjDXY@+;M*)qxVv3ZqwoyXLX
zfCGOiQ`jh7zWs~XGwgp%W!fM1e8cv1rRD!HD3-BOG4I&kG~wS_?th7g7?=a&?ZG&s
zQUc{w@ORP8LZ5rjH{f#{?*AUagAi$@zqH1fdaodfc8xt((Y1`ijv?g-qp1MU62xP5
zCRrq2g@l8@fL~bxxGS~uSj+W*O*}}x_@Pl!onW~eL64u(+UIoJ!aGV$uZCQ&4?Fce
z!tg>!d~-GV0TPp-RiIX!1lwtxo-b?At?sw&-OxKwL2Zh-J>t@x+kBoF&IhDLiw+O5
zzRt}2-h=h&{`M)=wEg1Hgln<{F_B4ulU;0jE*AlZr#J!5#cOARvRnyRJ}jGJopi=f
zqI=G()q=F0&qfgrU&2GiYhN84ZB7v-|!8w}yCH^etP(tL1+n1N$mpd?r8Mj_PWct*o{j7%E
zg2aPy!{fk3mmA1cBv$j`%LSEi7I{sjVquw^QS-%oYXw%?PQqxy(f-p+>O`eGEq5EOyDJ38fm;d<23?2$z>`BV8%`k3OTGqx1UB_n^p3nawYqvZ
zj;B3v+uBJPlWqPgiUTmDK)0>8=3j0D0ag!lkef_1v#M=;^!s1OwY5)eu&|3@sUnLfH@5M#HMcEO`kN*5wDg3sE-&BS)n~&zaloBV&NIDWpTZJlmdq1T
zAJB&g%88Oc&-2~aRnHzOU`5X|2v|1z%*{Hli2yMx=@_Az{g=UcGlr&3EA4^oHG`NMO;{L1^+lzdd1yVpE38
zn`3o$VuT9tHt_4#697MvVkwor2DSPklN;gb>tO4gMHmtgmYal$~pdwf5L=^jDo_gwUu7wJ_bEf&c
z%0wHLT^8EsQ!f_ve;UmV@;9*o@lcu?`b0BBz}R4CBhWPp_=mjY{ZthYqV7#qxxd36
z%dr6}IS9e6+KCkG=3-u?OKxG-p^1~t?(Zt#oPxYHnr)>ph6ucj*r7W;OKo{TQYVDx
zJ7phn>6OO^FFE`Uix<&E;^%GX3r&$8?~j#kN6Z+V5T9o(T5wwA`ED)Ze9@Q))2Ee3
z^{}%N(uHiHH!Dwg_9SHBwr?Jv|53Xs)4pG>#_y_NgNbmMRCT>dBCf!>B)j(4r@wsrn@duQ=EbJ5#g!+!{5+P*0}d%n1x
zo%iiO(GL!pi6Xf)Y&k&^9!oZK+tSGQeB5IMcy{MwMn{dbu*eZIU$*ayxZ>Wpz#T75o)Cn!(rGnU03i_GpS26j9kyprh#mpUrO@U%s@
ztzV)vE9I7Q%N~M)zHbaDJ8{W6i67r=T;iv+&?wzlLv}#IE`5J_S(OElTwi5K+mRM+
zk4aR2&4H8SUlU==C^zX&XJBbkXT!^Yns_n%cypUb8
z6UZCLa6Y92Y4)y3ty>lk!baV9)t2gphCF3u;$k?g$7Uew8L_88|~yGgn64EtXiT;_>r|>iZi(
z>4-h-5!?-pz0Wv!qwl7In;=5k$FWb{r3U1hsM}aE{7-D>0fN0-C3-qtA$5ji$4t|#GmUDZU>7hzR*hi^f|2>_>0B=StN0`
zqdX+O$+S%)Q~xUYp*(DV-MfiKbKh9cGw*(Up-
z)Y^!=ue=d=D0bJ(MNp9>h@x~h0L?nCLoI$j1>eT;q$A{LuMTBfIX%1wM?h(eB`Xg+
ze^n9JPKOY6I)p#|JaK2ZKW1&mH;usK`{jbOKRLmC&gEcaNeRchok|Ux5ZiLxK~nnV5D&&WqbdRok2*@}
z>~7^>y);5+&QD=)1KljT+_uL(E1&$m_8Q)?_&lGxDNv->OR0BJI7sr(R7_d3@x!o?
zB&J+)&kOqZ{=y$tyqZnnV7L2uyWS`LNKQMRUsma@(48D%XqeSEU~c7VMtNeI=GdOO
zcMLIoH1tjY@3$Nn>P^|c?Hf5n10zOZ`*N$@iu0LpkP35sALexGND}Ms9)Tp@h>OSg$)+N2!EX<
zf*l)k>zR{kVHITh2!L$!ky9G8DdFb1$^W9bB3k;jMxyFiRUEw}?JrVyXsICTJ2Z5a
zNuS_dZm?wfrbu#2!A-Yfc(PJXE4OmF=CB3PE*_v1@jde_KY?X>)-&d~?yE=fSAcE_
z?-yXgO8}HnDye;#GIMZ*NrQ-xrQL;Ogp1o2^UuMm(PhKaBr-uC#;kZF$tm27T{{Pc
z{;oYI)*6xC>OTF**rl*2I87@|{xAzNh7BEc4DWMh)^F@#^8MAi#o9cT?sah*AE+F!
z|0POMm9NpKoe%Hn^+~j@XdX-hfoC~kA}`DV?g_&)6iH-P&K{)9^VLx3Ft*EKH2k}d
zSal1Ldhny}!~1t0u6tL>4*IaVkFU5}k1a7OM0M$`Iu^NI|z$@pO5;v
zv>_bLB2Stb8{gupeO@i42{4`fz5$qq4!{72SdLuZ<$Fiv%+$0U(`mTTynvAAN$)9I
z4>vtw)HpV@a{$DLBqy44f+AvKc$VJ#~!+l%q}tRKC?T;rvE`1>34M|DRw;Ke2Bm`wH6
zWdgj)Y(w4SBx}~;a66hmp6la&!Gh>UQGUrvK$0-P&6Jfl(C=sQgcd=N=!`6XL2C
z9YHFQYsD$(Pb^ql?HqT_#2)%i&lc$hn_tNaE*ij-P;OgKOTCMAwN1Qv@V2QM4ZwcB
zd{rL*Oig3+H)-jl0d1f&nM82gQZv1B{OQJQ55f+yJxDR|X)D>h{fN^MjM`cD`xB!b
z97hWaK%+(p(ee(UjDp*D%_NQ`ai&oKHC<4&IjE*J03Zsd5i(rwVy=f^5O=g6VeWFRpXE9@Z#-
zb5C;%);g(;oi3U+l4qP5>O
z;iwCwyz@F%#{Zp#@+K0%u*GVG=16`l3onc!ycxJS`omqe?f24X!!?OBI__a~ZMK-V
zQ_ynRs&M;t!_?5~iZX$=nvjc4A+mmH}p(v|O%@KcYoDDQ6b$-+%
zH?v!&a{Jnavv1bhB5TNSB+&w6+ie{&`Wc@M?6A#-&0sUhcaU{nZHy;)?(y#7qtBad?M9z!#f<&X`raL_9+
z!uX<5r&=P}68e5VpdS7Fynffc0>d^a)YTmHhM^DjI$kR;Wz-=a9aM17D%IjZ1x(&P
z{5FJsKlu-}ewyb=|Mxx+$W5yUj|xO>q}G?f=u*_2Uix)A
zL-F!W;VpBNNTHO#I2|)xw>TDwd+MztC}KG8%$O-ofwmaP5{8aPv5zqu+W0uVeY^&b
z7Bg&m2{GJTA=Coyy=Uz+lmX6)v2DVbv%cW={yeQvmcIsUV?q@Hu^>fXPxD>BAlvWn
zK}_t&9c1N4%NduJ#dq3{;2qKo}=Ni^LQ@&lTN1bKCS$zt394|NP
zB;qJX&uq&V@CXz&h^slgh}zM3T+nTs`^j=7K(S{vl{IzjTJk|7YS}1F-%h;tJ1}6M
zY2(+;HIh@*QYkVzVAX$9`Hl{QA3NH&l#tfTn8v41`
zY`+hUv;36Q6vx1%B`*ejaXepCzaP!DXQiidAxBi5Wzrpx6B%4k$Qu%u19~ZUh1$x>
z>&DdsH&$v?j=EfMG7Ctp_@Y{8u0YC+Tg>|xb5R0`9BDPAA*mX^+oufmeqh#-np4hs
za{gx*Fo!wARgcx6E>5@V_Y?4-jyfwl8?s{Qy8Lzk*o8
zk46o0xc0oNz8r`d9Gs3ZRZu}?6gZ@G6#nFvU#wonYz07eq;P+j_`b>$eWrk3PLNws
zp}h{s>+mw96pXJ_i>VKzOcCw8aegBmo{xxA+S@j?)~lNp`N8(TE<<{jcPU}erkK}7
zoWM+{ONI2(!tkF04EbN$xyBc78&iMp{Mmma9sEBl6tgoei;n-ZqR4rZSFsr~`6)V$
zf8BsvYv2*H$^u(5`kD;KFZ+epXiUOC=YR_1l)fhA$sAfsY_dWEbfLs!7CxNHDk$qp
z-79kTym>%z2!+w@@^{-nIe?I_^$xD$`%Ftpl9%%$B^yCz!QuM-Lv*n2tttr8_C6XZ
z?PAg2X}-68OCMHYF0aGz{y_8^EJYrs7GQZg($S1trMBS*mfy(1D+9wGRUdvw>nAgq^^*Hc&$cR+F0Bz5_*N^P6h?EN3{~Eu5(v@f%fy6@?oX2OT!Wn|1y=>S
zs|)lg?KF8c@f*P0iRXtEGRKnAkhgyD8em`PzZETFe^1iG$v~LM_@?=3f}B0p!{Sov`DK(k`9jlkUC=
z^kwPiac8Hi$pCUx2UB?8sdx~zi$gnavph>H(vEENNdmZ}^H>(-d|piv+z+KiP8n21
znY!-cXfF*@+I{wWN3IbG1V!e9m8c&Ac4J3<@|PDv$KGZs_mpExe0nc%gh&Wq8090O
zdVHMbp6}mwspJKh+!`BFau1CPCf25zlkb1l9C&XMjH7+`HcuV7Xytpk9p)z&>iI16
z<(k5(N)tfe_W2~z-olyUFfl9v&>E`>M7mWjN9gyp?)^_B|97ytGy5NL|6lBwKvO7L
zHkPaU*k(U5%!ROpKbJmk6cOP-n*tMA)3`R&-x%gO{s!;mzymcKr-ez^S>MP}_mz*%
z&HA8@JR`7spAUs?Z%tO3FdJR1&J(7ca1(V>?YRD{!i_Qx!V7#V`*88o^1Crqk@wYG
z1qV5c*`@>4V1m(frexspB+FJA@5#+065clWG-YK@8QXL5`*rs$&&Y_TtK7;qxqEx<
zbb4>RYz=`h&SS&f~W6l4>
z10bO>BFC?{HPPUDE9dSArnsq%h4SRl>c^Bjot4#Hn%>Q{Yaevv^!gkI2w1n+?*~k$
zqb5vNmGA$QV@KCwUU^dfFR`!1ZmVD;uywb&8CON{Yz
zL5o67H{Xw_kib4KRFviR6ddyn!daL10ot_A+>M*R=x-<7>C!ntich1mIv?Okq-9W|
zk!I$3E*}1wTi+<%jo+o-(~r}+bIKGx6~Sc%rxu0Kl8qM|mHZY9GJfFUXtQ<Z)
zvM2Gn5oGhm>4+4k-WF@H(F?L*fK17P9pZd>lxt`7h&{GJ5~Do!03j
zrz*Q759_~jT{G8QgF8%;fG2U$<$b40ObaTj^Bkxt2^xD+lAOVX-wW6dQ<#bji;mgn
zK9bfaeJ#Khlj@VObT>rhxKQ+toRVlsdgRZ#WN?hL~V=i+;hWa@oj28$d3!U0Mv-q
z`wSfoh=fY|COe6mjW6Lre5i{Vpzmc)#ok9m&0he|#Ghy5*soO{JN;1LgEHep8{2Bd
z7V3)8_(|&mt8ciyQORuSl&XvI7XgJ{N`64H`dyg5D{5xnyP^9*pPhJ)c`<(7PgjGd
z?!$>wk-kw#tesFe>V0iGFrrfed@QM@yhW;B8H7=cas)4&`CL9XwqymGabtLPCaCM_
z7)BU8?RLlOScd>(at1F{;>7OX<8UFup#G_X1Ue-P|?z=A%3GnHB+vcii_>!Vu;)^c|+$eskrXGg#)Nq+|T782L|5decDD=a>xdc
zI?GBijd&H`!~Q|J$O_=yqWY+ANiy{MoxU`Up9K5OB%N2k6KS9C^znO1&Ab1jQ0WB&
z&PyECC;wK64haYU;<(q&?Bq70fiA;VdYQA}+wEGvjnM-}r1#A$XC~4E()njJ8=G&d
z)XLmyhzML;Q3vDo@>QJOlUcKJ^r+(=Y3Cz=C4Z35ijW_5db{_a@^Miyr0?k=fz%`K
z{cCOPLXU}e54a=&PrEVFmC|wv#LpL8w*L2r)pd)%ph)EKs3#+KQ{)+CM~qKmULKo7
ztm(sahPlg`hQ7zTf+uo7rhgRcb6Lz&CuyZfe9TWP&O4c>pH3o*^kEH^-tXt0G6Oe7
zOV_;)$C}RG@hs)U-oJ@~HE}_=0>FdM>R?xPOjLLF_b)OP7;bD|lUi?dQ^5<2`iFXU
zk6+%eZ3qlGbUz`x8C>rZf`u7&c%HE3z}-Lc>JnMqhR2kyj#tyy?dXQth<#9U@<+fMXN0226=ij_;BLLgXIX&;-4V5LLTb@xC8qO5j91>>W>^45EXGERb
zN8Fw(On&w$aZqCt(T5~WPTQLX^bgq;C~SZ+e+n8N>WUh^Wb?0yoUSH
z{+dOc5JzWrd|?~Jdx}qn&uUmVx|O*L<|{0o@vi=4RYj}2GSZ`p=?y0k$zRG-0}dU`
z_Q|-y_cq&oijUpu=I&=ZE9SYkQ>Y@iu(ot^QT~t*6<)cM`pe9h8`7a3uF`XDiEpE46dI(i#kbPL*4R$#{?O*_C@mmSf|ajj
zhl6Uj$40=uy*jtORTldTeQFwe0PmN8?Yl%5GsyAXqv5{XQx+8&6*p&wg?w%O1|FIE
zXiJ}LSCNVvUYR}d50mmlaortFh36lmv{u`Ac@!&&EL^s}p|Q+!ikMLac38z=6na^F_JMv-fzmhq(=QKgY*X-)Z2Is$%q)YvMT<_-z;
zAU8M5?(Ggm-#J_ArPS+DdPdpe+(TOe_28m*ASj3NQpjmV8dWq))Y#(!3K9V{M}*O7wTWRDL^G7@?CsEsdl32{7KFnkuK^iKSz#Z(2m8_bafDxD
z>h=Y)DdV@``-dl~Io~nOB{@7ESAe=6uK(TM{(nc%1HI}0ow7^??Y~3sVqgVsWxeqg
z>~CxI(32k1mGpA2;=1^h?H+>YWxOP9{846q9pfK
zZC_gY>7~XTIC~n=50u?(*@?a1+Pu$sJ|=vxRbWlolHs9}{Z_fqre}4#J58h96Zpw#
zA&HXa2bFdB9?FjXNLPz&1BYJm^f&EBY|W=X6GU&;2jxbSjC
zoPNLnTx?9ER!HeS8r>#eK;6-{vJYrE8eM1GZB}}q`g!O__`i)nu=vFivNaSx>HzJw
zF|aznoLYUD1H}X~xD-EbXTBk{riWPNB5(zw6O5aL2d4Mx5e-la+Jo=1fi7X8u1%{o
zpiOZyh-5n*KE5IvQ%5eRV1!;j_PP0l}O4xy&N&(@ON*
z(+m{lyx&(q(Lb&^BsMGnL(C|R%_#{IjQ+;Y&p%?xVl4Hf%oRvy+m-kxopR^fnSz0L
z#DS(zrZZoMuf>_J{{4KE@fK4W?(Vu=Bn~);&Up2<_^XYj6@1_CH+_R%wpjcOvcs5z?7X16$)pRxX{v3758sgJ
z>b81GP=|EII4)kYi@JPa6-&Z2&h~ItR(i6y47ew=9mbC)FLXG^+z7QZ14s;%fZ35N
zv$tIG+z4JXI|f5M1$SDfU-IGaBo<5WAZ0=udvg3-p@}cQ4qJ$JH$`tA`oM=hUiN!9
z_2N%-Z4<|LW8bRGTj|Hsgv=a2tCYGQ9N-8TNV4F~vyyZ^6nHku
zsqnTW%PI_Zz_>BI4+0zWj4lbR$`77M3SgKxIMBfhxQQjg~F>
z9L`UuRT&EK6LiM%bMa${whJZSYvrs6dHslK#5tE2&K5(0v$ddpu~hXMX;aoO_;t^n
zWAy?s8~QP1tAAFONmqJJ3Nj)5mfdlUGBr=0Q4*%hN2;SX4^)$@Pmp=p%X3{e`0XRi
zI!g$9^B^%x+H(S!c0k<0p1Lj19@9QpDIB#r!=q&U>vbBhTGXa|m|`SL;PuNO$9?SDP-zmooM&HTLm
zPyFv~)3(U}@aML(B7vb02stpDqRdkpo=*`mw0*?Zh3U8E#60Vo19QUB01fcVd5D);3W%|Tr
zONFNSPMFIiBG3(Hw_+@IH)ulf^(1od4ifc2q$H17zrSj1FT}3_a$nxVe8nZKGqr
zCSJCsY+d3YoNlF6lr+^OqYH<=5C*L
zr;HDN*2=0&8iIHcjlrQMzZsG~enM6r&F(hCva{OrBCUWYip6YaZDMzrj-3ua0!C(1
zL1yO&hVaWBmUJH%9(m_e6;A>_U!OlVx9-Ik4g4aRw9^Id3$a&_Vt`rL6?wvGX>ar1
z!d+wA0}r;zLVVeZEn(&!$-Z#f$zi<#S#LxLvga_0jf#5xir?88B4Bv0ca_sF%Jh@L
z^Np1X04U}EW*(bS9Aeh}&}XW#@ZmH4Vk@7P>P$zL509=QOBw#!0w%h@pOlb#CTGW5z0Vf^&%mw(%IC5ZPia)zV$8lz_pTqq
zl6m1el@jfIvetNVP2Vc7b$bJa1^&$h?TE+Vp=`k2u<136X0x}$7BWX%M(jx2s|Nx=kc6n4kMu3
zVc)(%ck`hKBlowX8)E*jK%ja|Z_eCj8*o*bae?IfpLw4+$uYgO+BCxCs&C20CBswG-hoQ<;q@uZ`<$|t7=m;Dd(
zo}I%iF8@xUycK?!@(z-=5Z_#EnfqXdn0)l#S)LJ)7Zbl=ip1@S4ZL<{9ATERnjzMB
zW36JZUY8%4;!(xnw((n2pi%~G@W&TM5_^GU-<981#*0scXWgfty(LX49;-2qz@hi9
z`{EN41*+Xu(n78QgSi*GvTpG}C01N|re4}pEh3iPVJmCvUurECi}2tdtE>V-cdtDC
zNKkN->)_phPfUnK6Sh4!vIc!Vn?-!Ow}RXDltAB4P?kLuKx`xs!~9@A8M>CdaYX)5
zaI0DKCGNGyi7vpA#Zay=z4RcV|7I0xwFmwTJ6{*gXIunS#vPwDjBV=Fco^G;XGG_}+mqM==P!FjEMHAS3*0elI<0Z9j<>Q1av
zdn7;Cl2k>$#pEUKG~NVZ4-tRfOLxSLqPi;X-x0@Y72lQw5K###+iX+JToor2LE@7L
zcnR)?w?^&tNbYxHn8oqBKeu?5>^thiz)jrH#ju}F8l72uH4c6pQPg3}q$id~1Pw?u
zQ5pDxRy`=8g~Ym}a;Sf!Z=xx;VAMAhvgFf4?_&;Bk&4X&AvFGsAZY#ONMDZ7k-z-0
zyIJ<}iaub~z)z~#5PK|`75%Y4it;UwGmY~2l=AO&@KdP$AinX!cf~ofccam;h(W*&
z{1YSwCFE68mlK>@m%LFAFJ+s*`(^r*Yvk0UmxKxxbJYHn+k?(K4$l+)5Oi_ZcVT!&
z!w2KU3i5q^_N$9)k#g}l-;QSRE}it%sL#7>%!WLvMu
zW5UOvkzh6b))pD%H-BqGP3N)p77CZZdJlyD3AOxu5oY?LBVRT8U!_Q*wV;V-6H7X}
zji)qe=ojy0E0v}O2|_&nPP)9~h0Ogm@RB}U5X(_~!m2
zat=HVyf?wP!<5(yTgtohA5)}In=xdZtktP&+n-t|mu@%m@n_Go4!-Xke4Xq@h|ejA
zB@Q)KpLKrjy2*r&cK}4y3yktl#lK78N;Qm9j2O69O*{wgYpT{x2r^dXqR7$L?v&te
zF*qr5gYR(Y6FOK4z&+pMq4FkR*D?)l$}SH)k2A!}L05?TuNQVr9`T1NI41Lx;}b09
zsal|dil>xu1fp3-zaRx+TN!m6KGk^NOpml-YFXR7O~&pPA?I&-zJ4{I
zXCGSKfF&k{SQ5-$^-wDGmG~q&Uq(2oBzsxnaS3NTpT5s*&*5Lg)qLG@XQAqj6+XlebdHK^gwERIrkQ~fRiSWZNQ;mL<@
zd#=d?V}rkamfaQj3iTU44_~)*N=ZYEqW+Cw{J%bNhh~HRFD^HcsDC3w^qc?W7z`wh
zhAV}EH&+XH_qVBgEReRm00ImuEQu&~JLufcy!z|fWz)AU?tDYy$I(khxVMAQU6wQ;
zGB|>TSej@0PngyEnJ#9Sr;duFHkFUs$j=KmzS*HBX|ZmwkKZ^7Z434Fwq5D%HE6+!
zcsYV|>Qwci2$T@rMX&Ix){4&*Wtir;CR)72dUA@+0eOSyeGpqCG#EBnv!1t+q!fn-
zWt<5R;g|8&>O_{=pyz!dCJzvRT5ul2uVR%Y-|3$t=-T4^zRO6gaGY(yNz4L$7Jd*&
z7W1Qe@;#>Ur|1LeK;~fy;k7xvnY`;eUDCz{Z?+pw(eWn_WlrxoAi7rd*rj*|XTytJ
z>B}`B&X*0sj#BBX+r*Dwp6fvyHSWZ)Q3Ca;9HS32?)tplIVzxz?f~<4+4KOJc$Z&)
zoFGa?rl|IwJr)L`0pkoOb7;H|kUF0inyCSIOa16T2F!wq~
zIONntukBm>VaQ6%k7_+jJ*)+n4RlnW-r#)UN(q9`vc>1@RFSP&IkyzBNRzIm&D?yv}a>uZMPAUjZ^wwkJPWKj?C}V+ys^DRBn5OX99;3g(%}smNX1;
zyoH~{#9(;-!zsNu43?aXngVwh-ODzT;DjH2dtr1n{dQYR8`G3z_!tQdr2T7o1Hx`k
zbIMEi&Gj`0-2aj$z~QE~IiMiXVfGKV`t#?-9m9((7{31%b#UltZr@63$V0JzJ@1*|
zkS1O>nrE7O3nPwU(u0~f9m9lf14x0+wO%5T(q3Zfd6_w(
zV$H%8tyR6jDdA{hUP7eUS3W-{8g~6^Z8r+-j7dGtqF_lbYbXdvh;zO+;)i1fr+Ys@_d2D&?BiGWG0K>m+Wv!I
z>LP}Q^$>Txg9!AsFLR=(Aq$}%ca4A1jI?Y==D2I;VkL4%&-5L&!4__g)(H;j(Rf|s}fL8(Kbn)1UNnn0tE!>
z30JK-Th+cJo@GRwu~Vg(^{c%EEV%8ezhmQ>Kg8o0{C!38Ac-*cXV#-!yfWSy=%~Qe
zDt{v@KD51TQcj0Yc4}~I1wY_$h%Kj^peUnhfpeYN9eHB`)voAk`2uIVv3y(R^xrHS
zH60!SomR#lrkoL*6|l3wJ&W&ftV}_<^vZz+T`WdsA)#r&bb|z2CmBU%l_ddjk&p
z+p4}dzyEuKzooBC1hSXse7~Q&=~Z{LNkFJ}FL(|8d;u&OpE_%Qh-*@ReGTWI^{bVTWDQTdK2WbwcWcB{fSjBh~#
zHOGK1{?7kALq}&vB-!T=q%FMc$jaH(9f#JfJJ!ot9s_*#H)o_+RGwK1E{sF)`<1fS
z?YIP>_D=6!f-TKe)Ih)6FXLQ;La?3S;dO0(c<%LOh|f4&Nld|DeQ(H_ureFG6Z2}v
z_DrsUfUBZ8(0K{j$br7H6%@;T9XxlpKkU+KV(q
z9R}p>wV{)5HkIObo&FQBbMx-MzyWj25YjB|)+6=cj{p#X0`nbfI@c_|>;t&PrZV#;
zSG?!?toM0;971PKRc&jdF`79nORx=P2Z)`JwOS_-j#vTerAczl~xkl`*#FD
zFoo;Yk0|`@%-XRq(IyRf*@Bfv$D;{N-(-Vf2>8`g9;Je(WCIRD488jX!!)}z%GbcK
ze|UpkoA;`#X5`51yC}YQO}*>mvu5`YZM~(?v{o!t7{AB
zT62pDJXP~tVQVLO1&fVc5C9Uh*}{I~$<8pBPw5eS|AAf_iq&Kqia$~0--
zMP^?7UgXAL>Yt3-@JWAs^f|}ru=@EAf0toY*+S*WffM!(3GpsHhVb5(EQaecIlcW;
zTVj~_yFcIZvVUHtHP+6K96!MYSJ58|80Mw37bZX+nzTK6KIu9y1WlzpS2eER8KC{%
z1lR&(v3Rt%*SdBzGY_E-6%O4FY;DMXl^3nn0V*@eRGa6>!YJ!5Pb9K$PCS1vrQ;pp
z$2(xh0v?L~B#q#CEFW=-bTAGNr5eZf27LPvrd=!^Pj4!-knQ{*^@+rFiw74Hzn)=VqwV4%DzX$zSDA(!oSI)3yrh6e5G(K2KZ$eF;hpiIo5n^^$cqQZ;IQw4H9N<`7A!wLTm<$YMIWWJqI*XCw_OeeLEv7-zlxL&lxvQUK2=f&TnQqLAF1*-x>;w
zxSelc^Rr-L+L!m`wdjV0T#0cK6K?3GjVFi>7jU8KpphPH(pI->Lh
zJ>7O|ZhJfAhJMzf$+|Y^m?YdDyfSVye9=J~jve)0OYpxWALS2ka0Dj$SQo3jFMR94
z6F1*Boeg?$Z&Q_nR#}@SgZU!OqlXpaPMtxd*~}Ox#IS3<3FyT@U|8%ynV5uA&pU#
zyZLuxGRwG(WIzE4w%a68T_jJUg6;%gy*-*Ve;vy%aG$4mAe9ySs0x_Lq&4%w
z$+Gw#ITixS4*q&N%WMXgl-Z)ykiA_!K*8$e1ymui(d0Ca|5P^5tt7-PEZT>wtyHDf`i}A#^-u?+aJ@yyWVj9@8IwyJa?76Pk1zgeLZ-KjX
z-0XbRzX_jiU2D3U^{BH=09KevsC&Mc;&J9fQ=c$o@x*~j1l;8Hh4FVUb}T?f+yuv3
z;`{3R0a5sgsaT`3p6nTs+{Xxbt>#0Y$0-KJQ#d-1Cw(l;Op)-5sMSiJRJSW+*PZY4
zo+IuTE*S1F8y>fEzCu7Gpz6GZQuE3{c)SP7e3fHJpH4hIG4%C(og+FwZ&|Lar8g*8m;(fR~3;*+~p^ii~_r@2W!~OVKmIE2kKHrdu7RtBnj%`StgOflD
z&*YTad#>xIZ$|8XZ#V|@ke#&jX&t?S3>8#49dvrua2}88HHncS2H9D_vfvZnMJ?%<
z^b}x|5yQwSHuuFNCM0=(7LTryQ&_M~qvlly1me-bBKdFFbZol(_m@4;YOmjPG1*{g
zd-&G%hK^$?272Qoa}twt#keM&T$GQ(Yk804I$8{qN%ixVo5ydhfPSr?+(vnlY9U1{
zD)f}rhb0%?)q?mdyCngCC&U*CyM#Ccn@6K_$?zejzyX-y6RTUl!JFA;iJ*q>14^>c
zMCtBi)ZATUh-mZH4yctA&;8D!*OrDcM^tevQd4rhM4uGYaE#5dzSb_GJL2PD0&}etdLBBa_EWX?%`6;J1mq|Z~_6qrn>DMY*
z`Mv+=z$+DYK>B9bDGH~#I$Rig-wyxoW&nrV3JhMm3Rv;|?anzk=gafU#hw+HHODxL
zA)}Nu5|3YN$riy;c7>~gTF+%~lz&|$(zz3Zqe3#?P
zqUZzC>hi_*WS#?_qEc|Uxgpb|g!>zD{mXu{C+M_v5Q^a~;N-=qF5}fPzil%cDy3%?
z!@6G&0uQ0vOgSMA4mFj%%eVvS!h1|188VWM<^g!--SZRt1ek-+$5Q8&I)7Y1#JIP&
z?OolMbP}o;p=Y>KeE$;vFossg1us9_-~I^*t!XKC0aQ^tVd-}WOY~6;9Yxv>i!D4U
zAp^$J^udCDep&Fwy|h+>YtP^)w?}&oWykwEVW`8x{!tB07%_9=;2f)n7nHR@le>Cv
zhlD%&del*SnB4IN;er4J>h|7v^L~#yrl;F_(>}V676QB_pdSt?TYHWp0#%yE1`U??
zY9RoX85dU_tFB>Cxx7w76=6kb3tP!=f4cD!m<02imihBDR#`=O;&tX;mp0sLm6?-r
zLHWfVV;A9mCo929+G0U5YBe=>l>YYThqi?W2gdzz_Tfw*?rMv_Oevn!oIb`4A-s$#
z(z9Luc1Ny+xMl(UI%Lvn65}7gvYBG{_XdZA%ER>>5Y$Gm&KPuhz{KtVVhC9f|MefS
z?d0r;Z&u$r-ijS+CjD<9T|~3_zZB>-{cHEolwp{AiZLH<{x{8j`9~loi1BW>{2^9|
zE)Lrxdn1NeQs)wf-|Od|3ruMN4SgQG)It8YRr$2zZRJ!R&?G%0k{Qd1>R6QqR?i}X
zFL%a$Mt9i?{{wVUfXgfKIpX9=+W`
zT@auWBAV{J->HXeIK!rX$#hBCCYfb3Ce!|D_rV57%MUzg@=g|e>*x}5=0cqFexDUD
zm(0NHk5X_?Go+xJ1G)?mUMYr+=a9Sc>7n=At`Frqx)?N&D?b^y%<3T-?OfBPhitQM
z{774%t7SV;w6N>m+ih{a>lS
zDr$^81ZX5UY@|x<|0XcV@?wutw}Vb95+~iw4!DkPiRHbHmmDRS!gx`PE4m7om9>ki
z>xhxw0{ZohF(1Uc%fXC!W##LWq=snmGEk50y$Dg|%!s#ra>C6NyE}}udwC^V&xoAb
z2mS>`F!?hw@=w)$y~l}Uj<3?!k1Z`XD$HVlLP*rf?uPe+2|Wd^gu+Kk*kY)|T2P$%
z!8*sE`vsN4*6&j&)(?20Uy935c02V9_8;u+t2#eZiIKPx5R6k@lnl+iG#_amMMGeD
zzbHjIhi4*RZn4%Bq3nx&ZdBaVQdq-u-i|J~fO#AHk+NBv$}t!1_|^DhQ?B_I{Wx!{
zNN}7LA>gL`vo83^D)
z&v4@&yEnAAn{?Lr*Zza{*7J$MZmFd??dI29hvq~f#S^&*egSY&f+*$YL>1zN%eOI!Y4KiK;3nwyfu3Z`
z{O@S)KT^U_kGJ;8UoPIy(-=9d{ap0zS4$tg3rhBjH2iZ)c~w-+V~+0Mi=itnyzzGL
zEO|0H3-Ta
zKZH=Ew|Ru2`uCHYj}M16h136*=wi^_jn|J16oTW)CY${*E=5r(YSL+|-2}t|Bj&en
zC%Xopgce9;Y$Y2yekk_2=$5%AJxOEdy;=>N)tBhptOADatba6QpnNTRFEQUrzzm(Z
z$Rqfi*Sb2u5!$AK%(l4f4q>%yv-G`0kya)c)tTfKOn|7{r_Fb&Z22M%oGBzoXXeur
zS4!9oQi{4O&>eS#Y_tv7HnP14ph?%YU3HlK^VC_8CN9-sMkgiGA~3F$`qcFS4;rgaueDDz#qwh+I2W~6U_L=p*Gkr=bt@CA}e1#=GM#mr88g(
zt00`Zpux#;%4Bi~BO4dbci!!CnOW9MZGMG!hexDyF#jWB${3o?{8GP(snx7UAON2F
zKBcBgI$rweeK*)dt4gZ0l0E8uggW4=MRiV?L9uYc9v3Z~MES0%t8zt_MbN
z73K##%df^2AW?Wb@pgtVJj{@=M5LT*HyK`(CTq4IKG^r0>S_6%ZE6aWo4`Orw
zNBDSHC*J)3s}nQP@5&TeJIK7!vs&)e
zJH3$9K4s;y{u@Z8hz7|F`=oX?j`B?|Nf)NW7Sti06})w_!qDtXoQd8;`eDv1C1@Bn
zD6qyRmp{ec7rUj0EPLJVC4S@nSSqCEDppP3;S(7q9EqnlO(yE(o`Vgcuk1+G1~jsB
z{gAw}mS|pwBf(5ZCrM*7YspmLuY++fsmzBHJTeIgL|42g?b4oHb4L?owqnMLk@M8*Y3C?LuG>ckT)cyECDY-uU6?~zGeQw%usWLOw
zQX;X{_RPcKH1+xyQt-W