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Memory.qsf
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2021 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and any partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details, at
# https://fpgasoftware.intel.com/eula.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 21.1.0 Build 842 10/21/2021 SJ Lite Edition
# Date created = 20:57:51 March 17, 2022
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# Memory_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Intel recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "MAX II"
set_global_assignment -name DEVICE EPM240T100C5
set_global_assignment -name TOP_LEVEL_ENTITY VGA
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 21.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:14:58 MARCH 18, 2022"
set_global_assignment -name LAST_QUARTUS_VERSION "21.1.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
set_global_assignment -name POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR 3.3V
set_global_assignment -name EDA_SIMULATION_TOOL "Questa Intel FPGA (Verilog)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_location_assignment PIN_12 -to clock
set_location_assignment PIN_30 -to hSync
set_location_assignment PIN_33 -to vSync
set_location_assignment PIN_78 -to ramWriteEnable
set_location_assignment PIN_81 -to ramAddress[0]
set_location_assignment PIN_82 -to ramAddress[1]
set_location_assignment PIN_83 -to ramAddress[2]
set_location_assignment PIN_84 -to ramAddress[3]
set_location_assignment PIN_85 -to ramAddress[4]
set_location_assignment PIN_86 -to ramAddress[5]
set_location_assignment PIN_87 -to ramAddress[6]
set_location_assignment PIN_88 -to ramAddress[7]
set_location_assignment PIN_89 -to ramAddress[8]
set_location_assignment PIN_90 -to ramAddress[9]
set_location_assignment PIN_91 -to ramAddress[10]
set_location_assignment PIN_92 -to ramAddress[11]
set_location_assignment PIN_95 -to ramAddress[12]
set_location_assignment PIN_96 -to ramAddress[13]
set_location_assignment PIN_97 -to ramAddress[14]
set_location_assignment PIN_98 -to ramAddress[15]
set_location_assignment PIN_99 -to ramAddress[16]
set_location_assignment PIN_68 -to ramData[0]
set_location_assignment PIN_69 -to ramData[1]
set_location_assignment PIN_70 -to ramData[2]
set_location_assignment PIN_71 -to ramData[3]
set_location_assignment PIN_72 -to ramData[4]
set_location_assignment PIN_73 -to ramData[5]
set_location_assignment PIN_74 -to ramData[6]
set_location_assignment PIN_75 -to ramData[7]
set_global_assignment -name SMART_RECOMPILE ON
set_location_assignment PIN_54 -to mpuData[0]
set_location_assignment PIN_55 -to mpuData[1]
set_location_assignment PIN_56 -to mpuData[2]
set_location_assignment PIN_57 -to mpuData[3]
set_location_assignment PIN_58 -to mpuData[4]
set_location_assignment PIN_61 -to mpuData[5]
set_location_assignment PIN_66 -to mpuData[6]
set_location_assignment PIN_67 -to mpuData[7]
set_location_assignment PIN_43 -to mpuChipSelect
set_location_assignment PIN_42 -to mpuWriteEnable
set_location_assignment PIN_44 -to mpuRegisterSelect[0]
set_location_assignment PIN_47 -to mpuRegisterSelect[1]
set_location_assignment PIN_48 -to mpuRegisterSelect[2]
set_global_assignment -name OPTIMIZATION_MODE BALANCED
set_location_assignment PIN_41 -to videoOutputData[7]
set_location_assignment PIN_40 -to videoOutputData[6]
set_location_assignment PIN_39 -to videoOutputData[5]
set_location_assignment PIN_38 -to videoOutputData[4]
set_location_assignment PIN_37 -to videoOutputData[3]
set_location_assignment PIN_36 -to videoOutputData[2]
set_location_assignment PIN_35 -to videoOutputData[1]
set_location_assignment PIN_34 -to videoOutputData[0]
set_global_assignment -name SYSTEMVERILOG_FILE mcu_interface.sv
set_global_assignment -name SYSTEMVERILOG_FILE memory_manager.sv
set_global_assignment -name SYSTEMVERILOG_FILE video_output.sv
set_global_assignment -name SYSTEMVERILOG_FILE VGA.sv
set_location_assignment PIN_29 -to mpuVideoInterrupt
set_global_assignment -name ENABLE_OCT_DONE OFF
set_global_assignment -name GENERATE_SVF_FILE ON
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
set_global_assignment -name MAX_LABS 24