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0070-drm-phytium-Add-Phytium-Display-Engine-support.patch
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From cf399aa0d2df8047db0ad20dad42ee961d3d3ec7 Mon Sep 17 00:00:00 2001
From: Yang Xun <[email protected]>
Date: Mon, 17 Jun 2024 19:33:06 +0800
Subject: [PATCH 070/150] drm/phytium: Add Phytium Display Engine support
The Phytium chipset and subsequent SoCs share the same display
controller with display ports. Add this driver to support it.
Signed-off-by: Yang Xun <[email protected]>
Signed-off-by: Wang Hao <[email protected]>
Signed-off-by: Yu Da <[email protected]>
Signed-off-by: Liu Tianyu <[email protected]>
Signed-off-by: Li Mingzhe <[email protected]>
Signed-off-by: Liu Tao <[email protected]>
Signed-off-by: Chen Baozi <[email protected]>
Change-Id: I51599872e277f97ecff853d3c621eba6467cb6fd
Signed-off-by: Andrew Powers-Holmes <[email protected]>
---
MAINTAINERS | 1 +
drivers/gpu/drm/Kconfig | 2 +
drivers/gpu/drm/Makefile | 1 +
drivers/gpu/drm/phytium/Kconfig | 10 +
drivers/gpu/drm/phytium/Makefile | 20 +
drivers/gpu/drm/phytium/pe220x_dc.c | 255 ++
drivers/gpu/drm/phytium/pe220x_dc.h | 31 +
drivers/gpu/drm/phytium/pe220x_dp.c | 514 ++++
drivers/gpu/drm/phytium/pe220x_dp.h | 14 +
drivers/gpu/drm/phytium/pe220x_reg.h | 209 ++
drivers/gpu/drm/phytium/phytium_crtc.c | 828 +++++
drivers/gpu/drm/phytium/phytium_crtc.h | 39 +
drivers/gpu/drm/phytium/phytium_debugfs.c | 456 +++
drivers/gpu/drm/phytium/phytium_debugfs.h | 13 +
drivers/gpu/drm/phytium/phytium_display_drv.c | 451 +++
drivers/gpu/drm/phytium/phytium_display_drv.h | 175 ++
drivers/gpu/drm/phytium/phytium_dp.c | 2650 +++++++++++++++++
drivers/gpu/drm/phytium/phytium_dp.h | 156 +
drivers/gpu/drm/phytium/phytium_fb.c | 131 +
drivers/gpu/drm/phytium/phytium_fb.h | 26 +
drivers/gpu/drm/phytium/phytium_fbdev.c | 145 +
drivers/gpu/drm/phytium/phytium_fbdev.h | 13 +
drivers/gpu/drm/phytium/phytium_gem.c | 528 ++++
drivers/gpu/drm/phytium/phytium_gem.h | 43 +
drivers/gpu/drm/phytium/phytium_panel.c | 420 +++
drivers/gpu/drm/phytium/phytium_panel.h | 46 +
drivers/gpu/drm/phytium/phytium_pci.c | 431 +++
drivers/gpu/drm/phytium/phytium_pci.h | 26 +
drivers/gpu/drm/phytium/phytium_plane.c | 672 +++++
drivers/gpu/drm/phytium/phytium_plane.h | 46 +
drivers/gpu/drm/phytium/phytium_platform.c | 308 ++
drivers/gpu/drm/phytium/phytium_platform.h | 18 +
drivers/gpu/drm/phytium/phytium_reg.h | 366 +++
drivers/gpu/drm/phytium/px210_dc.c | 326 ++
drivers/gpu/drm/phytium/px210_dc.h | 30 +
drivers/gpu/drm/phytium/px210_dp.c | 920 ++++++
drivers/gpu/drm/phytium/px210_dp.h | 13 +
drivers/gpu/drm/phytium/px210_reg.h | 349 +++
38 files changed, 10682 insertions(+)
create mode 100644 drivers/gpu/drm/phytium/Kconfig
create mode 100644 drivers/gpu/drm/phytium/Makefile
create mode 100644 drivers/gpu/drm/phytium/pe220x_dc.c
create mode 100644 drivers/gpu/drm/phytium/pe220x_dc.h
create mode 100644 drivers/gpu/drm/phytium/pe220x_dp.c
create mode 100644 drivers/gpu/drm/phytium/pe220x_dp.h
create mode 100644 drivers/gpu/drm/phytium/pe220x_reg.h
create mode 100644 drivers/gpu/drm/phytium/phytium_crtc.c
create mode 100644 drivers/gpu/drm/phytium/phytium_crtc.h
create mode 100644 drivers/gpu/drm/phytium/phytium_debugfs.c
create mode 100644 drivers/gpu/drm/phytium/phytium_debugfs.h
create mode 100644 drivers/gpu/drm/phytium/phytium_display_drv.c
create mode 100644 drivers/gpu/drm/phytium/phytium_display_drv.h
create mode 100644 drivers/gpu/drm/phytium/phytium_dp.c
create mode 100644 drivers/gpu/drm/phytium/phytium_dp.h
create mode 100644 drivers/gpu/drm/phytium/phytium_fb.c
create mode 100644 drivers/gpu/drm/phytium/phytium_fb.h
create mode 100644 drivers/gpu/drm/phytium/phytium_fbdev.c
create mode 100644 drivers/gpu/drm/phytium/phytium_fbdev.h
create mode 100644 drivers/gpu/drm/phytium/phytium_gem.c
create mode 100644 drivers/gpu/drm/phytium/phytium_gem.h
create mode 100644 drivers/gpu/drm/phytium/phytium_panel.c
create mode 100644 drivers/gpu/drm/phytium/phytium_panel.h
create mode 100644 drivers/gpu/drm/phytium/phytium_pci.c
create mode 100644 drivers/gpu/drm/phytium/phytium_pci.h
create mode 100644 drivers/gpu/drm/phytium/phytium_plane.c
create mode 100644 drivers/gpu/drm/phytium/phytium_plane.h
create mode 100644 drivers/gpu/drm/phytium/phytium_platform.c
create mode 100644 drivers/gpu/drm/phytium/phytium_platform.h
create mode 100644 drivers/gpu/drm/phytium/phytium_reg.h
create mode 100644 drivers/gpu/drm/phytium/px210_dc.c
create mode 100644 drivers/gpu/drm/phytium/px210_dc.h
create mode 100644 drivers/gpu/drm/phytium/px210_dp.c
create mode 100644 drivers/gpu/drm/phytium/px210_dp.h
create mode 100644 drivers/gpu/drm/phytium/px210_reg.h
diff --git a/MAINTAINERS b/MAINTAINERS
index c49e14bd230b..5af0776d6c87 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2561,6 +2561,7 @@ F: drivers/char/ipmi/bt_bmc_phytium.c
F: drivers/char/ipmi/kcs_bmc_phytium.c
F: drivers/gpio/gpio-phytium*
F: drivers/gpio/gpio-phytium-sgpio.c
+F: drivers/gpu/drm/phytium/*
F: drivers/hwmon/tacho-phytium.c
F: drivers/hwspinlock/phytium_hwspinlock.c
F: drivers/i2c/busses/i2c-phytium-*
diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
index ec4abf9ff47b..d1cad875d2f7 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
@@ -388,6 +388,8 @@ source "drivers/gpu/drm/solomon/Kconfig"
source "drivers/gpu/drm/sprd/Kconfig"
+source "drivers/gpu/drm/phytium/Kconfig"
+
config DRM_HYPERV
tristate "DRM Support for Hyper-V synthetic video device"
depends on DRM && PCI && MMU && HYPERV
diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
index 215e78e79125..a670c0d95023 100644
--- a/drivers/gpu/drm/Makefile
+++ b/drivers/gpu/drm/Makefile
@@ -198,3 +198,4 @@ obj-$(CONFIG_DRM_HYPERV) += hyperv/
obj-y += solomon/
obj-$(CONFIG_DRM_SPRD) += sprd/
obj-$(CONFIG_DRM_LOONGSON) += loongson/
+obj-$(CONFIG_DRM_PHYTIUM) += phytium/
diff --git a/drivers/gpu/drm/phytium/Kconfig b/drivers/gpu/drm/phytium/Kconfig
new file mode 100644
index 000000000000..3d3e00b14c25
--- /dev/null
+++ b/drivers/gpu/drm/phytium/Kconfig
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+config DRM_PHYTIUM
+ tristate "DRM Support for Phytium Graphics Card"
+ depends on DRM
+ select DRM_KMS_HELPER
+ select FB_IOMEM_HELPERS
+ help
+ Choose this option if you have a phytium graphics card.
+ This driver provides kernel mode setting and buffer management to userspace.
diff --git a/drivers/gpu/drm/phytium/Makefile b/drivers/gpu/drm/phytium/Makefile
new file mode 100644
index 000000000000..1f68cdcd80da
--- /dev/null
+++ b/drivers/gpu/drm/phytium/Makefile
@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+phytium-dc-drm-y := phytium_display_drv.o \
+ phytium_plane.o \
+ phytium_crtc.o \
+ phytium_dp.o \
+ phytium_fb.o \
+ phytium_gem.o \
+ phytium_fbdev.o \
+ phytium_debugfs.o \
+ px210_dp.o \
+ phytium_panel.o \
+ px210_dc.o \
+ phytium_pci.o \
+ pe220x_dp.o \
+ pe220x_dc.o \
+ phytium_platform.o
+
+obj-$(CONFIG_DRM_PHYTIUM) += phytium-dc-drm.o
+CFLAGS_REMOVE_phytium_crtc.o += -mgeneral-regs-only
diff --git a/drivers/gpu/drm/phytium/pe220x_dc.c b/drivers/gpu/drm/phytium/pe220x_dc.c
new file mode 100644
index 000000000000..8f74199f9a47
--- /dev/null
+++ b/drivers/gpu/drm/phytium/pe220x_dc.c
@@ -0,0 +1,255 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Phytium Pe220x display controller DRM driver
+ *
+ * Copyright (C) 2021-2023, Phytium Technology Co., Ltd.
+ */
+
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_atomic.h>
+#include <asm/neon.h>
+#include <linux/delay.h>
+#include "phytium_display_drv.h"
+#include "pe220x_reg.h"
+#include "phytium_crtc.h"
+#include "phytium_plane.h"
+#include "phytium_fb.h"
+#include "phytium_gem.h"
+
+void pe220x_dc_hw_disable(struct drm_crtc *crtc);
+
+static const unsigned int pe220x_primary_formats[] = {
+ DRM_FORMAT_ARGB2101010,
+ DRM_FORMAT_ABGR2101010,
+ DRM_FORMAT_RGBA1010102,
+ DRM_FORMAT_BGRA1010102,
+ DRM_FORMAT_ARGB8888,
+ DRM_FORMAT_ABGR8888,
+ DRM_FORMAT_RGBA8888,
+ DRM_FORMAT_BGRA8888,
+ DRM_FORMAT_XRGB8888,
+ DRM_FORMAT_XBGR8888,
+ DRM_FORMAT_RGBX8888,
+ DRM_FORMAT_BGRX8888,
+ DRM_FORMAT_ARGB4444,
+ DRM_FORMAT_ABGR4444,
+ DRM_FORMAT_RGBA4444,
+ DRM_FORMAT_BGRA4444,
+ DRM_FORMAT_XRGB4444,
+ DRM_FORMAT_XBGR4444,
+ DRM_FORMAT_RGBX4444,
+ DRM_FORMAT_BGRX4444,
+ DRM_FORMAT_ARGB1555,
+ DRM_FORMAT_ABGR1555,
+ DRM_FORMAT_RGBA5551,
+ DRM_FORMAT_BGRA5551,
+ DRM_FORMAT_XRGB1555,
+ DRM_FORMAT_XBGR1555,
+ DRM_FORMAT_RGBX5551,
+ DRM_FORMAT_BGRX5551,
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_BGR565,
+ DRM_FORMAT_YUYV,
+ DRM_FORMAT_UYVY,
+ DRM_FORMAT_NV16,
+ DRM_FORMAT_NV12,
+ DRM_FORMAT_NV21,
+};
+
+static uint64_t pe220x_primary_formats_modifiers[] = {
+ DRM_FORMAT_MOD_LINEAR,
+ DRM_FORMAT_MOD_INVALID
+};
+
+static uint64_t pe220x_cursor_formats_modifiers[] = {
+ DRM_FORMAT_MOD_LINEAR,
+ DRM_FORMAT_MOD_INVALID
+};
+
+static const unsigned int pe220x_cursor_formats[] = {
+ DRM_FORMAT_ARGB8888,
+};
+
+void pe220x_dc_hw_vram_init(struct phytium_display_private *priv, resource_size_t vram_addr,
+ resource_size_t vram_size)
+{
+ uint32_t config;
+ uint32_t group_offset = priv->address_transform_base;
+
+ phytium_writel_reg(priv, (vram_addr & SRC_ADDR_MASK) >> SRC_ADDR_OFFSET,
+ group_offset, PE220X_DC_ADDRESS_TRANSFORM_SRC_ADDR);
+ phytium_writel_reg(priv, (vram_size >> SIZE_OFFSET) | ADDRESS_TRANSFORM_ENABLE,
+ group_offset, PE220X_DC_ADDRESS_TRANSFORM_SIZE);
+ config = phytium_readl_reg(priv, group_offset, PE220X_DC_ADDRESS_TRANSFORM_DST_ADDR);
+ phytium_writel_reg(priv, config, group_offset, PE220X_DC_ADDRESS_TRANSFORM_DST_ADDR);
+}
+
+void pe220x_dc_hw_config_pix_clock(struct drm_crtc *crtc, int clock)
+{
+ struct drm_device *dev = crtc->dev;
+ struct phytium_display_private *priv = dev->dev_private;
+ struct phytium_crtc *phytium_crtc = to_phytium_crtc(crtc);
+ int phys_pipe = phytium_crtc->phys_pipe;
+ int ret = 0;
+
+ /* config pix clock */
+ phytium_writel_reg(priv, FLAG_REQUEST | CMD_PIXEL_CLOCK | (clock & PIXEL_CLOCK_MASK),
+ 0, PE220X_DC_CMD_REGISTER(phys_pipe));
+ ret = phytium_wait_cmd_done(priv, PE220X_DC_CMD_REGISTER(phys_pipe),
+ FLAG_REQUEST, FLAG_REPLY);
+ if (ret < 0)
+ DRM_ERROR("%s: failed to set pixel clock\n", __func__);
+}
+
+void pe220x_dc_hw_reset(struct drm_crtc *crtc)
+{
+ struct drm_device *dev = crtc->dev;
+ struct phytium_display_private *priv = dev->dev_private;
+ struct phytium_crtc *phytium_crtc = to_phytium_crtc(crtc);
+ int config = 0;
+ int phys_pipe = phytium_crtc->phys_pipe;
+
+ /* disable pixel clock for bmc mode */
+ if (phys_pipe == 0)
+ pe220x_dc_hw_disable(crtc);
+
+ config = phytium_readl_reg(priv, 0, PE220X_DC_CLOCK_CONTROL);
+ config &= (~(DC0_CORE_RESET | DC1_CORE_RESET | AXI_RESET | AHB_RESET));
+
+ if (phys_pipe == 0) {
+ phytium_writel_reg(priv, config | DC0_CORE_RESET,
+ 0, PE220X_DC_CLOCK_CONTROL);
+ udelay(20);
+ phytium_writel_reg(priv, config | DC0_CORE_RESET | AXI_RESET,
+ 0, PE220X_DC_CLOCK_CONTROL);
+ udelay(20);
+ phytium_writel_reg(priv, config | DC0_CORE_RESET | AXI_RESET | AHB_RESET,
+ 0, PE220X_DC_CLOCK_CONTROL);
+ udelay(20);
+ phytium_writel_reg(priv, config | DC0_CORE_RESET | AXI_RESET,
+ 0, PE220X_DC_CLOCK_CONTROL);
+ udelay(20);
+ phytium_writel_reg(priv, config | DC0_CORE_RESET,
+ 0, PE220X_DC_CLOCK_CONTROL);
+ udelay(20);
+ phytium_writel_reg(priv, config, 0, PE220X_DC_CLOCK_CONTROL);
+ udelay(20);
+ } else {
+ phytium_writel_reg(priv, config | DC1_CORE_RESET,
+ 0, PE220X_DC_CLOCK_CONTROL);
+ udelay(20);
+ phytium_writel_reg(priv, config | DC1_CORE_RESET | AXI_RESET,
+ 0, PE220X_DC_CLOCK_CONTROL);
+ udelay(20);
+ phytium_writel_reg(priv, config | DC1_CORE_RESET | AXI_RESET | AHB_RESET,
+ 0, PE220X_DC_CLOCK_CONTROL);
+ udelay(20);
+ phytium_writel_reg(priv, config | DC1_CORE_RESET | AXI_RESET,
+ 0, PE220X_DC_CLOCK_CONTROL);
+ udelay(20);
+ phytium_writel_reg(priv, config | DC1_CORE_RESET,
+ 0, PE220X_DC_CLOCK_CONTROL);
+ udelay(20);
+ phytium_writel_reg(priv, config, 0, PE220X_DC_CLOCK_CONTROL);
+ udelay(20);
+ }
+}
+
+void pe220x_dc_hw_disable(struct drm_crtc *crtc)
+{
+ struct drm_device *dev = crtc->dev;
+ struct phytium_display_private *priv = dev->dev_private;
+ struct phytium_crtc *phytium_crtc = to_phytium_crtc(crtc);
+ int config = 0;
+ int phys_pipe = phytium_crtc->phys_pipe;
+
+ /* clear framebuffer */
+ phytium_writel_reg(priv, CLEAR_VALUE_BLACK, priv->dc_reg_base[phys_pipe],
+ PHYTIUM_DC_FRAMEBUFFER_CLEARVALUE);
+ config = phytium_readl_reg(priv, priv->dc_reg_base[phys_pipe],
+ PHYTIUM_DC_FRAMEBUFFER_CONFIG);
+ config |= FRAMEBUFFER_CLEAR;
+ phytium_writel_reg(priv, config, priv->dc_reg_base[phys_pipe],
+ PHYTIUM_DC_FRAMEBUFFER_CONFIG);
+
+ /* disable cursor */
+ config = phytium_readl_reg(priv, priv->dc_reg_base[phys_pipe], PHYTIUM_DC_CURSOR_CONFIG);
+ config = ((config & (~CURSOR_FORMAT_MASK)) | CURSOR_FORMAT_DISABLED);
+ phytium_writel_reg(priv, config, priv->dc_reg_base[phys_pipe], PHYTIUM_DC_CURSOR_CONFIG);
+ mdelay(20);
+
+ /* reset pix clock */
+ pe220x_dc_hw_config_pix_clock(crtc, 0);
+
+ if (phys_pipe == 0) {
+ config = phytium_readl_reg(priv, 0, PE220X_DC_CLOCK_CONTROL);
+ phytium_writel_reg(priv, config | DC0_CORE_RESET, 0, PE220X_DC_CLOCK_CONTROL);
+ udelay(20);
+ phytium_writel_reg(priv, config & (~DC0_CORE_RESET), 0, PE220X_DC_CLOCK_CONTROL);
+ } else {
+ config = phytium_readl_reg(priv, 0, PE220X_DC_CLOCK_CONTROL);
+ phytium_writel_reg(priv, config | DC1_CORE_RESET, 0, PE220X_DC_CLOCK_CONTROL);
+ udelay(20);
+ phytium_writel_reg(priv, config & (~DC1_CORE_RESET), 0, PE220X_DC_CLOCK_CONTROL);
+ }
+ udelay(20);
+}
+
+int pe220x_dc_hw_fb_format_check(const struct drm_mode_fb_cmd2 *mode_cmd, int count)
+{
+ int ret = 0;
+
+ if (mode_cmd->modifier[count] != DRM_FORMAT_MOD_LINEAR) {
+ DRM_ERROR("unsupported fb modifier 0x%llx\n", mode_cmd->modifier[count]);
+ ret = -EINVAL;
+ }
+
+ return ret;
+}
+
+void pe220x_dc_hw_plane_get_primary_format(const uint64_t **format_modifiers,
+ const uint32_t **formats,
+ uint32_t *format_count)
+{
+ *format_modifiers = pe220x_primary_formats_modifiers;
+ *formats = pe220x_primary_formats;
+ *format_count = ARRAY_SIZE(pe220x_primary_formats);
+}
+
+void pe220x_dc_hw_plane_get_cursor_format(const uint64_t **format_modifiers,
+ const uint32_t **formats,
+ uint32_t *format_count)
+{
+ *format_modifiers = pe220x_cursor_formats_modifiers;
+ *formats = pe220x_cursor_formats;
+ *format_count = ARRAY_SIZE(pe220x_cursor_formats);
+}
+
+void pe220x_dc_hw_update_primary_hi_addr(struct drm_plane *plane)
+{
+ struct drm_device *dev = plane->dev;
+ struct phytium_display_private *priv = dev->dev_private;
+ struct phytium_plane *phytium_plane = to_phytium_plane(plane);
+ int phys_pipe = phytium_plane->phys_pipe;
+
+ phytium_writel_reg(priv, (phytium_plane->iova[0] >> PREFIX_SHIFT) & PREFIX_MASK,
+ priv->dc_reg_base[phys_pipe], PE220X_DC_FRAMEBUFFER_Y_HI_ADDRESS);
+
+ phytium_writel_reg(priv, (phytium_plane->iova[1] >> U_PREFIX_SHIFT) & U_PREFIX_MASK,
+ priv->dc_reg_base[phys_pipe], PE220X_DC_FRAMEBUFFER_U_HI_ADDRESS);
+
+ phytium_writel_reg(priv, (phytium_plane->iova[2] >> V_PREFIX_SHIFT) & V_PREFIX_MASK,
+ priv->dc_reg_base[phys_pipe], PE220X_DC_FRAMEBUFFER_V_HI_ADDRESS);
+}
+
+void pe220x_dc_hw_update_cursor_hi_addr(struct drm_plane *plane, uint64_t iova)
+{
+ struct drm_device *dev = plane->dev;
+ struct phytium_display_private *priv = dev->dev_private;
+ struct phytium_plane *phytium_plane = to_phytium_plane(plane);
+ int phys_pipe = phytium_plane->phys_pipe;
+ int config;
+
+ config = ((iova >> CURSOR_PREFIX_SHIFT) & CURSOR_PREFIX_MASK);
+ phytium_writel_reg(priv, config, priv->dc_reg_base[phys_pipe], PE220X_DC_CURSOR_HI_ADDRESS);
+}
diff --git a/drivers/gpu/drm/phytium/pe220x_dc.h b/drivers/gpu/drm/phytium/pe220x_dc.h
new file mode 100644
index 000000000000..f88a054cf0d0
--- /dev/null
+++ b/drivers/gpu/drm/phytium/pe220x_dc.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Phytium Pe220x display controller DRM driver
+ *
+ * Copyright (C) 2021-2023, Phytium Technology Co., Ltd.
+ */
+
+#ifndef __PE220X_DC_H__
+#define __PE220X_DC_H__
+
+#define PE220X_DC_PIX_CLOCK_MAX (594000)
+#define PE220X_DC_HDISPLAY_MAX 3840
+#define PE220X_DC_VDISPLAY_MAX 2160
+#define PE220X_DC_ADDRESS_MASK 0x7f
+
+extern void pe220x_dc_hw_vram_init(struct phytium_display_private *priv,
+ resource_size_t vram_addr,
+ resource_size_t vram_size);
+extern void pe220x_dc_hw_config_pix_clock(struct drm_crtc *crtc, int clock);
+extern void pe220x_dc_hw_disable(struct drm_crtc *crtc);
+extern int pe220x_dc_hw_fb_format_check(const struct drm_mode_fb_cmd2 *mode_cmd, int count);
+extern void pe220x_dc_hw_plane_get_primary_format(const uint64_t **format_modifiers,
+ const uint32_t **formats,
+ uint32_t *format_count);
+extern void pe220x_dc_hw_plane_get_cursor_format(const uint64_t **format_modifiers,
+ const uint32_t **formats,
+ uint32_t *format_count);
+extern void pe220x_dc_hw_update_primary_hi_addr(struct drm_plane *plane);
+extern void pe220x_dc_hw_update_cursor_hi_addr(struct drm_plane *plane, uint64_t iova);
+void pe220x_dc_hw_reset(struct drm_crtc *crtc);
+#endif /* __PE220X_DC_H__ */
diff --git a/drivers/gpu/drm/phytium/pe220x_dp.c b/drivers/gpu/drm/phytium/pe220x_dp.c
new file mode 100644
index 000000000000..54a6e8ac454b
--- /dev/null
+++ b/drivers/gpu/drm/phytium/pe220x_dp.c
@@ -0,0 +1,514 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Phytium display port DRM driver
+ *
+ * Copyright (C) 2021-2023, Phytium Technology Co., Ltd.
+ */
+
+#include "phytium_display_drv.h"
+#include "pe220x_reg.h"
+#include "phytium_dp.h"
+#include "pe220x_dp.h"
+
+static uint8_t pe220x_dp_source_lane_count[2] = {1, 1};
+
+/* [reg][ling_rate 1.62->8.1] */
+static int vco_val[12][4] = {
+ {0x0509, 0x0509, 0x0509, 0x0509}, /* CP_PADJ */
+ {0x0f00, 0x0f00, 0x0f00, 0x0f00}, /* CP_IADJ */
+ {0x0F08, 0x0F08, 0x0F08, 0x0F08}, /* FILT_PADJ */
+ {0x0061, 0x006C, 0x006C, 0x0051}, /* INTDIV */
+ {0x3333, 0x0000, 0x0000, 0x0000}, /* FRACDIVL */
+ {0x0000, 0x0000, 0x0000, 0x0000}, /* FRACDIVH */
+ {0x0042, 0x0048, 0x0048, 0x0036}, /* HIGH_THR */
+ {0x0002, 0x0002, 0x0002, 0x0002}, /* PDIAG_CTRL */
+ {0x0c5e, 0x0c5e, 0x0c5e, 0x0c5e}, /* VCOCAL_PLLCNT_START */
+ {0x00c7, 0x00c7, 0x00c7, 0x00c7}, /* LOCK_PEFCNT */
+ {0x00c7, 0x00c7, 0x00c7, 0x00c7}, /* LOCK_PLLCNT_START */
+ {0x0005, 0x0005, 0x0005, 0x0005}, /* LOCK_PLLCNT_THR */
+};
+
+/* [link_rate][swing][emphasis] */
+static int mgnfs_val[4][4][4] = {
+ /* 1.62Gbps */
+ {
+ {0x0026, 0x001f, 0x0012, 0x0000},
+ {0x0013, 0x0013, 0x0000, 0x0000},
+ {0x0006, 0x0000, 0x0000, 0x0000},
+ {0x0000, 0x0000, 0x0000, 0x0000},
+ },
+ /* 2.7Gbps */
+ {
+ {0x0026, 0x001f, 0x0012, 0x0000},
+ {0x0013, 0x0013, 0x0000, 0x0000},
+ {0x0006, 0x0000, 0x0000, 0x0000},
+ {0x0000, 0x0000, 0x0000, 0x0000},
+ },
+ /* 5.4Gbps */
+ {
+ {0x001f, 0x0013, 0x005, 0x0000},
+ {0x0018, 0x006, 0x0000, 0x0000},
+ {0x000c, 0x0000, 0x0000, 0x0000},
+ {0x0000, 0x0000, 0x0000, 0x0000},
+ },
+ /* 8.1Gbps */
+ {
+ {0x0026, 0x0013, 0x005, 0x0000},
+ {0x0013, 0x006, 0x0000, 0x0000},
+ {0x0006, 0x0000, 0x0000, 0x0000},
+ {0x0000, 0x0000, 0x0000, 0x0000},
+ },
+};
+
+/* [link_rate][swing][emphasis] */
+static int cpost_val[4][4][4] = {
+ /* 1.62Gbps */
+ {
+ {0x0000, 0x0014, 0x0020, 0x002a},
+ {0x0000, 0x0010, 0x001f, 0x0000},
+ {0x0000, 0x0013, 0x0000, 0x0000},
+ {0x0000, 0x0000, 0x0000, 0x0000},
+ },
+ /* 2.7Gbps */
+ {
+ {0x0000, 0x0014, 0x0020, 0x002a},
+ {0x0000, 0x0010, 0x001f, 0x0000},
+ {0x0000, 0x0013, 0x0000, 0x0000},
+ {0x0000, 0x0000, 0x0000, 0x0000},
+ },
+ /* 5.4Gbps */
+ {
+ {0x0005, 0x0014, 0x0022, 0x002e},
+ {0x0000, 0x0013, 0x0020, 0x0000},
+ {0x0000, 0x0013, 0x0000, 0x0000},
+ {0x0000, 0x0000, 0x0000, 0x0000},
+ },
+ /* 8.1Gbps */
+ {
+ {0x0000, 0x0014, 0x0022, 0x002e},
+ {0x0000, 0x0013, 0x0020, 0x0000},
+ {0x0000, 0x0013, 0x0000, 0x0000},
+ {0x0000, 0x0000, 0x0000, 0x0000},
+ },
+};
+
+static int pe220x_dp_hw_set_phy_lane_and_rate(struct phytium_dp_device *phytium_dp,
+ uint8_t link_lane_count, uint32_t link_rate)
+{
+ int port = phytium_dp->port%2;
+ int i = 0, data, tmp, tmp1, index = 0, mask = 0;
+ int timeout = 500, ret = 0;
+
+ /* set pma powerdown */
+ data = 0;
+ for (i = 0; i < phytium_dp->source_max_lane_count; i++)
+ data |= (A3_POWERDOWN3 << (i * A3_POWERDOWN3_SHIFT));
+ phytium_phy_writel(phytium_dp, PE220X_PHY_PMA0_POWER(port), data);
+
+ /* lane pll disable */
+ data = 0;
+ for (i = 0; i < phytium_dp->source_max_lane_count; i++) {
+ data |= (PLL_EN << (i * PLL_EN_SHIFT));
+ mask |= (((1<<PLL_EN_SHIFT) - 1) << (i * PLL_EN_SHIFT));
+ }
+ data &= ~mask;
+ phytium_phy_writel(phytium_dp, PE220X_PHY_PLL_EN(port), data);
+
+ /* pma pll disable */
+ data = CONTROL_ENABLE & (~CONTROL_ENABLE_MASK);
+ phytium_phy_writel(phytium_dp, PE220X_PHY_PMA_CONTROL(port), data);
+
+ /* read pma pll disable state */
+ mdelay(2);
+ phytium_phy_readl(phytium_dp, PE220X_PHY_PMA_CONTROL2(port));
+
+ /* config link rate */
+ switch (link_rate) {
+ case 810000:
+ tmp = PLL_LINK_RATE_810000;
+ tmp1 = HSCLK_LINK_RATE_810000;
+ index = 3;
+ break;
+ case 540000:
+ tmp = PLL_LINK_RATE_540000;
+ tmp1 = HSCLK_LINK_RATE_540000;
+ index = 2;
+ break;
+ case 270000:
+ tmp = PLL_LINK_RATE_270000;
+ tmp1 = HSCLK_LINK_RATE_270000;
+ index = 1;
+ break;
+ case 162000:
+ tmp = PLL_LINK_RATE_162000;
+ tmp1 = HSCLK_LINK_RATE_162000;
+ index = 0;
+ break;
+ default:
+ DRM_ERROR("phytium dp rate(%d) not support\n", link_rate);
+ tmp = PLL_LINK_RATE_162000;
+ tmp1 = HSCLK_LINK_RATE_162000;
+ index = 0;
+ break;
+ }
+
+ /* config analog pll for link0 */
+ phytium_phy_writel(phytium_dp, PE220X_PHY_PLL0_CLK_SEL(port), tmp);
+ phytium_phy_writel(phytium_dp, PE220X_PHY_HSCLK0_SEL(port), HSCLK_LINK_0);
+ phytium_phy_writel(phytium_dp, PE220X_PHY_HSCLK0_DIV(port), tmp1);
+
+ /* config digital pll for link0 */
+ phytium_phy_writel(phytium_dp, PE220X_PHY_PLLDRC0_CTRL(port), PLLDRC_LINK0);
+
+ /* common for all rate */
+ phytium_phy_writel(phytium_dp, PE220X_PHY_PLL0_DSM_M0(port), PLL0_DSM_M0);
+ phytium_phy_writel(phytium_dp, PE220X_PHY_PLL0_VCOCAL_START(port),
+ PLL0_VCOCAL_START);
+ phytium_phy_writel(phytium_dp, PE220X_PHY_PLL0_VCOCAL_CTRL(port),
+ PLL0_VCOCAL_CTRL);
+
+ /* different for all rate */
+ phytium_phy_writel(phytium_dp, PE220X_PHY_PLL0_CP_PADJ(port),
+ vco_val[0][index]);
+ phytium_phy_writel(phytium_dp, PE220X_PHY_PLL0_CP_IADJ(port),
+ vco_val[1][index]);
+ phytium_phy_writel(phytium_dp, PE220X_PHY_PLL0_CP_FILT_PADJ(port),
+ vco_val[2][index]);
+ phytium_phy_writel(phytium_dp, PE220X_PHY_PLL0_INTDIV(port),
+ vco_val[3][index]);
+ phytium_phy_writel(phytium_dp, PE220X_PHY_PLL0_FRACDIVL(port),
+ vco_val[4][index]);
+ phytium_phy_writel(phytium_dp, PE220X_PHY_PLL0_FRACDIVH(port),
+ vco_val[5][index]);
+ phytium_phy_writel(phytium_dp, PE220X_PHY_PLL0_HIGH_THR(port),
+ vco_val[6][index]);
+ phytium_phy_writel(phytium_dp, PE220X_PHY_PLL0_PDIAG_CTRL(port),
+ vco_val[7][index]);
+ phytium_phy_writel(phytium_dp, PE220X_PHY_PLL0_VCOCAL_PLLCNT_START(port),
+ vco_val[8][index]);
+ phytium_phy_writel(phytium_dp, PE220X_PHY_PLL0_LOCK_PEFCNT(port),
+ vco_val[9][index]);
+ phytium_phy_writel(phytium_dp, PE220X_PHY_PLL0_LOCK_PLLCNT_START(port),
+ vco_val[10][index]);
+ phytium_phy_writel(phytium_dp, PE220X_PHY_PLL0_LOCK_PLLCNT_THR(port),
+ vco_val[11][index]);
+
+ phytium_phy_writel(phytium_dp, PE220X_PHY_PLL0_TX_PSC_A0(port),
+ PLL0_TX_PSC_A0);
+ phytium_phy_writel(phytium_dp, PE220X_PHY_PLL0_TX_PSC_A2(port),
+ PLL0_TX_PSC_A2);
+ phytium_phy_writel(phytium_dp, PE220X_PHY_PLL0_TX_PSC_A3(port),
+ PLL0_TX_PSC_A3);
+ phytium_phy_writel(phytium_dp, PE220X_PHY_PLL0_RX_PSC_A0(port),
+ PLL0_RX_PSC_A0);
+ phytium_phy_writel(phytium_dp, PE220X_PHY_PLL0_RX_PSC_A2(port),
+ PLL0_RX_PSC_A2);
+ phytium_phy_writel(phytium_dp, PE220X_PHY_PLL0_RX_PSC_A3(port),
+ PLL0_RX_PSC_A3);
+ phytium_phy_writel(phytium_dp, PE220X_PHY_PLL0_RX_PSC_CAL(port),
+ PLL0_RX_PSC_CAL);
+
+ phytium_phy_writel(phytium_dp, PE220X_PHY_PLL0_XCVR_CTRL(port),
+ PLL0_XCVR_CTRL);
+ phytium_phy_writel(phytium_dp, PE220X_PHY_PLL0_RX_GCSM1_CTRL(port),
+ PLL0_RX_GCSM1_CTRL);
+ phytium_phy_writel(phytium_dp, PE220X_PHY_PLL0_RX_GCSM2_CTRL(port),
+ PLL0_RX_GCSM2_CTRL);
+ phytium_phy_writel(phytium_dp, PE220X_PHY_PLL0_RX_PERGCSM_CTRL(port),
+ PLL0_RX_PERGCSM_CTRL);
+
+ /* pma pll enable */
+ data = CONTROL_ENABLE;
+ phytium_phy_writel(phytium_dp, PE220X_PHY_PMA_CONTROL(port), data);
+
+ /* lane pll enable */
+ data = 0;
+ for (i = 0; i < phytium_dp->source_max_lane_count; i++)
+ data |= (PLL_EN << (i * PLL_EN_SHIFT));
+ phytium_phy_writel(phytium_dp, PE220X_PHY_PLL_EN(port), data);
+
+ /* set pma power active */
+ data = 0;
+ for (i = 0; i < phytium_dp->source_max_lane_count; i++)
+ data |= (A0_ACTIVE << (i * A0_ACTIVE_SHIFT));
+ phytium_phy_writel(phytium_dp, PE220X_PHY_PMA0_POWER(port), data);
+
+ mask = PLL0_LOCK_DONE;
+ do {
+ mdelay(1);
+ timeout--;
+ tmp = phytium_phy_readl(phytium_dp, PE220X_PHY_PMA_CONTROL2(port));
+ } while ((!(tmp & mask)) && timeout);
+
+ if (timeout == 0) {
+ DRM_ERROR("dp(%d) phy pll lock failed\n", port);
+ ret = -1;
+ }
+ udelay(1);
+
+ return ret;
+}
+
+static void pe220x_dp_hw_set_phy_lane_setting(struct phytium_dp_device *phytium_dp,
+ uint32_t link_rate, uint8_t train_set)
+{
+ int port = phytium_dp->port % 3;
+ int voltage_swing = 0;
+ int pre_emphasis = 0, link_rate_index = 0;
+
+ switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
+ case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
+ voltage_swing = 1;
+ break;
+ case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
+ voltage_swing = 2;
+ break;
+ case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
+ voltage_swing = 3;
+ break;
+ default:
+ voltage_swing = 0;
+ break;
+ }
+
+ switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
+ case DP_TRAIN_PRE_EMPH_LEVEL_1:
+ pre_emphasis = 1;
+ break;
+ case DP_TRAIN_PRE_EMPH_LEVEL_2:
+ pre_emphasis = 2;
+ break;
+ case DP_TRAIN_PRE_EMPH_LEVEL_3:
+ pre_emphasis = 3;
+ break;
+ default:
+ pre_emphasis = 0;
+ break;
+ }
+
+ switch (link_rate) {
+ case 810000:
+ link_rate_index = 3;
+ break;
+ case 540000:
+ link_rate_index = 2;
+ break;
+ case 270000:
+ link_rate_index = 1;
+ break;
+ case 162000:
+ link_rate_index = 0;
+ break;
+ default:
+ DRM_ERROR("phytium dp rate(%d) not support\n", link_rate);
+ link_rate_index = 2;
+ break;
+ }
+
+ phytium_phy_writel(phytium_dp, PE220X_PHY_PLL0_TX_DIAG_ACYA(port), LOCK);
+ phytium_phy_writel(phytium_dp, PE220X_PHY_PLL0_TX_TXCC_CTRL(port), TX_TXCC_CTRL);
+ phytium_phy_writel(phytium_dp, PE220X_PHY_PLL0_TX_DRV(port), TX_DRV);
+ phytium_phy_writel(phytium_dp, PE220X_PHY_PLL0_TX_MGNFS(port),
+ mgnfs_val[link_rate_index][voltage_swing][pre_emphasis]);
+ phytium_phy_writel(phytium_dp, PE220X_PHY_PLL0_TX_CPOST(port),
+ cpost_val[link_rate_index][voltage_swing][pre_emphasis]);
+ phytium_phy_writel(phytium_dp, PE220X_PHY_PLL0_TX_DIAG_ACYA(port), UNLOCK);
+}
+
+static int pe220x_dp_hw_init_phy(struct phytium_dp_device *phytium_dp)
+{
+ int port = phytium_dp->port;
+ int i = 0, data, tmp, mask;
+ int timeout = 500, ret = 0;
+
+ phytium_phy_writel(phytium_dp, PE220X_PHY_APB_RESET(port), APB_RESET);
+ phytium_phy_writel(phytium_dp, PE220X_PHY_PIPE_RESET(port), RESET);
+
+ /* config lane to dp mode */
+ data = 0;
+ for (i = 0; i < phytium_dp->source_max_lane_count; i++)
+ data |= (LANE_BIT << (i * LANE_BIT_SHIFT));
+ phytium_phy_writel(phytium_dp, PE220X_PHY_MODE(port), data);
+
+ /* pll clock enable */
+ data = 0;
+ for (i = 0; i < phytium_dp->source_max_lane_count; i++)
+ data |= (PLL_EN << (i * PLL_EN_SHIFT));
+ phytium_phy_writel(phytium_dp, PE220X_PHY_PLL_EN(port), data);
+
+ /* config input 20 bit */
+ data = 0;
+ for (i = 0; i < phytium_dp->source_max_lane_count; i++)
+ data |= (BIT_20 << (i * BIT_20_SHIFT));
+ phytium_phy_writel(phytium_dp, PE220X_PHY_PMA_WIDTH(port), data);
+
+ /* config lane active power state */
+ data = 0;
+ for (i = 0; i < phytium_dp->source_max_lane_count; i++)
+ data |= (A0_ACTIVE << (i * A0_ACTIVE_SHIFT));
+ phytium_phy_writel(phytium_dp, PE220X_PHY_PMA0_POWER(port), data);
+
+ /* link reset */
+ phytium_phy_writel(phytium_dp, PE220X_PHY_LINK_RESET(port), LINK_RESET);
+
+ phytium_phy_writel(phytium_dp, PE220X_PHY_SGMII_DPSEL_INIT(port), DP_SEL);
+
+ /* config single link */
+ phytium_phy_writel(phytium_dp, PE220X_PHY_PLL_CFG(port), SINGLE_LINK);
+
+ /* pipe reset */
+ phytium_phy_writel(phytium_dp, PE220X_PHY_PIPE_RESET(port), RESET_DEASSERT);
+
+ mask = PLL0_LOCK_DONE;
+ do {
+ mdelay(1);
+ timeout--;
+ tmp = phytium_phy_readl(phytium_dp, PE220X_PHY_PMA_CONTROL2(port));
+ } while ((!(tmp & mask)) && timeout);
+
+ if (timeout == 0) {
+ DRM_ERROR("reset dp(%d) phy failed\n", port);
+ ret = -1;
+ }
+ udelay(1);
+
+ return ret;
+}
+
+static void pe220x_dp_hw_poweron_panel(struct phytium_dp_device *phytium_dp)
+{
+ struct drm_device *dev = phytium_dp->dev;
+ struct phytium_display_private *priv = dev->dev_private;
+ int port = phytium_dp->port;
+ int ret = 0;
+
+ phytium_writel_reg(priv, FLAG_REQUEST | CMD_BACKLIGHT | PANEL_POWER_ENABLE,
+ 0, PE220X_DC_CMD_REGISTER(port));
+ ret = phytium_wait_cmd_done(priv, PE220X_DC_CMD_REGISTER(port),
+ FLAG_REQUEST, FLAG_REPLY);
+ if (ret < 0)
+ DRM_ERROR("%s: failed to poweron panel\n", __func__);
+}
+
+static void pe220x_dp_hw_poweroff_panel(struct phytium_dp_device *phytium_dp)
+{
+ struct drm_device *dev = phytium_dp->dev;
+ struct phytium_display_private *priv = dev->dev_private;
+ int port = phytium_dp->port;
+ int ret = 0;
+
+ phytium_writel_reg(priv, FLAG_REQUEST | CMD_BACKLIGHT | PANEL_POWER_DISABLE,
+ 0, PE220X_DC_CMD_REGISTER(port));
+ ret = phytium_wait_cmd_done(priv, PE220X_DC_CMD_REGISTER(port),
+ FLAG_REQUEST, FLAG_REPLY);
+ if (ret < 0)
+ DRM_ERROR("%s: failed to poweroff panel\n", __func__);
+}
+
+static void pe220x_dp_hw_enable_backlight(struct phytium_dp_device *phytium_dp)
+{
+ struct drm_device *dev = phytium_dp->dev;
+ struct phytium_display_private *priv = dev->dev_private;
+ int port = phytium_dp->port, ret = 0;
+
+ phytium_writel_reg(priv, FLAG_REQUEST | CMD_BACKLIGHT | BACKLIGHT_ENABLE,
+ 0, PE220X_DC_CMD_REGISTER(port));
+ ret = phytium_wait_cmd_done(priv, PE220X_DC_CMD_REGISTER(port),
+ FLAG_REQUEST, FLAG_REPLY);
+ if (ret < 0)
+ DRM_ERROR("%s: failed to enable backlight\n", __func__);
+}
+
+static void pe220x_dp_hw_disable_backlight(struct phytium_dp_device *phytium_dp)
+{
+ struct drm_device *dev = phytium_dp->dev;
+ struct phytium_display_private *priv = dev->dev_private;
+ int port = phytium_dp->port;
+ int ret = 0;
+
+ phytium_writel_reg(priv, FLAG_REQUEST | CMD_BACKLIGHT | BACKLIGHT_DISABLE,
+ 0, PE220X_DC_CMD_REGISTER(port));
+ ret = phytium_wait_cmd_done(priv, PE220X_DC_CMD_REGISTER(port),
+ FLAG_REQUEST, FLAG_REPLY);
+ if (ret < 0)
+ DRM_ERROR("%s: failed to disable backlight\n", __func__);
+}
+
+static uint32_t pe220x_dp_hw_get_backlight(struct phytium_dp_device *phytium_dp)
+{
+ struct drm_device *dev = phytium_dp->dev;
+ struct phytium_display_private *priv = dev->dev_private;
+ int config;
+ uint32_t group_offset = priv->address_transform_base;
+
+ config = phytium_readl_reg(priv, group_offset, PE220X_DC_ADDRESS_TRANSFORM_BACKLIGHT_VALUE);
+ return ((config >> BACKLIGHT_VALUE_SHIFT) & BACKLIGHT_VALUE_MASK);
+}
+
+static int pe220x_dp_hw_set_backlight(struct phytium_dp_device *phytium_dp, uint32_t level)
+{
+ struct drm_device *dev = phytium_dp->dev;
+ struct phytium_display_private *priv = dev->dev_private;
+ int port = phytium_dp->port;
+ int config = 0;
+ int ret = 0;
+
+ if (level > PE220X_DP_BACKLIGHT_MAX) {
+ ret = -EINVAL;
+ goto out;
+ }
+
+ config = FLAG_REQUEST | CMD_BACKLIGHT | ((level & BACKLIGHT_MASK) << BACKLIGHT_SHIFT);
+ phytium_writel_reg(priv, config, 0, PE220X_DC_CMD_REGISTER(port));
+ ret = phytium_wait_cmd_done(priv, PE220X_DC_CMD_REGISTER(port),
+ FLAG_REQUEST, FLAG_REPLY);
+ if (ret < 0)
+ DRM_ERROR("%s: failed to set backlight\n", __func__);
+out:
+ return ret;
+}
+
+bool pe220x_dp_hw_spread_is_enable(struct phytium_dp_device *phytium_dp)
+{
+ return false;
+}
+
+int pe220x_dp_hw_reset(struct phytium_dp_device *phytium_dp)
+{
+ struct drm_device *dev = phytium_dp->dev;
+ struct phytium_display_private *priv = dev->dev_private;
+ int port = phytium_dp->port;
+ uint32_t group_offset = priv->dp_reg_base[port];
+
+ phytium_writel_reg(priv, DP_RESET, group_offset, PE220X_DP_CONTROLLER_RESET);
+ udelay(500);
+ phytium_writel_reg(priv, AUX_CLK_DIVIDER_100, group_offset, PHYTIUM_DP_AUX_CLK_DIVIDER);
+ phytium_writel_reg(priv, SUPPORT_EDP_1_4, group_offset, PHYTIUM_EDP_CRC_ENABLE);
+
+ return 0;
+}
+
+uint8_t pe220x_dp_hw_get_source_lane_count(struct phytium_dp_device *phytium_dp)
+{
+ return pe220x_dp_source_lane_count[phytium_dp->port];
+}
+
+static struct phytium_dp_func pe220x_dp_funcs = {
+ .dp_hw_get_source_lane_count = pe220x_dp_hw_get_source_lane_count,
+ .dp_hw_reset = pe220x_dp_hw_reset,
+ .dp_hw_spread_is_enable = pe220x_dp_hw_spread_is_enable,
+ .dp_hw_set_backlight = pe220x_dp_hw_set_backlight,
+ .dp_hw_get_backlight = pe220x_dp_hw_get_backlight,
+ .dp_hw_disable_backlight = pe220x_dp_hw_disable_backlight,
+ .dp_hw_enable_backlight = pe220x_dp_hw_enable_backlight,
+ .dp_hw_poweroff_panel = pe220x_dp_hw_poweroff_panel,
+ .dp_hw_poweron_panel = pe220x_dp_hw_poweron_panel,
+ .dp_hw_init_phy = pe220x_dp_hw_init_phy,
+ .dp_hw_set_phy_lane_setting = pe220x_dp_hw_set_phy_lane_setting,
+ .dp_hw_set_phy_lane_and_rate = pe220x_dp_hw_set_phy_lane_and_rate,
+};
+
+void pe220x_dp_func_register(struct phytium_dp_device *phytium_dp)
+{
+ phytium_dp->funcs = &pe220x_dp_funcs;
+}
diff --git a/drivers/gpu/drm/phytium/pe220x_dp.h b/drivers/gpu/drm/phytium/pe220x_dp.h
new file mode 100644
index 000000000000..6b763d996631
--- /dev/null
+++ b/drivers/gpu/drm/phytium/pe220x_dp.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Phytium display port DRM driver
+ *
+ * Copyright (C) 2021-2023, Phytium Technology Co., Ltd.
+ */
+