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Introduction to OpenTitan

OpenTitan is an open source silicon Root of Trust (RoT) project. OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. OpenTitan is administered by lowRISC CIC as a collaborative [project]({{< relref "doc/project" >}}) to produce high quality, open IP for instantiation as a full-featured product. This repository exists to enable collaboration across partners participating in the OpenTitan project.

To get started using or contributing to the OpenTitan codebase, see the [list of user guides]({{< relref "doc/ug" >}}). For details on coding styles or how to use our project-specific tooling, see the [reference manuals]({{< relref "doc/rm" >}}). [This page]({{< relref "hw" >}}) contains technical documentation on the SoC, the Ibex processor core, and the individual IP blocks. For questions about how the project is organized, see the [project]({{< relref "doc/project" >}}) landing spot for more information.

Repository Structure

The underlying repo is set up as a monolithic repository to contain RTL, helper scripts, technical documentation, and other software necessary to produce our hardware designs.

Unless otherwise noted, everything in the repository is covered by the Apache License, Version 2.0. See the LICENSE file and repository README for more information on licensing and see the user guides below for more information on development methodology.

Documentation Sections

  • [Project]({{< relref "doc/project" >}})
    • How the OpenTitan project is organized
    • Progress tracking
  • [User Guides]({{< relref "doc/ug" >}})
    • How to get started with the repo
    • How to emulate on an FPGA
    • How hardware design is done in OpenTitan
    • How verification is done in OpenTitan
  • [Reference Manuals]({{< relref "doc/rm" >}})
    • Defining comportable IP peripherals
    • Coding style guides for Verilog, Python, Hjson, C/C++ and Markdown
    • OpenTitan tools
  • [Hardware Specifications]({{< relref "hw" >}})
    • Top-level SoC
    • Ibex processor core
    • Comportable IP blocks
  • [Security Docs]({{< relref "doc/security" >}})
    • Overview
    • Use cases
    • Logical security documents
  • [Tools]({{< relref "util" >}})
    • READMEs of OpenTitan tools