Highlights
- Pro
-
fusesoc Public
Package manager and build abstraction tool for FPGA/ASIC development
-
edalize Public
An abstraction library for interfacing EDA tools
-
-
axi Public
Forked from pulp-platform/axiAXI4 and AXI4-Lite synthesizable modules and verification infrastructure
-
-
serv Public
SERV - The SErial RISC-V CPU
-
gpio Public
Forked from pulp-platform/gpioParametric GPIO Peripheral
SystemVerilog Other UpdatedJan 29, 2025 -
-
riscv-formal Public
Forked from YosysHQ/riscv-formalRISC-V Formal Verification Framework
-
subservient Public
Small SERV-based SoC primarily for OpenMPW tapeout
-
-
-
-
opentitan Public
Forked from lowRISC/opentitanOpenTitan: Open source silicon root of trust
-
common_cells Public
Forked from pulp-platform/common_cellsCommon SystemVerilog components
-
-
tt08-vga-drop Public
Forked from rejunity/tt08-vga-drop"The Drop" ASIC 640x480 60Hz audio visual demo
-
Cores-VeeR-EH1 Public
Forked from chipsalliance/Cores-VeeR-EH1SweRV EH1 core
-
aes Public
Forked from secworks/aesVerilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.
-
-
-
cocotb Public
Forked from cocotb/cocotbcocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
Python BSD 3-Clause "New" or "Revised" License UpdatedMay 19, 2024 -
-
prince Public
Forked from secworks/princeThe Prince lightweight block cipher in Verilog.
Verilog BSD 2-Clause "Simplified" License UpdatedJan 10, 2024 -
-
subservient_gfmpw1 Public template
Forked from efabless/caravel_user_projecthttps://caravel-user-project.readthedocs.io
Verilog Apache License 2.0 UpdatedOct 28, 2023 -
riscv-opcodes Public
Forked from riscv/riscv-opcodesRISC-V Opcodes
-
keball Public
Regardless if you are 13 years old or retired, you might want to run keball
C++ UpdatedJul 14, 2023 -
hossein1387.github.io Public
Forked from hossein1387/hossein1387.github.ioPersonal Website
HTML UpdatedJun 12, 2023 -
basejump_stl Public
Forked from bespoke-silicon-group/basejump_stlBaseJump STL: A Standard Template Library for SystemVerilog
Verilog Other UpdatedMar 26, 2023