diff --git a/test/conformance/usm/helpers.h b/test/conformance/usm/helpers.h new file mode 100644 index 0000000000..e8176c13b1 --- /dev/null +++ b/test/conformance/usm/helpers.h @@ -0,0 +1,42 @@ +// Copyright (C) 2024 Intel Corporation +// Part of the Unified-Runtime Project, under the Apache License v2.0 with LLVM Exceptions. +// See LICENSE.TXT +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception + +#ifndef UUR_USM_HELPERS_H_INCLUDED +#define UUR_USM_HELPERS_H_INCLUDED + +#include + +namespace uur { + +using USMDeviceAllocParams = std::tuple; + +template +inline std::string printUSMAllocTestString( + const testing::TestParamInfo &info) { + // ParamType will be std::tuple + const auto device_handle = std::get<0>(info.param); + const auto platform_device_name = + uur::GetPlatformAndDeviceName(device_handle); + const auto usmDeviceAllocParams = std::get<1>(info.param); + const auto BoolParam = std::get<0>(usmDeviceAllocParams); + + std::stringstream ss; + ss << BoolParam.name << (BoolParam.value ? "Enabled" : "Disabled"); + + const auto alignment = std::get<1>(usmDeviceAllocParams); + const auto size = std::get<2>(usmDeviceAllocParams); + if (alignment && size > 0) { + ss << "_"; + ss << std::get<1>(usmDeviceAllocParams); + ss << "_"; + ss << std::get<2>(usmDeviceAllocParams); + } + + return platform_device_name + "__" + ss.str(); +} + +} // namespace uur + +#endif // UUR_ENQUEUE_RECT_HELPERS_H_INCLUDED diff --git a/test/conformance/usm/urUSMDeviceAlloc.cpp b/test/conformance/usm/urUSMDeviceAlloc.cpp index 1d66a91148..cd48e73dbe 100644 --- a/test/conformance/usm/urUSMDeviceAlloc.cpp +++ b/test/conformance/usm/urUSMDeviceAlloc.cpp @@ -2,39 +2,14 @@ // Part of the Unified-Runtime Project, under the Apache License v2.0 with LLVM Exceptions. // See LICENSE.TXT // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +#include "helpers.h" #include -using USMDeviceAllocParams = std::tuple; - -template -inline std::string printUSMDeviceAllocTestString( - const testing::TestParamInfo &info) { - // ParamType will be std::tuple - const auto device_handle = std::get<0>(info.param); - const auto platform_device_name = - uur::GetPlatformAndDeviceName(device_handle); - const auto usmDeviceAllocParams = std::get<1>(info.param); - const auto BoolParam = std::get<0>(usmDeviceAllocParams); - - std::stringstream ss; - ss << BoolParam.name << (BoolParam.value ? "Enabled" : "Disabled"); - - const auto alignment = std::get<1>(usmDeviceAllocParams); - const auto size = std::get<2>(usmDeviceAllocParams); - if (alignment && size > 0) { - ss << "_"; - ss << std::get<1>(usmDeviceAllocParams); - ss << "_"; - ss << std::get<2>(usmDeviceAllocParams); - } - - return platform_device_name + "__" + ss.str(); -} - -struct urUSMDeviceAllocTest : uur::urQueueTestWithParam { +struct urUSMDeviceAllocTest + : uur::urQueueTestWithParam { void SetUp() override { UUR_RETURN_ON_FATAL_FAILURE( - uur::urQueueTestWithParam::SetUp()); + uur::urQueueTestWithParam::SetUp()); ur_device_usm_access_capability_flags_t deviceUSMSupport = 0; ASSERT_SUCCESS( uur::GetDeviceUSMDeviceSupport(device, deviceUSMSupport)); @@ -53,20 +28,22 @@ struct urUSMDeviceAllocTest : uur::urQueueTestWithParam { ASSERT_SUCCESS(urUSMPoolRelease(pool)); } UUR_RETURN_ON_FATAL_FAILURE( - uur::urQueueTestWithParam::TearDown()); + uur::urQueueTestWithParam::TearDown()); } ur_usm_pool_handle_t pool = nullptr; bool usePool = std::get<0>(getParam()).value; }; -// The 0 value parameters are not relevant for urUSMDeviceAllocTest tests, they are used below in urUSMDeviceAllocAlignmentTest +// The 0 value parameters are not relevant for urUSMDeviceAllocTest tests, they +// are used below in urUSMDeviceAllocAlignmentTest for allocation size and +// alignment values UUR_TEST_SUITE_P( urUSMDeviceAllocTest, testing::Combine( testing::ValuesIn(uur::BoolTestParam::makeBoolParam("UsePool")), testing::Values(0), testing::Values(0)), - printUSMDeviceAllocTestString); + uur::printUSMAllocTestString); TEST_P(urUSMDeviceAllocTest, Success) { void *ptr = nullptr; @@ -155,7 +132,7 @@ UUR_TEST_SUITE_P( testing::Combine( testing::ValuesIn(uur::BoolTestParam::makeBoolParam("UsePool")), testing::Values(4, 8, 16, 32, 64), testing::Values(8, 512, 2048)), - printUSMDeviceAllocTestString); + uur::printUSMAllocTestString); TEST_P(urUSMDeviceAllocAlignmentTest, SuccessAlignedAllocations) { uint32_t alignment = std::get<1>(getParam()); @@ -168,6 +145,7 @@ TEST_P(urUSMDeviceAllocAlignmentTest, SuccessAlignedAllocations) { ur_usm_desc_t usm_desc{UR_STRUCTURE_TYPE_USM_DESC, &usm_device_desc, /* mem advice flags */ UR_USM_ADVICE_FLAG_DEFAULT, alignment}; + void *ptr = nullptr; ASSERT_SUCCESS(urUSMDeviceAlloc(context, device, &usm_desc, pool, allocation_size, &ptr)); diff --git a/test/conformance/usm/urUSMHostAlloc.cpp b/test/conformance/usm/urUSMHostAlloc.cpp index 3cf8833783..ce11ddf3c1 100644 --- a/test/conformance/usm/urUSMHostAlloc.cpp +++ b/test/conformance/usm/urUSMHostAlloc.cpp @@ -3,19 +3,22 @@ // See LICENSE.TXT // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +#include "helpers.h" #include #include -struct urUSMHostAllocTest : uur::urQueueTestWithParam { +struct urUSMHostAllocTest + : uur::urQueueTestWithParam { void SetUp() override { UUR_RETURN_ON_FATAL_FAILURE( - uur::urQueueTestWithParam::SetUp()); + uur::urQueueTestWithParam::SetUp()); ur_device_usm_access_capability_flags_t hostUSMSupport = 0; ASSERT_SUCCESS(uur::GetDeviceUSMHostSupport(device, hostUSMSupport)); if (!hostUSMSupport) { GTEST_SKIP() << "Device USM is not supported."; } - if (getParam().value) { + + if (usePool) { ur_usm_pool_desc_t pool_desc = {}; ASSERT_SUCCESS(urUSMPoolCreate(context, &pool_desc, &pool)); } @@ -26,16 +29,22 @@ struct urUSMHostAllocTest : uur::urQueueTestWithParam { ASSERT_SUCCESS(urUSMPoolRelease(pool)); } UUR_RETURN_ON_FATAL_FAILURE( - uur::urQueueTestWithParam::TearDown()); + uur::urQueueTestWithParam::TearDown()); } ur_usm_pool_handle_t pool = nullptr; + bool usePool = std::get<0>(getParam()).value; }; +// The 0 value parameters are not relevant for urUSMHostAllocTest tests, they +// are used below in urUSMHostAllocAlignmentTest for allocation size and +// alignment values UUR_TEST_SUITE_P( urUSMHostAllocTest, - testing::ValuesIn(uur::BoolTestParam::makeBoolParam("UsePool")), - uur::deviceTestWithParamPrinter); + testing::Combine( + testing::ValuesIn(uur::BoolTestParam::makeBoolParam("UsePool")), + testing::Values(0), testing::Values(0)), + uur::printUSMAllocTestString); TEST_P(urUSMHostAllocTest, Success) { ur_device_usm_access_capability_flags_t hostUSMSupport = 0; @@ -77,7 +86,6 @@ TEST_P(urUSMHostAllocTest, Success) { } TEST_P(urUSMHostAllocTest, SuccessWithDescriptors) { - ur_usm_host_desc_t usm_host_desc{UR_STRUCTURE_TYPE_USM_HOST_DESC, nullptr, /* host flags */ 0}; @@ -88,6 +96,7 @@ TEST_P(urUSMHostAllocTest, SuccessWithDescriptors) { size_t allocation_size = sizeof(int); ASSERT_SUCCESS( urUSMHostAlloc(context, &usm_desc, pool, allocation_size, &ptr)); + ASSERT_NE(ptr, nullptr); ur_event_handle_t event = nullptr; uint8_t pattern = 0; @@ -125,3 +134,38 @@ TEST_P(urUSMHostAllocTest, InvalidValueAlignPowerOfTwo) { ASSERT_EQ_RESULT(UR_RESULT_ERROR_INVALID_VALUE, urUSMHostAlloc(context, &desc, pool, sizeof(int), &ptr)); } + +using urUSMHostAllocAlignmentTest = urUSMHostAllocTest; + +UUR_TEST_SUITE_P( + urUSMHostAllocAlignmentTest, + testing::Combine( + testing::ValuesIn(uur::BoolTestParam::makeBoolParam("UsePool")), + testing::Values(4, 8, 16, 32, 64), testing::Values(8, 512, 2048)), + uur::printUSMAllocTestString); + +TEST_P(urUSMHostAllocAlignmentTest, SuccessAlignedAllocations) { + uint32_t alignment = std::get<1>(getParam()); + size_t allocation_size = std::get<2>(getParam()); + + ur_usm_host_desc_t usm_host_desc{UR_STRUCTURE_TYPE_USM_HOST_DESC, nullptr, + /* host flags */ 0}; + + ur_usm_desc_t usm_desc{UR_STRUCTURE_TYPE_USM_DESC, &usm_host_desc, + /* mem advice flags */ UR_USM_ADVICE_FLAG_DEFAULT, + alignment}; + + void *ptr = nullptr; + ASSERT_SUCCESS( + urUSMHostAlloc(context, &usm_desc, pool, allocation_size, &ptr)); + ASSERT_NE(ptr, nullptr); + + ur_event_handle_t event = nullptr; + uint8_t pattern = 0; + ASSERT_SUCCESS(urEnqueueUSMFill(queue, ptr, sizeof(pattern), &pattern, + allocation_size, 0, nullptr, &event)); + ASSERT_SUCCESS(urEventWait(1, &event)); + + ASSERT_SUCCESS(urUSMFree(context, ptr)); + EXPECT_SUCCESS(urEventRelease(event)); +} diff --git a/test/conformance/usm/urUSMSharedAlloc.cpp b/test/conformance/usm/urUSMSharedAlloc.cpp index e400cdc7d8..e50bd8cfe7 100644 --- a/test/conformance/usm/urUSMSharedAlloc.cpp +++ b/test/conformance/usm/urUSMSharedAlloc.cpp @@ -3,12 +3,14 @@ // See LICENSE.TXT // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +#include "helpers.h" #include -struct urUSMSharedAllocTest : uur::urQueueTestWithParam { +struct urUSMSharedAllocTest + : uur::urQueueTestWithParam { void SetUp() override { UUR_RETURN_ON_FATAL_FAILURE( - uur::urQueueTestWithParam::SetUp()); + uur::urQueueTestWithParam::SetUp()); ur_device_usm_access_capability_flags_t shared_usm_cross = 0; ur_device_usm_access_capability_flags_t shared_usm_single = 0; @@ -21,7 +23,7 @@ struct urUSMSharedAllocTest : uur::urQueueTestWithParam { GTEST_SKIP() << "Shared USM is not supported by the device."; } - if (getParam().value) { + if (usePool) { ur_usm_pool_desc_t pool_desc = {}; ASSERT_SUCCESS(urUSMPoolCreate(context, &pool_desc, &pool)); } @@ -32,22 +34,29 @@ struct urUSMSharedAllocTest : uur::urQueueTestWithParam { ASSERT_SUCCESS(urUSMPoolRelease(pool)); } UUR_RETURN_ON_FATAL_FAILURE( - uur::urQueueTestWithParam::TearDown()); + uur::urQueueTestWithParam::TearDown()); } ur_usm_pool_handle_t pool = nullptr; + bool usePool = std::get<0>(getParam()).value; }; +// The 0 value parameters are not relevant for urUSMSharedAllocTest tests, they +// are used below in urUSMSharedAllocAlignmentTest for allocation size and +// alignment values UUR_TEST_SUITE_P( urUSMSharedAllocTest, - testing::ValuesIn(uur::BoolTestParam::makeBoolParam("UsePool")), - uur::deviceTestWithParamPrinter); + testing::Combine( + testing::ValuesIn(uur::BoolTestParam::makeBoolParam("UsePool")), + testing::Values(0), testing::Values(0)), + uur::printUSMAllocTestString); TEST_P(urUSMSharedAllocTest, Success) { void *ptr = nullptr; size_t allocation_size = sizeof(int); ASSERT_SUCCESS(urUSMSharedAlloc(context, device, nullptr, pool, allocation_size, &ptr)); + ASSERT_NE(ptr, nullptr); ur_event_handle_t event = nullptr; uint8_t pattern = 0; @@ -60,7 +69,6 @@ TEST_P(urUSMSharedAllocTest, Success) { } TEST_P(urUSMSharedAllocTest, SuccessWithDescriptors) { - ur_usm_device_desc_t usm_device_desc{UR_STRUCTURE_TYPE_USM_DEVICE_DESC, nullptr, /* device flags */ 0}; @@ -76,6 +84,7 @@ TEST_P(urUSMSharedAllocTest, SuccessWithDescriptors) { size_t allocation_size = sizeof(int); ASSERT_SUCCESS(urUSMSharedAlloc(context, device, &usm_desc, pool, allocation_size, &ptr)); + ASSERT_NE(ptr, nullptr); ur_event_handle_t event = nullptr; uint8_t pattern = 0; @@ -97,6 +106,7 @@ TEST_P(urUSMSharedAllocTest, SuccessWithMultipleAdvices) { size_t allocation_size = sizeof(int); ASSERT_SUCCESS(urUSMSharedAlloc(context, device, &usm_desc, pool, allocation_size, &ptr)); + ASSERT_NE(ptr, nullptr); ur_event_handle_t event = nullptr; uint8_t pattern = 0; @@ -144,3 +154,43 @@ TEST_P(urUSMSharedAllocTest, InvalidValueAlignPowerOfTwo) { UR_RESULT_ERROR_INVALID_VALUE, urUSMSharedAlloc(context, device, &desc, pool, sizeof(int), &ptr)); } + +using urUSMSharedAllocAlignmentTest = urUSMSharedAllocTest; + +UUR_TEST_SUITE_P( + urUSMSharedAllocAlignmentTest, + testing::Combine( + testing::ValuesIn(uur::BoolTestParam::makeBoolParam("UsePool")), + testing::Values(4, 8, 16, 32, 64), testing::Values(8, 512, 2048)), + uur::printUSMAllocTestString); + +TEST_P(urUSMSharedAllocAlignmentTest, SuccessAlignedAllocations) { + uint32_t alignment = std::get<1>(getParam()); + size_t allocation_size = std::get<2>(getParam()); + + ur_usm_device_desc_t usm_device_desc{UR_STRUCTURE_TYPE_USM_DEVICE_DESC, + nullptr, + /* device flags */ 0}; + + ur_usm_host_desc_t usm_host_desc{UR_STRUCTURE_TYPE_USM_HOST_DESC, + &usm_device_desc, + /* host flags */ 0}; + + ur_usm_desc_t usm_desc{UR_STRUCTURE_TYPE_USM_DESC, &usm_host_desc, + /* mem advice flags */ UR_USM_ADVICE_FLAG_DEFAULT, + alignment}; + + void *ptr = nullptr; + ASSERT_SUCCESS(urUSMSharedAlloc(context, device, &usm_desc, pool, + allocation_size, &ptr)); + ASSERT_NE(ptr, nullptr); + + ur_event_handle_t event = nullptr; + uint8_t pattern = 0; + ASSERT_SUCCESS(urEnqueueUSMFill(queue, ptr, sizeof(pattern), &pattern, + allocation_size, 0, nullptr, &event)); + ASSERT_SUCCESS(urEventWait(1, &event)); + + ASSERT_SUCCESS(urUSMFree(context, ptr)); + EXPECT_SUCCESS(urEventRelease(event)); +} diff --git a/test/conformance/usm/usm_adapter_hip.match b/test/conformance/usm/usm_adapter_hip.match index 0e91676d80..43b9a98077 100644 --- a/test/conformance/usm/usm_adapter_hip.match +++ b/test/conformance/usm/usm_adapter_hip.match @@ -31,6 +31,21 @@ {{OPT}}urUSMHostAllocTest.InvalidUSMSize/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled {{OPT}}urUSMHostAllocTest.InvalidUSMSize/AMD_HIP_BACKEND___{{.*}}___UsePoolDisabled {{OPT}}urUSMHostAllocTest.InvalidValueAlignPowerOfTwo/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled +{{OPT}}urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_4_8 +{{OPT}}urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_4_512 +{{OPT}}urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_4_2048 +{{OPT}}urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_8_8 +{{OPT}}urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_8_512 +{{OPT}}urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_8_2048 +{{OPT}}urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_16_8 +{{OPT}}urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_16_512 +{{OPT}}urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_16_2048 +{{OPT}}urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_32_8 +{{OPT}}urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_32_512 +{{OPT}}urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_32_2048 +{{OPT}}urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_64_8 +{{OPT}}urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_64_512 +{{OPT}}urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_64_2048 {{OPT}}urUSMPoolCreateTest.Success/AMD_HIP_BACKEND___{{.*}}_ {{OPT}}urUSMPoolCreateTest.SuccessWithFlag/AMD_HIP_BACKEND___{{.*}}_ {{OPT}}urUSMPoolCreateTest.InvalidNullHandleContext/AMD_HIP_BACKEND___{{.*}}_ @@ -58,3 +73,18 @@ {{OPT}}urUSMSharedAllocTest.InvalidUSMSize/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled {{OPT}}urUSMSharedAllocTest.InvalidUSMSize/AMD_HIP_BACKEND___{{.*}}___UsePoolDisabled {{OPT}}urUSMSharedAllocTest.InvalidValueAlignPowerOfTwo/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled +{{OPT}}urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_4_8 +{{OPT}}urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_4_512 +{{OPT}}urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_4_2048 +{{OPT}}urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_8_8 +{{OPT}}urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_8_512 +{{OPT}}urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_8_2048 +{{OPT}}urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_16_8 +{{OPT}}urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_16_512 +{{OPT}}urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_16_2048 +{{OPT}}urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_32_8 +{{OPT}}urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_32_512 +{{OPT}}urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_32_2048 +{{OPT}}urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_64_8 +{{OPT}}urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_64_512 +{{OPT}}urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/AMD_HIP_BACKEND___{{.*}}___UsePoolEnabled_64_2048 diff --git a/test/conformance/usm/usm_adapter_native_cpu.match b/test/conformance/usm/usm_adapter_native_cpu.match index ce088ef43d..97844eb179 100644 --- a/test/conformance/usm/usm_adapter_native_cpu.match +++ b/test/conformance/usm/usm_adapter_native_cpu.match @@ -66,6 +66,36 @@ urUSMHostAllocTest.InvalidUSMSize/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolEna urUSMHostAllocTest.InvalidUSMSize/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolDisabled urUSMHostAllocTest.InvalidValueAlignPowerOfTwo/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolEnabled urUSMHostAllocTest.InvalidValueAlignPowerOfTwo/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolDisabled +urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolEnabled_4_8 +urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolEnabled_4_512 +urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolEnabled_4_2048 +urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolEnabled_8_8 +urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolEnabled_8_512 +urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolEnabled_8_2048 +urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolEnabled_16_8 +urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolEnabled_16_512 +urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolEnabled_16_2048 +urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolEnabled_32_8 +urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolEnabled_32_512 +urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolEnabled_32_2048 +urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolEnabled_64_8 +urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolEnabled_64_512 +urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolEnabled_64_2048 +urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolDisabled_4_8 +urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolDisabled_4_512 +urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolDisabled_4_2048 +urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolDisabled_8_8 +urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolDisabled_8_512 +urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolDisabled_8_2048 +urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolDisabled_16_8 +urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolDisabled_16_512 +urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolDisabled_16_2048 +urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolDisabled_32_8 +urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolDisabled_32_512 +urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolDisabled_32_2048 +urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolDisabled_64_8 +urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolDisabled_64_512 +urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolDisabled_64_2048 urUSMPoolCreateTest.Success/SYCL_NATIVE_CPU___SYCL_Native_CPU_ urUSMPoolCreateTest.SuccessWithFlag/SYCL_NATIVE_CPU___SYCL_Native_CPU_ urUSMPoolGetInfoTestWithInfoParam.Success/SYCL_NATIVE_CPU___SYCL_Native_CPU___UR_USM_POOL_INFO_CONTEXT @@ -96,3 +126,33 @@ urUSMSharedAllocTest.InvalidUSMSize/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolE urUSMSharedAllocTest.InvalidUSMSize/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolDisabled urUSMSharedAllocTest.InvalidValueAlignPowerOfTwo/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolEnabled urUSMSharedAllocTest.InvalidValueAlignPowerOfTwo/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolDisabled +urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolEnabled_4_8 +urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolEnabled_4_512 +urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolEnabled_4_2048 +urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolEnabled_8_8 +urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolEnabled_8_512 +urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolEnabled_8_2048 +urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolEnabled_16_8 +urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolEnabled_16_512 +urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolEnabled_16_2048 +urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolEnabled_32_8 +urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolEnabled_32_512 +urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolEnabled_32_2048 +urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolEnabled_64_8 +urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolEnabled_64_512 +urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolEnabled_64_2048 +urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolDisabled_4_8 +urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolDisabled_4_512 +urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolDisabled_4_2048 +urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolDisabled_8_8 +urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolDisabled_8_512 +urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolDisabled_8_2048 +urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolDisabled_16_8 +urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolDisabled_16_512 +urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolDisabled_16_2048 +urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolDisabled_32_8 +urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolDisabled_32_512 +urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolDisabled_32_2048 +urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolDisabled_64_8 +urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolDisabled_64_512 +urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/SYCL_NATIVE_CPU___SYCL_Native_CPU___UsePoolDisabled_64_2048 diff --git a/test/conformance/usm/usm_adapter_opencl.match b/test/conformance/usm/usm_adapter_opencl.match index e598869a3f..cb00bebc57 100644 --- a/test/conformance/usm/usm_adapter_opencl.match +++ b/test/conformance/usm/usm_adapter_opencl.match @@ -27,6 +27,21 @@ urUSMHostAllocTest.InvalidNullHandleContext/Intel_R__OpenCL___{{.*}}___UsePoolEn urUSMHostAllocTest.InvalidNullPtrMem/Intel_R__OpenCL___{{.*}}___UsePoolEnabled urUSMHostAllocTest.InvalidUSMSize/Intel_R__OpenCL___{{.*}}___UsePoolEnabled urUSMHostAllocTest.InvalidValueAlignPowerOfTwo/Intel_R__OpenCL___{{.*}}___UsePoolEnabled +urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/Intel_R__OpenCL___{{.*}}___UsePoolEnabled_4_8 +urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/Intel_R__OpenCL___{{.*}}___UsePoolEnabled_4_512 +urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/Intel_R__OpenCL___{{.*}}___UsePoolEnabled_4_2048 +urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/Intel_R__OpenCL___{{.*}}___UsePoolEnabled_8_8 +urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/Intel_R__OpenCL___{{.*}}___UsePoolEnabled_8_512 +urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/Intel_R__OpenCL___{{.*}}___UsePoolEnabled_8_2048 +urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/Intel_R__OpenCL___{{.*}}___UsePoolEnabled_16_8 +urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/Intel_R__OpenCL___{{.*}}___UsePoolEnabled_16_512 +urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/Intel_R__OpenCL___{{.*}}___UsePoolEnabled_16_2048 +urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/Intel_R__OpenCL___{{.*}}___UsePoolEnabled_32_8 +urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/Intel_R__OpenCL___{{.*}}___UsePoolEnabled_32_512 +urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/Intel_R__OpenCL___{{.*}}___UsePoolEnabled_32_2048 +urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/Intel_R__OpenCL___{{.*}}___UsePoolEnabled_64_8 +urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/Intel_R__OpenCL___{{.*}}___UsePoolEnabled_64_512 +urUSMHostAllocAlignmentTest.SuccessAlignedAllocations/Intel_R__OpenCL___{{.*}}___UsePoolEnabled_64_2048 urUSMPoolCreateTest.Success/Intel_R__OpenCL___{{.*}} urUSMPoolCreateTest.SuccessWithFlag/Intel_R__OpenCL___{{.*}} urUSMPoolCreateTest.InvalidNullHandleContext/Intel_R__OpenCL___{{.*}} @@ -53,3 +68,18 @@ urUSMSharedAllocTest.InvalidNullHandleDevice/Intel_R__OpenCL___{{.*}}___UsePoolE urUSMSharedAllocTest.InvalidNullPtrMem/Intel_R__OpenCL___{{.*}}___UsePoolEnabled urUSMSharedAllocTest.InvalidUSMSize/Intel_R__OpenCL___{{.*}}___UsePoolEnabled urUSMSharedAllocTest.InvalidValueAlignPowerOfTwo/Intel_R__OpenCL___{{.*}}___UsePoolEnabled +urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/Intel_R__OpenCL___{{.*}}___UsePoolEnabled_4_8 +urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/Intel_R__OpenCL___{{.*}}___UsePoolEnabled_4_512 +urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/Intel_R__OpenCL___{{.*}}___UsePoolEnabled_4_2048 +urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/Intel_R__OpenCL___{{.*}}___UsePoolEnabled_8_8 +urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/Intel_R__OpenCL___{{.*}}___UsePoolEnabled_8_512 +urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/Intel_R__OpenCL___{{.*}}___UsePoolEnabled_8_2048 +urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/Intel_R__OpenCL___{{.*}}___UsePoolEnabled_16_8 +urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/Intel_R__OpenCL___{{.*}}___UsePoolEnabled_16_512 +urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/Intel_R__OpenCL___{{.*}}___UsePoolEnabled_16_2048 +urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/Intel_R__OpenCL___{{.*}}___UsePoolEnabled_32_8 +urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/Intel_R__OpenCL___{{.*}}___UsePoolEnabled_32_512 +urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/Intel_R__OpenCL___{{.*}}___UsePoolEnabled_32_2048 +urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/Intel_R__OpenCL___{{.*}}___UsePoolEnabled_64_8 +urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/Intel_R__OpenCL___{{.*}}___UsePoolEnabled_64_512 +urUSMSharedAllocAlignmentTest.SuccessAlignedAllocations/Intel_R__OpenCL___{{.*}}___UsePoolEnabled_64_2048